2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <linux/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
72 #include <ttm/ttm_execbuf_util.h>
74 #include "radeon_family.h"
75 #include "radeon_mode.h"
76 #include "radeon_reg.h"
81 extern int radeon_no_wb;
82 extern int radeon_modeset;
83 extern int radeon_dynclks;
84 extern int radeon_r4xx_atom;
85 extern int radeon_agpmode;
86 extern int radeon_vram_limit;
87 extern int radeon_gart_size;
88 extern int radeon_benchmarking;
89 extern int radeon_testing;
90 extern int radeon_connector_table;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
95 extern int radeon_pcie_gen2;
96 extern int radeon_msi;
97 extern int radeon_lockup_timeout;
98 extern int radeon_fastfb;
99 extern int radeon_dpm;
102 * Copy from radeon_drv.h so we don't have to include both and have conflicting
105 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
106 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
107 /* RADEON_IB_POOL_SIZE must be a power of 2 */
108 #define RADEON_IB_POOL_SIZE 16
109 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
110 #define RADEONFB_CONN_LIMIT 4
111 #define RADEON_BIOS_NUM_SCRATCH 8
113 /* max number of rings */
114 #define RADEON_NUM_RINGS 6
116 /* fence seq are set to this number when signaled */
117 #define RADEON_FENCE_SIGNALED_SEQ 0LL
119 /* internal ring indices */
120 /* r1xx+ has gfx CP ring */
121 #define RADEON_RING_TYPE_GFX_INDEX 0
123 /* cayman has 2 compute CP rings */
124 #define CAYMAN_RING_TYPE_CP1_INDEX 1
125 #define CAYMAN_RING_TYPE_CP2_INDEX 2
127 /* R600+ has an async dma ring */
128 #define R600_RING_TYPE_DMA_INDEX 3
129 /* cayman add a second async dma ring */
130 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
133 #define R600_RING_TYPE_UVD_INDEX 5
135 /* hardcode those limit for now */
136 #define RADEON_VA_IB_OFFSET (1 << 20)
137 #define RADEON_VA_RESERVED_SIZE (8 << 20)
138 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
141 #define RADEON_RESET_GFX (1 << 0)
142 #define RADEON_RESET_COMPUTE (1 << 1)
143 #define RADEON_RESET_DMA (1 << 2)
144 #define RADEON_RESET_CP (1 << 3)
145 #define RADEON_RESET_GRBM (1 << 4)
146 #define RADEON_RESET_DMA1 (1 << 5)
147 #define RADEON_RESET_RLC (1 << 6)
148 #define RADEON_RESET_SEM (1 << 7)
149 #define RADEON_RESET_IH (1 << 8)
150 #define RADEON_RESET_VMC (1 << 9)
151 #define RADEON_RESET_MC (1 << 10)
152 #define RADEON_RESET_DISPLAY (1 << 11)
154 /* max cursor sizes (in pixels) */
155 #define CURSOR_WIDTH 64
156 #define CURSOR_HEIGHT 64
158 #define CIK_CURSOR_WIDTH 128
159 #define CIK_CURSOR_HEIGHT 128
162 * Errata workarounds.
164 enum radeon_pll_errata {
165 CHIP_ERRATA_R300_CG = 0x00000001,
166 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
167 CHIP_ERRATA_PLL_DELAY = 0x00000004
171 struct radeon_device;
177 bool radeon_get_bios(struct radeon_device *rdev);
182 struct radeon_dummy_page {
186 int radeon_dummy_page_init(struct radeon_device *rdev);
187 void radeon_dummy_page_fini(struct radeon_device *rdev);
193 struct radeon_clock {
194 struct radeon_pll p1pll;
195 struct radeon_pll p2pll;
196 struct radeon_pll dcpll;
197 struct radeon_pll spll;
198 struct radeon_pll mpll;
200 uint32_t default_mclk;
201 uint32_t default_sclk;
202 uint32_t default_dispclk;
203 uint32_t current_dispclk;
205 uint32_t max_pixel_clock;
211 int radeon_pm_init(struct radeon_device *rdev);
212 void radeon_pm_fini(struct radeon_device *rdev);
213 void radeon_pm_compute_clocks(struct radeon_device *rdev);
214 void radeon_pm_suspend(struct radeon_device *rdev);
215 void radeon_pm_resume(struct radeon_device *rdev);
216 void radeon_combios_get_power_modes(struct radeon_device *rdev);
217 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
218 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
222 struct atom_clock_dividers *dividers);
223 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
226 struct atom_mpll_param *mpll_param);
227 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
228 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
229 u16 voltage_level, u8 voltage_type,
230 u32 *gpio_value, u32 *gpio_mask);
231 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
232 u32 eng_clock, u32 mem_clock);
233 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
234 u8 voltage_type, u16 *voltage_step);
235 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
236 u16 voltage_id, u16 *voltage);
237 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
240 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
244 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
245 u8 voltage_type, u16 *min_voltage);
246 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
247 u8 voltage_type, u16 *max_voltage);
248 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
249 u8 voltage_type, u8 voltage_mode,
250 struct atom_voltage_table *voltage_table);
251 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
252 u8 voltage_type, u8 voltage_mode);
253 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
255 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
257 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
259 struct atom_mc_reg_table *reg_table);
260 int radeon_atom_get_memory_info(struct radeon_device *rdev,
261 u8 module_index, struct atom_memory_info *mem_info);
262 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
263 bool gddr5, u8 module_index,
264 struct atom_memory_clock_range_table *mclk_range_table);
265 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
266 u16 voltage_id, u16 *voltage);
267 void rs690_pm_info(struct radeon_device *rdev);
268 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
269 unsigned *bankh, unsigned *mtaspect,
270 unsigned *tile_split);
275 struct radeon_fence_driver {
276 uint32_t scratch_reg;
278 volatile uint32_t *cpu_addr;
279 /* sync_seq is protected by ring emission lock */
280 uint64_t sync_seq[RADEON_NUM_RINGS];
282 unsigned long last_activity;
286 struct radeon_fence {
287 struct radeon_device *rdev;
289 /* protected by radeon_fence.lock */
295 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
296 int radeon_fence_driver_init(struct radeon_device *rdev);
297 void radeon_fence_driver_fini(struct radeon_device *rdev);
298 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
299 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
300 void radeon_fence_process(struct radeon_device *rdev, int ring);
301 bool radeon_fence_signaled(struct radeon_fence *fence);
302 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
303 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
304 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
305 int radeon_fence_wait_any(struct radeon_device *rdev,
306 struct radeon_fence **fences,
308 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
309 void radeon_fence_unref(struct radeon_fence **fence);
310 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
311 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
312 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
313 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
314 struct radeon_fence *b)
324 BUG_ON(a->ring != b->ring);
326 if (a->seq > b->seq) {
333 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
334 struct radeon_fence *b)
344 BUG_ON(a->ring != b->ring);
346 return a->seq < b->seq;
352 struct radeon_surface_reg {
353 struct radeon_bo *bo;
356 #define RADEON_GEM_MAX_SURFACES 8
362 struct ttm_bo_global_ref bo_global_ref;
363 struct drm_global_reference mem_global_ref;
364 struct ttm_bo_device bdev;
365 bool mem_global_referenced;
369 /* bo virtual address in a specific vm */
370 struct radeon_bo_va {
371 /* protected by bo being reserved */
372 struct list_head bo_list;
379 /* protected by vm mutex */
380 struct list_head vm_list;
382 /* constant after initialization */
383 struct radeon_vm *vm;
384 struct radeon_bo *bo;
388 /* Protected by gem.mutex */
389 struct list_head list;
390 /* Protected by tbo.reserved */
392 struct ttm_placement placement;
393 struct ttm_buffer_object tbo;
394 struct ttm_bo_kmap_obj kmap;
400 /* list of all virtual address to which this bo
404 /* Constant after initialization */
405 struct radeon_device *rdev;
406 struct drm_gem_object gem_base;
408 struct ttm_bo_kmap_obj dma_buf_vmap;
411 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
413 struct radeon_bo_list {
414 struct ttm_validate_buffer tv;
415 struct radeon_bo *bo;
423 int radeon_gem_debugfs_init(struct radeon_device *rdev);
425 /* sub-allocation manager, it has to be protected by another lock.
426 * By conception this is an helper for other part of the driver
427 * like the indirect buffer or semaphore, which both have their
430 * Principe is simple, we keep a list of sub allocation in offset
431 * order (first entry has offset == 0, last entry has the highest
434 * When allocating new object we first check if there is room at
435 * the end total_size - (last_object_offset + last_object_size) >=
436 * alloc_size. If so we allocate new object there.
438 * When there is not enough room at the end, we start waiting for
439 * each sub object until we reach object_offset+object_size >=
440 * alloc_size, this object then become the sub object we return.
442 * Alignment can't be bigger than page size.
444 * Hole are not considered for allocation to keep things simple.
445 * Assumption is that there won't be hole (all object on same
448 struct radeon_sa_manager {
449 wait_queue_head_t wq;
450 struct radeon_bo *bo;
451 struct list_head *hole;
452 struct list_head flist[RADEON_NUM_RINGS];
453 struct list_head olist;
462 /* sub-allocation buffer */
463 struct radeon_sa_bo {
464 struct list_head olist;
465 struct list_head flist;
466 struct radeon_sa_manager *manager;
469 struct radeon_fence *fence;
477 struct list_head objects;
480 int radeon_gem_init(struct radeon_device *rdev);
481 void radeon_gem_fini(struct radeon_device *rdev);
482 int radeon_gem_object_create(struct radeon_device *rdev, int size,
483 int alignment, int initial_domain,
484 bool discardable, bool kernel,
485 struct drm_gem_object **obj);
487 int radeon_mode_dumb_create(struct drm_file *file_priv,
488 struct drm_device *dev,
489 struct drm_mode_create_dumb *args);
490 int radeon_mode_dumb_mmap(struct drm_file *filp,
491 struct drm_device *dev,
492 uint32_t handle, uint64_t *offset_p);
493 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
494 struct drm_device *dev,
500 /* everything here is constant */
501 struct radeon_semaphore {
502 struct radeon_sa_bo *sa_bo;
507 int radeon_semaphore_create(struct radeon_device *rdev,
508 struct radeon_semaphore **semaphore);
509 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
510 struct radeon_semaphore *semaphore);
511 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
512 struct radeon_semaphore *semaphore);
513 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
514 struct radeon_semaphore *semaphore,
515 int signaler, int waiter);
516 void radeon_semaphore_free(struct radeon_device *rdev,
517 struct radeon_semaphore **semaphore,
518 struct radeon_fence *fence);
521 * GART structures, functions & helpers
525 #define RADEON_GPU_PAGE_SIZE 4096
526 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
527 #define RADEON_GPU_PAGE_SHIFT 12
528 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
531 dma_addr_t table_addr;
532 struct radeon_bo *robj;
534 unsigned num_gpu_pages;
535 unsigned num_cpu_pages;
538 dma_addr_t *pages_addr;
542 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
543 void radeon_gart_table_ram_free(struct radeon_device *rdev);
544 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
545 void radeon_gart_table_vram_free(struct radeon_device *rdev);
546 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
547 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
548 int radeon_gart_init(struct radeon_device *rdev);
549 void radeon_gart_fini(struct radeon_device *rdev);
550 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
552 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
553 int pages, struct page **pagelist,
554 dma_addr_t *dma_addr);
555 void radeon_gart_restore(struct radeon_device *rdev);
559 * GPU MC structures, functions & helpers
562 resource_size_t aper_size;
563 resource_size_t aper_base;
564 resource_size_t agp_base;
565 /* for some chips with <= 32MB we need to lie
566 * about vram size near mc fb location */
568 u64 visible_vram_size;
578 bool igp_sideport_enabled;
583 bool radeon_combios_sideport_present(struct radeon_device *rdev);
584 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
587 * GPU scratch registers structures, functions & helpers
589 struct radeon_scratch {
596 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
597 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
600 * GPU doorbell structures, functions & helpers
602 struct radeon_doorbell {
606 resource_size_t base;
607 resource_size_t size;
611 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
612 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
618 struct radeon_unpin_work {
619 struct work_struct work;
620 struct radeon_device *rdev;
622 struct radeon_fence *fence;
623 struct drm_pending_vblank_event *event;
624 struct radeon_bo *old_rbo;
628 struct r500_irq_stat_regs {
633 struct r600_irq_stat_regs {
643 struct evergreen_irq_stat_regs {
664 struct cik_irq_stat_regs {
674 union radeon_irq_stat_regs {
675 struct r500_irq_stat_regs r500;
676 struct r600_irq_stat_regs r600;
677 struct evergreen_irq_stat_regs evergreen;
678 struct cik_irq_stat_regs cik;
681 #define RADEON_MAX_HPD_PINS 6
682 #define RADEON_MAX_CRTCS 6
683 #define RADEON_MAX_AFMT_BLOCKS 6
688 atomic_t ring_int[RADEON_NUM_RINGS];
689 bool crtc_vblank_int[RADEON_MAX_CRTCS];
690 atomic_t pflip[RADEON_MAX_CRTCS];
691 wait_queue_head_t vblank_queue;
692 bool hpd[RADEON_MAX_HPD_PINS];
693 bool afmt[RADEON_MAX_AFMT_BLOCKS];
694 union radeon_irq_stat_regs stat_regs;
698 int radeon_irq_kms_init(struct radeon_device *rdev);
699 void radeon_irq_kms_fini(struct radeon_device *rdev);
700 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
701 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
702 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
703 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
704 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
705 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
706 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
707 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
714 struct radeon_sa_bo *sa_bo;
719 struct radeon_fence *fence;
720 struct radeon_vm *vm;
722 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
723 struct radeon_semaphore *semaphore;
727 struct radeon_bo *ring_obj;
728 volatile uint32_t *ring;
732 unsigned rptr_save_reg;
733 u64 next_rptr_gpu_addr;
734 volatile u32 *next_rptr_cpu_addr;
739 unsigned ring_free_dw;
741 unsigned long last_activity;
751 u64 last_semaphore_signal_addr;
752 u64 last_semaphore_wait_addr;
757 struct radeon_bo *mqd_obj;
758 u32 doorbell_page_num;
764 struct radeon_bo *hpd_eop_obj;
765 u64 hpd_eop_gpu_addr;
775 /* maximum number of VMIDs */
776 #define RADEON_NUM_VM 16
778 /* defines number of bits in page table versus page directory,
779 * a page is 4KB so we have 12 bits offset, 9 bits in the page
780 * table and the remaining 19 bits are in the page directory */
781 #define RADEON_VM_BLOCK_SIZE 9
783 /* number of entries in page table */
784 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
787 struct list_head list;
791 /* contains the page directory */
792 struct radeon_sa_bo *page_directory;
793 uint64_t pd_gpu_addr;
795 /* array of page tables, one for each page directory entry */
796 struct radeon_sa_bo **page_tables;
799 /* last fence for cs using this vm */
800 struct radeon_fence *fence;
801 /* last flush or NULL if we still need to flush */
802 struct radeon_fence *last_flush;
805 struct radeon_vm_manager {
807 struct list_head lru_vm;
808 struct radeon_fence *active[RADEON_NUM_VM];
809 struct radeon_sa_manager sa_manager;
811 /* number of VMIDs */
813 /* vram base address for page table entry */
814 u64 vram_base_offset;
820 * file private structure
822 struct radeon_fpriv {
830 struct radeon_bo *ring_obj;
831 volatile uint32_t *ring;
840 struct r600_blit_cp_primitives {
841 void (*set_render_target)(struct radeon_device *rdev, int format,
842 int w, int h, u64 gpu_addr);
843 void (*cp_set_surface_sync)(struct radeon_device *rdev,
844 u32 sync_type, u32 size,
846 void (*set_shaders)(struct radeon_device *rdev);
847 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
848 void (*set_tex_resource)(struct radeon_device *rdev,
849 int format, int w, int h, int pitch,
850 u64 gpu_addr, u32 size);
851 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
853 void (*draw_auto)(struct radeon_device *rdev);
854 void (*set_default_state)(struct radeon_device *rdev);
858 struct radeon_bo *shader_obj;
859 struct r600_blit_cp_primitives primitives;
861 int ring_size_common;
862 int ring_size_per_loop;
864 u32 vs_offset, ps_offset;
872 #include "clearstate_defs.h"
875 /* for power gating */
876 struct radeon_bo *save_restore_obj;
877 uint64_t save_restore_gpu_addr;
878 volatile uint32_t *sr_ptr;
881 /* for clear state */
882 struct radeon_bo *clear_state_obj;
883 uint64_t clear_state_gpu_addr;
884 volatile uint32_t *cs_ptr;
885 struct cs_section_def *cs_data;
888 int radeon_ib_get(struct radeon_device *rdev, int ring,
889 struct radeon_ib *ib, struct radeon_vm *vm,
891 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
892 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
893 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
894 struct radeon_ib *const_ib);
895 int radeon_ib_pool_init(struct radeon_device *rdev);
896 void radeon_ib_pool_fini(struct radeon_device *rdev);
897 int radeon_ib_ring_tests(struct radeon_device *rdev);
898 /* Ring access between begin & end cannot sleep */
899 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
900 struct radeon_ring *ring);
901 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
902 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
903 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
904 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
905 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
906 void radeon_ring_undo(struct radeon_ring *ring);
907 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
908 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
909 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
910 void radeon_ring_lockup_update(struct radeon_ring *ring);
911 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
912 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
914 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
915 unsigned size, uint32_t *data);
916 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
917 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
918 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
919 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
923 void r600_dma_stop(struct radeon_device *rdev);
924 int r600_dma_resume(struct radeon_device *rdev);
925 void r600_dma_fini(struct radeon_device *rdev);
927 void cayman_dma_stop(struct radeon_device *rdev);
928 int cayman_dma_resume(struct radeon_device *rdev);
929 void cayman_dma_fini(struct radeon_device *rdev);
934 struct radeon_cs_reloc {
935 struct drm_gem_object *gobj;
936 struct radeon_bo *robj;
937 struct radeon_bo_list lobj;
942 struct radeon_cs_chunk {
948 void __user *user_ptr;
949 int last_copied_page;
953 struct radeon_cs_parser {
955 struct radeon_device *rdev;
956 struct drm_file *filp;
959 struct radeon_cs_chunk *chunks;
960 uint64_t *chunks_array;
965 struct radeon_cs_reloc *relocs;
966 struct radeon_cs_reloc **relocs_ptr;
967 struct list_head validated;
968 unsigned dma_reloc_idx;
969 /* indices of various chunks */
971 int chunk_relocs_idx;
973 int chunk_const_ib_idx;
975 struct radeon_ib const_ib;
982 struct ww_acquire_ctx ticket;
985 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
986 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
988 struct radeon_cs_packet {
997 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
998 struct radeon_cs_packet *pkt,
999 unsigned idx, unsigned reg);
1000 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1001 struct radeon_cs_packet *pkt);
1007 int radeon_agp_init(struct radeon_device *rdev);
1008 void radeon_agp_resume(struct radeon_device *rdev);
1009 void radeon_agp_suspend(struct radeon_device *rdev);
1010 void radeon_agp_fini(struct radeon_device *rdev);
1017 struct radeon_bo *wb_obj;
1018 volatile uint32_t *wb;
1024 #define RADEON_WB_SCRATCH_OFFSET 0
1025 #define RADEON_WB_RING0_NEXT_RPTR 256
1026 #define RADEON_WB_CP_RPTR_OFFSET 1024
1027 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1028 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1029 #define R600_WB_DMA_RPTR_OFFSET 1792
1030 #define R600_WB_IH_WPTR_OFFSET 2048
1031 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1032 #define R600_WB_UVD_RPTR_OFFSET 2560
1033 #define R600_WB_EVENT_OFFSET 3072
1034 #define CIK_WB_CP1_WPTR_OFFSET 3328
1035 #define CIK_WB_CP2_WPTR_OFFSET 3584
1038 * struct radeon_pm - power management datas
1039 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1040 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1041 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1042 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1043 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1044 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1045 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1046 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1047 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1048 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1049 * @needed_bandwidth: current bandwidth needs
1051 * It keeps track of various data needed to take powermanagement decision.
1052 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1053 * Equation between gpu/memory clock and available bandwidth is hw dependent
1054 * (type of memory, bus size, efficiency, ...)
1057 enum radeon_pm_method {
1063 enum radeon_dynpm_state {
1064 DYNPM_STATE_DISABLED,
1065 DYNPM_STATE_MINIMUM,
1068 DYNPM_STATE_SUSPENDED,
1070 enum radeon_dynpm_action {
1072 DYNPM_ACTION_MINIMUM,
1073 DYNPM_ACTION_DOWNCLOCK,
1074 DYNPM_ACTION_UPCLOCK,
1075 DYNPM_ACTION_DEFAULT
1078 enum radeon_voltage_type {
1085 enum radeon_pm_state_type {
1086 /* not used for dpm */
1087 POWER_STATE_TYPE_DEFAULT,
1088 POWER_STATE_TYPE_POWERSAVE,
1089 /* user selectable states */
1090 POWER_STATE_TYPE_BATTERY,
1091 POWER_STATE_TYPE_BALANCED,
1092 POWER_STATE_TYPE_PERFORMANCE,
1093 /* internal states */
1094 POWER_STATE_TYPE_INTERNAL_UVD,
1095 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1096 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1097 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1098 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1099 POWER_STATE_TYPE_INTERNAL_BOOT,
1100 POWER_STATE_TYPE_INTERNAL_THERMAL,
1101 POWER_STATE_TYPE_INTERNAL_ACPI,
1102 POWER_STATE_TYPE_INTERNAL_ULV,
1103 POWER_STATE_TYPE_INTERNAL_3DPERF,
1106 enum radeon_pm_profile_type {
1114 #define PM_PROFILE_DEFAULT_IDX 0
1115 #define PM_PROFILE_LOW_SH_IDX 1
1116 #define PM_PROFILE_MID_SH_IDX 2
1117 #define PM_PROFILE_HIGH_SH_IDX 3
1118 #define PM_PROFILE_LOW_MH_IDX 4
1119 #define PM_PROFILE_MID_MH_IDX 5
1120 #define PM_PROFILE_HIGH_MH_IDX 6
1121 #define PM_PROFILE_MAX 7
1123 struct radeon_pm_profile {
1124 int dpms_off_ps_idx;
1126 int dpms_off_cm_idx;
1130 enum radeon_int_thermal_type {
1132 THERMAL_TYPE_EXTERNAL,
1133 THERMAL_TYPE_EXTERNAL_GPIO,
1136 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1137 THERMAL_TYPE_EVERGREEN,
1141 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1145 struct radeon_voltage {
1146 enum radeon_voltage_type type;
1148 struct radeon_gpio_rec gpio;
1149 u32 delay; /* delay in usec from voltage drop to sclk change */
1150 bool active_high; /* voltage drop is active when bit is high */
1152 u8 vddc_id; /* index into vddc voltage table */
1153 u8 vddci_id; /* index into vddci voltage table */
1157 /* evergreen+ vddci */
1161 /* clock mode flags */
1162 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1164 struct radeon_pm_clock_info {
1170 struct radeon_voltage voltage;
1171 /* standardized clock flags */
1176 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1178 struct radeon_power_state {
1179 enum radeon_pm_state_type type;
1180 struct radeon_pm_clock_info *clock_info;
1181 /* number of valid clock modes in this power state */
1182 int num_clock_modes;
1183 struct radeon_pm_clock_info *default_clock_mode;
1184 /* standardized state flags */
1186 u32 misc; /* vbios specific flags */
1187 u32 misc2; /* vbios specific flags */
1188 int pcie_lanes; /* pcie lanes */
1192 * Some modes are overclocked by very low value, accept them
1194 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1196 enum radeon_dpm_auto_throttle_src {
1197 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1198 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1201 enum radeon_dpm_event_src {
1202 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1203 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1204 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1205 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1206 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1210 u32 caps; /* vbios flags */
1211 u32 class; /* vbios flags */
1212 u32 class2; /* vbios flags */
1220 struct radeon_dpm_thermal {
1221 /* thermal interrupt work */
1222 struct work_struct work;
1223 /* low temperature threshold */
1225 /* high temperature threshold */
1227 /* was interrupt low to high or high to low */
1231 enum radeon_clk_action
1237 struct radeon_blacklist_clocks
1241 enum radeon_clk_action action;
1244 struct radeon_clock_and_voltage_limits {
1251 struct radeon_clock_array {
1256 struct radeon_clock_voltage_dependency_entry {
1261 struct radeon_clock_voltage_dependency_table {
1263 struct radeon_clock_voltage_dependency_entry *entries;
1266 struct radeon_cac_leakage_entry {
1271 struct radeon_cac_leakage_table {
1273 struct radeon_cac_leakage_entry *entries;
1276 struct radeon_phase_shedding_limits_entry {
1282 struct radeon_phase_shedding_limits_table {
1284 struct radeon_phase_shedding_limits_entry *entries;
1287 struct radeon_ppm_table {
1289 u16 cpu_core_number;
1291 u32 small_ac_platform_tdp;
1293 u32 small_ac_platform_tdc;
1300 struct radeon_dpm_dynamic_state {
1301 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1302 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1303 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1304 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1305 struct radeon_clock_array valid_sclk_values;
1306 struct radeon_clock_array valid_mclk_values;
1307 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1308 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1309 u32 mclk_sclk_ratio;
1310 u32 sclk_mclk_delta;
1311 u16 vddc_vddci_delta;
1312 u16 min_vddc_for_pcie_gen2;
1313 struct radeon_cac_leakage_table cac_leakage_table;
1314 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1315 struct radeon_ppm_table *ppm_table;
1318 struct radeon_dpm_fan {
1328 bool ucode_fan_control;
1331 enum radeon_pcie_gen {
1332 RADEON_PCIE_GEN1 = 0,
1333 RADEON_PCIE_GEN2 = 1,
1334 RADEON_PCIE_GEN3 = 2,
1335 RADEON_PCIE_GEN_INVALID = 0xffff
1339 struct radeon_ps *ps;
1340 /* number of valid power states */
1342 /* current power state that is active */
1343 struct radeon_ps *current_ps;
1344 /* requested power state */
1345 struct radeon_ps *requested_ps;
1346 /* boot up power state */
1347 struct radeon_ps *boot_ps;
1348 /* default uvd power state */
1349 struct radeon_ps *uvd_ps;
1350 enum radeon_pm_state_type state;
1351 enum radeon_pm_state_type user_state;
1353 u32 voltage_response_time;
1354 u32 backbias_response_time;
1356 u32 new_active_crtcs;
1357 int new_active_crtc_count;
1358 u32 current_active_crtcs;
1359 int current_active_crtc_count;
1360 struct radeon_dpm_dynamic_state dyn_state;
1361 struct radeon_dpm_fan fan;
1364 u32 near_tdp_limit_adjusted;
1365 u32 sq_ramping_threshold;
1369 u16 load_line_slope;
1372 /* special states active */
1373 bool thermal_active;
1375 /* thermal handling */
1376 struct radeon_dpm_thermal thermal;
1379 void radeon_dpm_enable_power_state(struct radeon_device *rdev,
1380 enum radeon_pm_state_type dpm_state);
1385 /* write locked while reprogramming mclk */
1386 struct rw_semaphore mclk_lock;
1388 int active_crtc_count;
1391 fixed20_12 max_bandwidth;
1392 fixed20_12 igp_sideport_mclk;
1393 fixed20_12 igp_system_mclk;
1394 fixed20_12 igp_ht_link_clk;
1395 fixed20_12 igp_ht_link_width;
1396 fixed20_12 k8_bandwidth;
1397 fixed20_12 sideport_bandwidth;
1398 fixed20_12 ht_bandwidth;
1399 fixed20_12 core_bandwidth;
1402 fixed20_12 needed_bandwidth;
1403 struct radeon_power_state *power_state;
1404 /* number of valid power states */
1405 int num_power_states;
1406 int current_power_state_index;
1407 int current_clock_mode_index;
1408 int requested_power_state_index;
1409 int requested_clock_mode_index;
1410 int default_power_state_index;
1419 struct radeon_i2c_chan *i2c_bus;
1420 /* selected pm method */
1421 enum radeon_pm_method pm_method;
1422 /* dynpm power management */
1423 struct delayed_work dynpm_idle_work;
1424 enum radeon_dynpm_state dynpm_state;
1425 enum radeon_dynpm_action dynpm_planned_action;
1426 unsigned long dynpm_action_timeout;
1427 bool dynpm_can_upclock;
1428 bool dynpm_can_downclock;
1429 /* profile-based power management */
1430 enum radeon_pm_profile_type profile;
1432 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1433 /* internal thermal controller on rv6xx+ */
1434 enum radeon_int_thermal_type int_thermal_type;
1435 struct device *int_hwmon_dev;
1438 struct radeon_dpm dpm;
1441 int radeon_pm_get_type_index(struct radeon_device *rdev,
1442 enum radeon_pm_state_type ps_type,
1447 #define RADEON_MAX_UVD_HANDLES 10
1448 #define RADEON_UVD_STACK_SIZE (1024*1024)
1449 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1452 struct radeon_bo *vcpu_bo;
1455 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1456 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1457 struct delayed_work idle_work;
1460 int radeon_uvd_init(struct radeon_device *rdev);
1461 void radeon_uvd_fini(struct radeon_device *rdev);
1462 int radeon_uvd_suspend(struct radeon_device *rdev);
1463 int radeon_uvd_resume(struct radeon_device *rdev);
1464 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1465 uint32_t handle, struct radeon_fence **fence);
1466 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1467 uint32_t handle, struct radeon_fence **fence);
1468 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1469 void radeon_uvd_free_handles(struct radeon_device *rdev,
1470 struct drm_file *filp);
1471 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1472 void radeon_uvd_note_usage(struct radeon_device *rdev);
1473 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1474 unsigned vclk, unsigned dclk,
1475 unsigned vco_min, unsigned vco_max,
1476 unsigned fb_factor, unsigned fb_mask,
1477 unsigned pd_min, unsigned pd_max,
1479 unsigned *optimal_fb_div,
1480 unsigned *optimal_vclk_div,
1481 unsigned *optimal_dclk_div);
1482 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1483 unsigned cg_upll_func_cntl);
1488 int bits_per_sample;
1496 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1502 void radeon_test_moves(struct radeon_device *rdev);
1503 void radeon_test_ring_sync(struct radeon_device *rdev,
1504 struct radeon_ring *cpA,
1505 struct radeon_ring *cpB);
1506 void radeon_test_syncing(struct radeon_device *rdev);
1512 struct radeon_debugfs {
1513 struct drm_info_list *files;
1517 int radeon_debugfs_add_files(struct radeon_device *rdev,
1518 struct drm_info_list *files,
1520 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1524 * ASIC specific functions.
1526 struct radeon_asic {
1527 int (*init)(struct radeon_device *rdev);
1528 void (*fini)(struct radeon_device *rdev);
1529 int (*resume)(struct radeon_device *rdev);
1530 int (*suspend)(struct radeon_device *rdev);
1531 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1532 int (*asic_reset)(struct radeon_device *rdev);
1533 /* ioctl hw specific callback. Some hw might want to perform special
1534 * operation on specific ioctl. For instance on wait idle some hw
1535 * might want to perform and HDP flush through MMIO as it seems that
1536 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1539 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1540 /* check if 3D engine is idle */
1541 bool (*gui_idle)(struct radeon_device *rdev);
1542 /* wait for mc_idle */
1543 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1544 /* get the reference clock */
1545 u32 (*get_xclk)(struct radeon_device *rdev);
1546 /* get the gpu clock counter */
1547 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1550 void (*tlb_flush)(struct radeon_device *rdev);
1551 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1554 int (*init)(struct radeon_device *rdev);
1555 void (*fini)(struct radeon_device *rdev);
1558 void (*set_page)(struct radeon_device *rdev,
1559 struct radeon_ib *ib,
1561 uint64_t addr, unsigned count,
1562 uint32_t incr, uint32_t flags);
1564 /* ring specific callbacks */
1566 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1567 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1568 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1569 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1570 struct radeon_semaphore *semaphore, bool emit_wait);
1571 int (*cs_parse)(struct radeon_cs_parser *p);
1572 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1573 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1574 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1575 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1576 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1578 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1579 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1580 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1581 } ring[RADEON_NUM_RINGS];
1584 int (*set)(struct radeon_device *rdev);
1585 int (*process)(struct radeon_device *rdev);
1589 /* display watermarks */
1590 void (*bandwidth_update)(struct radeon_device *rdev);
1591 /* get frame count */
1592 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1593 /* wait for vblank */
1594 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1595 /* set backlight level */
1596 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1597 /* get backlight level */
1598 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1599 /* audio callbacks */
1600 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1601 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1603 /* copy functions for bo handling */
1605 int (*blit)(struct radeon_device *rdev,
1606 uint64_t src_offset,
1607 uint64_t dst_offset,
1608 unsigned num_gpu_pages,
1609 struct radeon_fence **fence);
1610 u32 blit_ring_index;
1611 int (*dma)(struct radeon_device *rdev,
1612 uint64_t src_offset,
1613 uint64_t dst_offset,
1614 unsigned num_gpu_pages,
1615 struct radeon_fence **fence);
1617 /* method used for bo copy */
1618 int (*copy)(struct radeon_device *rdev,
1619 uint64_t src_offset,
1620 uint64_t dst_offset,
1621 unsigned num_gpu_pages,
1622 struct radeon_fence **fence);
1623 /* ring used for bo copies */
1624 u32 copy_ring_index;
1628 int (*set_reg)(struct radeon_device *rdev, int reg,
1629 uint32_t tiling_flags, uint32_t pitch,
1630 uint32_t offset, uint32_t obj_size);
1631 void (*clear_reg)(struct radeon_device *rdev, int reg);
1633 /* hotplug detect */
1635 void (*init)(struct radeon_device *rdev);
1636 void (*fini)(struct radeon_device *rdev);
1637 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1638 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1640 /* static power management */
1642 void (*misc)(struct radeon_device *rdev);
1643 void (*prepare)(struct radeon_device *rdev);
1644 void (*finish)(struct radeon_device *rdev);
1645 void (*init_profile)(struct radeon_device *rdev);
1646 void (*get_dynpm_state)(struct radeon_device *rdev);
1647 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1648 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1649 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1650 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1651 int (*get_pcie_lanes)(struct radeon_device *rdev);
1652 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1653 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1654 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1655 int (*get_temperature)(struct radeon_device *rdev);
1657 /* dynamic power management */
1659 int (*init)(struct radeon_device *rdev);
1660 void (*setup_asic)(struct radeon_device *rdev);
1661 int (*enable)(struct radeon_device *rdev);
1662 void (*disable)(struct radeon_device *rdev);
1663 int (*pre_set_power_state)(struct radeon_device *rdev);
1664 int (*set_power_state)(struct radeon_device *rdev);
1665 void (*post_set_power_state)(struct radeon_device *rdev);
1666 void (*display_configuration_changed)(struct radeon_device *rdev);
1667 void (*fini)(struct radeon_device *rdev);
1668 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1669 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1670 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1671 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1675 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1676 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1677 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1685 const unsigned *reg_safe_bm;
1686 unsigned reg_safe_bm_size;
1691 const unsigned *reg_safe_bm;
1692 unsigned reg_safe_bm_size;
1699 unsigned max_tile_pipes;
1701 unsigned max_backends;
1703 unsigned max_threads;
1704 unsigned max_stack_entries;
1705 unsigned max_hw_contexts;
1706 unsigned max_gs_threads;
1707 unsigned sx_max_export_size;
1708 unsigned sx_max_export_pos_size;
1709 unsigned sx_max_export_smx_size;
1710 unsigned sq_num_cf_insts;
1711 unsigned tiling_nbanks;
1712 unsigned tiling_npipes;
1713 unsigned tiling_group_size;
1714 unsigned tile_config;
1715 unsigned backend_map;
1720 unsigned max_tile_pipes;
1722 unsigned max_backends;
1724 unsigned max_threads;
1725 unsigned max_stack_entries;
1726 unsigned max_hw_contexts;
1727 unsigned max_gs_threads;
1728 unsigned sx_max_export_size;
1729 unsigned sx_max_export_pos_size;
1730 unsigned sx_max_export_smx_size;
1731 unsigned sq_num_cf_insts;
1732 unsigned sx_num_of_sets;
1733 unsigned sc_prim_fifo_size;
1734 unsigned sc_hiz_tile_fifo_size;
1735 unsigned sc_earlyz_tile_fifo_fize;
1736 unsigned tiling_nbanks;
1737 unsigned tiling_npipes;
1738 unsigned tiling_group_size;
1739 unsigned tile_config;
1740 unsigned backend_map;
1743 struct evergreen_asic {
1746 unsigned max_tile_pipes;
1748 unsigned max_backends;
1750 unsigned max_threads;
1751 unsigned max_stack_entries;
1752 unsigned max_hw_contexts;
1753 unsigned max_gs_threads;
1754 unsigned sx_max_export_size;
1755 unsigned sx_max_export_pos_size;
1756 unsigned sx_max_export_smx_size;
1757 unsigned sq_num_cf_insts;
1758 unsigned sx_num_of_sets;
1759 unsigned sc_prim_fifo_size;
1760 unsigned sc_hiz_tile_fifo_size;
1761 unsigned sc_earlyz_tile_fifo_size;
1762 unsigned tiling_nbanks;
1763 unsigned tiling_npipes;
1764 unsigned tiling_group_size;
1765 unsigned tile_config;
1766 unsigned backend_map;
1769 struct cayman_asic {
1770 unsigned max_shader_engines;
1771 unsigned max_pipes_per_simd;
1772 unsigned max_tile_pipes;
1773 unsigned max_simds_per_se;
1774 unsigned max_backends_per_se;
1775 unsigned max_texture_channel_caches;
1777 unsigned max_threads;
1778 unsigned max_gs_threads;
1779 unsigned max_stack_entries;
1780 unsigned sx_num_of_sets;
1781 unsigned sx_max_export_size;
1782 unsigned sx_max_export_pos_size;
1783 unsigned sx_max_export_smx_size;
1784 unsigned max_hw_contexts;
1785 unsigned sq_num_cf_insts;
1786 unsigned sc_prim_fifo_size;
1787 unsigned sc_hiz_tile_fifo_size;
1788 unsigned sc_earlyz_tile_fifo_size;
1790 unsigned num_shader_engines;
1791 unsigned num_shader_pipes_per_simd;
1792 unsigned num_tile_pipes;
1793 unsigned num_simds_per_se;
1794 unsigned num_backends_per_se;
1795 unsigned backend_disable_mask_per_asic;
1796 unsigned backend_map;
1797 unsigned num_texture_channel_caches;
1798 unsigned mem_max_burst_length_bytes;
1799 unsigned mem_row_size_in_kb;
1800 unsigned shader_engine_tile_size;
1802 unsigned multi_gpu_tile_size;
1804 unsigned tile_config;
1808 unsigned max_shader_engines;
1809 unsigned max_tile_pipes;
1810 unsigned max_cu_per_sh;
1811 unsigned max_sh_per_se;
1812 unsigned max_backends_per_se;
1813 unsigned max_texture_channel_caches;
1815 unsigned max_gs_threads;
1816 unsigned max_hw_contexts;
1817 unsigned sc_prim_fifo_size_frontend;
1818 unsigned sc_prim_fifo_size_backend;
1819 unsigned sc_hiz_tile_fifo_size;
1820 unsigned sc_earlyz_tile_fifo_size;
1822 unsigned num_tile_pipes;
1823 unsigned num_backends_per_se;
1824 unsigned backend_disable_mask_per_asic;
1825 unsigned backend_map;
1826 unsigned num_texture_channel_caches;
1827 unsigned mem_max_burst_length_bytes;
1828 unsigned mem_row_size_in_kb;
1829 unsigned shader_engine_tile_size;
1831 unsigned multi_gpu_tile_size;
1833 unsigned tile_config;
1834 uint32_t tile_mode_array[32];
1838 unsigned max_shader_engines;
1839 unsigned max_tile_pipes;
1840 unsigned max_cu_per_sh;
1841 unsigned max_sh_per_se;
1842 unsigned max_backends_per_se;
1843 unsigned max_texture_channel_caches;
1845 unsigned max_gs_threads;
1846 unsigned max_hw_contexts;
1847 unsigned sc_prim_fifo_size_frontend;
1848 unsigned sc_prim_fifo_size_backend;
1849 unsigned sc_hiz_tile_fifo_size;
1850 unsigned sc_earlyz_tile_fifo_size;
1852 unsigned num_tile_pipes;
1853 unsigned num_backends_per_se;
1854 unsigned backend_disable_mask_per_asic;
1855 unsigned backend_map;
1856 unsigned num_texture_channel_caches;
1857 unsigned mem_max_burst_length_bytes;
1858 unsigned mem_row_size_in_kb;
1859 unsigned shader_engine_tile_size;
1861 unsigned multi_gpu_tile_size;
1863 unsigned tile_config;
1864 uint32_t tile_mode_array[32];
1867 union radeon_asic_config {
1868 struct r300_asic r300;
1869 struct r100_asic r100;
1870 struct r600_asic r600;
1871 struct rv770_asic rv770;
1872 struct evergreen_asic evergreen;
1873 struct cayman_asic cayman;
1875 struct cik_asic cik;
1879 * asic initizalization from radeon_asic.c
1881 void radeon_agp_disable(struct radeon_device *rdev);
1882 int radeon_asic_init(struct radeon_device *rdev);
1888 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1889 struct drm_file *filp);
1890 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1891 struct drm_file *filp);
1892 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1893 struct drm_file *file_priv);
1894 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1895 struct drm_file *file_priv);
1896 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1897 struct drm_file *file_priv);
1898 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1899 struct drm_file *file_priv);
1900 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1901 struct drm_file *filp);
1902 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1903 struct drm_file *filp);
1904 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1905 struct drm_file *filp);
1906 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1907 struct drm_file *filp);
1908 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1909 struct drm_file *filp);
1910 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1911 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1912 struct drm_file *filp);
1913 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1914 struct drm_file *filp);
1916 /* VRAM scratch page for HDP bug, default vram page */
1917 struct r600_vram_scratch {
1918 struct radeon_bo *robj;
1919 volatile uint32_t *ptr;
1926 struct radeon_atif_notification_cfg {
1931 struct radeon_atif_notifications {
1932 bool display_switch;
1933 bool expansion_mode_change;
1935 bool forced_power_state;
1936 bool system_power_state;
1937 bool display_conf_change;
1939 bool brightness_change;
1940 bool dgpu_display_event;
1943 struct radeon_atif_functions {
1945 bool sbios_requests;
1946 bool select_active_disp;
1948 bool get_tv_standard;
1949 bool set_tv_standard;
1950 bool get_panel_expansion_mode;
1951 bool set_panel_expansion_mode;
1952 bool temperature_change;
1953 bool graphics_device_types;
1956 struct radeon_atif {
1957 struct radeon_atif_notifications notifications;
1958 struct radeon_atif_functions functions;
1959 struct radeon_atif_notification_cfg notification_cfg;
1960 struct radeon_encoder *encoder_for_bl;
1963 struct radeon_atcs_functions {
1967 bool pcie_bus_width;
1970 struct radeon_atcs {
1971 struct radeon_atcs_functions functions;
1975 * Core structure, functions and helpers.
1977 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1978 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1980 struct radeon_device {
1982 struct drm_device *ddev;
1983 struct pci_dev *pdev;
1984 struct rw_semaphore exclusive_lock;
1986 union radeon_asic_config config;
1987 enum radeon_family family;
1988 unsigned long flags;
1990 enum radeon_pll_errata pll_errata;
1997 uint16_t bios_header_start;
1998 struct radeon_bo *stollen_vga_memory;
2000 resource_size_t rmmio_base;
2001 resource_size_t rmmio_size;
2002 /* protects concurrent MM_INDEX/DATA based register access */
2003 spinlock_t mmio_idx_lock;
2004 void __iomem *rmmio;
2005 radeon_rreg_t mc_rreg;
2006 radeon_wreg_t mc_wreg;
2007 radeon_rreg_t pll_rreg;
2008 radeon_wreg_t pll_wreg;
2009 uint32_t pcie_reg_mask;
2010 radeon_rreg_t pciep_rreg;
2011 radeon_wreg_t pciep_wreg;
2013 void __iomem *rio_mem;
2014 resource_size_t rio_mem_size;
2015 struct radeon_clock clock;
2016 struct radeon_mc mc;
2017 struct radeon_gart gart;
2018 struct radeon_mode_info mode_info;
2019 struct radeon_scratch scratch;
2020 struct radeon_doorbell doorbell;
2021 struct radeon_mman mman;
2022 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2023 wait_queue_head_t fence_queue;
2024 struct mutex ring_lock;
2025 struct radeon_ring ring[RADEON_NUM_RINGS];
2027 struct radeon_sa_manager ring_tmp_bo;
2028 struct radeon_irq irq;
2029 struct radeon_asic *asic;
2030 struct radeon_gem gem;
2031 struct radeon_pm pm;
2032 struct radeon_uvd uvd;
2033 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2034 struct radeon_wb wb;
2035 struct radeon_dummy_page dummy_page;
2040 bool fastfb_working; /* IGP feature*/
2041 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2042 const struct firmware *me_fw; /* all family ME firmware */
2043 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2044 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2045 const struct firmware *mc_fw; /* NI MC firmware */
2046 const struct firmware *ce_fw; /* SI CE firmware */
2047 const struct firmware *uvd_fw; /* UVD firmware */
2048 const struct firmware *mec_fw; /* CIK MEC firmware */
2049 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2050 const struct firmware *smc_fw; /* SMC firmware */
2051 struct r600_blit r600_blit;
2052 struct r600_vram_scratch vram_scratch;
2053 int msi_enabled; /* msi enabled */
2054 struct r600_ih ih; /* r6/700 interrupt ring */
2055 struct radeon_rlc rlc;
2056 struct radeon_mec mec;
2057 struct work_struct hotplug_work;
2058 struct work_struct audio_work;
2059 struct work_struct reset_work;
2060 int num_crtc; /* number of crtcs */
2061 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2064 struct r600_audio audio_status; /* audio stuff */
2065 struct notifier_block acpi_nb;
2066 /* only one userspace can use Hyperz features or CMASK at a time */
2067 struct drm_file *hyperz_filp;
2068 struct drm_file *cmask_filp;
2070 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2072 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2073 unsigned debugfs_count;
2074 /* virtual memory */
2075 struct radeon_vm_manager vm_manager;
2076 struct mutex gpu_clock_mutex;
2077 /* ACPI interface */
2078 struct radeon_atif atif;
2079 struct radeon_atcs atcs;
2082 int radeon_device_init(struct radeon_device *rdev,
2083 struct drm_device *ddev,
2084 struct pci_dev *pdev,
2086 void radeon_device_fini(struct radeon_device *rdev);
2087 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2089 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2090 bool always_indirect);
2091 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2092 bool always_indirect);
2093 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2094 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2096 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2097 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2102 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2105 * Registers read & write functions.
2107 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2108 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2109 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2110 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2111 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2112 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2113 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2114 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2115 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2116 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2117 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2118 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2119 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2120 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2121 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2122 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2123 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2124 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2125 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2126 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2127 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2128 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2129 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2130 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2131 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2132 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2133 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2134 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2135 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2136 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2137 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2138 #define WREG32_P(reg, val, mask) \
2140 uint32_t tmp_ = RREG32(reg); \
2142 tmp_ |= ((val) & ~(mask)); \
2143 WREG32(reg, tmp_); \
2145 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2146 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
2147 #define WREG32_PLL_P(reg, val, mask) \
2149 uint32_t tmp_ = RREG32_PLL(reg); \
2151 tmp_ |= ((val) & ~(mask)); \
2152 WREG32_PLL(reg, tmp_); \
2154 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2155 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2156 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2158 #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2159 #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2162 * Indirect registers accessor
2164 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2168 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2169 r = RREG32(RADEON_PCIE_DATA);
2173 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2175 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2176 WREG32(RADEON_PCIE_DATA, (v));
2179 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2183 WREG32(TN_SMC_IND_INDEX_0, (reg));
2184 r = RREG32(TN_SMC_IND_DATA_0);
2188 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2190 WREG32(TN_SMC_IND_INDEX_0, (reg));
2191 WREG32(TN_SMC_IND_DATA_0, (v));
2194 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2198 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2199 r = RREG32(R600_RCU_DATA);
2203 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2205 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2206 WREG32(R600_RCU_DATA, (v));
2209 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2213 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2214 r = RREG32(EVERGREEN_CG_IND_DATA);
2218 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2220 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2221 WREG32(EVERGREEN_CG_IND_DATA, (v));
2224 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2228 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2229 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2233 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2235 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2236 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2239 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2243 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2244 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2248 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2250 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2251 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2254 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2258 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2259 r = RREG32(R600_UVD_CTX_DATA);
2263 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2265 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2266 WREG32(R600_UVD_CTX_DATA, (v));
2269 void r100_pll_errata_after_index(struct radeon_device *rdev);
2275 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2276 (rdev->pdev->device == 0x5969))
2277 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2278 (rdev->family == CHIP_RV200) || \
2279 (rdev->family == CHIP_RS100) || \
2280 (rdev->family == CHIP_RS200) || \
2281 (rdev->family == CHIP_RV250) || \
2282 (rdev->family == CHIP_RV280) || \
2283 (rdev->family == CHIP_RS300))
2284 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2285 (rdev->family == CHIP_RV350) || \
2286 (rdev->family == CHIP_R350) || \
2287 (rdev->family == CHIP_RV380) || \
2288 (rdev->family == CHIP_R420) || \
2289 (rdev->family == CHIP_R423) || \
2290 (rdev->family == CHIP_RV410) || \
2291 (rdev->family == CHIP_RS400) || \
2292 (rdev->family == CHIP_RS480))
2293 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2294 (rdev->ddev->pdev->device == 0x9443) || \
2295 (rdev->ddev->pdev->device == 0x944B) || \
2296 (rdev->ddev->pdev->device == 0x9506) || \
2297 (rdev->ddev->pdev->device == 0x9509) || \
2298 (rdev->ddev->pdev->device == 0x950F) || \
2299 (rdev->ddev->pdev->device == 0x689C) || \
2300 (rdev->ddev->pdev->device == 0x689D))
2301 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2302 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2303 (rdev->family == CHIP_RS690) || \
2304 (rdev->family == CHIP_RS740) || \
2305 (rdev->family >= CHIP_R600))
2306 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2307 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2308 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2309 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2310 (rdev->flags & RADEON_IS_IGP))
2311 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2312 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2313 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2314 (rdev->flags & RADEON_IS_IGP))
2315 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2316 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2317 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2319 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2320 (rdev->ddev->pdev->device == 0x6850) || \
2321 (rdev->ddev->pdev->device == 0x6858) || \
2322 (rdev->ddev->pdev->device == 0x6859) || \
2323 (rdev->ddev->pdev->device == 0x6840) || \
2324 (rdev->ddev->pdev->device == 0x6841) || \
2325 (rdev->ddev->pdev->device == 0x6842) || \
2326 (rdev->ddev->pdev->device == 0x6843))
2331 #define RBIOS8(i) (rdev->bios[i])
2332 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2333 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2335 int radeon_combios_init(struct radeon_device *rdev);
2336 void radeon_combios_fini(struct radeon_device *rdev);
2337 int radeon_atombios_init(struct radeon_device *rdev);
2338 void radeon_atombios_fini(struct radeon_device *rdev);
2344 #if DRM_DEBUG_CODE == 0
2345 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2347 ring->ring[ring->wptr++] = v;
2348 ring->wptr &= ring->ptr_mask;
2350 ring->ring_free_dw--;
2353 /* With debugging this is just too big to inline */
2354 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2360 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2361 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2362 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2363 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2364 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
2365 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2366 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2367 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2368 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2369 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2370 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2371 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2372 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2373 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2374 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
2375 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
2376 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
2377 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
2378 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
2379 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2380 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2381 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
2382 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2383 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2384 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2385 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2386 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2387 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2388 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2389 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2390 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2391 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2392 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2393 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2394 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2395 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2396 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2397 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2398 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2399 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2400 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2401 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2402 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2403 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2404 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2405 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2406 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2407 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2408 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2409 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2410 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2411 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2412 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2413 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2414 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2415 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2416 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2417 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2418 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2419 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2420 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2421 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2422 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2423 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2424 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2425 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2426 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2427 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2428 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2429 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2430 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2431 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2432 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2433 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2434 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2435 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2436 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2437 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2438 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2440 /* Common functions */
2442 extern int radeon_gpu_reset(struct radeon_device *rdev);
2443 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2444 extern void radeon_agp_disable(struct radeon_device *rdev);
2445 extern int radeon_modeset_init(struct radeon_device *rdev);
2446 extern void radeon_modeset_fini(struct radeon_device *rdev);
2447 extern bool radeon_card_posted(struct radeon_device *rdev);
2448 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2449 extern void radeon_update_display_priority(struct radeon_device *rdev);
2450 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2451 extern void radeon_scratch_init(struct radeon_device *rdev);
2452 extern void radeon_wb_fini(struct radeon_device *rdev);
2453 extern int radeon_wb_init(struct radeon_device *rdev);
2454 extern void radeon_wb_disable(struct radeon_device *rdev);
2455 extern void radeon_surface_init(struct radeon_device *rdev);
2456 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2457 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2458 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2459 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2460 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2461 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2462 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2463 extern int radeon_resume_kms(struct drm_device *dev);
2464 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2465 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2466 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2467 const u32 *registers,
2468 const u32 array_size);
2473 int radeon_vm_manager_init(struct radeon_device *rdev);
2474 void radeon_vm_manager_fini(struct radeon_device *rdev);
2475 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2476 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2477 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2478 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2479 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2480 struct radeon_vm *vm, int ring);
2481 void radeon_vm_fence(struct radeon_device *rdev,
2482 struct radeon_vm *vm,
2483 struct radeon_fence *fence);
2484 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2485 int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2486 struct radeon_vm *vm,
2487 struct radeon_bo *bo,
2488 struct ttm_mem_reg *mem);
2489 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2490 struct radeon_bo *bo);
2491 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2492 struct radeon_bo *bo);
2493 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2494 struct radeon_vm *vm,
2495 struct radeon_bo *bo);
2496 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2497 struct radeon_bo_va *bo_va,
2500 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2501 struct radeon_bo_va *bo_va);
2504 void r600_audio_update_hdmi(struct work_struct *work);
2507 * R600 vram scratch functions
2509 int r600_vram_scratch_init(struct radeon_device *rdev);
2510 void r600_vram_scratch_fini(struct radeon_device *rdev);
2513 * r600 cs checking helper
2515 unsigned r600_mip_minify(unsigned size, unsigned level);
2516 bool r600_fmt_is_valid_color(u32 format);
2517 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2518 int r600_fmt_get_blocksize(u32 format);
2519 int r600_fmt_get_nblocksx(u32 format, u32 w);
2520 int r600_fmt_get_nblocksy(u32 format, u32 h);
2523 * r600 functions used by radeon_encoder.c
2525 struct radeon_hdmi_acr {
2539 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2541 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2542 u32 tiling_pipe_num,
2544 u32 total_max_rb_num,
2545 u32 enabled_rb_mask);
2548 * evergreen functions used by radeon_encoder.c
2551 extern int ni_init_microcode(struct radeon_device *rdev);
2552 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2555 #if defined(CONFIG_ACPI)
2556 extern int radeon_acpi_init(struct radeon_device *rdev);
2557 extern void radeon_acpi_fini(struct radeon_device *rdev);
2558 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2559 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2560 u8 perf_req, bool advertise);
2561 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2563 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2564 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2567 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2568 struct radeon_cs_packet *pkt,
2570 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2571 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2572 struct radeon_cs_packet *pkt);
2573 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2574 struct radeon_cs_reloc **cs_reloc,
2576 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2577 uint32_t *vline_start_end,
2578 uint32_t *vline_status);
2580 #include "radeon_object.h"