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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_USBCX_TYPEDEFS_H__
53 #define __CVMX_USBCX_TYPEDEFS_H__
55 #define CVMX_USBCX_DAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull)
56 #define CVMX_USBCX_DAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull)
57 #define CVMX_USBCX_DCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull)
58 #define CVMX_USBCX_DCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull)
59 #define CVMX_USBCX_DIEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
60 #define CVMX_USBCX_DIEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
61 #define CVMX_USBCX_DIEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull)
62 #define CVMX_USBCX_DIEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
63 #define CVMX_USBCX_DOEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
64 #define CVMX_USBCX_DOEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
65 #define CVMX_USBCX_DOEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull)
66 #define CVMX_USBCX_DOEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
67 #define CVMX_USBCX_DPTXFSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4)
68 #define CVMX_USBCX_DSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull)
69 #define CVMX_USBCX_DTKNQR1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull)
70 #define CVMX_USBCX_DTKNQR2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull)
71 #define CVMX_USBCX_DTKNQR3(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull)
72 #define CVMX_USBCX_DTKNQR4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull)
73 #define CVMX_USBCX_GAHBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull)
74 #define CVMX_USBCX_GHWCFG1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull)
75 #define CVMX_USBCX_GHWCFG2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull)
76 #define CVMX_USBCX_GHWCFG3(block_id) (CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull)
77 #define CVMX_USBCX_GHWCFG4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull)
78 #define CVMX_USBCX_GINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull)
79 #define CVMX_USBCX_GINTSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull)
80 #define CVMX_USBCX_GNPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull)
81 #define CVMX_USBCX_GNPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull)
82 #define CVMX_USBCX_GOTGCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull)
83 #define CVMX_USBCX_GOTGINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull)
84 #define CVMX_USBCX_GRSTCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull)
85 #define CVMX_USBCX_GRXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull)
86 #define CVMX_USBCX_GRXSTSPD(block_id) (CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull)
87 #define CVMX_USBCX_GRXSTSPH(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull)
88 #define CVMX_USBCX_GRXSTSRD(block_id) (CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull)
89 #define CVMX_USBCX_GRXSTSRH(block_id) (CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull)
90 #define CVMX_USBCX_GSNPSID(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull)
91 #define CVMX_USBCX_GUSBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull)
92 #define CVMX_USBCX_HAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull)
93 #define CVMX_USBCX_HAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull)
94 #define CVMX_USBCX_HCCHARX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
95 #define CVMX_USBCX_HCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull)
96 #define CVMX_USBCX_HCINTMSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
97 #define CVMX_USBCX_HCINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
98 #define CVMX_USBCX_HCSPLTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
99 #define CVMX_USBCX_HCTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
100 #define CVMX_USBCX_HFIR(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull)
101 #define CVMX_USBCX_HFNUM(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull)
102 #define CVMX_USBCX_HPRT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull)
103 #define CVMX_USBCX_HPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull)
104 #define CVMX_USBCX_HPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull)
105 #define CVMX_USBCX_NPTXDFIFOX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096)
106 #define CVMX_USBCX_PCGCCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull)
111 * Core AHB Configuration Register (GAHBCFG)
113 * This register can be used to configure the core after power-on or a change in mode of operation.
114 * This register mainly contains AHB system-related configuration parameters. The AHB is the processor
115 * interface to the O2P USB core. In general, software need not know about this interface except to
116 * program the values as specified.
118 * The application must program this register as part of the O2P USB core initialization.
119 * Do not change this register after the initial programming.
121 union cvmx_usbcx_gahbcfg {
124 * struct cvmx_usbcx_gahbcfg_s
125 * @ptxfemplvl: Periodic TxFIFO Empty Level (PTxFEmpLvl)
126 * Software should set this bit to 0x1.
127 * Indicates when the Periodic TxFIFO Empty Interrupt bit in the
128 * Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
129 * bit is used only in Slave mode.
130 * * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic
131 * TxFIFO is half empty
132 * * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic
133 * TxFIFO is completely empty
134 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
135 * Software should set this bit to 0x1.
136 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
137 * the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
138 * This bit is used only in Slave mode.
139 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
140 * Periodic TxFIFO is half empty
141 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
142 * Periodic TxFIFO is completely empty
143 * @dmaen: DMA Enable (DMAEn)
144 * * 1'b0: Core operates in Slave mode
145 * * 1'b1: Core operates in a DMA mode
146 * @hbstlen: Burst Length/Type (HBstLen)
147 * This field has not effect and should be left as 0x0.
148 * @glblintrmsk: Global Interrupt Mask (GlblIntrMsk)
149 * Software should set this field to 0x1.
150 * The application uses this bit to mask or unmask the interrupt
151 * line assertion to itself. Irrespective of this bit's setting, the
152 * interrupt status registers are updated by the core.
153 * * 1'b0: Mask the interrupt assertion to the application.
154 * * 1'b1: Unmask the interrupt assertion to the application.
156 struct cvmx_usbcx_gahbcfg_s {
157 uint32_t reserved_9_31 : 23;
158 uint32_t ptxfemplvl : 1;
159 uint32_t nptxfemplvl : 1;
160 uint32_t reserved_6_6 : 1;
162 uint32_t hbstlen : 4;
163 uint32_t glblintrmsk : 1;
166 typedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t;
171 * User HW Config3 Register (GHWCFG3)
173 * This register contains the configuration options of the O2P USB core.
175 union cvmx_usbcx_ghwcfg3 {
178 * struct cvmx_usbcx_ghwcfg3_s
179 * @dfifodepth: DFIFO Depth (DfifoDepth)
180 * This value is in terms of 32-bit words.
181 * * Minimum value is 32
182 * * Maximum value is 32768
183 * @ahbphysync: AHB and PHY Synchronous (AhbPhySync)
184 * Indicates whether AHB and PHY clocks are synchronous to
188 * This bit is tied to 1.
189 * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType)
190 * * 1'b0: Asynchronous reset is used in the core
191 * * 1'b1: Synchronous reset is used in the core
192 * @optfeature: Optional Features Removed (OptFeature)
193 * Indicates whether the User ID register, GPIO interface ports,
194 * and SOF toggle and counter ports were removed for gate count
196 * @vendor_control_interface_support: Vendor Control Interface Support
197 * * 1'b0: Vendor Control Interface is not available on the core.
198 * * 1'b1: Vendor Control Interface is available.
199 * @i2c_selection: I2C Selection
200 * * 1'b0: I2C Interface is not available on the core.
201 * * 1'b1: I2C Interface is available on the core.
202 * @otgen: OTG Function Enabled (OtgEn)
203 * The application uses this bit to indicate the O2P USB core's
205 * * 1'b0: Not OTG capable
206 * * 1'b1: OTG Capable
207 * @pktsizewidth: Width of Packet Size Counters (PktSizeWidth)
216 * @xfersizewidth: Width of Transfer Size Counters (XferSizeWidth)
223 struct cvmx_usbcx_ghwcfg3_s {
224 uint32_t dfifodepth : 16;
225 uint32_t reserved_13_15 : 3;
226 uint32_t ahbphysync : 1;
227 uint32_t rsttype : 1;
228 uint32_t optfeature : 1;
229 uint32_t vendor_control_interface_support : 1;
230 uint32_t i2c_selection : 1;
232 uint32_t pktsizewidth : 3;
233 uint32_t xfersizewidth : 4;
236 typedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t;
241 * Core Interrupt Mask Register (GINTMSK)
243 * This register works with the Core Interrupt register to interrupt the application.
244 * When an interrupt bit is masked, the interrupt associated with that bit will not be generated.
245 * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set.
246 * Mask interrupt: 1'b0, Unmask interrupt: 1'b1
248 union cvmx_usbcx_gintmsk {
251 * struct cvmx_usbcx_gintmsk_s
252 * @wkupintmsk: Resume/Remote Wakeup Detected Interrupt Mask
254 * @sessreqintmsk: Session Request/New Session Detected Interrupt Mask
256 * @disconnintmsk: Disconnect Detected Interrupt Mask (DisconnIntMsk)
257 * @conidstschngmsk: Connector ID Status Change Mask (ConIDStsChngMsk)
258 * @ptxfempmsk: Periodic TxFIFO Empty Mask (PTxFEmpMsk)
259 * @hchintmsk: Host Channels Interrupt Mask (HChIntMsk)
260 * @prtintmsk: Host Port Interrupt Mask (PrtIntMsk)
261 * @fetsuspmsk: Data Fetch Suspended Mask (FetSuspMsk)
262 * @incomplpmsk: Incomplete Periodic Transfer Mask (incomplPMsk)
263 * Incomplete Isochronous OUT Transfer Mask
265 * @incompisoinmsk: Incomplete Isochronous IN Transfer Mask (incompISOINMsk)
266 * @oepintmsk: OUT Endpoints Interrupt Mask (OEPIntMsk)
267 * @inepintmsk: IN Endpoints Interrupt Mask (INEPIntMsk)
268 * @epmismsk: Endpoint Mismatch Interrupt Mask (EPMisMsk)
269 * @eopfmsk: End of Periodic Frame Interrupt Mask (EOPFMsk)
270 * @isooutdropmsk: Isochronous OUT Packet Dropped Interrupt Mask
272 * @enumdonemsk: Enumeration Done Mask (EnumDoneMsk)
273 * @usbrstmsk: USB Reset Mask (USBRstMsk)
274 * @usbsuspmsk: USB Suspend Mask (USBSuspMsk)
275 * @erlysuspmsk: Early Suspend Mask (ErlySuspMsk)
276 * @i2cint: I2C Interrupt Mask (I2CINT)
277 * @ulpickintmsk: ULPI Carkit Interrupt Mask (ULPICKINTMsk)
278 * I2C Carkit Interrupt Mask (I2CCKINTMsk)
279 * @goutnakeffmsk: Global OUT NAK Effective Mask (GOUTNakEffMsk)
280 * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask (GINNakEffMsk)
281 * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk)
282 * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk)
283 * @sofmsk: Start of (micro)Frame Mask (SofMsk)
284 * @otgintmsk: OTG Interrupt Mask (OTGIntMsk)
285 * @modemismsk: Mode Mismatch Interrupt Mask (ModeMisMsk)
287 struct cvmx_usbcx_gintmsk_s {
288 uint32_t wkupintmsk : 1;
289 uint32_t sessreqintmsk : 1;
290 uint32_t disconnintmsk : 1;
291 uint32_t conidstschngmsk : 1;
292 uint32_t reserved_27_27 : 1;
293 uint32_t ptxfempmsk : 1;
294 uint32_t hchintmsk : 1;
295 uint32_t prtintmsk : 1;
296 uint32_t reserved_23_23 : 1;
297 uint32_t fetsuspmsk : 1;
298 uint32_t incomplpmsk : 1;
299 uint32_t incompisoinmsk : 1;
300 uint32_t oepintmsk : 1;
301 uint32_t inepintmsk : 1;
302 uint32_t epmismsk : 1;
303 uint32_t reserved_16_16 : 1;
304 uint32_t eopfmsk : 1;
305 uint32_t isooutdropmsk : 1;
306 uint32_t enumdonemsk : 1;
307 uint32_t usbrstmsk : 1;
308 uint32_t usbsuspmsk : 1;
309 uint32_t erlysuspmsk : 1;
311 uint32_t ulpickintmsk : 1;
312 uint32_t goutnakeffmsk : 1;
313 uint32_t ginnakeffmsk : 1;
314 uint32_t nptxfempmsk : 1;
315 uint32_t rxflvlmsk : 1;
317 uint32_t otgintmsk : 1;
318 uint32_t modemismsk : 1;
319 uint32_t reserved_0_0 : 1;
322 typedef union cvmx_usbcx_gintmsk cvmx_usbcx_gintmsk_t;
327 * Core Interrupt Register (GINTSTS)
329 * This register interrupts the application for system-level events in the current mode of operation
330 * (Device mode or Host mode). It is shown in Interrupt. Some of the bits in this register are valid only in Host mode,
331 * while others are valid in Device mode only. This register also indicates the current mode of operation.
332 * In order to clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit.
333 * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these
334 * interrupts, FIFO interrupt conditions are cleared automatically.
336 union cvmx_usbcx_gintsts {
339 * struct cvmx_usbcx_gintsts_s
340 * @wkupint: Resume/Remote Wakeup Detected Interrupt (WkUpInt)
341 * In Device mode, this interrupt is asserted when a resume is
342 * detected on the USB. In Host mode, this interrupt is asserted
343 * when a remote wakeup is detected on the USB.
344 * For more information on how to use this interrupt, see "Partial
345 * Power-Down and Clock Gating Programming Model" on
347 * @sessreqint: Session Request/New Session Detected Interrupt (SessReqInt)
348 * In Host mode, this interrupt is asserted when a session request
349 * is detected from the device. In Device mode, this interrupt is
350 * asserted when the utmiotg_bvalid signal goes high.
351 * For more information on how to use this interrupt, see "Partial
352 * Power-Down and Clock Gating Programming Model" on
354 * @disconnint: Disconnect Detected Interrupt (DisconnInt)
355 * Asserted when a device disconnect is detected.
356 * @conidstschng: Connector ID Status Change (ConIDStsChng)
357 * The core sets this bit when there is a change in connector ID
359 * @ptxfemp: Periodic TxFIFO Empty (PTxFEmp)
360 * Asserted when the Periodic Transmit FIFO is either half or
361 * completely empty and there is space for at least one entry to be
362 * written in the Periodic Request Queue. The half or completely
363 * empty status is determined by the Periodic TxFIFO Empty Level
364 * bit in the Core AHB Configuration register
365 * (GAHBCFG.PTxFEmpLvl).
366 * @hchint: Host Channels Interrupt (HChInt)
367 * The core sets this bit to indicate that an interrupt is pending on
368 * one of the channels of the core (in Host mode). The application
369 * must read the Host All Channels Interrupt (HAINT) register to
370 * determine the exact number of the channel on which the
371 * interrupt occurred, and then read the corresponding Host
372 * Channel-n Interrupt (HCINTn) register to determine the exact
373 * cause of the interrupt. The application must clear the
374 * appropriate status bit in the HCINTn register to clear this bit.
375 * @prtint: Host Port Interrupt (PrtInt)
376 * The core sets this bit to indicate a change in port status of one
377 * of the O2P USB core ports in Host mode. The application must
378 * read the Host Port Control and Status (HPRT) register to
379 * determine the exact event that caused this interrupt. The
380 * application must clear the appropriate status bit in the Host Port
381 * Control and Status register to clear this bit.
382 * @fetsusp: Data Fetch Suspended (FetSusp)
383 * This interrupt is valid only in DMA mode. This interrupt indicates
384 * that the core has stopped fetching data for IN endpoints due to
385 * the unavailability of TxFIFO space or Request Queue space.
386 * This interrupt is used by the application for an endpoint
387 * mismatch algorithm.
388 * @incomplp: Incomplete Periodic Transfer (incomplP)
389 * In Host mode, the core sets this interrupt bit when there are
390 * incomplete periodic transactions still pending which are
391 * scheduled for the current microframe.
392 * Incomplete Isochronous OUT Transfer (incompISOOUT)
393 * The Device mode, the core sets this interrupt to indicate that
394 * there is at least one isochronous OUT endpoint on which the
395 * transfer is not completed in the current microframe. This
396 * interrupt is asserted along with the End of Periodic Frame
397 * Interrupt (EOPF) bit in this register.
398 * @incompisoin: Incomplete Isochronous IN Transfer (incompISOIN)
399 * The core sets this interrupt to indicate that there is at least one
400 * isochronous IN endpoint on which the transfer is not completed
401 * in the current microframe. This interrupt is asserted along with
402 * the End of Periodic Frame Interrupt (EOPF) bit in this register.
403 * @oepint: OUT Endpoints Interrupt (OEPInt)
404 * The core sets this bit to indicate that an interrupt is pending on
405 * one of the OUT endpoints of the core (in Device mode). The
406 * application must read the Device All Endpoints Interrupt
407 * (DAINT) register to determine the exact number of the OUT
408 * endpoint on which the interrupt occurred, and then read the
409 * corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
410 * register to determine the exact cause of the interrupt. The
411 * application must clear the appropriate status bit in the
412 * corresponding DOEPINTn register to clear this bit.
413 * @iepint: IN Endpoints Interrupt (IEPInt)
414 * The core sets this bit to indicate that an interrupt is pending on
415 * one of the IN endpoints of the core (in Device mode). The
416 * application must read the Device All Endpoints Interrupt
417 * (DAINT) register to determine the exact number of the IN
418 * endpoint on which the interrupt occurred, and then read the
419 * corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
420 * register to determine the exact cause of the interrupt. The
421 * application must clear the appropriate status bit in the
422 * corresponding DIEPINTn register to clear this bit.
423 * @epmis: Endpoint Mismatch Interrupt (EPMis)
424 * Indicates that an IN token has been received for a non-periodic
425 * endpoint, but the data for another endpoint is present in the top
426 * of the Non-Periodic Transmit FIFO and the IN endpoint
427 * mismatch count programmed by the application has expired.
428 * @eopf: End of Periodic Frame Interrupt (EOPF)
429 * Indicates that the period specified in the Periodic Frame Interval
430 * field of the Device Configuration register (DCFG.PerFrInt) has
431 * been reached in the current microframe.
432 * @isooutdrop: Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
433 * The core sets this bit when it fails to write an isochronous OUT
434 * packet into the RxFIFO because the RxFIFO doesn't have
435 * enough space to accommodate a maximum packet size packet
436 * for the isochronous OUT endpoint.
437 * @enumdone: Enumeration Done (EnumDone)
438 * The core sets this bit to indicate that speed enumeration is
439 * complete. The application must read the Device Status (DSTS)
440 * register to obtain the enumerated speed.
441 * @usbrst: USB Reset (USBRst)
442 * The core sets this bit to indicate that a reset is detected on the
444 * @usbsusp: USB Suspend (USBSusp)
445 * The core sets this bit to indicate that a suspend was detected
446 * on the USB. The core enters the Suspended state when there
447 * is no activity on the phy_line_state_i signal for an extended
449 * @erlysusp: Early Suspend (ErlySusp)
450 * The core sets this bit to indicate that an Idle state has been
451 * detected on the USB for 3 ms.
452 * @i2cint: I2C Interrupt (I2CINT)
453 * This bit is always 0x0.
454 * @ulpickint: ULPI Carkit Interrupt (ULPICKINT)
455 * This bit is always 0x0.
456 * @goutnakeff: Global OUT NAK Effective (GOUTNakEff)
457 * Indicates that the Set Global OUT NAK bit in the Device Control
458 * register (DCTL.SGOUTNak), set by the application, has taken
459 * effect in the core. This bit can be cleared by writing the Clear
460 * Global OUT NAK bit in the Device Control register
462 * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff)
463 * Indicates that the Set Global Non-Periodic IN NAK bit in the
464 * Device Control register (DCTL.SGNPInNak), set by the
465 * application, has taken effect in the core. That is, the core has
466 * sampled the Global IN NAK bit set by the application. This bit
467 * can be cleared by clearing the Clear Global Non-Periodic IN
468 * NAK bit in the Device Control register (DCTL.CGNPInNak).
469 * This interrupt does not necessarily mean that a NAK handshake
470 * is sent out on the USB. The STALL bit takes precedence over
472 * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp)
473 * This interrupt is asserted when the Non-Periodic TxFIFO is
474 * either half or completely empty, and there is space for at least
475 * one entry to be written to the Non-Periodic Transmit Request
476 * Queue. The half or completely empty status is determined by
477 * the Non-Periodic TxFIFO Empty Level bit in the Core AHB
478 * Configuration register (GAHBCFG.NPTxFEmpLvl).
479 * @rxflvl: RxFIFO Non-Empty (RxFLvl)
480 * Indicates that there is at least one packet pending to be read
482 * @sof: Start of (micro)Frame (Sof)
483 * In Host mode, the core sets this bit to indicate that an SOF
484 * (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
485 * USB. The application must write a 1 to this bit to clear the
487 * In Device mode, in the core sets this bit to indicate that an SOF
488 * token has been received on the USB. The application can read
489 * the Device Status register to get the current (micro)frame
490 * number. This interrupt is seen only when the core is operating
491 * at either HS or FS.
492 * @otgint: OTG Interrupt (OTGInt)
493 * The core sets this bit to indicate an OTG protocol event. The
494 * application must read the OTG Interrupt Status (GOTGINT)
495 * register to determine the exact event that caused this interrupt.
496 * The application must clear the appropriate status bit in the
497 * GOTGINT register to clear this bit.
498 * @modemis: Mode Mismatch Interrupt (ModeMis)
499 * The core sets this bit when the application is trying to access:
500 * * A Host mode register, when the core is operating in Device
502 * * A Device mode register, when the core is operating in Host
504 * The register access is completed on the AHB with an OKAY
505 * response, but is ignored by the core internally and doesn't
506 * affect the operation of the core.
507 * @curmod: Current Mode of Operation (CurMod)
508 * Indicates the current mode of operation.
509 * * 1'b0: Device mode
512 struct cvmx_usbcx_gintsts_s {
513 uint32_t wkupint : 1;
514 uint32_t sessreqint : 1;
515 uint32_t disconnint : 1;
516 uint32_t conidstschng : 1;
517 uint32_t reserved_27_27 : 1;
518 uint32_t ptxfemp : 1;
521 uint32_t reserved_23_23 : 1;
522 uint32_t fetsusp : 1;
523 uint32_t incomplp : 1;
524 uint32_t incompisoin : 1;
528 uint32_t reserved_16_16 : 1;
530 uint32_t isooutdrop : 1;
531 uint32_t enumdone : 1;
533 uint32_t usbsusp : 1;
534 uint32_t erlysusp : 1;
536 uint32_t ulpickint : 1;
537 uint32_t goutnakeff : 1;
538 uint32_t ginnakeff : 1;
539 uint32_t nptxfemp : 1;
543 uint32_t modemis : 1;
547 typedef union cvmx_usbcx_gintsts cvmx_usbcx_gintsts_t;
550 * cvmx_usbc#_gnptxfsiz
552 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
554 * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO.
556 union cvmx_usbcx_gnptxfsiz {
559 * struct cvmx_usbcx_gnptxfsiz_s
560 * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep)
561 * This value is in terms of 32-bit words.
562 * Minimum value is 16
563 * Maximum value is 32768
564 * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
565 * This field contains the memory start address for Non-Periodic
568 struct cvmx_usbcx_gnptxfsiz_s {
569 uint32_t nptxfdep : 16;
570 uint32_t nptxfstaddr : 16;
573 typedef union cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxfsiz_t;
576 * cvmx_usbc#_gnptxsts
578 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
580 * This read-only register contains the free space information for the Non-Periodic TxFIFO and
581 * the Non-Periodic Transmit Request Queue
583 union cvmx_usbcx_gnptxsts {
586 * struct cvmx_usbcx_gnptxsts_s
587 * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
588 * Entry in the Non-Periodic Tx Request Queue that is currently
589 * being processed by the MAC.
590 * * Bits [30:27]: Channel/endpoint number
592 * - 2'b00: IN/OUT token
593 * - 2'b01: Zero-length transmit packet (device IN/host OUT)
594 * - 2'b10: PING/CSPLIT token
595 * - 2'b11: Channel halt command
596 * * Bit [24]: Terminate (last entry for selected channel/endpoint)
597 * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available
599 * Indicates the amount of free space available in the Non-
600 * Periodic Transmit Request Queue. This queue holds both IN
601 * and OUT requests in Host mode. Device mode has only IN
603 * * 8'h0: Non-Periodic Transmit Request Queue is full
604 * * 8'h1: 1 location available
605 * * 8'h2: 2 locations available
606 * * n: n locations available (0..8)
608 * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
609 * Indicates the amount of free space available in the Non-
611 * Values are in terms of 32-bit words.
612 * * 16'h0: Non-Periodic TxFIFO is full
613 * * 16'h1: 1 word available
614 * * 16'h2: 2 words available
615 * * 16'hn: n words available (where 0..32768)
616 * * 16'h8000: 32768 words available
619 struct cvmx_usbcx_gnptxsts_s {
620 uint32_t reserved_31_31 : 1;
621 uint32_t nptxqtop : 7;
622 uint32_t nptxqspcavail : 8;
623 uint32_t nptxfspcavail : 16;
626 typedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t;
631 * Core Reset Register (GRSTCTL)
633 * The application uses this register to reset various hardware features inside the core.
635 union cvmx_usbcx_grstctl {
638 * struct cvmx_usbcx_grstctl_s
639 * @ahbidle: AHB Master Idle (AHBIdle)
640 * Indicates that the AHB Master State Machine is in the IDLE
642 * @dmareq: DMA Request Signal (DMAReq)
643 * Indicates that the DMA request is in progress. Used for debug.
644 * @txfnum: TxFIFO Number (TxFNum)
645 * This is the FIFO number that must be flushed using the TxFIFO
646 * Flush bit. This field must not be changed until the core clears
647 * the TxFIFO Flush bit.
648 * * 5'h0: Non-Periodic TxFIFO flush
649 * * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
650 * TxFIFO flush in Host mode
651 * * 5'h2: Periodic TxFIFO 2 flush in Device mode
653 * * 5'hF: Periodic TxFIFO 15 flush in Device mode
654 * * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
656 * @txfflsh: TxFIFO Flush (TxFFlsh)
657 * This bit selectively flushes a single or all transmit FIFOs, but
658 * cannot do so if the core is in the midst of a transaction.
659 * The application must only write this bit after checking that the
660 * core is neither writing to the TxFIFO nor reading from the
662 * The application must wait until the core clears this bit before
663 * performing any operations. This bit takes 8 clocks (of phy_clk or
664 * hclk, whichever is slower) to clear.
665 * @rxfflsh: RxFIFO Flush (RxFFlsh)
666 * The application can flush the entire RxFIFO using this bit, but
667 * must first ensure that the core is not in the middle of a
669 * The application must only write to this bit after checking that the
670 * core is neither reading from the RxFIFO nor writing to the
672 * The application must wait until the bit is cleared before
673 * performing any other operations. This bit will take 8 clocks
674 * (slowest of PHY or AHB clock) to clear.
675 * @intknqflsh: IN Token Sequence Learning Queue Flush (INTknQFlsh)
676 * The application writes this bit to flush the IN Token Sequence
678 * @frmcntrrst: Host Frame Counter Reset (FrmCntrRst)
679 * The application writes this bit to reset the (micro)frame number
680 * counter inside the core. When the (micro)frame counter is reset,
681 * the subsequent SOF sent out by the core will have a
682 * (micro)frame number of 0.
683 * @hsftrst: HClk Soft Reset (HSftRst)
684 * The application uses this bit to flush the control logic in the AHB
685 * Clock domain. Only AHB Clock Domain pipelines are reset.
686 * * FIFOs are not flushed with this bit.
687 * * All state machines in the AHB clock domain are reset to the
688 * Idle state after terminating the transactions on the AHB,
689 * following the protocol.
690 * * CSR control bits used by the AHB clock domain state
691 * machines are cleared.
692 * * To clear this interrupt, status mask bits that control the
693 * interrupt status and are generated by the AHB clock domain
694 * state machine are cleared.
695 * * Because interrupt status bits are not cleared, the application
696 * can get the status of any core events that occurred after it set
698 * This is a self-clearing bit that the core clears after all necessary
699 * logic is reset in the core. This may take several clocks,
700 * depending on the core's current state.
701 * @csftrst: Core Soft Reset (CSftRst)
702 * Resets the hclk and phy_clock domains as follows:
703 * * Clears the interrupts and all the CSR registers except the
704 * following register bits:
705 * - PCGCCTL.RstPdwnModule
708 * - PCGCCTL.StopPPhyLPwrClkSelclk
709 * - GUSBCFG.PhyLPwrClkSel
713 * - GUSBCFG.ULPI_UTMI_Sel
717 * * All module state machines (except the AHB Slave Unit) are
718 * reset to the IDLE state, and all the transmit FIFOs and the
719 * receive FIFO are flushed.
720 * * Any transactions on the AHB Master are terminated as soon
721 * as possible, after gracefully completing the last data phase of
722 * an AHB transfer. Any transactions on the USB are terminated
724 * The application can write to this bit any time it wants to reset
725 * the core. This is a self-clearing bit and the core clears this bit
726 * after all the necessary logic is reset in the core, which may take
727 * several clocks, depending on the current state of the core.
728 * Once this bit is cleared software should wait at least 3 PHY
729 * clocks before doing any access to the PHY domain
730 * (synchronization delay). Software should also should check that
731 * bit 31 of this register is 1 (AHB Master is IDLE) before starting
733 * Typically software reset is used during software development
734 * and also when you dynamically change the PHY selection bits
735 * in the USB configuration registers listed above. When you
736 * change the PHY, the corresponding clock for the PHY is
737 * selected and used in the PHY domain. Once a new clock is
738 * selected, the PHY domain has to be reset for proper operation.
740 struct cvmx_usbcx_grstctl_s {
741 uint32_t ahbidle : 1;
743 uint32_t reserved_11_29 : 19;
745 uint32_t txfflsh : 1;
746 uint32_t rxfflsh : 1;
747 uint32_t intknqflsh : 1;
748 uint32_t frmcntrrst : 1;
749 uint32_t hsftrst : 1;
750 uint32_t csftrst : 1;
753 typedef union cvmx_usbcx_grstctl cvmx_usbcx_grstctl_t;
758 * Receive FIFO Size Register (GRXFSIZ)
760 * The application can program the RAM size that must be allocated to the RxFIFO.
762 union cvmx_usbcx_grxfsiz {
765 * struct cvmx_usbcx_grxfsiz_s
766 * @rxfdep: RxFIFO Depth (RxFDep)
767 * This value is in terms of 32-bit words.
768 * * Minimum value is 16
769 * * Maximum value is 32768
771 struct cvmx_usbcx_grxfsiz_s {
772 uint32_t reserved_16_31 : 16;
773 uint32_t rxfdep : 16;
776 typedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t;
779 * cvmx_usbc#_grxstsph
781 * Receive Status Read and Pop Register, Host Mode (GRXSTSPH)
783 * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
784 * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSPD instead.
785 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
786 * The offset difference shown in this document is for software clarity and is actually ignored by the
789 union cvmx_usbcx_grxstsph {
792 * struct cvmx_usbcx_grxstsph_s
793 * @pktsts: Packet Status (PktSts)
794 * Indicates the status of the received packet
795 * * 4'b0010: IN data packet received
796 * * 4'b0011: IN transfer completed (triggers an interrupt)
797 * * 4'b0101: Data toggle error (triggers an interrupt)
798 * * 4'b0111: Channel halted (triggers an interrupt)
800 * @dpid: Data PID (DPID)
805 * @bcnt: Byte Count (BCnt)
806 * Indicates the byte count of the received IN data packet
807 * @chnum: Channel Number (ChNum)
808 * Indicates the channel number to which the current received
811 struct cvmx_usbcx_grxstsph_s {
812 uint32_t reserved_21_31 : 11;
819 typedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t;
824 * Core USB Configuration Register (GUSBCFG)
826 * This register can be used to configure the core after power-on or a changing to Host mode or Device mode.
827 * It contains USB and USB-PHY related configuration parameters. The application must program this register
828 * before starting any transactions on either the AHB or the USB.
829 * Do not make changes to this register after the initial programming.
831 union cvmx_usbcx_gusbcfg {
834 * struct cvmx_usbcx_gusbcfg_s
835 * @otgi2csel: UTMIFS or I2C Interface Select (OtgI2CSel)
836 * This bit is always 0x0.
837 * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel)
838 * Software should set this bit to 0x0.
839 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
840 * FS and LS modes, the PHY can usually operate on a 48-MHz
841 * clock to save power.
842 * * 1'b0: 480-MHz Internal PLL clock
843 * * 1'b1: 48-MHz External Clock
844 * In 480 MHz mode, the UTMI interface operates at either 60 or
845 * 30-MHz, depending upon whether 8- or 16-bit data width is
846 * selected. In 48-MHz mode, the UTMI interface operates at 48
847 * MHz in FS mode and at either 48 or 6 MHz in LS mode
848 * (depending on the PHY vendor).
849 * This bit drives the utmi_fsls_low_power core output signal, and
850 * is valid only for UTMI+ PHYs.
851 * @usbtrdtim: USB Turnaround Time (USBTrdTim)
852 * Sets the turnaround time in PHY clocks.
853 * Specifies the response time for a MAC request to the Packet
854 * FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
855 * This must be programmed to 0x5.
856 * @hnpcap: HNP-Capable (HNPCap)
857 * This bit is always 0x0.
858 * @srpcap: SRP-Capable (SRPCap)
859 * This bit is always 0x0.
860 * @ddrsel: ULPI DDR Select (DDRSel)
861 * Software should set this bit to 0x0.
862 * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
863 * Software should set this bit to 0x0.
864 * @fsintf: Full-Speed Serial Interface Select (FSIntf)
865 * Software should set this bit to 0x0.
866 * @ulpi_utmi_sel: ULPI or UTMI+ Select (ULPI_UTMI_Sel)
867 * This bit is always 0x0.
868 * @phyif: PHY Interface (PHYIf)
869 * This bit is always 0x1.
870 * @toutcal: HS/FS Timeout Calibration (TOutCal)
871 * The number of PHY clocks that the application programs in this
872 * field is added to the high-speed/full-speed interpacket timeout
873 * duration in the core to account for any additional delays
874 * introduced by the PHY. This may be required, since the delay
875 * introduced by the PHY in generating the linestate condition may
876 * vary from one PHY to another.
877 * The USB standard timeout value for high-speed operation is
878 * 736 to 816 (inclusive) bit times. The USB standard timeout
879 * value for full-speed operation is 16 to 18 (inclusive) bit times.
880 * The application must program this field based on the speed of
881 * enumeration. The number of bit times added per PHY clock are:
882 * High-speed operation:
883 * * One 30-MHz PHY clock = 16 bit times
884 * * One 60-MHz PHY clock = 8 bit times
885 * Full-speed operation:
886 * * One 30-MHz PHY clock = 0.4 bit times
887 * * One 60-MHz PHY clock = 0.2 bit times
888 * * One 48-MHz PHY clock = 0.25 bit times
890 struct cvmx_usbcx_gusbcfg_s {
891 uint32_t reserved_17_31 : 15;
892 uint32_t otgi2csel : 1;
893 uint32_t phylpwrclksel : 1;
894 uint32_t reserved_14_14 : 1;
895 uint32_t usbtrdtim : 4;
901 uint32_t ulpi_utmi_sel : 1;
903 uint32_t toutcal : 3;
906 typedef union cvmx_usbcx_gusbcfg cvmx_usbcx_gusbcfg_t;
911 * Host All Channels Interrupt Register (HAINT)
913 * When a significant event occurs on a channel, the Host All Channels Interrupt register
914 * interrupts the application using the Host Channels Interrupt bit of the Core Interrupt
915 * register (GINTSTS.HChInt). This is shown in Interrupt . There is one interrupt bit per
916 * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the
917 * application sets and clears bits in the corresponding Host Channel-n Interrupt register.
919 union cvmx_usbcx_haint {
922 * struct cvmx_usbcx_haint_s
923 * @haint: Channel Interrupts (HAINT)
924 * One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
926 struct cvmx_usbcx_haint_s {
927 uint32_t reserved_16_31 : 16;
931 typedef union cvmx_usbcx_haint cvmx_usbcx_haint_t;
934 * cvmx_usbc#_haintmsk
936 * Host All Channels Interrupt Mask Register (HAINTMSK)
938 * The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt
939 * register to interrupt the application when an event occurs on a channel. There is one
940 * interrupt mask bit per channel, up to a maximum of 16 bits.
941 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
943 union cvmx_usbcx_haintmsk {
946 * struct cvmx_usbcx_haintmsk_s
947 * @haintmsk: Channel Interrupt Mask (HAINTMsk)
948 * One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
950 struct cvmx_usbcx_haintmsk_s {
951 uint32_t reserved_16_31 : 16;
952 uint32_t haintmsk : 16;
955 typedef union cvmx_usbcx_haintmsk cvmx_usbcx_haintmsk_t;
960 * Host Channel-n Characteristics Register (HCCHAR)
963 union cvmx_usbcx_hccharx {
966 * struct cvmx_usbcx_hccharx_s
967 * @chena: Channel Enable (ChEna)
968 * This field is set by the application and cleared by the OTG host.
969 * * 1'b0: Channel disabled
970 * * 1'b1: Channel enabled
971 * @chdis: Channel Disable (ChDis)
972 * The application sets this bit to stop transmitting/receiving data
973 * on a channel, even before the transfer for that channel is
974 * complete. The application must wait for the Channel Disabled
975 * interrupt before treating the channel as disabled.
976 * @oddfrm: Odd Frame (OddFrm)
977 * This field is set (reset) by the application to indicate that the
978 * OTG host must perform a transfer in an odd (micro)frame. This
979 * field is applicable for only periodic (isochronous and interrupt)
981 * * 1'b0: Even (micro)frame
982 * * 1'b1: Odd (micro)frame
983 * @devaddr: Device Address (DevAddr)
984 * This field selects the specific device serving as the data source
986 * @ec: Multi Count (MC) / Error Count (EC)
987 * When the Split Enable bit of the Host Channel-n Split Control
988 * register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates
989 * to the host the number of transactions that should be executed
990 * per microframe for this endpoint.
991 * * 2'b00: Reserved. This field yields undefined results.
992 * * 2'b01: 1 transaction
993 * * 2'b10: 2 transactions to be issued for this endpoint per
995 * * 2'b11: 3 transactions to be issued for this endpoint per
997 * When HCSPLTn.SpltEna is set (1'b1), this field indicates the
998 * number of immediate retries to be performed for a periodic split
999 * transactions on transaction errors. This field must be set to at
1001 * @eptype: Endpoint Type (EPType)
1002 * Indicates the transfer type selected.
1004 * * 2'b01: Isochronous
1006 * * 2'b11: Interrupt
1007 * @lspddev: Low-Speed Device (LSpdDev)
1008 * This field is set by the application to indicate that this channel is
1009 * communicating to a low-speed device.
1010 * @epdir: Endpoint Direction (EPDir)
1011 * Indicates whether the transaction is IN or OUT.
1014 * @epnum: Endpoint Number (EPNum)
1015 * Indicates the endpoint number on the device serving as the
1016 * data source or sink.
1017 * @mps: Maximum Packet Size (MPS)
1018 * Indicates the maximum packet size of the associated endpoint.
1020 struct cvmx_usbcx_hccharx_s {
1023 uint32_t oddfrm : 1;
1024 uint32_t devaddr : 7;
1026 uint32_t eptype : 2;
1027 uint32_t lspddev : 1;
1028 uint32_t reserved_16_16 : 1;
1034 typedef union cvmx_usbcx_hccharx cvmx_usbcx_hccharx_t;
1039 * Host Configuration Register (HCFG)
1041 * This register configures the core after power-on. Do not make changes to this register after initializing the host.
1043 union cvmx_usbcx_hcfg {
1046 * struct cvmx_usbcx_hcfg_s
1047 * @fslssupp: FS- and LS-Only Support (FSLSSupp)
1048 * The application uses this bit to control the core's enumeration
1049 * speed. Using this bit, the application can make the core
1050 * enumerate as a FS host, even if the connected device supports
1051 * HS traffic. Do not make changes to this field after initial
1053 * * 1'b0: HS/FS/LS, based on the maximum speed supported by
1054 * the connected device
1055 * * 1'b1: FS/LS-only, even if the connected device can support HS
1056 * @fslspclksel: FS/LS PHY Clock Select (FSLSPclkSel)
1057 * When the core is in FS Host mode
1058 * * 2'b00: PHY clock is running at 30/60 MHz
1059 * * 2'b01: PHY clock is running at 48 MHz
1060 * * Others: Reserved
1061 * When the core is in LS Host mode
1062 * * 2'b00: PHY clock is running at 30/60 MHz. When the
1063 * UTMI+/ULPI PHY Low Power mode is not selected, use
1065 * * 2'b01: PHY clock is running at 48 MHz. When the UTMI+
1066 * PHY Low Power mode is selected, use 48MHz if the PHY
1067 * supplies a 48 MHz clock during LS mode.
1068 * * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
1069 * use 6 MHz when the UTMI+ PHY Low Power mode is
1070 * selected and the PHY supplies a 6 MHz clock during LS
1071 * mode. If you select a 6 MHz clock during LS mode, you must
1075 struct cvmx_usbcx_hcfg_s {
1076 uint32_t reserved_3_31 : 29;
1077 uint32_t fslssupp : 1;
1078 uint32_t fslspclksel : 2;
1081 typedef union cvmx_usbcx_hcfg cvmx_usbcx_hcfg_t;
1086 * Host Channel-n Interrupt Register (HCINT)
1088 * This register indicates the status of a channel with respect to USB- and AHB-related events.
1089 * The application must read this register when the Host Channels Interrupt bit of the Core Interrupt
1090 * register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read
1091 * the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n
1092 * Interrupt register. The application must clear the appropriate bit in this register to clear the
1093 * corresponding bits in the HAINT and GINTSTS registers.
1095 union cvmx_usbcx_hcintx {
1098 * struct cvmx_usbcx_hcintx_s
1099 * @datatglerr: Data Toggle Error (DataTglErr)
1100 * @frmovrun: Frame Overrun (FrmOvrun)
1101 * @bblerr: Babble Error (BblErr)
1102 * @xacterr: Transaction Error (XactErr)
1103 * @nyet: NYET Response Received Interrupt (NYET)
1104 * @ack: ACK Response Received Interrupt (ACK)
1105 * @nak: NAK Response Received Interrupt (NAK)
1106 * @stall: STALL Response Received Interrupt (STALL)
1107 * @ahberr: This bit is always 0x0.
1108 * @chhltd: Channel Halted (ChHltd)
1109 * Indicates the transfer completed abnormally either because of
1110 * any USB transaction error or in response to disable request by
1112 * @xfercompl: Transfer Completed (XferCompl)
1113 * Transfer completed normally without any errors.
1115 struct cvmx_usbcx_hcintx_s {
1116 uint32_t reserved_11_31 : 21;
1117 uint32_t datatglerr : 1;
1118 uint32_t frmovrun : 1;
1119 uint32_t bblerr : 1;
1120 uint32_t xacterr : 1;
1125 uint32_t ahberr : 1;
1126 uint32_t chhltd : 1;
1127 uint32_t xfercompl : 1;
1130 typedef union cvmx_usbcx_hcintx cvmx_usbcx_hcintx_t;
1133 * cvmx_usbc#_hcintmsk#
1135 * Host Channel-n Interrupt Mask Register (HCINTMSKn)
1137 * This register reflects the mask for each channel status described in the previous section.
1138 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
1140 union cvmx_usbcx_hcintmskx {
1143 * struct cvmx_usbcx_hcintmskx_s
1144 * @datatglerrmsk: Data Toggle Error Mask (DataTglErrMsk)
1145 * @frmovrunmsk: Frame Overrun Mask (FrmOvrunMsk)
1146 * @bblerrmsk: Babble Error Mask (BblErrMsk)
1147 * @xacterrmsk: Transaction Error Mask (XactErrMsk)
1148 * @nyetmsk: NYET Response Received Interrupt Mask (NyetMsk)
1149 * @ackmsk: ACK Response Received Interrupt Mask (AckMsk)
1150 * @nakmsk: NAK Response Received Interrupt Mask (NakMsk)
1151 * @stallmsk: STALL Response Received Interrupt Mask (StallMsk)
1152 * @ahberrmsk: AHB Error Mask (AHBErrMsk)
1153 * @chhltdmsk: Channel Halted Mask (ChHltdMsk)
1154 * @xfercomplmsk: Transfer Completed Mask (XferComplMsk)
1156 struct cvmx_usbcx_hcintmskx_s {
1157 uint32_t reserved_11_31 : 21;
1158 uint32_t datatglerrmsk : 1;
1159 uint32_t frmovrunmsk : 1;
1160 uint32_t bblerrmsk : 1;
1161 uint32_t xacterrmsk : 1;
1162 uint32_t nyetmsk : 1;
1163 uint32_t ackmsk : 1;
1164 uint32_t nakmsk : 1;
1165 uint32_t stallmsk : 1;
1166 uint32_t ahberrmsk : 1;
1167 uint32_t chhltdmsk : 1;
1168 uint32_t xfercomplmsk : 1;
1171 typedef union cvmx_usbcx_hcintmskx cvmx_usbcx_hcintmskx_t;
1174 * cvmx_usbc#_hcsplt#
1176 * Host Channel-n Split Control Register (HCSPLT)
1179 union cvmx_usbcx_hcspltx {
1182 * struct cvmx_usbcx_hcspltx_s
1183 * @spltena: Split Enable (SpltEna)
1184 * The application sets this field to indicate that this channel is
1185 * enabled to perform split transactions.
1186 * @compsplt: Do Complete Split (CompSplt)
1187 * The application sets this field to request the OTG host to
1188 * perform a complete split transaction.
1189 * @xactpos: Transaction Position (XactPos)
1190 * This field is used to determine whether to send all, first, middle,
1191 * or last payloads with each OUT transaction.
1192 * * 2'b11: All. This is the entire data payload is of this transaction
1193 * (which is less than or equal to 188 bytes).
1194 * * 2'b10: Begin. This is the first data payload of this transaction
1195 * (which is larger than 188 bytes).
1196 * * 2'b00: Mid. This is the middle payload of this transaction
1197 * (which is larger than 188 bytes).
1198 * * 2'b01: End. This is the last payload of this transaction (which
1199 * is larger than 188 bytes).
1200 * @hubaddr: Hub Address (HubAddr)
1201 * This field holds the device address of the transaction
1203 * @prtaddr: Port Address (PrtAddr)
1204 * This field is the port number of the recipient transaction
1207 struct cvmx_usbcx_hcspltx_s {
1208 uint32_t spltena : 1;
1209 uint32_t reserved_17_30 : 14;
1210 uint32_t compsplt : 1;
1211 uint32_t xactpos : 2;
1212 uint32_t hubaddr : 7;
1213 uint32_t prtaddr : 7;
1216 typedef union cvmx_usbcx_hcspltx cvmx_usbcx_hcspltx_t;
1219 * cvmx_usbc#_hctsiz#
1221 * Host Channel-n Transfer Size Register (HCTSIZ)
1224 union cvmx_usbcx_hctsizx {
1227 * struct cvmx_usbcx_hctsizx_s
1228 * @dopng: Do Ping (DoPng)
1229 * Setting this field to 1 directs the host to do PING protocol.
1231 * The application programs this field with the type of PID to use
1232 * for the initial transaction. The host will maintain this field for the
1233 * rest of the transfer.
1237 * * 2'b11: MDATA (non-control)/SETUP (control)
1238 * @pktcnt: Packet Count (PktCnt)
1239 * This field is programmed by the application with the expected
1240 * number of packets to be transmitted (OUT) or received (IN).
1241 * The host decrements this count on every successful
1242 * transmission or reception of an OUT/IN packet. Once this count
1243 * reaches zero, the application is interrupted to indicate normal
1245 * @xfersize: Transfer Size (XferSize)
1246 * For an OUT, this field is the number of data bytes the host will
1247 * send during the transfer.
1248 * For an IN, this field is the buffer size that the application has
1249 * reserved for the transfer. The application is expected to
1250 * program this field as an integer multiple of the maximum packet
1251 * size for IN transactions (periodic and non-periodic).
1253 struct cvmx_usbcx_hctsizx_s {
1256 uint32_t pktcnt : 10;
1257 uint32_t xfersize : 19;
1260 typedef union cvmx_usbcx_hctsizx cvmx_usbcx_hctsizx_t;
1265 * Host Frame Interval Register (HFIR)
1267 * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated.
1269 union cvmx_usbcx_hfir {
1272 * struct cvmx_usbcx_hfir_s
1273 * @frint: Frame Interval (FrInt)
1274 * The value that the application programs to this field specifies
1275 * the interval between two consecutive SOFs (FS) or micro-
1276 * SOFs (HS) or Keep-Alive tokens (HS). This field contains the
1277 * number of PHY clocks that constitute the required frame
1278 * interval. The default value set in this field for a FS operation
1279 * when the PHY clock frequency is 60 MHz. The application can
1280 * write a value to this register only after the Port Enable bit of
1281 * the Host Port Control and Status register (HPRT.PrtEnaPort)
1282 * has been set. If no value is programmed, the core calculates
1283 * the value based on the PHY clock specified in the FS/LS PHY
1284 * Clock Select field of the Host Configuration register
1285 * (HCFG.FSLSPclkSel). Do not change the value of this field
1286 * after the initial configuration.
1287 * * 125 us (PHY clock frequency for HS)
1288 * * 1 ms (PHY clock frequency for FS/LS)
1290 struct cvmx_usbcx_hfir_s {
1291 uint32_t reserved_16_31 : 16;
1292 uint32_t frint : 16;
1295 typedef union cvmx_usbcx_hfir cvmx_usbcx_hfir_t;
1300 * Host Frame Number/Frame Time Remaining Register (HFNUM)
1302 * This register indicates the current frame number.
1303 * It also indicates the time remaining (in terms of the number of PHY clocks)
1304 * in the current (micro)frame.
1306 union cvmx_usbcx_hfnum {
1309 * struct cvmx_usbcx_hfnum_s
1310 * @frrem: Frame Time Remaining (FrRem)
1311 * Indicates the amount of time remaining in the current
1312 * microframe (HS) or frame (FS/LS), in terms of PHY clocks.
1313 * This field decrements on each PHY clock. When it reaches
1314 * zero, this field is reloaded with the value in the Frame Interval
1315 * register and a new SOF is transmitted on the USB.
1316 * @frnum: Frame Number (FrNum)
1317 * This field increments when a new SOF is transmitted on the
1318 * USB, and is reset to 0 when it reaches 16'h3FFF.
1320 struct cvmx_usbcx_hfnum_s {
1321 uint32_t frrem : 16;
1322 uint32_t frnum : 16;
1325 typedef union cvmx_usbcx_hfnum cvmx_usbcx_hfnum_t;
1330 * Host Port Control and Status Register (HPRT)
1332 * This register is available in both Host and Device modes.
1333 * Currently, the OTG Host supports only one port.
1334 * A single register holds USB port-related information such as USB reset, enable, suspend, resume,
1335 * connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an
1336 * interrupt to the application through the Host Port Interrupt bit of the Core Interrupt
1337 * register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear
1338 * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit
1339 * to clear the interrupt.
1341 union cvmx_usbcx_hprt {
1344 * struct cvmx_usbcx_hprt_s
1345 * @prtspd: Port Speed (PrtSpd)
1346 * Indicates the speed of the device attached to this port.
1347 * * 2'b00: High speed
1348 * * 2'b01: Full speed
1349 * * 2'b10: Low speed
1351 * @prttstctl: Port Test Control (PrtTstCtl)
1352 * The application writes a nonzero value to this field to put
1353 * the port into a Test mode, and the corresponding pattern is
1354 * signaled on the port.
1355 * * 4'b0000: Test mode disabled
1356 * * 4'b0001: Test_J mode
1357 * * 4'b0010: Test_K mode
1358 * * 4'b0011: Test_SE0_NAK mode
1359 * * 4'b0100: Test_Packet mode
1360 * * 4'b0101: Test_Force_Enable
1361 * * Others: Reserved
1362 * PrtSpd must be zero (i.e. the interface must be in high-speed
1363 * mode) to use the PrtTstCtl test modes.
1364 * @prtpwr: Port Power (PrtPwr)
1365 * The application uses this field to control power to this port,
1366 * and the core clears this bit on an overcurrent condition.
1369 * @prtlnsts: Port Line Status (PrtLnSts)
1370 * Indicates the current logic level USB data lines
1371 * * Bit [10]: Logic level of D-
1372 * * Bit [11]: Logic level of D+
1373 * @prtrst: Port Reset (PrtRst)
1374 * When the application sets this bit, a reset sequence is
1375 * started on this port. The application must time the reset
1376 * period and clear this bit after the reset sequence is
1378 * * 1'b0: Port not in reset
1379 * * 1'b1: Port in reset
1380 * The application must leave this bit set for at least a
1381 * minimum duration mentioned below to start a reset on the
1382 * port. The application can leave it set for another 10 ms in
1383 * addition to the required minimum duration, before clearing
1384 * the bit, even though there is no maximum limit set by the
1386 * * High speed: 50 ms
1387 * * Full speed/Low speed: 10 ms
1388 * @prtsusp: Port Suspend (PrtSusp)
1389 * The application sets this bit to put this port in Suspend
1390 * mode. The core only stops sending SOFs when this is set.
1391 * To stop the PHY clock, the application must set the Port
1392 * Clock Stop bit, which will assert the suspend input pin of
1394 * The read value of this bit reflects the current suspend
1395 * status of the port. This bit is cleared by the core after a
1396 * remote wakeup signal is detected or the application sets
1397 * the Port Reset bit or Port Resume bit in this register or the
1398 * Resume/Remote Wakeup Detected Interrupt bit or
1399 * Disconnect Detected Interrupt bit in the Core Interrupt
1400 * register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
1402 * * 1'b0: Port not in Suspend mode
1403 * * 1'b1: Port in Suspend mode
1404 * @prtres: Port Resume (PrtRes)
1405 * The application sets this bit to drive resume signaling on
1406 * the port. The core continues to drive the resume signal
1407 * until the application clears this bit.
1408 * If the core detects a USB remote wakeup sequence, as
1409 * indicated by the Port Resume/Remote Wakeup Detected
1410 * Interrupt bit of the Core Interrupt register
1411 * (GINTSTS.WkUpInt), the core starts driving resume
1412 * signaling without application intervention and clears this bit
1413 * when it detects a disconnect condition. The read value of
1414 * this bit indicates whether the core is currently driving
1416 * * 1'b0: No resume driven
1417 * * 1'b1: Resume driven
1418 * @prtovrcurrchng: Port Overcurrent Change (PrtOvrCurrChng)
1419 * The core sets this bit when the status of the Port
1420 * Overcurrent Active bit (bit 4) in this register changes.
1421 * @prtovrcurract: Port Overcurrent Active (PrtOvrCurrAct)
1422 * Indicates the overcurrent condition of the port.
1423 * * 1'b0: No overcurrent condition
1424 * * 1'b1: Overcurrent condition
1425 * @prtenchng: Port Enable/Disable Change (PrtEnChng)
1426 * The core sets this bit when the status of the Port Enable bit
1427 * [2] of this register changes.
1428 * @prtena: Port Enable (PrtEna)
1429 * A port is enabled only by the core after a reset sequence,
1430 * and is disabled by an overcurrent condition, a disconnect
1431 * condition, or by the application clearing this bit. The
1432 * application cannot set this bit by a register write. It can only
1433 * clear it to disable the port. This bit does not trigger any
1434 * interrupt to the application.
1435 * * 1'b0: Port disabled
1436 * * 1'b1: Port enabled
1437 * @prtconndet: Port Connect Detected (PrtConnDet)
1438 * The core sets this bit when a device connection is detected
1439 * to trigger an interrupt to the application using the Host Port
1440 * Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
1441 * The application must write a 1 to this bit to clear the
1443 * @prtconnsts: Port Connect Status (PrtConnSts)
1444 * * 0: No device is attached to the port.
1445 * * 1: A device is attached to the port.
1447 struct cvmx_usbcx_hprt_s {
1448 uint32_t reserved_19_31 : 13;
1449 uint32_t prtspd : 2;
1450 uint32_t prttstctl : 4;
1451 uint32_t prtpwr : 1;
1452 uint32_t prtlnsts : 2;
1453 uint32_t reserved_9_9 : 1;
1454 uint32_t prtrst : 1;
1455 uint32_t prtsusp : 1;
1456 uint32_t prtres : 1;
1457 uint32_t prtovrcurrchng : 1;
1458 uint32_t prtovrcurract : 1;
1459 uint32_t prtenchng : 1;
1460 uint32_t prtena : 1;
1461 uint32_t prtconndet : 1;
1462 uint32_t prtconnsts : 1;
1465 typedef union cvmx_usbcx_hprt cvmx_usbcx_hprt_t;
1468 * cvmx_usbc#_hptxfsiz
1470 * Host Periodic Transmit FIFO Size Register (HPTXFSIZ)
1472 * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311.
1474 union cvmx_usbcx_hptxfsiz {
1477 * struct cvmx_usbcx_hptxfsiz_s
1478 * @ptxfsize: Host Periodic TxFIFO Depth (PTxFSize)
1479 * This value is in terms of 32-bit words.
1480 * * Minimum value is 16
1481 * * Maximum value is 32768
1482 * @ptxfstaddr: Host Periodic TxFIFO Start Address (PTxFStAddr)
1484 struct cvmx_usbcx_hptxfsiz_s {
1485 uint32_t ptxfsize : 16;
1486 uint32_t ptxfstaddr : 16;
1489 typedef union cvmx_usbcx_hptxfsiz cvmx_usbcx_hptxfsiz_t;
1492 * cvmx_usbc#_hptxsts
1494 * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS)
1496 * This read-only register contains the free space information for the Periodic TxFIFO and
1497 * the Periodic Transmit Request Queue
1499 union cvmx_usbcx_hptxsts {
1502 * struct cvmx_usbcx_hptxsts_s
1503 * @ptxqtop: Top of the Periodic Transmit Request Queue (PTxQTop)
1504 * This indicates the entry in the Periodic Tx Request Queue that
1505 * is currently being processes by the MAC.
1506 * This register is used for debugging.
1507 * * Bit [31]: Odd/Even (micro)frame
1508 * - 1'b0: send in even (micro)frame
1509 * - 1'b1: send in odd (micro)frame
1510 * * Bits [30:27]: Channel/endpoint number
1511 * * Bits [26:25]: Type
1513 * - 2'b01: Zero-length packet
1515 * - 2'b11: Disable channel command
1516 * * Bit [24]: Terminate (last entry for the selected
1518 * @ptxqspcavail: Periodic Transmit Request Queue Space Available
1520 * Indicates the number of free locations available to be written in
1521 * the Periodic Transmit Request Queue. This queue holds both
1522 * IN and OUT requests.
1523 * * 8'h0: Periodic Transmit Request Queue is full
1524 * * 8'h1: 1 location available
1525 * * 8'h2: 2 locations available
1526 * * n: n locations available (0..8)
1527 * * Others: Reserved
1528 * @ptxfspcavail: Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)
1529 * Indicates the number of free locations available to be written to
1530 * in the Periodic TxFIFO.
1531 * Values are in terms of 32-bit words
1532 * * 16'h0: Periodic TxFIFO is full
1533 * * 16'h1: 1 word available
1534 * * 16'h2: 2 words available
1535 * * 16'hn: n words available (where 0..32768)
1536 * * 16'h8000: 32768 words available
1537 * * Others: Reserved
1539 struct cvmx_usbcx_hptxsts_s {
1540 uint32_t ptxqtop : 8;
1541 uint32_t ptxqspcavail : 8;
1542 uint32_t ptxfspcavail : 16;
1545 typedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t;