drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 void
 113 intel_edp_link_config(struct intel_encoder *intel_encoder,
 114                        int *lane_num, int *link_bw)
 115 {
 116         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 117
 118         *lane_num = intel_dp->lane_count;
 119         *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 120 }
 121
 122 int
 123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 124                        struct drm_display_mode *mode)
 125 {
 126         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 127         struct intel_connector *intel_connector = intel_dp->attached_connector;
 128
 129         if (intel_connector->panel.fixed_mode)
 130                 return intel_connector->panel.fixed_mode->clock;
 131         else
 132                 return mode->clock;
 133 }
 134
 135 static int
 136 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 137 {
 138         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 139
 140         switch (max_link_bw) {
 141         case DP_LINK_BW_1_62:
 142         case DP_LINK_BW_2_7:
 143                 break;
 144         default:
 145                 max_link_bw = DP_LINK_BW_1_62;
 146                 break;
 147         }
 148         return max_link_bw;
 149 }
 150
 151 /*
 152  * The units on the numbers in the next two are... bizarre.  Examples will
 153  * make it clearer; this one parallels an example in the eDP spec.
 154  *
 155  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 156  *
 157  *     270000 * 1 * 8 / 10 == 216000
 158  *
 159  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 160  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 161  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 162  * 119000.  At 18bpp that's 2142000 kilobits per second.
 163  *
 164  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 165  * get the result in decakilobits instead of kilobits.
 166  */
 167
 168 static int
 169 intel_dp_link_required(int pixel_clock, int bpp)
 170 {
 171         return (pixel_clock * bpp + 9) / 10;
 172 }
 173
 174 static int
 175 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 176 {
 177         return (max_link_clock * max_lanes * 8) / 10;
 178 }
 179
 180 static bool
 181 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 182                           struct drm_display_mode *mode,
 183                           bool adjust_mode)
 184 {
 185         int max_link_clock =
 186                 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 187         int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 188         int max_rate, mode_rate;
 189
 190         mode_rate = intel_dp_link_required(mode->clock, 24);
 191         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 192
 193         if (mode_rate > max_rate) {
 194                 mode_rate = intel_dp_link_required(mode->clock, 18);
 195                 if (mode_rate > max_rate)
 196                         return false;
 197
 198                 if (adjust_mode)
 199                         mode->private_flags
 200                                 |= INTEL_MODE_DP_FORCE_6BPC;
 201
 202                 return true;
 203         }
 204
 205         return true;
 206 }
 207
 208 static int
 209 intel_dp_mode_valid(struct drm_connector *connector,
 210                     struct drm_display_mode *mode)
 211 {
 212         struct intel_dp *intel_dp = intel_attached_dp(connector);
 213         struct intel_connector *intel_connector = to_intel_connector(connector);
 214         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 215
 216         if (is_edp(intel_dp) && fixed_mode) {
 217                 if (mode->hdisplay > fixed_mode->hdisplay)
 218                         return MODE_PANEL;
 219
 220                 if (mode->vdisplay > fixed_mode->vdisplay)
 221                         return MODE_PANEL;
 222         }
 223
 224         if (!intel_dp_adjust_dithering(intel_dp, mode, false))
 225                 return MODE_CLOCK_HIGH;
 226
 227         if (mode->clock < 10000)
 228                 return MODE_CLOCK_LOW;
 229
 230         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 231                 return MODE_H_ILLEGAL;
 232
 233         return MODE_OK;
 234 }
 235
 236 static uint32_t
 237 pack_aux(uint8_t *src, int src_bytes)
 238 {
 239         int     i;
 240         uint32_t v = 0;
 241
 242         if (src_bytes > 4)
 243                 src_bytes = 4;
 244         for (i = 0; i < src_bytes; i++)
 245                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 246         return v;
 247 }
 248
 249 static void
 250 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 251 {
 252         int i;
 253         if (dst_bytes > 4)
 254                 dst_bytes = 4;
 255         for (i = 0; i < dst_bytes; i++)
 256                 dst[i] = src >> ((3-i) * 8);
 257 }
 258
 259 /* hrawclock is 1/4 the FSB frequency */
 260 static int
 261 intel_hrawclk(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         uint32_t clkcfg;
 265
 266         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 267         if (IS_VALLEYVIEW(dev))
 268                 return 200;
 269
 270         clkcfg = I915_READ(CLKCFG);
 271         switch (clkcfg & CLKCFG_FSB_MASK) {
 272         case CLKCFG_FSB_400:
 273                 return 100;
 274         case CLKCFG_FSB_533:
 275                 return 133;
 276         case CLKCFG_FSB_667:
 277                 return 166;
 278         case CLKCFG_FSB_800:
 279                 return 200;
 280         case CLKCFG_FSB_1067:
 281                 return 266;
 282         case CLKCFG_FSB_1333:
 283                 return 333;
 284         /* these two are just a guess; one of them might be right */
 285         case CLKCFG_FSB_1600:
 286         case CLKCFG_FSB_1600_ALT:
 287                 return 400;
 288         default:
 289                 return 133;
 290         }
 291 }
 292
 293 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 294 {
 295         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 296         struct drm_i915_private *dev_priv = dev->dev_private;
 297
 298         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 299 }
 300
 301 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 302 {
 303         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 304         struct drm_i915_private *dev_priv = dev->dev_private;
 305
 306         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 307 }
 308
 309 static void
 310 intel_dp_check_edp(struct intel_dp *intel_dp)
 311 {
 312         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314
 315         if (!is_edp(intel_dp))
 316                 return;
 317         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 318                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 319                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 320                               I915_READ(PCH_PP_STATUS),
 321                               I915_READ(PCH_PP_CONTROL));
 322         }
 323 }
 324
 325 static uint32_t
 326 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 327 {
 328         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 329         struct drm_device *dev = intel_dig_port->base.base.dev;
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331         uint32_t ch_ctl = intel_dp->output_reg + 0x10;
 332         uint32_t status;
 333         bool done;
 334
 335         if (IS_HASWELL(dev)) {
 336                 switch (intel_dig_port->port) {
 337                 case PORT_A:
 338                         ch_ctl = DPA_AUX_CH_CTL;
 339                         break;
 340                 case PORT_B:
 341                         ch_ctl = PCH_DPB_AUX_CH_CTL;
 342                         break;
 343                 case PORT_C:
 344                         ch_ctl = PCH_DPC_AUX_CH_CTL;
 345                         break;
 346                 case PORT_D:
 347                         ch_ctl = PCH_DPD_AUX_CH_CTL;
 348                         break;
 349                 default:
 350                         BUG();
 351                 }
 352         }
 353
 354 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 355         if (has_aux_irq)
 356                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
 357         else
 358                 done = wait_for_atomic(C, 10) == 0;
 359         if (!done)
 360                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 361                           has_aux_irq);
 362 #undef C
 363
 364         return status;
 365 }
 366
 367 static int
 368 intel_dp_aux_ch(struct intel_dp *intel_dp,
 369                 uint8_t *send, int send_bytes,
 370                 uint8_t *recv, int recv_size)
 371 {
 372         uint32_t output_reg = intel_dp->output_reg;
 373         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 374         struct drm_device *dev = intel_dig_port->base.base.dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376         uint32_t ch_ctl = output_reg + 0x10;
 377         uint32_t ch_data = ch_ctl + 4;
 378         int i, ret, recv_bytes;
 379         uint32_t status;
 380         uint32_t aux_clock_divider;
 381         int try, precharge;
 382         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 383
 384         /* dp aux is extremely sensitive to irq latency, hence request the
 385          * lowest possible wakeup latency and so prevent the cpu from going into
 386          * deep sleep states.
 387          */
 388         pm_qos_update_request(&dev_priv->pm_qos, 0);
 389
 390         if (IS_HASWELL(dev)) {
 391                 switch (intel_dig_port->port) {
 392                 case PORT_A:
 393                         ch_ctl = DPA_AUX_CH_CTL;
 394                         ch_data = DPA_AUX_CH_DATA1;
 395                         break;
 396                 case PORT_B:
 397                         ch_ctl = PCH_DPB_AUX_CH_CTL;
 398                         ch_data = PCH_DPB_AUX_CH_DATA1;
 399                         break;
 400                 case PORT_C:
 401                         ch_ctl = PCH_DPC_AUX_CH_CTL;
 402                         ch_data = PCH_DPC_AUX_CH_DATA1;
 403                         break;
 404                 case PORT_D:
 405                         ch_ctl = PCH_DPD_AUX_CH_CTL;
 406                         ch_data = PCH_DPD_AUX_CH_DATA1;
 407                         break;
 408                 default:
 409                         BUG();
 410                 }
 411         }
 412
 413         intel_dp_check_edp(intel_dp);
 414         /* The clock divider is based off the hrawclk,
 415          * and would like to run at 2MHz. So, take the
 416          * hrawclk value and divide by 2 and use that
 417          *
 418          * Note that PCH attached eDP panels should use a 125MHz input
 419          * clock divider.
 420          */
 421         if (is_cpu_edp(intel_dp)) {
 422                 if (HAS_DDI(dev))
 423                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 424                 else if (IS_VALLEYVIEW(dev))
 425                         aux_clock_divider = 100;
 426                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 427                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 428                 else
 429                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 430         } else if (HAS_PCH_SPLIT(dev))
 431                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 432         else
 433                 aux_clock_divider = intel_hrawclk(dev) / 2;
 434
 435         if (IS_GEN6(dev))
 436                 precharge = 3;
 437         else
 438                 precharge = 5;
 439
 440         /* Try to wait for any previous AUX channel activity */
 441         for (try = 0; try < 3; try++) {
 442                 status = I915_READ_NOTRACE(ch_ctl);
 443                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 444                         break;
 445                 msleep(1);
 446         }
 447
 448         if (try == 3) {
 449                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 450                      I915_READ(ch_ctl));
 451                 ret = -EBUSY;
 452                 goto out;
 453         }
 454
 455         /* Must try at least 3 times according to DP spec */
 456         for (try = 0; try < 5; try++) {
 457                 /* Load the send data into the aux channel data registers */
 458                 for (i = 0; i < send_bytes; i += 4)
 459                         I915_WRITE(ch_data + i,
 460                                    pack_aux(send + i, send_bytes - i));
 461
 462                 /* Send the command and wait for it to complete */
 463                 I915_WRITE(ch_ctl,
 464                            DP_AUX_CH_CTL_SEND_BUSY |
 465                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 466                            DP_AUX_CH_CTL_TIME_OUT_400us |
 467                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 468                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 469                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 470                            DP_AUX_CH_CTL_DONE |
 471                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 472                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 473
 474                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 475
 476                 /* Clear done status and any errors */
 477                 I915_WRITE(ch_ctl,
 478                            status |
 479                            DP_AUX_CH_CTL_DONE |
 480                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 481                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 482
 483                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 484                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 485                         continue;
 486                 if (status & DP_AUX_CH_CTL_DONE)
 487                         break;
 488         }
 489
 490         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 491                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 492                 ret = -EBUSY;
 493                 goto out;
 494         }
 495
 496         /* Check for timeout or receive error.
 497          * Timeouts occur when the sink is not connected
 498          */
 499         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 500                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 501                 ret = -EIO;
 502                 goto out;
 503         }
 504
 505         /* Timeouts occur when the device isn't connected, so they're
 506          * "normal" -- don't fill the kernel log with these */
 507         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 508                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 509                 ret = -ETIMEDOUT;
 510                 goto out;
 511         }
 512
 513         /* Unload any bytes sent back from the other side */
 514         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 515                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 516         if (recv_bytes > recv_size)
 517                 recv_bytes = recv_size;
 518
 519         for (i = 0; i < recv_bytes; i += 4)
 520                 unpack_aux(I915_READ(ch_data + i),
 521                            recv + i, recv_bytes - i);
 522
 523         ret = recv_bytes;
 524 out:
 525         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 526
 527         return ret;
 528 }
 529
 530 /* Write data to the aux channel in native mode */
 531 static int
 532 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 533                           uint16_t address, uint8_t *send, int send_bytes)
 534 {
 535         int ret;
 536         uint8_t msg[20];
 537         int msg_bytes;
 538         uint8_t ack;
 539
 540         intel_dp_check_edp(intel_dp);
 541         if (send_bytes > 16)
 542                 return -1;
 543         msg[0] = AUX_NATIVE_WRITE << 4;
 544         msg[1] = address >> 8;
 545         msg[2] = address & 0xff;
 546         msg[3] = send_bytes - 1;
 547         memcpy(&msg[4], send, send_bytes);
 548         msg_bytes = send_bytes + 4;
 549         for (;;) {
 550                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 551                 if (ret < 0)
 552                         return ret;
 553                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 554                         break;
 555                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 556                         udelay(100);
 557                 else
 558                         return -EIO;
 559         }
 560         return send_bytes;
 561 }
 562
 563 /* Write a single byte to the aux channel in native mode */
 564 static int
 565 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 566                             uint16_t address, uint8_t byte)
 567 {
 568         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 569 }
 570
 571 /* read bytes from a native aux channel */
 572 static int
 573 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 574                          uint16_t address, uint8_t *recv, int recv_bytes)
 575 {
 576         uint8_t msg[4];
 577         int msg_bytes;
 578         uint8_t reply[20];
 579         int reply_bytes;
 580         uint8_t ack;
 581         int ret;
 582
 583         intel_dp_check_edp(intel_dp);
 584         msg[0] = AUX_NATIVE_READ << 4;
 585         msg[1] = address >> 8;
 586         msg[2] = address & 0xff;
 587         msg[3] = recv_bytes - 1;
 588
 589         msg_bytes = 4;
 590         reply_bytes = recv_bytes + 1;
 591
 592         for (;;) {
 593                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 594                                       reply, reply_bytes);
 595                 if (ret == 0)
 596                         return -EPROTO;
 597                 if (ret < 0)
 598                         return ret;
 599                 ack = reply[0];
 600                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 601                         memcpy(recv, reply + 1, ret - 1);
 602                         return ret - 1;
 603                 }
 604                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 605                         udelay(100);
 606                 else
 607                         return -EIO;
 608         }
 609 }
 610
 611 static int
 612 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 613                     uint8_t write_byte, uint8_t *read_byte)
 614 {
 615         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 616         struct intel_dp *intel_dp = container_of(adapter,
 617                                                 struct intel_dp,
 618                                                 adapter);
 619         uint16_t address = algo_data->address;
 620         uint8_t msg[5];
 621         uint8_t reply[2];
 622         unsigned retry;
 623         int msg_bytes;
 624         int reply_bytes;
 625         int ret;
 626
 627         intel_dp_check_edp(intel_dp);
 628         /* Set up the command byte */
 629         if (mode & MODE_I2C_READ)
 630                 msg[0] = AUX_I2C_READ << 4;
 631         else
 632                 msg[0] = AUX_I2C_WRITE << 4;
 633
 634         if (!(mode & MODE_I2C_STOP))
 635                 msg[0] |= AUX_I2C_MOT << 4;
 636
 637         msg[1] = address >> 8;
 638         msg[2] = address;
 639
 640         switch (mode) {
 641         case MODE_I2C_WRITE:
 642                 msg[3] = 0;
 643                 msg[4] = write_byte;
 644                 msg_bytes = 5;
 645                 reply_bytes = 1;
 646                 break;
 647         case MODE_I2C_READ:
 648                 msg[3] = 0;
 649                 msg_bytes = 4;
 650                 reply_bytes = 2;
 651                 break;
 652         default:
 653                 msg_bytes = 3;
 654                 reply_bytes = 1;
 655                 break;
 656         }
 657
 658         for (retry = 0; retry < 5; retry++) {
 659                 ret = intel_dp_aux_ch(intel_dp,
 660                                       msg, msg_bytes,
 661                                       reply, reply_bytes);
 662                 if (ret < 0) {
 663                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 664                         return ret;
 665                 }
 666
 667                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 668                 case AUX_NATIVE_REPLY_ACK:
 669                         /* I2C-over-AUX Reply field is only valid
 670                          * when paired with AUX ACK.
 671                          */
 672                         break;
 673                 case AUX_NATIVE_REPLY_NACK:
 674                         DRM_DEBUG_KMS("aux_ch native nack\n");
 675                         return -EREMOTEIO;
 676                 case AUX_NATIVE_REPLY_DEFER:
 677                         udelay(100);
 678                         continue;
 679                 default:
 680                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 681                                   reply[0]);
 682                         return -EREMOTEIO;
 683                 }
 684
 685                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 686                 case AUX_I2C_REPLY_ACK:
 687                         if (mode == MODE_I2C_READ) {
 688                                 *read_byte = reply[1];
 689                         }
 690                         return reply_bytes - 1;
 691                 case AUX_I2C_REPLY_NACK:
 692                         DRM_DEBUG_KMS("aux_i2c nack\n");
 693                         return -EREMOTEIO;
 694                 case AUX_I2C_REPLY_DEFER:
 695                         DRM_DEBUG_KMS("aux_i2c defer\n");
 696                         udelay(100);
 697                         break;
 698                 default:
 699                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 700                         return -EREMOTEIO;
 701                 }
 702         }
 703
 704         DRM_ERROR("too many retries, giving up\n");
 705         return -EREMOTEIO;
 706 }
 707
 708 static int
 709 intel_dp_i2c_init(struct intel_dp *intel_dp,
 710                   struct intel_connector *intel_connector, const char *name)
 711 {
 712         int     ret;
 713
 714         DRM_DEBUG_KMS("i2c_init %s\n", name);
 715         intel_dp->algo.running = false;
 716         intel_dp->algo.address = 0;
 717         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 718
 719         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 720         intel_dp->adapter.owner = THIS_MODULE;
 721         intel_dp->adapter.class = I2C_CLASS_DDC;
 722         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 723         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 724         intel_dp->adapter.algo_data = &intel_dp->algo;
 725         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 726
 727         ironlake_edp_panel_vdd_on(intel_dp);
 728         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 729         ironlake_edp_panel_vdd_off(intel_dp, false);
 730         return ret;
 731 }
 732
 733 bool
 734 intel_dp_mode_fixup(struct drm_encoder *encoder,
 735                     const struct drm_display_mode *mode,
 736                     struct drm_display_mode *adjusted_mode)
 737 {
 738         struct drm_device *dev = encoder->dev;
 739         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 740         struct intel_connector *intel_connector = intel_dp->attached_connector;
 741         int lane_count, clock;
 742         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 743         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 744         int bpp, mode_rate;
 745         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 746
 747         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 748                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 749                                        adjusted_mode);
 750                 intel_pch_panel_fitting(dev,
 751                                         intel_connector->panel.fitting_mode,
 752                                         mode, adjusted_mode);
 753         }
 754
 755         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 756                 return false;
 757
 758         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 759                       "max bw %02x pixel clock %iKHz\n",
 760                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 761
 762         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
 763                 return false;
 764
 765         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 766         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 767
 768         for (clock = 0; clock <= max_clock; clock++) {
 769                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 770                         int link_bw_clock =
 771                                 drm_dp_bw_code_to_link_rate(bws[clock]);
 772                         int link_avail = intel_dp_max_data_rate(link_bw_clock,
 773                                                                 lane_count);
 774
 775                         if (mode_rate <= link_avail) {
 776                                 intel_dp->link_bw = bws[clock];
 777                                 intel_dp->lane_count = lane_count;
 778                                 adjusted_mode->clock = link_bw_clock;
 779                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 780                                                 "count %d clock %d bpp %d\n",
 781                                        intel_dp->link_bw, intel_dp->lane_count,
 782                                        adjusted_mode->clock, bpp);
 783                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 784                                               mode_rate, link_avail);
 785                                 return true;
 786                         }
 787                 }
 788         }
 789
 790         return false;
 791 }
 792
 793 void
 794 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 795                  struct drm_display_mode *adjusted_mode)
 796 {
 797         struct drm_device *dev = crtc->dev;
 798         struct intel_encoder *intel_encoder;
 799         struct intel_dp *intel_dp;
 800         struct drm_i915_private *dev_priv = dev->dev_private;
 801         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 802         int lane_count = 4;
 803         struct intel_link_m_n m_n;
 804         int pipe = intel_crtc->pipe;
 805         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 806
 807         /*
 808          * Find the lane count in the intel_encoder private
 809          */
 810         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 811                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
 812
 813                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 814                     intel_encoder->type == INTEL_OUTPUT_EDP)
 815                 {
 816                         lane_count = intel_dp->lane_count;
 817                         break;
 818                 }
 819         }
 820
 821         /*
 822          * Compute the GMCH and Link ratios. The '3' here is
 823          * the number of bytes_per_pixel post-LUT, which we always
 824          * set up for 8-bits of R/G/B, or 3 bytes total.
 825          */
 826         intel_link_compute_m_n(intel_crtc->bpp, lane_count,
 827                                mode->clock, adjusted_mode->clock, &m_n);
 828
 829         if (IS_HASWELL(dev)) {
 830                 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
 831                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 832                 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
 833                 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
 834                 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 835         } else if (HAS_PCH_SPLIT(dev)) {
 836                 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 837                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 838                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 839                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 840         } else if (IS_VALLEYVIEW(dev)) {
 841                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 842                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 843                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 844                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 845         } else {
 846                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 847                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 848                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 849                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 850                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 851         }
 852 }
 853
 854 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 855 {
 856         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 857         intel_dp->link_configuration[0] = intel_dp->link_bw;
 858         intel_dp->link_configuration[1] = intel_dp->lane_count;
 859         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 860         /*
 861          * Check for DPCD version > 1.1 and enhanced framing support
 862          */
 863         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 864             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 865                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 866         }
 867 }
 868
 869 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 870 {
 871         struct drm_device *dev = crtc->dev;
 872         struct drm_i915_private *dev_priv = dev->dev_private;
 873         u32 dpa_ctl;
 874
 875         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 876         dpa_ctl = I915_READ(DP_A);
 877         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 878
 879         if (clock < 200000) {
 880                 /* For a long time we've carried around a ILK-DevA w/a for the
 881                  * 160MHz clock. If we're really unlucky, it's still required.
 882                  */
 883                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 884                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 885         } else {
 886                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 887         }
 888
 889         I915_WRITE(DP_A, dpa_ctl);
 890
 891         POSTING_READ(DP_A);
 892         udelay(500);
 893 }
 894
 895 static void
 896 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 897                   struct drm_display_mode *adjusted_mode)
 898 {
 899         struct drm_device *dev = encoder->dev;
 900         struct drm_i915_private *dev_priv = dev->dev_private;
 901         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 902         struct drm_crtc *crtc = encoder->crtc;
 903         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 904
 905         /*
 906          * There are four kinds of DP registers:
 907          *
 908          *      IBX PCH
 909          *      SNB CPU
 910          *      IVB CPU
 911          *      CPT PCH
 912          *
 913          * IBX PCH and CPU are the same for almost everything,
 914          * except that the CPU DP PLL is configured in this
 915          * register
 916          *
 917          * CPT PCH is quite different, having many bits moved
 918          * to the TRANS_DP_CTL register instead. That
 919          * configuration happens (oddly) in ironlake_pch_enable
 920          */
 921
 922         /* Preserve the BIOS-computed detected bit. This is
 923          * supposed to be read-only.
 924          */
 925         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 926
 927         /* Handle DP bits in common between all three register formats */
 928         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 929
 930         switch (intel_dp->lane_count) {
 931         case 1:
 932                 intel_dp->DP |= DP_PORT_WIDTH_1;
 933                 break;
 934         case 2:
 935                 intel_dp->DP |= DP_PORT_WIDTH_2;
 936                 break;
 937         case 4:
 938                 intel_dp->DP |= DP_PORT_WIDTH_4;
 939                 break;
 940         }
 941         if (intel_dp->has_audio) {
 942                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 943                                  pipe_name(intel_crtc->pipe));
 944                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 945                 intel_write_eld(encoder, adjusted_mode);
 946         }
 947
 948         intel_dp_init_link_config(intel_dp);
 949
 950         /* Split out the IBX/CPU vs CPT settings */
 951
 952         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 953                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 954                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 955                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 956                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 957                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 958
 959                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 960                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 961
 962                 intel_dp->DP |= intel_crtc->pipe << 29;
 963
 964                 /* don't miss out required setting for eDP */
 965                 if (adjusted_mode->clock < 200000)
 966                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 967                 else
 968                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 969         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 970                 intel_dp->DP |= intel_dp->color_range;
 971
 972                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 973                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 974                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 975                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 976                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 977
 978                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 979                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 980
 981                 if (intel_crtc->pipe == 1)
 982                         intel_dp->DP |= DP_PIPEB_SELECT;
 983
 984                 if (is_cpu_edp(intel_dp)) {
 985                         /* don't miss out required setting for eDP */
 986                         if (adjusted_mode->clock < 200000)
 987                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 988                         else
 989                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 990                 }
 991         } else {
 992                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 993         }
 994
 995         if (is_cpu_edp(intel_dp))
 996                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 997 }
 998
 999 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1000 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1001
1002 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1003 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1004
1005 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1006 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1007
1008 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1009                                        u32 mask,
1010                                        u32 value)
1011 {
1012         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1013         struct drm_i915_private *dev_priv = dev->dev_private;
1014
1015         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1016                       mask, value,
1017                       I915_READ(PCH_PP_STATUS),
1018                       I915_READ(PCH_PP_CONTROL));
1019
1020         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1021                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1022                           I915_READ(PCH_PP_STATUS),
1023                           I915_READ(PCH_PP_CONTROL));
1024         }
1025 }
1026
1027 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1028 {
1029         DRM_DEBUG_KMS("Wait for panel power on\n");
1030         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1031 }
1032
1033 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1034 {
1035         DRM_DEBUG_KMS("Wait for panel power off time\n");
1036         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1037 }
1038
1039 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1040 {
1041         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1042         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1043 }
1044
1045
1046 /* Read the current pp_control value, unlocking the register if it
1047  * is locked
1048  */
1049
1050 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1051 {
1052         u32     control = I915_READ(PCH_PP_CONTROL);
1053
1054         control &= ~PANEL_UNLOCK_MASK;
1055         control |= PANEL_UNLOCK_REGS;
1056         return control;
1057 }
1058
1059 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1060 {
1061         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1062         struct drm_i915_private *dev_priv = dev->dev_private;
1063         u32 pp;
1064
1065         if (!is_edp(intel_dp))
1066                 return;
1067         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1068
1069         WARN(intel_dp->want_panel_vdd,
1070              "eDP VDD already requested on\n");
1071
1072         intel_dp->want_panel_vdd = true;
1073
1074         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1075                 DRM_DEBUG_KMS("eDP VDD already on\n");
1076                 return;
1077         }
1078
1079         if (!ironlake_edp_have_panel_power(intel_dp))
1080                 ironlake_wait_panel_power_cycle(intel_dp);
1081
1082         pp = ironlake_get_pp_control(dev_priv);
1083         pp |= EDP_FORCE_VDD;
1084         I915_WRITE(PCH_PP_CONTROL, pp);
1085         POSTING_READ(PCH_PP_CONTROL);
1086         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1087                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1088
1089         /*
1090          * If the panel wasn't on, delay before accessing aux channel
1091          */
1092         if (!ironlake_edp_have_panel_power(intel_dp)) {
1093                 DRM_DEBUG_KMS("eDP was not running\n");
1094                 msleep(intel_dp->panel_power_up_delay);
1095         }
1096 }
1097
1098 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1099 {
1100         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1101         struct drm_i915_private *dev_priv = dev->dev_private;
1102         u32 pp;
1103
1104         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1105                 pp = ironlake_get_pp_control(dev_priv);
1106                 pp &= ~EDP_FORCE_VDD;
1107                 I915_WRITE(PCH_PP_CONTROL, pp);
1108                 POSTING_READ(PCH_PP_CONTROL);
1109
1110                 /* Make sure sequencer is idle before allowing subsequent activity */
1111                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1112                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1113
1114                 msleep(intel_dp->panel_power_down_delay);
1115         }
1116 }
1117
1118 static void ironlake_panel_vdd_work(struct work_struct *__work)
1119 {
1120         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1121                                                  struct intel_dp, panel_vdd_work);
1122         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1123
1124         mutex_lock(&dev->mode_config.mutex);
1125         ironlake_panel_vdd_off_sync(intel_dp);
1126         mutex_unlock(&dev->mode_config.mutex);
1127 }
1128
1129 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1130 {
1131         if (!is_edp(intel_dp))
1132                 return;
1133
1134         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1135         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1136
1137         intel_dp->want_panel_vdd = false;
1138
1139         if (sync) {
1140                 ironlake_panel_vdd_off_sync(intel_dp);
1141         } else {
1142                 /*
1143                  * Queue the timer to fire a long
1144                  * time from now (relative to the power down delay)
1145                  * to keep the panel power up across a sequence of operations
1146                  */
1147                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1148                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1149         }
1150 }
1151
1152 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1153 {
1154         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1155         struct drm_i915_private *dev_priv = dev->dev_private;
1156         u32 pp;
1157
1158         if (!is_edp(intel_dp))
1159                 return;
1160
1161         DRM_DEBUG_KMS("Turn eDP power on\n");
1162
1163         if (ironlake_edp_have_panel_power(intel_dp)) {
1164                 DRM_DEBUG_KMS("eDP power already on\n");
1165                 return;
1166         }
1167
1168         ironlake_wait_panel_power_cycle(intel_dp);
1169
1170         pp = ironlake_get_pp_control(dev_priv);
1171         if (IS_GEN5(dev)) {
1172                 /* ILK workaround: disable reset around power sequence */
1173                 pp &= ~PANEL_POWER_RESET;
1174                 I915_WRITE(PCH_PP_CONTROL, pp);
1175                 POSTING_READ(PCH_PP_CONTROL);
1176         }
1177
1178         pp |= POWER_TARGET_ON;
1179         if (!IS_GEN5(dev))
1180                 pp |= PANEL_POWER_RESET;
1181
1182         I915_WRITE(PCH_PP_CONTROL, pp);
1183         POSTING_READ(PCH_PP_CONTROL);
1184
1185         ironlake_wait_panel_on(intel_dp);
1186
1187         if (IS_GEN5(dev)) {
1188                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1189                 I915_WRITE(PCH_PP_CONTROL, pp);
1190                 POSTING_READ(PCH_PP_CONTROL);
1191         }
1192 }
1193
1194 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1195 {
1196         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         u32 pp;
1199
1200         if (!is_edp(intel_dp))
1201                 return;
1202
1203         DRM_DEBUG_KMS("Turn eDP power off\n");
1204
1205         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1206
1207         pp = ironlake_get_pp_control(dev_priv);
1208         /* We need to switch off panel power _and_ force vdd, for otherwise some
1209          * panels get very unhappy and cease to work. */
1210         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1211         I915_WRITE(PCH_PP_CONTROL, pp);
1212         POSTING_READ(PCH_PP_CONTROL);
1213
1214         intel_dp->want_panel_vdd = false;
1215
1216         ironlake_wait_panel_off(intel_dp);
1217 }
1218
1219 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1220 {
1221         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1222         struct drm_device *dev = intel_dig_port->base.base.dev;
1223         struct drm_i915_private *dev_priv = dev->dev_private;
1224         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1225         u32 pp;
1226
1227         if (!is_edp(intel_dp))
1228                 return;
1229
1230         DRM_DEBUG_KMS("\n");
1231         /*
1232          * If we enable the backlight right away following a panel power
1233          * on, we may see slight flicker as the panel syncs with the eDP
1234          * link.  So delay a bit to make sure the image is solid before
1235          * allowing it to appear.
1236          */
1237         msleep(intel_dp->backlight_on_delay);
1238         pp = ironlake_get_pp_control(dev_priv);
1239         pp |= EDP_BLC_ENABLE;
1240         I915_WRITE(PCH_PP_CONTROL, pp);
1241         POSTING_READ(PCH_PP_CONTROL);
1242
1243         intel_panel_enable_backlight(dev, pipe);
1244 }
1245
1246 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1247 {
1248         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1249         struct drm_i915_private *dev_priv = dev->dev_private;
1250         u32 pp;
1251
1252         if (!is_edp(intel_dp))
1253                 return;
1254
1255         intel_panel_disable_backlight(dev);
1256
1257         DRM_DEBUG_KMS("\n");
1258         pp = ironlake_get_pp_control(dev_priv);
1259         pp &= ~EDP_BLC_ENABLE;
1260         I915_WRITE(PCH_PP_CONTROL, pp);
1261         POSTING_READ(PCH_PP_CONTROL);
1262         msleep(intel_dp->backlight_off_delay);
1263 }
1264
1265 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1266 {
1267         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1268         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1269         struct drm_device *dev = crtc->dev;
1270         struct drm_i915_private *dev_priv = dev->dev_private;
1271         u32 dpa_ctl;
1272
1273         assert_pipe_disabled(dev_priv,
1274                              to_intel_crtc(crtc)->pipe);
1275
1276         DRM_DEBUG_KMS("\n");
1277         dpa_ctl = I915_READ(DP_A);
1278         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1279         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1280
1281         /* We don't adjust intel_dp->DP while tearing down the link, to
1282          * facilitate link retraining (e.g. after hotplug). Hence clear all
1283          * enable bits here to ensure that we don't enable too much. */
1284         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1285         intel_dp->DP |= DP_PLL_ENABLE;
1286         I915_WRITE(DP_A, intel_dp->DP);
1287         POSTING_READ(DP_A);
1288         udelay(200);
1289 }
1290
1291 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1292 {
1293         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1294         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1295         struct drm_device *dev = crtc->dev;
1296         struct drm_i915_private *dev_priv = dev->dev_private;
1297         u32 dpa_ctl;
1298
1299         assert_pipe_disabled(dev_priv,
1300                              to_intel_crtc(crtc)->pipe);
1301
1302         dpa_ctl = I915_READ(DP_A);
1303         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1304              "dp pll off, should be on\n");
1305         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1306
1307         /* We can't rely on the value tracked for the DP register in
1308          * intel_dp->DP because link_down must not change that (otherwise link
1309          * re-training will fail. */
1310         dpa_ctl &= ~DP_PLL_ENABLE;
1311         I915_WRITE(DP_A, dpa_ctl);
1312         POSTING_READ(DP_A);
1313         udelay(200);
1314 }
1315
1316 /* If the sink supports it, try to set the power state appropriately */
1317 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1318 {
1319         int ret, i;
1320
1321         /* Should have a valid DPCD by this point */
1322         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1323                 return;
1324
1325         if (mode != DRM_MODE_DPMS_ON) {
1326                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1327                                                   DP_SET_POWER_D3);
1328                 if (ret != 1)
1329                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1330         } else {
1331                 /*
1332                  * When turning on, we need to retry for 1ms to give the sink
1333                  * time to wake up.
1334                  */
1335                 for (i = 0; i < 3; i++) {
1336                         ret = intel_dp_aux_native_write_1(intel_dp,
1337                                                           DP_SET_POWER,
1338                                                           DP_SET_POWER_D0);
1339                         if (ret == 1)
1340                                 break;
1341                         msleep(1);
1342                 }
1343         }
1344 }
1345
1346 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1347                                   enum pipe *pipe)
1348 {
1349         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1350         struct drm_device *dev = encoder->base.dev;
1351         struct drm_i915_private *dev_priv = dev->dev_private;
1352         u32 tmp = I915_READ(intel_dp->output_reg);
1353
1354         if (!(tmp & DP_PORT_EN))
1355                 return false;
1356
1357         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1358                 *pipe = PORT_TO_PIPE_CPT(tmp);
1359         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1360                 *pipe = PORT_TO_PIPE(tmp);
1361         } else {
1362                 u32 trans_sel;
1363                 u32 trans_dp;
1364                 int i;
1365
1366                 switch (intel_dp->output_reg) {
1367                 case PCH_DP_B:
1368                         trans_sel = TRANS_DP_PORT_SEL_B;
1369                         break;
1370                 case PCH_DP_C:
1371                         trans_sel = TRANS_DP_PORT_SEL_C;
1372                         break;
1373                 case PCH_DP_D:
1374                         trans_sel = TRANS_DP_PORT_SEL_D;
1375                         break;
1376                 default:
1377                         return true;
1378                 }
1379
1380                 for_each_pipe(i) {
1381                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1382                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1383                                 *pipe = i;
1384                                 return true;
1385                         }
1386                 }
1387
1388                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1389                               intel_dp->output_reg);
1390         }
1391
1392         return true;
1393 }
1394
1395 static void intel_disable_dp(struct intel_encoder *encoder)
1396 {
1397         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1398
1399         /* Make sure the panel is off before trying to change the mode. But also
1400          * ensure that we have vdd while we switch off the panel. */
1401         ironlake_edp_panel_vdd_on(intel_dp);
1402         ironlake_edp_backlight_off(intel_dp);
1403         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1404         ironlake_edp_panel_off(intel_dp);
1405
1406         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1407         if (!is_cpu_edp(intel_dp))
1408                 intel_dp_link_down(intel_dp);
1409 }
1410
1411 static void intel_post_disable_dp(struct intel_encoder *encoder)
1412 {
1413         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1414
1415         if (is_cpu_edp(intel_dp)) {
1416                 intel_dp_link_down(intel_dp);
1417                 ironlake_edp_pll_off(intel_dp);
1418         }
1419 }
1420
1421 static void intel_enable_dp(struct intel_encoder *encoder)
1422 {
1423         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1424         struct drm_device *dev = encoder->base.dev;
1425         struct drm_i915_private *dev_priv = dev->dev_private;
1426         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1427
1428         if (WARN_ON(dp_reg & DP_PORT_EN))
1429                 return;
1430
1431         ironlake_edp_panel_vdd_on(intel_dp);
1432         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1433         intel_dp_start_link_train(intel_dp);
1434         ironlake_edp_panel_on(intel_dp);
1435         ironlake_edp_panel_vdd_off(intel_dp, true);
1436         intel_dp_complete_link_train(intel_dp);
1437         ironlake_edp_backlight_on(intel_dp);
1438 }
1439
1440 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1441 {
1442         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1443
1444         if (is_cpu_edp(intel_dp))
1445                 ironlake_edp_pll_on(intel_dp);
1446 }
1447
1448 /*
1449  * Native read with retry for link status and receiver capability reads for
1450  * cases where the sink may still be asleep.
1451  */
1452 static bool
1453 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1454                                uint8_t *recv, int recv_bytes)
1455 {
1456         int ret, i;
1457
1458         /*
1459          * Sinks are *supposed* to come up within 1ms from an off state,
1460          * but we're also supposed to retry 3 times per the spec.
1461          */
1462         for (i = 0; i < 3; i++) {
1463                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1464                                                recv_bytes);
1465                 if (ret == recv_bytes)
1466                         return true;
1467                 msleep(1);
1468         }
1469
1470         return false;
1471 }
1472
1473 /*
1474  * Fetch AUX CH registers 0x202 - 0x207 which contain
1475  * link status information
1476  */
1477 static bool
1478 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1479 {
1480         return intel_dp_aux_native_read_retry(intel_dp,
1481                                               DP_LANE0_1_STATUS,
1482                                               link_status,
1483                                               DP_LINK_STATUS_SIZE);
1484 }
1485
1486 #if 0
1487 static char     *voltage_names[] = {
1488         "0.4V", "0.6V", "0.8V", "1.2V"
1489 };
1490 static char     *pre_emph_names[] = {
1491         "0dB", "3.5dB", "6dB", "9.5dB"
1492 };
1493 static char     *link_train_names[] = {
1494         "pattern 1", "pattern 2", "idle", "off"
1495 };
1496 #endif
1497
1498 /*
1499  * These are source-specific values; current Intel hardware supports
1500  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1501  */
1502
1503 static uint8_t
1504 intel_dp_voltage_max(struct intel_dp *intel_dp)
1505 {
1506         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1507
1508         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1509                 return DP_TRAIN_VOLTAGE_SWING_800;
1510         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1511                 return DP_TRAIN_VOLTAGE_SWING_1200;
1512         else
1513                 return DP_TRAIN_VOLTAGE_SWING_800;
1514 }
1515
1516 static uint8_t
1517 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1518 {
1519         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1520
1521         if (IS_HASWELL(dev)) {
1522                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1523                 case DP_TRAIN_VOLTAGE_SWING_400:
1524                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1525                 case DP_TRAIN_VOLTAGE_SWING_600:
1526                         return DP_TRAIN_PRE_EMPHASIS_6;
1527                 case DP_TRAIN_VOLTAGE_SWING_800:
1528                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1529                 case DP_TRAIN_VOLTAGE_SWING_1200:
1530                 default:
1531                         return DP_TRAIN_PRE_EMPHASIS_0;
1532                 }
1533         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1534                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1535                 case DP_TRAIN_VOLTAGE_SWING_400:
1536                         return DP_TRAIN_PRE_EMPHASIS_6;
1537                 case DP_TRAIN_VOLTAGE_SWING_600:
1538                 case DP_TRAIN_VOLTAGE_SWING_800:
1539                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1540                 default:
1541                         return DP_TRAIN_PRE_EMPHASIS_0;
1542                 }
1543         } else {
1544                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1545                 case DP_TRAIN_VOLTAGE_SWING_400:
1546                         return DP_TRAIN_PRE_EMPHASIS_6;
1547                 case DP_TRAIN_VOLTAGE_SWING_600:
1548                         return DP_TRAIN_PRE_EMPHASIS_6;
1549                 case DP_TRAIN_VOLTAGE_SWING_800:
1550                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1551                 case DP_TRAIN_VOLTAGE_SWING_1200:
1552                 default:
1553                         return DP_TRAIN_PRE_EMPHASIS_0;
1554                 }
1555         }
1556 }
1557
1558 static void
1559 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1560 {
1561         uint8_t v = 0;
1562         uint8_t p = 0;
1563         int lane;
1564         uint8_t voltage_max;
1565         uint8_t preemph_max;
1566
1567         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1568                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1569                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1570
1571                 if (this_v > v)
1572                         v = this_v;
1573                 if (this_p > p)
1574                         p = this_p;
1575         }
1576
1577         voltage_max = intel_dp_voltage_max(intel_dp);
1578         if (v >= voltage_max)
1579                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1580
1581         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1582         if (p >= preemph_max)
1583                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1584
1585         for (lane = 0; lane < 4; lane++)
1586                 intel_dp->train_set[lane] = v | p;
1587 }
1588
1589 static uint32_t
1590 intel_dp_signal_levels(uint8_t train_set)
1591 {
1592         uint32_t        signal_levels = 0;
1593
1594         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1595         case DP_TRAIN_VOLTAGE_SWING_400:
1596         default:
1597                 signal_levels |= DP_VOLTAGE_0_4;
1598                 break;
1599         case DP_TRAIN_VOLTAGE_SWING_600:
1600                 signal_levels |= DP_VOLTAGE_0_6;
1601                 break;
1602         case DP_TRAIN_VOLTAGE_SWING_800:
1603                 signal_levels |= DP_VOLTAGE_0_8;
1604                 break;
1605         case DP_TRAIN_VOLTAGE_SWING_1200:
1606                 signal_levels |= DP_VOLTAGE_1_2;
1607                 break;
1608         }
1609         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1610         case DP_TRAIN_PRE_EMPHASIS_0:
1611         default:
1612                 signal_levels |= DP_PRE_EMPHASIS_0;
1613                 break;
1614         case DP_TRAIN_PRE_EMPHASIS_3_5:
1615                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1616                 break;
1617         case DP_TRAIN_PRE_EMPHASIS_6:
1618                 signal_levels |= DP_PRE_EMPHASIS_6;
1619                 break;
1620         case DP_TRAIN_PRE_EMPHASIS_9_5:
1621                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1622                 break;
1623         }
1624         return signal_levels;
1625 }
1626
1627 /* Gen6's DP voltage swing and pre-emphasis control */
1628 static uint32_t
1629 intel_gen6_edp_signal_levels(uint8_t train_set)
1630 {
1631         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1632                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1633         switch (signal_levels) {
1634         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1635         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1636                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1637         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1638                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1639         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1640         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1641                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1642         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1643         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1644                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1645         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1646         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1647                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1648         default:
1649                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1650                               "0x%x\n", signal_levels);
1651                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1652         }
1653 }
1654
1655 /* Gen7's DP voltage swing and pre-emphasis control */
1656 static uint32_t
1657 intel_gen7_edp_signal_levels(uint8_t train_set)
1658 {
1659         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1660                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1661         switch (signal_levels) {
1662         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1663                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1664         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1665                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1666         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1667                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1668
1669         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1670                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1671         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1672                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1673
1674         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1675                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1676         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1678
1679         default:
1680                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1681                               "0x%x\n", signal_levels);
1682                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1683         }
1684 }
1685
1686 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1687 static uint32_t
1688 intel_dp_signal_levels_hsw(uint8_t train_set)
1689 {
1690         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1691                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1692         switch (signal_levels) {
1693         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1694                 return DDI_BUF_EMP_400MV_0DB_HSW;
1695         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1696                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1697         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1698                 return DDI_BUF_EMP_400MV_6DB_HSW;
1699         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1700                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1701
1702         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1703                 return DDI_BUF_EMP_600MV_0DB_HSW;
1704         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1705                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1706         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1707                 return DDI_BUF_EMP_600MV_6DB_HSW;
1708
1709         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1710                 return DDI_BUF_EMP_800MV_0DB_HSW;
1711         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1712                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1713         default:
1714                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1715                               "0x%x\n", signal_levels);
1716                 return DDI_BUF_EMP_400MV_0DB_HSW;
1717         }
1718 }
1719
1720 static bool
1721 intel_dp_set_link_train(struct intel_dp *intel_dp,
1722                         uint32_t dp_reg_value,
1723                         uint8_t dp_train_pat)
1724 {
1725         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1726         struct drm_device *dev = intel_dig_port->base.base.dev;
1727         struct drm_i915_private *dev_priv = dev->dev_private;
1728         enum port port = intel_dig_port->port;
1729         int ret;
1730         uint32_t temp;
1731
1732         if (IS_HASWELL(dev)) {
1733                 temp = I915_READ(DP_TP_CTL(port));
1734
1735                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1736                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1737                 else
1738                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1739
1740                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1741                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1742                 case DP_TRAINING_PATTERN_DISABLE:
1743                         temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1744                         I915_WRITE(DP_TP_CTL(port), temp);
1745
1746                         if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1747                                       DP_TP_STATUS_IDLE_DONE), 1))
1748                                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1749
1750                         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1751                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1752
1753                         break;
1754                 case DP_TRAINING_PATTERN_1:
1755                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1756                         break;
1757                 case DP_TRAINING_PATTERN_2:
1758                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1759                         break;
1760                 case DP_TRAINING_PATTERN_3:
1761                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1762                         break;
1763                 }
1764                 I915_WRITE(DP_TP_CTL(port), temp);
1765
1766         } else if (HAS_PCH_CPT(dev) &&
1767                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1768                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1769
1770                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1771                 case DP_TRAINING_PATTERN_DISABLE:
1772                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1773                         break;
1774                 case DP_TRAINING_PATTERN_1:
1775                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1776                         break;
1777                 case DP_TRAINING_PATTERN_2:
1778                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1779                         break;
1780                 case DP_TRAINING_PATTERN_3:
1781                         DRM_ERROR("DP training pattern 3 not supported\n");
1782                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1783                         break;
1784                 }
1785
1786         } else {
1787                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1788
1789                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1790                 case DP_TRAINING_PATTERN_DISABLE:
1791                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1792                         break;
1793                 case DP_TRAINING_PATTERN_1:
1794                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1795                         break;
1796                 case DP_TRAINING_PATTERN_2:
1797                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1798                         break;
1799                 case DP_TRAINING_PATTERN_3:
1800                         DRM_ERROR("DP training pattern 3 not supported\n");
1801                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1802                         break;
1803                 }
1804         }
1805
1806         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1807         POSTING_READ(intel_dp->output_reg);
1808
1809         intel_dp_aux_native_write_1(intel_dp,
1810                                     DP_TRAINING_PATTERN_SET,
1811                                     dp_train_pat);
1812
1813         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1814             DP_TRAINING_PATTERN_DISABLE) {
1815                 ret = intel_dp_aux_native_write(intel_dp,
1816                                                 DP_TRAINING_LANE0_SET,
1817                                                 intel_dp->train_set,
1818                                                 intel_dp->lane_count);
1819                 if (ret != intel_dp->lane_count)
1820                         return false;
1821         }
1822
1823         return true;
1824 }
1825
1826 /* Enable corresponding port and start training pattern 1 */
1827 void
1828 intel_dp_start_link_train(struct intel_dp *intel_dp)
1829 {
1830         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1831         struct drm_device *dev = encoder->dev;
1832         int i;
1833         uint8_t voltage;
1834         bool clock_recovery = false;
1835         int voltage_tries, loop_tries;
1836         uint32_t DP = intel_dp->DP;
1837
1838         if (HAS_DDI(dev))
1839                 intel_ddi_prepare_link_retrain(encoder);
1840
1841         /* Write the link configuration data */
1842         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1843                                   intel_dp->link_configuration,
1844                                   DP_LINK_CONFIGURATION_SIZE);
1845
1846         DP |= DP_PORT_EN;
1847
1848         memset(intel_dp->train_set, 0, 4);
1849         voltage = 0xff;
1850         voltage_tries = 0;
1851         loop_tries = 0;
1852         clock_recovery = false;
1853         for (;;) {
1854                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1855                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1856                 uint32_t    signal_levels;
1857
1858                 if (IS_HASWELL(dev)) {
1859                         signal_levels = intel_dp_signal_levels_hsw(
1860                                                         intel_dp->train_set[0]);
1861                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1862                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1863                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1864                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1865                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1866                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1867                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1868                 } else {
1869                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1870                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1871                 }
1872                 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1873                               signal_levels);
1874
1875                 /* Set training pattern 1 */
1876                 if (!intel_dp_set_link_train(intel_dp, DP,
1877                                              DP_TRAINING_PATTERN_1 |
1878                                              DP_LINK_SCRAMBLING_DISABLE))
1879                         break;
1880
1881                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1882                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1883                         DRM_ERROR("failed to get link status\n");
1884                         break;
1885                 }
1886
1887                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1888                         DRM_DEBUG_KMS("clock recovery OK\n");
1889                         clock_recovery = true;
1890                         break;
1891                 }
1892
1893                 /* Check to see if we've tried the max voltage */
1894                 for (i = 0; i < intel_dp->lane_count; i++)
1895                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1896                                 break;
1897                 if (i == intel_dp->lane_count && voltage_tries == 5) {
1898                         ++loop_tries;
1899                         if (loop_tries == 5) {
1900                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1901                                 break;
1902                         }
1903                         memset(intel_dp->train_set, 0, 4);
1904                         voltage_tries = 0;
1905                         continue;
1906                 }
1907
1908                 /* Check to see if we've tried the same voltage 5 times */
1909                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1910                         ++voltage_tries;
1911                         if (voltage_tries == 5) {
1912                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1913                                 break;
1914                         }
1915                 } else
1916                         voltage_tries = 0;
1917                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1918
1919                 /* Compute new intel_dp->train_set as requested by target */
1920                 intel_get_adjust_train(intel_dp, link_status);
1921         }
1922
1923         intel_dp->DP = DP;
1924 }
1925
1926 void
1927 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1928 {
1929         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1930         bool channel_eq = false;
1931         int tries, cr_tries;
1932         uint32_t DP = intel_dp->DP;
1933
1934         /* channel equalization */
1935         tries = 0;
1936         cr_tries = 0;
1937         channel_eq = false;
1938         for (;;) {
1939                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1940                 uint32_t    signal_levels;
1941                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1942
1943                 if (cr_tries > 5) {
1944                         DRM_ERROR("failed to train DP, aborting\n");
1945                         intel_dp_link_down(intel_dp);
1946                         break;
1947                 }
1948
1949                 if (IS_HASWELL(dev)) {
1950                         signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1951                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1952                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1953                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1954                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1955                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1956                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1957                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1958                 } else {
1959                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1960                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1961                 }
1962
1963                 /* channel eq pattern */
1964                 if (!intel_dp_set_link_train(intel_dp, DP,
1965                                              DP_TRAINING_PATTERN_2 |
1966                                              DP_LINK_SCRAMBLING_DISABLE))
1967                         break;
1968
1969                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1970                 if (!intel_dp_get_link_status(intel_dp, link_status))
1971                         break;
1972
1973                 /* Make sure clock is still ok */
1974                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1975                         intel_dp_start_link_train(intel_dp);
1976                         cr_tries++;
1977                         continue;
1978                 }
1979
1980                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1981                         channel_eq = true;
1982                         break;
1983                 }
1984
1985                 /* Try 5 times, then try clock recovery if that fails */
1986                 if (tries > 5) {
1987                         intel_dp_link_down(intel_dp);
1988                         intel_dp_start_link_train(intel_dp);
1989                         tries = 0;
1990                         cr_tries++;
1991                         continue;
1992                 }
1993
1994                 /* Compute new intel_dp->train_set as requested by target */
1995                 intel_get_adjust_train(intel_dp, link_status);
1996                 ++tries;
1997         }
1998
1999         if (channel_eq)
2000                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2001
2002         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2003 }
2004
2005 static void
2006 intel_dp_link_down(struct intel_dp *intel_dp)
2007 {
2008         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2009         struct drm_device *dev = intel_dig_port->base.base.dev;
2010         struct drm_i915_private *dev_priv = dev->dev_private;
2011         struct intel_crtc *intel_crtc =
2012                 to_intel_crtc(intel_dig_port->base.base.crtc);
2013         uint32_t DP = intel_dp->DP;
2014
2015         /*
2016          * DDI code has a strict mode set sequence and we should try to respect
2017          * it, otherwise we might hang the machine in many different ways. So we
2018          * really should be disabling the port only on a complete crtc_disable
2019          * sequence. This function is just called under two conditions on DDI
2020          * code:
2021          * - Link train failed while doing crtc_enable, and on this case we
2022          *   really should respect the mode set sequence and wait for a
2023          *   crtc_disable.
2024          * - Someone turned the monitor off and intel_dp_check_link_status
2025          *   called us. We don't need to disable the whole port on this case, so
2026          *   when someone turns the monitor on again,
2027          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2028          *   train.
2029          */
2030         if (HAS_DDI(dev))
2031                 return;
2032
2033         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2034                 return;
2035
2036         DRM_DEBUG_KMS("\n");
2037
2038         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2039                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2040                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2041         } else {
2042                 DP &= ~DP_LINK_TRAIN_MASK;
2043                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2044         }
2045         POSTING_READ(intel_dp->output_reg);
2046
2047         /* We don't really know why we're doing this */
2048         intel_wait_for_vblank(dev, intel_crtc->pipe);
2049
2050         if (HAS_PCH_IBX(dev) &&
2051             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2052                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2053
2054                 /* Hardware workaround: leaving our transcoder select
2055                  * set to transcoder B while it's off will prevent the
2056                  * corresponding HDMI output on transcoder A.
2057                  *
2058                  * Combine this with another hardware workaround:
2059                  * transcoder select bit can only be cleared while the
2060                  * port is enabled.
2061                  */
2062                 DP &= ~DP_PIPEB_SELECT;
2063                 I915_WRITE(intel_dp->output_reg, DP);
2064
2065                 /* Changes to enable or select take place the vblank
2066                  * after being written.
2067                  */
2068                 if (WARN_ON(crtc == NULL)) {
2069                         /* We should never try to disable a port without a crtc
2070                          * attached. For paranoia keep the code around for a
2071                          * bit. */
2072                         POSTING_READ(intel_dp->output_reg);
2073                         msleep(50);
2074                 } else
2075                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2076         }
2077
2078         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2079         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2080         POSTING_READ(intel_dp->output_reg);
2081         msleep(intel_dp->panel_power_down_delay);
2082 }
2083
2084 static bool
2085 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2086 {
2087         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2088                                            sizeof(intel_dp->dpcd)) == 0)
2089                 return false; /* aux transfer failed */
2090
2091         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2092                 return false; /* DPCD not present */
2093
2094         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2095               DP_DWN_STRM_PORT_PRESENT))
2096                 return true; /* native DP sink */
2097
2098         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2099                 return true; /* no per-port downstream info */
2100
2101         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2102                                            intel_dp->downstream_ports,
2103                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2104                 return false; /* downstream port status fetch failed */
2105
2106         return true;
2107 }
2108
2109 static void
2110 intel_dp_probe_oui(struct intel_dp *intel_dp)
2111 {
2112         u8 buf[3];
2113
2114         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2115                 return;
2116
2117         ironlake_edp_panel_vdd_on(intel_dp);
2118
2119         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2120                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2121                               buf[0], buf[1], buf[2]);
2122
2123         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2124                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2125                               buf[0], buf[1], buf[2]);
2126
2127         ironlake_edp_panel_vdd_off(intel_dp, false);
2128 }
2129
2130 static bool
2131 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2132 {
2133         int ret;
2134
2135         ret = intel_dp_aux_native_read_retry(intel_dp,
2136                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2137                                              sink_irq_vector, 1);
2138         if (!ret)
2139                 return false;
2140
2141         return true;
2142 }
2143
2144 static void
2145 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2146 {
2147         /* NAK by default */
2148         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2149 }
2150
2151 /*
2152  * According to DP spec
2153  * 5.1.2:
2154  *  1. Read DPCD
2155  *  2. Configure link according to Receiver Capabilities
2156  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2157  *  4. Check link status on receipt of hot-plug interrupt
2158  */
2159
2160 void
2161 intel_dp_check_link_status(struct intel_dp *intel_dp)
2162 {
2163         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2164         u8 sink_irq_vector;
2165         u8 link_status[DP_LINK_STATUS_SIZE];
2166
2167         if (!intel_encoder->connectors_active)
2168                 return;
2169
2170         if (WARN_ON(!intel_encoder->base.crtc))
2171                 return;
2172
2173         /* Try to read receiver status if the link appears to be up */
2174         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2175                 intel_dp_link_down(intel_dp);
2176                 return;
2177         }
2178
2179         /* Now read the DPCD to see if it's actually running */
2180         if (!intel_dp_get_dpcd(intel_dp)) {
2181                 intel_dp_link_down(intel_dp);
2182                 return;
2183         }
2184
2185         /* Try to read the source of the interrupt */
2186         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2187             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2188                 /* Clear interrupt source */
2189                 intel_dp_aux_native_write_1(intel_dp,
2190                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2191                                             sink_irq_vector);
2192
2193                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2194                         intel_dp_handle_test_request(intel_dp);
2195                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2196                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2197         }
2198
2199         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2200                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2201                               drm_get_encoder_name(&intel_encoder->base));
2202                 intel_dp_start_link_train(intel_dp);
2203                 intel_dp_complete_link_train(intel_dp);
2204         }
2205 }
2206
2207 /* XXX this is probably wrong for multiple downstream ports */
2208 static enum drm_connector_status
2209 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2210 {
2211         uint8_t *dpcd = intel_dp->dpcd;
2212         bool hpd;
2213         uint8_t type;
2214
2215         if (!intel_dp_get_dpcd(intel_dp))
2216                 return connector_status_disconnected;
2217
2218         /* if there's no downstream port, we're done */
2219         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2220                 return connector_status_connected;
2221
2222         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2223         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2224         if (hpd) {
2225                 uint8_t reg;
2226                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2227                                                     &reg, 1))
2228                         return connector_status_unknown;
2229                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2230                                               : connector_status_disconnected;
2231         }
2232
2233         /* If no HPD, poke DDC gently */
2234         if (drm_probe_ddc(&intel_dp->adapter))
2235                 return connector_status_connected;
2236
2237         /* Well we tried, say unknown for unreliable port types */
2238         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2239         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2240                 return connector_status_unknown;
2241
2242         /* Anything else is out of spec, warn and ignore */
2243         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2244         return connector_status_disconnected;
2245 }
2246
2247 static enum drm_connector_status
2248 ironlake_dp_detect(struct intel_dp *intel_dp)
2249 {
2250         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2251         enum drm_connector_status status;
2252
2253         /* Can't disconnect eDP, but you can close the lid... */
2254         if (is_edp(intel_dp)) {
2255                 status = intel_panel_detect(dev);
2256                 if (status == connector_status_unknown)
2257                         status = connector_status_connected;
2258                 return status;
2259         }
2260
2261         return intel_dp_detect_dpcd(intel_dp);
2262 }
2263
2264 static enum drm_connector_status
2265 g4x_dp_detect(struct intel_dp *intel_dp)
2266 {
2267         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2268         struct drm_i915_private *dev_priv = dev->dev_private;
2269         uint32_t bit;
2270
2271         switch (intel_dp->output_reg) {
2272         case DP_B:
2273                 bit = DPB_HOTPLUG_LIVE_STATUS;
2274                 break;
2275         case DP_C:
2276                 bit = DPC_HOTPLUG_LIVE_STATUS;
2277                 break;
2278         case DP_D:
2279                 bit = DPD_HOTPLUG_LIVE_STATUS;
2280                 break;
2281         default:
2282                 return connector_status_unknown;
2283         }
2284
2285         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2286                 return connector_status_disconnected;
2287
2288         return intel_dp_detect_dpcd(intel_dp);
2289 }
2290
2291 static struct edid *
2292 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2293 {
2294         struct intel_connector *intel_connector = to_intel_connector(connector);
2295
2296         /* use cached edid if we have one */
2297         if (intel_connector->edid) {
2298                 struct edid *edid;
2299                 int size;
2300
2301                 /* invalid edid */
2302                 if (IS_ERR(intel_connector->edid))
2303                         return NULL;
2304
2305                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2306                 edid = kmalloc(size, GFP_KERNEL);
2307                 if (!edid)
2308                         return NULL;
2309
2310                 memcpy(edid, intel_connector->edid, size);
2311                 return edid;
2312         }
2313
2314         return drm_get_edid(connector, adapter);
2315 }
2316
2317 static int
2318 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2319 {
2320         struct intel_connector *intel_connector = to_intel_connector(connector);
2321
2322         /* use cached edid if we have one */
2323         if (intel_connector->edid) {
2324                 /* invalid edid */
2325                 if (IS_ERR(intel_connector->edid))
2326                         return 0;
2327
2328                 return intel_connector_update_modes(connector,
2329                                                     intel_connector->edid);
2330         }
2331
2332         return intel_ddc_get_modes(connector, adapter);
2333 }
2334
2335
2336 /**
2337  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2338  *
2339  * \return true if DP port is connected.
2340  * \return false if DP port is disconnected.
2341  */
2342 static enum drm_connector_status
2343 intel_dp_detect(struct drm_connector *connector, bool force)
2344 {
2345         struct intel_dp *intel_dp = intel_attached_dp(connector);
2346         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2347         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2348         struct drm_device *dev = connector->dev;
2349         enum drm_connector_status status;
2350         struct edid *edid = NULL;
2351         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2352
2353         intel_dp->has_audio = false;
2354
2355         if (HAS_PCH_SPLIT(dev))
2356                 status = ironlake_dp_detect(intel_dp);
2357         else
2358                 status = g4x_dp_detect(intel_dp);
2359
2360         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2361                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2362         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2363
2364         if (status != connector_status_connected)
2365                 return status;
2366
2367         intel_dp_probe_oui(intel_dp);
2368
2369         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2370                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2371         } else {
2372                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2373                 if (edid) {
2374                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2375                         kfree(edid);
2376                 }
2377         }
2378
2379         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2380                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2381         return connector_status_connected;
2382 }
2383
2384 static int intel_dp_get_modes(struct drm_connector *connector)
2385 {
2386         struct intel_dp *intel_dp = intel_attached_dp(connector);
2387         struct intel_connector *intel_connector = to_intel_connector(connector);
2388         struct drm_device *dev = connector->dev;
2389         int ret;
2390
2391         /* We should parse the EDID data and find out if it has an audio sink
2392          */
2393
2394         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2395         if (ret)
2396                 return ret;
2397
2398         /* if eDP has no EDID, fall back to fixed mode */
2399         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2400                 struct drm_display_mode *mode;
2401                 mode = drm_mode_duplicate(dev,
2402                                           intel_connector->panel.fixed_mode);
2403                 if (mode) {
2404                         drm_mode_probed_add(connector, mode);
2405                         return 1;
2406                 }
2407         }
2408         return 0;
2409 }
2410
2411 static bool
2412 intel_dp_detect_audio(struct drm_connector *connector)
2413 {
2414         struct intel_dp *intel_dp = intel_attached_dp(connector);
2415         struct edid *edid;
2416         bool has_audio = false;
2417
2418         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2419         if (edid) {
2420                 has_audio = drm_detect_monitor_audio(edid);
2421                 kfree(edid);
2422         }
2423
2424         return has_audio;
2425 }
2426
2427 static int
2428 intel_dp_set_property(struct drm_connector *connector,
2429                       struct drm_property *property,
2430                       uint64_t val)
2431 {
2432         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2433         struct intel_connector *intel_connector = to_intel_connector(connector);
2434         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2435         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2436         int ret;
2437
2438         ret = drm_object_property_set_value(&connector->base, property, val);
2439         if (ret)
2440                 return ret;
2441
2442         if (property == dev_priv->force_audio_property) {
2443                 int i = val;
2444                 bool has_audio;
2445
2446                 if (i == intel_dp->force_audio)
2447                         return 0;
2448
2449                 intel_dp->force_audio = i;
2450
2451                 if (i == HDMI_AUDIO_AUTO)
2452                         has_audio = intel_dp_detect_audio(connector);
2453                 else
2454                         has_audio = (i == HDMI_AUDIO_ON);
2455
2456                 if (has_audio == intel_dp->has_audio)
2457                         return 0;
2458
2459                 intel_dp->has_audio = has_audio;
2460                 goto done;
2461         }
2462
2463         if (property == dev_priv->broadcast_rgb_property) {
2464                 if (val == !!intel_dp->color_range)
2465                         return 0;
2466
2467                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2468                 goto done;
2469         }
2470
2471         if (is_edp(intel_dp) &&
2472             property == connector->dev->mode_config.scaling_mode_property) {
2473                 if (val == DRM_MODE_SCALE_NONE) {
2474                         DRM_DEBUG_KMS("no scaling not supported\n");
2475                         return -EINVAL;
2476                 }
2477
2478                 if (intel_connector->panel.fitting_mode == val) {
2479                         /* the eDP scaling property is not changed */
2480                         return 0;
2481                 }
2482                 intel_connector->panel.fitting_mode = val;
2483
2484                 goto done;
2485         }
2486
2487         return -EINVAL;
2488
2489 done:
2490         if (intel_encoder->base.crtc) {
2491                 struct drm_crtc *crtc = intel_encoder->base.crtc;
2492                 intel_set_mode(crtc, &crtc->mode,
2493                                crtc->x, crtc->y, crtc->fb);
2494         }
2495
2496         return 0;
2497 }
2498
2499 static void
2500 intel_dp_destroy(struct drm_connector *connector)
2501 {
2502         struct drm_device *dev = connector->dev;
2503         struct intel_dp *intel_dp = intel_attached_dp(connector);
2504         struct intel_connector *intel_connector = to_intel_connector(connector);
2505
2506         if (!IS_ERR_OR_NULL(intel_connector->edid))
2507                 kfree(intel_connector->edid);
2508
2509         if (is_edp(intel_dp)) {
2510                 intel_panel_destroy_backlight(dev);
2511                 intel_panel_fini(&intel_connector->panel);
2512         }
2513
2514         drm_sysfs_connector_remove(connector);
2515         drm_connector_cleanup(connector);
2516         kfree(connector);
2517 }
2518
2519 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2520 {
2521         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2522         struct intel_dp *intel_dp = &intel_dig_port->dp;
2523
2524         i2c_del_adapter(&intel_dp->adapter);
2525         drm_encoder_cleanup(encoder);
2526         if (is_edp(intel_dp)) {
2527                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2528                 ironlake_panel_vdd_off_sync(intel_dp);
2529         }
2530         kfree(intel_dig_port);
2531 }
2532
2533 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2534         .mode_fixup = intel_dp_mode_fixup,
2535         .mode_set = intel_dp_mode_set,
2536         .disable = intel_encoder_noop,
2537 };
2538
2539 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2540         .dpms = intel_connector_dpms,
2541         .detect = intel_dp_detect,
2542         .fill_modes = drm_helper_probe_single_connector_modes,
2543         .set_property = intel_dp_set_property,
2544         .destroy = intel_dp_destroy,
2545 };
2546
2547 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2548         .get_modes = intel_dp_get_modes,
2549         .mode_valid = intel_dp_mode_valid,
2550         .best_encoder = intel_best_encoder,
2551 };
2552
2553 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2554         .destroy = intel_dp_encoder_destroy,
2555 };
2556
2557 static void
2558 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2559 {
2560         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2561
2562         intel_dp_check_link_status(intel_dp);
2563 }
2564
2565 /* Return which DP Port should be selected for Transcoder DP control */
2566 int
2567 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2568 {
2569         struct drm_device *dev = crtc->dev;
2570         struct intel_encoder *intel_encoder;
2571         struct intel_dp *intel_dp;
2572
2573         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2574                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2575
2576                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2577                     intel_encoder->type == INTEL_OUTPUT_EDP)
2578                         return intel_dp->output_reg;
2579         }
2580
2581         return -1;
2582 }
2583
2584 /* check the VBT to see whether the eDP is on DP-D port */
2585 bool intel_dpd_is_edp(struct drm_device *dev)
2586 {
2587         struct drm_i915_private *dev_priv = dev->dev_private;
2588         struct child_device_config *p_child;
2589         int i;
2590
2591         if (!dev_priv->child_dev_num)
2592                 return false;
2593
2594         for (i = 0; i < dev_priv->child_dev_num; i++) {
2595                 p_child = dev_priv->child_dev + i;
2596
2597                 if (p_child->dvo_port == PORT_IDPD &&
2598                     p_child->device_type == DEVICE_TYPE_eDP)
2599                         return true;
2600         }
2601         return false;
2602 }
2603
2604 static void
2605 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2606 {
2607         struct intel_connector *intel_connector = to_intel_connector(connector);
2608
2609         intel_attach_force_audio_property(connector);
2610         intel_attach_broadcast_rgb_property(connector);
2611
2612         if (is_edp(intel_dp)) {
2613                 drm_mode_create_scaling_mode_property(connector->dev);
2614                 drm_connector_attach_property(
2615                         connector,
2616                         connector->dev->mode_config.scaling_mode_property,
2617                         DRM_MODE_SCALE_ASPECT);
2618                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2619         }
2620 }
2621
2622 static void
2623 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2624                                     struct intel_dp *intel_dp)
2625 {
2626         struct drm_i915_private *dev_priv = dev->dev_private;
2627         struct edp_power_seq cur, vbt, spec, final;
2628         u32 pp_on, pp_off, pp_div, pp;
2629
2630         /* Workaround: Need to write PP_CONTROL with the unlock key as
2631          * the very first thing. */
2632         pp = ironlake_get_pp_control(dev_priv);
2633         I915_WRITE(PCH_PP_CONTROL, pp);
2634
2635         pp_on = I915_READ(PCH_PP_ON_DELAYS);
2636         pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2637         pp_div = I915_READ(PCH_PP_DIVISOR);
2638
2639         /* Pull timing values out of registers */
2640         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2641                 PANEL_POWER_UP_DELAY_SHIFT;
2642
2643         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2644                 PANEL_LIGHT_ON_DELAY_SHIFT;
2645
2646         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2647                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2648
2649         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2650                 PANEL_POWER_DOWN_DELAY_SHIFT;
2651
2652         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2653                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2654
2655         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2656                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2657
2658         vbt = dev_priv->edp.pps;
2659
2660         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2661          * our hw here, which are all in 100usec. */
2662         spec.t1_t3 = 210 * 10;
2663         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2664         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2665         spec.t10 = 500 * 10;
2666         /* This one is special and actually in units of 100ms, but zero
2667          * based in the hw (so we need to add 100 ms). But the sw vbt
2668          * table multiplies it with 1000 to make it in units of 100usec,
2669          * too. */
2670         spec.t11_t12 = (510 + 100) * 10;
2671
2672         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2673                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2674
2675         /* Use the max of the register settings and vbt. If both are
2676          * unset, fall back to the spec limits. */
2677 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2678                                        spec.field : \
2679                                        max(cur.field, vbt.field))
2680         assign_final(t1_t3);
2681         assign_final(t8);
2682         assign_final(t9);
2683         assign_final(t10);
2684         assign_final(t11_t12);
2685 #undef assign_final
2686
2687 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2688         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2689         intel_dp->backlight_on_delay = get_delay(t8);
2690         intel_dp->backlight_off_delay = get_delay(t9);
2691         intel_dp->panel_power_down_delay = get_delay(t10);
2692         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2693 #undef get_delay
2694
2695         /* And finally store the new values in the power sequencer. */
2696         pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2697                 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2698         pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2699                  (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2700         /* Compute the divisor for the pp clock, simply match the Bspec
2701          * formula. */
2702         pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2703                         << PP_REFERENCE_DIVIDER_SHIFT;
2704         pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2705                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2706
2707         /* Haswell doesn't have any port selection bits for the panel
2708          * power sequencer any more. */
2709         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2710                 if (is_cpu_edp(intel_dp))
2711                         pp_on |= PANEL_POWER_PORT_DP_A;
2712                 else
2713                         pp_on |= PANEL_POWER_PORT_DP_D;
2714         }
2715
2716         I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2717         I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2718         I915_WRITE(PCH_PP_DIVISOR, pp_div);
2719
2720
2721         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2722                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2723                       intel_dp->panel_power_cycle_delay);
2724
2725         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2726                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2727
2728         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2729                       I915_READ(PCH_PP_ON_DELAYS),
2730                       I915_READ(PCH_PP_OFF_DELAYS),
2731                       I915_READ(PCH_PP_DIVISOR));
2732 }
2733
2734 void
2735 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2736                         struct intel_connector *intel_connector)
2737 {
2738         struct drm_connector *connector = &intel_connector->base;
2739         struct intel_dp *intel_dp = &intel_dig_port->dp;
2740         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2741         struct drm_device *dev = intel_encoder->base.dev;
2742         struct drm_i915_private *dev_priv = dev->dev_private;
2743         struct drm_display_mode *fixed_mode = NULL;
2744         enum port port = intel_dig_port->port;
2745         const char *name = NULL;
2746         int type;
2747
2748         /* Preserve the current hw state. */
2749         intel_dp->DP = I915_READ(intel_dp->output_reg);
2750         intel_dp->attached_connector = intel_connector;
2751
2752         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2753                 if (intel_dpd_is_edp(dev))
2754                         intel_dp->is_pch_edp = true;
2755
2756         /*
2757          * FIXME : We need to initialize built-in panels before external panels.
2758          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2759          */
2760         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2761                 type = DRM_MODE_CONNECTOR_eDP;
2762                 intel_encoder->type = INTEL_OUTPUT_EDP;
2763         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2764                 type = DRM_MODE_CONNECTOR_eDP;
2765                 intel_encoder->type = INTEL_OUTPUT_EDP;
2766         } else {
2767                 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2768                  * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2769                  * rewrite it.
2770                  */
2771                 type = DRM_MODE_CONNECTOR_DisplayPort;
2772         }
2773
2774         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2775         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2776
2777         connector->polled = DRM_CONNECTOR_POLL_HPD;
2778         connector->interlace_allowed = true;
2779         connector->doublescan_allowed = 0;
2780
2781         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2782                           ironlake_panel_vdd_work);
2783
2784         intel_connector_attach_encoder(intel_connector, intel_encoder);
2785         drm_sysfs_connector_add(connector);
2786
2787         if (HAS_DDI(dev))
2788                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2789         else
2790                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2791
2792
2793         /* Set up the DDC bus. */
2794         switch (port) {
2795         case PORT_A:
2796                 name = "DPDDC-A";
2797                 break;
2798         case PORT_B:
2799                 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2800                 name = "DPDDC-B";
2801                 break;
2802         case PORT_C:
2803                 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2804                 name = "DPDDC-C";
2805                 break;
2806         case PORT_D:
2807                 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2808                 name = "DPDDC-D";
2809                 break;
2810         default:
2811                 WARN(1, "Invalid port %c\n", port_name(port));
2812                 break;
2813         }
2814
2815         if (is_edp(intel_dp))
2816                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2817
2818         intel_dp_i2c_init(intel_dp, intel_connector, name);
2819
2820         /* Cache DPCD and EDID for edp. */
2821         if (is_edp(intel_dp)) {
2822                 bool ret;
2823                 struct drm_display_mode *scan;
2824                 struct edid *edid;
2825
2826                 ironlake_edp_panel_vdd_on(intel_dp);
2827                 ret = intel_dp_get_dpcd(intel_dp);
2828                 ironlake_edp_panel_vdd_off(intel_dp, false);
2829
2830                 if (ret) {
2831                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2832                                 dev_priv->no_aux_handshake =
2833                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2834                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2835                 } else {
2836                         /* if this fails, presume the device is a ghost */
2837                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2838                         intel_dp_encoder_destroy(&intel_encoder->base);
2839                         intel_dp_destroy(connector);
2840                         return;
2841                 }
2842
2843                 ironlake_edp_panel_vdd_on(intel_dp);
2844                 edid = drm_get_edid(connector, &intel_dp->adapter);
2845                 if (edid) {
2846                         if (drm_add_edid_modes(connector, edid)) {
2847                                 drm_mode_connector_update_edid_property(connector, edid);
2848                                 drm_edid_to_eld(connector, edid);
2849                         } else {
2850                                 kfree(edid);
2851                                 edid = ERR_PTR(-EINVAL);
2852                         }
2853                 } else {
2854                         edid = ERR_PTR(-ENOENT);
2855                 }
2856                 intel_connector->edid = edid;
2857
2858                 /* prefer fixed mode from EDID if available */
2859                 list_for_each_entry(scan, &connector->probed_modes, head) {
2860                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2861                                 fixed_mode = drm_mode_duplicate(dev, scan);
2862                                 break;
2863                         }
2864                 }
2865
2866                 /* fallback to VBT if available for eDP */
2867                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2868                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2869                         if (fixed_mode)
2870                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2871                 }
2872
2873                 ironlake_edp_panel_vdd_off(intel_dp, false);
2874         }
2875
2876         if (is_edp(intel_dp)) {
2877                 intel_panel_init(&intel_connector->panel, fixed_mode);
2878                 intel_panel_setup_backlight(connector);
2879         }
2880
2881         intel_dp_add_properties(intel_dp, connector);
2882
2883         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2884          * 0xd.  Failure to do so will result in spurious interrupts being
2885          * generated on the port when a cable is not attached.
2886          */
2887         if (IS_G4X(dev) && !IS_GM45(dev)) {
2888                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2889                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2890         }
2891 }
2892
2893 void
2894 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2895 {
2896         struct intel_digital_port *intel_dig_port;
2897         struct intel_encoder *intel_encoder;
2898         struct drm_encoder *encoder;
2899         struct intel_connector *intel_connector;
2900
2901         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2902         if (!intel_dig_port)
2903                 return;
2904
2905         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2906         if (!intel_connector) {
2907                 kfree(intel_dig_port);
2908                 return;
2909         }
2910
2911         intel_encoder = &intel_dig_port->base;
2912         encoder = &intel_encoder->base;
2913
2914         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2915                          DRM_MODE_ENCODER_TMDS);
2916         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2917
2918         intel_encoder->enable = intel_enable_dp;
2919         intel_encoder->pre_enable = intel_pre_enable_dp;
2920         intel_encoder->disable = intel_disable_dp;
2921         intel_encoder->post_disable = intel_post_disable_dp;
2922         intel_encoder->get_hw_state = intel_dp_get_hw_state;
2923
2924         intel_dig_port->port = port;
2925         intel_dig_port->dp.output_reg = output_reg;
2926
2927         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2928         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2929         intel_encoder->cloneable = false;
2930         intel_encoder->hot_plug = intel_dp_hot_plug;
2931
2932         intel_dp_init_connector(intel_dig_port, intel_connector);
2933 }