2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/bug.h>
22 #include <linux/compiler.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/firewire.h>
27 #include <linux/firewire-constants.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/mutex.h>
37 #include <linux/pci.h>
38 #include <linux/pci_ids.h>
39 #include <linux/slab.h>
40 #include <linux/spinlock.h>
41 #include <linux/string.h>
42 #include <linux/time.h>
43 #include <linux/vmalloc.h>
45 #include <asm/byteorder.h>
47 #include <asm/system.h>
49 #ifdef CONFIG_PPC_PMAC
50 #include <asm/pmac_feature.h>
56 #define DESCRIPTOR_OUTPUT_MORE 0
57 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
58 #define DESCRIPTOR_INPUT_MORE (2 << 12)
59 #define DESCRIPTOR_INPUT_LAST (3 << 12)
60 #define DESCRIPTOR_STATUS (1 << 11)
61 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
62 #define DESCRIPTOR_PING (1 << 7)
63 #define DESCRIPTOR_YY (1 << 6)
64 #define DESCRIPTOR_NO_IRQ (0 << 4)
65 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
66 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
67 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
68 #define DESCRIPTOR_WAIT (3 << 0)
74 __le32 branch_address;
76 __le16 transfer_status;
77 } __attribute__((aligned(16)));
79 #define CONTROL_SET(regs) (regs)
80 #define CONTROL_CLEAR(regs) ((regs) + 4)
81 #define COMMAND_PTR(regs) ((regs) + 12)
82 #define CONTEXT_MATCH(regs) ((regs) + 16)
84 #define AR_BUFFER_SIZE (32*1024)
85 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
86 /* we need at least two pages for proper list management */
87 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89 #define MAX_ASYNC_PAYLOAD 4096
90 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
91 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
95 struct page *pages[AR_BUFFERS];
97 struct descriptor *descriptors;
98 dma_addr_t descriptors_bus;
100 unsigned int last_buffer_index;
102 struct tasklet_struct tasklet;
107 typedef int (*descriptor_callback_t)(struct context *ctx,
108 struct descriptor *d,
109 struct descriptor *last);
112 * A buffer that contains a block of DMA-able coherent memory used for
113 * storing a portion of a DMA descriptor program.
115 struct descriptor_buffer {
116 struct list_head list;
117 dma_addr_t buffer_bus;
120 struct descriptor buffer[0];
124 struct fw_ohci *ohci;
126 int total_allocation;
129 * List of page-sized buffers for storing DMA descriptors.
130 * Head of list contains buffers in use and tail of list contains
133 struct list_head buffer_list;
136 * Pointer to a buffer inside buffer_list that contains the tail
137 * end of the current DMA program.
139 struct descriptor_buffer *buffer_tail;
142 * The descriptor containing the branch address of the first
143 * descriptor that has not yet been filled by the device.
145 struct descriptor *last;
148 * The last descriptor in the DMA program. It contains the branch
149 * address that must be updated upon appending a new descriptor.
151 struct descriptor *prev;
153 descriptor_callback_t callback;
155 struct tasklet_struct tasklet;
158 #define IT_HEADER_SY(v) ((v) << 0)
159 #define IT_HEADER_TCODE(v) ((v) << 4)
160 #define IT_HEADER_CHANNEL(v) ((v) << 8)
161 #define IT_HEADER_TAG(v) ((v) << 14)
162 #define IT_HEADER_SPEED(v) ((v) << 16)
163 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
166 struct fw_iso_context base;
167 struct context context;
170 size_t header_length;
173 #define CONFIG_ROM_SIZE 1024
178 __iomem char *registers;
181 int request_generation; /* for timestamping incoming requests */
183 unsigned int pri_req_max;
186 bool csr_state_setclear_abdicate;
189 * Spinlock for accessing fw_ohci data. Never call out of
190 * this driver with this lock held.
194 struct mutex phy_reg_mutex;
196 struct ar_context ar_request_ctx;
197 struct ar_context ar_response_ctx;
198 struct context at_request_ctx;
199 struct context at_response_ctx;
201 u32 it_context_mask; /* unoccupied IT contexts */
202 struct iso_context *it_context_list;
203 u64 ir_context_channels; /* unoccupied channels */
204 u32 ir_context_mask; /* unoccupied IR contexts */
205 struct iso_context *ir_context_list;
206 u64 mc_channels; /* channels in use by the multichannel IR context */
210 dma_addr_t config_rom_bus;
211 __be32 *next_config_rom;
212 dma_addr_t next_config_rom_bus;
216 dma_addr_t self_id_bus;
217 struct tasklet_struct bus_reset_tasklet;
219 u32 self_id_buffer[512];
222 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
224 return container_of(card, struct fw_ohci, card);
227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
228 #define IR_CONTEXT_BUFFER_FILL 0x80000000
229 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
231 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
232 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
234 #define CONTEXT_RUN 0x8000
235 #define CONTEXT_WAKE 0x1000
236 #define CONTEXT_DEAD 0x0800
237 #define CONTEXT_ACTIVE 0x0400
239 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
240 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
241 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
243 #define OHCI1394_REGISTER_SIZE 0x800
244 #define OHCI_LOOP_COUNT 500
245 #define OHCI1394_PCI_HCI_Control 0x40
246 #define SELF_ID_BUF_SIZE 0x800
247 #define OHCI_TCODE_PHY_PACKET 0x0e
248 #define OHCI_VERSION_1_1 0x010010
250 static char ohci_driver_name[] = KBUILD_MODNAME;
252 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
253 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
254 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
256 #define QUIRK_CYCLE_TIMER 1
257 #define QUIRK_RESET_PACKET 2
258 #define QUIRK_BE_HEADERS 4
259 #define QUIRK_NO_1394A 8
260 #define QUIRK_NO_MSI 16
262 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
263 static const struct {
264 unsigned short vendor, device, revision, flags;
266 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
269 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
272 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
275 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
278 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
281 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
284 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
285 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
287 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
290 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
291 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
294 /* This overrides anything that was found in ohci_quirks[]. */
295 static int param_quirks;
296 module_param_named(quirks, param_quirks, int, 0644);
297 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
298 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
299 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
300 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
301 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
302 ", disable MSI = " __stringify(QUIRK_NO_MSI)
305 #define OHCI_PARAM_DEBUG_AT_AR 1
306 #define OHCI_PARAM_DEBUG_SELFIDS 2
307 #define OHCI_PARAM_DEBUG_IRQS 4
308 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
310 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
312 static int param_debug;
313 module_param_named(debug, param_debug, int, 0644);
314 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
315 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
316 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
317 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
318 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
319 ", or a combination, or all = -1)");
321 static void log_irqs(u32 evt)
323 if (likely(!(param_debug &
324 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
327 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
328 !(evt & OHCI1394_busReset))
331 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
332 evt & OHCI1394_selfIDComplete ? " selfID" : "",
333 evt & OHCI1394_RQPkt ? " AR_req" : "",
334 evt & OHCI1394_RSPkt ? " AR_resp" : "",
335 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
336 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
337 evt & OHCI1394_isochRx ? " IR" : "",
338 evt & OHCI1394_isochTx ? " IT" : "",
339 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
340 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
341 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
342 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
343 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
344 evt & OHCI1394_busReset ? " busReset" : "",
345 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
346 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
347 OHCI1394_respTxComplete | OHCI1394_isochRx |
348 OHCI1394_isochTx | OHCI1394_postedWriteErr |
349 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
350 OHCI1394_cycleInconsistent |
351 OHCI1394_regAccessFail | OHCI1394_busReset)
355 static const char *speed[] = {
356 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
358 static const char *power[] = {
359 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
360 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
362 static const char port[] = { '.', '-', 'p', 'c', };
364 static char _p(u32 *s, int shift)
366 return port[*s >> shift & 3];
369 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
371 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
374 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
375 self_id_count, generation, node_id);
377 for (; self_id_count--; ++s)
378 if ((*s & 1 << 23) == 0)
379 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
380 "%s gc=%d %s %s%s%s\n",
381 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
382 speed[*s >> 14 & 3], *s >> 16 & 63,
383 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
384 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
386 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
388 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
389 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
392 static const char *evts[] = {
393 [0x00] = "evt_no_status", [0x01] = "-reserved-",
394 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
395 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
396 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
397 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
398 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
399 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
400 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
401 [0x10] = "-reserved-", [0x11] = "ack_complete",
402 [0x12] = "ack_pending ", [0x13] = "-reserved-",
403 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
404 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
405 [0x18] = "-reserved-", [0x19] = "-reserved-",
406 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
407 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
408 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
409 [0x20] = "pending/cancelled",
411 static const char *tcodes[] = {
412 [0x0] = "QW req", [0x1] = "BW req",
413 [0x2] = "W resp", [0x3] = "-reserved-",
414 [0x4] = "QR req", [0x5] = "BR req",
415 [0x6] = "QR resp", [0x7] = "BR resp",
416 [0x8] = "cycle start", [0x9] = "Lk req",
417 [0xa] = "async stream packet", [0xb] = "Lk resp",
418 [0xc] = "-reserved-", [0xd] = "-reserved-",
419 [0xe] = "link internal", [0xf] = "-reserved-",
421 static const char *phys[] = {
422 [0x0] = "phy config packet", [0x1] = "link-on packet",
423 [0x2] = "self-id packet", [0x3] = "-reserved-",
426 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
428 int tcode = header[0] >> 4 & 0xf;
431 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
434 if (unlikely(evt >= ARRAY_SIZE(evts)))
437 if (evt == OHCI1394_evt_bus_reset) {
438 fw_notify("A%c evt_bus_reset, generation %d\n",
439 dir, (header[2] >> 16) & 0xff);
443 if (header[0] == ~header[1]) {
444 fw_notify("A%c %s, %s, %08x\n",
445 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
450 case 0x0: case 0x6: case 0x8:
451 snprintf(specific, sizeof(specific), " = %08x",
452 be32_to_cpu((__force __be32)header[3]));
454 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
455 snprintf(specific, sizeof(specific), " %x,%x",
456 header[3] >> 16, header[3] & 0xffff);
464 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
466 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
467 fw_notify("A%c spd %x tl %02x, "
470 dir, speed, header[0] >> 10 & 0x3f,
471 header[1] >> 16, header[0] >> 16, evts[evt],
472 tcodes[tcode], header[1] & 0xffff, header[2], specific);
475 fw_notify("A%c spd %x tl %02x, "
478 dir, speed, header[0] >> 10 & 0x3f,
479 header[1] >> 16, header[0] >> 16, evts[evt],
480 tcodes[tcode], specific);
486 #define param_debug 0
487 static inline void log_irqs(u32 evt) {}
488 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
489 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
491 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
493 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
495 writel(data, ohci->registers + offset);
498 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
500 return readl(ohci->registers + offset);
503 static inline void flush_writes(const struct fw_ohci *ohci)
505 /* Do a dummy read to flush writes. */
506 reg_read(ohci, OHCI1394_Version);
509 static int read_phy_reg(struct fw_ohci *ohci, int addr)
514 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
515 for (i = 0; i < 3 + 100; i++) {
516 val = reg_read(ohci, OHCI1394_PhyControl);
517 if (val & OHCI1394_PhyControl_ReadDone)
518 return OHCI1394_PhyControl_ReadData(val);
521 * Try a few times without waiting. Sleeping is necessary
522 * only when the link/PHY interface is busy.
527 fw_error("failed to read phy reg\n");
532 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
536 reg_write(ohci, OHCI1394_PhyControl,
537 OHCI1394_PhyControl_Write(addr, val));
538 for (i = 0; i < 3 + 100; i++) {
539 val = reg_read(ohci, OHCI1394_PhyControl);
540 if (!(val & OHCI1394_PhyControl_WritePending))
546 fw_error("failed to write phy reg\n");
551 static int update_phy_reg(struct fw_ohci *ohci, int addr,
552 int clear_bits, int set_bits)
554 int ret = read_phy_reg(ohci, addr);
559 * The interrupt status bits are cleared by writing a one bit.
560 * Avoid clearing them unless explicitly requested in set_bits.
563 clear_bits |= PHY_INT_STATUS_BITS;
565 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
568 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
572 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
576 return read_phy_reg(ohci, addr);
579 static int ohci_read_phy_reg(struct fw_card *card, int addr)
581 struct fw_ohci *ohci = fw_ohci(card);
584 mutex_lock(&ohci->phy_reg_mutex);
585 ret = read_phy_reg(ohci, addr);
586 mutex_unlock(&ohci->phy_reg_mutex);
591 static int ohci_update_phy_reg(struct fw_card *card, int addr,
592 int clear_bits, int set_bits)
594 struct fw_ohci *ohci = fw_ohci(card);
597 mutex_lock(&ohci->phy_reg_mutex);
598 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
599 mutex_unlock(&ohci->phy_reg_mutex);
604 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
606 return page_private(ctx->pages[i]);
609 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
611 struct descriptor *d;
613 d = &ctx->descriptors[index];
614 d->branch_address &= cpu_to_le32(~0xf);
615 d->res_count = cpu_to_le16(PAGE_SIZE);
616 d->transfer_status = 0;
618 wmb(); /* finish init of new descriptors before branch_address update */
619 d = &ctx->descriptors[ctx->last_buffer_index];
620 d->branch_address |= cpu_to_le32(1);
622 ctx->last_buffer_index = index;
624 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
625 flush_writes(ctx->ohci);
628 static void ar_context_release(struct ar_context *ctx)
632 if (ctx->descriptors)
633 dma_free_coherent(ctx->ohci->card.device,
634 AR_BUFFERS * sizeof(struct descriptor),
635 ctx->descriptors, ctx->descriptors_bus);
638 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
640 for (i = 0; i < AR_BUFFERS; i++)
642 dma_unmap_page(ctx->ohci->card.device,
643 ar_buffer_bus(ctx, i),
644 PAGE_SIZE, DMA_FROM_DEVICE);
645 __free_page(ctx->pages[i]);
649 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
651 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
652 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
653 flush_writes(ctx->ohci);
655 fw_error("AR error: %s; DMA stopped\n", error_msg);
657 /* FIXME: restart? */
660 static inline unsigned int ar_next_buffer_index(unsigned int index)
662 return (index + 1) % AR_BUFFERS;
665 static inline unsigned int ar_prev_buffer_index(unsigned int index)
667 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
670 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
672 return ar_next_buffer_index(ctx->last_buffer_index);
676 * We search for the buffer that contains the last AR packet DMA data written
679 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
680 unsigned int *buffer_offset)
682 unsigned int i, next_i, last = ctx->last_buffer_index;
683 __le16 res_count, next_res_count;
685 i = ar_first_buffer_index(ctx);
686 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
688 /* A buffer that is not yet completely filled must be the last one. */
689 while (i != last && res_count == 0) {
691 /* Peek at the next descriptor. */
692 next_i = ar_next_buffer_index(i);
693 rmb(); /* read descriptors in order */
694 next_res_count = ACCESS_ONCE(
695 ctx->descriptors[next_i].res_count);
697 * If the next descriptor is still empty, we must stop at this
700 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
702 * The exception is when the DMA data for one packet is
703 * split over three buffers; in this case, the middle
704 * buffer's descriptor might be never updated by the
705 * controller and look still empty, and we have to peek
708 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
709 next_i = ar_next_buffer_index(next_i);
711 next_res_count = ACCESS_ONCE(
712 ctx->descriptors[next_i].res_count);
713 if (next_res_count != cpu_to_le16(PAGE_SIZE))
714 goto next_buffer_is_active;
720 next_buffer_is_active:
722 res_count = next_res_count;
725 rmb(); /* read res_count before the DMA data */
727 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
728 if (*buffer_offset > PAGE_SIZE) {
730 ar_context_abort(ctx, "corrupted descriptor");
736 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
737 unsigned int end_buffer_index,
738 unsigned int end_buffer_offset)
742 i = ar_first_buffer_index(ctx);
743 while (i != end_buffer_index) {
744 dma_sync_single_for_cpu(ctx->ohci->card.device,
745 ar_buffer_bus(ctx, i),
746 PAGE_SIZE, DMA_FROM_DEVICE);
747 i = ar_next_buffer_index(i);
749 if (end_buffer_offset > 0)
750 dma_sync_single_for_cpu(ctx->ohci->card.device,
751 ar_buffer_bus(ctx, i),
752 end_buffer_offset, DMA_FROM_DEVICE);
755 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
756 #define cond_le32_to_cpu(v) \
757 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
759 #define cond_le32_to_cpu(v) le32_to_cpu(v)
762 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
764 struct fw_ohci *ohci = ctx->ohci;
766 u32 status, length, tcode;
769 p.header[0] = cond_le32_to_cpu(buffer[0]);
770 p.header[1] = cond_le32_to_cpu(buffer[1]);
771 p.header[2] = cond_le32_to_cpu(buffer[2]);
773 tcode = (p.header[0] >> 4) & 0x0f;
775 case TCODE_WRITE_QUADLET_REQUEST:
776 case TCODE_READ_QUADLET_RESPONSE:
777 p.header[3] = (__force __u32) buffer[3];
778 p.header_length = 16;
779 p.payload_length = 0;
782 case TCODE_READ_BLOCK_REQUEST :
783 p.header[3] = cond_le32_to_cpu(buffer[3]);
784 p.header_length = 16;
785 p.payload_length = 0;
788 case TCODE_WRITE_BLOCK_REQUEST:
789 case TCODE_READ_BLOCK_RESPONSE:
790 case TCODE_LOCK_REQUEST:
791 case TCODE_LOCK_RESPONSE:
792 p.header[3] = cond_le32_to_cpu(buffer[3]);
793 p.header_length = 16;
794 p.payload_length = p.header[3] >> 16;
795 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
796 ar_context_abort(ctx, "invalid packet length");
801 case TCODE_WRITE_RESPONSE:
802 case TCODE_READ_QUADLET_REQUEST:
803 case OHCI_TCODE_PHY_PACKET:
804 p.header_length = 12;
805 p.payload_length = 0;
809 ar_context_abort(ctx, "invalid tcode");
813 p.payload = (void *) buffer + p.header_length;
815 /* FIXME: What to do about evt_* errors? */
816 length = (p.header_length + p.payload_length + 3) / 4;
817 status = cond_le32_to_cpu(buffer[length]);
818 evt = (status >> 16) & 0x1f;
821 p.speed = (status >> 21) & 0x7;
822 p.timestamp = status & 0xffff;
823 p.generation = ohci->request_generation;
825 log_ar_at_event('R', p.speed, p.header, evt);
828 * Several controllers, notably from NEC and VIA, forget to
829 * write ack_complete status at PHY packet reception.
831 if (evt == OHCI1394_evt_no_status &&
832 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
833 p.ack = ACK_COMPLETE;
836 * The OHCI bus reset handler synthesizes a PHY packet with
837 * the new generation number when a bus reset happens (see
838 * section 8.4.2.3). This helps us determine when a request
839 * was received and make sure we send the response in the same
840 * generation. We only need this for requests; for responses
841 * we use the unique tlabel for finding the matching
844 * Alas some chips sometimes emit bus reset packets with a
845 * wrong generation. We set the correct generation for these
846 * at a slightly incorrect time (in bus_reset_tasklet).
848 if (evt == OHCI1394_evt_bus_reset) {
849 if (!(ohci->quirks & QUIRK_RESET_PACKET))
850 ohci->request_generation = (p.header[2] >> 16) & 0xff;
851 } else if (ctx == &ohci->ar_request_ctx) {
852 fw_core_handle_request(&ohci->card, &p);
854 fw_core_handle_response(&ohci->card, &p);
857 return buffer + length + 1;
860 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
865 next = handle_ar_packet(ctx, p);
874 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
878 i = ar_first_buffer_index(ctx);
879 while (i != end_buffer) {
880 dma_sync_single_for_device(ctx->ohci->card.device,
881 ar_buffer_bus(ctx, i),
882 PAGE_SIZE, DMA_FROM_DEVICE);
883 ar_context_link_page(ctx, i);
884 i = ar_next_buffer_index(i);
888 static void ar_context_tasklet(unsigned long data)
890 struct ar_context *ctx = (struct ar_context *)data;
891 unsigned int end_buffer_index, end_buffer_offset;
898 end_buffer_index = ar_search_last_active_buffer(ctx,
900 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
901 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
903 if (end_buffer_index < ar_first_buffer_index(ctx)) {
905 * The filled part of the overall buffer wraps around; handle
906 * all packets up to the buffer end here. If the last packet
907 * wraps around, its tail will be visible after the buffer end
908 * because the buffer start pages are mapped there again.
910 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
911 p = handle_ar_packets(ctx, p, buffer_end);
914 /* adjust p to point back into the actual buffer */
915 p -= AR_BUFFERS * PAGE_SIZE;
918 p = handle_ar_packets(ctx, p, end);
921 ar_context_abort(ctx, "inconsistent descriptor");
926 ar_recycle_buffers(ctx, end_buffer_index);
934 static int ar_context_init(struct ar_context *ctx,
935 struct fw_ohci *ohci, u32 regs)
939 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
940 struct descriptor *d;
944 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
946 for (i = 0; i < AR_BUFFERS; i++) {
947 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
950 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
951 0, PAGE_SIZE, DMA_FROM_DEVICE);
952 if (dma_mapping_error(ohci->card.device, dma_addr)) {
953 __free_page(ctx->pages[i]);
954 ctx->pages[i] = NULL;
957 set_page_private(ctx->pages[i], dma_addr);
960 for (i = 0; i < AR_BUFFERS; i++)
961 pages[i] = ctx->pages[i];
962 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
963 pages[AR_BUFFERS + i] = ctx->pages[i];
964 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
970 dma_alloc_coherent(ohci->card.device,
971 AR_BUFFERS * sizeof(struct descriptor),
972 &ctx->descriptors_bus,
974 if (!ctx->descriptors)
977 for (i = 0; i < AR_BUFFERS; i++) {
978 d = &ctx->descriptors[i];
979 d->req_count = cpu_to_le16(PAGE_SIZE);
980 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
982 DESCRIPTOR_BRANCH_ALWAYS);
983 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
984 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
985 ar_next_buffer_index(i) * sizeof(struct descriptor));
991 ar_context_release(ctx);
996 static void ar_context_run(struct ar_context *ctx)
1000 for (i = 0; i < AR_BUFFERS; i++)
1001 ar_context_link_page(ctx, i);
1003 ctx->pointer = ctx->buffer;
1005 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1006 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1007 flush_writes(ctx->ohci);
1010 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1014 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
1015 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
1017 /* figure out which descriptor the branch address goes in */
1018 if (z == 2 && (b == 3 || key == 2))
1024 static void context_tasklet(unsigned long data)
1026 struct context *ctx = (struct context *) data;
1027 struct descriptor *d, *last;
1030 struct descriptor_buffer *desc;
1032 desc = list_entry(ctx->buffer_list.next,
1033 struct descriptor_buffer, list);
1035 while (last->branch_address != 0) {
1036 struct descriptor_buffer *old_desc = desc;
1037 address = le32_to_cpu(last->branch_address);
1041 /* If the branch address points to a buffer outside of the
1042 * current buffer, advance to the next buffer. */
1043 if (address < desc->buffer_bus ||
1044 address >= desc->buffer_bus + desc->used)
1045 desc = list_entry(desc->list.next,
1046 struct descriptor_buffer, list);
1047 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1048 last = find_branch_descriptor(d, z);
1050 if (!ctx->callback(ctx, d, last))
1053 if (old_desc != desc) {
1054 /* If we've advanced to the next buffer, move the
1055 * previous buffer to the free list. */
1056 unsigned long flags;
1058 spin_lock_irqsave(&ctx->ohci->lock, flags);
1059 list_move_tail(&old_desc->list, &ctx->buffer_list);
1060 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1067 * Allocate a new buffer and add it to the list of free buffers for this
1068 * context. Must be called with ohci->lock held.
1070 static int context_add_buffer(struct context *ctx)
1072 struct descriptor_buffer *desc;
1073 dma_addr_t uninitialized_var(bus_addr);
1077 * 16MB of descriptors should be far more than enough for any DMA
1078 * program. This will catch run-away userspace or DoS attacks.
1080 if (ctx->total_allocation >= 16*1024*1024)
1083 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1084 &bus_addr, GFP_ATOMIC);
1088 offset = (void *)&desc->buffer - (void *)desc;
1089 desc->buffer_size = PAGE_SIZE - offset;
1090 desc->buffer_bus = bus_addr + offset;
1093 list_add_tail(&desc->list, &ctx->buffer_list);
1094 ctx->total_allocation += PAGE_SIZE;
1099 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1100 u32 regs, descriptor_callback_t callback)
1104 ctx->total_allocation = 0;
1106 INIT_LIST_HEAD(&ctx->buffer_list);
1107 if (context_add_buffer(ctx) < 0)
1110 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1111 struct descriptor_buffer, list);
1113 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1114 ctx->callback = callback;
1117 * We put a dummy descriptor in the buffer that has a NULL
1118 * branch address and looks like it's been sent. That way we
1119 * have a descriptor to append DMA programs to.
1121 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1122 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1123 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1124 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1125 ctx->last = ctx->buffer_tail->buffer;
1126 ctx->prev = ctx->buffer_tail->buffer;
1131 static void context_release(struct context *ctx)
1133 struct fw_card *card = &ctx->ohci->card;
1134 struct descriptor_buffer *desc, *tmp;
1136 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1137 dma_free_coherent(card->device, PAGE_SIZE, desc,
1139 ((void *)&desc->buffer - (void *)desc));
1142 /* Must be called with ohci->lock held */
1143 static struct descriptor *context_get_descriptors(struct context *ctx,
1144 int z, dma_addr_t *d_bus)
1146 struct descriptor *d = NULL;
1147 struct descriptor_buffer *desc = ctx->buffer_tail;
1149 if (z * sizeof(*d) > desc->buffer_size)
1152 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1153 /* No room for the descriptor in this buffer, so advance to the
1156 if (desc->list.next == &ctx->buffer_list) {
1157 /* If there is no free buffer next in the list,
1159 if (context_add_buffer(ctx) < 0)
1162 desc = list_entry(desc->list.next,
1163 struct descriptor_buffer, list);
1164 ctx->buffer_tail = desc;
1167 d = desc->buffer + desc->used / sizeof(*d);
1168 memset(d, 0, z * sizeof(*d));
1169 *d_bus = desc->buffer_bus + desc->used;
1174 static void context_run(struct context *ctx, u32 extra)
1176 struct fw_ohci *ohci = ctx->ohci;
1178 reg_write(ohci, COMMAND_PTR(ctx->regs),
1179 le32_to_cpu(ctx->last->branch_address));
1180 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1181 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1185 static void context_append(struct context *ctx,
1186 struct descriptor *d, int z, int extra)
1189 struct descriptor_buffer *desc = ctx->buffer_tail;
1191 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1193 desc->used += (z + extra) * sizeof(*d);
1195 wmb(); /* finish init of new descriptors before branch_address update */
1196 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1197 ctx->prev = find_branch_descriptor(d, z);
1199 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1200 flush_writes(ctx->ohci);
1203 static void context_stop(struct context *ctx)
1208 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1209 flush_writes(ctx->ohci);
1211 for (i = 0; i < 10; i++) {
1212 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1213 if ((reg & CONTEXT_ACTIVE) == 0)
1218 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1221 struct driver_data {
1222 struct fw_packet *packet;
1226 * This function apppends a packet to the DMA queue for transmission.
1227 * Must always be called with the ochi->lock held to ensure proper
1228 * generation handling and locking around packet queue manipulation.
1230 static int at_context_queue_packet(struct context *ctx,
1231 struct fw_packet *packet)
1233 struct fw_ohci *ohci = ctx->ohci;
1234 dma_addr_t d_bus, uninitialized_var(payload_bus);
1235 struct driver_data *driver_data;
1236 struct descriptor *d, *last;
1241 d = context_get_descriptors(ctx, 4, &d_bus);
1243 packet->ack = RCODE_SEND_ERROR;
1247 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1248 d[0].res_count = cpu_to_le16(packet->timestamp);
1251 * The DMA format for asyncronous link packets is different
1252 * from the IEEE1394 layout, so shift the fields around
1253 * accordingly. If header_length is 8, it's a PHY packet, to
1254 * which we need to prepend an extra quadlet.
1257 header = (__le32 *) &d[1];
1258 switch (packet->header_length) {
1261 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1262 (packet->speed << 16));
1263 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1264 (packet->header[0] & 0xffff0000));
1265 header[2] = cpu_to_le32(packet->header[2]);
1267 tcode = (packet->header[0] >> 4) & 0x0f;
1268 if (TCODE_IS_BLOCK_PACKET(tcode))
1269 header[3] = cpu_to_le32(packet->header[3]);
1271 header[3] = (__force __le32) packet->header[3];
1273 d[0].req_count = cpu_to_le16(packet->header_length);
1277 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1278 (packet->speed << 16));
1279 header[1] = cpu_to_le32(packet->header[0]);
1280 header[2] = cpu_to_le32(packet->header[1]);
1281 d[0].req_count = cpu_to_le16(12);
1283 if (is_ping_packet(packet->header))
1284 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1288 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1289 (packet->speed << 16));
1290 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1291 d[0].req_count = cpu_to_le16(8);
1296 packet->ack = RCODE_SEND_ERROR;
1300 driver_data = (struct driver_data *) &d[3];
1301 driver_data->packet = packet;
1302 packet->driver_data = driver_data;
1304 if (packet->payload_length > 0) {
1306 dma_map_single(ohci->card.device, packet->payload,
1307 packet->payload_length, DMA_TO_DEVICE);
1308 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1309 packet->ack = RCODE_SEND_ERROR;
1312 packet->payload_bus = payload_bus;
1313 packet->payload_mapped = true;
1315 d[2].req_count = cpu_to_le16(packet->payload_length);
1316 d[2].data_address = cpu_to_le32(payload_bus);
1324 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1325 DESCRIPTOR_IRQ_ALWAYS |
1326 DESCRIPTOR_BRANCH_ALWAYS);
1329 * If the controller and packet generations don't match, we need to
1330 * bail out and try again. If IntEvent.busReset is set, the AT context
1331 * is halted, so appending to the context and trying to run it is
1332 * futile. Most controllers do the right thing and just flush the AT
1333 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1334 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1335 * up stalling out. So we just bail out in software and try again
1336 * later, and everyone is happy.
1337 * FIXME: Document how the locking works.
1339 if (ohci->generation != packet->generation ||
1340 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1341 if (packet->payload_mapped)
1342 dma_unmap_single(ohci->card.device, payload_bus,
1343 packet->payload_length, DMA_TO_DEVICE);
1344 packet->ack = RCODE_GENERATION;
1348 context_append(ctx, d, z, 4 - z);
1350 /* If the context isn't already running, start it up. */
1351 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1352 if ((reg & CONTEXT_RUN) == 0)
1353 context_run(ctx, 0);
1358 static int handle_at_packet(struct context *context,
1359 struct descriptor *d,
1360 struct descriptor *last)
1362 struct driver_data *driver_data;
1363 struct fw_packet *packet;
1364 struct fw_ohci *ohci = context->ohci;
1367 if (last->transfer_status == 0)
1368 /* This descriptor isn't done yet, stop iteration. */
1371 driver_data = (struct driver_data *) &d[3];
1372 packet = driver_data->packet;
1374 /* This packet was cancelled, just continue. */
1377 if (packet->payload_mapped)
1378 dma_unmap_single(ohci->card.device, packet->payload_bus,
1379 packet->payload_length, DMA_TO_DEVICE);
1381 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1382 packet->timestamp = le16_to_cpu(last->res_count);
1384 log_ar_at_event('T', packet->speed, packet->header, evt);
1387 case OHCI1394_evt_timeout:
1388 /* Async response transmit timed out. */
1389 packet->ack = RCODE_CANCELLED;
1392 case OHCI1394_evt_flushed:
1394 * The packet was flushed should give same error as
1395 * when we try to use a stale generation count.
1397 packet->ack = RCODE_GENERATION;
1400 case OHCI1394_evt_missing_ack:
1402 * Using a valid (current) generation count, but the
1403 * node is not on the bus or not sending acks.
1405 packet->ack = RCODE_NO_ACK;
1408 case ACK_COMPLETE + 0x10:
1409 case ACK_PENDING + 0x10:
1410 case ACK_BUSY_X + 0x10:
1411 case ACK_BUSY_A + 0x10:
1412 case ACK_BUSY_B + 0x10:
1413 case ACK_DATA_ERROR + 0x10:
1414 case ACK_TYPE_ERROR + 0x10:
1415 packet->ack = evt - 0x10;
1419 packet->ack = RCODE_SEND_ERROR;
1423 packet->callback(packet, &ohci->card, packet->ack);
1428 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1429 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1430 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1431 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1432 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1434 static void handle_local_rom(struct fw_ohci *ohci,
1435 struct fw_packet *packet, u32 csr)
1437 struct fw_packet response;
1438 int tcode, length, i;
1440 tcode = HEADER_GET_TCODE(packet->header[0]);
1441 if (TCODE_IS_BLOCK_PACKET(tcode))
1442 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1446 i = csr - CSR_CONFIG_ROM;
1447 if (i + length > CONFIG_ROM_SIZE) {
1448 fw_fill_response(&response, packet->header,
1449 RCODE_ADDRESS_ERROR, NULL, 0);
1450 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1451 fw_fill_response(&response, packet->header,
1452 RCODE_TYPE_ERROR, NULL, 0);
1454 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1455 (void *) ohci->config_rom + i, length);
1458 fw_core_handle_response(&ohci->card, &response);
1461 static void handle_local_lock(struct fw_ohci *ohci,
1462 struct fw_packet *packet, u32 csr)
1464 struct fw_packet response;
1465 int tcode, length, ext_tcode, sel, try;
1466 __be32 *payload, lock_old;
1467 u32 lock_arg, lock_data;
1469 tcode = HEADER_GET_TCODE(packet->header[0]);
1470 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1471 payload = packet->payload;
1472 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1474 if (tcode == TCODE_LOCK_REQUEST &&
1475 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1476 lock_arg = be32_to_cpu(payload[0]);
1477 lock_data = be32_to_cpu(payload[1]);
1478 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1482 fw_fill_response(&response, packet->header,
1483 RCODE_TYPE_ERROR, NULL, 0);
1487 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1488 reg_write(ohci, OHCI1394_CSRData, lock_data);
1489 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1490 reg_write(ohci, OHCI1394_CSRControl, sel);
1492 for (try = 0; try < 20; try++)
1493 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1494 lock_old = cpu_to_be32(reg_read(ohci,
1496 fw_fill_response(&response, packet->header,
1498 &lock_old, sizeof(lock_old));
1502 fw_error("swap not done (CSR lock timeout)\n");
1503 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1506 fw_core_handle_response(&ohci->card, &response);
1509 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1513 if (ctx == &ctx->ohci->at_request_ctx) {
1514 packet->ack = ACK_PENDING;
1515 packet->callback(packet, &ctx->ohci->card, packet->ack);
1519 ((unsigned long long)
1520 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1522 csr = offset - CSR_REGISTER_BASE;
1524 /* Handle config rom reads. */
1525 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1526 handle_local_rom(ctx->ohci, packet, csr);
1528 case CSR_BUS_MANAGER_ID:
1529 case CSR_BANDWIDTH_AVAILABLE:
1530 case CSR_CHANNELS_AVAILABLE_HI:
1531 case CSR_CHANNELS_AVAILABLE_LO:
1532 handle_local_lock(ctx->ohci, packet, csr);
1535 if (ctx == &ctx->ohci->at_request_ctx)
1536 fw_core_handle_request(&ctx->ohci->card, packet);
1538 fw_core_handle_response(&ctx->ohci->card, packet);
1542 if (ctx == &ctx->ohci->at_response_ctx) {
1543 packet->ack = ACK_COMPLETE;
1544 packet->callback(packet, &ctx->ohci->card, packet->ack);
1548 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1550 unsigned long flags;
1553 spin_lock_irqsave(&ctx->ohci->lock, flags);
1555 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1556 ctx->ohci->generation == packet->generation) {
1557 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1558 handle_local_request(ctx, packet);
1562 ret = at_context_queue_packet(ctx, packet);
1563 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1566 packet->callback(packet, &ctx->ohci->card, packet->ack);
1570 static u32 cycle_timer_ticks(u32 cycle_timer)
1574 ticks = cycle_timer & 0xfff;
1575 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1576 ticks += (3072 * 8000) * (cycle_timer >> 25);
1582 * Some controllers exhibit one or more of the following bugs when updating the
1583 * iso cycle timer register:
1584 * - When the lowest six bits are wrapping around to zero, a read that happens
1585 * at the same time will return garbage in the lowest ten bits.
1586 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1587 * not incremented for about 60 ns.
1588 * - Occasionally, the entire register reads zero.
1590 * To catch these, we read the register three times and ensure that the
1591 * difference between each two consecutive reads is approximately the same, i.e.
1592 * less than twice the other. Furthermore, any negative difference indicates an
1593 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1594 * execute, so we have enough precision to compute the ratio of the differences.)
1596 static u32 get_cycle_time(struct fw_ohci *ohci)
1603 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1605 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1608 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1612 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1613 t0 = cycle_timer_ticks(c0);
1614 t1 = cycle_timer_ticks(c1);
1615 t2 = cycle_timer_ticks(c2);
1618 } while ((diff01 <= 0 || diff12 <= 0 ||
1619 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1627 * This function has to be called at least every 64 seconds. The bus_time
1628 * field stores not only the upper 25 bits of the BUS_TIME register but also
1629 * the most significant bit of the cycle timer in bit 6 so that we can detect
1630 * changes in this bit.
1632 static u32 update_bus_time(struct fw_ohci *ohci)
1634 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1636 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1637 ohci->bus_time += 0x40;
1639 return ohci->bus_time | cycle_time_seconds;
1642 static void bus_reset_tasklet(unsigned long data)
1644 struct fw_ohci *ohci = (struct fw_ohci *)data;
1645 int self_id_count, i, j, reg;
1646 int generation, new_generation;
1647 unsigned long flags;
1648 void *free_rom = NULL;
1649 dma_addr_t free_rom_bus = 0;
1652 reg = reg_read(ohci, OHCI1394_NodeID);
1653 if (!(reg & OHCI1394_NodeID_idValid)) {
1654 fw_notify("node ID not valid, new bus reset in progress\n");
1657 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1658 fw_notify("malconfigured bus\n");
1661 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1662 OHCI1394_NodeID_nodeNumber);
1664 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1665 if (!(ohci->is_root && is_new_root))
1666 reg_write(ohci, OHCI1394_LinkControlSet,
1667 OHCI1394_LinkControl_cycleMaster);
1668 ohci->is_root = is_new_root;
1670 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1671 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1672 fw_notify("inconsistent self IDs\n");
1676 * The count in the SelfIDCount register is the number of
1677 * bytes in the self ID receive buffer. Since we also receive
1678 * the inverted quadlets and a header quadlet, we shift one
1679 * bit extra to get the actual number of self IDs.
1681 self_id_count = (reg >> 3) & 0xff;
1682 if (self_id_count == 0 || self_id_count > 252) {
1683 fw_notify("inconsistent self IDs\n");
1686 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1689 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1690 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1691 fw_notify("inconsistent self IDs\n");
1694 ohci->self_id_buffer[j] =
1695 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1700 * Check the consistency of the self IDs we just read. The
1701 * problem we face is that a new bus reset can start while we
1702 * read out the self IDs from the DMA buffer. If this happens,
1703 * the DMA buffer will be overwritten with new self IDs and we
1704 * will read out inconsistent data. The OHCI specification
1705 * (section 11.2) recommends a technique similar to
1706 * linux/seqlock.h, where we remember the generation of the
1707 * self IDs in the buffer before reading them out and compare
1708 * it to the current generation after reading them out. If
1709 * the two generations match we know we have a consistent set
1713 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1714 if (new_generation != generation) {
1715 fw_notify("recursive bus reset detected, "
1716 "discarding self ids\n");
1720 /* FIXME: Document how the locking works. */
1721 spin_lock_irqsave(&ohci->lock, flags);
1723 ohci->generation = generation;
1724 context_stop(&ohci->at_request_ctx);
1725 context_stop(&ohci->at_response_ctx);
1726 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1728 if (ohci->quirks & QUIRK_RESET_PACKET)
1729 ohci->request_generation = generation;
1732 * This next bit is unrelated to the AT context stuff but we
1733 * have to do it under the spinlock also. If a new config rom
1734 * was set up before this reset, the old one is now no longer
1735 * in use and we can free it. Update the config rom pointers
1736 * to point to the current config rom and clear the
1737 * next_config_rom pointer so a new update can take place.
1740 if (ohci->next_config_rom != NULL) {
1741 if (ohci->next_config_rom != ohci->config_rom) {
1742 free_rom = ohci->config_rom;
1743 free_rom_bus = ohci->config_rom_bus;
1745 ohci->config_rom = ohci->next_config_rom;
1746 ohci->config_rom_bus = ohci->next_config_rom_bus;
1747 ohci->next_config_rom = NULL;
1750 * Restore config_rom image and manually update
1751 * config_rom registers. Writing the header quadlet
1752 * will indicate that the config rom is ready, so we
1755 reg_write(ohci, OHCI1394_BusOptions,
1756 be32_to_cpu(ohci->config_rom[2]));
1757 ohci->config_rom[0] = ohci->next_header;
1758 reg_write(ohci, OHCI1394_ConfigROMhdr,
1759 be32_to_cpu(ohci->next_header));
1762 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1763 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1764 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1767 spin_unlock_irqrestore(&ohci->lock, flags);
1770 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1771 free_rom, free_rom_bus);
1773 log_selfids(ohci->node_id, generation,
1774 self_id_count, ohci->self_id_buffer);
1776 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1777 self_id_count, ohci->self_id_buffer,
1778 ohci->csr_state_setclear_abdicate);
1779 ohci->csr_state_setclear_abdicate = false;
1782 static irqreturn_t irq_handler(int irq, void *data)
1784 struct fw_ohci *ohci = data;
1785 u32 event, iso_event;
1788 event = reg_read(ohci, OHCI1394_IntEventClear);
1790 if (!event || !~event)
1793 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1794 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1797 if (event & OHCI1394_selfIDComplete)
1798 tasklet_schedule(&ohci->bus_reset_tasklet);
1800 if (event & OHCI1394_RQPkt)
1801 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1803 if (event & OHCI1394_RSPkt)
1804 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1806 if (event & OHCI1394_reqTxComplete)
1807 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1809 if (event & OHCI1394_respTxComplete)
1810 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1812 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1813 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1816 i = ffs(iso_event) - 1;
1817 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1818 iso_event &= ~(1 << i);
1821 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1822 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1825 i = ffs(iso_event) - 1;
1826 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1827 iso_event &= ~(1 << i);
1830 if (unlikely(event & OHCI1394_regAccessFail))
1831 fw_error("Register access failure - "
1832 "please notify linux1394-devel@lists.sf.net\n");
1834 if (unlikely(event & OHCI1394_postedWriteErr))
1835 fw_error("PCI posted write error\n");
1837 if (unlikely(event & OHCI1394_cycleTooLong)) {
1838 if (printk_ratelimit())
1839 fw_notify("isochronous cycle too long\n");
1840 reg_write(ohci, OHCI1394_LinkControlSet,
1841 OHCI1394_LinkControl_cycleMaster);
1844 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1846 * We need to clear this event bit in order to make
1847 * cycleMatch isochronous I/O work. In theory we should
1848 * stop active cycleMatch iso contexts now and restart
1849 * them at least two cycles later. (FIXME?)
1851 if (printk_ratelimit())
1852 fw_notify("isochronous cycle inconsistent\n");
1855 if (event & OHCI1394_cycle64Seconds) {
1856 spin_lock(&ohci->lock);
1857 update_bus_time(ohci);
1858 spin_unlock(&ohci->lock);
1865 static int software_reset(struct fw_ohci *ohci)
1869 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1871 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1872 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1873 OHCI1394_HCControl_softReset) == 0)
1881 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1883 size_t size = length * 4;
1885 memcpy(dest, src, size);
1886 if (size < CONFIG_ROM_SIZE)
1887 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1890 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1893 int ret, clear, set, offset;
1895 /* Check if the driver should configure link and PHY. */
1896 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1897 OHCI1394_HCControl_programPhyEnable))
1900 /* Paranoia: check whether the PHY supports 1394a, too. */
1901 enable_1394a = false;
1902 ret = read_phy_reg(ohci, 2);
1905 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1906 ret = read_paged_phy_reg(ohci, 1, 8);
1910 enable_1394a = true;
1913 if (ohci->quirks & QUIRK_NO_1394A)
1914 enable_1394a = false;
1916 /* Configure PHY and link consistently. */
1919 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1921 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1924 ret = update_phy_reg(ohci, 5, clear, set);
1929 offset = OHCI1394_HCControlSet;
1931 offset = OHCI1394_HCControlClear;
1932 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1934 /* Clean up: configuration has been taken care of. */
1935 reg_write(ohci, OHCI1394_HCControlClear,
1936 OHCI1394_HCControl_programPhyEnable);
1941 static int ohci_enable(struct fw_card *card,
1942 const __be32 *config_rom, size_t length)
1944 struct fw_ohci *ohci = fw_ohci(card);
1945 struct pci_dev *dev = to_pci_dev(card->device);
1946 u32 lps, seconds, version, irqs;
1949 if (software_reset(ohci)) {
1950 fw_error("Failed to reset ohci card.\n");
1955 * Now enable LPS, which we need in order to start accessing
1956 * most of the registers. In fact, on some cards (ALI M5251),
1957 * accessing registers in the SClk domain without LPS enabled
1958 * will lock up the machine. Wait 50msec to make sure we have
1959 * full link enabled. However, with some cards (well, at least
1960 * a JMicron PCIe card), we have to try again sometimes.
1962 reg_write(ohci, OHCI1394_HCControlSet,
1963 OHCI1394_HCControl_LPS |
1964 OHCI1394_HCControl_postedWriteEnable);
1967 for (lps = 0, i = 0; !lps && i < 3; i++) {
1969 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1970 OHCI1394_HCControl_LPS;
1974 fw_error("Failed to set Link Power Status\n");
1978 reg_write(ohci, OHCI1394_HCControlClear,
1979 OHCI1394_HCControl_noByteSwapData);
1981 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1982 reg_write(ohci, OHCI1394_LinkControlSet,
1983 OHCI1394_LinkControl_rcvSelfID |
1984 OHCI1394_LinkControl_rcvPhyPkt |
1985 OHCI1394_LinkControl_cycleTimerEnable |
1986 OHCI1394_LinkControl_cycleMaster);
1988 reg_write(ohci, OHCI1394_ATRetries,
1989 OHCI1394_MAX_AT_REQ_RETRIES |
1990 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1991 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1994 seconds = lower_32_bits(get_seconds());
1995 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1996 ohci->bus_time = seconds & ~0x3f;
1998 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1999 if (version >= OHCI_VERSION_1_1) {
2000 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2002 card->broadcast_channel_auto_allocated = true;
2005 /* Get implemented bits of the priority arbitration request counter. */
2006 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2007 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2008 reg_write(ohci, OHCI1394_FairnessControl, 0);
2009 card->priority_budget_implemented = ohci->pri_req_max != 0;
2011 ar_context_run(&ohci->ar_request_ctx);
2012 ar_context_run(&ohci->ar_response_ctx);
2014 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2015 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2016 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2018 ret = configure_1394a_enhancements(ohci);
2022 /* Activate link_on bit and contender bit in our self ID packets.*/
2023 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2028 * When the link is not yet enabled, the atomic config rom
2029 * update mechanism described below in ohci_set_config_rom()
2030 * is not active. We have to update ConfigRomHeader and
2031 * BusOptions manually, and the write to ConfigROMmap takes
2032 * effect immediately. We tie this to the enabling of the
2033 * link, so we have a valid config rom before enabling - the
2034 * OHCI requires that ConfigROMhdr and BusOptions have valid
2035 * values before enabling.
2037 * However, when the ConfigROMmap is written, some controllers
2038 * always read back quadlets 0 and 2 from the config rom to
2039 * the ConfigRomHeader and BusOptions registers on bus reset.
2040 * They shouldn't do that in this initial case where the link
2041 * isn't enabled. This means we have to use the same
2042 * workaround here, setting the bus header to 0 and then write
2043 * the right values in the bus reset tasklet.
2047 ohci->next_config_rom =
2048 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2049 &ohci->next_config_rom_bus,
2051 if (ohci->next_config_rom == NULL)
2054 copy_config_rom(ohci->next_config_rom, config_rom, length);
2057 * In the suspend case, config_rom is NULL, which
2058 * means that we just reuse the old config rom.
2060 ohci->next_config_rom = ohci->config_rom;
2061 ohci->next_config_rom_bus = ohci->config_rom_bus;
2064 ohci->next_header = ohci->next_config_rom[0];
2065 ohci->next_config_rom[0] = 0;
2066 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2067 reg_write(ohci, OHCI1394_BusOptions,
2068 be32_to_cpu(ohci->next_config_rom[2]));
2069 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2071 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2073 if (!(ohci->quirks & QUIRK_NO_MSI))
2074 pci_enable_msi(dev);
2075 if (request_irq(dev->irq, irq_handler,
2076 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2077 ohci_driver_name, ohci)) {
2078 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2079 pci_disable_msi(dev);
2080 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2081 ohci->config_rom, ohci->config_rom_bus);
2085 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2086 OHCI1394_RQPkt | OHCI1394_RSPkt |
2087 OHCI1394_isochTx | OHCI1394_isochRx |
2088 OHCI1394_postedWriteErr |
2089 OHCI1394_selfIDComplete |
2090 OHCI1394_regAccessFail |
2091 OHCI1394_cycle64Seconds |
2092 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
2093 OHCI1394_masterIntEnable;
2094 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2095 irqs |= OHCI1394_busReset;
2096 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2098 reg_write(ohci, OHCI1394_HCControlSet,
2099 OHCI1394_HCControl_linkEnable |
2100 OHCI1394_HCControl_BIBimageValid);
2103 /* We are ready to go, reset bus to finish initialization. */
2104 fw_schedule_bus_reset(&ohci->card, false, true);
2109 static int ohci_set_config_rom(struct fw_card *card,
2110 const __be32 *config_rom, size_t length)
2112 struct fw_ohci *ohci;
2113 unsigned long flags;
2115 __be32 *next_config_rom;
2116 dma_addr_t uninitialized_var(next_config_rom_bus);
2118 ohci = fw_ohci(card);
2121 * When the OHCI controller is enabled, the config rom update
2122 * mechanism is a bit tricky, but easy enough to use. See
2123 * section 5.5.6 in the OHCI specification.
2125 * The OHCI controller caches the new config rom address in a
2126 * shadow register (ConfigROMmapNext) and needs a bus reset
2127 * for the changes to take place. When the bus reset is
2128 * detected, the controller loads the new values for the
2129 * ConfigRomHeader and BusOptions registers from the specified
2130 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2131 * shadow register. All automatically and atomically.
2133 * Now, there's a twist to this story. The automatic load of
2134 * ConfigRomHeader and BusOptions doesn't honor the
2135 * noByteSwapData bit, so with a be32 config rom, the
2136 * controller will load be32 values in to these registers
2137 * during the atomic update, even on litte endian
2138 * architectures. The workaround we use is to put a 0 in the
2139 * header quadlet; 0 is endian agnostic and means that the
2140 * config rom isn't ready yet. In the bus reset tasklet we
2141 * then set up the real values for the two registers.
2143 * We use ohci->lock to avoid racing with the code that sets
2144 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2148 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2149 &next_config_rom_bus, GFP_KERNEL);
2150 if (next_config_rom == NULL)
2153 spin_lock_irqsave(&ohci->lock, flags);
2155 if (ohci->next_config_rom == NULL) {
2156 ohci->next_config_rom = next_config_rom;
2157 ohci->next_config_rom_bus = next_config_rom_bus;
2159 copy_config_rom(ohci->next_config_rom, config_rom, length);
2161 ohci->next_header = config_rom[0];
2162 ohci->next_config_rom[0] = 0;
2164 reg_write(ohci, OHCI1394_ConfigROMmap,
2165 ohci->next_config_rom_bus);
2169 spin_unlock_irqrestore(&ohci->lock, flags);
2172 * Now initiate a bus reset to have the changes take
2173 * effect. We clean up the old config rom memory and DMA
2174 * mappings in the bus reset tasklet, since the OHCI
2175 * controller could need to access it before the bus reset
2179 fw_schedule_bus_reset(&ohci->card, true, true);
2181 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2182 next_config_rom, next_config_rom_bus);
2187 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2189 struct fw_ohci *ohci = fw_ohci(card);
2191 at_context_transmit(&ohci->at_request_ctx, packet);
2194 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2196 struct fw_ohci *ohci = fw_ohci(card);
2198 at_context_transmit(&ohci->at_response_ctx, packet);
2201 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2203 struct fw_ohci *ohci = fw_ohci(card);
2204 struct context *ctx = &ohci->at_request_ctx;
2205 struct driver_data *driver_data = packet->driver_data;
2208 tasklet_disable(&ctx->tasklet);
2210 if (packet->ack != 0)
2213 if (packet->payload_mapped)
2214 dma_unmap_single(ohci->card.device, packet->payload_bus,
2215 packet->payload_length, DMA_TO_DEVICE);
2217 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2218 driver_data->packet = NULL;
2219 packet->ack = RCODE_CANCELLED;
2220 packet->callback(packet, &ohci->card, packet->ack);
2223 tasklet_enable(&ctx->tasklet);
2228 static int ohci_enable_phys_dma(struct fw_card *card,
2229 int node_id, int generation)
2231 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2234 struct fw_ohci *ohci = fw_ohci(card);
2235 unsigned long flags;
2239 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2240 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2243 spin_lock_irqsave(&ohci->lock, flags);
2245 if (ohci->generation != generation) {
2251 * Note, if the node ID contains a non-local bus ID, physical DMA is
2252 * enabled for _all_ nodes on remote buses.
2255 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2257 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2259 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2263 spin_unlock_irqrestore(&ohci->lock, flags);
2266 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2269 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2271 struct fw_ohci *ohci = fw_ohci(card);
2272 unsigned long flags;
2275 switch (csr_offset) {
2276 case CSR_STATE_CLEAR:
2278 if (ohci->is_root &&
2279 (reg_read(ohci, OHCI1394_LinkControlSet) &
2280 OHCI1394_LinkControl_cycleMaster))
2281 value = CSR_STATE_BIT_CMSTR;
2284 if (ohci->csr_state_setclear_abdicate)
2285 value |= CSR_STATE_BIT_ABDICATE;
2290 return reg_read(ohci, OHCI1394_NodeID) << 16;
2292 case CSR_CYCLE_TIME:
2293 return get_cycle_time(ohci);
2297 * We might be called just after the cycle timer has wrapped
2298 * around but just before the cycle64Seconds handler, so we
2299 * better check here, too, if the bus time needs to be updated.
2301 spin_lock_irqsave(&ohci->lock, flags);
2302 value = update_bus_time(ohci);
2303 spin_unlock_irqrestore(&ohci->lock, flags);
2306 case CSR_BUSY_TIMEOUT:
2307 value = reg_read(ohci, OHCI1394_ATRetries);
2308 return (value >> 4) & 0x0ffff00f;
2310 case CSR_PRIORITY_BUDGET:
2311 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2312 (ohci->pri_req_max << 8);
2320 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2322 struct fw_ohci *ohci = fw_ohci(card);
2323 unsigned long flags;
2325 switch (csr_offset) {
2326 case CSR_STATE_CLEAR:
2327 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2328 reg_write(ohci, OHCI1394_LinkControlClear,
2329 OHCI1394_LinkControl_cycleMaster);
2332 if (value & CSR_STATE_BIT_ABDICATE)
2333 ohci->csr_state_setclear_abdicate = false;
2337 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2338 reg_write(ohci, OHCI1394_LinkControlSet,
2339 OHCI1394_LinkControl_cycleMaster);
2342 if (value & CSR_STATE_BIT_ABDICATE)
2343 ohci->csr_state_setclear_abdicate = true;
2347 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2351 case CSR_CYCLE_TIME:
2352 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2353 reg_write(ohci, OHCI1394_IntEventSet,
2354 OHCI1394_cycleInconsistent);
2359 spin_lock_irqsave(&ohci->lock, flags);
2360 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2361 spin_unlock_irqrestore(&ohci->lock, flags);
2364 case CSR_BUSY_TIMEOUT:
2365 value = (value & 0xf) | ((value & 0xf) << 4) |
2366 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2367 reg_write(ohci, OHCI1394_ATRetries, value);
2371 case CSR_PRIORITY_BUDGET:
2372 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2382 static void copy_iso_headers(struct iso_context *ctx, void *p)
2384 int i = ctx->header_length;
2386 if (i + ctx->base.header_size > PAGE_SIZE)
2390 * The iso header is byteswapped to little endian by
2391 * the controller, but the remaining header quadlets
2392 * are big endian. We want to present all the headers
2393 * as big endian, so we have to swap the first quadlet.
2395 if (ctx->base.header_size > 0)
2396 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2397 if (ctx->base.header_size > 4)
2398 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2399 if (ctx->base.header_size > 8)
2400 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2401 ctx->header_length += ctx->base.header_size;
2404 static int handle_ir_packet_per_buffer(struct context *context,
2405 struct descriptor *d,
2406 struct descriptor *last)
2408 struct iso_context *ctx =
2409 container_of(context, struct iso_context, context);
2410 struct descriptor *pd;
2414 for (pd = d; pd <= last; pd++)
2415 if (pd->transfer_status)
2418 /* Descriptor(s) not done yet, stop iteration */
2422 copy_iso_headers(ctx, p);
2424 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2425 ir_header = (__le32 *) p;
2426 ctx->base.callback.sc(&ctx->base,
2427 le32_to_cpu(ir_header[0]) & 0xffff,
2428 ctx->header_length, ctx->header,
2429 ctx->base.callback_data);
2430 ctx->header_length = 0;
2436 /* d == last because each descriptor block is only a single descriptor. */
2437 static int handle_ir_buffer_fill(struct context *context,
2438 struct descriptor *d,
2439 struct descriptor *last)
2441 struct iso_context *ctx =
2442 container_of(context, struct iso_context, context);
2444 if (!last->transfer_status)
2445 /* Descriptor(s) not done yet, stop iteration */
2448 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2449 ctx->base.callback.mc(&ctx->base,
2450 le32_to_cpu(last->data_address) +
2451 le16_to_cpu(last->req_count) -
2452 le16_to_cpu(last->res_count),
2453 ctx->base.callback_data);
2458 static int handle_it_packet(struct context *context,
2459 struct descriptor *d,
2460 struct descriptor *last)
2462 struct iso_context *ctx =
2463 container_of(context, struct iso_context, context);
2465 struct descriptor *pd;
2467 for (pd = d; pd <= last; pd++)
2468 if (pd->transfer_status)
2471 /* Descriptor(s) not done yet, stop iteration */
2474 i = ctx->header_length;
2475 if (i + 4 < PAGE_SIZE) {
2476 /* Present this value as big-endian to match the receive code */
2477 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2478 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2479 le16_to_cpu(pd->res_count));
2480 ctx->header_length += 4;
2482 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2483 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2484 ctx->header_length, ctx->header,
2485 ctx->base.callback_data);
2486 ctx->header_length = 0;
2491 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2493 u32 hi = channels >> 32, lo = channels;
2495 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2496 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2497 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2498 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2500 ohci->mc_channels = channels;
2503 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2504 int type, int channel, size_t header_size)
2506 struct fw_ohci *ohci = fw_ohci(card);
2507 struct iso_context *uninitialized_var(ctx);
2508 descriptor_callback_t uninitialized_var(callback);
2509 u64 *uninitialized_var(channels);
2510 u32 *uninitialized_var(mask), uninitialized_var(regs);
2511 unsigned long flags;
2512 int index, ret = -EBUSY;
2514 spin_lock_irqsave(&ohci->lock, flags);
2517 case FW_ISO_CONTEXT_TRANSMIT:
2518 mask = &ohci->it_context_mask;
2519 callback = handle_it_packet;
2520 index = ffs(*mask) - 1;
2522 *mask &= ~(1 << index);
2523 regs = OHCI1394_IsoXmitContextBase(index);
2524 ctx = &ohci->it_context_list[index];
2528 case FW_ISO_CONTEXT_RECEIVE:
2529 channels = &ohci->ir_context_channels;
2530 mask = &ohci->ir_context_mask;
2531 callback = handle_ir_packet_per_buffer;
2532 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2534 *channels &= ~(1ULL << channel);
2535 *mask &= ~(1 << index);
2536 regs = OHCI1394_IsoRcvContextBase(index);
2537 ctx = &ohci->ir_context_list[index];
2541 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2542 mask = &ohci->ir_context_mask;
2543 callback = handle_ir_buffer_fill;
2544 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2546 ohci->mc_allocated = true;
2547 *mask &= ~(1 << index);
2548 regs = OHCI1394_IsoRcvContextBase(index);
2549 ctx = &ohci->ir_context_list[index];
2558 spin_unlock_irqrestore(&ohci->lock, flags);
2561 return ERR_PTR(ret);
2563 memset(ctx, 0, sizeof(*ctx));
2564 ctx->header_length = 0;
2565 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2566 if (ctx->header == NULL) {
2570 ret = context_init(&ctx->context, ohci, regs, callback);
2572 goto out_with_header;
2574 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2575 set_multichannel_mask(ohci, 0);
2580 free_page((unsigned long)ctx->header);
2582 spin_lock_irqsave(&ohci->lock, flags);
2585 case FW_ISO_CONTEXT_RECEIVE:
2586 *channels |= 1ULL << channel;
2589 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2590 ohci->mc_allocated = false;
2593 *mask |= 1 << index;
2595 spin_unlock_irqrestore(&ohci->lock, flags);
2597 return ERR_PTR(ret);
2600 static int ohci_start_iso(struct fw_iso_context *base,
2601 s32 cycle, u32 sync, u32 tags)
2603 struct iso_context *ctx = container_of(base, struct iso_context, base);
2604 struct fw_ohci *ohci = ctx->context.ohci;
2605 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2608 switch (ctx->base.type) {
2609 case FW_ISO_CONTEXT_TRANSMIT:
2610 index = ctx - ohci->it_context_list;
2613 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2614 (cycle & 0x7fff) << 16;
2616 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2617 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2618 context_run(&ctx->context, match);
2621 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2622 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2624 case FW_ISO_CONTEXT_RECEIVE:
2625 index = ctx - ohci->ir_context_list;
2626 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2628 match |= (cycle & 0x07fff) << 12;
2629 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2632 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2633 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2634 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2635 context_run(&ctx->context, control);
2642 static int ohci_stop_iso(struct fw_iso_context *base)
2644 struct fw_ohci *ohci = fw_ohci(base->card);
2645 struct iso_context *ctx = container_of(base, struct iso_context, base);
2648 switch (ctx->base.type) {
2649 case FW_ISO_CONTEXT_TRANSMIT:
2650 index = ctx - ohci->it_context_list;
2651 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2654 case FW_ISO_CONTEXT_RECEIVE:
2655 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2656 index = ctx - ohci->ir_context_list;
2657 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2661 context_stop(&ctx->context);
2666 static void ohci_free_iso_context(struct fw_iso_context *base)
2668 struct fw_ohci *ohci = fw_ohci(base->card);
2669 struct iso_context *ctx = container_of(base, struct iso_context, base);
2670 unsigned long flags;
2673 ohci_stop_iso(base);
2674 context_release(&ctx->context);
2675 free_page((unsigned long)ctx->header);
2677 spin_lock_irqsave(&ohci->lock, flags);
2679 switch (base->type) {
2680 case FW_ISO_CONTEXT_TRANSMIT:
2681 index = ctx - ohci->it_context_list;
2682 ohci->it_context_mask |= 1 << index;
2685 case FW_ISO_CONTEXT_RECEIVE:
2686 index = ctx - ohci->ir_context_list;
2687 ohci->ir_context_mask |= 1 << index;
2688 ohci->ir_context_channels |= 1ULL << base->channel;
2691 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2692 index = ctx - ohci->ir_context_list;
2693 ohci->ir_context_mask |= 1 << index;
2694 ohci->ir_context_channels |= ohci->mc_channels;
2695 ohci->mc_channels = 0;
2696 ohci->mc_allocated = false;
2700 spin_unlock_irqrestore(&ohci->lock, flags);
2703 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2705 struct fw_ohci *ohci = fw_ohci(base->card);
2706 unsigned long flags;
2709 switch (base->type) {
2710 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2712 spin_lock_irqsave(&ohci->lock, flags);
2714 /* Don't allow multichannel to grab other contexts' channels. */
2715 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2716 *channels = ohci->ir_context_channels;
2719 set_multichannel_mask(ohci, *channels);
2723 spin_unlock_irqrestore(&ohci->lock, flags);
2733 static int queue_iso_transmit(struct iso_context *ctx,
2734 struct fw_iso_packet *packet,
2735 struct fw_iso_buffer *buffer,
2736 unsigned long payload)
2738 struct descriptor *d, *last, *pd;
2739 struct fw_iso_packet *p;
2741 dma_addr_t d_bus, page_bus;
2742 u32 z, header_z, payload_z, irq;
2743 u32 payload_index, payload_end_index, next_page_index;
2744 int page, end_page, i, length, offset;
2747 payload_index = payload;
2753 if (p->header_length > 0)
2756 /* Determine the first page the payload isn't contained in. */
2757 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2758 if (p->payload_length > 0)
2759 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2765 /* Get header size in number of descriptors. */
2766 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2768 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2773 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2774 d[0].req_count = cpu_to_le16(8);
2776 * Link the skip address to this descriptor itself. This causes
2777 * a context to skip a cycle whenever lost cycles or FIFO
2778 * overruns occur, without dropping the data. The application
2779 * should then decide whether this is an error condition or not.
2780 * FIXME: Make the context's cycle-lost behaviour configurable?
2782 d[0].branch_address = cpu_to_le32(d_bus | z);
2784 header = (__le32 *) &d[1];
2785 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2786 IT_HEADER_TAG(p->tag) |
2787 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2788 IT_HEADER_CHANNEL(ctx->base.channel) |
2789 IT_HEADER_SPEED(ctx->base.speed));
2791 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2792 p->payload_length));
2795 if (p->header_length > 0) {
2796 d[2].req_count = cpu_to_le16(p->header_length);
2797 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2798 memcpy(&d[z], p->header, p->header_length);
2801 pd = d + z - payload_z;
2802 payload_end_index = payload_index + p->payload_length;
2803 for (i = 0; i < payload_z; i++) {
2804 page = payload_index >> PAGE_SHIFT;
2805 offset = payload_index & ~PAGE_MASK;
2806 next_page_index = (page + 1) << PAGE_SHIFT;
2808 min(next_page_index, payload_end_index) - payload_index;
2809 pd[i].req_count = cpu_to_le16(length);
2811 page_bus = page_private(buffer->pages[page]);
2812 pd[i].data_address = cpu_to_le32(page_bus + offset);
2814 payload_index += length;
2818 irq = DESCRIPTOR_IRQ_ALWAYS;
2820 irq = DESCRIPTOR_NO_IRQ;
2822 last = z == 2 ? d : d + z - 1;
2823 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2825 DESCRIPTOR_BRANCH_ALWAYS |
2828 context_append(&ctx->context, d, z, header_z);
2833 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2834 struct fw_iso_packet *packet,
2835 struct fw_iso_buffer *buffer,
2836 unsigned long payload)
2838 struct descriptor *d, *pd;
2839 dma_addr_t d_bus, page_bus;
2840 u32 z, header_z, rest;
2842 int page, offset, packet_count, header_size, payload_per_buffer;
2845 * The OHCI controller puts the isochronous header and trailer in the
2846 * buffer, so we need at least 8 bytes.
2848 packet_count = packet->header_length / ctx->base.header_size;
2849 header_size = max(ctx->base.header_size, (size_t)8);
2851 /* Get header size in number of descriptors. */
2852 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2853 page = payload >> PAGE_SHIFT;
2854 offset = payload & ~PAGE_MASK;
2855 payload_per_buffer = packet->payload_length / packet_count;
2857 for (i = 0; i < packet_count; i++) {
2858 /* d points to the header descriptor */
2859 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2860 d = context_get_descriptors(&ctx->context,
2861 z + header_z, &d_bus);
2865 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2866 DESCRIPTOR_INPUT_MORE);
2867 if (packet->skip && i == 0)
2868 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2869 d->req_count = cpu_to_le16(header_size);
2870 d->res_count = d->req_count;
2871 d->transfer_status = 0;
2872 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2874 rest = payload_per_buffer;
2876 for (j = 1; j < z; j++) {
2878 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2879 DESCRIPTOR_INPUT_MORE);
2881 if (offset + rest < PAGE_SIZE)
2884 length = PAGE_SIZE - offset;
2885 pd->req_count = cpu_to_le16(length);
2886 pd->res_count = pd->req_count;
2887 pd->transfer_status = 0;
2889 page_bus = page_private(buffer->pages[page]);
2890 pd->data_address = cpu_to_le32(page_bus + offset);
2892 offset = (offset + length) & ~PAGE_MASK;
2897 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2898 DESCRIPTOR_INPUT_LAST |
2899 DESCRIPTOR_BRANCH_ALWAYS);
2900 if (packet->interrupt && i == packet_count - 1)
2901 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2903 context_append(&ctx->context, d, z, header_z);
2909 static int queue_iso_buffer_fill(struct iso_context *ctx,
2910 struct fw_iso_packet *packet,
2911 struct fw_iso_buffer *buffer,
2912 unsigned long payload)
2914 struct descriptor *d;
2915 dma_addr_t d_bus, page_bus;
2916 int page, offset, rest, z, i, length;
2918 page = payload >> PAGE_SHIFT;
2919 offset = payload & ~PAGE_MASK;
2920 rest = packet->payload_length;
2922 /* We need one descriptor for each page in the buffer. */
2923 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
2925 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
2928 for (i = 0; i < z; i++) {
2929 d = context_get_descriptors(&ctx->context, 1, &d_bus);
2933 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
2934 DESCRIPTOR_BRANCH_ALWAYS);
2935 if (packet->skip && i == 0)
2936 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2937 if (packet->interrupt && i == z - 1)
2938 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2940 if (offset + rest < PAGE_SIZE)
2943 length = PAGE_SIZE - offset;
2944 d->req_count = cpu_to_le16(length);
2945 d->res_count = d->req_count;
2946 d->transfer_status = 0;
2948 page_bus = page_private(buffer->pages[page]);
2949 d->data_address = cpu_to_le32(page_bus + offset);
2955 context_append(&ctx->context, d, 1, 0);
2961 static int ohci_queue_iso(struct fw_iso_context *base,
2962 struct fw_iso_packet *packet,
2963 struct fw_iso_buffer *buffer,
2964 unsigned long payload)
2966 struct iso_context *ctx = container_of(base, struct iso_context, base);
2967 unsigned long flags;
2970 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2971 switch (base->type) {
2972 case FW_ISO_CONTEXT_TRANSMIT:
2973 ret = queue_iso_transmit(ctx, packet, buffer, payload);
2975 case FW_ISO_CONTEXT_RECEIVE:
2976 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
2978 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2979 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
2982 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2987 static const struct fw_card_driver ohci_driver = {
2988 .enable = ohci_enable,
2989 .read_phy_reg = ohci_read_phy_reg,
2990 .update_phy_reg = ohci_update_phy_reg,
2991 .set_config_rom = ohci_set_config_rom,
2992 .send_request = ohci_send_request,
2993 .send_response = ohci_send_response,
2994 .cancel_packet = ohci_cancel_packet,
2995 .enable_phys_dma = ohci_enable_phys_dma,
2996 .read_csr = ohci_read_csr,
2997 .write_csr = ohci_write_csr,
2999 .allocate_iso_context = ohci_allocate_iso_context,
3000 .free_iso_context = ohci_free_iso_context,
3001 .set_iso_channels = ohci_set_iso_channels,
3002 .queue_iso = ohci_queue_iso,
3003 .start_iso = ohci_start_iso,
3004 .stop_iso = ohci_stop_iso,
3007 #ifdef CONFIG_PPC_PMAC
3008 static void pmac_ohci_on(struct pci_dev *dev)
3010 if (machine_is(powermac)) {
3011 struct device_node *ofn = pci_device_to_OF_node(dev);
3014 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3015 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3020 static void pmac_ohci_off(struct pci_dev *dev)
3022 if (machine_is(powermac)) {
3023 struct device_node *ofn = pci_device_to_OF_node(dev);
3026 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3027 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3032 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3033 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3034 #endif /* CONFIG_PPC_PMAC */
3036 static int __devinit pci_probe(struct pci_dev *dev,
3037 const struct pci_device_id *ent)
3039 struct fw_ohci *ohci;
3040 u32 bus_options, max_receive, link_speed, version;
3042 int i, err, n_ir, n_it;
3045 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3051 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3055 err = pci_enable_device(dev);
3057 fw_error("Failed to enable OHCI hardware\n");
3061 pci_set_master(dev);
3062 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3063 pci_set_drvdata(dev, ohci);
3065 spin_lock_init(&ohci->lock);
3066 mutex_init(&ohci->phy_reg_mutex);
3068 tasklet_init(&ohci->bus_reset_tasklet,
3069 bus_reset_tasklet, (unsigned long)ohci);
3071 err = pci_request_region(dev, 0, ohci_driver_name);
3073 fw_error("MMIO resource unavailable\n");
3077 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3078 if (ohci->registers == NULL) {
3079 fw_error("Failed to remap registers\n");
3084 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3085 if ((ohci_quirks[i].vendor == dev->vendor) &&
3086 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3087 ohci_quirks[i].device == dev->device) &&
3088 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3089 ohci_quirks[i].revision >= dev->revision)) {
3090 ohci->quirks = ohci_quirks[i].flags;
3094 ohci->quirks = param_quirks;
3096 err = ar_context_init(&ohci->ar_request_ctx, ohci,
3097 OHCI1394_AsReqRcvContextControlSet);
3101 err = ar_context_init(&ohci->ar_response_ctx, ohci,
3102 OHCI1394_AsRspRcvContextControlSet);
3104 goto fail_arreq_ctx;
3106 err = context_init(&ohci->at_request_ctx, ohci,
3107 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3109 goto fail_arrsp_ctx;
3111 err = context_init(&ohci->at_response_ctx, ohci,
3112 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3114 goto fail_atreq_ctx;
3116 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3117 ohci->ir_context_channels = ~0ULL;
3118 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3119 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3120 n_ir = hweight32(ohci->ir_context_mask);
3121 size = sizeof(struct iso_context) * n_ir;
3122 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3124 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3125 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3126 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3127 n_it = hweight32(ohci->it_context_mask);
3128 size = sizeof(struct iso_context) * n_it;
3129 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3131 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3136 /* self-id dma buffer allocation */
3137 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
3141 if (ohci->self_id_cpu == NULL) {
3146 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3147 max_receive = (bus_options >> 12) & 0xf;
3148 link_speed = bus_options & 0x7;
3149 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3150 reg_read(ohci, OHCI1394_GUIDLo);
3152 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3156 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3157 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3158 "%d IR + %d IT contexts, quirks 0x%x\n",
3159 dev_name(&dev->dev), version >> 16, version & 0xff,
3160 n_ir, n_it, ohci->quirks);
3165 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3166 ohci->self_id_cpu, ohci->self_id_bus);
3168 kfree(ohci->ir_context_list);
3169 kfree(ohci->it_context_list);
3170 context_release(&ohci->at_response_ctx);
3172 context_release(&ohci->at_request_ctx);
3174 ar_context_release(&ohci->ar_response_ctx);
3176 ar_context_release(&ohci->ar_request_ctx);
3178 pci_iounmap(dev, ohci->registers);
3180 pci_release_region(dev, 0);
3182 pci_disable_device(dev);
3188 fw_error("Out of memory\n");
3193 static void pci_remove(struct pci_dev *dev)
3195 struct fw_ohci *ohci;
3197 ohci = pci_get_drvdata(dev);
3198 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3200 fw_core_remove_card(&ohci->card);
3203 * FIXME: Fail all pending packets here, now that the upper
3204 * layers can't queue any more.
3207 software_reset(ohci);
3208 free_irq(dev->irq, ohci);
3210 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3211 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3212 ohci->next_config_rom, ohci->next_config_rom_bus);
3213 if (ohci->config_rom)
3214 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3215 ohci->config_rom, ohci->config_rom_bus);
3216 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
3217 ohci->self_id_cpu, ohci->self_id_bus);
3218 ar_context_release(&ohci->ar_request_ctx);
3219 ar_context_release(&ohci->ar_response_ctx);
3220 context_release(&ohci->at_request_ctx);
3221 context_release(&ohci->at_response_ctx);
3222 kfree(ohci->it_context_list);
3223 kfree(ohci->ir_context_list);
3224 pci_disable_msi(dev);
3225 pci_iounmap(dev, ohci->registers);
3226 pci_release_region(dev, 0);
3227 pci_disable_device(dev);
3231 fw_notify("Removed fw-ohci device.\n");
3235 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3237 struct fw_ohci *ohci = pci_get_drvdata(dev);
3240 software_reset(ohci);
3241 free_irq(dev->irq, ohci);
3242 pci_disable_msi(dev);
3243 err = pci_save_state(dev);
3245 fw_error("pci_save_state failed\n");
3248 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3250 fw_error("pci_set_power_state failed with %d\n", err);
3256 static int pci_resume(struct pci_dev *dev)
3258 struct fw_ohci *ohci = pci_get_drvdata(dev);
3262 pci_set_power_state(dev, PCI_D0);
3263 pci_restore_state(dev);
3264 err = pci_enable_device(dev);
3266 fw_error("pci_enable_device failed\n");
3270 return ohci_enable(&ohci->card, NULL, 0);
3274 static const struct pci_device_id pci_table[] = {
3275 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3279 MODULE_DEVICE_TABLE(pci, pci_table);
3281 static struct pci_driver fw_ohci_pci_driver = {
3282 .name = ohci_driver_name,
3283 .id_table = pci_table,
3285 .remove = pci_remove,
3287 .resume = pci_resume,
3288 .suspend = pci_suspend,
3292 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3293 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3294 MODULE_LICENSE("GPL");
3296 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3297 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3298 MODULE_ALIAS("ohci1394");
3301 static int __init fw_ohci_init(void)
3303 return pci_register_driver(&fw_ohci_pci_driver);
3306 static void __exit fw_ohci_cleanup(void)
3308 pci_unregister_driver(&fw_ohci_pci_driver);
3311 module_init(fw_ohci_init);
3312 module_exit(fw_ohci_cleanup);