drivers/pinctrl/sh-pfc/pfc-r8a7779.c

   1 /*
   2  * r8a7779 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/kernel.h>
  22
  23 #include "sh_pfc.h"
  24
  25 #define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
  26
  27 #define PORT_GP_32(bank, fn, sfx)                                       \
  28         PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
  29         PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
  30         PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
  31         PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
  32         PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
  33         PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
  34         PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
  35         PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
  36         PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
  37         PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
  38         PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
  39         PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
  40         PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
  41         PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
  42         PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
  43         PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
  44
  45 #define PORT_GP_32_9(bank, fn, sfx)                                     \
  46         PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx),       \
  47         PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx),       \
  48         PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx),       \
  49         PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx),       \
  50         PORT_GP_1(bank, 8, fn, sfx)
  51
  52 #define PORT_GP_32_REV(bank, fn, sfx)                                   \
  53         PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
  54         PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
  55         PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
  56         PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
  57         PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
  58         PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
  59         PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
  60         PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
  61         PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
  62         PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
  63         PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
  64         PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
  65         PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
  66         PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
  67         PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
  68         PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
  69
  70 #define CPU_ALL_PORT(fn, sfx)                                           \
  71         PORT_GP_32(0, fn, sfx),                                         \
  72         PORT_GP_32(1, fn, sfx),                                         \
  73         PORT_GP_32(2, fn, sfx),                                         \
  74         PORT_GP_32(3, fn, sfx),                                         \
  75         PORT_GP_32(4, fn, sfx),                                         \
  76         PORT_GP_32(5, fn, sfx),                                         \
  77         PORT_GP_32_9(6, fn, sfx)
  78
  79 #define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
  80
  81 #define _GP_GPIO(bank, pin, _name, sfx)                                 \
  82         [(bank * 32) + pin] = {                                         \
  83                 .name = __stringify(_name),                             \
  84                 .enum_id = _name##_DATA,                                \
  85         }
  86
  87 #define _GP_DATA(bank, pin, name, sfx)                                  \
  88         PINMUX_DATA(name##_DATA, name##_FN)
  89
  90 #define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
  91 #define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
  92 #define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
  93
  94 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
  95 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
  96                                                           FN_##ipsr, FN_##fn)
  97
  98 enum {
  99         PINMUX_RESERVED = 0,
 100
 101         PINMUX_DATA_BEGIN,
 102         GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
 103         PINMUX_DATA_END,
 104
 105         PINMUX_FUNCTION_BEGIN,
 106         GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
 107
 108         /* GPSR0 */
 109         FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
 110         FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
 111         FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
 112         FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
 113         FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
 114         FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
 115         FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
 116         FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
 117
 118         /* GPSR1 */
 119         FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
 120         FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
 121         FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
 122         FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
 123         FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
 124         FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
 125         FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
 126         FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
 127
 128         /* GPSR2 */
 129         FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
 130         FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
 131         FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
 132         FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
 133         FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
 134         FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
 135         FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
 136         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
 137
 138         /* GPSR3 */
 139         FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
 140         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
 141         FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
 142         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
 143         FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
 144         FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
 145         FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
 146         FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
 147
 148         /* GPSR4 */
 149         FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
 150         FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
 151         FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
 152         FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
 153         FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
 154         FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
 155         FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
 156         FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
 157
 158         /* GPSR5 */
 159         FN_A1, FN_A2, FN_A3, FN_A4,
 160         FN_A5, FN_A6, FN_A7, FN_A8,
 161         FN_A9, FN_A10, FN_A11, FN_A12,
 162         FN_A13, FN_A14, FN_A15, FN_A16,
 163         FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
 164         FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
 165         FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
 166         FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
 167
 168         /* GPSR6 */
 169         FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
 170         FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
 171         FN_IP3_20,
 172
 173         /* IPSR0 */
 174         FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
 175         FN_HRTS1, FN_RX4_C,
 176         FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
 177         FN_CS0, FN_HSPI_CS2_B,
 178         FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
 179         FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
 180         FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
 181         FN_CTS0_B,
 182         FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
 183         FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
 184         FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
 185         FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
 186         FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
 187         FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
 188         FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
 189         FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 190         FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
 191         FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 192         FN_SCIF_CLK, FN_TCLK0_C,
 193
 194         /* IPSR1 */
 195         FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
 196         FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
 197         FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
 198         FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
 199         FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
 200         FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
 201         FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
 202         FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
 203         FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
 204         FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
 205         FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
 206         FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
 207         FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
 208         FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
 209         FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
 210         FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
 211
 212         /* IPSR2 */
 213         FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
 214         FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
 215         FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
 216         FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
 217         FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
 218         FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
 219         FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
 220         FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
 221         FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
 222         FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
 223         FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
 224         FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
 225         FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
 226         FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
 227         FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
 228         FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
 229         FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
 230         FN_DREQ1, FN_SCL2, FN_AUDATA2,
 231
 232         /* IPSR3 */
 233         FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
 234         FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
 235         FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
 236         FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
 237         FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
 238         FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
 239         FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
 240         FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
 241         FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
 242         FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
 243         FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
 244         FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
 245         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
 246         FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
 247         FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
 248         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
 249         FN_TX2_C, FN_SCL2_C, FN_REMOCON,
 250
 251         /* IPSR4 */
 252         FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
 253         FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
 254         FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
 255         FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
 256         FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
 257         FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
 258         FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
 259         FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
 260         FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
 261         FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
 262         FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
 263         FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
 264         FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
 265         FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
 266         FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
 267         FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
 268         FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
 269         FN_SCK0_D,
 270
 271         /* IPSR5 */
 272         FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
 273         FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
 274         FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
 275         FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
 276         FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
 277         FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
 278         FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
 279         FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
 280         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
 281         FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
 282         FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
 283         FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
 284         FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
 285         FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
 286         FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
 287         FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
 288         FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
 289         FN_CAN_DEBUGOUT0, FN_MOUT0,
 290
 291         /* IPSR6 */
 292         FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
 293         FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
 294         FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
 295         FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
 296         FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
 297         FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
 298         FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
 299         FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
 300         FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
 301         FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
 302         FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
 303         FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
 304         FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
 305
 306         /* IPSR7 */
 307         FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
 308         FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
 309         FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
 310         FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
 311         FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
 312         FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
 313         FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
 314         FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
 315         FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
 316         FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
 317         FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
 318         FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
 319         FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
 320         FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
 321
 322         /* IPSR8 */
 323         FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
 324         FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
 325         FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
 326         FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
 327         FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
 328         FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
 329         FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
 330         FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
 331         FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
 332         FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
 333         FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
 334         FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
 335         FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
 336         FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
 337         FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
 338         FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
 339
 340         /* IPSR9 */
 341         FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
 342         FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
 343         FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
 344         FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
 345         FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
 346         FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
 347         FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
 348         FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
 349         FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
 350         FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
 351         FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
 352         FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
 353         FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
 354         FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
 355
 356         /* IPSR10 */
 357         FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
 358         FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
 359         FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
 360         FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
 361         FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
 362         FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
 363         FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
 364         FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
 365         FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
 366         FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
 367         FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
 368         FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
 369         FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
 370         FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
 371         FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
 372         FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
 373
 374         /* IPSR11 */
 375         FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
 376         FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
 377         FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
 378         FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
 379         FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
 380         FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
 381         FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
 382         FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
 383         FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
 384         FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
 385         FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
 386         FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
 387         FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
 388         FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
 389
 390         /* IPSR12 */
 391         FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
 392         FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
 393         FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
 394         FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
 395         FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
 396         FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
 397         FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
 398         FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
 399         FN_GPS_MAG, FN_FCE, FN_SCK4_B,
 400
 401         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
 402         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 403         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
 404         FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
 405         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
 406         FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
 407         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
 408         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 409         FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
 410         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 411         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 412         FN_SEL_VI0_0, FN_SEL_VI0_1,
 413         FN_SEL_SD2_0, FN_SEL_SD2_1,
 414         FN_SEL_INT3_0, FN_SEL_INT3_1,
 415         FN_SEL_INT2_0, FN_SEL_INT2_1,
 416         FN_SEL_INT1_0, FN_SEL_INT1_1,
 417         FN_SEL_INT0_0, FN_SEL_INT0_1,
 418         FN_SEL_IE_0, FN_SEL_IE_1,
 419         FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
 420         FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
 421         FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
 422
 423         FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
 424         FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
 425         FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
 426         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
 427         FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 428         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 429         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 430         FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
 431         FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
 432         FN_SEL_ADI_0, FN_SEL_ADI_1,
 433         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 434         FN_SEL_SIM_0, FN_SEL_SIM_1,
 435         FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
 436         FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
 437         FN_SEL_I2C3_0, FN_SEL_I2C3_1,
 438         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 439         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
 440         PINMUX_FUNCTION_END,
 441
 442         PINMUX_MARK_BEGIN,
 443         AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
 444         A19_MARK,
 445
 446         RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
 447         HRTS1_MARK, RX4_C_MARK,
 448         CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
 449         CS0_MARK, HSPI_CS2_B_MARK,
 450         CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
 451         A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
 452         HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
 453         A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
 454         HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
 455         A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
 456         A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
 457         A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
 458         A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
 459         A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
 460         BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
 461         ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
 462         USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
 463         SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
 464         SCIF_CLK_MARK, TCLK0_C_MARK,
 465
 466         EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
 467         FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
 468         EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
 469         ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
 470         FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
 471         HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
 472         EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
 473         ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
 474         TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
 475         SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
 476         VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
 477         SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
 478         MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
 479         PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
 480         SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
 481         CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
 482
 483         HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
 484         SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
 485         CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
 486         MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
 487         SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
 488         CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
 489         STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
 490         SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
 491         RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
 492         CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
 493         CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
 494         GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
 495         LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
 496         AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
 497         DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
 498         DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
 499         DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
 500         DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
 501
 502         DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
 503         AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
 504         LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
 505         LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
 506         LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
 507         SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
 508         LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
 509         AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
 510         DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
 511         DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
 512         DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 513         TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
 514         DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
 515         SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 516         QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
 517         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
 518         TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
 519
 520         DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
 521         DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
 522         DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
 523         VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
 524         AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
 525         PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
 526         CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
 527         VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
 528         VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
 529         VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
 530         SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
 531         DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
 532         SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
 533         VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
 534         VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
 535         VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
 536         VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
 537         SCK0_D_MARK,
 538
 539         DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
 540         RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
 541         DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
 542         DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
 543         DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
 544         HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
 545         SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
 546         VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
 547         VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
 548         TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
 549         VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
 550         GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
 551         QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
 552         GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
 553         RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
 554         VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
 555         GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
 556         USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
 557
 558         SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
 559         CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
 560         MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
 561         SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
 562         CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
 563         SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
 564         SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
 565         CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
 566         SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
 567         ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
 568         SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
 569         SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
 570         SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
 571
 572         SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
 573         SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
 574         SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
 575         HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
 576         SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
 577         IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
 578         VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
 579         ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
 580         TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
 581         RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
 582         SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
 583         TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
 584         RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
 585         RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
 586
 587         HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
 588         CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
 589         CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
 590         AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
 591         CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
 592         CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
 593         CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
 594         CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
 595         AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
 596         CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
 597         PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
 598         VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
 599         MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
 600         VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
 601         MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
 602         RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
 603
 604         VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
 605         VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
 606         VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
 607         MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
 608         VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
 609         MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
 610         MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
 611         IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
 612         IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
 613         MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
 614         ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
 615         VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
 616         VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
 617         VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
 618         VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
 619
 620         VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
 621         ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
 622         DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
 623         VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
 624         ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
 625         IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
 626         SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
 627         TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
 628         HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
 629         VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
 630         TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
 631         ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
 632         TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
 633         VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
 634         PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
 635         SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
 636
 637         VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
 638         ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
 639         SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
 640         SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
 641         VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
 642         ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
 643         SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
 644         VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
 645         HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
 646         MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
 647         SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
 648         VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
 649         DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
 650         VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
 651         DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
 652
 653         VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
 654         SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
 655         SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
 656         VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
 657         SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
 658         GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
 659         VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
 660         RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
 661         GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
 662         PINMUX_MARK_END,
 663 };
 664
 665 static const pinmux_enum_t pinmux_data[] = {
 666         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 667
 668         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 669         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 670         PINMUX_DATA(A17_MARK, FN_A17),
 671         PINMUX_DATA(A18_MARK, FN_A18),
 672         PINMUX_DATA(A19_MARK, FN_A19),
 673
 674         PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
 675         PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
 676
 677         PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
 678         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
 679         PINMUX_IPSR_DATA(IP0_2_0, PWM1),
 680         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
 681         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
 682         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
 683         PINMUX_IPSR_DATA(IP0_5_3, BS),
 684         PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
 685         PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
 686         PINMUX_IPSR_DATA(IP0_5_3, FD2),
 687         PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
 688         PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
 689         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
 690         PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
 691         PINMUX_IPSR_DATA(IP0_7_6, A0),
 692         PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
 693         PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
 694         PINMUX_IPSR_DATA(IP0_7_6, FD3),
 695         PINMUX_IPSR_DATA(IP0_9_8, A20),
 696         PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
 697         PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
 698         PINMUX_IPSR_DATA(IP0_11_10, A21),
 699         PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
 700         PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
 701         PINMUX_IPSR_DATA(IP0_13_12, A22),
 702         PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
 703         PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
 704         PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
 705         PINMUX_IPSR_DATA(IP0_15_14, A23),
 706         PINMUX_IPSR_DATA(IP0_15_14, FCLE),
 707         PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
 708         PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
 709         PINMUX_IPSR_DATA(IP0_18_16, A24),
 710         PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
 711         PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
 712         PINMUX_IPSR_DATA(IP0_18_16, FD4),
 713         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
 714         PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
 715         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
 716         PINMUX_IPSR_DATA(IP0_22_19, A25),
 717         PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
 718         PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
 719         PINMUX_IPSR_DATA(IP0_22_19, FD5),
 720         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
 721         PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
 722         PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
 723         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
 724         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
 725         PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
 726         PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
 727         PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
 728         PINMUX_IPSR_DATA(IP0_25, CS0),
 729         PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
 730         PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
 731         PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
 732         PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
 733         PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
 734         PINMUX_IPSR_DATA(IP0_30_28, FWE),
 735         PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
 736         PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
 737         PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
 738         PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
 739
 740         PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
 741         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
 742         PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
 743         PINMUX_IPSR_DATA(IP1_1_0, FD6),
 744         PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
 745         PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
 746         PINMUX_IPSR_DATA(IP1_3_2, FD7),
 747         PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
 748         PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
 749         PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
 750         PINMUX_IPSR_DATA(IP1_6_4, FALE),
 751         PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
 752         PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
 753         PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
 754         PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
 755         PINMUX_IPSR_DATA(IP1_10_7, FRE),
 756         PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
 757         PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
 758         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
 759         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
 760         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
 761         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
 762         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
 763         PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
 764         PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
 765         PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
 766         PINMUX_IPSR_DATA(IP1_14_11, FD0),
 767         PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
 768         PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
 769         PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
 770         PINMUX_IPSR_DATA(IP1_14_11, HTX1),
 771         PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
 772         PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
 773         PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
 774         PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
 775         PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
 776         PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
 777         PINMUX_IPSR_DATA(IP1_18_15, FD1),
 778         PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
 779         PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
 780         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
 781         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
 782         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
 783         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
 784         PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
 785         PINMUX_IPSR_DATA(IP1_20_19, PWM2),
 786         PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
 787         PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
 788         PINMUX_IPSR_DATA(IP1_22_21, PWM3),
 789         PINMUX_IPSR_DATA(IP1_22_21, TX4),
 790         PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
 791         PINMUX_IPSR_DATA(IP1_24_23, PWM4),
 792         PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
 793         PINMUX_IPSR_DATA(IP1_28_25, HTX0),
 794         PINMUX_IPSR_DATA(IP1_28_25, TX1),
 795         PINMUX_IPSR_DATA(IP1_28_25, SDATA),
 796         PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
 797         PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
 798         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
 799         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
 800         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
 801         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
 802         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
 803
 804         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
 805         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
 806         PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
 807         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
 808         PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
 809         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
 810         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
 811         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
 812         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
 813         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
 814         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
 815         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
 816         PINMUX_IPSR_DATA(IP2_7_4, MTS),
 817         PINMUX_IPSR_DATA(IP2_7_4, PWM5),
 818         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
 819         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
 820         PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
 821         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
 822         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
 823         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
 824         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
 825         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
 826         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
 827         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
 828         PINMUX_IPSR_DATA(IP2_11_8, STM),
 829         PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
 830         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
 831         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
 832         PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
 833         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
 834         PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
 835         PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
 836         PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
 837         PINMUX_IPSR_DATA(IP2_15_12, MDATA),
 838         PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
 839         PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
 840         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
 841         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
 842         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
 843         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
 844         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
 845         PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
 846         PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
 847         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
 848         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
 849         PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
 850         PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
 851         PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
 852         PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
 853         PINMUX_IPSR_DATA(IP2_21_19, DACK0),
 854         PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
 855         PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
 856         PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
 857         PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
 858         PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
 859         PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
 860         PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
 861         PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
 862         PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
 863         PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
 864         PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
 865         PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
 866         PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
 867         PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
 868         PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
 869         PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
 870         PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
 871         PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
 872         PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
 873         PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
 874         PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
 875
 876         PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
 877         PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
 878         PINMUX_IPSR_DATA(IP3_2_0, DACK1),
 879         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
 880         PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
 881         PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
 882         PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
 883         PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
 884         PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
 885         PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
 886         PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
 887         PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
 888         PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
 889         PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
 890         PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
 891         PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
 892         PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
 893         PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
 894         PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
 895         PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
 896         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
 897         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
 898         PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
 899         PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
 900         PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
 901         PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
 902         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
 903         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
 904         PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
 905         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
 906         PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
 907         PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
 908         PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
 909         PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
 910         PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
 911         PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
 912         PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
 913         PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
 914         PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
 915         PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
 916         PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
 917         PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
 918         PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
 919         PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
 920         PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
 921         PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
 922         PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
 923         PINMUX_IPSR_DATA(IP3_23, QCLK),
 924         PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
 925         PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
 926         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
 927         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
 928         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
 929         PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
 930         PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
 931         PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
 932         PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
 933         PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
 934         PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
 935         PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 936         PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
 937         PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
 938         PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
 939         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
 940         PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
 941
 942         PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
 943         PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
 944         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
 945         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
 946         PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
 947         PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
 948         PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
 949         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
 950         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
 951         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
 952         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
 953         PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
 954         PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
 955         PINMUX_IPSR_DATA(IP4_7_5, PWM6),
 956         PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
 957         PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
 958         PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
 959         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
 960         PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
 961         PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
 962         PINMUX_IPSR_DATA(IP4_10_8, PWM0),
 963         PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
 964         PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
 965         PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
 966         PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
 967         PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
 968         PINMUX_IPSR_DATA(IP4_11, VI2_G0),
 969         PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
 970         PINMUX_IPSR_DATA(IP4_12, VI2_G1),
 971         PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
 972         PINMUX_IPSR_DATA(IP4_13, VI2_G2),
 973         PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
 974         PINMUX_IPSR_DATA(IP4_14, VI2_G3),
 975         PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
 976         PINMUX_IPSR_DATA(IP4_15, VI2_G4),
 977         PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
 978         PINMUX_IPSR_DATA(IP4_16, VI2_G5),
 979         PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
 980         PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
 981         PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
 982         PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
 983         PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
 984         PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
 985         PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
 986         PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
 987         PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
 988         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
 989         PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
 990         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
 991         PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
 992         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
 993         PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
 994         PINMUX_IPSR_DATA(IP4_23, VI2_G6),
 995         PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
 996         PINMUX_IPSR_DATA(IP4_24, VI2_G7),
 997         PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
 998         PINMUX_IPSR_DATA(IP4_25, VI2_R0),
 999         PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
1000         PINMUX_IPSR_DATA(IP4_26, VI2_R1),
1001         PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
1002         PINMUX_IPSR_DATA(IP4_27, VI2_R2),
1003         PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
1004         PINMUX_IPSR_DATA(IP4_28, VI2_R3),
1005         PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
1006         PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
1007         PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
1008         PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
1009         PINMUX_IPSR_DATA(IP4_31_29, TX5),
1010         PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
1011
1012         PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
1013         PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
1014         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
1015         PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
1016         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
1017         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
1018         PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
1019         PINMUX_IPSR_DATA(IP5_3, VI2_R4),
1020         PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
1021         PINMUX_IPSR_DATA(IP5_4, VI2_R5),
1022         PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
1023         PINMUX_IPSR_DATA(IP5_5, VI2_R6),
1024         PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
1025         PINMUX_IPSR_DATA(IP5_6, VI2_R7),
1026         PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
1027         PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
1028         PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
1029         PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
1030         PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
1031         PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
1032         PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
1033         PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
1034         PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
1035         PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
1036         PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
1037         PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
1038         PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
1039         PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
1040         PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
1041         PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
1042         PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
1043         PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1044         PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
1045         PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
1046         PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
1047         PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
1048         PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
1049         PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
1050         PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
1051         PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
1052         PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
1053         PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
1054         PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
1055         PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
1056         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
1057         PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
1058         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
1059         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
1060         PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
1061         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
1062         PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
1063         PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
1064         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1065         PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
1066         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1067         PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
1068         PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
1069         PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
1070         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
1071         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
1072         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
1073         PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
1074         PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
1075         PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
1076         PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
1077         PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
1078         PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
1079
1080         PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
1081         PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
1082         PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
1083         PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
1084         PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
1085         PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
1086         PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
1087         PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
1088         PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
1089         PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
1090         PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
1091         PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
1092         PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
1093         PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
1094         PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
1095         PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
1096         PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
1097         PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
1098         PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1099         PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
1100         PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
1101         PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1102         PINMUX_IPSR_DATA(IP6_14_12, IETX),
1103         PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1104         PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
1105         PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
1106         PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
1107         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1108         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
1109         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1110         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1111         PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
1112         PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
1113         PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1114         PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
1115         PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
1116         PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
1117         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
1118         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1119         PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
1120         PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1121         PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
1122         PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
1123         PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
1124         PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
1125         PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
1126         PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1127         PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
1128         PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
1129         PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
1130         PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
1131
1132         PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
1133         PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
1134         PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1135         PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
1136         PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
1137         PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
1138         PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1139         PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
1140         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1141         PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
1142         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
1143         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1144         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1145         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1146         PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
1147         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
1148         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1149         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1150         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1151         PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
1152         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
1153         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1154         PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
1155         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1156         PINMUX_IPSR_DATA(IP7_14_13, VSP),
1157         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
1158         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1159         PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
1160         PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
1161         PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1162         PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
1163         PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
1164         PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
1165         PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
1166         PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
1167         PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
1168         PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
1169         PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
1170         PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
1171         PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
1172         PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1173         PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
1174         PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
1175         PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
1176         PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
1177         PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
1178         PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
1179         PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
1180         PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
1181         PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
1182         PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
1183         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1184         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1185         PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
1186         PINMUX_IPSR_DATA(IP7_30_29, DACK2),
1187         PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1188
1189         PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
1190         PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
1191         PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
1192         PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
1193         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
1194         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
1195         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
1196         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
1197         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
1198         PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
1199         PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1200         PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
1201         PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
1202         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
1203         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
1204         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
1205         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
1206         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
1207         PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
1208         PINMUX_IPSR_DATA(IP8_11_8, TX0),
1209         PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
1210         PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
1211         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
1212         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
1213         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
1214         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
1215         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
1216         PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
1217         PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
1218         PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
1219         PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
1220         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
1221         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
1222         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
1223         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
1224         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
1225         PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
1226         PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
1227         PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
1228         PINMUX_IPSR_DATA(IP8_18, BPFCLK),
1229         PINMUX_IPSR_DATA(IP8_18, PCMWE),
1230         PINMUX_IPSR_DATA(IP8_19, FMIN),
1231         PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
1232         PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
1233         PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
1234         PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
1235         PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
1236         PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
1237         PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
1238         PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
1239         PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
1240         PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1241         PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
1242         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1243         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1244         PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
1245         PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
1246         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1247         PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
1248         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1249         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1250         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
1251         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1252
1253         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1254         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1255         PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
1256         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1257         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1258         PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
1259         PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
1260         PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
1261         PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
1262         PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
1263         PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
1264         PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
1265         PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
1266         PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
1267         PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
1268         PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
1269         PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
1270         PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
1271         PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
1272         PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
1273         PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
1274         PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1275         PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
1276         PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
1277         PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
1278         PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1279         PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
1280         PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
1281         PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
1282         PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
1283         PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
1284         PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
1285         PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
1286         PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
1287         PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
1288         PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
1289         PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
1290         PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
1291         PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
1292         PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
1293         PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1294         PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
1295         PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
1296         PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
1297         PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1298         PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
1299         PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
1300         PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
1301         PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1302         PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
1303         PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
1304         PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
1305         PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1306         PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
1307
1308         PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
1309         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1310         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1311         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1312         PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
1313         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1314         PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
1315         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1316         PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
1317         PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
1318         PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
1319         PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
1320         PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
1321         PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1322         PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
1323         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
1324         PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
1325         PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
1326         PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
1327         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1328         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
1329         PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
1330         PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
1331         PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
1332         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1333         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1334         PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
1335         PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
1336         PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
1337         PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
1338         PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
1339         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1340         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1341         PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
1342         PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
1343         PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
1344         PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
1345         PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
1346         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1347         PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
1348         PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
1349         PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
1350         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1351         PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
1352         PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
1353         PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
1354         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1355         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1356         PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
1357         PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
1358         PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
1359         PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
1360         PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
1361         PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
1362         PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
1363         PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
1364         PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1365         PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1366         PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
1367         PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
1368         PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
1369         PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
1370         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1371         PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
1372         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
1373
1374         PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
1375         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1376         PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
1377         PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
1378         PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
1379         PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
1380         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1381         PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
1382         PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
1383         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1384         PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
1385         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1386         PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
1387         PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
1388         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1389         PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
1390         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1391         PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
1392         PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
1393         PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
1394         PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
1395         PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
1396         PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
1397         PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
1398         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1399         PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
1400         PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
1401         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
1402         PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
1403         PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
1404         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1405         PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
1406         PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
1407         PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
1408         PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
1409         PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
1410         PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
1411         PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
1412         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
1413         PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
1414         PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
1415         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1416         PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1417         PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1418         PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1419         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1420         PINMUX_IPSR_DATA(IP11_26_24, TX2),
1421         PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
1422         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1423         PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
1424         PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
1425         PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
1426         PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
1427         PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
1428         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
1429         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1430
1431         PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
1432         PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
1433         PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
1434         PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
1435         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
1436         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1437         PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
1438         PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
1439         PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
1440         PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
1441         PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
1442         PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
1443         PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
1444         PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
1445         PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
1446         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
1447         PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
1448         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1449         PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
1450         PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
1451         PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
1452         PINMUX_IPSR_DATA(IP12_11_9, FSE),
1453         PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
1454         PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
1455         PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
1456         PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
1457         PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1458         PINMUX_IPSR_DATA(IP12_14_12, FRB),
1459         PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
1460         PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
1461         PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
1462         PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
1463         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
1464         PINMUX_IPSR_DATA(IP12_17_15, FCE),
1465         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1466 };
1467
1468 static struct sh_pfc_pin pinmux_pins[] = {
1469         PINMUX_GPIO_GP_ALL(),
1470 };
1471
1472 /* - DU0 -------------------------------------------------------------------- */
1473 static const unsigned int du0_rgb666_pins[] = {
1474         /* R[7:2], G[7:2], B[7:2] */
1475         188, 187, 186, 185, 184, 183,
1476         194, 193, 192, 191, 190, 189,
1477         200, 199, 198, 197, 196, 195,
1478 };
1479 static const unsigned int du0_rgb666_mux[] = {
1480         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1481         DU0_DR3_MARK, DU0_DR2_MARK,
1482         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1483         DU0_DG3_MARK, DU0_DG2_MARK,
1484         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1485         DU0_DB3_MARK, DU0_DB2_MARK,
1486 };
1487 static const unsigned int du0_rgb888_pins[] = {
1488         /* R[7:0], G[7:0], B[7:0] */
1489         188, 187, 186, 185, 184, 183, 24, 23,
1490         194, 193, 192, 191, 190, 189, 26, 25,
1491         200, 199, 198, 197, 196, 195, 28, 27,
1492 };
1493 static const unsigned int du0_rgb888_mux[] = {
1494         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1495         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1496         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1497         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1498         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1499         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1500 };
1501 static const unsigned int du0_clk_in_pins[] = {
1502         /* CLKIN */
1503         29,
1504 };
1505 static const unsigned int du0_clk_in_mux[] = {
1506         DU0_DOTCLKIN_MARK,
1507 };
1508 static const unsigned int du0_clk_out_0_pins[] = {
1509         /* CLKOUT */
1510         180,
1511 };
1512 static const unsigned int du0_clk_out_0_mux[] = {
1513         DU0_DOTCLKOUT0_MARK,
1514 };
1515 static const unsigned int du0_clk_out_1_pins[] = {
1516         /* CLKOUT */
1517         30,
1518 };
1519 static const unsigned int du0_clk_out_1_mux[] = {
1520         DU0_DOTCLKOUT1_MARK,
1521 };
1522 static const unsigned int du0_sync_0_pins[] = {
1523         /* VSYNC, HSYNC, DISP */
1524         182, 181, 31,
1525 };
1526 static const unsigned int du0_sync_0_mux[] = {
1527         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1528         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1529 };
1530 static const unsigned int du0_sync_1_pins[] = {
1531         /* VSYNC, HSYNC, DISP */
1532         182, 181, 32,
1533 };
1534 static const unsigned int du0_sync_1_mux[] = {
1535         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1536         DU0_DISP_MARK
1537 };
1538 static const unsigned int du0_oddf_pins[] = {
1539         /* ODDF */
1540         31,
1541 };
1542 static const unsigned int du0_oddf_mux[] = {
1543         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1544 };
1545 static const unsigned int du0_cde_pins[] = {
1546         /* CDE */
1547         33,
1548 };
1549 static const unsigned int du0_cde_mux[] = {
1550         DU0_CDE_MARK
1551 };
1552 /* - DU1 -------------------------------------------------------------------- */
1553 static const unsigned int du1_rgb666_pins[] = {
1554         /* R[7:2], G[7:2], B[7:2] */
1555         41, 40, 39, 38, 37, 36,
1556         49, 48, 47, 46, 45, 44,
1557         57, 56, 55, 54, 53, 52,
1558 };
1559 static const unsigned int du1_rgb666_mux[] = {
1560         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1561         DU1_DR3_MARK, DU1_DR2_MARK,
1562         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1563         DU1_DG3_MARK, DU1_DG2_MARK,
1564         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1565         DU1_DB3_MARK, DU1_DB2_MARK,
1566 };
1567 static const unsigned int du1_rgb888_pins[] = {
1568         /* R[7:0], G[7:0], B[7:0] */
1569         41, 40, 39, 38, 37, 36, 35, 34,
1570         49, 48, 47, 46, 45, 44, 43, 32,
1571         57, 56, 55, 54, 53, 52, 51, 50,
1572 };
1573 static const unsigned int du1_rgb888_mux[] = {
1574         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1575         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1576         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1577         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1578         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1579         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1580 };
1581 static const unsigned int du1_clk_in_pins[] = {
1582         /* CLKIN */
1583         58,
1584 };
1585 static const unsigned int du1_clk_in_mux[] = {
1586         DU1_DOTCLKIN_MARK,
1587 };
1588 static const unsigned int du1_clk_out_pins[] = {
1589         /* CLKOUT */
1590         59,
1591 };
1592 static const unsigned int du1_clk_out_mux[] = {
1593         DU1_DOTCLKOUT_MARK,
1594 };
1595 static const unsigned int du1_sync_0_pins[] = {
1596         /* VSYNC, HSYNC, DISP */
1597         61, 60, 62,
1598 };
1599 static const unsigned int du1_sync_0_mux[] = {
1600         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1601         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1602 };
1603 static const unsigned int du1_sync_1_pins[] = {
1604         /* VSYNC, HSYNC, DISP */
1605         61, 60, 63,
1606 };
1607 static const unsigned int du1_sync_1_mux[] = {
1608         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1609         DU1_DISP_MARK
1610 };
1611 static const unsigned int du1_oddf_pins[] = {
1612         /* ODDF */
1613         62,
1614 };
1615 static const unsigned int du1_oddf_mux[] = {
1616         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1617 };
1618 static const unsigned int du1_cde_pins[] = {
1619         /* CDE */
1620         64,
1621 };
1622 static const unsigned int du1_cde_mux[] = {
1623         DU1_CDE_MARK
1624 };
1625 /* - HSPI0 ------------------------------------------------------------------ */
1626 static const unsigned int hspi0_pins[] = {
1627         /* CLK, CS, RX, TX */
1628         150, 151, 153, 152,
1629 };
1630 static const unsigned int hspi0_mux[] = {
1631         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
1632 };
1633 /* - HSPI1 ------------------------------------------------------------------ */
1634 static const unsigned int hspi1_pins[] = {
1635         /* CLK, CS, RX, TX */
1636         63, 58, 64, 62,
1637 };
1638 static const unsigned int hspi1_mux[] = {
1639         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1640 };
1641 static const unsigned int hspi1_b_pins[] = {
1642         /* CLK, CS, RX, TX */
1643         90, 91, 93, 92,
1644 };
1645 static const unsigned int hspi1_b_mux[] = {
1646         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1647 };
1648 static const unsigned int hspi1_c_pins[] = {
1649         /* CLK, CS, RX, TX */
1650         141, 142, 144, 143,
1651 };
1652 static const unsigned int hspi1_c_mux[] = {
1653         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1654 };
1655 static const unsigned int hspi1_d_pins[] = {
1656         /* CLK, CS, RX, TX */
1657         101, 102, 104, 103,
1658 };
1659 static const unsigned int hspi1_d_mux[] = {
1660         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
1661 };
1662 /* - HSPI2 ------------------------------------------------------------------ */
1663 static const unsigned int hspi2_pins[] = {
1664         /* CLK, CS, RX, TX */
1665         9, 10, 11, 14,
1666 };
1667 static const unsigned int hspi2_mux[] = {
1668         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1669 };
1670 static const unsigned int hspi2_b_pins[] = {
1671         /* CLK, CS, RX, TX */
1672         7, 13, 8, 6,
1673 };
1674 static const unsigned int hspi2_b_mux[] = {
1675         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1676 };
1677 /* - INTC ------------------------------------------------------------------- */
1678 static const unsigned int intc_irq0_pins[] = {
1679         /* IRQ */
1680         78,
1681 };
1682 static const unsigned int intc_irq0_mux[] = {
1683         IRQ0_MARK,
1684 };
1685 static const unsigned int intc_irq0_b_pins[] = {
1686         /* IRQ */
1687         141,
1688 };
1689 static const unsigned int intc_irq0_b_mux[] = {
1690         IRQ0_B_MARK,
1691 };
1692 static const unsigned int intc_irq1_pins[] = {
1693         /* IRQ */
1694         79,
1695 };
1696 static const unsigned int intc_irq1_mux[] = {
1697         IRQ1_MARK,
1698 };
1699 static const unsigned int intc_irq1_b_pins[] = {
1700         /* IRQ */
1701         142,
1702 };
1703 static const unsigned int intc_irq1_b_mux[] = {
1704         IRQ1_B_MARK,
1705 };
1706 static const unsigned int intc_irq2_pins[] = {
1707         /* IRQ */
1708         88,
1709 };
1710 static const unsigned int intc_irq2_mux[] = {
1711         IRQ2_MARK,
1712 };
1713 static const unsigned int intc_irq2_b_pins[] = {
1714         /* IRQ */
1715         143,
1716 };
1717 static const unsigned int intc_irq2_b_mux[] = {
1718         IRQ2_B_MARK,
1719 };
1720 static const unsigned int intc_irq3_pins[] = {
1721         /* IRQ */
1722         89,
1723 };
1724 static const unsigned int intc_irq3_mux[] = {
1725         IRQ3_MARK,
1726 };
1727 static const unsigned int intc_irq3_b_pins[] = {
1728         /* IRQ */
1729         144,
1730 };
1731 static const unsigned int intc_irq3_b_mux[] = {
1732         IRQ3_B_MARK,
1733 };
1734 /* - LSBC ------------------------------------------------------------------- */
1735 static const unsigned int lbsc_cs0_pins[] = {
1736         /* CS */
1737         13,
1738 };
1739 static const unsigned int lbsc_cs0_mux[] = {
1740         CS0_MARK,
1741 };
1742 static const unsigned int lbsc_cs1_pins[] = {
1743         /* CS */
1744         14,
1745 };
1746 static const unsigned int lbsc_cs1_mux[] = {
1747         CS1_A26_MARK,
1748 };
1749 static const unsigned int lbsc_ex_cs0_pins[] = {
1750         /* CS */
1751         15,
1752 };
1753 static const unsigned int lbsc_ex_cs0_mux[] = {
1754         EX_CS0_MARK,
1755 };
1756 static const unsigned int lbsc_ex_cs1_pins[] = {
1757         /* CS */
1758         16,
1759 };
1760 static const unsigned int lbsc_ex_cs1_mux[] = {
1761         EX_CS1_MARK,
1762 };
1763 static const unsigned int lbsc_ex_cs2_pins[] = {
1764         /* CS */
1765         17,
1766 };
1767 static const unsigned int lbsc_ex_cs2_mux[] = {
1768         EX_CS2_MARK,
1769 };
1770 static const unsigned int lbsc_ex_cs3_pins[] = {
1771         /* CS */
1772         18,
1773 };
1774 static const unsigned int lbsc_ex_cs3_mux[] = {
1775         EX_CS3_MARK,
1776 };
1777 static const unsigned int lbsc_ex_cs4_pins[] = {
1778         /* CS */
1779         19,
1780 };
1781 static const unsigned int lbsc_ex_cs4_mux[] = {
1782         EX_CS4_MARK,
1783 };
1784 static const unsigned int lbsc_ex_cs5_pins[] = {
1785         /* CS */
1786         20,
1787 };
1788 static const unsigned int lbsc_ex_cs5_mux[] = {
1789         EX_CS5_MARK,
1790 };
1791 /* - MMCIF ------------------------------------------------------------------ */
1792 static const unsigned int mmc0_data1_pins[] = {
1793         /* D[0] */
1794         19,
1795 };
1796 static const unsigned int mmc0_data1_mux[] = {
1797         MMC0_D0_MARK,
1798 };
1799 static const unsigned int mmc0_data4_pins[] = {
1800         /* D[0:3] */
1801         19, 20, 21, 2,
1802 };
1803 static const unsigned int mmc0_data4_mux[] = {
1804         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1805 };
1806 static const unsigned int mmc0_data8_pins[] = {
1807         /* D[0:7] */
1808         19, 20, 21, 2, 10, 11, 15, 16,
1809 };
1810 static const unsigned int mmc0_data8_mux[] = {
1811         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1812         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1813 };
1814 static const unsigned int mmc0_ctrl_pins[] = {
1815         /* CMD, CLK */
1816         18, 17,
1817 };
1818 static const unsigned int mmc0_ctrl_mux[] = {
1819         MMC0_CMD_MARK, MMC0_CLK_MARK,
1820 };
1821 static const unsigned int mmc1_data1_pins[] = {
1822         /* D[0] */
1823         72,
1824 };
1825 static const unsigned int mmc1_data1_mux[] = {
1826         MMC1_D0_MARK,
1827 };
1828 static const unsigned int mmc1_data4_pins[] = {
1829         /* D[0:3] */
1830         72, 73, 74, 75,
1831 };
1832 static const unsigned int mmc1_data4_mux[] = {
1833         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1834 };
1835 static const unsigned int mmc1_data8_pins[] = {
1836         /* D[0:7] */
1837         72, 73, 74, 75, 76, 77, 80, 81,
1838 };
1839 static const unsigned int mmc1_data8_mux[] = {
1840         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1841         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1842 };
1843 static const unsigned int mmc1_ctrl_pins[] = {
1844         /* CMD, CLK */
1845         68, 65,
1846 };
1847 static const unsigned int mmc1_ctrl_mux[] = {
1848         MMC1_CMD_MARK, MMC1_CLK_MARK,
1849 };
1850 /* - SCIF0 ------------------------------------------------------------------ */
1851 static const unsigned int scif0_data_pins[] = {
1852         /* RXD, TXD */
1853         153, 152,
1854 };
1855 static const unsigned int scif0_data_mux[] = {
1856         RX0_MARK, TX0_MARK,
1857 };
1858 static const unsigned int scif0_clk_pins[] = {
1859         /* SCK */
1860         156,
1861 };
1862 static const unsigned int scif0_clk_mux[] = {
1863         SCK0_MARK,
1864 };
1865 static const unsigned int scif0_ctrl_pins[] = {
1866         /* RTS, CTS */
1867         151, 150,
1868 };
1869 static const unsigned int scif0_ctrl_mux[] = {
1870         RTS0_TANS_MARK, CTS0_MARK,
1871 };
1872 static const unsigned int scif0_data_b_pins[] = {
1873         /* RXD, TXD */
1874         20, 19,
1875 };
1876 static const unsigned int scif0_data_b_mux[] = {
1877         RX0_B_MARK, TX0_B_MARK,
1878 };
1879 static const unsigned int scif0_clk_b_pins[] = {
1880         /* SCK */
1881         33,
1882 };
1883 static const unsigned int scif0_clk_b_mux[] = {
1884         SCK0_B_MARK,
1885 };
1886 static const unsigned int scif0_ctrl_b_pins[] = {
1887         /* RTS, CTS */
1888         18, 11,
1889 };
1890 static const unsigned int scif0_ctrl_b_mux[] = {
1891         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
1892 };
1893 static const unsigned int scif0_data_c_pins[] = {
1894         /* RXD, TXD */
1895         146, 147,
1896 };
1897 static const unsigned int scif0_data_c_mux[] = {
1898         RX0_C_MARK, TX0_C_MARK,
1899 };
1900 static const unsigned int scif0_clk_c_pins[] = {
1901         /* SCK */
1902         145,
1903 };
1904 static const unsigned int scif0_clk_c_mux[] = {
1905         SCK0_C_MARK,
1906 };
1907 static const unsigned int scif0_ctrl_c_pins[] = {
1908         /* RTS, CTS */
1909         149, 148,
1910 };
1911 static const unsigned int scif0_ctrl_c_mux[] = {
1912         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
1913 };
1914 static const unsigned int scif0_data_d_pins[] = {
1915         /* RXD, TXD */
1916         43, 42,
1917 };
1918 static const unsigned int scif0_data_d_mux[] = {
1919         RX0_D_MARK, TX0_D_MARK,
1920 };
1921 static const unsigned int scif0_clk_d_pins[] = {
1922         /* SCK */
1923         50,
1924 };
1925 static const unsigned int scif0_clk_d_mux[] = {
1926         SCK0_D_MARK,
1927 };
1928 static const unsigned int scif0_ctrl_d_pins[] = {
1929         /* RTS, CTS */
1930         51, 35,
1931 };
1932 static const unsigned int scif0_ctrl_d_mux[] = {
1933         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
1934 };
1935 /* - SCIF1 ------------------------------------------------------------------ */
1936 static const unsigned int scif1_data_pins[] = {
1937         /* RXD, TXD */
1938         149, 148,
1939 };
1940 static const unsigned int scif1_data_mux[] = {
1941         RX1_MARK, TX1_MARK,
1942 };
1943 static const unsigned int scif1_clk_pins[] = {
1944         /* SCK */
1945         145,
1946 };
1947 static const unsigned int scif1_clk_mux[] = {
1948         SCK1_MARK,
1949 };
1950 static const unsigned int scif1_ctrl_pins[] = {
1951         /* RTS, CTS */
1952         147, 146,
1953 };
1954 static const unsigned int scif1_ctrl_mux[] = {
1955         RTS1_TANS_MARK, CTS1_MARK,
1956 };
1957 static const unsigned int scif1_data_b_pins[] = {
1958         /* RXD, TXD */
1959         117, 114,
1960 };
1961 static const unsigned int scif1_data_b_mux[] = {
1962         RX1_B_MARK, TX1_B_MARK,
1963 };
1964 static const unsigned int scif1_clk_b_pins[] = {
1965         /* SCK */
1966         113,
1967 };
1968 static const unsigned int scif1_clk_b_mux[] = {
1969         SCK1_B_MARK,
1970 };
1971 static const unsigned int scif1_ctrl_b_pins[] = {
1972         /* RTS, CTS */
1973         115, 116,
1974 };
1975 static const unsigned int scif1_ctrl_b_mux[] = {
1976         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
1977 };
1978 static const unsigned int scif1_data_c_pins[] = {
1979         /* RXD, TXD */
1980         67, 66,
1981 };
1982 static const unsigned int scif1_data_c_mux[] = {
1983         RX1_C_MARK, TX1_C_MARK,
1984 };
1985 static const unsigned int scif1_clk_c_pins[] = {
1986         /* SCK */
1987         86,
1988 };
1989 static const unsigned int scif1_clk_c_mux[] = {
1990         SCK1_C_MARK,
1991 };
1992 static const unsigned int scif1_ctrl_c_pins[] = {
1993         /* RTS, CTS */
1994         69, 68,
1995 };
1996 static const unsigned int scif1_ctrl_c_mux[] = {
1997         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
1998 };
1999 /* - SCIF2 ------------------------------------------------------------------ */
2000 static const unsigned int scif2_data_pins[] = {
2001         /* RXD, TXD */
2002         106, 105,
2003 };
2004 static const unsigned int scif2_data_mux[] = {
2005         RX2_MARK, TX2_MARK,
2006 };
2007 static const unsigned int scif2_clk_pins[] = {
2008         /* SCK */
2009         107,
2010 };
2011 static const unsigned int scif2_clk_mux[] = {
2012         SCK2_MARK,
2013 };
2014 static const unsigned int scif2_data_b_pins[] = {
2015         /* RXD, TXD */
2016         120, 119,
2017 };
2018 static const unsigned int scif2_data_b_mux[] = {
2019         RX2_B_MARK, TX2_B_MARK,
2020 };
2021 static const unsigned int scif2_clk_b_pins[] = {
2022         /* SCK */
2023         118,
2024 };
2025 static const unsigned int scif2_clk_b_mux[] = {
2026         SCK2_B_MARK,
2027 };
2028 static const unsigned int scif2_data_c_pins[] = {
2029         /* RXD, TXD */
2030         33, 31,
2031 };
2032 static const unsigned int scif2_data_c_mux[] = {
2033         RX2_C_MARK, TX2_C_MARK,
2034 };
2035 static const unsigned int scif2_clk_c_pins[] = {
2036         /* SCK */
2037         32,
2038 };
2039 static const unsigned int scif2_clk_c_mux[] = {
2040         SCK2_C_MARK,
2041 };
2042 static const unsigned int scif2_data_d_pins[] = {
2043         /* RXD, TXD */
2044         64, 62,
2045 };
2046 static const unsigned int scif2_data_d_mux[] = {
2047         RX2_D_MARK, TX2_D_MARK,
2048 };
2049 static const unsigned int scif2_clk_d_pins[] = {
2050         /* SCK */
2051         63,
2052 };
2053 static const unsigned int scif2_clk_d_mux[] = {
2054         SCK2_D_MARK,
2055 };
2056 static const unsigned int scif2_data_e_pins[] = {
2057         /* RXD, TXD */
2058         20, 19,
2059 };
2060 static const unsigned int scif2_data_e_mux[] = {
2061         RX2_E_MARK, TX2_E_MARK,
2062 };
2063 /* - SCIF3 ------------------------------------------------------------------ */
2064 static const unsigned int scif3_data_pins[] = {
2065         /* RXD, TXD */
2066         137, 136,
2067 };
2068 static const unsigned int scif3_data_mux[] = {
2069         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
2070 };
2071 static const unsigned int scif3_clk_pins[] = {
2072         /* SCK */
2073         135,
2074 };
2075 static const unsigned int scif3_clk_mux[] = {
2076         SCK3_MARK,
2077 };
2078
2079 static const unsigned int scif3_data_b_pins[] = {
2080         /* RXD, TXD */
2081         64, 62,
2082 };
2083 static const unsigned int scif3_data_b_mux[] = {
2084         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
2085 };
2086 static const unsigned int scif3_data_c_pins[] = {
2087         /* RXD, TXD */
2088         15, 12,
2089 };
2090 static const unsigned int scif3_data_c_mux[] = {
2091         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
2092 };
2093 static const unsigned int scif3_data_d_pins[] = {
2094         /* RXD, TXD */
2095         30, 29,
2096 };
2097 static const unsigned int scif3_data_d_mux[] = {
2098         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
2099 };
2100 static const unsigned int scif3_data_e_pins[] = {
2101         /* RXD, TXD */
2102         35, 34,
2103 };
2104 static const unsigned int scif3_data_e_mux[] = {
2105         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
2106 };
2107 static const unsigned int scif3_clk_e_pins[] = {
2108         /* SCK */
2109         42,
2110 };
2111 static const unsigned int scif3_clk_e_mux[] = {
2112         SCK3_E_MARK,
2113 };
2114 /* - SCIF4 ------------------------------------------------------------------ */
2115 static const unsigned int scif4_data_pins[] = {
2116         /* RXD, TXD */
2117         123, 122,
2118 };
2119 static const unsigned int scif4_data_mux[] = {
2120         RX4_MARK, TX4_MARK,
2121 };
2122 static const unsigned int scif4_clk_pins[] = {
2123         /* SCK */
2124         121,
2125 };
2126 static const unsigned int scif4_clk_mux[] = {
2127         SCK4_MARK,
2128 };
2129 static const unsigned int scif4_data_b_pins[] = {
2130         /* RXD, TXD */
2131         111, 110,
2132 };
2133 static const unsigned int scif4_data_b_mux[] = {
2134         RX4_B_MARK, TX4_B_MARK,
2135 };
2136 static const unsigned int scif4_clk_b_pins[] = {
2137         /* SCK */
2138         112,
2139 };
2140 static const unsigned int scif4_clk_b_mux[] = {
2141         SCK4_B_MARK,
2142 };
2143 static const unsigned int scif4_data_c_pins[] = {
2144         /* RXD, TXD */
2145         22, 21,
2146 };
2147 static const unsigned int scif4_data_c_mux[] = {
2148         RX4_C_MARK, TX4_C_MARK,
2149 };
2150 static const unsigned int scif4_data_d_pins[] = {
2151         /* RXD, TXD */
2152         69, 68,
2153 };
2154 static const unsigned int scif4_data_d_mux[] = {
2155         RX4_D_MARK, TX4_D_MARK,
2156 };
2157 /* - SCIF5 ------------------------------------------------------------------ */
2158 static const unsigned int scif5_data_pins[] = {
2159         /* RXD, TXD */
2160         51, 50,
2161 };
2162 static const unsigned int scif5_data_mux[] = {
2163         RX5_MARK, TX5_MARK,
2164 };
2165 static const unsigned int scif5_clk_pins[] = {
2166         /* SCK */
2167         43,
2168 };
2169 static const unsigned int scif5_clk_mux[] = {
2170         SCK5_MARK,
2171 };
2172 static const unsigned int scif5_data_b_pins[] = {
2173         /* RXD, TXD */
2174         18, 11,
2175 };
2176 static const unsigned int scif5_data_b_mux[] = {
2177         RX5_B_MARK, TX5_B_MARK,
2178 };
2179 static const unsigned int scif5_clk_b_pins[] = {
2180         /* SCK */
2181         19,
2182 };
2183 static const unsigned int scif5_clk_b_mux[] = {
2184         SCK5_B_MARK,
2185 };
2186 static const unsigned int scif5_data_c_pins[] = {
2187         /* RXD, TXD */
2188         24, 23,
2189 };
2190 static const unsigned int scif5_data_c_mux[] = {
2191         RX5_C_MARK, TX5_C_MARK,
2192 };
2193 static const unsigned int scif5_clk_c_pins[] = {
2194         /* SCK */
2195         28,
2196 };
2197 static const unsigned int scif5_clk_c_mux[] = {
2198         SCK5_C_MARK,
2199 };
2200 static const unsigned int scif5_data_d_pins[] = {
2201         /* RXD, TXD */
2202         8, 6,
2203 };
2204 static const unsigned int scif5_data_d_mux[] = {
2205         RX5_D_MARK, TX5_D_MARK,
2206 };
2207 static const unsigned int scif5_clk_d_pins[] = {
2208         /* SCK */
2209         7,
2210 };
2211 static const unsigned int scif5_clk_d_mux[] = {
2212         SCK5_D_MARK,
2213 };
2214 /* - SDHI0 ------------------------------------------------------------------ */
2215 static const unsigned int sdhi0_data1_pins[] = {
2216         /* D0 */
2217         117,
2218 };
2219 static const unsigned int sdhi0_data1_mux[] = {
2220         SD0_DAT0_MARK,
2221 };
2222 static const unsigned int sdhi0_data4_pins[] = {
2223         /* D[0:3] */
2224         117, 118, 119, 120,
2225 };
2226 static const unsigned int sdhi0_data4_mux[] = {
2227         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2228 };
2229 static const unsigned int sdhi0_ctrl_pins[] = {
2230         /* CMD, CLK */
2231         114, 113,
2232 };
2233 static const unsigned int sdhi0_ctrl_mux[] = {
2234         SD0_CMD_MARK, SD0_CLK_MARK,
2235 };
2236 static const unsigned int sdhi0_cd_pins[] = {
2237         /* CD */
2238         115,
2239 };
2240 static const unsigned int sdhi0_cd_mux[] = {
2241         SD0_CD_MARK,
2242 };
2243 static const unsigned int sdhi0_wp_pins[] = {
2244         /* WP */
2245         116,
2246 };
2247 static const unsigned int sdhi0_wp_mux[] = {
2248         SD0_WP_MARK,
2249 };
2250 /* - SDHI1 ------------------------------------------------------------------ */
2251 static const unsigned int sdhi1_data1_pins[] = {
2252         /* D0 */
2253         19,
2254 };
2255 static const unsigned int sdhi1_data1_mux[] = {
2256         SD1_DAT0_MARK,
2257 };
2258 static const unsigned int sdhi1_data4_pins[] = {
2259         /* D[0:3] */
2260         19, 20, 21, 2,
2261 };
2262 static const unsigned int sdhi1_data4_mux[] = {
2263         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2264 };
2265 static const unsigned int sdhi1_ctrl_pins[] = {
2266         /* CMD, CLK */
2267         18, 17,
2268 };
2269 static const unsigned int sdhi1_ctrl_mux[] = {
2270         SD1_CMD_MARK, SD1_CLK_MARK,
2271 };
2272 static const unsigned int sdhi1_cd_pins[] = {
2273         /* CD */
2274         10,
2275 };
2276 static const unsigned int sdhi1_cd_mux[] = {
2277         SD1_CD_MARK,
2278 };
2279 static const unsigned int sdhi1_wp_pins[] = {
2280         /* WP */
2281         11,
2282 };
2283 static const unsigned int sdhi1_wp_mux[] = {
2284         SD1_WP_MARK,
2285 };
2286 /* - SDHI2 ------------------------------------------------------------------ */
2287 static const unsigned int sdhi2_data1_pins[] = {
2288         /* D0 */
2289         97,
2290 };
2291 static const unsigned int sdhi2_data1_mux[] = {
2292         SD2_DAT0_MARK,
2293 };
2294 static const unsigned int sdhi2_data4_pins[] = {
2295         /* D[0:3] */
2296         97, 98, 99, 100,
2297 };
2298 static const unsigned int sdhi2_data4_mux[] = {
2299         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2300 };
2301 static const unsigned int sdhi2_ctrl_pins[] = {
2302         /* CMD, CLK */
2303         102, 101,
2304 };
2305 static const unsigned int sdhi2_ctrl_mux[] = {
2306         SD2_CMD_MARK, SD2_CLK_MARK,
2307 };
2308 static const unsigned int sdhi2_cd_pins[] = {
2309         /* CD */
2310         103,
2311 };
2312 static const unsigned int sdhi2_cd_mux[] = {
2313         SD2_CD_MARK,
2314 };
2315 static const unsigned int sdhi2_wp_pins[] = {
2316         /* WP */
2317         104,
2318 };
2319 static const unsigned int sdhi2_wp_mux[] = {
2320         SD2_WP_MARK,
2321 };
2322 /* - SDHI3 ------------------------------------------------------------------ */
2323 static const unsigned int sdhi3_data1_pins[] = {
2324         /* D0 */
2325         50,
2326 };
2327 static const unsigned int sdhi3_data1_mux[] = {
2328         SD3_DAT0_MARK,
2329 };
2330 static const unsigned int sdhi3_data4_pins[] = {
2331         /* D[0:3] */
2332         50, 51, 52, 53,
2333 };
2334 static const unsigned int sdhi3_data4_mux[] = {
2335         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2336 };
2337 static const unsigned int sdhi3_ctrl_pins[] = {
2338         /* CMD, CLK */
2339         35, 34,
2340 };
2341 static const unsigned int sdhi3_ctrl_mux[] = {
2342         SD3_CMD_MARK, SD3_CLK_MARK,
2343 };
2344 static const unsigned int sdhi3_cd_pins[] = {
2345         /* CD */
2346         62,
2347 };
2348 static const unsigned int sdhi3_cd_mux[] = {
2349         SD3_CD_MARK,
2350 };
2351 static const unsigned int sdhi3_wp_pins[] = {
2352         /* WP */
2353         64,
2354 };
2355 static const unsigned int sdhi3_wp_mux[] = {
2356         SD3_WP_MARK,
2357 };
2358 /* - USB0 ------------------------------------------------------------------- */
2359 static const unsigned int usb0_pins[] = {
2360         /* PENC */
2361         154,
2362 };
2363 static const unsigned int usb0_mux[] = {
2364         USB_PENC0_MARK,
2365 };
2366 static const unsigned int usb0_ovc_pins[] = {
2367         /* USB_OVC */
2368         150
2369 };
2370 static const unsigned int usb0_ovc_mux[] = {
2371         USB_OVC0_MARK,
2372 };
2373 /* - USB1 ------------------------------------------------------------------- */
2374 static const unsigned int usb1_pins[] = {
2375         /* PENC */
2376         155,
2377 };
2378 static const unsigned int usb1_mux[] = {
2379         USB_PENC1_MARK,
2380 };
2381 static const unsigned int usb1_ovc_pins[] = {
2382         /* USB_OVC */
2383         152,
2384 };
2385 static const unsigned int usb1_ovc_mux[] = {
2386         USB_OVC1_MARK,
2387 };
2388 /* - USB2 ------------------------------------------------------------------- */
2389 static const unsigned int usb2_pins[] = {
2390         /* PENC */
2391         156,
2392 };
2393 static const unsigned int usb2_mux[] = {
2394         USB_PENC2_MARK,
2395 };
2396 static const unsigned int usb2_ovc_pins[] = {
2397         /* USB_OVC */
2398         125,
2399 };
2400 static const unsigned int usb2_ovc_mux[] = {
2401         USB_OVC2_MARK,
2402 };
2403
2404 static const struct sh_pfc_pin_group pinmux_groups[] = {
2405         SH_PFC_PIN_GROUP(du0_rgb666),
2406         SH_PFC_PIN_GROUP(du0_rgb888),
2407         SH_PFC_PIN_GROUP(du0_clk_in),
2408         SH_PFC_PIN_GROUP(du0_clk_out_0),
2409         SH_PFC_PIN_GROUP(du0_clk_out_1),
2410         SH_PFC_PIN_GROUP(du0_sync_0),
2411         SH_PFC_PIN_GROUP(du0_sync_1),
2412         SH_PFC_PIN_GROUP(du0_oddf),
2413         SH_PFC_PIN_GROUP(du0_cde),
2414         SH_PFC_PIN_GROUP(du1_rgb666),
2415         SH_PFC_PIN_GROUP(du1_rgb888),
2416         SH_PFC_PIN_GROUP(du1_clk_in),
2417         SH_PFC_PIN_GROUP(du1_clk_out),
2418         SH_PFC_PIN_GROUP(du1_sync_0),
2419         SH_PFC_PIN_GROUP(du1_sync_1),
2420         SH_PFC_PIN_GROUP(du1_oddf),
2421         SH_PFC_PIN_GROUP(du1_cde),
2422         SH_PFC_PIN_GROUP(hspi0),
2423         SH_PFC_PIN_GROUP(hspi1),
2424         SH_PFC_PIN_GROUP(hspi1_b),
2425         SH_PFC_PIN_GROUP(hspi1_c),
2426         SH_PFC_PIN_GROUP(hspi1_d),
2427         SH_PFC_PIN_GROUP(hspi2),
2428         SH_PFC_PIN_GROUP(hspi2_b),
2429         SH_PFC_PIN_GROUP(intc_irq0),
2430         SH_PFC_PIN_GROUP(intc_irq0_b),
2431         SH_PFC_PIN_GROUP(intc_irq1),
2432         SH_PFC_PIN_GROUP(intc_irq1_b),
2433         SH_PFC_PIN_GROUP(intc_irq2),
2434         SH_PFC_PIN_GROUP(intc_irq2_b),
2435         SH_PFC_PIN_GROUP(intc_irq3),
2436         SH_PFC_PIN_GROUP(intc_irq3_b),
2437         SH_PFC_PIN_GROUP(lbsc_cs0),
2438         SH_PFC_PIN_GROUP(lbsc_cs1),
2439         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
2440         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
2441         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
2442         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
2443         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
2444         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
2445         SH_PFC_PIN_GROUP(mmc0_data1),
2446         SH_PFC_PIN_GROUP(mmc0_data4),
2447         SH_PFC_PIN_GROUP(mmc0_data8),
2448         SH_PFC_PIN_GROUP(mmc0_ctrl),
2449         SH_PFC_PIN_GROUP(mmc1_data1),
2450         SH_PFC_PIN_GROUP(mmc1_data4),
2451         SH_PFC_PIN_GROUP(mmc1_data8),
2452         SH_PFC_PIN_GROUP(mmc1_ctrl),
2453         SH_PFC_PIN_GROUP(scif0_data),
2454         SH_PFC_PIN_GROUP(scif0_clk),
2455         SH_PFC_PIN_GROUP(scif0_ctrl),
2456         SH_PFC_PIN_GROUP(scif0_data_b),
2457         SH_PFC_PIN_GROUP(scif0_clk_b),
2458         SH_PFC_PIN_GROUP(scif0_ctrl_b),
2459         SH_PFC_PIN_GROUP(scif0_data_c),
2460         SH_PFC_PIN_GROUP(scif0_clk_c),
2461         SH_PFC_PIN_GROUP(scif0_ctrl_c),
2462         SH_PFC_PIN_GROUP(scif0_data_d),
2463         SH_PFC_PIN_GROUP(scif0_clk_d),
2464         SH_PFC_PIN_GROUP(scif0_ctrl_d),
2465         SH_PFC_PIN_GROUP(scif1_data),
2466         SH_PFC_PIN_GROUP(scif1_clk),
2467         SH_PFC_PIN_GROUP(scif1_ctrl),
2468         SH_PFC_PIN_GROUP(scif1_data_b),
2469         SH_PFC_PIN_GROUP(scif1_clk_b),
2470         SH_PFC_PIN_GROUP(scif1_ctrl_b),
2471         SH_PFC_PIN_GROUP(scif1_data_c),
2472         SH_PFC_PIN_GROUP(scif1_clk_c),
2473         SH_PFC_PIN_GROUP(scif1_ctrl_c),
2474         SH_PFC_PIN_GROUP(scif2_data),
2475         SH_PFC_PIN_GROUP(scif2_clk),
2476         SH_PFC_PIN_GROUP(scif2_data_b),
2477         SH_PFC_PIN_GROUP(scif2_clk_b),
2478         SH_PFC_PIN_GROUP(scif2_data_c),
2479         SH_PFC_PIN_GROUP(scif2_clk_c),
2480         SH_PFC_PIN_GROUP(scif2_data_d),
2481         SH_PFC_PIN_GROUP(scif2_clk_d),
2482         SH_PFC_PIN_GROUP(scif2_data_e),
2483         SH_PFC_PIN_GROUP(scif3_data),
2484         SH_PFC_PIN_GROUP(scif3_clk),
2485         SH_PFC_PIN_GROUP(scif3_data_b),
2486         SH_PFC_PIN_GROUP(scif3_data_c),
2487         SH_PFC_PIN_GROUP(scif3_data_d),
2488         SH_PFC_PIN_GROUP(scif3_data_e),
2489         SH_PFC_PIN_GROUP(scif3_clk_e),
2490         SH_PFC_PIN_GROUP(scif4_data),
2491         SH_PFC_PIN_GROUP(scif4_clk),
2492         SH_PFC_PIN_GROUP(scif4_data_b),
2493         SH_PFC_PIN_GROUP(scif4_clk_b),
2494         SH_PFC_PIN_GROUP(scif4_data_c),
2495         SH_PFC_PIN_GROUP(scif4_data_d),
2496         SH_PFC_PIN_GROUP(scif5_data),
2497         SH_PFC_PIN_GROUP(scif5_clk),
2498         SH_PFC_PIN_GROUP(scif5_data_b),
2499         SH_PFC_PIN_GROUP(scif5_clk_b),
2500         SH_PFC_PIN_GROUP(scif5_data_c),
2501         SH_PFC_PIN_GROUP(scif5_clk_c),
2502         SH_PFC_PIN_GROUP(scif5_data_d),
2503         SH_PFC_PIN_GROUP(scif5_clk_d),
2504         SH_PFC_PIN_GROUP(sdhi0_data1),
2505         SH_PFC_PIN_GROUP(sdhi0_data4),
2506         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2507         SH_PFC_PIN_GROUP(sdhi0_cd),
2508         SH_PFC_PIN_GROUP(sdhi0_wp),
2509         SH_PFC_PIN_GROUP(sdhi1_data1),
2510         SH_PFC_PIN_GROUP(sdhi1_data4),
2511         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2512         SH_PFC_PIN_GROUP(sdhi1_cd),
2513         SH_PFC_PIN_GROUP(sdhi1_wp),
2514         SH_PFC_PIN_GROUP(sdhi2_data1),
2515         SH_PFC_PIN_GROUP(sdhi2_data4),
2516         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2517         SH_PFC_PIN_GROUP(sdhi2_cd),
2518         SH_PFC_PIN_GROUP(sdhi2_wp),
2519         SH_PFC_PIN_GROUP(sdhi3_data1),
2520         SH_PFC_PIN_GROUP(sdhi3_data4),
2521         SH_PFC_PIN_GROUP(sdhi3_ctrl),
2522         SH_PFC_PIN_GROUP(sdhi3_cd),
2523         SH_PFC_PIN_GROUP(sdhi3_wp),
2524         SH_PFC_PIN_GROUP(usb0),
2525         SH_PFC_PIN_GROUP(usb0_ovc),
2526         SH_PFC_PIN_GROUP(usb1),
2527         SH_PFC_PIN_GROUP(usb1_ovc),
2528         SH_PFC_PIN_GROUP(usb2),
2529         SH_PFC_PIN_GROUP(usb2_ovc),
2530 };
2531
2532 static const char * const du0_groups[] = {
2533         "du0_rgb666",
2534         "du0_rgb888",
2535         "du0_clk_in",
2536         "du0_clk_out_0",
2537         "du0_clk_out_1",
2538         "du0_sync_0",
2539         "du0_sync_1",
2540         "du0_oddf",
2541         "du0_cde",
2542 };
2543
2544 static const char * const du1_groups[] = {
2545         "du1_rgb666",
2546         "du1_rgb888",
2547         "du1_clk_in",
2548         "du1_clk_out",
2549         "du1_sync_0",
2550         "du1_sync_1",
2551         "du1_oddf",
2552         "du1_cde",
2553 };
2554
2555 static const char * const hspi0_groups[] = {
2556         "hspi0",
2557 };
2558
2559 static const char * const hspi1_groups[] = {
2560         "hspi1",
2561         "hspi1_b",
2562         "hspi1_c",
2563         "hspi1_d",
2564 };
2565
2566 static const char * const hspi2_groups[] = {
2567         "hspi2",
2568         "hspi2_b",
2569 };
2570
2571 static const char * const intc_groups[] = {
2572         "intc_irq0",
2573         "intc_irq0_b",
2574         "intc_irq1",
2575         "intc_irq1_b",
2576         "intc_irq2",
2577         "intc_irq2_b",
2578         "intc_irq3",
2579         "intc_irq3_b",
2580 };
2581
2582 static const char * const lbsc_groups[] = {
2583         "lbsc_cs0",
2584         "lbsc_cs1",
2585         "lbsc_ex_cs0",
2586         "lbsc_ex_cs1",
2587         "lbsc_ex_cs2",
2588         "lbsc_ex_cs3",
2589         "lbsc_ex_cs4",
2590         "lbsc_ex_cs5",
2591 };
2592
2593 static const char * const mmc0_groups[] = {
2594         "mmc0_data1",
2595         "mmc0_data4",
2596         "mmc0_data8",
2597         "mmc0_ctrl",
2598 };
2599
2600 static const char * const mmc1_groups[] = {
2601         "mmc1_data1",
2602         "mmc1_data4",
2603         "mmc1_data8",
2604         "mmc1_ctrl",
2605 };
2606
2607 static const char * const scif0_groups[] = {
2608         "scif0_data",
2609         "scif0_clk",
2610         "scif0_ctrl",
2611         "scif0_data_b",
2612         "scif0_clk_b",
2613         "scif0_ctrl_b",
2614         "scif0_data_c",
2615         "scif0_clk_c",
2616         "scif0_ctrl_c",
2617         "scif0_data_d",
2618         "scif0_clk_d",
2619         "scif0_ctrl_d",
2620 };
2621
2622 static const char * const scif1_groups[] = {
2623         "scif1_data",
2624         "scif1_clk",
2625         "scif1_ctrl",
2626         "scif1_data_b",
2627         "scif1_clk_b",
2628         "scif1_ctrl_b",
2629         "scif1_data_c",
2630         "scif1_clk_c",
2631         "scif1_ctrl_c",
2632 };
2633
2634 static const char * const scif2_groups[] = {
2635         "scif2_data",
2636         "scif2_clk",
2637         "scif2_data_b",
2638         "scif2_clk_b",
2639         "scif2_data_c",
2640         "scif2_clk_c",
2641         "scif2_data_d",
2642         "scif2_clk_d",
2643         "scif2_data_e",
2644 };
2645
2646 static const char * const scif3_groups[] = {
2647         "scif3_data",
2648         "scif3_clk",
2649         "scif3_data_b",
2650         "scif3_data_c",
2651         "scif3_data_d",
2652         "scif3_data_e",
2653         "scif3_clk_e",
2654 };
2655
2656 static const char * const scif4_groups[] = {
2657         "scif4_data",
2658         "scif4_clk",
2659         "scif4_data_b",
2660         "scif4_clk_b",
2661         "scif4_data_c",
2662         "scif4_data_d",
2663 };
2664
2665 static const char * const scif5_groups[] = {
2666         "scif5_data",
2667         "scif5_clk",
2668         "scif5_data_b",
2669         "scif5_clk_b",
2670         "scif5_data_c",
2671         "scif5_clk_c",
2672         "scif5_data_d",
2673         "scif5_clk_d",
2674 };
2675
2676 static const char * const sdhi0_groups[] = {
2677         "sdhi0_data1",
2678         "sdhi0_data4",
2679         "sdhi0_ctrl",
2680         "sdhi0_cd",
2681         "sdhi0_wp",
2682 };
2683
2684 static const char * const sdhi1_groups[] = {
2685         "sdhi1_data1",
2686         "sdhi1_data4",
2687         "sdhi1_ctrl",
2688         "sdhi1_cd",
2689         "sdhi1_wp",
2690 };
2691
2692 static const char * const sdhi2_groups[] = {
2693         "sdhi2_data1",
2694         "sdhi2_data4",
2695         "sdhi2_ctrl",
2696         "sdhi2_cd",
2697         "sdhi2_wp",
2698 };
2699
2700 static const char * const sdhi3_groups[] = {
2701         "sdhi3_data1",
2702         "sdhi3_data4",
2703         "sdhi3_ctrl",
2704         "sdhi3_cd",
2705         "sdhi3_wp",
2706 };
2707
2708 static const char * const usb0_groups[] = {
2709         "usb0",
2710         "usb0_ovc",
2711 };
2712
2713 static const char * const usb1_groups[] = {
2714         "usb1",
2715         "usb1_ovc",
2716 };
2717
2718 static const char * const usb2_groups[] = {
2719         "usb2",
2720         "usb2_ovc",
2721 };
2722
2723 static const struct sh_pfc_function pinmux_functions[] = {
2724         SH_PFC_FUNCTION(du0),
2725         SH_PFC_FUNCTION(du1),
2726         SH_PFC_FUNCTION(hspi0),
2727         SH_PFC_FUNCTION(hspi1),
2728         SH_PFC_FUNCTION(hspi2),
2729         SH_PFC_FUNCTION(intc),
2730         SH_PFC_FUNCTION(lbsc),
2731         SH_PFC_FUNCTION(mmc0),
2732         SH_PFC_FUNCTION(mmc1),
2733         SH_PFC_FUNCTION(sdhi0),
2734         SH_PFC_FUNCTION(sdhi1),
2735         SH_PFC_FUNCTION(sdhi2),
2736         SH_PFC_FUNCTION(sdhi3),
2737         SH_PFC_FUNCTION(scif0),
2738         SH_PFC_FUNCTION(scif1),
2739         SH_PFC_FUNCTION(scif2),
2740         SH_PFC_FUNCTION(scif3),
2741         SH_PFC_FUNCTION(scif4),
2742         SH_PFC_FUNCTION(scif5),
2743         SH_PFC_FUNCTION(usb0),
2744         SH_PFC_FUNCTION(usb1),
2745         SH_PFC_FUNCTION(usb2),
2746 };
2747
2748 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2749         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
2750                 GP_0_31_FN, FN_IP3_31_29,
2751                 GP_0_30_FN, FN_IP3_26_24,
2752                 GP_0_29_FN, FN_IP3_22_21,
2753                 GP_0_28_FN, FN_IP3_14_12,
2754                 GP_0_27_FN, FN_IP3_11_9,
2755                 GP_0_26_FN, FN_IP3_2_0,
2756                 GP_0_25_FN, FN_IP2_30_28,
2757                 GP_0_24_FN, FN_IP2_21_19,
2758                 GP_0_23_FN, FN_IP2_18_16,
2759                 GP_0_22_FN, FN_IP0_30_28,
2760                 GP_0_21_FN, FN_IP0_5_3,
2761                 GP_0_20_FN, FN_IP1_18_15,
2762                 GP_0_19_FN, FN_IP1_14_11,
2763                 GP_0_18_FN, FN_IP1_10_7,
2764                 GP_0_17_FN, FN_IP1_6_4,
2765                 GP_0_16_FN, FN_IP1_3_2,
2766                 GP_0_15_FN, FN_IP1_1_0,
2767                 GP_0_14_FN, FN_IP0_27_26,
2768                 GP_0_13_FN, FN_IP0_25,
2769                 GP_0_12_FN, FN_IP0_24_23,
2770                 GP_0_11_FN, FN_IP0_22_19,
2771                 GP_0_10_FN, FN_IP0_18_16,
2772                 GP_0_9_FN, FN_IP0_15_14,
2773                 GP_0_8_FN, FN_IP0_13_12,
2774                 GP_0_7_FN, FN_IP0_11_10,
2775                 GP_0_6_FN, FN_IP0_9_8,
2776                 GP_0_5_FN, FN_A19,
2777                 GP_0_4_FN, FN_A18,
2778                 GP_0_3_FN, FN_A17,
2779                 GP_0_2_FN, FN_IP0_7_6,
2780                 GP_0_1_FN, FN_AVS2,
2781                 GP_0_0_FN, FN_AVS1 }
2782         },
2783         { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
2784                 GP_1_31_FN, FN_IP5_23_21,
2785                 GP_1_30_FN, FN_IP5_20_17,
2786                 GP_1_29_FN, FN_IP5_16_15,
2787                 GP_1_28_FN, FN_IP5_14_13,
2788                 GP_1_27_FN, FN_IP5_12_11,
2789                 GP_1_26_FN, FN_IP5_10_9,
2790                 GP_1_25_FN, FN_IP5_8,
2791                 GP_1_24_FN, FN_IP5_7,
2792                 GP_1_23_FN, FN_IP5_6,
2793                 GP_1_22_FN, FN_IP5_5,
2794                 GP_1_21_FN, FN_IP5_4,
2795                 GP_1_20_FN, FN_IP5_3,
2796                 GP_1_19_FN, FN_IP5_2_0,
2797                 GP_1_18_FN, FN_IP4_31_29,
2798                 GP_1_17_FN, FN_IP4_28,
2799                 GP_1_16_FN, FN_IP4_27,
2800                 GP_1_15_FN, FN_IP4_26,
2801                 GP_1_14_FN, FN_IP4_25,
2802                 GP_1_13_FN, FN_IP4_24,
2803                 GP_1_12_FN, FN_IP4_23,
2804                 GP_1_11_FN, FN_IP4_22_20,
2805                 GP_1_10_FN, FN_IP4_19_17,
2806                 GP_1_9_FN, FN_IP4_16,
2807                 GP_1_8_FN, FN_IP4_15,
2808                 GP_1_7_FN, FN_IP4_14,
2809                 GP_1_6_FN, FN_IP4_13,
2810                 GP_1_5_FN, FN_IP4_12,
2811                 GP_1_4_FN, FN_IP4_11,
2812                 GP_1_3_FN, FN_IP4_10_8,
2813                 GP_1_2_FN, FN_IP4_7_5,
2814                 GP_1_1_FN, FN_IP4_4_2,
2815                 GP_1_0_FN, FN_IP4_1_0 }
2816         },
2817         { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
2818                 GP_2_31_FN, FN_IP10_28_26,
2819                 GP_2_30_FN, FN_IP10_25_24,
2820                 GP_2_29_FN, FN_IP10_23_21,
2821                 GP_2_28_FN, FN_IP10_20_18,
2822                 GP_2_27_FN, FN_IP10_17_15,
2823                 GP_2_26_FN, FN_IP10_14_12,
2824                 GP_2_25_FN, FN_IP10_11_9,
2825                 GP_2_24_FN, FN_IP10_8_6,
2826                 GP_2_23_FN, FN_IP10_5_3,
2827                 GP_2_22_FN, FN_IP10_2_0,
2828                 GP_2_21_FN, FN_IP9_29_28,
2829                 GP_2_20_FN, FN_IP9_27_26,
2830                 GP_2_19_FN, FN_IP9_25_24,
2831                 GP_2_18_FN, FN_IP9_23_22,
2832                 GP_2_17_FN, FN_IP9_21_19,
2833                 GP_2_16_FN, FN_IP9_18_16,
2834                 GP_2_15_FN, FN_IP9_15_14,
2835                 GP_2_14_FN, FN_IP9_13_12,
2836                 GP_2_13_FN, FN_IP9_11_10,
2837                 GP_2_12_FN, FN_IP9_9_8,
2838                 GP_2_11_FN, FN_IP9_7,
2839                 GP_2_10_FN, FN_IP9_6,
2840                 GP_2_9_FN, FN_IP9_5,
2841                 GP_2_8_FN, FN_IP9_4,
2842                 GP_2_7_FN, FN_IP9_3_2,
2843                 GP_2_6_FN, FN_IP9_1_0,
2844                 GP_2_5_FN, FN_IP8_30_28,
2845                 GP_2_4_FN, FN_IP8_27_25,
2846                 GP_2_3_FN, FN_IP8_24_23,
2847                 GP_2_2_FN, FN_IP8_22_21,
2848                 GP_2_1_FN, FN_IP8_20,
2849                 GP_2_0_FN, FN_IP5_27_24 }
2850         },
2851         { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
2852                 GP_3_31_FN, FN_IP6_3_2,
2853                 GP_3_30_FN, FN_IP6_1_0,
2854                 GP_3_29_FN, FN_IP5_30_29,
2855                 GP_3_28_FN, FN_IP5_28,
2856                 GP_3_27_FN, FN_IP1_24_23,
2857                 GP_3_26_FN, FN_IP1_22_21,
2858                 GP_3_25_FN, FN_IP1_20_19,
2859                 GP_3_24_FN, FN_IP7_26_25,
2860                 GP_3_23_FN, FN_IP7_24_23,
2861                 GP_3_22_FN, FN_IP7_22_21,
2862                 GP_3_21_FN, FN_IP7_20_19,
2863                 GP_3_20_FN, FN_IP7_30_29,
2864                 GP_3_19_FN, FN_IP7_28_27,
2865                 GP_3_18_FN, FN_IP7_18_17,
2866                 GP_3_17_FN, FN_IP7_16_15,
2867                 GP_3_16_FN, FN_IP12_17_15,
2868                 GP_3_15_FN, FN_IP12_14_12,
2869                 GP_3_14_FN, FN_IP12_11_9,
2870                 GP_3_13_FN, FN_IP12_8_6,
2871                 GP_3_12_FN, FN_IP12_5_3,
2872                 GP_3_11_FN, FN_IP12_2_0,
2873                 GP_3_10_FN, FN_IP11_29_27,
2874                 GP_3_9_FN, FN_IP11_26_24,
2875                 GP_3_8_FN, FN_IP11_23_21,
2876                 GP_3_7_FN, FN_IP11_20_18,
2877                 GP_3_6_FN, FN_IP11_17_15,
2878                 GP_3_5_FN, FN_IP11_14_12,
2879                 GP_3_4_FN, FN_IP11_11_9,
2880                 GP_3_3_FN, FN_IP11_8_6,
2881                 GP_3_2_FN, FN_IP11_5_3,
2882                 GP_3_1_FN, FN_IP11_2_0,
2883                 GP_3_0_FN, FN_IP10_31_29 }
2884         },
2885         { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
2886                 GP_4_31_FN, FN_IP8_19,
2887                 GP_4_30_FN, FN_IP8_18,
2888                 GP_4_29_FN, FN_IP8_17_16,
2889                 GP_4_28_FN, FN_IP0_2_0,
2890                 GP_4_27_FN, FN_USB_PENC1,
2891                 GP_4_26_FN, FN_USB_PENC0,
2892                 GP_4_25_FN, FN_IP8_15_12,
2893                 GP_4_24_FN, FN_IP8_11_8,
2894                 GP_4_23_FN, FN_IP8_7_4,
2895                 GP_4_22_FN, FN_IP8_3_0,
2896                 GP_4_21_FN, FN_IP2_3_0,
2897                 GP_4_20_FN, FN_IP1_28_25,
2898                 GP_4_19_FN, FN_IP2_15_12,
2899                 GP_4_18_FN, FN_IP2_11_8,
2900                 GP_4_17_FN, FN_IP2_7_4,
2901                 GP_4_16_FN, FN_IP7_14_13,
2902                 GP_4_15_FN, FN_IP7_12_10,
2903                 GP_4_14_FN, FN_IP7_9_7,
2904                 GP_4_13_FN, FN_IP7_6_4,
2905                 GP_4_12_FN, FN_IP7_3_2,
2906                 GP_4_11_FN, FN_IP7_1_0,
2907                 GP_4_10_FN, FN_IP6_30_29,
2908                 GP_4_9_FN, FN_IP6_26_25,
2909                 GP_4_8_FN, FN_IP6_24_23,
2910                 GP_4_7_FN, FN_IP6_22_20,
2911                 GP_4_6_FN, FN_IP6_19_18,
2912                 GP_4_5_FN, FN_IP6_17_15,
2913                 GP_4_4_FN, FN_IP6_14_12,
2914                 GP_4_3_FN, FN_IP6_11_9,
2915                 GP_4_2_FN, FN_IP6_8,
2916                 GP_4_1_FN, FN_IP6_7_6,
2917                 GP_4_0_FN, FN_IP6_5_4 }
2918         },
2919         { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
2920                 GP_5_31_FN, FN_IP3_5,
2921                 GP_5_30_FN, FN_IP3_4,
2922                 GP_5_29_FN, FN_IP3_3,
2923                 GP_5_28_FN, FN_IP2_27,
2924                 GP_5_27_FN, FN_IP2_26,
2925                 GP_5_26_FN, FN_IP2_25,
2926                 GP_5_25_FN, FN_IP2_24,
2927                 GP_5_24_FN, FN_IP2_23,
2928                 GP_5_23_FN, FN_IP2_22,
2929                 GP_5_22_FN, FN_IP3_28,
2930                 GP_5_21_FN, FN_IP3_27,
2931                 GP_5_20_FN, FN_IP3_23,
2932                 GP_5_19_FN, FN_EX_WAIT0,
2933                 GP_5_18_FN, FN_WE1,
2934                 GP_5_17_FN, FN_WE0,
2935                 GP_5_16_FN, FN_RD,
2936                 GP_5_15_FN, FN_A16,
2937                 GP_5_14_FN, FN_A15,
2938                 GP_5_13_FN, FN_A14,
2939                 GP_5_12_FN, FN_A13,
2940                 GP_5_11_FN, FN_A12,
2941                 GP_5_10_FN, FN_A11,
2942                 GP_5_9_FN, FN_A10,
2943                 GP_5_8_FN, FN_A9,
2944                 GP_5_7_FN, FN_A8,
2945                 GP_5_6_FN, FN_A7,
2946                 GP_5_5_FN, FN_A6,
2947                 GP_5_4_FN, FN_A5,
2948                 GP_5_3_FN, FN_A4,
2949                 GP_5_2_FN, FN_A3,
2950                 GP_5_1_FN, FN_A2,
2951                 GP_5_0_FN, FN_A1 }
2952         },
2953         { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
2954                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2955                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2956                 0, 0, 0, 0, 0, 0, 0, 0,
2957                 0, 0,
2958                 0, 0,
2959                 0, 0,
2960                 GP_6_8_FN, FN_IP3_20,
2961                 GP_6_7_FN, FN_IP3_19,
2962                 GP_6_6_FN, FN_IP3_18,
2963                 GP_6_5_FN, FN_IP3_17,
2964                 GP_6_4_FN, FN_IP3_16,
2965                 GP_6_3_FN, FN_IP3_15,
2966                 GP_6_2_FN, FN_IP3_8,
2967                 GP_6_1_FN, FN_IP3_7,
2968                 GP_6_0_FN, FN_IP3_6 }
2969         },
2970
2971         { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2972                              1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
2973                 /* IP0_31 [1] */
2974                 0, 0,
2975                 /* IP0_30_28 [3] */
2976                 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
2977                 FN_HRTS1, FN_RX4_C, 0, 0,
2978                 /* IP0_27_26 [2] */
2979                 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
2980                 /* IP0_25 [1] */
2981                 FN_CS0, FN_HSPI_CS2_B,
2982                 /* IP0_24_23 [2] */
2983                 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
2984                 /* IP0_22_19 [4] */
2985                 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
2986                 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
2987                 FN_CTS0_B, 0, 0, 0,
2988                 0, 0, 0, 0,
2989                 /* IP0_18_16 [3] */
2990                 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
2991                 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
2992                 /* IP0_15_14 [2] */
2993                 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
2994                 /* IP0_13_12 [2] */
2995                 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
2996                 /* IP0_11_10 [2] */
2997                 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
2998                 /* IP0_9_8 [2] */
2999                 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
3000                 /* IP0_7_6 [2] */
3001                 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
3002                 /* IP0_5_3 [3] */
3003                 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
3004                 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
3005                 /* IP0_2_0 [3] */
3006                 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
3007                 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
3008         },
3009         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3010                              3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
3011                 /* IP1_31_29 [3] */
3012                 0, 0, 0, 0, 0, 0, 0, 0,
3013                 /* IP1_28_25 [4] */
3014                 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
3015                 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
3016                 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
3017                 0, 0, 0, 0,
3018                 /* IP1_24_23 [2] */
3019                 FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
3020                 /* IP1_22_21 [2] */
3021                 FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
3022                 /* IP1_20_19 [2] */
3023                 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
3024                 /* IP1_18_15 [4] */
3025                 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
3026                 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
3027                 FN_RX0_B, FN_SSI_WS9, 0, 0,
3028                 0, 0, 0, 0,
3029                 /* IP1_14_11 [4] */
3030                 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
3031                 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
3032                 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
3033                 0, 0, 0, 0,
3034                 /* IP1_10_7 [4] */
3035                 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
3036                 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
3037                 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
3038                 0, 0, 0, 0,
3039                 /* IP1_6_4 [3] */
3040                 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
3041                 FN_ATACS00, 0, 0, 0,
3042                 /* IP1_3_2 [2] */
3043                 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
3044                 /* IP1_1_0 [2] */
3045                 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
3046         },
3047         { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3048                              1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
3049                 /* IP2_31 [1] */
3050                 0, 0,
3051                 /* IP2_30_28 [3] */
3052                 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
3053                 FN_AUDATA2, 0, 0, 0,
3054                 /* IP2_27 [1] */
3055                 FN_DU0_DR7, FN_LCDOUT7,
3056                 /* IP2_26 [1] */
3057                 FN_DU0_DR6, FN_LCDOUT6,
3058                 /* IP2_25 [1] */
3059                 FN_DU0_DR5, FN_LCDOUT5,
3060                 /* IP2_24 [1] */
3061                 FN_DU0_DR4, FN_LCDOUT4,
3062                 /* IP2_23 [1] */
3063                 FN_DU0_DR3, FN_LCDOUT3,
3064                 /* IP2_22 [1] */
3065                 FN_DU0_DR2, FN_LCDOUT2,
3066                 /* IP2_21_19 [3] */
3067                 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
3068                 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
3069                 /* IP2_18_16 [3] */
3070                 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
3071                 FN_AUDATA0, FN_TX5_C, 0, 0,
3072                 /* IP2_15_12 [4] */
3073                 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
3074                 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
3075                 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
3076                 0, 0, 0, 0,
3077                 /* IP2_11_8 [4] */
3078                 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
3079                 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
3080                 FN_CC5_OSCOUT, 0, 0, 0,
3081                 0, 0, 0, 0,
3082                 /* IP2_7_4 [4] */
3083                 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
3084                 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
3085                 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
3086                 0, 0, 0, 0,
3087                 /* IP2_3_0 [4] */
3088                 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
3089                 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
3090                 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
3091                 0, 0, 0, 0 }
3092         },
3093         { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3094                              3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
3095                              1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
3096             /* IP3_31_29 [3] */
3097             FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
3098             FN_SCL2_C, FN_REMOCON, 0, 0,
3099             /* IP3_28 [1] */
3100             FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
3101             /* IP3_27 [1] */
3102             FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
3103             /* IP3_26_24 [3] */
3104             FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
3105             FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
3106             /* IP3_23 [1] */
3107             FN_DU0_DOTCLKOUT0, FN_QCLK,
3108             /* IP3_22_21 [2] */
3109             FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
3110             /* IP3_20 [1] */
3111             FN_DU0_DB7, FN_LCDOUT23,
3112             /* IP3_19 [1] */
3113             FN_DU0_DB6, FN_LCDOUT22,
3114             /* IP3_18 [1] */
3115             FN_DU0_DB5, FN_LCDOUT21,
3116             /* IP3_17 [1] */
3117             FN_DU0_DB4, FN_LCDOUT20,
3118             /* IP3_16 [1] */
3119             FN_DU0_DB3, FN_LCDOUT19,
3120             /* IP3_15 [1] */
3121             FN_DU0_DB2, FN_LCDOUT18,
3122             /* IP3_14_12 [3] */
3123             FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
3124             FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
3125             /* IP3_11_9 [3] */
3126             FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
3127             FN_TCLK1, FN_AUDATA4, 0, 0,
3128             /* IP3_8 [1] */
3129             FN_DU0_DG7, FN_LCDOUT15,
3130             /* IP3_7 [1] */
3131             FN_DU0_DG6, FN_LCDOUT14,
3132             /* IP3_6 [1] */
3133             FN_DU0_DG5, FN_LCDOUT13,
3134             /* IP3_5 [1] */
3135             FN_DU0_DG4, FN_LCDOUT12,
3136             /* IP3_4 [1] */
3137             FN_DU0_DG3, FN_LCDOUT11,
3138             /* IP3_3 [1] */
3139             FN_DU0_DG2, FN_LCDOUT10,
3140             /* IP3_2_0 [3] */
3141             FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
3142             FN_AUDATA3, 0, 0, 0 }
3143         },
3144         { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3145                              3, 1, 1, 1, 1, 1, 1, 3, 3,
3146                              1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
3147             /* IP4_31_29 [3] */
3148             FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
3149             FN_TX5, FN_SCK0_D, 0, 0,
3150             /* IP4_28 [1] */
3151             FN_DU1_DG7, FN_VI2_R3,
3152             /* IP4_27 [1] */
3153             FN_DU1_DG6, FN_VI2_R2,
3154             /* IP4_26 [1] */
3155             FN_DU1_DG5, FN_VI2_R1,
3156             /* IP4_25 [1] */
3157             FN_DU1_DG4, FN_VI2_R0,
3158             /* IP4_24 [1] */
3159             FN_DU1_DG3, FN_VI2_G7,
3160             /* IP4_23 [1] */
3161             FN_DU1_DG2, FN_VI2_G6,
3162             /* IP4_22_20 [3] */
3163             FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
3164             FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
3165             /* IP4_19_17 [3] */
3166             FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
3167             FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
3168             /* IP4_16 [1] */
3169             FN_DU1_DR7, FN_VI2_G5,
3170             /* IP4_15 [1] */
3171             FN_DU1_DR6, FN_VI2_G4,
3172             /* IP4_14 [1] */
3173             FN_DU1_DR5, FN_VI2_G3,
3174             /* IP4_13 [1] */
3175             FN_DU1_DR4, FN_VI2_G2,
3176             /* IP4_12 [1] */
3177             FN_DU1_DR3, FN_VI2_G1,
3178             /* IP4_11 [1] */
3179             FN_DU1_DR2, FN_VI2_G0,
3180             /* IP4_10_8 [3] */
3181             FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
3182             FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
3183             /* IP4_7_5 [3] */
3184             FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
3185             FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
3186             /* IP4_4_2 [3] */
3187             FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
3188             FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
3189             /* IP4_1_0 [2] */
3190             FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
3191         },
3192         { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3193                              1, 2, 1, 4, 3, 4, 2, 2,
3194                              2, 2, 1, 1, 1, 1, 1, 1, 3) {
3195             /* IP5_31 [1] */
3196             0, 0,
3197             /* IP5_30_29 [2] */
3198             FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
3199             /* IP5_28 [1] */
3200             FN_AUDIO_CLKA, FN_CAN_TXCLK,
3201             /* IP5_27_24 [4] */
3202             FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
3203             FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
3204             FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
3205             0, 0, 0, 0,
3206             /* IP5_23_21 [3] */
3207             FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
3208             FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
3209             /* IP5_20_17 [4] */
3210             FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
3211             FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
3212             FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
3213             0, 0, 0, 0,
3214             /* IP5_16_15 [2] */
3215             FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
3216             /* IP5_14_13 [2] */
3217             FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
3218             /* IP5_12_11 [2] */
3219             FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
3220             /* IP5_10_9 [2] */
3221             FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
3222             /* IP5_8 [1] */
3223             FN_DU1_DB7, FN_SDA2_D,
3224             /* IP5_7 [1] */
3225             FN_DU1_DB6, FN_SCL2_D,
3226             /* IP5_6 [1] */
3227             FN_DU1_DB5, FN_VI2_R7,
3228             /* IP5_5 [1] */
3229             FN_DU1_DB4, FN_VI2_R6,
3230             /* IP5_4 [1] */
3231             FN_DU1_DB3, FN_VI2_R5,
3232             /* IP5_3 [1] */
3233             FN_DU1_DB2, FN_VI2_R4,
3234             /* IP5_2_0 [3] */
3235             FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
3236             FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
3237         },
3238         { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3239                              1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
3240             /* IP6_31 [1] */
3241             0, 0,
3242             /* IP6_30_29 [2] */
3243             FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
3244             /* IP_28_27 [2] */
3245             0, 0, 0, 0,
3246             /* IP6_26_25 [2] */
3247             FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
3248             /* IP6_24_23 [2] */
3249             FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
3250             /* IP6_22_20 [3] */
3251             FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
3252             FN_TCLK0_D, 0, 0, 0,
3253             /* IP6_19_18 [2] */
3254             FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
3255             /* IP6_17_15 [3] */
3256             FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
3257             FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
3258             /* IP6_14_12 [3] */
3259             FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
3260             FN_SSI_WS9_C, 0, 0, 0,
3261             /* IP6_11_9 [3] */
3262             FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
3263             FN_SSI_SCK9_C, 0, 0, 0,
3264             /* IP6_8 [1] */
3265             FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
3266             /* IP6_7_6 [2] */
3267             FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
3268             /* IP6_5_4 [2] */
3269             FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
3270             /* IP6_3_2 [2] */
3271             FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
3272             /* IP6_1_0 [2] */
3273             FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
3274         },
3275         { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3276                              1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
3277             /* IP7_31 [1] */
3278             0, 0,
3279             /* IP7_30_29 [2] */
3280             FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
3281             /* IP7_28_27 [2] */
3282             FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
3283             /* IP7_26_25 [2] */
3284             FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
3285             /* IP7_24_23 [2] */
3286             FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
3287             /* IP7_22_21 [2] */
3288             FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
3289             /* IP7_20_19 [2] */
3290             FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
3291             /* IP7_18_17 [2] */
3292             FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
3293             /* IP7_16_15 [2] */
3294             FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
3295             /* IP7_14_13 [2] */
3296             FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
3297             /* IP7_12_10 [3] */
3298             FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
3299             FN_HSPI_TX1_C, 0, 0, 0,
3300             /* IP7_9_7 [3] */
3301             FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
3302             FN_HSPI_CS1_C, 0, 0, 0,
3303             /* IP7_6_4 [3] */
3304             FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
3305             FN_HSPI_CLK1_C, 0, 0, 0,
3306             /* IP7_3_2 [2] */
3307             FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
3308             /* IP7_1_0 [2] */
3309             FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
3310         },
3311         { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3312                              1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
3313             /* IP8_31 [1] */
3314             0, 0,
3315             /* IP8_30_28 [3] */
3316             FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
3317             FN_PWMFSW0_C, 0, 0, 0,
3318             /* IP8_27_25 [3] */
3319             FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
3320             FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
3321             /* IP8_24_23 [2] */
3322             FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
3323             /* IP8_22_21 [2] */
3324             FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
3325             /* IP8_20 [1] */
3326             FN_VI0_CLK, FN_MMC1_CLK,
3327             /* IP8_19 [1] */
3328             FN_FMIN, FN_RDS_DATA,
3329             /* IP8_18 [1] */
3330             FN_BPFCLK, FN_PCMWE,
3331             /* IP8_17_16 [2] */
3332             FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
3333             /* IP8_15_12 [4] */
3334             FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
3335             FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
3336             FN_CC5_STATE39, 0, 0, 0,
3337             0, 0, 0, 0,
3338             /* IP8_11_8 [4] */
3339             FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
3340             FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
3341             FN_CC5_STATE38, 0, 0, 0,
3342             0, 0, 0, 0,
3343             /* IP8_7_4 [4] */
3344             FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
3345             FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
3346             FN_CC5_STATE37, 0, 0, 0,
3347             0, 0, 0, 0,
3348             /* IP8_3_0 [4] */
3349             FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
3350             FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
3351             FN_CC5_STATE36, 0, 0, 0,
3352             0, 0, 0, 0 }
3353         },
3354         { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
3355                              2, 2, 2, 2, 2, 3, 3, 2, 2,
3356                              2, 2, 1, 1, 1, 1, 2, 2) {
3357             /* IP9_31_30 [2] */
3358             0, 0, 0, 0,
3359             /* IP9_29_28 [2] */
3360             FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
3361             /* IP9_27_26 [2] */
3362             FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
3363             /* IP9_25_24 [2] */
3364             FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
3365             /* IP9_23_22 [2] */
3366             FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
3367             /* IP9_21_19 [3] */
3368             FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
3369             FN_TS_SDAT0, 0, 0, 0,
3370             /* IP9_18_16 [3] */
3371             FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
3372             FN_TS_SPSYNC0, 0, 0, 0,
3373             /* IP9_15_14 [2] */
3374             FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
3375             /* IP9_13_12 [2] */
3376             FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
3377             /* IP9_11_10 [2] */
3378             FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
3379             /* IP9_9_8 [2] */
3380             FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
3381             /* IP9_7 [1] */
3382             FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
3383             /* IP9_6 [1] */
3384             FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
3385             /* IP9_5 [1] */
3386             FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
3387             /* IP9_4 [1] */
3388             FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
3389             /* IP9_3_2 [2] */
3390             FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
3391             /* IP9_1_0 [2] */
3392             FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
3393         },
3394         { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
3395                              3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
3396             /* IP10_31_29 [3] */
3397             FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
3398             FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
3399             /* IP10_28_26 [3] */
3400             FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
3401             FN_PWMFSW0_E, 0, 0, 0,
3402             /* IP10_25_24 [2] */
3403             FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
3404             /* IP10_23_21 [3] */
3405             FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
3406             FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
3407             /* IP10_20_18 [3] */
3408             FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
3409             FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
3410             /* IP10_17_15 [3] */
3411             FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
3412             FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
3413             /* IP10_14_12 [3] */
3414             FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
3415             FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
3416             /* IP10_11_9 [3] */
3417             FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
3418             FN_ARM_TRACEDATA_13, 0, 0, 0,
3419             /* IP10_8_6 [3] */
3420             FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
3421             FN_ARM_TRACEDATA_12, 0, 0, 0,
3422             /* IP10_5_3 [3] */
3423             FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
3424             FN_DACK0_C, FN_DRACK0_C, 0, 0,
3425             /* IP10_2_0 [3] */
3426             FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
3427             FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
3428         },
3429         { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
3430                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3431             /* IP11_31_30 [2] */
3432             0, 0, 0, 0,
3433             /* IP11_29_27 [3] */
3434             FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
3435             FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
3436             /* IP11_26_24 [3] */
3437             FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
3438             FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
3439             /* IP11_23_21 [3] */
3440             FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
3441             FN_HSPI_RX1_D, 0, 0, 0,
3442             /* IP11_20_18 [3] */
3443             FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
3444             FN_HSPI_TX1_D, 0, 0, 0,
3445             /* IP11_17_15 [3] */
3446             FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
3447             FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
3448             /* IP11_14_12 [3] */
3449             FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
3450             FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
3451             /* IP11_11_9 [3] */
3452             FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
3453             FN_ADICHS0_B, 0, 0, 0,
3454             /* IP11_8_6 [3] */
3455             FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
3456             FN_ADIDATA_B, 0, 0, 0,
3457             /* IP11_5_3 [3] */
3458             FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
3459             FN_ADICS_B_SAMP_B, 0, 0, 0,
3460             /* IP11_2_0 [3] */
3461             FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
3462             FN_ADICLK_B, 0, 0, 0 }
3463         },
3464         { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
3465                              4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
3466             /* IP12_31_28 [4] */
3467             0, 0, 0, 0, 0, 0, 0, 0,
3468             0, 0, 0, 0, 0, 0, 0, 0,
3469             /* IP12_27_24 [4] */
3470             0, 0, 0, 0, 0, 0, 0, 0,
3471             0, 0, 0, 0, 0, 0, 0, 0,
3472             /* IP12_23_20 [4] */
3473             0, 0, 0, 0, 0, 0, 0, 0,
3474             0, 0, 0, 0, 0, 0, 0, 0,
3475             /* IP12_19_18 [2] */
3476             0, 0, 0, 0,
3477             /* IP12_17_15 [3] */
3478             FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
3479             FN_SCK4_B, 0, 0, 0,
3480             /* IP12_14_12 [3] */
3481             FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
3482             FN_RX4_B, FN_SIM_CLK_B, 0, 0,
3483             /* IP12_11_9 [3] */
3484             FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
3485             FN_TX4_B, FN_SIM_D_B, 0, 0,
3486             /* IP12_8_6 [3] */
3487             FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
3488             FN_SIM_RST_B, FN_HRX0_B, 0, 0,
3489             /* IP12_5_3 [3] */
3490             FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
3491             FN_SCL1_C, FN_HTX0_B, 0, 0,
3492             /* IP12_2_0 [3] */
3493             FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
3494             FN_SCK2, FN_HSCK0_B, 0, 0 }
3495         },
3496         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
3497                              2, 2, 3, 3, 2, 2, 2, 2, 2,
3498                              1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
3499             /* SEL_SCIF5 [2] */
3500             FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3501             /* SEL_SCIF4 [2] */
3502             FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3503             /* SEL_SCIF3 [3] */
3504             FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
3505             FN_SEL_SCIF3_4, 0, 0, 0,
3506             /* SEL_SCIF2 [3] */
3507             FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
3508             FN_SEL_SCIF2_4, 0, 0, 0,
3509             /* SEL_SCIF1 [2] */
3510             FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
3511             /* SEL_SCIF0 [2] */
3512             FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3513             /* SEL_SSI9 [2] */
3514             FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
3515             /* SEL_SSI8 [2] */
3516             FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
3517             /* SEL_SSI7 [2] */
3518             FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3519             /* SEL_VI0 [1] */
3520             FN_SEL_VI0_0, FN_SEL_VI0_1,
3521             /* SEL_SD2 [1] */
3522             FN_SEL_SD2_0, FN_SEL_SD2_1,
3523             /* SEL_INT3 [1] */
3524             FN_SEL_INT3_0, FN_SEL_INT3_1,
3525             /* SEL_INT2 [1] */
3526             FN_SEL_INT2_0, FN_SEL_INT2_1,
3527             /* SEL_INT1 [1] */
3528             FN_SEL_INT1_0, FN_SEL_INT1_1,
3529             /* SEL_INT0 [1] */
3530             FN_SEL_INT0_0, FN_SEL_INT0_1,
3531             /* SEL_IE [1] */
3532             FN_SEL_IE_0, FN_SEL_IE_1,
3533             /* SEL_EXBUS2 [2] */
3534             FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
3535             /* SEL_EXBUS1 [1] */
3536             FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
3537             /* SEL_EXBUS0 [2] */
3538             FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
3539         },
3540         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
3541                              2, 2, 2, 2, 1, 1, 1, 3, 1,
3542                              2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
3543             /* SEL_TMU1 [2] */
3544             FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
3545             /* SEL_TMU0 [2] */
3546             FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
3547             /* SEL_SCIF [2] */
3548             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
3549             /* SEL_CANCLK [2] */
3550             FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
3551             /* SEL_CAN0 [1] */
3552             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
3553             /* SEL_HSCIF1 [1] */
3554             FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3555             /* SEL_HSCIF0 [1] */
3556             FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
3557             /* SEL_PWMFSW [3] */
3558             FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
3559             FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
3560             /* SEL_ADI [1] */
3561             FN_SEL_ADI_0, FN_SEL_ADI_1,
3562             /* [2] */
3563             0, 0, 0, 0,
3564             /* [2] */
3565             0, 0, 0, 0,
3566             /* [2] */
3567             0, 0, 0, 0,
3568             /* SEL_GPS [2] */
3569             FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
3570             /* SEL_SIM [1] */
3571             FN_SEL_SIM_0, FN_SEL_SIM_1,
3572             /* SEL_HSPI2 [1] */
3573             FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
3574             /* SEL_HSPI1 [2] */
3575             FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
3576             /* SEL_I2C3 [1] */
3577             FN_SEL_I2C3_0, FN_SEL_I2C3_1,
3578             /* SEL_I2C2 [2] */
3579             FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3580             /* SEL_I2C1 [2] */
3581             FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
3582         },
3583         { },
3584 };
3585
3586 const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3587         .name = "r8a7779_pfc",
3588
3589         .unlock_reg = 0xfffc0000, /* PMMR */
3590
3591         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3592
3593         .pins = pinmux_pins,
3594         .nr_pins = ARRAY_SIZE(pinmux_pins),
3595         .groups = pinmux_groups,
3596         .nr_groups = ARRAY_SIZE(pinmux_groups),
3597         .functions = pinmux_functions,
3598         .nr_functions = ARRAY_SIZE(pinmux_functions),
3599
3600         .cfg_regs = pinmux_config_regs,
3601
3602         .gpio_data = pinmux_data,
3603         .gpio_data_size = ARRAY_SIZE(pinmux_data),
3604 };