2 * Copyright © 2006-2011 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
25 #include "framebuffer.h"
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_display.h"
32 struct psb_intel_clock_t {
44 struct psb_intel_range_t {
48 struct psb_intel_p2_t {
53 struct psb_intel_limit_t {
54 struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1;
55 struct psb_intel_p2_t p2;
58 #define INTEL_LIMIT_I9XX_SDVO_DAC 0
59 #define INTEL_LIMIT_I9XX_LVDS 1
61 static const struct psb_intel_limit_t psb_intel_limits[] = {
62 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
63 .dot = {.min = 20000, .max = 400000},
64 .vco = {.min = 1400000, .max = 2800000},
65 .n = {.min = 1, .max = 6},
66 .m = {.min = 70, .max = 120},
67 .m1 = {.min = 8, .max = 18},
68 .m2 = {.min = 3, .max = 7},
69 .p = {.min = 5, .max = 80},
70 .p1 = {.min = 1, .max = 8},
71 .p2 = {.dot_limit = 200000,
72 .p2_slow = 10, .p2_fast = 5},
74 { /* INTEL_LIMIT_I9XX_LVDS */
75 .dot = {.min = 20000, .max = 400000},
76 .vco = {.min = 1400000, .max = 2800000},
77 .n = {.min = 1, .max = 6},
78 .m = {.min = 70, .max = 120},
79 .m1 = {.min = 8, .max = 18},
80 .m2 = {.min = 3, .max = 7},
81 .p = {.min = 7, .max = 98},
82 .p1 = {.min = 1, .max = 8},
83 /* The single-channel range is 25-112Mhz, and dual-channel
84 * is 80-224Mhz. Prefer single channel as much as possible.
86 .p2 = {.dot_limit = 112000,
87 .p2_slow = 14, .p2_fast = 7},
91 static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc)
93 const struct psb_intel_limit_t *limit;
95 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
96 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
98 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
102 static void psb_intel_clock(int refclk, struct psb_intel_clock_t *clock)
104 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
105 clock->p = clock->p1 * clock->p2;
106 clock->vco = refclk * clock->m / (clock->n + 2);
107 clock->dot = clock->vco / clock->p;
111 * Returns whether any output on the specified pipe is of the specified type
113 bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type)
115 struct drm_device *dev = crtc->dev;
116 struct drm_mode_config *mode_config = &dev->mode_config;
117 struct drm_connector *l_entry;
119 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
120 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
121 struct psb_intel_encoder *psb_intel_encoder =
122 psb_intel_attached_encoder(l_entry);
123 if (psb_intel_encoder->type == type)
130 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
132 * Returns whether the given set of divisors are valid for a given refclk with
133 * the given connectors.
136 static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc,
137 struct psb_intel_clock_t *clock)
139 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
141 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
142 INTELPllInvalid("p1 out of range\n");
143 if (clock->p < limit->p.min || limit->p.max < clock->p)
144 INTELPllInvalid("p out of range\n");
145 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
146 INTELPllInvalid("m2 out of range\n");
147 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
148 INTELPllInvalid("m1 out of range\n");
149 if (clock->m1 <= clock->m2)
150 INTELPllInvalid("m1 <= m2\n");
151 if (clock->m < limit->m.min || limit->m.max < clock->m)
152 INTELPllInvalid("m out of range\n");
153 if (clock->n < limit->n.min || limit->n.max < clock->n)
154 INTELPllInvalid("n out of range\n");
155 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
156 INTELPllInvalid("vco out of range\n");
157 /* XXX: We may need to be checking "Dot clock"
158 * depending on the multiplier, connector, etc.,
159 * rather than just a single range.
161 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
162 INTELPllInvalid("dot out of range\n");
168 * Returns a set of divisors for the desired target clock with the given
169 * refclk, or FALSE. The returned values represent the clock equation:
170 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
172 static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target,
174 struct psb_intel_clock_t *best_clock)
176 struct drm_device *dev = crtc->dev;
177 struct psb_intel_clock_t clock;
178 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
181 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
182 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
184 * For LVDS, if the panel is on, just rely on its current
185 * settings for dual-channel. We haven't figured out how to
186 * reliably set up different single/dual channel state, if we
189 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
191 clock.p2 = limit->p2.p2_fast;
193 clock.p2 = limit->p2.p2_slow;
195 if (target < limit->p2.dot_limit)
196 clock.p2 = limit->p2.p2_slow;
198 clock.p2 = limit->p2.p2_fast;
201 memset(best_clock, 0, sizeof(*best_clock));
203 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
205 for (clock.m2 = limit->m2.min;
206 clock.m2 < clock.m1 && clock.m2 <= limit->m2.max;
208 for (clock.n = limit->n.min;
209 clock.n <= limit->n.max; clock.n++) {
210 for (clock.p1 = limit->p1.min;
211 clock.p1 <= limit->p1.max;
215 psb_intel_clock(refclk, &clock);
217 if (!psb_intel_PLL_is_valid
221 this_err = abs(clock.dot - target);
222 if (this_err < err) {
231 return err != target;
234 void psb_intel_wait_for_vblank(struct drm_device *dev)
236 /* Wait for 20ms, i.e. one cycle at 50hz. */
240 static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
241 int x, int y, struct drm_framebuffer *old_fb)
243 struct drm_device *dev = crtc->dev;
244 struct drm_psb_private *dev_priv = dev->dev_private;
245 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
246 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
247 int pipe = psb_intel_crtc->pipe;
248 const struct psb_offset *map = &dev_priv->regmap[pipe];
249 unsigned long start, offset;
253 if (!gma_power_begin(dev, true))
258 dev_dbg(dev->dev, "No FB bound\n");
259 goto psb_intel_pipe_cleaner;
262 /* We are displaying this buffer, make sure it is actually loaded
264 ret = psb_gtt_pin(psbfb->gtt);
266 goto psb_intel_pipe_set_base_exit;
267 start = psbfb->gtt->offset;
269 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
271 REG_WRITE(map->stride, crtc->fb->pitches[0]);
273 dspcntr = REG_READ(map->cntr);
274 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
276 switch (crtc->fb->bits_per_pixel) {
278 dspcntr |= DISPPLANE_8BPP;
281 if (crtc->fb->depth == 15)
282 dspcntr |= DISPPLANE_15_16BPP;
284 dspcntr |= DISPPLANE_16BPP;
288 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
291 dev_err(dev->dev, "Unknown color depth\n");
293 psb_gtt_unpin(psbfb->gtt);
294 goto psb_intel_pipe_set_base_exit;
296 REG_WRITE(map->cntr, dspcntr);
298 REG_WRITE(map->base, start + offset);
301 psb_intel_pipe_cleaner:
302 /* If there was a previous display we can now unpin it */
304 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
306 psb_intel_pipe_set_base_exit:
312 * Sets the power management mode of the pipe and plane.
314 * This code should probably grow support for turning the cursor off and back
315 * on appropriately at the same time as we're turning the pipe off/on.
317 static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
319 struct drm_device *dev = crtc->dev;
320 struct drm_psb_private *dev_priv = dev->dev_private;
321 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
322 int pipe = psb_intel_crtc->pipe;
323 const struct psb_offset *map = &dev_priv->regmap[pipe];
326 /* XXX: When our outputs are all unaware of DPMS modes other than off
327 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
330 case DRM_MODE_DPMS_ON:
331 case DRM_MODE_DPMS_STANDBY:
332 case DRM_MODE_DPMS_SUSPEND:
333 /* Enable the DPLL */
334 temp = REG_READ(map->dpll);
335 if ((temp & DPLL_VCO_ENABLE) == 0) {
336 REG_WRITE(map->dpll, temp);
338 /* Wait for the clocks to stabilize. */
340 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
342 /* Wait for the clocks to stabilize. */
344 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
346 /* Wait for the clocks to stabilize. */
350 /* Enable the pipe */
351 temp = REG_READ(map->conf);
352 if ((temp & PIPEACONF_ENABLE) == 0)
353 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
355 /* Enable the plane */
356 temp = REG_READ(map->cntr);
357 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
359 temp | DISPLAY_PLANE_ENABLE);
360 /* Flush the plane changes */
361 REG_WRITE(map->base, REG_READ(map->base));
364 psb_intel_crtc_load_lut(crtc);
366 /* Give the overlay scaler a chance to enable
367 * if it's on this pipe */
368 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
370 case DRM_MODE_DPMS_OFF:
371 /* Give the overlay scaler a chance to disable
372 * if it's on this pipe */
373 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
375 /* Disable the VGA plane that we never use */
376 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
378 /* Disable display plane */
379 temp = REG_READ(map->cntr);
380 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
382 temp & ~DISPLAY_PLANE_ENABLE);
383 /* Flush the plane changes */
384 REG_WRITE(map->base, REG_READ(map->base));
388 /* Next, disable display pipes */
389 temp = REG_READ(map->conf);
390 if ((temp & PIPEACONF_ENABLE) != 0) {
391 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
395 /* Wait for vblank for the disable to take effect. */
396 psb_intel_wait_for_vblank(dev);
398 temp = REG_READ(map->dpll);
399 if ((temp & DPLL_VCO_ENABLE) != 0) {
400 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
404 /* Wait for the clocks to turn off. */
409 /*Set FIFO Watermarks*/
410 REG_WRITE(DSPARB, 0x3F3E);
413 static void psb_intel_crtc_prepare(struct drm_crtc *crtc)
415 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
416 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
419 static void psb_intel_crtc_commit(struct drm_crtc *crtc)
421 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
422 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
425 void psb_intel_encoder_prepare(struct drm_encoder *encoder)
427 struct drm_encoder_helper_funcs *encoder_funcs =
428 encoder->helper_private;
429 /* lvds has its own version of prepare see psb_intel_lvds_prepare */
430 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
433 void psb_intel_encoder_commit(struct drm_encoder *encoder)
435 struct drm_encoder_helper_funcs *encoder_funcs =
436 encoder->helper_private;
437 /* lvds has its own version of commit see psb_intel_lvds_commit */
438 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
441 void psb_intel_encoder_destroy(struct drm_encoder *encoder)
443 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
445 drm_encoder_cleanup(encoder);
446 kfree(intel_encoder);
449 static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc,
450 const struct drm_display_mode *mode,
451 struct drm_display_mode *adjusted_mode)
458 * Return the pipe currently connected to the panel fitter,
459 * or -1 if the panel fitter is not present or not in use
461 static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
465 pfit_control = REG_READ(PFIT_CONTROL);
467 /* See if the panel fitter is in use */
468 if ((pfit_control & PFIT_ENABLE) == 0)
470 /* Must be on PIPE 1 for PSB */
474 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
475 struct drm_display_mode *mode,
476 struct drm_display_mode *adjusted_mode,
478 struct drm_framebuffer *old_fb)
480 struct drm_device *dev = crtc->dev;
481 struct drm_psb_private *dev_priv = dev->dev_private;
482 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
483 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
484 int pipe = psb_intel_crtc->pipe;
485 const struct psb_offset *map = &dev_priv->regmap[pipe];
487 struct psb_intel_clock_t clock;
488 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
489 bool ok, is_sdvo = false;
490 bool is_lvds = false, is_tv = false;
491 struct drm_mode_config *mode_config = &dev->mode_config;
492 struct drm_connector *connector;
494 /* No scan out no play */
495 if (crtc->fb == NULL) {
496 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
500 list_for_each_entry(connector, &mode_config->connector_list, head) {
501 struct psb_intel_encoder *psb_intel_encoder =
502 psb_intel_attached_encoder(connector);
504 if (!connector->encoder
505 || connector->encoder->crtc != crtc)
508 switch (psb_intel_encoder->type) {
509 case INTEL_OUTPUT_LVDS:
512 case INTEL_OUTPUT_SDVO:
515 case INTEL_OUTPUT_TVOUT:
523 ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
526 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
530 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
532 dpll = DPLL_VGA_MODE_DIS;
534 dpll |= DPLLB_MODE_LVDS;
535 dpll |= DPLL_DVO_HIGH_SPEED;
537 dpll |= DPLLB_MODE_DAC_SERIAL;
539 int sdvo_pixel_multiply =
540 adjusted_mode->clock / mode->clock;
541 dpll |= DPLL_DVO_HIGH_SPEED;
543 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
546 /* compute bitmask from p1 value */
547 dpll |= (1 << (clock.p1 - 1)) << 16;
550 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
553 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
556 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
559 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
564 /* XXX: just matching BIOS for now */
565 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
568 dpll |= PLL_REF_INPUT_DREFCLK;
571 pipeconf = REG_READ(map->conf);
573 /* Set up the display plane register */
574 dspcntr = DISPPLANE_GAMMA_ENABLE;
577 dspcntr |= DISPPLANE_SEL_PIPE_A;
579 dspcntr |= DISPPLANE_SEL_PIPE_B;
581 dspcntr |= DISPLAY_PLANE_ENABLE;
582 pipeconf |= PIPEACONF_ENABLE;
583 dpll |= DPLL_VCO_ENABLE;
586 /* Disable the panel fitter if it was on our pipe */
587 if (psb_intel_panel_fitter_pipe(dev) == pipe)
588 REG_WRITE(PFIT_CONTROL, 0);
590 drm_mode_debug_printmodeline(mode);
592 if (dpll & DPLL_VCO_ENABLE) {
593 REG_WRITE(map->fp0, fp);
594 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
599 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
600 * This is an exception to the general rule that mode_set doesn't turn
604 u32 lvds = REG_READ(LVDS);
606 lvds &= ~LVDS_PIPEB_SELECT;
608 lvds |= LVDS_PIPEB_SELECT;
610 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
611 /* Set the B0-B3 data pairs corresponding to
612 * whether we're going to
613 * set the DPLLs for dual-channel mode or not.
615 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
617 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
619 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
620 * appropriately here, but we need to look more
621 * thoroughly into how panels behave in the two modes.
624 REG_WRITE(LVDS, lvds);
628 REG_WRITE(map->fp0, fp);
629 REG_WRITE(map->dpll, dpll);
631 /* Wait for the clocks to stabilize. */
634 /* write it again -- the BIOS does, after all */
635 REG_WRITE(map->dpll, dpll);
638 /* Wait for the clocks to stabilize. */
641 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
642 ((adjusted_mode->crtc_htotal - 1) << 16));
643 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
644 ((adjusted_mode->crtc_hblank_end - 1) << 16));
645 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
646 ((adjusted_mode->crtc_hsync_end - 1) << 16));
647 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
648 ((adjusted_mode->crtc_vtotal - 1) << 16));
649 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
650 ((adjusted_mode->crtc_vblank_end - 1) << 16));
651 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
652 ((adjusted_mode->crtc_vsync_end - 1) << 16));
653 /* pipesrc and dspsize control the size that is scaled from,
654 * which should always be the user's requested size.
657 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
658 REG_WRITE(map->pos, 0);
660 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
661 REG_WRITE(map->conf, pipeconf);
664 psb_intel_wait_for_vblank(dev);
666 REG_WRITE(map->cntr, dspcntr);
668 /* Flush the plane changes */
669 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
671 psb_intel_wait_for_vblank(dev);
676 /** Loads the palette/gamma unit for the CRTC with the prepared values */
677 void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
679 struct drm_device *dev = crtc->dev;
680 struct drm_psb_private *dev_priv = dev->dev_private;
681 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
682 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
683 int palreg = map->palette;
686 /* The clocks have to be on to load the palette. */
690 switch (psb_intel_crtc->pipe) {
695 dev_err(dev->dev, "Illegal Pipe Number.\n");
699 if (gma_power_begin(dev, false)) {
700 for (i = 0; i < 256; i++) {
701 REG_WRITE(palreg + 4 * i,
702 ((psb_intel_crtc->lut_r[i] +
703 psb_intel_crtc->lut_adj[i]) << 16) |
704 ((psb_intel_crtc->lut_g[i] +
705 psb_intel_crtc->lut_adj[i]) << 8) |
706 (psb_intel_crtc->lut_b[i] +
707 psb_intel_crtc->lut_adj[i]));
711 for (i = 0; i < 256; i++) {
712 dev_priv->regs.pipe[0].palette[i] =
713 ((psb_intel_crtc->lut_r[i] +
714 psb_intel_crtc->lut_adj[i]) << 16) |
715 ((psb_intel_crtc->lut_g[i] +
716 psb_intel_crtc->lut_adj[i]) << 8) |
717 (psb_intel_crtc->lut_b[i] +
718 psb_intel_crtc->lut_adj[i]);
725 * Save HW states of giving crtc
727 static void psb_intel_crtc_save(struct drm_crtc *crtc)
729 struct drm_device *dev = crtc->dev;
730 struct drm_psb_private *dev_priv = dev->dev_private;
731 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
732 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
733 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
738 dev_err(dev->dev, "No CRTC state found\n");
742 crtc_state->saveDSPCNTR = REG_READ(map->cntr);
743 crtc_state->savePIPECONF = REG_READ(map->conf);
744 crtc_state->savePIPESRC = REG_READ(map->src);
745 crtc_state->saveFP0 = REG_READ(map->fp0);
746 crtc_state->saveFP1 = REG_READ(map->fp1);
747 crtc_state->saveDPLL = REG_READ(map->dpll);
748 crtc_state->saveHTOTAL = REG_READ(map->htotal);
749 crtc_state->saveHBLANK = REG_READ(map->hblank);
750 crtc_state->saveHSYNC = REG_READ(map->hsync);
751 crtc_state->saveVTOTAL = REG_READ(map->vtotal);
752 crtc_state->saveVBLANK = REG_READ(map->vblank);
753 crtc_state->saveVSYNC = REG_READ(map->vsync);
754 crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
756 /*NOTE: DSPSIZE DSPPOS only for psb*/
757 crtc_state->saveDSPSIZE = REG_READ(map->size);
758 crtc_state->saveDSPPOS = REG_READ(map->pos);
760 crtc_state->saveDSPBASE = REG_READ(map->base);
762 paletteReg = map->palette;
763 for (i = 0; i < 256; ++i)
764 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
768 * Restore HW states of giving crtc
770 static void psb_intel_crtc_restore(struct drm_crtc *crtc)
772 struct drm_device *dev = crtc->dev;
773 struct drm_psb_private *dev_priv = dev->dev_private;
774 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
775 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
776 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
781 dev_err(dev->dev, "No crtc state\n");
785 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
787 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
792 REG_WRITE(map->fp0, crtc_state->saveFP0);
795 REG_WRITE(map->fp1, crtc_state->saveFP1);
798 REG_WRITE(map->dpll, crtc_state->saveDPLL);
802 REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
803 REG_WRITE(map->hblank, crtc_state->saveHBLANK);
804 REG_WRITE(map->hsync, crtc_state->saveHSYNC);
805 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
806 REG_WRITE(map->vblank, crtc_state->saveVBLANK);
807 REG_WRITE(map->vsync, crtc_state->saveVSYNC);
808 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
810 REG_WRITE(map->size, crtc_state->saveDSPSIZE);
811 REG_WRITE(map->pos, crtc_state->saveDSPPOS);
813 REG_WRITE(map->src, crtc_state->savePIPESRC);
814 REG_WRITE(map->base, crtc_state->saveDSPBASE);
815 REG_WRITE(map->conf, crtc_state->savePIPECONF);
817 psb_intel_wait_for_vblank(dev);
819 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
820 REG_WRITE(map->base, crtc_state->saveDSPBASE);
822 psb_intel_wait_for_vblank(dev);
824 paletteReg = map->palette;
825 for (i = 0; i < 256; ++i)
826 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
829 static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
830 struct drm_file *file_priv,
832 uint32_t width, uint32_t height)
834 struct drm_device *dev = crtc->dev;
835 struct drm_psb_private *dev_priv = dev->dev_private;
836 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
837 int pipe = psb_intel_crtc->pipe;
838 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
839 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
842 struct gtt_range *gt;
843 struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt;
844 struct drm_gem_object *obj;
845 void *tmp_dst, *tmp_src;
846 int ret = 0, i, cursor_pages;
848 /* if we want to turn of the cursor ignore width and height */
850 /* turn off the cursor */
851 temp = CURSOR_MODE_DISABLE;
853 if (gma_power_begin(dev, false)) {
854 REG_WRITE(control, temp);
859 /* Unpin the old GEM object */
860 if (psb_intel_crtc->cursor_obj) {
861 gt = container_of(psb_intel_crtc->cursor_obj,
862 struct gtt_range, gem);
864 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
865 psb_intel_crtc->cursor_obj = NULL;
871 /* Currently we only support 64x64 cursors */
872 if (width != 64 || height != 64) {
873 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
877 obj = drm_gem_object_lookup(dev, file_priv, handle);
881 if (obj->size < width * height * 4) {
882 dev_dbg(dev->dev, "buffer is to small\n");
887 gt = container_of(obj, struct gtt_range, gem);
889 /* Pin the memory into the GTT */
890 ret = psb_gtt_pin(gt);
892 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
896 if (dev_priv->ops->cursor_needs_phys) {
897 if (cursor_gt == NULL) {
898 dev_err(dev->dev, "No hardware cursor mem available");
903 /* Prevent overflow */
907 cursor_pages = gt->npage;
909 /* Copy the cursor to cursor mem */
910 tmp_dst = dev_priv->vram_addr + cursor_gt->offset;
911 for (i = 0; i < cursor_pages; i++) {
912 tmp_src = kmap(gt->pages[i]);
913 memcpy(tmp_dst, tmp_src, PAGE_SIZE);
914 kunmap(gt->pages[i]);
915 tmp_dst += PAGE_SIZE;
918 addr = psb_intel_crtc->cursor_addr;
920 addr = gt->offset; /* Or resource.start ??? */
921 psb_intel_crtc->cursor_addr = addr;
925 /* set the pipe for the cursor */
926 temp |= (pipe << 28);
927 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
929 if (gma_power_begin(dev, false)) {
930 REG_WRITE(control, temp);
931 REG_WRITE(base, addr);
935 /* unpin the old bo */
936 if (psb_intel_crtc->cursor_obj) {
937 gt = container_of(psb_intel_crtc->cursor_obj,
938 struct gtt_range, gem);
940 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
943 psb_intel_crtc->cursor_obj = obj;
947 drm_gem_object_unreference(obj);
951 static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
953 struct drm_device *dev = crtc->dev;
954 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
955 int pipe = psb_intel_crtc->pipe;
961 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
965 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
969 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
970 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
972 addr = psb_intel_crtc->cursor_addr;
974 if (gma_power_begin(dev, false)) {
975 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
976 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
982 static void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
983 u16 *green, u16 *blue, uint32_t type, uint32_t size)
985 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
991 for (i = 0; i < 256; i++) {
992 psb_intel_crtc->lut_r[i] = red[i] >> 8;
993 psb_intel_crtc->lut_g[i] = green[i] >> 8;
994 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
997 psb_intel_crtc_load_lut(crtc);
1000 static int psb_crtc_set_config(struct drm_mode_set *set)
1003 struct drm_device *dev = set->crtc->dev;
1004 struct drm_psb_private *dev_priv = dev->dev_private;
1006 if (!dev_priv->rpm_enabled)
1007 return drm_crtc_helper_set_config(set);
1009 pm_runtime_forbid(&dev->pdev->dev);
1010 ret = drm_crtc_helper_set_config(set);
1011 pm_runtime_allow(&dev->pdev->dev);
1015 /* Returns the clock of the currently programmed mode of the given pipe. */
1016 static int psb_intel_crtc_clock_get(struct drm_device *dev,
1017 struct drm_crtc *crtc)
1019 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1020 struct drm_psb_private *dev_priv = dev->dev_private;
1021 int pipe = psb_intel_crtc->pipe;
1022 const struct psb_offset *map = &dev_priv->regmap[pipe];
1025 struct psb_intel_clock_t clock;
1027 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1029 if (gma_power_begin(dev, false)) {
1030 dpll = REG_READ(map->dpll);
1031 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1032 fp = REG_READ(map->fp0);
1034 fp = REG_READ(map->fp1);
1035 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1040 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1045 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
1049 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1050 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1051 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1056 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1057 DPLL_FPA01_P1_POST_DIV_SHIFT);
1060 if ((dpll & PLL_REF_INPUT_MASK) ==
1061 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1062 /* XXX: might not be 66MHz */
1063 psb_intel_clock(66000, &clock);
1065 psb_intel_clock(48000, &clock);
1067 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1072 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1073 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1075 if (dpll & PLL_P2_DIVIDE_BY_4)
1080 psb_intel_clock(48000, &clock);
1083 /* XXX: It would be nice to validate the clocks, but we can't reuse
1084 * i830PllIsValid() because it relies on the xf86_config connector
1085 * configuration being accurate, which it isn't necessarily.
1091 /** Returns the currently programmed mode of the given pipe. */
1092 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
1093 struct drm_crtc *crtc)
1095 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1096 int pipe = psb_intel_crtc->pipe;
1097 struct drm_display_mode *mode;
1102 struct drm_psb_private *dev_priv = dev->dev_private;
1103 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1104 const struct psb_offset *map = &dev_priv->regmap[pipe];
1106 if (gma_power_begin(dev, false)) {
1107 htot = REG_READ(map->htotal);
1108 hsync = REG_READ(map->hsync);
1109 vtot = REG_READ(map->vtotal);
1110 vsync = REG_READ(map->vsync);
1119 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1123 mode->clock = psb_intel_crtc_clock_get(dev, crtc);
1124 mode->hdisplay = (htot & 0xffff) + 1;
1125 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1126 mode->hsync_start = (hsync & 0xffff) + 1;
1127 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1128 mode->vdisplay = (vtot & 0xffff) + 1;
1129 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1130 mode->vsync_start = (vsync & 0xffff) + 1;
1131 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1133 drm_mode_set_name(mode);
1134 drm_mode_set_crtcinfo(mode, 0);
1139 static void psb_intel_crtc_destroy(struct drm_crtc *crtc)
1141 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1142 struct gtt_range *gt;
1144 /* Unpin the old GEM object */
1145 if (psb_intel_crtc->cursor_obj) {
1146 gt = container_of(psb_intel_crtc->cursor_obj,
1147 struct gtt_range, gem);
1149 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1150 psb_intel_crtc->cursor_obj = NULL;
1153 if (psb_intel_crtc->cursor_gt != NULL)
1154 psb_gtt_free_range(crtc->dev, psb_intel_crtc->cursor_gt);
1155 kfree(psb_intel_crtc->crtc_state);
1156 drm_crtc_cleanup(crtc);
1157 kfree(psb_intel_crtc);
1160 static void psb_intel_crtc_disable(struct drm_crtc *crtc)
1162 struct gtt_range *gt;
1163 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1165 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1168 gt = to_psb_fb(crtc->fb)->gtt;
1173 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
1174 .dpms = psb_intel_crtc_dpms,
1175 .mode_fixup = psb_intel_crtc_mode_fixup,
1176 .mode_set = psb_intel_crtc_mode_set,
1177 .mode_set_base = psb_intel_pipe_set_base,
1178 .prepare = psb_intel_crtc_prepare,
1179 .commit = psb_intel_crtc_commit,
1180 .disable = psb_intel_crtc_disable,
1183 const struct drm_crtc_funcs psb_intel_crtc_funcs = {
1184 .save = psb_intel_crtc_save,
1185 .restore = psb_intel_crtc_restore,
1186 .cursor_set = psb_intel_crtc_cursor_set,
1187 .cursor_move = psb_intel_crtc_cursor_move,
1188 .gamma_set = psb_intel_crtc_gamma_set,
1189 .set_config = psb_crtc_set_config,
1190 .destroy = psb_intel_crtc_destroy,
1194 * Set the default value of cursor control and base register
1195 * to zero. This is a workaround for h/w defect on Oaktrail
1197 static void psb_intel_cursor_init(struct drm_device *dev,
1198 struct psb_intel_crtc *psb_intel_crtc)
1200 struct drm_psb_private *dev_priv = dev->dev_private;
1201 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
1202 u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
1203 struct gtt_range *cursor_gt;
1205 if (dev_priv->ops->cursor_needs_phys) {
1206 /* Allocate 4 pages of stolen mem for a hardware cursor. That
1207 * is enough for the 64 x 64 ARGB cursors we support.
1209 cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1);
1211 psb_intel_crtc->cursor_gt = NULL;
1214 psb_intel_crtc->cursor_gt = cursor_gt;
1215 psb_intel_crtc->cursor_addr = dev_priv->stolen_base +
1218 psb_intel_crtc->cursor_gt = NULL;
1222 REG_WRITE(control[psb_intel_crtc->pipe], 0);
1223 REG_WRITE(base[psb_intel_crtc->pipe], 0);
1226 void psb_intel_crtc_init(struct drm_device *dev, int pipe,
1227 struct psb_intel_mode_device *mode_dev)
1229 struct drm_psb_private *dev_priv = dev->dev_private;
1230 struct psb_intel_crtc *psb_intel_crtc;
1232 uint16_t *r_base, *g_base, *b_base;
1234 /* We allocate a extra array of drm_connector pointers
1235 * for fbdev after the crtc */
1237 kzalloc(sizeof(struct psb_intel_crtc) +
1238 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
1240 if (psb_intel_crtc == NULL)
1243 psb_intel_crtc->crtc_state =
1244 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
1245 if (!psb_intel_crtc->crtc_state) {
1246 dev_err(dev->dev, "Crtc state error: No memory\n");
1247 kfree(psb_intel_crtc);
1251 /* Set the CRTC operations from the chip specific data */
1252 drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs);
1254 drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256);
1255 psb_intel_crtc->pipe = pipe;
1256 psb_intel_crtc->plane = pipe;
1258 r_base = psb_intel_crtc->base.gamma_store;
1259 g_base = r_base + 256;
1260 b_base = g_base + 256;
1261 for (i = 0; i < 256; i++) {
1262 psb_intel_crtc->lut_r[i] = i;
1263 psb_intel_crtc->lut_g[i] = i;
1264 psb_intel_crtc->lut_b[i] = i;
1269 psb_intel_crtc->lut_adj[i] = 0;
1272 psb_intel_crtc->mode_dev = mode_dev;
1273 psb_intel_crtc->cursor_addr = 0;
1275 drm_crtc_helper_add(&psb_intel_crtc->base,
1276 dev_priv->ops->crtc_helper);
1278 /* Setup the array of drm_connector pointer array */
1279 psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base;
1280 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
1281 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL);
1282 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] =
1283 &psb_intel_crtc->base;
1284 dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] =
1285 &psb_intel_crtc->base;
1286 psb_intel_crtc->mode_set.connectors =
1287 (struct drm_connector **) (psb_intel_crtc + 1);
1288 psb_intel_crtc->mode_set.num_connectors = 0;
1289 psb_intel_cursor_init(dev, psb_intel_crtc);
1291 /* Set to true so that the pipe is forced off on initial config. */
1292 psb_intel_crtc->active = true;
1295 int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1296 struct drm_file *file_priv)
1298 struct drm_psb_private *dev_priv = dev->dev_private;
1299 struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data;
1300 struct drm_mode_object *drmmode_obj;
1301 struct psb_intel_crtc *crtc;
1304 dev_err(dev->dev, "called with no initialization\n");
1308 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
1309 DRM_MODE_OBJECT_CRTC);
1312 dev_err(dev->dev, "no such CRTC id\n");
1316 crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj));
1317 pipe_from_crtc_id->pipe = crtc->pipe;
1322 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1324 struct drm_crtc *crtc = NULL;
1326 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1327 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1328 if (psb_intel_crtc->pipe == pipe)
1334 int psb_intel_connector_clones(struct drm_device *dev, int type_mask)
1337 struct drm_connector *connector;
1340 list_for_each_entry(connector, &dev->mode_config.connector_list,
1342 struct psb_intel_encoder *psb_intel_encoder =
1343 psb_intel_attached_encoder(connector);
1344 if (type_mask & (1 << psb_intel_encoder->type))
1345 index_mask |= (1 << entry);
1351 /* current intel driver doesn't take advantage of encoders
1352 always give back the encoder for the connector
1354 struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector)
1356 struct psb_intel_encoder *psb_intel_encoder =
1357 psb_intel_attached_encoder(connector);
1359 return &psb_intel_encoder->base;
1362 void psb_intel_connector_attach_encoder(struct psb_intel_connector *connector,
1363 struct psb_intel_encoder *encoder)
1365 connector->encoder = encoder;
1366 drm_mode_connector_attach_encoder(&connector->base,