arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/bitops.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqchip.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/gpio.h>
  20 #include <clocksource/samsung_pwm.h>
  21 #include <linux/sched.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/of.h>
  24 #include <linux/of_fdt.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/export.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/of_address.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/clk-provider.h>
  31 #include <linux/irqchip/arm-gic.h>
  32 #include <linux/irqchip/chained_irq.h>
  33
  34 #include <asm/proc-fns.h>
  35 #include <asm/exception.h>
  36 #include <asm/hardware/cache-l2x0.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/irq.h>
  39 #include <asm/cacheflush.h>
  40
  41 #include <mach/regs-irq.h>
  42 #include <mach/regs-pmu.h>
  43 #include <mach/regs-gpio.h>
  44 #include <mach/irqs.h>
  45
  46 #include <plat/cpu.h>
  47 #include <plat/devs.h>
  48 #include <plat/pm.h>
  49 #include <plat/sdhci.h>
  50 #include <plat/gpio-cfg.h>
  51 #include <plat/adc-core.h>
  52 #include <plat/fb-core.h>
  53 #include <plat/fimc-core.h>
  54 #include <plat/iic-core.h>
  55 #include <plat/tv-core.h>
  56 #include <plat/spi-core.h>
  57 #include <plat/regs-serial.h>
  58
  59 #include "common.h"
  60 #define L2_AUX_VAL 0x7C470001
  61 #define L2_AUX_MASK 0xC200ffff
  62
  63 static const char name_exynos4210[] = "EXYNOS4210";
  64 static const char name_exynos4212[] = "EXYNOS4212";
  65 static const char name_exynos4412[] = "EXYNOS4412";
  66 static const char name_exynos5250[] = "EXYNOS5250";
  67 static const char name_exynos5440[] = "EXYNOS5440";
  68
  69 static void exynos4_map_io(void);
  70 static void exynos5_map_io(void);
  71 static void exynos5440_map_io(void);
  72 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  73 static int exynos_init(void);
  74
  75 unsigned long xxti_f = 0, xusbxti_f = 0;
  76
  77 static struct cpu_table cpu_ids[] __initdata = {
  78         {
  79                 .idcode         = EXYNOS4210_CPU_ID,
  80                 .idmask         = EXYNOS4_CPU_MASK,
  81                 .map_io         = exynos4_map_io,
  82                 .init_uarts     = exynos4_init_uarts,
  83                 .init           = exynos_init,
  84                 .name           = name_exynos4210,
  85         }, {
  86                 .idcode         = EXYNOS4212_CPU_ID,
  87                 .idmask         = EXYNOS4_CPU_MASK,
  88                 .map_io         = exynos4_map_io,
  89                 .init_uarts     = exynos4_init_uarts,
  90                 .init           = exynos_init,
  91                 .name           = name_exynos4212,
  92         }, {
  93                 .idcode         = EXYNOS4412_CPU_ID,
  94                 .idmask         = EXYNOS4_CPU_MASK,
  95                 .map_io         = exynos4_map_io,
  96                 .init_uarts     = exynos4_init_uarts,
  97                 .init           = exynos_init,
  98                 .name           = name_exynos4412,
  99         }, {
 100                 .idcode         = EXYNOS5250_SOC_ID,
 101                 .idmask         = EXYNOS5_SOC_MASK,
 102                 .map_io         = exynos5_map_io,
 103                 .init           = exynos_init,
 104                 .name           = name_exynos5250,
 105         }, {
 106                 .idcode         = EXYNOS5440_SOC_ID,
 107                 .idmask         = EXYNOS5_SOC_MASK,
 108                 .map_io         = exynos5440_map_io,
 109                 .init           = exynos_init,
 110                 .name           = name_exynos5440,
 111         },
 112 };
 113
 114 /* Initial IO mappings */
 115
 116 static struct map_desc exynos_iodesc[] __initdata = {
 117         {
 118                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 119                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 120                 .length         = SZ_4K,
 121                 .type           = MT_DEVICE,
 122         },
 123 };
 124
 125 static struct map_desc exynos4_iodesc[] __initdata = {
 126         {
 127                 .virtual        = (unsigned long)S3C_VA_SYS,
 128                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 129                 .length         = SZ_64K,
 130                 .type           = MT_DEVICE,
 131         }, {
 132                 .virtual        = (unsigned long)S3C_VA_TIMER,
 133                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 134                 .length         = SZ_16K,
 135                 .type           = MT_DEVICE,
 136         }, {
 137                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 138                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 139                 .length         = SZ_4K,
 140                 .type           = MT_DEVICE,
 141         }, {
 142                 .virtual        = (unsigned long)S5P_VA_SROMC,
 143                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 144                 .length         = SZ_4K,
 145                 .type           = MT_DEVICE,
 146         }, {
 147                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 148                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE,
 151         }, {
 152                 .virtual        = (unsigned long)S5P_VA_PMU,
 153                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 154                 .length         = SZ_64K,
 155                 .type           = MT_DEVICE,
 156         }, {
 157                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 158                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 159                 .length         = SZ_4K,
 160                 .type           = MT_DEVICE,
 161         }, {
 162                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 163                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 164                 .length         = SZ_64K,
 165                 .type           = MT_DEVICE,
 166         }, {
 167                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 168                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 169                 .length         = SZ_64K,
 170                 .type           = MT_DEVICE,
 171         }, {
 172                 .virtual        = (unsigned long)S3C_VA_UART,
 173                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 174                 .length         = SZ_512K,
 175                 .type           = MT_DEVICE,
 176         }, {
 177                 .virtual        = (unsigned long)S5P_VA_CMU,
 178                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 179                 .length         = SZ_128K,
 180                 .type           = MT_DEVICE,
 181         }, {
 182                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 183                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 184                 .length         = SZ_8K,
 185                 .type           = MT_DEVICE,
 186         }, {
 187                 .virtual        = (unsigned long)S5P_VA_L2CC,
 188                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 189                 .length         = SZ_4K,
 190                 .type           = MT_DEVICE,
 191         }, {
 192                 .virtual        = (unsigned long)S5P_VA_DMC0,
 193                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 194                 .length         = SZ_64K,
 195                 .type           = MT_DEVICE,
 196         }, {
 197                 .virtual        = (unsigned long)S5P_VA_DMC1,
 198                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 199                 .length         = SZ_64K,
 200                 .type           = MT_DEVICE,
 201         }, {
 202                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 203                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 204                 .length         = SZ_4K,
 205                 .type           = MT_DEVICE,
 206         },
 207 };
 208
 209 static struct map_desc exynos4_iodesc0[] __initdata = {
 210         {
 211                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 212                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 213                 .length         = SZ_4K,
 214                 .type           = MT_DEVICE,
 215         },
 216 };
 217
 218 static struct map_desc exynos4_iodesc1[] __initdata = {
 219         {
 220                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 221                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 222                 .length         = SZ_4K,
 223                 .type           = MT_DEVICE,
 224         },
 225 };
 226
 227 static struct map_desc exynos4210_iodesc[] __initdata = {
 228         {
 229                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 230                 .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
 231                 .length         = SZ_4K,
 232                 .type           = MT_DEVICE,
 233         },
 234 };
 235
 236 static struct map_desc exynos4x12_iodesc[] __initdata = {
 237         {
 238                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 239                 .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
 240                 .length         = SZ_4K,
 241                 .type           = MT_DEVICE,
 242         },
 243 };
 244
 245 static struct map_desc exynos5250_iodesc[] __initdata = {
 246         {
 247                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 248                 .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
 249                 .length         = SZ_4K,
 250                 .type           = MT_DEVICE,
 251         },
 252 };
 253
 254 static struct map_desc exynos5_iodesc[] __initdata = {
 255         {
 256                 .virtual        = (unsigned long)S3C_VA_SYS,
 257                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 258                 .length         = SZ_64K,
 259                 .type           = MT_DEVICE,
 260         }, {
 261                 .virtual        = (unsigned long)S3C_VA_TIMER,
 262                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 263                 .length         = SZ_16K,
 264                 .type           = MT_DEVICE,
 265         }, {
 266                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 267                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 268                 .length         = SZ_4K,
 269                 .type           = MT_DEVICE,
 270         }, {
 271                 .virtual        = (unsigned long)S5P_VA_SROMC,
 272                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 273                 .length         = SZ_4K,
 274                 .type           = MT_DEVICE,
 275         }, {
 276                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 277                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 278                 .length         = SZ_4K,
 279                 .type           = MT_DEVICE,
 280         }, {
 281                 .virtual        = (unsigned long)S5P_VA_CMU,
 282                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 283                 .length         = 144 * SZ_1K,
 284                 .type           = MT_DEVICE,
 285         }, {
 286                 .virtual        = (unsigned long)S5P_VA_PMU,
 287                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 288                 .length         = SZ_64K,
 289                 .type           = MT_DEVICE,
 290         }, {
 291                 .virtual        = (unsigned long)S3C_VA_UART,
 292                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 293                 .length         = SZ_512K,
 294                 .type           = MT_DEVICE,
 295         },
 296 };
 297
 298 static struct map_desc exynos5440_iodesc0[] __initdata = {
 299         {
 300                 .virtual        = (unsigned long)S3C_VA_UART,
 301                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 302                 .length         = SZ_512K,
 303                 .type           = MT_DEVICE,
 304         },
 305 };
 306
 307 static struct samsung_pwm_variant exynos4_pwm_variant = {
 308         .bits           = 32,
 309         .div_base       = 0,
 310         .has_tint_cstat = true,
 311         .tclk_mask      = 0,
 312 };
 313
 314 void exynos4_restart(char mode, const char *cmd)
 315 {
 316         __raw_writel(0x1, S5P_SWRESET);
 317 }
 318
 319 void exynos5_restart(char mode, const char *cmd)
 320 {
 321         struct device_node *np;
 322         u32 val;
 323         void __iomem *addr;
 324
 325         if (of_machine_is_compatible("samsung,exynos5250")) {
 326                 val = 0x1;
 327                 addr = EXYNOS_SWRESET;
 328         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 329                 u32 status;
 330                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 331
 332                 addr = of_iomap(np, 0) + 0xbc;
 333                 status = __raw_readl(addr);
 334
 335                 addr = of_iomap(np, 0) + 0xcc;
 336                 val = __raw_readl(addr);
 337
 338                 val = (val & 0xffff0000) | (status & 0xffff);
 339         } else {
 340                 pr_err("%s: cannot support non-DT\n", __func__);
 341                 return;
 342         }
 343
 344         __raw_writel(val, addr);
 345 }
 346
 347 void __init exynos_init_late(void)
 348 {
 349         if (of_machine_is_compatible("samsung,exynos5440"))
 350                 /* to be supported later */
 351                 return;
 352
 353         exynos_pm_late_initcall();
 354 }
 355
 356 #ifdef CONFIG_OF
 357 int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 358                                         int depth, void *data)
 359 {
 360         struct map_desc iodesc;
 361         __be32 *reg;
 362         unsigned long len;
 363
 364         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 365                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 366                 return 0;
 367
 368         reg = of_get_flat_dt_prop(node, "reg", &len);
 369         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 370                 return 0;
 371
 372         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 373         iodesc.length = be32_to_cpu(reg[1]) - 1;
 374         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 375         iodesc.type = MT_DEVICE;
 376         iotable_init(&iodesc, 1);
 377         return 1;
 378 }
 379 #endif
 380
 381 /*
 382  * exynos_map_io
 383  *
 384  * register the standard cpu IO areas
 385  */
 386
 387 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 388 {
 389         debug_ll_io_init();
 390
 391 #ifdef CONFIG_OF
 392         if (initial_boot_params)
 393                 of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 394         else
 395 #endif
 396                 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 397
 398         if (mach_desc)
 399                 iotable_init(mach_desc, size);
 400
 401         /* detect cpu id and rev. */
 402         s5p_init_cpu(S5P_VA_CHIPID);
 403
 404         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 405 }
 406
 407 static void __init exynos4_map_io(void)
 408 {
 409         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 410
 411         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 412                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 413         else
 414                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 415
 416         if (soc_is_exynos4210())
 417                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
 418         if (soc_is_exynos4212() || soc_is_exynos4412())
 419                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
 420
 421         /* initialize device information early */
 422         exynos4_default_sdhci0();
 423         exynos4_default_sdhci1();
 424         exynos4_default_sdhci2();
 425         exynos4_default_sdhci3();
 426
 427         s3c_adc_setname("samsung-adc-v3");
 428
 429         s3c_fimc_setname(0, "exynos4-fimc");
 430         s3c_fimc_setname(1, "exynos4-fimc");
 431         s3c_fimc_setname(2, "exynos4-fimc");
 432         s3c_fimc_setname(3, "exynos4-fimc");
 433
 434         s3c_sdhci_setname(0, "exynos4-sdhci");
 435         s3c_sdhci_setname(1, "exynos4-sdhci");
 436         s3c_sdhci_setname(2, "exynos4-sdhci");
 437         s3c_sdhci_setname(3, "exynos4-sdhci");
 438
 439         /* The I2C bus controllers are directly compatible with s3c2440 */
 440         s3c_i2c0_setname("s3c2440-i2c");
 441         s3c_i2c1_setname("s3c2440-i2c");
 442         s3c_i2c2_setname("s3c2440-i2c");
 443
 444         s5p_fb_setname(0, "exynos4-fb");
 445         s5p_hdmi_setname("exynos4-hdmi");
 446
 447         s3c64xx_spi_setname("exynos4210-spi");
 448 }
 449
 450 static void __init exynos5_map_io(void)
 451 {
 452         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 453
 454         if (soc_is_exynos5250())
 455                 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 456 }
 457
 458 static void __init exynos5440_map_io(void)
 459 {
 460         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 461 }
 462
 463 void __init exynos_set_timer_source(u8 channels)
 464 {
 465         exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 466         exynos4_pwm_variant.output_mask &= ~channels;
 467 }
 468
 469 void __init exynos_init_time(void)
 470 {
 471         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 472                 EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
 473                 EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
 474                 EXYNOS4_IRQ_TIMER4_VIC,
 475         };
 476
 477         if (of_have_populated_dt()) {
 478 #ifdef CONFIG_OF
 479                 of_clk_init(NULL);
 480                 clocksource_of_init();
 481 #endif
 482         } else {
 483                 /* todo: remove after migrating legacy E4 platforms to dt */
 484 #ifdef CONFIG_ARCH_EXYNOS4
 485                 exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
 486                 exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
 487 #endif
 488 #ifdef CONFIG_CLKSRC_SAMSUNG_PWM
 489                 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 490                         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 491                                         timer_irqs, &exynos4_pwm_variant);
 492                 else
 493 #endif
 494                         mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
 495                                         EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
 496         }
 497 }
 498
 499 static unsigned int max_combiner_nr(void)
 500 {
 501         if (soc_is_exynos5250())
 502                 return EXYNOS5_MAX_COMBINER_NR;
 503         else if (soc_is_exynos4412())
 504                 return EXYNOS4412_MAX_COMBINER_NR;
 505         else if (soc_is_exynos4212())
 506                 return EXYNOS4212_MAX_COMBINER_NR;
 507         else
 508                 return EXYNOS4210_MAX_COMBINER_NR;
 509 }
 510
 511
 512 void __init exynos4_init_irq(void)
 513 {
 514         unsigned int gic_bank_offset;
 515
 516         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 517
 518         if (!of_have_populated_dt())
 519                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 520 #ifdef CONFIG_OF
 521         else
 522                 irqchip_init();
 523 #endif
 524
 525         if (!of_have_populated_dt())
 526                 combiner_init(S5P_VA_COMBINER_BASE, NULL,
 527                               max_combiner_nr(), COMBINER_IRQ(0, 0));
 528
 529         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 530 }
 531
 532 void __init exynos5_init_irq(void)
 533 {
 534 #ifdef CONFIG_OF
 535         irqchip_init();
 536 #endif
 537         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 538 }
 539
 540 struct bus_type exynos_subsys = {
 541         .name           = "exynos-core",
 542         .dev_name       = "exynos-core",
 543 };
 544
 545 static struct device exynos4_dev = {
 546         .bus    = &exynos_subsys,
 547 };
 548
 549 static int __init exynos_core_init(void)
 550 {
 551         return subsys_system_register(&exynos_subsys, NULL);
 552 }
 553 core_initcall(exynos_core_init);
 554
 555 #ifdef CONFIG_CACHE_L2X0
 556 static int __init exynos4_l2x0_cache_init(void)
 557 {
 558         int ret;
 559
 560         if (soc_is_exynos5250() || soc_is_exynos5440())
 561                 return 0;
 562
 563         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 564         if (!ret) {
 565                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 566                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 567                 return 0;
 568         }
 569
 570         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 571                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 572                 /* TAG, Data Latency Control: 2 cycles */
 573                 l2x0_saved_regs.tag_latency = 0x110;
 574
 575                 if (soc_is_exynos4212() || soc_is_exynos4412())
 576                         l2x0_saved_regs.data_latency = 0x120;
 577                 else
 578                         l2x0_saved_regs.data_latency = 0x110;
 579
 580                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 581                 l2x0_saved_regs.pwr_ctrl =
 582                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 583
 584                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 585
 586                 __raw_writel(l2x0_saved_regs.tag_latency,
 587                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 588                 __raw_writel(l2x0_saved_regs.data_latency,
 589                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 590
 591                 /* L2X0 Prefetch Control */
 592                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 593                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 594
 595                 /* L2X0 Power Control */
 596                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 597                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 598
 599                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 600                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 601         }
 602
 603         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 604         return 0;
 605 }
 606 early_initcall(exynos4_l2x0_cache_init);
 607 #endif
 608
 609 static int __init exynos_init(void)
 610 {
 611         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 612
 613         return device_register(&exynos4_dev);
 614 }
 615
 616 /* uart registration process */
 617
 618 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 619 {
 620         struct s3c2410_uartcfg *tcfg = cfg;
 621         u32 ucnt;
 622
 623         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 624                 tcfg->has_fracval = 1;
 625
 626         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 627 }
 628
 629 static void __iomem *exynos_eint_base;
 630
 631 static DEFINE_SPINLOCK(eint_lock);
 632
 633 static unsigned int eint0_15_data[16];
 634
 635 static inline int exynos4_irq_to_gpio(unsigned int irq)
 636 {
 637         if (irq < IRQ_EINT(0))
 638                 return -EINVAL;
 639
 640         irq -= IRQ_EINT(0);
 641         if (irq < 8)
 642                 return EXYNOS4_GPX0(irq);
 643
 644         irq -= 8;
 645         if (irq < 8)
 646                 return EXYNOS4_GPX1(irq);
 647
 648         irq -= 8;
 649         if (irq < 8)
 650                 return EXYNOS4_GPX2(irq);
 651
 652         irq -= 8;
 653         if (irq < 8)
 654                 return EXYNOS4_GPX3(irq);
 655
 656         return -EINVAL;
 657 }
 658
 659 static inline int exynos5_irq_to_gpio(unsigned int irq)
 660 {
 661         if (irq < IRQ_EINT(0))
 662                 return -EINVAL;
 663
 664         irq -= IRQ_EINT(0);
 665         if (irq < 8)
 666                 return EXYNOS5_GPX0(irq);
 667
 668         irq -= 8;
 669         if (irq < 8)
 670                 return EXYNOS5_GPX1(irq);
 671
 672         irq -= 8;
 673         if (irq < 8)
 674                 return EXYNOS5_GPX2(irq);
 675
 676         irq -= 8;
 677         if (irq < 8)
 678                 return EXYNOS5_GPX3(irq);
 679
 680         return -EINVAL;
 681 }
 682
 683 static unsigned int exynos4_eint0_15_src_int[16] = {
 684         EXYNOS4_IRQ_EINT0,
 685         EXYNOS4_IRQ_EINT1,
 686         EXYNOS4_IRQ_EINT2,
 687         EXYNOS4_IRQ_EINT3,
 688         EXYNOS4_IRQ_EINT4,
 689         EXYNOS4_IRQ_EINT5,
 690         EXYNOS4_IRQ_EINT6,
 691         EXYNOS4_IRQ_EINT7,
 692         EXYNOS4_IRQ_EINT8,
 693         EXYNOS4_IRQ_EINT9,
 694         EXYNOS4_IRQ_EINT10,
 695         EXYNOS4_IRQ_EINT11,
 696         EXYNOS4_IRQ_EINT12,
 697         EXYNOS4_IRQ_EINT13,
 698         EXYNOS4_IRQ_EINT14,
 699         EXYNOS4_IRQ_EINT15,
 700 };
 701
 702 static unsigned int exynos5_eint0_15_src_int[16] = {
 703         EXYNOS5_IRQ_EINT0,
 704         EXYNOS5_IRQ_EINT1,
 705         EXYNOS5_IRQ_EINT2,
 706         EXYNOS5_IRQ_EINT3,
 707         EXYNOS5_IRQ_EINT4,
 708         EXYNOS5_IRQ_EINT5,
 709         EXYNOS5_IRQ_EINT6,
 710         EXYNOS5_IRQ_EINT7,
 711         EXYNOS5_IRQ_EINT8,
 712         EXYNOS5_IRQ_EINT9,
 713         EXYNOS5_IRQ_EINT10,
 714         EXYNOS5_IRQ_EINT11,
 715         EXYNOS5_IRQ_EINT12,
 716         EXYNOS5_IRQ_EINT13,
 717         EXYNOS5_IRQ_EINT14,
 718         EXYNOS5_IRQ_EINT15,
 719 };
 720 static inline void exynos_irq_eint_mask(struct irq_data *data)
 721 {
 722         u32 mask;
 723
 724         spin_lock(&eint_lock);
 725         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 726         mask |= EINT_OFFSET_BIT(data->irq);
 727         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 728         spin_unlock(&eint_lock);
 729 }
 730
 731 static void exynos_irq_eint_unmask(struct irq_data *data)
 732 {
 733         u32 mask;
 734
 735         spin_lock(&eint_lock);
 736         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 737         mask &= ~(EINT_OFFSET_BIT(data->irq));
 738         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 739         spin_unlock(&eint_lock);
 740 }
 741
 742 static inline void exynos_irq_eint_ack(struct irq_data *data)
 743 {
 744         __raw_writel(EINT_OFFSET_BIT(data->irq),
 745                      EINT_PEND(exynos_eint_base, data->irq));
 746 }
 747
 748 static void exynos_irq_eint_maskack(struct irq_data *data)
 749 {
 750         exynos_irq_eint_mask(data);
 751         exynos_irq_eint_ack(data);
 752 }
 753
 754 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 755 {
 756         int offs = EINT_OFFSET(data->irq);
 757         int shift;
 758         u32 ctrl, mask;
 759         u32 newvalue = 0;
 760
 761         switch (type) {
 762         case IRQ_TYPE_EDGE_RISING:
 763                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 764                 break;
 765
 766         case IRQ_TYPE_EDGE_FALLING:
 767                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 768                 break;
 769
 770         case IRQ_TYPE_EDGE_BOTH:
 771                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 772                 break;
 773
 774         case IRQ_TYPE_LEVEL_LOW:
 775                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 776                 break;
 777
 778         case IRQ_TYPE_LEVEL_HIGH:
 779                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 780                 break;
 781
 782         default:
 783                 printk(KERN_ERR "No such irq type %d", type);
 784                 return -EINVAL;
 785         }
 786
 787         shift = (offs & 0x7) * 4;
 788         mask = 0x7 << shift;
 789
 790         spin_lock(&eint_lock);
 791         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 792         ctrl &= ~mask;
 793         ctrl |= newvalue << shift;
 794         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 795         spin_unlock(&eint_lock);
 796
 797         if (soc_is_exynos5250())
 798                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 799         else
 800                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 801
 802         return 0;
 803 }
 804
 805 static struct irq_chip exynos_irq_eint = {
 806         .name           = "exynos-eint",
 807         .irq_mask       = exynos_irq_eint_mask,
 808         .irq_unmask     = exynos_irq_eint_unmask,
 809         .irq_mask_ack   = exynos_irq_eint_maskack,
 810         .irq_ack        = exynos_irq_eint_ack,
 811         .irq_set_type   = exynos_irq_eint_set_type,
 812 #ifdef CONFIG_PM
 813         .irq_set_wake   = s3c_irqext_wake,
 814 #endif
 815 };
 816
 817 /*
 818  * exynos4_irq_demux_eint
 819  *
 820  * This function demuxes the IRQ from from EINTs 16 to 31.
 821  * It is designed to be inlined into the specific handler
 822  * s5p_irq_demux_eintX_Y.
 823  *
 824  * Each EINT pend/mask registers handle eight of them.
 825  */
 826 static inline void exynos_irq_demux_eint(unsigned int start)
 827 {
 828         unsigned int irq;
 829
 830         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 831         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 832
 833         status &= ~mask;
 834         status &= 0xff;
 835
 836         while (status) {
 837                 irq = fls(status) - 1;
 838                 generic_handle_irq(irq + start);
 839                 status &= ~(1 << irq);
 840         }
 841 }
 842
 843 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 844 {
 845         struct irq_chip *chip = irq_get_chip(irq);
 846         chained_irq_enter(chip, desc);
 847         exynos_irq_demux_eint(IRQ_EINT(16));
 848         exynos_irq_demux_eint(IRQ_EINT(24));
 849         chained_irq_exit(chip, desc);
 850 }
 851
 852 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 853 {
 854         u32 *irq_data = irq_get_handler_data(irq);
 855         struct irq_chip *chip = irq_get_chip(irq);
 856
 857         chained_irq_enter(chip, desc);
 858         generic_handle_irq(*irq_data);
 859         chained_irq_exit(chip, desc);
 860 }
 861
 862 static int __init exynos_init_irq_eint(void)
 863 {
 864         int irq;
 865
 866 #ifdef CONFIG_PINCTRL_SAMSUNG
 867         /*
 868          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 869          * functionality along with support for external gpio and wakeup
 870          * interrupts. If the samsung pinctrl driver is enabled and includes
 871          * the wakeup interrupt support, then the setting up external wakeup
 872          * interrupts here can be skipped. This check here is temporary to
 873          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 874          * co-exist with platforms that do. When all of the Samsung Exynos4
 875          * platforms switch over to using the pinctrl driver, the wakeup
 876          * interrupt support code here can be completely removed.
 877          */
 878         static const struct of_device_id exynos_pinctrl_ids[] = {
 879                 { .compatible = "samsung,exynos4210-pinctrl", },
 880                 { .compatible = "samsung,exynos4x12-pinctrl", },
 881                 { .compatible = "samsung,exynos5250-pinctrl", },
 882         };
 883         struct device_node *pctrl_np, *wkup_np;
 884         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 885
 886         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
 887                 if (of_device_is_available(pctrl_np)) {
 888                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
 889                                                         wkup_compat);
 890                         if (wkup_np)
 891                                 return -ENODEV;
 892                 }
 893         }
 894 #endif
 895         if (soc_is_exynos5440())
 896                 return 0;
 897
 898         if (soc_is_exynos5250())
 899                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 900         else
 901                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 902
 903         if (exynos_eint_base == NULL) {
 904                 pr_err("unable to ioremap for EINT base address\n");
 905                 return -ENOMEM;
 906         }
 907
 908         for (irq = 0 ; irq <= 31 ; irq++) {
 909                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 910                                          handle_level_irq);
 911                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 912         }
 913
 914         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 915
 916         for (irq = 0 ; irq <= 15 ; irq++) {
 917                 eint0_15_data[irq] = IRQ_EINT(irq);
 918
 919                 if (soc_is_exynos5250()) {
 920                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 921                                              &eint0_15_data[irq]);
 922                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 923                                                 exynos_irq_eint0_15);
 924                 } else {
 925                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 926                                              &eint0_15_data[irq]);
 927                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 928                                                 exynos_irq_eint0_15);
 929                 }
 930         }
 931
 932         return 0;
 933 }
 934 arch_initcall(exynos_init_irq_eint);
 935
 936 static struct resource exynos4_pmu_resource[] = {
 937         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
 938         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
 939 #if defined(CONFIG_SOC_EXYNOS4412)
 940         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
 941         DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
 942 #endif
 943 };
 944
 945 static struct platform_device exynos4_device_pmu = {
 946         .name           = "arm-pmu",
 947         .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
 948         .resource       = exynos4_pmu_resource,
 949 };
 950
 951 static int __init exynos_armpmu_init(void)
 952 {
 953         if (!of_have_populated_dt()) {
 954                 if (soc_is_exynos4210() || soc_is_exynos4212())
 955                         exynos4_device_pmu.num_resources = 2;
 956                 platform_device_register(&exynos4_device_pmu);
 957         }
 958
 959         return 0;
 960 }
 961 arch_initcall(exynos_armpmu_init);