2 * Copyright © 2008,2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uk>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/dma_remapping.h>
37 struct list_head objects;
40 struct drm_i915_gem_object *lut[0];
41 struct hlist_head buckets[0];
45 static struct eb_objects *
46 eb_create(struct drm_i915_gem_execbuffer2 *args)
48 struct eb_objects *eb = NULL;
50 if (args->flags & I915_EXEC_HANDLE_LUT) {
51 int size = args->buffer_count;
52 size *= sizeof(struct drm_i915_gem_object *);
53 size += sizeof(struct eb_objects);
54 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
58 int size = args->buffer_count;
59 int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
60 BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head)));
61 while (count > 2*size)
63 eb = kzalloc(count*sizeof(struct hlist_head) +
64 sizeof(struct eb_objects),
71 eb->and = -args->buffer_count;
73 INIT_LIST_HEAD(&eb->objects);
78 eb_reset(struct eb_objects *eb)
81 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
85 eb_lookup_objects(struct eb_objects *eb,
86 struct drm_i915_gem_exec_object2 *exec,
87 const struct drm_i915_gem_execbuffer2 *args,
88 struct drm_file *file)
92 spin_lock(&file->table_lock);
93 for (i = 0; i < args->buffer_count; i++) {
94 struct drm_i915_gem_object *obj;
96 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
98 spin_unlock(&file->table_lock);
99 DRM_DEBUG("Invalid object handle %d at index %d\n",
104 if (!list_empty(&obj->exec_list)) {
105 spin_unlock(&file->table_lock);
106 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
107 obj, exec[i].handle, i);
111 drm_gem_object_reference(&obj->base);
112 list_add_tail(&obj->exec_list, &eb->objects);
114 obj->exec_entry = &exec[i];
118 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
119 obj->exec_handle = handle;
120 hlist_add_head(&obj->exec_node,
121 &eb->buckets[handle & eb->and]);
124 spin_unlock(&file->table_lock);
129 static struct drm_i915_gem_object *
130 eb_get_object(struct eb_objects *eb, unsigned long handle)
133 if (handle >= -eb->and)
135 return eb->lut[handle];
137 struct hlist_head *head;
138 struct hlist_node *node;
140 head = &eb->buckets[handle & eb->and];
141 hlist_for_each(node, head) {
142 struct drm_i915_gem_object *obj;
144 obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
145 if (obj->exec_handle == handle)
153 eb_destroy(struct eb_objects *eb)
155 while (!list_empty(&eb->objects)) {
156 struct drm_i915_gem_object *obj;
158 obj = list_first_entry(&eb->objects,
159 struct drm_i915_gem_object,
161 list_del_init(&obj->exec_list);
162 drm_gem_object_unreference(&obj->base);
167 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
169 return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
170 !obj->map_and_fenceable ||
171 obj->cache_level != I915_CACHE_NONE);
175 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
176 struct eb_objects *eb,
177 struct drm_i915_gem_relocation_entry *reloc)
179 struct drm_device *dev = obj->base.dev;
180 struct drm_gem_object *target_obj;
181 struct drm_i915_gem_object *target_i915_obj;
182 uint32_t target_offset;
185 /* we've already hold a reference to all valid objects */
186 target_obj = &eb_get_object(eb, reloc->target_handle)->base;
187 if (unlikely(target_obj == NULL))
190 target_i915_obj = to_intel_bo(target_obj);
191 target_offset = target_i915_obj->gtt_offset;
193 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
194 * pipe_control writes because the gpu doesn't properly redirect them
195 * through the ppgtt for non_secure batchbuffers. */
196 if (unlikely(IS_GEN6(dev) &&
197 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
198 !target_i915_obj->has_global_gtt_mapping)) {
199 i915_gem_gtt_bind_object(target_i915_obj,
200 target_i915_obj->cache_level);
203 /* Validate that the target is in a valid r/w GPU domain */
204 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
205 DRM_DEBUG("reloc with multiple write domains: "
206 "obj %p target %d offset %d "
207 "read %08x write %08x",
208 obj, reloc->target_handle,
211 reloc->write_domain);
214 if (unlikely((reloc->write_domain | reloc->read_domains)
215 & ~I915_GEM_GPU_DOMAINS)) {
216 DRM_DEBUG("reloc with read/write non-GPU domains: "
217 "obj %p target %d offset %d "
218 "read %08x write %08x",
219 obj, reloc->target_handle,
222 reloc->write_domain);
226 target_obj->pending_read_domains |= reloc->read_domains;
227 target_obj->pending_write_domain |= reloc->write_domain;
229 /* If the relocation already has the right value in it, no
230 * more work needs to be done.
232 if (target_offset == reloc->presumed_offset)
235 /* Check that the relocation address is valid... */
236 if (unlikely(reloc->offset > obj->base.size - 4)) {
237 DRM_DEBUG("Relocation beyond object bounds: "
238 "obj %p target %d offset %d size %d.\n",
239 obj, reloc->target_handle,
241 (int) obj->base.size);
244 if (unlikely(reloc->offset & 3)) {
245 DRM_DEBUG("Relocation not 4-byte aligned: "
246 "obj %p target %d offset %d.\n",
247 obj, reloc->target_handle,
248 (int) reloc->offset);
252 /* We can't wait for rendering with pagefaults disabled */
253 if (obj->active && in_atomic())
256 reloc->delta += target_offset;
257 if (use_cpu_reloc(obj)) {
258 uint32_t page_offset = reloc->offset & ~PAGE_MASK;
261 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
265 vaddr = kmap_atomic(i915_gem_object_get_page(obj,
266 reloc->offset >> PAGE_SHIFT));
267 *(uint32_t *)(vaddr + page_offset) = reloc->delta;
268 kunmap_atomic(vaddr);
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 uint32_t __iomem *reloc_entry;
272 void __iomem *reloc_page;
274 ret = i915_gem_object_set_to_gtt_domain(obj, true);
278 ret = i915_gem_object_put_fence(obj);
282 /* Map the page containing the relocation we're going to perform. */
283 reloc->offset += obj->gtt_offset;
284 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
285 reloc->offset & PAGE_MASK);
286 reloc_entry = (uint32_t __iomem *)
287 (reloc_page + (reloc->offset & ~PAGE_MASK));
288 iowrite32(reloc->delta, reloc_entry);
289 io_mapping_unmap_atomic(reloc_page);
292 /* and update the user's relocation entry */
293 reloc->presumed_offset = target_offset;
299 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
300 struct eb_objects *eb)
302 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
303 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
304 struct drm_i915_gem_relocation_entry __user *user_relocs;
305 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
308 user_relocs = to_user_ptr(entry->relocs_ptr);
310 remain = entry->relocation_count;
312 struct drm_i915_gem_relocation_entry *r = stack_reloc;
314 if (count > ARRAY_SIZE(stack_reloc))
315 count = ARRAY_SIZE(stack_reloc);
318 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
322 u64 offset = r->presumed_offset;
324 ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
328 if (r->presumed_offset != offset &&
329 __copy_to_user_inatomic(&user_relocs->presumed_offset,
331 sizeof(r->presumed_offset))) {
345 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
346 struct eb_objects *eb,
347 struct drm_i915_gem_relocation_entry *relocs)
349 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
352 for (i = 0; i < entry->relocation_count; i++) {
353 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
362 i915_gem_execbuffer_relocate(struct eb_objects *eb)
364 struct drm_i915_gem_object *obj;
367 /* This is the fast path and we cannot handle a pagefault whilst
368 * holding the struct mutex lest the user pass in the relocations
369 * contained within a mmaped bo. For in such a case we, the page
370 * fault handler would call i915_gem_fault() and we would try to
371 * acquire the struct mutex again. Obviously this is bad and so
372 * lockdep complains vehemently.
375 list_for_each_entry(obj, &eb->objects, exec_list) {
376 ret = i915_gem_execbuffer_relocate_object(obj, eb);
385 #define __EXEC_OBJECT_HAS_PIN (1<<31)
386 #define __EXEC_OBJECT_HAS_FENCE (1<<30)
389 need_reloc_mappable(struct drm_i915_gem_object *obj)
391 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
392 return entry->relocation_count && !use_cpu_reloc(obj);
396 i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
397 struct intel_ring_buffer *ring,
400 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
401 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
402 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
403 bool need_fence, need_mappable;
407 has_fenced_gpu_access &&
408 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
409 obj->tiling_mode != I915_TILING_NONE;
410 need_mappable = need_fence || need_reloc_mappable(obj);
412 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false);
416 entry->flags |= __EXEC_OBJECT_HAS_PIN;
418 if (has_fenced_gpu_access) {
419 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
420 ret = i915_gem_object_get_fence(obj);
424 if (i915_gem_object_pin_fence(obj))
425 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
427 obj->pending_fenced_gpu_access = true;
431 /* Ensure ppgtt mapping exists if needed */
432 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
433 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
434 obj, obj->cache_level);
436 obj->has_aliasing_ppgtt_mapping = 1;
439 if (entry->offset != obj->gtt_offset) {
440 entry->offset = obj->gtt_offset;
444 if (entry->flags & EXEC_OBJECT_WRITE) {
445 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
446 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
449 if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
450 !obj->has_global_gtt_mapping)
451 i915_gem_gtt_bind_object(obj, obj->cache_level);
457 i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
459 struct drm_i915_gem_exec_object2 *entry;
464 entry = obj->exec_entry;
466 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
467 i915_gem_object_unpin_fence(obj);
469 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
470 i915_gem_object_unpin(obj);
472 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
476 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
477 struct list_head *objects,
480 struct drm_i915_gem_object *obj;
481 struct list_head ordered_objects;
482 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
485 INIT_LIST_HEAD(&ordered_objects);
486 while (!list_empty(objects)) {
487 struct drm_i915_gem_exec_object2 *entry;
488 bool need_fence, need_mappable;
490 obj = list_first_entry(objects,
491 struct drm_i915_gem_object,
493 entry = obj->exec_entry;
496 has_fenced_gpu_access &&
497 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
498 obj->tiling_mode != I915_TILING_NONE;
499 need_mappable = need_fence || need_reloc_mappable(obj);
502 list_move(&obj->exec_list, &ordered_objects);
504 list_move_tail(&obj->exec_list, &ordered_objects);
506 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
507 obj->base.pending_write_domain = 0;
508 obj->pending_fenced_gpu_access = false;
510 list_splice(&ordered_objects, objects);
512 /* Attempt to pin all of the buffers into the GTT.
513 * This is done in 3 phases:
515 * 1a. Unbind all objects that do not match the GTT constraints for
516 * the execbuffer (fenceable, mappable, alignment etc).
517 * 1b. Increment pin count for already bound objects.
518 * 2. Bind new objects.
519 * 3. Decrement pin count.
521 * This avoid unnecessary unbinding of later objects in order to make
522 * room for the earlier objects *unless* we need to defragment.
528 /* Unbind any ill-fitting objects or pin. */
529 list_for_each_entry(obj, objects, exec_list) {
530 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
531 bool need_fence, need_mappable;
537 has_fenced_gpu_access &&
538 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
539 obj->tiling_mode != I915_TILING_NONE;
540 need_mappable = need_fence || need_reloc_mappable(obj);
542 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
543 (need_mappable && !obj->map_and_fenceable))
544 ret = i915_gem_object_unbind(obj);
546 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
551 /* Bind fresh objects */
552 list_for_each_entry(obj, objects, exec_list) {
556 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
561 err: /* Decrement pin count for bound objects */
562 list_for_each_entry(obj, objects, exec_list)
563 i915_gem_execbuffer_unreserve_object(obj);
565 if (ret != -ENOSPC || retry++)
568 ret = i915_gem_evict_everything(ring->dev);
575 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
576 struct drm_i915_gem_execbuffer2 *args,
577 struct drm_file *file,
578 struct intel_ring_buffer *ring,
579 struct eb_objects *eb,
580 struct drm_i915_gem_exec_object2 *exec)
582 struct drm_i915_gem_relocation_entry *reloc;
583 struct drm_i915_gem_object *obj;
587 int count = args->buffer_count;
589 /* We may process another execbuffer during the unlock... */
590 while (!list_empty(&eb->objects)) {
591 obj = list_first_entry(&eb->objects,
592 struct drm_i915_gem_object,
594 list_del_init(&obj->exec_list);
595 drm_gem_object_unreference(&obj->base);
598 mutex_unlock(&dev->struct_mutex);
601 for (i = 0; i < count; i++)
602 total += exec[i].relocation_count;
604 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
605 reloc = drm_malloc_ab(total, sizeof(*reloc));
606 if (reloc == NULL || reloc_offset == NULL) {
607 drm_free_large(reloc);
608 drm_free_large(reloc_offset);
609 mutex_lock(&dev->struct_mutex);
614 for (i = 0; i < count; i++) {
615 struct drm_i915_gem_relocation_entry __user *user_relocs;
616 u64 invalid_offset = (u64)-1;
619 user_relocs = to_user_ptr(exec[i].relocs_ptr);
621 if (copy_from_user(reloc+total, user_relocs,
622 exec[i].relocation_count * sizeof(*reloc))) {
624 mutex_lock(&dev->struct_mutex);
628 /* As we do not update the known relocation offsets after
629 * relocating (due to the complexities in lock handling),
630 * we need to mark them as invalid now so that we force the
631 * relocation processing next time. Just in case the target
632 * object is evicted and then rebound into its old
633 * presumed_offset before the next execbuffer - if that
634 * happened we would make the mistake of assuming that the
635 * relocations were valid.
637 for (j = 0; j < exec[i].relocation_count; j++) {
638 if (copy_to_user(&user_relocs[j].presumed_offset,
640 sizeof(invalid_offset))) {
642 mutex_lock(&dev->struct_mutex);
647 reloc_offset[i] = total;
648 total += exec[i].relocation_count;
651 ret = i915_mutex_lock_interruptible(dev);
653 mutex_lock(&dev->struct_mutex);
657 /* reacquire the objects */
659 ret = eb_lookup_objects(eb, exec, args, file);
663 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
664 ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs);
668 list_for_each_entry(obj, &eb->objects, exec_list) {
669 int offset = obj->exec_entry - exec;
670 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
671 reloc + reloc_offset[offset]);
676 /* Leave the user relocations as are, this is the painfully slow path,
677 * and we want to avoid the complication of dropping the lock whilst
678 * having buffers reserved in the aperture and so causing spurious
679 * ENOSPC for random operations.
683 drm_free_large(reloc);
684 drm_free_large(reloc_offset);
689 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
690 struct list_head *objects)
692 struct drm_i915_gem_object *obj;
693 uint32_t flush_domains = 0;
696 list_for_each_entry(obj, objects, exec_list) {
697 ret = i915_gem_object_sync(obj, ring);
701 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
702 i915_gem_clflush_object(obj);
704 flush_domains |= obj->base.write_domain;
707 if (flush_domains & I915_GEM_DOMAIN_CPU)
708 i915_gem_chipset_flush(ring->dev);
710 if (flush_domains & I915_GEM_DOMAIN_GTT)
713 /* Unconditionally invalidate gpu caches and ensure that we do flush
714 * any residual writes from the previous batch.
716 return intel_ring_invalidate_all_caches(ring);
720 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
722 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
725 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
729 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
734 for (i = 0; i < count; i++) {
735 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
736 int length; /* limited by fault_in_pages_readable() */
738 if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
741 /* First check for malicious input causing overflow */
742 if (exec[i].relocation_count >
743 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
746 length = exec[i].relocation_count *
747 sizeof(struct drm_i915_gem_relocation_entry);
749 * We must check that the entire relocation array is safe
750 * to read, but since we may need to update the presumed
751 * offsets during execution, check for full write access.
753 if (!access_ok(VERIFY_WRITE, ptr, length))
756 if (fault_in_multipages_readable(ptr, length))
764 i915_gem_execbuffer_move_to_active(struct list_head *objects,
765 struct intel_ring_buffer *ring)
767 struct drm_i915_gem_object *obj;
769 list_for_each_entry(obj, objects, exec_list) {
770 u32 old_read = obj->base.read_domains;
771 u32 old_write = obj->base.write_domain;
773 obj->base.write_domain = obj->base.pending_write_domain;
774 if (obj->base.write_domain == 0)
775 obj->base.pending_read_domains |= obj->base.read_domains;
776 obj->base.read_domains = obj->base.pending_read_domains;
777 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
779 i915_gem_object_move_to_active(obj, ring);
780 if (obj->base.write_domain) {
782 obj->last_write_seqno = intel_ring_get_seqno(ring);
783 if (obj->pin_count) /* check for potential scanout */
784 intel_mark_fb_busy(obj);
787 trace_i915_gem_object_change_domain(obj, old_read, old_write);
792 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
793 struct drm_file *file,
794 struct intel_ring_buffer *ring)
796 /* Unconditionally force add_request to emit a full flush. */
797 ring->gpu_caches_dirty = true;
799 /* Add a breadcrumb for the completion of the batch buffer */
800 (void)i915_add_request(ring, file, NULL);
804 i915_reset_gen7_sol_offsets(struct drm_device *dev,
805 struct intel_ring_buffer *ring)
807 drm_i915_private_t *dev_priv = dev->dev_private;
810 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
813 ret = intel_ring_begin(ring, 4 * 3);
817 for (i = 0; i < 4; i++) {
818 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
819 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
820 intel_ring_emit(ring, 0);
823 intel_ring_advance(ring);
829 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
830 struct drm_file *file,
831 struct drm_i915_gem_execbuffer2 *args,
832 struct drm_i915_gem_exec_object2 *exec)
834 drm_i915_private_t *dev_priv = dev->dev_private;
835 struct eb_objects *eb;
836 struct drm_i915_gem_object *batch_obj;
837 struct drm_clip_rect *cliprects = NULL;
838 struct intel_ring_buffer *ring;
839 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
840 u32 exec_start, exec_len;
845 if (!i915_gem_check_execbuffer(args))
848 ret = validate_exec_list(exec, args->buffer_count);
853 if (args->flags & I915_EXEC_SECURE) {
854 if (!file->is_master || !capable(CAP_SYS_ADMIN))
857 flags |= I915_DISPATCH_SECURE;
859 if (args->flags & I915_EXEC_IS_PINNED)
860 flags |= I915_DISPATCH_PINNED;
862 switch (args->flags & I915_EXEC_RING_MASK) {
863 case I915_EXEC_DEFAULT:
864 case I915_EXEC_RENDER:
865 ring = &dev_priv->ring[RCS];
868 ring = &dev_priv->ring[VCS];
870 DRM_DEBUG("Ring %s doesn't support contexts\n",
876 ring = &dev_priv->ring[BCS];
878 DRM_DEBUG("Ring %s doesn't support contexts\n",
884 DRM_DEBUG("execbuf with unknown ring: %d\n",
885 (int)(args->flags & I915_EXEC_RING_MASK));
888 if (!intel_ring_initialized(ring)) {
889 DRM_DEBUG("execbuf with invalid ring: %d\n",
890 (int)(args->flags & I915_EXEC_RING_MASK));
894 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
895 mask = I915_EXEC_CONSTANTS_MASK;
897 case I915_EXEC_CONSTANTS_REL_GENERAL:
898 case I915_EXEC_CONSTANTS_ABSOLUTE:
899 case I915_EXEC_CONSTANTS_REL_SURFACE:
900 if (ring == &dev_priv->ring[RCS] &&
901 mode != dev_priv->relative_constants_mode) {
902 if (INTEL_INFO(dev)->gen < 4)
905 if (INTEL_INFO(dev)->gen > 5 &&
906 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
909 /* The HW changed the meaning on this bit on gen6 */
910 if (INTEL_INFO(dev)->gen >= 6)
911 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
915 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
919 if (args->buffer_count < 1) {
920 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
924 if (args->num_cliprects != 0) {
925 if (ring != &dev_priv->ring[RCS]) {
926 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
930 if (INTEL_INFO(dev)->gen >= 5) {
931 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
935 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
936 DRM_DEBUG("execbuf with %u cliprects\n",
937 args->num_cliprects);
941 cliprects = kmalloc(args->num_cliprects * sizeof(*cliprects),
943 if (cliprects == NULL) {
948 if (copy_from_user(cliprects,
949 to_user_ptr(args->cliprects_ptr),
950 sizeof(*cliprects)*args->num_cliprects)) {
956 ret = i915_mutex_lock_interruptible(dev);
960 if (dev_priv->mm.suspended) {
961 mutex_unlock(&dev->struct_mutex);
966 eb = eb_create(args);
968 mutex_unlock(&dev->struct_mutex);
973 /* Look up object handles */
974 ret = eb_lookup_objects(eb, exec, args, file);
978 /* take note of the batch buffer before we might reorder the lists */
979 batch_obj = list_entry(eb->objects.prev,
980 struct drm_i915_gem_object,
983 /* Move the objects en-masse into the GTT, evicting if necessary. */
984 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
985 ret = i915_gem_execbuffer_reserve(ring, &eb->objects, &need_relocs);
989 /* The objects are in their final locations, apply the relocations. */
991 ret = i915_gem_execbuffer_relocate(eb);
993 if (ret == -EFAULT) {
994 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
996 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1002 /* Set the pending read domains for the batch buffer to COMMAND */
1003 if (batch_obj->base.pending_write_domain) {
1004 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1008 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1010 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1011 * batch" bit. Hence we need to pin secure batches into the global gtt.
1012 * hsw should have this fixed, but let's be paranoid and do it
1013 * unconditionally for now. */
1014 if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
1015 i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
1017 ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects);
1021 ret = i915_switch_context(ring, file, ctx_id);
1025 if (ring == &dev_priv->ring[RCS] &&
1026 mode != dev_priv->relative_constants_mode) {
1027 ret = intel_ring_begin(ring, 4);
1031 intel_ring_emit(ring, MI_NOOP);
1032 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
1033 intel_ring_emit(ring, INSTPM);
1034 intel_ring_emit(ring, mask << 16 | mode);
1035 intel_ring_advance(ring);
1037 dev_priv->relative_constants_mode = mode;
1040 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1041 ret = i915_reset_gen7_sol_offsets(dev, ring);
1046 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1047 exec_len = args->batch_len;
1049 for (i = 0; i < args->num_cliprects; i++) {
1050 ret = i915_emit_box(dev, &cliprects[i],
1051 args->DR1, args->DR4);
1055 ret = ring->dispatch_execbuffer(ring,
1056 exec_start, exec_len,
1062 ret = ring->dispatch_execbuffer(ring,
1063 exec_start, exec_len,
1069 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
1071 i915_gem_execbuffer_move_to_active(&eb->objects, ring);
1072 i915_gem_execbuffer_retire_commands(dev, file, ring);
1077 mutex_unlock(&dev->struct_mutex);
1085 * Legacy execbuffer just creates an exec2 list from the original exec object
1086 * list array and passes it to the real function.
1089 i915_gem_execbuffer(struct drm_device *dev, void *data,
1090 struct drm_file *file)
1092 struct drm_i915_gem_execbuffer *args = data;
1093 struct drm_i915_gem_execbuffer2 exec2;
1094 struct drm_i915_gem_exec_object *exec_list = NULL;
1095 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1098 if (args->buffer_count < 1) {
1099 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1103 /* Copy in the exec list from userland */
1104 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1105 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1106 if (exec_list == NULL || exec2_list == NULL) {
1107 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1108 args->buffer_count);
1109 drm_free_large(exec_list);
1110 drm_free_large(exec2_list);
1113 ret = copy_from_user(exec_list,
1114 to_user_ptr(args->buffers_ptr),
1115 sizeof(*exec_list) * args->buffer_count);
1117 DRM_DEBUG("copy %d exec entries failed %d\n",
1118 args->buffer_count, ret);
1119 drm_free_large(exec_list);
1120 drm_free_large(exec2_list);
1124 for (i = 0; i < args->buffer_count; i++) {
1125 exec2_list[i].handle = exec_list[i].handle;
1126 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1127 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1128 exec2_list[i].alignment = exec_list[i].alignment;
1129 exec2_list[i].offset = exec_list[i].offset;
1130 if (INTEL_INFO(dev)->gen < 4)
1131 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1133 exec2_list[i].flags = 0;
1136 exec2.buffers_ptr = args->buffers_ptr;
1137 exec2.buffer_count = args->buffer_count;
1138 exec2.batch_start_offset = args->batch_start_offset;
1139 exec2.batch_len = args->batch_len;
1140 exec2.DR1 = args->DR1;
1141 exec2.DR4 = args->DR4;
1142 exec2.num_cliprects = args->num_cliprects;
1143 exec2.cliprects_ptr = args->cliprects_ptr;
1144 exec2.flags = I915_EXEC_RENDER;
1145 i915_execbuffer2_set_context_id(exec2, 0);
1147 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1149 /* Copy the new buffer offsets back to the user's exec list. */
1150 for (i = 0; i < args->buffer_count; i++)
1151 exec_list[i].offset = exec2_list[i].offset;
1152 /* ... and back out to userspace */
1153 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1155 sizeof(*exec_list) * args->buffer_count);
1158 DRM_DEBUG("failed to copy %d exec entries "
1159 "back to user (%d)\n",
1160 args->buffer_count, ret);
1164 drm_free_large(exec_list);
1165 drm_free_large(exec2_list);
1170 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1171 struct drm_file *file)
1173 struct drm_i915_gem_execbuffer2 *args = data;
1174 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1177 if (args->buffer_count < 1 ||
1178 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1179 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1183 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1184 GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
1185 if (exec2_list == NULL)
1186 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
1187 args->buffer_count);
1188 if (exec2_list == NULL) {
1189 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1190 args->buffer_count);
1193 ret = copy_from_user(exec2_list,
1194 to_user_ptr(args->buffers_ptr),
1195 sizeof(*exec2_list) * args->buffer_count);
1197 DRM_DEBUG("copy %d exec entries failed %d\n",
1198 args->buffer_count, ret);
1199 drm_free_large(exec2_list);
1203 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1205 /* Copy the new buffer offsets back to the user's exec list. */
1206 ret = copy_to_user(to_user_ptr(args->buffers_ptr),
1208 sizeof(*exec2_list) * args->buffer_count);
1211 DRM_DEBUG("failed to copy %d exec entries "
1212 "back to user (%d)\n",
1213 args->buffer_count, ret);
1217 drm_free_large(exec2_list);