drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  56 {
  57         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  58
  59         return intel_dig_port->base.base.dev;
  60 }
  61
  62 /**
  63  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  64  * @intel_dp: DP struct
  65  *
  66  * Returns true if the given DP struct corresponds to a CPU eDP port.
  67  */
  68 static bool is_cpu_edp(struct intel_dp *intel_dp)
  69 {
  70         struct drm_device *dev = intel_dp_to_dev(intel_dp);
  71         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  72         enum port port = intel_dig_port->port;
  73
  74         return is_edp(intel_dp) &&
  75                 (port == PORT_A || (port == PORT_C && IS_VALLEYVIEW(dev)));
  76 }
  77
  78 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  79 {
  80         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  81 }
  82
  83 static void intel_dp_link_down(struct intel_dp *intel_dp);
  84
  85 static int
  86 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  87 {
  88         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  89
  90         switch (max_link_bw) {
  91         case DP_LINK_BW_1_62:
  92         case DP_LINK_BW_2_7:
  93                 break;
  94         default:
  95                 max_link_bw = DP_LINK_BW_1_62;
  96                 break;
  97         }
  98         return max_link_bw;
  99 }
 100
 101 /*
 102  * The units on the numbers in the next two are... bizarre.  Examples will
 103  * make it clearer; this one parallels an example in the eDP spec.
 104  *
 105  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 106  *
 107  *     270000 * 1 * 8 / 10 == 216000
 108  *
 109  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 110  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 111  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 112  * 119000.  At 18bpp that's 2142000 kilobits per second.
 113  *
 114  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 115  * get the result in decakilobits instead of kilobits.
 116  */
 117
 118 static int
 119 intel_dp_link_required(int pixel_clock, int bpp)
 120 {
 121         return (pixel_clock * bpp + 9) / 10;
 122 }
 123
 124 static int
 125 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 126 {
 127         return (max_link_clock * max_lanes * 8) / 10;
 128 }
 129
 130 static int
 131 intel_dp_mode_valid(struct drm_connector *connector,
 132                     struct drm_display_mode *mode)
 133 {
 134         struct intel_dp *intel_dp = intel_attached_dp(connector);
 135         struct intel_connector *intel_connector = to_intel_connector(connector);
 136         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 137         int target_clock = mode->clock;
 138         int max_rate, mode_rate, max_lanes, max_link_clock;
 139
 140         if (is_edp(intel_dp) && fixed_mode) {
 141                 if (mode->hdisplay > fixed_mode->hdisplay)
 142                         return MODE_PANEL;
 143
 144                 if (mode->vdisplay > fixed_mode->vdisplay)
 145                         return MODE_PANEL;
 146
 147                 target_clock = fixed_mode->clock;
 148         }
 149
 150         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 151         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 152
 153         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 154         mode_rate = intel_dp_link_required(target_clock, 18);
 155
 156         if (mode_rate > max_rate)
 157                 return MODE_CLOCK_HIGH;
 158
 159         if (mode->clock < 10000)
 160                 return MODE_CLOCK_LOW;
 161
 162         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 163                 return MODE_H_ILLEGAL;
 164
 165         return MODE_OK;
 166 }
 167
 168 static uint32_t
 169 pack_aux(uint8_t *src, int src_bytes)
 170 {
 171         int     i;
 172         uint32_t v = 0;
 173
 174         if (src_bytes > 4)
 175                 src_bytes = 4;
 176         for (i = 0; i < src_bytes; i++)
 177                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 178         return v;
 179 }
 180
 181 static void
 182 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 183 {
 184         int i;
 185         if (dst_bytes > 4)
 186                 dst_bytes = 4;
 187         for (i = 0; i < dst_bytes; i++)
 188                 dst[i] = src >> ((3-i) * 8);
 189 }
 190
 191 /* hrawclock is 1/4 the FSB frequency */
 192 static int
 193 intel_hrawclk(struct drm_device *dev)
 194 {
 195         struct drm_i915_private *dev_priv = dev->dev_private;
 196         uint32_t clkcfg;
 197
 198         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 199         if (IS_VALLEYVIEW(dev))
 200                 return 200;
 201
 202         clkcfg = I915_READ(CLKCFG);
 203         switch (clkcfg & CLKCFG_FSB_MASK) {
 204         case CLKCFG_FSB_400:
 205                 return 100;
 206         case CLKCFG_FSB_533:
 207                 return 133;
 208         case CLKCFG_FSB_667:
 209                 return 166;
 210         case CLKCFG_FSB_800:
 211                 return 200;
 212         case CLKCFG_FSB_1067:
 213                 return 266;
 214         case CLKCFG_FSB_1333:
 215                 return 333;
 216         /* these two are just a guess; one of them might be right */
 217         case CLKCFG_FSB_1600:
 218         case CLKCFG_FSB_1600_ALT:
 219                 return 400;
 220         default:
 221                 return 133;
 222         }
 223 }
 224
 225 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 226 {
 227         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         u32 pp_stat_reg;
 230
 231         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 232         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 233 }
 234
 235 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 236 {
 237         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         u32 pp_ctrl_reg;
 240
 241         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 242         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 243 }
 244
 245 static void
 246 intel_dp_check_edp(struct intel_dp *intel_dp)
 247 {
 248         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250         u32 pp_stat_reg, pp_ctrl_reg;
 251
 252         if (!is_edp(intel_dp))
 253                 return;
 254
 255         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 256         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 257
 258         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 259                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 260                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 261                                 I915_READ(pp_stat_reg),
 262                                 I915_READ(pp_ctrl_reg));
 263         }
 264 }
 265
 266 static uint32_t
 267 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 268 {
 269         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 270         struct drm_device *dev = intel_dig_port->base.base.dev;
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 273         uint32_t status;
 274         bool done;
 275
 276 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 277         if (has_aux_irq)
 278                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 279                                           msecs_to_jiffies(10));
 280         else
 281                 done = wait_for_atomic(C, 10) == 0;
 282         if (!done)
 283                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 284                           has_aux_irq);
 285 #undef C
 286
 287         return status;
 288 }
 289
 290 static int
 291 intel_dp_aux_ch(struct intel_dp *intel_dp,
 292                 uint8_t *send, int send_bytes,
 293                 uint8_t *recv, int recv_size)
 294 {
 295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 296         struct drm_device *dev = intel_dig_port->base.base.dev;
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 299         uint32_t ch_data = ch_ctl + 4;
 300         int i, ret, recv_bytes;
 301         uint32_t status;
 302         uint32_t aux_clock_divider;
 303         int try, precharge;
 304         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 305
 306         /* dp aux is extremely sensitive to irq latency, hence request the
 307          * lowest possible wakeup latency and so prevent the cpu from going into
 308          * deep sleep states.
 309          */
 310         pm_qos_update_request(&dev_priv->pm_qos, 0);
 311
 312         intel_dp_check_edp(intel_dp);
 313         /* The clock divider is based off the hrawclk,
 314          * and would like to run at 2MHz. So, take the
 315          * hrawclk value and divide by 2 and use that
 316          *
 317          * Note that PCH attached eDP panels should use a 125MHz input
 318          * clock divider.
 319          */
 320         if (is_cpu_edp(intel_dp)) {
 321                 if (HAS_DDI(dev))
 322                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 323                 else if (IS_VALLEYVIEW(dev))
 324                         aux_clock_divider = 100;
 325                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 326                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 327                 else
 328                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 329         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 330                 /* Workaround for non-ULT HSW */
 331                 aux_clock_divider = 74;
 332         } else if (HAS_PCH_SPLIT(dev)) {
 333                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 334         } else {
 335                 aux_clock_divider = intel_hrawclk(dev) / 2;
 336         }
 337
 338         if (IS_GEN6(dev))
 339                 precharge = 3;
 340         else
 341                 precharge = 5;
 342
 343         /* Try to wait for any previous AUX channel activity */
 344         for (try = 0; try < 3; try++) {
 345                 status = I915_READ_NOTRACE(ch_ctl);
 346                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 347                         break;
 348                 msleep(1);
 349         }
 350
 351         if (try == 3) {
 352                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 353                      I915_READ(ch_ctl));
 354                 ret = -EBUSY;
 355                 goto out;
 356         }
 357
 358         /* Must try at least 3 times according to DP spec */
 359         for (try = 0; try < 5; try++) {
 360                 /* Load the send data into the aux channel data registers */
 361                 for (i = 0; i < send_bytes; i += 4)
 362                         I915_WRITE(ch_data + i,
 363                                    pack_aux(send + i, send_bytes - i));
 364
 365                 /* Send the command and wait for it to complete */
 366                 I915_WRITE(ch_ctl,
 367                            DP_AUX_CH_CTL_SEND_BUSY |
 368                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 369                            DP_AUX_CH_CTL_TIME_OUT_400us |
 370                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 371                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 372                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 373                            DP_AUX_CH_CTL_DONE |
 374                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 375                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 376
 377                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 378
 379                 /* Clear done status and any errors */
 380                 I915_WRITE(ch_ctl,
 381                            status |
 382                            DP_AUX_CH_CTL_DONE |
 383                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 384                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 385
 386                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 387                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 388                         continue;
 389                 if (status & DP_AUX_CH_CTL_DONE)
 390                         break;
 391         }
 392
 393         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 394                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 395                 ret = -EBUSY;
 396                 goto out;
 397         }
 398
 399         /* Check for timeout or receive error.
 400          * Timeouts occur when the sink is not connected
 401          */
 402         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 403                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 404                 ret = -EIO;
 405                 goto out;
 406         }
 407
 408         /* Timeouts occur when the device isn't connected, so they're
 409          * "normal" -- don't fill the kernel log with these */
 410         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 411                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 412                 ret = -ETIMEDOUT;
 413                 goto out;
 414         }
 415
 416         /* Unload any bytes sent back from the other side */
 417         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 418                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 419         if (recv_bytes > recv_size)
 420                 recv_bytes = recv_size;
 421
 422         for (i = 0; i < recv_bytes; i += 4)
 423                 unpack_aux(I915_READ(ch_data + i),
 424                            recv + i, recv_bytes - i);
 425
 426         ret = recv_bytes;
 427 out:
 428         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 429
 430         return ret;
 431 }
 432
 433 /* Write data to the aux channel in native mode */
 434 static int
 435 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 436                           uint16_t address, uint8_t *send, int send_bytes)
 437 {
 438         int ret;
 439         uint8_t msg[20];
 440         int msg_bytes;
 441         uint8_t ack;
 442
 443         intel_dp_check_edp(intel_dp);
 444         if (send_bytes > 16)
 445                 return -1;
 446         msg[0] = AUX_NATIVE_WRITE << 4;
 447         msg[1] = address >> 8;
 448         msg[2] = address & 0xff;
 449         msg[3] = send_bytes - 1;
 450         memcpy(&msg[4], send, send_bytes);
 451         msg_bytes = send_bytes + 4;
 452         for (;;) {
 453                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 454                 if (ret < 0)
 455                         return ret;
 456                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 457                         break;
 458                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 459                         udelay(100);
 460                 else
 461                         return -EIO;
 462         }
 463         return send_bytes;
 464 }
 465
 466 /* Write a single byte to the aux channel in native mode */
 467 static int
 468 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 469                             uint16_t address, uint8_t byte)
 470 {
 471         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 472 }
 473
 474 /* read bytes from a native aux channel */
 475 static int
 476 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 477                          uint16_t address, uint8_t *recv, int recv_bytes)
 478 {
 479         uint8_t msg[4];
 480         int msg_bytes;
 481         uint8_t reply[20];
 482         int reply_bytes;
 483         uint8_t ack;
 484         int ret;
 485
 486         intel_dp_check_edp(intel_dp);
 487         msg[0] = AUX_NATIVE_READ << 4;
 488         msg[1] = address >> 8;
 489         msg[2] = address & 0xff;
 490         msg[3] = recv_bytes - 1;
 491
 492         msg_bytes = 4;
 493         reply_bytes = recv_bytes + 1;
 494
 495         for (;;) {
 496                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 497                                       reply, reply_bytes);
 498                 if (ret == 0)
 499                         return -EPROTO;
 500                 if (ret < 0)
 501                         return ret;
 502                 ack = reply[0];
 503                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 504                         memcpy(recv, reply + 1, ret - 1);
 505                         return ret - 1;
 506                 }
 507                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 508                         udelay(100);
 509                 else
 510                         return -EIO;
 511         }
 512 }
 513
 514 static int
 515 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 516                     uint8_t write_byte, uint8_t *read_byte)
 517 {
 518         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 519         struct intel_dp *intel_dp = container_of(adapter,
 520                                                 struct intel_dp,
 521                                                 adapter);
 522         uint16_t address = algo_data->address;
 523         uint8_t msg[5];
 524         uint8_t reply[2];
 525         unsigned retry;
 526         int msg_bytes;
 527         int reply_bytes;
 528         int ret;
 529
 530         intel_dp_check_edp(intel_dp);
 531         /* Set up the command byte */
 532         if (mode & MODE_I2C_READ)
 533                 msg[0] = AUX_I2C_READ << 4;
 534         else
 535                 msg[0] = AUX_I2C_WRITE << 4;
 536
 537         if (!(mode & MODE_I2C_STOP))
 538                 msg[0] |= AUX_I2C_MOT << 4;
 539
 540         msg[1] = address >> 8;
 541         msg[2] = address;
 542
 543         switch (mode) {
 544         case MODE_I2C_WRITE:
 545                 msg[3] = 0;
 546                 msg[4] = write_byte;
 547                 msg_bytes = 5;
 548                 reply_bytes = 1;
 549                 break;
 550         case MODE_I2C_READ:
 551                 msg[3] = 0;
 552                 msg_bytes = 4;
 553                 reply_bytes = 2;
 554                 break;
 555         default:
 556                 msg_bytes = 3;
 557                 reply_bytes = 1;
 558                 break;
 559         }
 560
 561         for (retry = 0; retry < 5; retry++) {
 562                 ret = intel_dp_aux_ch(intel_dp,
 563                                       msg, msg_bytes,
 564                                       reply, reply_bytes);
 565                 if (ret < 0) {
 566                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 567                         return ret;
 568                 }
 569
 570                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 571                 case AUX_NATIVE_REPLY_ACK:
 572                         /* I2C-over-AUX Reply field is only valid
 573                          * when paired with AUX ACK.
 574                          */
 575                         break;
 576                 case AUX_NATIVE_REPLY_NACK:
 577                         DRM_DEBUG_KMS("aux_ch native nack\n");
 578                         return -EREMOTEIO;
 579                 case AUX_NATIVE_REPLY_DEFER:
 580                         udelay(100);
 581                         continue;
 582                 default:
 583                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 584                                   reply[0]);
 585                         return -EREMOTEIO;
 586                 }
 587
 588                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 589                 case AUX_I2C_REPLY_ACK:
 590                         if (mode == MODE_I2C_READ) {
 591                                 *read_byte = reply[1];
 592                         }
 593                         return reply_bytes - 1;
 594                 case AUX_I2C_REPLY_NACK:
 595                         DRM_DEBUG_KMS("aux_i2c nack\n");
 596                         return -EREMOTEIO;
 597                 case AUX_I2C_REPLY_DEFER:
 598                         DRM_DEBUG_KMS("aux_i2c defer\n");
 599                         udelay(100);
 600                         break;
 601                 default:
 602                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 603                         return -EREMOTEIO;
 604                 }
 605         }
 606
 607         DRM_ERROR("too many retries, giving up\n");
 608         return -EREMOTEIO;
 609 }
 610
 611 static int
 612 intel_dp_i2c_init(struct intel_dp *intel_dp,
 613                   struct intel_connector *intel_connector, const char *name)
 614 {
 615         int     ret;
 616
 617         DRM_DEBUG_KMS("i2c_init %s\n", name);
 618         intel_dp->algo.running = false;
 619         intel_dp->algo.address = 0;
 620         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 621
 622         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 623         intel_dp->adapter.owner = THIS_MODULE;
 624         intel_dp->adapter.class = I2C_CLASS_DDC;
 625         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 626         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 627         intel_dp->adapter.algo_data = &intel_dp->algo;
 628         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 629
 630         ironlake_edp_panel_vdd_on(intel_dp);
 631         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 632         ironlake_edp_panel_vdd_off(intel_dp, false);
 633         return ret;
 634 }
 635
 636 static void
 637 intel_dp_set_clock(struct intel_encoder *encoder,
 638                    struct intel_crtc_config *pipe_config, int link_bw)
 639 {
 640         struct drm_device *dev = encoder->base.dev;
 641
 642         if (IS_G4X(dev)) {
 643                 if (link_bw == DP_LINK_BW_1_62) {
 644                         pipe_config->dpll.p1 = 2;
 645                         pipe_config->dpll.p2 = 10;
 646                         pipe_config->dpll.n = 2;
 647                         pipe_config->dpll.m1 = 23;
 648                         pipe_config->dpll.m2 = 8;
 649                 } else {
 650                         pipe_config->dpll.p1 = 1;
 651                         pipe_config->dpll.p2 = 10;
 652                         pipe_config->dpll.n = 1;
 653                         pipe_config->dpll.m1 = 14;
 654                         pipe_config->dpll.m2 = 2;
 655                 }
 656                 pipe_config->clock_set = true;
 657         } else if (IS_HASWELL(dev)) {
 658                 /* Haswell has special-purpose DP DDI clocks. */
 659         } else if (HAS_PCH_SPLIT(dev)) {
 660                 if (link_bw == DP_LINK_BW_1_62) {
 661                         pipe_config->dpll.n = 1;
 662                         pipe_config->dpll.p1 = 2;
 663                         pipe_config->dpll.p2 = 10;
 664                         pipe_config->dpll.m1 = 12;
 665                         pipe_config->dpll.m2 = 9;
 666                 } else {
 667                         pipe_config->dpll.n = 2;
 668                         pipe_config->dpll.p1 = 1;
 669                         pipe_config->dpll.p2 = 10;
 670                         pipe_config->dpll.m1 = 14;
 671                         pipe_config->dpll.m2 = 8;
 672                 }
 673                 pipe_config->clock_set = true;
 674         } else if (IS_VALLEYVIEW(dev)) {
 675                 /* FIXME: Need to figure out optimized DP clocks for vlv. */
 676         }
 677 }
 678
 679 bool
 680 intel_dp_compute_config(struct intel_encoder *encoder,
 681                         struct intel_crtc_config *pipe_config)
 682 {
 683         struct drm_device *dev = encoder->base.dev;
 684         struct drm_i915_private *dev_priv = dev->dev_private;
 685         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 686         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 687         struct intel_crtc *intel_crtc = encoder->new_crtc;
 688         struct intel_connector *intel_connector = intel_dp->attached_connector;
 689         int lane_count, clock;
 690         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 691         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 692         int bpp, mode_rate;
 693         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 694         int target_clock, link_avail, link_clock;
 695
 696         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
 697                 pipe_config->has_pch_encoder = true;
 698
 699         pipe_config->has_dp_encoder = true;
 700
 701         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 702                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 703                                        adjusted_mode);
 704                 if (!HAS_PCH_SPLIT(dev))
 705                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 706                                                  intel_connector->panel.fitting_mode);
 707                 else
 708                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 709                                                 intel_connector->panel.fitting_mode);
 710         }
 711         /* We need to take the panel's fixed mode into account. */
 712         target_clock = adjusted_mode->clock;
 713
 714         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 715                 return false;
 716
 717         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 718                       "max bw %02x pixel clock %iKHz\n",
 719                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 720
 721         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 722          * bpc in between. */
 723         bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
 724         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
 725                 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
 726
 727         for (; bpp >= 6*3; bpp -= 2*3) {
 728                 mode_rate = intel_dp_link_required(target_clock, bpp);
 729
 730                 for (clock = 0; clock <= max_clock; clock++) {
 731                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 732                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 733                                 link_avail = intel_dp_max_data_rate(link_clock,
 734                                                                     lane_count);
 735
 736                                 if (mode_rate <= link_avail) {
 737                                         goto found;
 738                                 }
 739                         }
 740                 }
 741         }
 742
 743         return false;
 744
 745 found:
 746         if (intel_dp->color_range_auto) {
 747                 /*
 748                  * See:
 749                  * CEA-861-E - 5.1 Default Encoding Parameters
 750                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 751                  */
 752                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 753                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 754                 else
 755                         intel_dp->color_range = 0;
 756         }
 757
 758         if (intel_dp->color_range)
 759                 pipe_config->limited_color_range = true;
 760
 761         intel_dp->link_bw = bws[clock];
 762         intel_dp->lane_count = lane_count;
 763         adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 764         pipe_config->pipe_bpp = bpp;
 765         pipe_config->pixel_target_clock = target_clock;
 766
 767         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 768                       intel_dp->link_bw, intel_dp->lane_count,
 769                       adjusted_mode->clock, bpp);
 770         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 771                       mode_rate, link_avail);
 772
 773         intel_link_compute_m_n(bpp, lane_count,
 774                                target_clock, adjusted_mode->clock,
 775                                &pipe_config->dp_m_n);
 776
 777         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 778
 779         return true;
 780 }
 781
 782 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 783 {
 784         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 785         intel_dp->link_configuration[0] = intel_dp->link_bw;
 786         intel_dp->link_configuration[1] = intel_dp->lane_count;
 787         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 788         /*
 789          * Check for DPCD version > 1.1 and enhanced framing support
 790          */
 791         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 792             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 793                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 794         }
 795 }
 796
 797 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 798 {
 799         struct drm_device *dev = crtc->dev;
 800         struct drm_i915_private *dev_priv = dev->dev_private;
 801         u32 dpa_ctl;
 802
 803         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 804         dpa_ctl = I915_READ(DP_A);
 805         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 806
 807         if (clock < 200000) {
 808                 /* For a long time we've carried around a ILK-DevA w/a for the
 809                  * 160MHz clock. If we're really unlucky, it's still required.
 810                  */
 811                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 812                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 813         } else {
 814                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 815         }
 816
 817         I915_WRITE(DP_A, dpa_ctl);
 818
 819         POSTING_READ(DP_A);
 820         udelay(500);
 821 }
 822
 823 static void
 824 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 825                   struct drm_display_mode *adjusted_mode)
 826 {
 827         struct drm_device *dev = encoder->dev;
 828         struct drm_i915_private *dev_priv = dev->dev_private;
 829         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 830         struct drm_crtc *crtc = encoder->crtc;
 831         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 832
 833         /*
 834          * There are four kinds of DP registers:
 835          *
 836          *      IBX PCH
 837          *      SNB CPU
 838          *      IVB CPU
 839          *      CPT PCH
 840          *
 841          * IBX PCH and CPU are the same for almost everything,
 842          * except that the CPU DP PLL is configured in this
 843          * register
 844          *
 845          * CPT PCH is quite different, having many bits moved
 846          * to the TRANS_DP_CTL register instead. That
 847          * configuration happens (oddly) in ironlake_pch_enable
 848          */
 849
 850         /* Preserve the BIOS-computed detected bit. This is
 851          * supposed to be read-only.
 852          */
 853         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 854
 855         /* Handle DP bits in common between all three register formats */
 856         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 857         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 858
 859         if (intel_dp->has_audio) {
 860                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 861                                  pipe_name(intel_crtc->pipe));
 862                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 863                 intel_write_eld(encoder, adjusted_mode);
 864         }
 865
 866         intel_dp_init_link_config(intel_dp);
 867
 868         /* Split out the IBX/CPU vs CPT settings */
 869
 870         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 871                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 872                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 873                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 874                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 875                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 876
 877                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 878                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 879
 880                 intel_dp->DP |= intel_crtc->pipe << 29;
 881
 882                 /* don't miss out required setting for eDP */
 883                 if (adjusted_mode->clock < 200000)
 884                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 885                 else
 886                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 887         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 888                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 889                         intel_dp->DP |= intel_dp->color_range;
 890
 891                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 892                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 893                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 894                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 895                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 896
 897                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 898                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 899
 900                 if (intel_crtc->pipe == 1)
 901                         intel_dp->DP |= DP_PIPEB_SELECT;
 902
 903                 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
 904                         /* don't miss out required setting for eDP */
 905                         if (adjusted_mode->clock < 200000)
 906                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 907                         else
 908                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 909                 }
 910         } else {
 911                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 912         }
 913
 914         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 915                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 916 }
 917
 918 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 919 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 920
 921 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 922 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 923
 924 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 925 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 926
 927 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 928                                        u32 mask,
 929                                        u32 value)
 930 {
 931         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 pp_stat_reg, pp_ctrl_reg;
 934
 935         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 936         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 937
 938         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 939                         mask, value,
 940                         I915_READ(pp_stat_reg),
 941                         I915_READ(pp_ctrl_reg));
 942
 943         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 944                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 945                                 I915_READ(pp_stat_reg),
 946                                 I915_READ(pp_ctrl_reg));
 947         }
 948 }
 949
 950 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 951 {
 952         DRM_DEBUG_KMS("Wait for panel power on\n");
 953         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 954 }
 955
 956 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 957 {
 958         DRM_DEBUG_KMS("Wait for panel power off time\n");
 959         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 960 }
 961
 962 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 963 {
 964         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 965         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 966 }
 967
 968
 969 /* Read the current pp_control value, unlocking the register if it
 970  * is locked
 971  */
 972
 973 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 974 {
 975         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 976         struct drm_i915_private *dev_priv = dev->dev_private;
 977         u32 control;
 978         u32 pp_ctrl_reg;
 979
 980         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 981         control = I915_READ(pp_ctrl_reg);
 982
 983         control &= ~PANEL_UNLOCK_MASK;
 984         control |= PANEL_UNLOCK_REGS;
 985         return control;
 986 }
 987
 988 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 989 {
 990         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 991         struct drm_i915_private *dev_priv = dev->dev_private;
 992         u32 pp;
 993         u32 pp_stat_reg, pp_ctrl_reg;
 994
 995         if (!is_edp(intel_dp))
 996                 return;
 997         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 998
 999         WARN(intel_dp->want_panel_vdd,
1000              "eDP VDD already requested on\n");
1001
1002         intel_dp->want_panel_vdd = true;
1003
1004         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1005                 DRM_DEBUG_KMS("eDP VDD already on\n");
1006                 return;
1007         }
1008
1009         if (!ironlake_edp_have_panel_power(intel_dp))
1010                 ironlake_wait_panel_power_cycle(intel_dp);
1011
1012         pp = ironlake_get_pp_control(intel_dp);
1013         pp |= EDP_FORCE_VDD;
1014
1015         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1016         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1017
1018         I915_WRITE(pp_ctrl_reg, pp);
1019         POSTING_READ(pp_ctrl_reg);
1020         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1021                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1022         /*
1023          * If the panel wasn't on, delay before accessing aux channel
1024          */
1025         if (!ironlake_edp_have_panel_power(intel_dp)) {
1026                 DRM_DEBUG_KMS("eDP was not running\n");
1027                 msleep(intel_dp->panel_power_up_delay);
1028         }
1029 }
1030
1031 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1032 {
1033         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         u32 pp;
1036         u32 pp_stat_reg, pp_ctrl_reg;
1037
1038         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1039
1040         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1041                 pp = ironlake_get_pp_control(intel_dp);
1042                 pp &= ~EDP_FORCE_VDD;
1043
1044                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1045                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1046
1047                 I915_WRITE(pp_ctrl_reg, pp);
1048                 POSTING_READ(pp_ctrl_reg);
1049
1050                 /* Make sure sequencer is idle before allowing subsequent activity */
1051                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1052                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1053                 msleep(intel_dp->panel_power_down_delay);
1054         }
1055 }
1056
1057 static void ironlake_panel_vdd_work(struct work_struct *__work)
1058 {
1059         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1060                                                  struct intel_dp, panel_vdd_work);
1061         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1062
1063         mutex_lock(&dev->mode_config.mutex);
1064         ironlake_panel_vdd_off_sync(intel_dp);
1065         mutex_unlock(&dev->mode_config.mutex);
1066 }
1067
1068 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1069 {
1070         if (!is_edp(intel_dp))
1071                 return;
1072
1073         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1074         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1075
1076         intel_dp->want_panel_vdd = false;
1077
1078         if (sync) {
1079                 ironlake_panel_vdd_off_sync(intel_dp);
1080         } else {
1081                 /*
1082                  * Queue the timer to fire a long
1083                  * time from now (relative to the power down delay)
1084                  * to keep the panel power up across a sequence of operations
1085                  */
1086                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1087                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1088         }
1089 }
1090
1091 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1092 {
1093         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1094         struct drm_i915_private *dev_priv = dev->dev_private;
1095         u32 pp;
1096         u32 pp_ctrl_reg;
1097
1098         if (!is_edp(intel_dp))
1099                 return;
1100
1101         DRM_DEBUG_KMS("Turn eDP power on\n");
1102
1103         if (ironlake_edp_have_panel_power(intel_dp)) {
1104                 DRM_DEBUG_KMS("eDP power already on\n");
1105                 return;
1106         }
1107
1108         ironlake_wait_panel_power_cycle(intel_dp);
1109
1110         pp = ironlake_get_pp_control(intel_dp);
1111         if (IS_GEN5(dev)) {
1112                 /* ILK workaround: disable reset around power sequence */
1113                 pp &= ~PANEL_POWER_RESET;
1114                 I915_WRITE(PCH_PP_CONTROL, pp);
1115                 POSTING_READ(PCH_PP_CONTROL);
1116         }
1117
1118         pp |= POWER_TARGET_ON;
1119         if (!IS_GEN5(dev))
1120                 pp |= PANEL_POWER_RESET;
1121
1122         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1123
1124         I915_WRITE(pp_ctrl_reg, pp);
1125         POSTING_READ(pp_ctrl_reg);
1126
1127         ironlake_wait_panel_on(intel_dp);
1128
1129         if (IS_GEN5(dev)) {
1130                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1131                 I915_WRITE(PCH_PP_CONTROL, pp);
1132                 POSTING_READ(PCH_PP_CONTROL);
1133         }
1134 }
1135
1136 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1137 {
1138         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1139         struct drm_i915_private *dev_priv = dev->dev_private;
1140         u32 pp;
1141         u32 pp_ctrl_reg;
1142
1143         if (!is_edp(intel_dp))
1144                 return;
1145
1146         DRM_DEBUG_KMS("Turn eDP power off\n");
1147
1148         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1149
1150         pp = ironlake_get_pp_control(intel_dp);
1151         /* We need to switch off panel power _and_ force vdd, for otherwise some
1152          * panels get very unhappy and cease to work. */
1153         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1154
1155         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1156
1157         I915_WRITE(pp_ctrl_reg, pp);
1158         POSTING_READ(pp_ctrl_reg);
1159
1160         intel_dp->want_panel_vdd = false;
1161
1162         ironlake_wait_panel_off(intel_dp);
1163 }
1164
1165 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1166 {
1167         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1168         struct drm_device *dev = intel_dig_port->base.base.dev;
1169         struct drm_i915_private *dev_priv = dev->dev_private;
1170         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1171         u32 pp;
1172         u32 pp_ctrl_reg;
1173
1174         if (!is_edp(intel_dp))
1175                 return;
1176
1177         DRM_DEBUG_KMS("\n");
1178         /*
1179          * If we enable the backlight right away following a panel power
1180          * on, we may see slight flicker as the panel syncs with the eDP
1181          * link.  So delay a bit to make sure the image is solid before
1182          * allowing it to appear.
1183          */
1184         msleep(intel_dp->backlight_on_delay);
1185         pp = ironlake_get_pp_control(intel_dp);
1186         pp |= EDP_BLC_ENABLE;
1187
1188         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1189
1190         I915_WRITE(pp_ctrl_reg, pp);
1191         POSTING_READ(pp_ctrl_reg);
1192
1193         intel_panel_enable_backlight(dev, pipe);
1194 }
1195
1196 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1197 {
1198         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200         u32 pp;
1201         u32 pp_ctrl_reg;
1202
1203         if (!is_edp(intel_dp))
1204                 return;
1205
1206         intel_panel_disable_backlight(dev);
1207
1208         DRM_DEBUG_KMS("\n");
1209         pp = ironlake_get_pp_control(intel_dp);
1210         pp &= ~EDP_BLC_ENABLE;
1211
1212         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1213
1214         I915_WRITE(pp_ctrl_reg, pp);
1215         POSTING_READ(pp_ctrl_reg);
1216         msleep(intel_dp->backlight_off_delay);
1217 }
1218
1219 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1220 {
1221         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1222         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1223         struct drm_device *dev = crtc->dev;
1224         struct drm_i915_private *dev_priv = dev->dev_private;
1225         u32 dpa_ctl;
1226
1227         assert_pipe_disabled(dev_priv,
1228                              to_intel_crtc(crtc)->pipe);
1229
1230         DRM_DEBUG_KMS("\n");
1231         dpa_ctl = I915_READ(DP_A);
1232         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1233         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1234
1235         /* We don't adjust intel_dp->DP while tearing down the link, to
1236          * facilitate link retraining (e.g. after hotplug). Hence clear all
1237          * enable bits here to ensure that we don't enable too much. */
1238         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1239         intel_dp->DP |= DP_PLL_ENABLE;
1240         I915_WRITE(DP_A, intel_dp->DP);
1241         POSTING_READ(DP_A);
1242         udelay(200);
1243 }
1244
1245 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1246 {
1247         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1248         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1249         struct drm_device *dev = crtc->dev;
1250         struct drm_i915_private *dev_priv = dev->dev_private;
1251         u32 dpa_ctl;
1252
1253         assert_pipe_disabled(dev_priv,
1254                              to_intel_crtc(crtc)->pipe);
1255
1256         dpa_ctl = I915_READ(DP_A);
1257         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1258              "dp pll off, should be on\n");
1259         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1260
1261         /* We can't rely on the value tracked for the DP register in
1262          * intel_dp->DP because link_down must not change that (otherwise link
1263          * re-training will fail. */
1264         dpa_ctl &= ~DP_PLL_ENABLE;
1265         I915_WRITE(DP_A, dpa_ctl);
1266         POSTING_READ(DP_A);
1267         udelay(200);
1268 }
1269
1270 /* If the sink supports it, try to set the power state appropriately */
1271 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1272 {
1273         int ret, i;
1274
1275         /* Should have a valid DPCD by this point */
1276         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1277                 return;
1278
1279         if (mode != DRM_MODE_DPMS_ON) {
1280                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1281                                                   DP_SET_POWER_D3);
1282                 if (ret != 1)
1283                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1284         } else {
1285                 /*
1286                  * When turning on, we need to retry for 1ms to give the sink
1287                  * time to wake up.
1288                  */
1289                 for (i = 0; i < 3; i++) {
1290                         ret = intel_dp_aux_native_write_1(intel_dp,
1291                                                           DP_SET_POWER,
1292                                                           DP_SET_POWER_D0);
1293                         if (ret == 1)
1294                                 break;
1295                         msleep(1);
1296                 }
1297         }
1298 }
1299
1300 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1301                                   enum pipe *pipe)
1302 {
1303         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1304         struct drm_device *dev = encoder->base.dev;
1305         struct drm_i915_private *dev_priv = dev->dev_private;
1306         u32 tmp = I915_READ(intel_dp->output_reg);
1307
1308         if (!(tmp & DP_PORT_EN))
1309                 return false;
1310
1311         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1312                 *pipe = PORT_TO_PIPE_CPT(tmp);
1313         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1314                 *pipe = PORT_TO_PIPE(tmp);
1315         } else {
1316                 u32 trans_sel;
1317                 u32 trans_dp;
1318                 int i;
1319
1320                 switch (intel_dp->output_reg) {
1321                 case PCH_DP_B:
1322                         trans_sel = TRANS_DP_PORT_SEL_B;
1323                         break;
1324                 case PCH_DP_C:
1325                         trans_sel = TRANS_DP_PORT_SEL_C;
1326                         break;
1327                 case PCH_DP_D:
1328                         trans_sel = TRANS_DP_PORT_SEL_D;
1329                         break;
1330                 default:
1331                         return true;
1332                 }
1333
1334                 for_each_pipe(i) {
1335                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1336                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1337                                 *pipe = i;
1338                                 return true;
1339                         }
1340                 }
1341
1342                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1343                               intel_dp->output_reg);
1344         }
1345
1346         return true;
1347 }
1348
1349 static void intel_disable_dp(struct intel_encoder *encoder)
1350 {
1351         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1352
1353         /* Make sure the panel is off before trying to change the mode. But also
1354          * ensure that we have vdd while we switch off the panel. */
1355         ironlake_edp_panel_vdd_on(intel_dp);
1356         ironlake_edp_backlight_off(intel_dp);
1357         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1358         ironlake_edp_panel_off(intel_dp);
1359
1360         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1361         if (!is_cpu_edp(intel_dp))
1362                 intel_dp_link_down(intel_dp);
1363 }
1364
1365 static void intel_post_disable_dp(struct intel_encoder *encoder)
1366 {
1367         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1368         struct drm_device *dev = encoder->base.dev;
1369
1370         if (is_cpu_edp(intel_dp)) {
1371                 intel_dp_link_down(intel_dp);
1372                 if (!IS_VALLEYVIEW(dev))
1373                         ironlake_edp_pll_off(intel_dp);
1374         }
1375 }
1376
1377 static void intel_enable_dp(struct intel_encoder *encoder)
1378 {
1379         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1380         struct drm_device *dev = encoder->base.dev;
1381         struct drm_i915_private *dev_priv = dev->dev_private;
1382         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1383
1384         if (WARN_ON(dp_reg & DP_PORT_EN))
1385                 return;
1386
1387         ironlake_edp_panel_vdd_on(intel_dp);
1388         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1389         intel_dp_start_link_train(intel_dp);
1390         ironlake_edp_panel_on(intel_dp);
1391         ironlake_edp_panel_vdd_off(intel_dp, true);
1392         intel_dp_complete_link_train(intel_dp);
1393         intel_dp_stop_link_train(intel_dp);
1394         ironlake_edp_backlight_on(intel_dp);
1395
1396         if (IS_VALLEYVIEW(dev)) {
1397                 struct intel_digital_port *dport =
1398                         enc_to_dig_port(&encoder->base);
1399                 int channel = vlv_dport_to_channel(dport);
1400
1401                 vlv_wait_port_ready(dev_priv, channel);
1402         }
1403 }
1404
1405 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1406 {
1407         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1408         struct drm_device *dev = encoder->base.dev;
1409         struct drm_i915_private *dev_priv = dev->dev_private;
1410
1411         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1412                 ironlake_edp_pll_on(intel_dp);
1413
1414         if (IS_VALLEYVIEW(dev)) {
1415                 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1416                 struct intel_crtc *intel_crtc =
1417                         to_intel_crtc(encoder->base.crtc);
1418                 int port = vlv_dport_to_channel(dport);
1419                 int pipe = intel_crtc->pipe;
1420                 u32 val;
1421
1422                 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1423
1424                 val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1425                 val = 0;
1426                 if (pipe)
1427                         val |= (1<<21);
1428                 else
1429                         val &= ~(1<<21);
1430                 val |= 0x001000c4;
1431                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1432
1433                 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1434                                  0x00760018);
1435                 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1436                                  0x00400888);
1437         }
1438 }
1439
1440 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1441 {
1442         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1443         struct drm_device *dev = encoder->base.dev;
1444         struct drm_i915_private *dev_priv = dev->dev_private;
1445         int port = vlv_dport_to_channel(dport);
1446
1447         if (!IS_VALLEYVIEW(dev))
1448                 return;
1449
1450         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1451
1452         /* Program Tx lane resets to default */
1453         intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
1454                          DPIO_PCS_TX_LANE2_RESET |
1455                          DPIO_PCS_TX_LANE1_RESET);
1456         intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1457                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1458                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1459                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1460                                  DPIO_PCS_CLK_SOFT_RESET);
1461
1462         /* Fix up inter-pair skew failure */
1463         intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1464         intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1465         intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1466 }
1467
1468 /*
1469  * Native read with retry for link status and receiver capability reads for
1470  * cases where the sink may still be asleep.
1471  */
1472 static bool
1473 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1474                                uint8_t *recv, int recv_bytes)
1475 {
1476         int ret, i;
1477
1478         /*
1479          * Sinks are *supposed* to come up within 1ms from an off state,
1480          * but we're also supposed to retry 3 times per the spec.
1481          */
1482         for (i = 0; i < 3; i++) {
1483                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1484                                                recv_bytes);
1485                 if (ret == recv_bytes)
1486                         return true;
1487                 msleep(1);
1488         }
1489
1490         return false;
1491 }
1492
1493 /*
1494  * Fetch AUX CH registers 0x202 - 0x207 which contain
1495  * link status information
1496  */
1497 static bool
1498 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1499 {
1500         return intel_dp_aux_native_read_retry(intel_dp,
1501                                               DP_LANE0_1_STATUS,
1502                                               link_status,
1503                                               DP_LINK_STATUS_SIZE);
1504 }
1505
1506 #if 0
1507 static char     *voltage_names[] = {
1508         "0.4V", "0.6V", "0.8V", "1.2V"
1509 };
1510 static char     *pre_emph_names[] = {
1511         "0dB", "3.5dB", "6dB", "9.5dB"
1512 };
1513 static char     *link_train_names[] = {
1514         "pattern 1", "pattern 2", "idle", "off"
1515 };
1516 #endif
1517
1518 /*
1519  * These are source-specific values; current Intel hardware supports
1520  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1521  */
1522
1523 static uint8_t
1524 intel_dp_voltage_max(struct intel_dp *intel_dp)
1525 {
1526         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1527
1528         if (IS_VALLEYVIEW(dev))
1529                 return DP_TRAIN_VOLTAGE_SWING_1200;
1530         else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1531                 return DP_TRAIN_VOLTAGE_SWING_800;
1532         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1533                 return DP_TRAIN_VOLTAGE_SWING_1200;
1534         else
1535                 return DP_TRAIN_VOLTAGE_SWING_800;
1536 }
1537
1538 static uint8_t
1539 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1540 {
1541         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1542
1543         if (HAS_DDI(dev)) {
1544                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1545                 case DP_TRAIN_VOLTAGE_SWING_400:
1546                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1547                 case DP_TRAIN_VOLTAGE_SWING_600:
1548                         return DP_TRAIN_PRE_EMPHASIS_6;
1549                 case DP_TRAIN_VOLTAGE_SWING_800:
1550                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1551                 case DP_TRAIN_VOLTAGE_SWING_1200:
1552                 default:
1553                         return DP_TRAIN_PRE_EMPHASIS_0;
1554                 }
1555         } else if (IS_VALLEYVIEW(dev)) {
1556                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1557                 case DP_TRAIN_VOLTAGE_SWING_400:
1558                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1559                 case DP_TRAIN_VOLTAGE_SWING_600:
1560                         return DP_TRAIN_PRE_EMPHASIS_6;
1561                 case DP_TRAIN_VOLTAGE_SWING_800:
1562                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1563                 case DP_TRAIN_VOLTAGE_SWING_1200:
1564                 default:
1565                         return DP_TRAIN_PRE_EMPHASIS_0;
1566                 }
1567         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1568                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1569                 case DP_TRAIN_VOLTAGE_SWING_400:
1570                         return DP_TRAIN_PRE_EMPHASIS_6;
1571                 case DP_TRAIN_VOLTAGE_SWING_600:
1572                 case DP_TRAIN_VOLTAGE_SWING_800:
1573                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1574                 default:
1575                         return DP_TRAIN_PRE_EMPHASIS_0;
1576                 }
1577         } else {
1578                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1579                 case DP_TRAIN_VOLTAGE_SWING_400:
1580                         return DP_TRAIN_PRE_EMPHASIS_6;
1581                 case DP_TRAIN_VOLTAGE_SWING_600:
1582                         return DP_TRAIN_PRE_EMPHASIS_6;
1583                 case DP_TRAIN_VOLTAGE_SWING_800:
1584                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1585                 case DP_TRAIN_VOLTAGE_SWING_1200:
1586                 default:
1587                         return DP_TRAIN_PRE_EMPHASIS_0;
1588                 }
1589         }
1590 }
1591
1592 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1593 {
1594         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1595         struct drm_i915_private *dev_priv = dev->dev_private;
1596         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1597         unsigned long demph_reg_value, preemph_reg_value,
1598                 uniqtranscale_reg_value;
1599         uint8_t train_set = intel_dp->train_set[0];
1600         int port = vlv_dport_to_channel(dport);
1601
1602         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1603
1604         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1605         case DP_TRAIN_PRE_EMPHASIS_0:
1606                 preemph_reg_value = 0x0004000;
1607                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1608                 case DP_TRAIN_VOLTAGE_SWING_400:
1609                         demph_reg_value = 0x2B405555;
1610                         uniqtranscale_reg_value = 0x552AB83A;
1611                         break;
1612                 case DP_TRAIN_VOLTAGE_SWING_600:
1613                         demph_reg_value = 0x2B404040;
1614                         uniqtranscale_reg_value = 0x5548B83A;
1615                         break;
1616                 case DP_TRAIN_VOLTAGE_SWING_800:
1617                         demph_reg_value = 0x2B245555;
1618                         uniqtranscale_reg_value = 0x5560B83A;
1619                         break;
1620                 case DP_TRAIN_VOLTAGE_SWING_1200:
1621                         demph_reg_value = 0x2B405555;
1622                         uniqtranscale_reg_value = 0x5598DA3A;
1623                         break;
1624                 default:
1625                         return 0;
1626                 }
1627                 break;
1628         case DP_TRAIN_PRE_EMPHASIS_3_5:
1629                 preemph_reg_value = 0x0002000;
1630                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1631                 case DP_TRAIN_VOLTAGE_SWING_400:
1632                         demph_reg_value = 0x2B404040;
1633                         uniqtranscale_reg_value = 0x5552B83A;
1634                         break;
1635                 case DP_TRAIN_VOLTAGE_SWING_600:
1636                         demph_reg_value = 0x2B404848;
1637                         uniqtranscale_reg_value = 0x5580B83A;
1638                         break;
1639                 case DP_TRAIN_VOLTAGE_SWING_800:
1640                         demph_reg_value = 0x2B404040;
1641                         uniqtranscale_reg_value = 0x55ADDA3A;
1642                         break;
1643                 default:
1644                         return 0;
1645                 }
1646                 break;
1647         case DP_TRAIN_PRE_EMPHASIS_6:
1648                 preemph_reg_value = 0x0000000;
1649                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1650                 case DP_TRAIN_VOLTAGE_SWING_400:
1651                         demph_reg_value = 0x2B305555;
1652                         uniqtranscale_reg_value = 0x5570B83A;
1653                         break;
1654                 case DP_TRAIN_VOLTAGE_SWING_600:
1655                         demph_reg_value = 0x2B2B4040;
1656                         uniqtranscale_reg_value = 0x55ADDA3A;
1657                         break;
1658                 default:
1659                         return 0;
1660                 }
1661                 break;
1662         case DP_TRAIN_PRE_EMPHASIS_9_5:
1663                 preemph_reg_value = 0x0006000;
1664                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1665                 case DP_TRAIN_VOLTAGE_SWING_400:
1666                         demph_reg_value = 0x1B405555;
1667                         uniqtranscale_reg_value = 0x55ADDA3A;
1668                         break;
1669                 default:
1670                         return 0;
1671                 }
1672                 break;
1673         default:
1674                 return 0;
1675         }
1676
1677         intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1678         intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1679         intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1680                          uniqtranscale_reg_value);
1681         intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1682         intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1683         intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1684         intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1685
1686         return 0;
1687 }
1688
1689 static void
1690 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1691 {
1692         uint8_t v = 0;
1693         uint8_t p = 0;
1694         int lane;
1695         uint8_t voltage_max;
1696         uint8_t preemph_max;
1697
1698         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1699                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1700                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1701
1702                 if (this_v > v)
1703                         v = this_v;
1704                 if (this_p > p)
1705                         p = this_p;
1706         }
1707
1708         voltage_max = intel_dp_voltage_max(intel_dp);
1709         if (v >= voltage_max)
1710                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1711
1712         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1713         if (p >= preemph_max)
1714                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1715
1716         for (lane = 0; lane < 4; lane++)
1717                 intel_dp->train_set[lane] = v | p;
1718 }
1719
1720 static uint32_t
1721 intel_gen4_signal_levels(uint8_t train_set)
1722 {
1723         uint32_t        signal_levels = 0;
1724
1725         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1726         case DP_TRAIN_VOLTAGE_SWING_400:
1727         default:
1728                 signal_levels |= DP_VOLTAGE_0_4;
1729                 break;
1730         case DP_TRAIN_VOLTAGE_SWING_600:
1731                 signal_levels |= DP_VOLTAGE_0_6;
1732                 break;
1733         case DP_TRAIN_VOLTAGE_SWING_800:
1734                 signal_levels |= DP_VOLTAGE_0_8;
1735                 break;
1736         case DP_TRAIN_VOLTAGE_SWING_1200:
1737                 signal_levels |= DP_VOLTAGE_1_2;
1738                 break;
1739         }
1740         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1741         case DP_TRAIN_PRE_EMPHASIS_0:
1742         default:
1743                 signal_levels |= DP_PRE_EMPHASIS_0;
1744                 break;
1745         case DP_TRAIN_PRE_EMPHASIS_3_5:
1746                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1747                 break;
1748         case DP_TRAIN_PRE_EMPHASIS_6:
1749                 signal_levels |= DP_PRE_EMPHASIS_6;
1750                 break;
1751         case DP_TRAIN_PRE_EMPHASIS_9_5:
1752                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1753                 break;
1754         }
1755         return signal_levels;
1756 }
1757
1758 /* Gen6's DP voltage swing and pre-emphasis control */
1759 static uint32_t
1760 intel_gen6_edp_signal_levels(uint8_t train_set)
1761 {
1762         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1763                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1764         switch (signal_levels) {
1765         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1766         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1767                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1768         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1769                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1770         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1771         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1772                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1773         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1774         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1775                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1776         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1777         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1778                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1779         default:
1780                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1781                               "0x%x\n", signal_levels);
1782                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1783         }
1784 }
1785
1786 /* Gen7's DP voltage swing and pre-emphasis control */
1787 static uint32_t
1788 intel_gen7_edp_signal_levels(uint8_t train_set)
1789 {
1790         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1791                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1792         switch (signal_levels) {
1793         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1794                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1795         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1796                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1797         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1798                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1799
1800         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1801                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1802         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1803                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1804
1805         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1806                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1807         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1808                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1809
1810         default:
1811                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1812                               "0x%x\n", signal_levels);
1813                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1814         }
1815 }
1816
1817 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1818 static uint32_t
1819 intel_hsw_signal_levels(uint8_t train_set)
1820 {
1821         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1822                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1823         switch (signal_levels) {
1824         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1825                 return DDI_BUF_EMP_400MV_0DB_HSW;
1826         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1827                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1828         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1829                 return DDI_BUF_EMP_400MV_6DB_HSW;
1830         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1831                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1832
1833         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1834                 return DDI_BUF_EMP_600MV_0DB_HSW;
1835         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1836                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1837         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1838                 return DDI_BUF_EMP_600MV_6DB_HSW;
1839
1840         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1841                 return DDI_BUF_EMP_800MV_0DB_HSW;
1842         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1843                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1844         default:
1845                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1846                               "0x%x\n", signal_levels);
1847                 return DDI_BUF_EMP_400MV_0DB_HSW;
1848         }
1849 }
1850
1851 /* Properly updates "DP" with the correct signal levels. */
1852 static void
1853 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1854 {
1855         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1856         struct drm_device *dev = intel_dig_port->base.base.dev;
1857         uint32_t signal_levels, mask;
1858         uint8_t train_set = intel_dp->train_set[0];
1859
1860         if (HAS_DDI(dev)) {
1861                 signal_levels = intel_hsw_signal_levels(train_set);
1862                 mask = DDI_BUF_EMP_MASK;
1863         } else if (IS_VALLEYVIEW(dev)) {
1864                 signal_levels = intel_vlv_signal_levels(intel_dp);
1865                 mask = 0;
1866         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1867                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1868                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1869         } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1870                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1871                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1872         } else {
1873                 signal_levels = intel_gen4_signal_levels(train_set);
1874                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1875         }
1876
1877         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1878
1879         *DP = (*DP & ~mask) | signal_levels;
1880 }
1881
1882 static bool
1883 intel_dp_set_link_train(struct intel_dp *intel_dp,
1884                         uint32_t dp_reg_value,
1885                         uint8_t dp_train_pat)
1886 {
1887         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1888         struct drm_device *dev = intel_dig_port->base.base.dev;
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         enum port port = intel_dig_port->port;
1891         int ret;
1892
1893         if (HAS_DDI(dev)) {
1894                 uint32_t temp = I915_READ(DP_TP_CTL(port));
1895
1896                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1897                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1898                 else
1899                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1900
1901                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1902                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1903                 case DP_TRAINING_PATTERN_DISABLE:
1904                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1905
1906                         break;
1907                 case DP_TRAINING_PATTERN_1:
1908                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1909                         break;
1910                 case DP_TRAINING_PATTERN_2:
1911                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1912                         break;
1913                 case DP_TRAINING_PATTERN_3:
1914                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1915                         break;
1916                 }
1917                 I915_WRITE(DP_TP_CTL(port), temp);
1918
1919         } else if (HAS_PCH_CPT(dev) &&
1920                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1921                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1922
1923                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1924                 case DP_TRAINING_PATTERN_DISABLE:
1925                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1926                         break;
1927                 case DP_TRAINING_PATTERN_1:
1928                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1929                         break;
1930                 case DP_TRAINING_PATTERN_2:
1931                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1932                         break;
1933                 case DP_TRAINING_PATTERN_3:
1934                         DRM_ERROR("DP training pattern 3 not supported\n");
1935                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1936                         break;
1937                 }
1938
1939         } else {
1940                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1941
1942                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1943                 case DP_TRAINING_PATTERN_DISABLE:
1944                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1945                         break;
1946                 case DP_TRAINING_PATTERN_1:
1947                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1948                         break;
1949                 case DP_TRAINING_PATTERN_2:
1950                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1951                         break;
1952                 case DP_TRAINING_PATTERN_3:
1953                         DRM_ERROR("DP training pattern 3 not supported\n");
1954                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1955                         break;
1956                 }
1957         }
1958
1959         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1960         POSTING_READ(intel_dp->output_reg);
1961
1962         intel_dp_aux_native_write_1(intel_dp,
1963                                     DP_TRAINING_PATTERN_SET,
1964                                     dp_train_pat);
1965
1966         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1967             DP_TRAINING_PATTERN_DISABLE) {
1968                 ret = intel_dp_aux_native_write(intel_dp,
1969                                                 DP_TRAINING_LANE0_SET,
1970                                                 intel_dp->train_set,
1971                                                 intel_dp->lane_count);
1972                 if (ret != intel_dp->lane_count)
1973                         return false;
1974         }
1975
1976         return true;
1977 }
1978
1979 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1980 {
1981         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1982         struct drm_device *dev = intel_dig_port->base.base.dev;
1983         struct drm_i915_private *dev_priv = dev->dev_private;
1984         enum port port = intel_dig_port->port;
1985         uint32_t val;
1986
1987         if (!HAS_DDI(dev))
1988                 return;
1989
1990         val = I915_READ(DP_TP_CTL(port));
1991         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1992         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
1993         I915_WRITE(DP_TP_CTL(port), val);
1994
1995         /*
1996          * On PORT_A we can have only eDP in SST mode. There the only reason
1997          * we need to set idle transmission mode is to work around a HW issue
1998          * where we enable the pipe while not in idle link-training mode.
1999          * In this case there is requirement to wait for a minimum number of
2000          * idle patterns to be sent.
2001          */
2002         if (port == PORT_A)
2003                 return;
2004
2005         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2006                      1))
2007                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2008 }
2009
2010 /* Enable corresponding port and start training pattern 1 */
2011 void
2012 intel_dp_start_link_train(struct intel_dp *intel_dp)
2013 {
2014         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2015         struct drm_device *dev = encoder->dev;
2016         int i;
2017         uint8_t voltage;
2018         bool clock_recovery = false;
2019         int voltage_tries, loop_tries;
2020         uint32_t DP = intel_dp->DP;
2021
2022         if (HAS_DDI(dev))
2023                 intel_ddi_prepare_link_retrain(encoder);
2024
2025         /* Write the link configuration data */
2026         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2027                                   intel_dp->link_configuration,
2028                                   DP_LINK_CONFIGURATION_SIZE);
2029
2030         DP |= DP_PORT_EN;
2031
2032         memset(intel_dp->train_set, 0, 4);
2033         voltage = 0xff;
2034         voltage_tries = 0;
2035         loop_tries = 0;
2036         clock_recovery = false;
2037         for (;;) {
2038                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2039                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2040
2041                 intel_dp_set_signal_levels(intel_dp, &DP);
2042
2043                 /* Set training pattern 1 */
2044                 if (!intel_dp_set_link_train(intel_dp, DP,
2045                                              DP_TRAINING_PATTERN_1 |
2046                                              DP_LINK_SCRAMBLING_DISABLE))
2047                         break;
2048
2049                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2050                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2051                         DRM_ERROR("failed to get link status\n");
2052                         break;
2053                 }
2054
2055                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2056                         DRM_DEBUG_KMS("clock recovery OK\n");
2057                         clock_recovery = true;
2058                         break;
2059                 }
2060
2061                 /* Check to see if we've tried the max voltage */
2062                 for (i = 0; i < intel_dp->lane_count; i++)
2063                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2064                                 break;
2065                 if (i == intel_dp->lane_count) {
2066                         ++loop_tries;
2067                         if (loop_tries == 5) {
2068                                 DRM_DEBUG_KMS("too many full retries, give up\n");
2069                                 break;
2070                         }
2071                         memset(intel_dp->train_set, 0, 4);
2072                         voltage_tries = 0;
2073                         continue;
2074                 }
2075
2076                 /* Check to see if we've tried the same voltage 5 times */
2077                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2078                         ++voltage_tries;
2079                         if (voltage_tries == 5) {
2080                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2081                                 break;
2082                         }
2083                 } else
2084                         voltage_tries = 0;
2085                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2086
2087                 /* Compute new intel_dp->train_set as requested by target */
2088                 intel_get_adjust_train(intel_dp, link_status);
2089         }
2090
2091         intel_dp->DP = DP;
2092 }
2093
2094 void
2095 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2096 {
2097         bool channel_eq = false;
2098         int tries, cr_tries;
2099         uint32_t DP = intel_dp->DP;
2100
2101         /* channel equalization */
2102         tries = 0;
2103         cr_tries = 0;
2104         channel_eq = false;
2105         for (;;) {
2106                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2107
2108                 if (cr_tries > 5) {
2109                         DRM_ERROR("failed to train DP, aborting\n");
2110                         intel_dp_link_down(intel_dp);
2111                         break;
2112                 }
2113
2114                 intel_dp_set_signal_levels(intel_dp, &DP);
2115
2116                 /* channel eq pattern */
2117                 if (!intel_dp_set_link_train(intel_dp, DP,
2118                                              DP_TRAINING_PATTERN_2 |
2119                                              DP_LINK_SCRAMBLING_DISABLE))
2120                         break;
2121
2122                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2123                 if (!intel_dp_get_link_status(intel_dp, link_status))
2124                         break;
2125
2126                 /* Make sure clock is still ok */
2127                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2128                         intel_dp_start_link_train(intel_dp);
2129                         cr_tries++;
2130                         continue;
2131                 }
2132
2133                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2134                         channel_eq = true;
2135                         break;
2136                 }
2137
2138                 /* Try 5 times, then try clock recovery if that fails */
2139                 if (tries > 5) {
2140                         intel_dp_link_down(intel_dp);
2141                         intel_dp_start_link_train(intel_dp);
2142                         tries = 0;
2143                         cr_tries++;
2144                         continue;
2145                 }
2146
2147                 /* Compute new intel_dp->train_set as requested by target */
2148                 intel_get_adjust_train(intel_dp, link_status);
2149                 ++tries;
2150         }
2151
2152         intel_dp_set_idle_link_train(intel_dp);
2153
2154         intel_dp->DP = DP;
2155
2156         if (channel_eq)
2157                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2158
2159 }
2160
2161 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2162 {
2163         intel_dp_set_link_train(intel_dp, intel_dp->DP,
2164                                 DP_TRAINING_PATTERN_DISABLE);
2165 }
2166
2167 static void
2168 intel_dp_link_down(struct intel_dp *intel_dp)
2169 {
2170         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2171         struct drm_device *dev = intel_dig_port->base.base.dev;
2172         struct drm_i915_private *dev_priv = dev->dev_private;
2173         struct intel_crtc *intel_crtc =
2174                 to_intel_crtc(intel_dig_port->base.base.crtc);
2175         uint32_t DP = intel_dp->DP;
2176
2177         /*
2178          * DDI code has a strict mode set sequence and we should try to respect
2179          * it, otherwise we might hang the machine in many different ways. So we
2180          * really should be disabling the port only on a complete crtc_disable
2181          * sequence. This function is just called under two conditions on DDI
2182          * code:
2183          * - Link train failed while doing crtc_enable, and on this case we
2184          *   really should respect the mode set sequence and wait for a
2185          *   crtc_disable.
2186          * - Someone turned the monitor off and intel_dp_check_link_status
2187          *   called us. We don't need to disable the whole port on this case, so
2188          *   when someone turns the monitor on again,
2189          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2190          *   train.
2191          */
2192         if (HAS_DDI(dev))
2193                 return;
2194
2195         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2196                 return;
2197
2198         DRM_DEBUG_KMS("\n");
2199
2200         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2201                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2202                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2203         } else {
2204                 DP &= ~DP_LINK_TRAIN_MASK;
2205                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2206         }
2207         POSTING_READ(intel_dp->output_reg);
2208
2209         /* We don't really know why we're doing this */
2210         intel_wait_for_vblank(dev, intel_crtc->pipe);
2211
2212         if (HAS_PCH_IBX(dev) &&
2213             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2214                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2215
2216                 /* Hardware workaround: leaving our transcoder select
2217                  * set to transcoder B while it's off will prevent the
2218                  * corresponding HDMI output on transcoder A.
2219                  *
2220                  * Combine this with another hardware workaround:
2221                  * transcoder select bit can only be cleared while the
2222                  * port is enabled.
2223                  */
2224                 DP &= ~DP_PIPEB_SELECT;
2225                 I915_WRITE(intel_dp->output_reg, DP);
2226
2227                 /* Changes to enable or select take place the vblank
2228                  * after being written.
2229                  */
2230                 if (WARN_ON(crtc == NULL)) {
2231                         /* We should never try to disable a port without a crtc
2232                          * attached. For paranoia keep the code around for a
2233                          * bit. */
2234                         POSTING_READ(intel_dp->output_reg);
2235                         msleep(50);
2236                 } else
2237                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2238         }
2239
2240         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2241         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2242         POSTING_READ(intel_dp->output_reg);
2243         msleep(intel_dp->panel_power_down_delay);
2244 }
2245
2246 static bool
2247 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2248 {
2249         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2250
2251         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2252                                            sizeof(intel_dp->dpcd)) == 0)
2253                 return false; /* aux transfer failed */
2254
2255         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2256                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2257         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2258
2259         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2260                 return false; /* DPCD not present */
2261
2262         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2263               DP_DWN_STRM_PORT_PRESENT))
2264                 return true; /* native DP sink */
2265
2266         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2267                 return true; /* no per-port downstream info */
2268
2269         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2270                                            intel_dp->downstream_ports,
2271                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2272                 return false; /* downstream port status fetch failed */
2273
2274         return true;
2275 }
2276
2277 static void
2278 intel_dp_probe_oui(struct intel_dp *intel_dp)
2279 {
2280         u8 buf[3];
2281
2282         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2283                 return;
2284
2285         ironlake_edp_panel_vdd_on(intel_dp);
2286
2287         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2288                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2289                               buf[0], buf[1], buf[2]);
2290
2291         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2292                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2293                               buf[0], buf[1], buf[2]);
2294
2295         ironlake_edp_panel_vdd_off(intel_dp, false);
2296 }
2297
2298 static bool
2299 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2300 {
2301         int ret;
2302
2303         ret = intel_dp_aux_native_read_retry(intel_dp,
2304                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2305                                              sink_irq_vector, 1);
2306         if (!ret)
2307                 return false;
2308
2309         return true;
2310 }
2311
2312 static void
2313 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2314 {
2315         /* NAK by default */
2316         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2317 }
2318
2319 /*
2320  * According to DP spec
2321  * 5.1.2:
2322  *  1. Read DPCD
2323  *  2. Configure link according to Receiver Capabilities
2324  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2325  *  4. Check link status on receipt of hot-plug interrupt
2326  */
2327
2328 void
2329 intel_dp_check_link_status(struct intel_dp *intel_dp)
2330 {
2331         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2332         u8 sink_irq_vector;
2333         u8 link_status[DP_LINK_STATUS_SIZE];
2334
2335         if (!intel_encoder->connectors_active)
2336                 return;
2337
2338         if (WARN_ON(!intel_encoder->base.crtc))
2339                 return;
2340
2341         /* Try to read receiver status if the link appears to be up */
2342         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2343                 intel_dp_link_down(intel_dp);
2344                 return;
2345         }
2346
2347         /* Now read the DPCD to see if it's actually running */
2348         if (!intel_dp_get_dpcd(intel_dp)) {
2349                 intel_dp_link_down(intel_dp);
2350                 return;
2351         }
2352
2353         /* Try to read the source of the interrupt */
2354         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2355             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2356                 /* Clear interrupt source */
2357                 intel_dp_aux_native_write_1(intel_dp,
2358                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2359                                             sink_irq_vector);
2360
2361                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2362                         intel_dp_handle_test_request(intel_dp);
2363                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2364                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2365         }
2366
2367         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2368                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2369                               drm_get_encoder_name(&intel_encoder->base));
2370                 intel_dp_start_link_train(intel_dp);
2371                 intel_dp_complete_link_train(intel_dp);
2372                 intel_dp_stop_link_train(intel_dp);
2373         }
2374 }
2375
2376 /* XXX this is probably wrong for multiple downstream ports */
2377 static enum drm_connector_status
2378 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2379 {
2380         uint8_t *dpcd = intel_dp->dpcd;
2381         bool hpd;
2382         uint8_t type;
2383
2384         if (!intel_dp_get_dpcd(intel_dp))
2385                 return connector_status_disconnected;
2386
2387         /* if there's no downstream port, we're done */
2388         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2389                 return connector_status_connected;
2390
2391         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2392         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2393         if (hpd) {
2394                 uint8_t reg;
2395                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2396                                                     &reg, 1))
2397                         return connector_status_unknown;
2398                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2399                                               : connector_status_disconnected;
2400         }
2401
2402         /* If no HPD, poke DDC gently */
2403         if (drm_probe_ddc(&intel_dp->adapter))
2404                 return connector_status_connected;
2405
2406         /* Well we tried, say unknown for unreliable port types */
2407         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2408         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2409                 return connector_status_unknown;
2410
2411         /* Anything else is out of spec, warn and ignore */
2412         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2413         return connector_status_disconnected;
2414 }
2415
2416 static enum drm_connector_status
2417 ironlake_dp_detect(struct intel_dp *intel_dp)
2418 {
2419         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2420         struct drm_i915_private *dev_priv = dev->dev_private;
2421         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2422         enum drm_connector_status status;
2423
2424         /* Can't disconnect eDP, but you can close the lid... */
2425         if (is_edp(intel_dp)) {
2426                 status = intel_panel_detect(dev);
2427                 if (status == connector_status_unknown)
2428                         status = connector_status_connected;
2429                 return status;
2430         }
2431
2432         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2433                 return connector_status_disconnected;
2434
2435         return intel_dp_detect_dpcd(intel_dp);
2436 }
2437
2438 static enum drm_connector_status
2439 g4x_dp_detect(struct intel_dp *intel_dp)
2440 {
2441         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2442         struct drm_i915_private *dev_priv = dev->dev_private;
2443         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2444         uint32_t bit;
2445
2446         /* Can't disconnect eDP, but you can close the lid... */
2447         if (is_edp(intel_dp)) {
2448                 enum drm_connector_status status;
2449
2450                 status = intel_panel_detect(dev);
2451                 if (status == connector_status_unknown)
2452                         status = connector_status_connected;
2453                 return status;
2454         }
2455
2456         switch (intel_dig_port->port) {
2457         case PORT_B:
2458                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2459                 break;
2460         case PORT_C:
2461                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2462                 break;
2463         case PORT_D:
2464                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2465                 break;
2466         default:
2467                 return connector_status_unknown;
2468         }
2469
2470         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2471                 return connector_status_disconnected;
2472
2473         return intel_dp_detect_dpcd(intel_dp);
2474 }
2475
2476 static struct edid *
2477 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2478 {
2479         struct intel_connector *intel_connector = to_intel_connector(connector);
2480
2481         /* use cached edid if we have one */
2482         if (intel_connector->edid) {
2483                 struct edid *edid;
2484                 int size;
2485
2486                 /* invalid edid */
2487                 if (IS_ERR(intel_connector->edid))
2488                         return NULL;
2489
2490                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2491                 edid = kmalloc(size, GFP_KERNEL);
2492                 if (!edid)
2493                         return NULL;
2494
2495                 memcpy(edid, intel_connector->edid, size);
2496                 return edid;
2497         }
2498
2499         return drm_get_edid(connector, adapter);
2500 }
2501
2502 static int
2503 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2504 {
2505         struct intel_connector *intel_connector = to_intel_connector(connector);
2506
2507         /* use cached edid if we have one */
2508         if (intel_connector->edid) {
2509                 /* invalid edid */
2510                 if (IS_ERR(intel_connector->edid))
2511                         return 0;
2512
2513                 return intel_connector_update_modes(connector,
2514                                                     intel_connector->edid);
2515         }
2516
2517         return intel_ddc_get_modes(connector, adapter);
2518 }
2519
2520 static enum drm_connector_status
2521 intel_dp_detect(struct drm_connector *connector, bool force)
2522 {
2523         struct intel_dp *intel_dp = intel_attached_dp(connector);
2524         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2525         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2526         struct drm_device *dev = connector->dev;
2527         enum drm_connector_status status;
2528         struct edid *edid = NULL;
2529
2530         intel_dp->has_audio = false;
2531
2532         if (HAS_PCH_SPLIT(dev))
2533                 status = ironlake_dp_detect(intel_dp);
2534         else
2535                 status = g4x_dp_detect(intel_dp);
2536
2537         if (status != connector_status_connected)
2538                 return status;
2539
2540         intel_dp_probe_oui(intel_dp);
2541
2542         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2543                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2544         } else {
2545                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2546                 if (edid) {
2547                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2548                         kfree(edid);
2549                 }
2550         }
2551
2552         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2553                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2554         return connector_status_connected;
2555 }
2556
2557 static int intel_dp_get_modes(struct drm_connector *connector)
2558 {
2559         struct intel_dp *intel_dp = intel_attached_dp(connector);
2560         struct intel_connector *intel_connector = to_intel_connector(connector);
2561         struct drm_device *dev = connector->dev;
2562         int ret;
2563
2564         /* We should parse the EDID data and find out if it has an audio sink
2565          */
2566
2567         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2568         if (ret)
2569                 return ret;
2570
2571         /* if eDP has no EDID, fall back to fixed mode */
2572         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2573                 struct drm_display_mode *mode;
2574                 mode = drm_mode_duplicate(dev,
2575                                           intel_connector->panel.fixed_mode);
2576                 if (mode) {
2577                         drm_mode_probed_add(connector, mode);
2578                         return 1;
2579                 }
2580         }
2581         return 0;
2582 }
2583
2584 static bool
2585 intel_dp_detect_audio(struct drm_connector *connector)
2586 {
2587         struct intel_dp *intel_dp = intel_attached_dp(connector);
2588         struct edid *edid;
2589         bool has_audio = false;
2590
2591         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2592         if (edid) {
2593                 has_audio = drm_detect_monitor_audio(edid);
2594                 kfree(edid);
2595         }
2596
2597         return has_audio;
2598 }
2599
2600 static int
2601 intel_dp_set_property(struct drm_connector *connector,
2602                       struct drm_property *property,
2603                       uint64_t val)
2604 {
2605         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2606         struct intel_connector *intel_connector = to_intel_connector(connector);
2607         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2608         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2609         int ret;
2610
2611         ret = drm_object_property_set_value(&connector->base, property, val);
2612         if (ret)
2613                 return ret;
2614
2615         if (property == dev_priv->force_audio_property) {
2616                 int i = val;
2617                 bool has_audio;
2618
2619                 if (i == intel_dp->force_audio)
2620                         return 0;
2621
2622                 intel_dp->force_audio = i;
2623
2624                 if (i == HDMI_AUDIO_AUTO)
2625                         has_audio = intel_dp_detect_audio(connector);
2626                 else
2627                         has_audio = (i == HDMI_AUDIO_ON);
2628
2629                 if (has_audio == intel_dp->has_audio)
2630                         return 0;
2631
2632                 intel_dp->has_audio = has_audio;
2633                 goto done;
2634         }
2635
2636         if (property == dev_priv->broadcast_rgb_property) {
2637                 bool old_auto = intel_dp->color_range_auto;
2638                 uint32_t old_range = intel_dp->color_range;
2639
2640                 switch (val) {
2641                 case INTEL_BROADCAST_RGB_AUTO:
2642                         intel_dp->color_range_auto = true;
2643                         break;
2644                 case INTEL_BROADCAST_RGB_FULL:
2645                         intel_dp->color_range_auto = false;
2646                         intel_dp->color_range = 0;
2647                         break;
2648                 case INTEL_BROADCAST_RGB_LIMITED:
2649                         intel_dp->color_range_auto = false;
2650                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2651                         break;
2652                 default:
2653                         return -EINVAL;
2654                 }
2655
2656                 if (old_auto == intel_dp->color_range_auto &&
2657                     old_range == intel_dp->color_range)
2658                         return 0;
2659
2660                 goto done;
2661         }
2662
2663         if (is_edp(intel_dp) &&
2664             property == connector->dev->mode_config.scaling_mode_property) {
2665                 if (val == DRM_MODE_SCALE_NONE) {
2666                         DRM_DEBUG_KMS("no scaling not supported\n");
2667                         return -EINVAL;
2668                 }
2669
2670                 if (intel_connector->panel.fitting_mode == val) {
2671                         /* the eDP scaling property is not changed */
2672                         return 0;
2673                 }
2674                 intel_connector->panel.fitting_mode = val;
2675
2676                 goto done;
2677         }
2678
2679         return -EINVAL;
2680
2681 done:
2682         if (intel_encoder->base.crtc)
2683                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2684
2685         return 0;
2686 }
2687
2688 static void
2689 intel_dp_destroy(struct drm_connector *connector)
2690 {
2691         struct intel_dp *intel_dp = intel_attached_dp(connector);
2692         struct intel_connector *intel_connector = to_intel_connector(connector);
2693
2694         if (!IS_ERR_OR_NULL(intel_connector->edid))
2695                 kfree(intel_connector->edid);
2696
2697         if (is_edp(intel_dp))
2698                 intel_panel_fini(&intel_connector->panel);
2699
2700         drm_sysfs_connector_remove(connector);
2701         drm_connector_cleanup(connector);
2702         kfree(connector);
2703 }
2704
2705 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2706 {
2707         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2708         struct intel_dp *intel_dp = &intel_dig_port->dp;
2709         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2710
2711         i2c_del_adapter(&intel_dp->adapter);
2712         drm_encoder_cleanup(encoder);
2713         if (is_edp(intel_dp)) {
2714                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2715                 mutex_lock(&dev->mode_config.mutex);
2716                 ironlake_panel_vdd_off_sync(intel_dp);
2717                 mutex_unlock(&dev->mode_config.mutex);
2718         }
2719         kfree(intel_dig_port);
2720 }
2721
2722 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2723         .mode_set = intel_dp_mode_set,
2724 };
2725
2726 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2727         .dpms = intel_connector_dpms,
2728         .detect = intel_dp_detect,
2729         .fill_modes = drm_helper_probe_single_connector_modes,
2730         .set_property = intel_dp_set_property,
2731         .destroy = intel_dp_destroy,
2732 };
2733
2734 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2735         .get_modes = intel_dp_get_modes,
2736         .mode_valid = intel_dp_mode_valid,
2737         .best_encoder = intel_best_encoder,
2738 };
2739
2740 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2741         .destroy = intel_dp_encoder_destroy,
2742 };
2743
2744 static void
2745 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2746 {
2747         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2748
2749         intel_dp_check_link_status(intel_dp);
2750 }
2751
2752 /* Return which DP Port should be selected for Transcoder DP control */
2753 int
2754 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2755 {
2756         struct drm_device *dev = crtc->dev;
2757         struct intel_encoder *intel_encoder;
2758         struct intel_dp *intel_dp;
2759
2760         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2761                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2762
2763                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2764                     intel_encoder->type == INTEL_OUTPUT_EDP)
2765                         return intel_dp->output_reg;
2766         }
2767
2768         return -1;
2769 }
2770
2771 /* check the VBT to see whether the eDP is on DP-D port */
2772 bool intel_dpd_is_edp(struct drm_device *dev)
2773 {
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         struct child_device_config *p_child;
2776         int i;
2777
2778         if (!dev_priv->vbt.child_dev_num)
2779                 return false;
2780
2781         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2782                 p_child = dev_priv->vbt.child_dev + i;
2783
2784                 if (p_child->dvo_port == PORT_IDPD &&
2785                     p_child->device_type == DEVICE_TYPE_eDP)
2786                         return true;
2787         }
2788         return false;
2789 }
2790
2791 static void
2792 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2793 {
2794         struct intel_connector *intel_connector = to_intel_connector(connector);
2795
2796         intel_attach_force_audio_property(connector);
2797         intel_attach_broadcast_rgb_property(connector);
2798         intel_dp->color_range_auto = true;
2799
2800         if (is_edp(intel_dp)) {
2801                 drm_mode_create_scaling_mode_property(connector->dev);
2802                 drm_object_attach_property(
2803                         &connector->base,
2804                         connector->dev->mode_config.scaling_mode_property,
2805                         DRM_MODE_SCALE_ASPECT);
2806                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2807         }
2808 }
2809
2810 static void
2811 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2812                                     struct intel_dp *intel_dp,
2813                                     struct edp_power_seq *out)
2814 {
2815         struct drm_i915_private *dev_priv = dev->dev_private;
2816         struct edp_power_seq cur, vbt, spec, final;
2817         u32 pp_on, pp_off, pp_div, pp;
2818         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2819
2820         if (HAS_PCH_SPLIT(dev)) {
2821                 pp_control_reg = PCH_PP_CONTROL;
2822                 pp_on_reg = PCH_PP_ON_DELAYS;
2823                 pp_off_reg = PCH_PP_OFF_DELAYS;
2824                 pp_div_reg = PCH_PP_DIVISOR;
2825         } else {
2826                 pp_control_reg = PIPEA_PP_CONTROL;
2827                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2828                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2829                 pp_div_reg = PIPEA_PP_DIVISOR;
2830         }
2831
2832         /* Workaround: Need to write PP_CONTROL with the unlock key as
2833          * the very first thing. */
2834         pp = ironlake_get_pp_control(intel_dp);
2835         I915_WRITE(pp_control_reg, pp);
2836
2837         pp_on = I915_READ(pp_on_reg);
2838         pp_off = I915_READ(pp_off_reg);
2839         pp_div = I915_READ(pp_div_reg);
2840
2841         /* Pull timing values out of registers */
2842         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2843                 PANEL_POWER_UP_DELAY_SHIFT;
2844
2845         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2846                 PANEL_LIGHT_ON_DELAY_SHIFT;
2847
2848         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2849                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2850
2851         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2852                 PANEL_POWER_DOWN_DELAY_SHIFT;
2853
2854         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2855                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2856
2857         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2858                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2859
2860         vbt = dev_priv->vbt.edp_pps;
2861
2862         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2863          * our hw here, which are all in 100usec. */
2864         spec.t1_t3 = 210 * 10;
2865         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2866         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2867         spec.t10 = 500 * 10;
2868         /* This one is special and actually in units of 100ms, but zero
2869          * based in the hw (so we need to add 100 ms). But the sw vbt
2870          * table multiplies it with 1000 to make it in units of 100usec,
2871          * too. */
2872         spec.t11_t12 = (510 + 100) * 10;
2873
2874         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2875                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2876
2877         /* Use the max of the register settings and vbt. If both are
2878          * unset, fall back to the spec limits. */
2879 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2880                                        spec.field : \
2881                                        max(cur.field, vbt.field))
2882         assign_final(t1_t3);
2883         assign_final(t8);
2884         assign_final(t9);
2885         assign_final(t10);
2886         assign_final(t11_t12);
2887 #undef assign_final
2888
2889 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2890         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2891         intel_dp->backlight_on_delay = get_delay(t8);
2892         intel_dp->backlight_off_delay = get_delay(t9);
2893         intel_dp->panel_power_down_delay = get_delay(t10);
2894         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2895 #undef get_delay
2896
2897         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2898                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2899                       intel_dp->panel_power_cycle_delay);
2900
2901         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2902                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2903
2904         if (out)
2905                 *out = final;
2906 }
2907
2908 static void
2909 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2910                                               struct intel_dp *intel_dp,
2911                                               struct edp_power_seq *seq)
2912 {
2913         struct drm_i915_private *dev_priv = dev->dev_private;
2914         u32 pp_on, pp_off, pp_div, port_sel = 0;
2915         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2916         int pp_on_reg, pp_off_reg, pp_div_reg;
2917
2918         if (HAS_PCH_SPLIT(dev)) {
2919                 pp_on_reg = PCH_PP_ON_DELAYS;
2920                 pp_off_reg = PCH_PP_OFF_DELAYS;
2921                 pp_div_reg = PCH_PP_DIVISOR;
2922         } else {
2923                 pp_on_reg = PIPEA_PP_ON_DELAYS;
2924                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2925                 pp_div_reg = PIPEA_PP_DIVISOR;
2926         }
2927
2928         if (IS_VALLEYVIEW(dev))
2929                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2930
2931         /* And finally store the new values in the power sequencer. */
2932         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2933                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2934         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2935                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2936         /* Compute the divisor for the pp clock, simply match the Bspec
2937          * formula. */
2938         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2939         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2940                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2941
2942         /* Haswell doesn't have any port selection bits for the panel
2943          * power sequencer any more. */
2944         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2945                 if (is_cpu_edp(intel_dp))
2946                         port_sel = PANEL_POWER_PORT_DP_A;
2947                 else
2948                         port_sel = PANEL_POWER_PORT_DP_D;
2949         }
2950
2951         pp_on |= port_sel;
2952
2953         I915_WRITE(pp_on_reg, pp_on);
2954         I915_WRITE(pp_off_reg, pp_off);
2955         I915_WRITE(pp_div_reg, pp_div);
2956
2957         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2958                       I915_READ(pp_on_reg),
2959                       I915_READ(pp_off_reg),
2960                       I915_READ(pp_div_reg));
2961 }
2962
2963 void
2964 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2965                         struct intel_connector *intel_connector)
2966 {
2967         struct drm_connector *connector = &intel_connector->base;
2968         struct intel_dp *intel_dp = &intel_dig_port->dp;
2969         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2970         struct drm_device *dev = intel_encoder->base.dev;
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972         struct drm_display_mode *fixed_mode = NULL;
2973         struct edp_power_seq power_seq = { 0 };
2974         enum port port = intel_dig_port->port;
2975         const char *name = NULL;
2976         int type;
2977
2978         /* Preserve the current hw state. */
2979         intel_dp->DP = I915_READ(intel_dp->output_reg);
2980         intel_dp->attached_connector = intel_connector;
2981
2982         type = DRM_MODE_CONNECTOR_DisplayPort;
2983         /*
2984          * FIXME : We need to initialize built-in panels before external panels.
2985          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2986          */
2987         switch (port) {
2988         case PORT_A:
2989                 type = DRM_MODE_CONNECTOR_eDP;
2990                 break;
2991         case PORT_C:
2992                 if (IS_VALLEYVIEW(dev))
2993                         type = DRM_MODE_CONNECTOR_eDP;
2994                 break;
2995         case PORT_D:
2996                 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
2997                         type = DRM_MODE_CONNECTOR_eDP;
2998                 break;
2999         default:        /* silence GCC warning */
3000                 break;
3001         }
3002
3003         /*
3004          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3005          * for DP the encoder type can be set by the caller to
3006          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3007          */
3008         if (type == DRM_MODE_CONNECTOR_eDP)
3009                 intel_encoder->type = INTEL_OUTPUT_EDP;
3010
3011         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3012                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3013                         port_name(port));
3014
3015         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3016         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3017
3018         connector->interlace_allowed = true;
3019         connector->doublescan_allowed = 0;
3020
3021         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3022                           ironlake_panel_vdd_work);
3023
3024         intel_connector_attach_encoder(intel_connector, intel_encoder);
3025         drm_sysfs_connector_add(connector);
3026
3027         if (HAS_DDI(dev))
3028                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3029         else
3030                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3031
3032         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3033         if (HAS_DDI(dev)) {
3034                 switch (intel_dig_port->port) {
3035                 case PORT_A:
3036                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3037                         break;
3038                 case PORT_B:
3039                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3040                         break;
3041                 case PORT_C:
3042                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3043                         break;
3044                 case PORT_D:
3045                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3046                         break;
3047                 default:
3048                         BUG();
3049                 }
3050         }
3051
3052         /* Set up the DDC bus. */
3053         switch (port) {
3054         case PORT_A:
3055                 intel_encoder->hpd_pin = HPD_PORT_A;
3056                 name = "DPDDC-A";
3057                 break;
3058         case PORT_B:
3059                 intel_encoder->hpd_pin = HPD_PORT_B;
3060                 name = "DPDDC-B";
3061                 break;
3062         case PORT_C:
3063                 intel_encoder->hpd_pin = HPD_PORT_C;
3064                 name = "DPDDC-C";
3065                 break;
3066         case PORT_D:
3067                 intel_encoder->hpd_pin = HPD_PORT_D;
3068                 name = "DPDDC-D";
3069                 break;
3070         default:
3071                 BUG();
3072         }
3073
3074         if (is_edp(intel_dp))
3075                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3076
3077         intel_dp_i2c_init(intel_dp, intel_connector, name);
3078
3079         /* Cache DPCD and EDID for edp. */
3080         if (is_edp(intel_dp)) {
3081                 bool ret;
3082                 struct drm_display_mode *scan;
3083                 struct edid *edid;
3084
3085                 ironlake_edp_panel_vdd_on(intel_dp);
3086                 ret = intel_dp_get_dpcd(intel_dp);
3087                 ironlake_edp_panel_vdd_off(intel_dp, false);
3088
3089                 if (ret) {
3090                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3091                                 dev_priv->no_aux_handshake =
3092                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3093                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3094                 } else {
3095                         /* if this fails, presume the device is a ghost */
3096                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
3097                         intel_dp_encoder_destroy(&intel_encoder->base);
3098                         intel_dp_destroy(connector);
3099                         return;
3100                 }
3101
3102                 /* We now know it's not a ghost, init power sequence regs. */
3103                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3104                                                               &power_seq);
3105
3106                 ironlake_edp_panel_vdd_on(intel_dp);
3107                 edid = drm_get_edid(connector, &intel_dp->adapter);
3108                 if (edid) {
3109                         if (drm_add_edid_modes(connector, edid)) {
3110                                 drm_mode_connector_update_edid_property(connector, edid);
3111                                 drm_edid_to_eld(connector, edid);
3112                         } else {
3113                                 kfree(edid);
3114                                 edid = ERR_PTR(-EINVAL);
3115                         }
3116                 } else {
3117                         edid = ERR_PTR(-ENOENT);
3118                 }
3119                 intel_connector->edid = edid;
3120
3121                 /* prefer fixed mode from EDID if available */
3122                 list_for_each_entry(scan, &connector->probed_modes, head) {
3123                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3124                                 fixed_mode = drm_mode_duplicate(dev, scan);
3125                                 break;
3126                         }
3127                 }
3128
3129                 /* fallback to VBT if available for eDP */
3130                 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3131                         fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
3132                         if (fixed_mode)
3133                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3134                 }
3135
3136                 ironlake_edp_panel_vdd_off(intel_dp, false);
3137         }
3138
3139         if (is_edp(intel_dp)) {
3140                 intel_panel_init(&intel_connector->panel, fixed_mode);
3141                 intel_panel_setup_backlight(connector);
3142         }
3143
3144         intel_dp_add_properties(intel_dp, connector);
3145
3146         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3147          * 0xd.  Failure to do so will result in spurious interrupts being
3148          * generated on the port when a cable is not attached.
3149          */
3150         if (IS_G4X(dev) && !IS_GM45(dev)) {
3151                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3152                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3153         }
3154 }
3155
3156 void
3157 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3158 {
3159         struct intel_digital_port *intel_dig_port;
3160         struct intel_encoder *intel_encoder;
3161         struct drm_encoder *encoder;
3162         struct intel_connector *intel_connector;
3163
3164         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3165         if (!intel_dig_port)
3166                 return;
3167
3168         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3169         if (!intel_connector) {
3170                 kfree(intel_dig_port);
3171                 return;
3172         }
3173
3174         intel_encoder = &intel_dig_port->base;
3175         encoder = &intel_encoder->base;
3176
3177         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3178                          DRM_MODE_ENCODER_TMDS);
3179         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
3180
3181         intel_encoder->compute_config = intel_dp_compute_config;
3182         intel_encoder->enable = intel_enable_dp;
3183         intel_encoder->pre_enable = intel_pre_enable_dp;
3184         intel_encoder->disable = intel_disable_dp;
3185         intel_encoder->post_disable = intel_post_disable_dp;
3186         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3187         if (IS_VALLEYVIEW(dev))
3188                 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3189
3190         intel_dig_port->port = port;
3191         intel_dig_port->dp.output_reg = output_reg;
3192
3193         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3194         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3195         intel_encoder->cloneable = false;
3196         intel_encoder->hot_plug = intel_dp_hot_plug;
3197
3198         intel_dp_init_connector(intel_dig_port, intel_connector);
3199 }