drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
 122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 123 MODULE_PARM_DESC(preliminary_hw_support,
 124                 "Enable preliminary hardware support. (default: false)");
 125
 126 int i915_disable_power_well __read_mostly = 0;
 127 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 128 MODULE_PARM_DESC(disable_power_well,
 129                  "Disable the power well when possible (default: false)");
 130
 131 static struct drm_driver driver;
 132 extern int intel_agp_enabled;
 133
 134 #define INTEL_VGA_DEVICE(id, info) {            \
 135         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 136         .class_mask = 0xff0000,                 \
 137         .vendor = 0x8086,                       \
 138         .device = id,                           \
 139         .subvendor = PCI_ANY_ID,                \
 140         .subdevice = PCI_ANY_ID,                \
 141         .driver_data = (unsigned long) info }
 142
 143 #define INTEL_QUANTA_VGA_DEVICE(info) {         \
 144         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 145         .class_mask = 0xff0000,                 \
 146         .vendor = 0x8086,                       \
 147         .device = 0x16a,                        \
 148         .subvendor = 0x152d,                    \
 149         .subdevice = 0x8990,                    \
 150         .driver_data = (unsigned long) info }
 151
 152
 153 static const struct intel_device_info intel_i830_info = {
 154         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 155         .has_overlay = 1, .overlay_needs_physical = 1,
 156 };
 157
 158 static const struct intel_device_info intel_845g_info = {
 159         .gen = 2, .num_pipes = 1,
 160         .has_overlay = 1, .overlay_needs_physical = 1,
 161 };
 162
 163 static const struct intel_device_info intel_i85x_info = {
 164         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 165         .cursor_needs_physical = 1,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167 };
 168
 169 static const struct intel_device_info intel_i865g_info = {
 170         .gen = 2, .num_pipes = 1,
 171         .has_overlay = 1, .overlay_needs_physical = 1,
 172 };
 173
 174 static const struct intel_device_info intel_i915g_info = {
 175         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 176         .has_overlay = 1, .overlay_needs_physical = 1,
 177 };
 178 static const struct intel_device_info intel_i915gm_info = {
 179         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 180         .cursor_needs_physical = 1,
 181         .has_overlay = 1, .overlay_needs_physical = 1,
 182         .supports_tv = 1,
 183 };
 184 static const struct intel_device_info intel_i945g_info = {
 185         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 186         .has_overlay = 1, .overlay_needs_physical = 1,
 187 };
 188 static const struct intel_device_info intel_i945gm_info = {
 189         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 190         .has_hotplug = 1, .cursor_needs_physical = 1,
 191         .has_overlay = 1, .overlay_needs_physical = 1,
 192         .supports_tv = 1,
 193 };
 194
 195 static const struct intel_device_info intel_i965g_info = {
 196         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 197         .has_hotplug = 1,
 198         .has_overlay = 1,
 199 };
 200
 201 static const struct intel_device_info intel_i965gm_info = {
 202         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 203         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 204         .has_overlay = 1,
 205         .supports_tv = 1,
 206 };
 207
 208 static const struct intel_device_info intel_g33_info = {
 209         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 210         .need_gfx_hws = 1, .has_hotplug = 1,
 211         .has_overlay = 1,
 212 };
 213
 214 static const struct intel_device_info intel_g45_info = {
 215         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 216         .has_pipe_cxsr = 1, .has_hotplug = 1,
 217         .has_bsd_ring = 1,
 218 };
 219
 220 static const struct intel_device_info intel_gm45_info = {
 221         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 222         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 223         .has_pipe_cxsr = 1, .has_hotplug = 1,
 224         .supports_tv = 1,
 225         .has_bsd_ring = 1,
 226 };
 227
 228 static const struct intel_device_info intel_pineview_info = {
 229         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 230         .need_gfx_hws = 1, .has_hotplug = 1,
 231         .has_overlay = 1,
 232 };
 233
 234 static const struct intel_device_info intel_ironlake_d_info = {
 235         .gen = 5, .num_pipes = 2,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_bsd_ring = 1,
 238 };
 239
 240 static const struct intel_device_info intel_ironlake_m_info = {
 241         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 242         .need_gfx_hws = 1, .has_hotplug = 1,
 243         .has_fbc = 1,
 244         .has_bsd_ring = 1,
 245 };
 246
 247 static const struct intel_device_info intel_sandybridge_d_info = {
 248         .gen = 6, .num_pipes = 2,
 249         .need_gfx_hws = 1, .has_hotplug = 1,
 250         .has_bsd_ring = 1,
 251         .has_blt_ring = 1,
 252         .has_llc = 1,
 253         .has_force_wake = 1,
 254 };
 255
 256 static const struct intel_device_info intel_sandybridge_m_info = {
 257         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 258         .need_gfx_hws = 1, .has_hotplug = 1,
 259         .has_fbc = 1,
 260         .has_bsd_ring = 1,
 261         .has_blt_ring = 1,
 262         .has_llc = 1,
 263         .has_force_wake = 1,
 264 };
 265
 266 #define GEN7_FEATURES  \
 267         .gen = 7, .num_pipes = 3, \
 268         .need_gfx_hws = 1, .has_hotplug = 1, \
 269         .has_bsd_ring = 1, \
 270         .has_blt_ring = 1, \
 271         .has_llc = 1, \
 272         .has_force_wake = 1
 273
 274 static const struct intel_device_info intel_ivybridge_d_info = {
 275         GEN7_FEATURES,
 276         .is_ivybridge = 1,
 277 };
 278
 279 static const struct intel_device_info intel_ivybridge_m_info = {
 280         GEN7_FEATURES,
 281         .is_ivybridge = 1,
 282         .is_mobile = 1,
 283         .has_fbc = 1,
 284 };
 285
 286 static const struct intel_device_info intel_ivybridge_q_info = {
 287         GEN7_FEATURES,
 288         .is_ivybridge = 1,
 289         .num_pipes = 0, /* legal, last one wins */
 290 };
 291
 292 static const struct intel_device_info intel_valleyview_m_info = {
 293         GEN7_FEATURES,
 294         .is_mobile = 1,
 295         .num_pipes = 2,
 296         .is_valleyview = 1,
 297         .display_mmio_offset = VLV_DISPLAY_BASE,
 298         .has_llc = 0, /* legal, last one wins */
 299 };
 300
 301 static const struct intel_device_info intel_valleyview_d_info = {
 302         GEN7_FEATURES,
 303         .num_pipes = 2,
 304         .is_valleyview = 1,
 305         .display_mmio_offset = VLV_DISPLAY_BASE,
 306         .has_llc = 0, /* legal, last one wins */
 307 };
 308
 309 static const struct intel_device_info intel_haswell_d_info = {
 310         GEN7_FEATURES,
 311         .is_haswell = 1,
 312         .has_ddi = 1,
 313         .has_fpga_dbg = 1,
 314 };
 315
 316 static const struct intel_device_info intel_haswell_m_info = {
 317         GEN7_FEATURES,
 318         .is_haswell = 1,
 319         .is_mobile = 1,
 320         .has_ddi = 1,
 321         .has_fpga_dbg = 1,
 322         .has_fbc = 1,
 323 };
 324
 325 static const struct pci_device_id pciidlist[] = {               /* aka */
 326         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 327         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 328         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 329         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 330         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 331         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 332         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 333         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 334         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 335         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 336         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 337         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 338         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 339         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 340         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 341         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 342         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 343         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 344         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 345         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 346         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 347         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 348         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 349         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 350         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 351         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 352         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 353         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 354         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 355         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 356         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 357         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 358         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 359         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 360         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 361         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 362         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 363         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 364         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 365         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 366         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 367         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 368         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 369         INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
 370         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 371         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 372         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 373         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 374         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 375         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 376         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 377         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 378         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 379         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 380         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 381         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 382         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 383         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 384         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 385         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 386         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 387         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 388         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 389         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 390         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 391         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 392         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 393         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 394         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 395         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 396         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 397         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 398         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
 399         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
 400         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 401         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
 402         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
 403         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 404         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
 405         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
 406         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 407         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 408         INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
 409         INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
 410         INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
 411         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 412         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 413         {0, 0, 0}
 414 };
 415
 416 #if defined(CONFIG_DRM_I915_KMS)
 417 MODULE_DEVICE_TABLE(pci, pciidlist);
 418 #endif
 419
 420 void intel_detect_pch(struct drm_device *dev)
 421 {
 422         struct drm_i915_private *dev_priv = dev->dev_private;
 423         struct pci_dev *pch;
 424
 425         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 426          * (which really amounts to a PCH but no South Display).
 427          */
 428         if (INTEL_INFO(dev)->num_pipes == 0) {
 429                 dev_priv->pch_type = PCH_NOP;
 430                 dev_priv->num_pch_pll = 0;
 431                 return;
 432         }
 433
 434         /*
 435          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 436          * make graphics device passthrough work easy for VMM, that only
 437          * need to expose ISA bridge to let driver know the real hardware
 438          * underneath. This is a requirement from virtualization team.
 439          */
 440         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 441         if (pch) {
 442                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 443                         unsigned short id;
 444                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 445                         dev_priv->pch_id = id;
 446
 447                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 448                                 dev_priv->pch_type = PCH_IBX;
 449                                 dev_priv->num_pch_pll = 2;
 450                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 451                                 WARN_ON(!IS_GEN5(dev));
 452                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 453                                 dev_priv->pch_type = PCH_CPT;
 454                                 dev_priv->num_pch_pll = 2;
 455                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 456                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 457                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 458                                 /* PantherPoint is CPT compatible */
 459                                 dev_priv->pch_type = PCH_CPT;
 460                                 dev_priv->num_pch_pll = 2;
 461                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 462                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 463                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 464                                 dev_priv->pch_type = PCH_LPT;
 465                                 dev_priv->num_pch_pll = 0;
 466                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 467                                 WARN_ON(!IS_HASWELL(dev));
 468                                 WARN_ON(IS_ULT(dev));
 469                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 470                                 dev_priv->pch_type = PCH_LPT;
 471                                 dev_priv->num_pch_pll = 0;
 472                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 473                                 WARN_ON(!IS_HASWELL(dev));
 474                                 WARN_ON(!IS_ULT(dev));
 475                         }
 476                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 477                 }
 478                 pci_dev_put(pch);
 479         }
 480 }
 481
 482 bool i915_semaphore_is_enabled(struct drm_device *dev)
 483 {
 484         if (INTEL_INFO(dev)->gen < 6)
 485                 return 0;
 486
 487         if (i915_semaphores >= 0)
 488                 return i915_semaphores;
 489
 490 #ifdef CONFIG_INTEL_IOMMU
 491         /* Enable semaphores on SNB when IO remapping is off */
 492         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 493                 return false;
 494 #endif
 495
 496         return 1;
 497 }
 498
 499 static int i915_drm_freeze(struct drm_device *dev)
 500 {
 501         struct drm_i915_private *dev_priv = dev->dev_private;
 502         struct drm_crtc *crtc;
 503
 504         /* ignore lid events during suspend */
 505         mutex_lock(&dev_priv->modeset_restore_lock);
 506         dev_priv->modeset_restore = MODESET_SUSPENDED;
 507         mutex_unlock(&dev_priv->modeset_restore_lock);
 508
 509         intel_set_power_well(dev, true);
 510
 511         drm_kms_helper_poll_disable(dev);
 512
 513         pci_save_state(dev->pdev);
 514
 515         /* If KMS is active, we do the leavevt stuff here */
 516         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 517                 int error = i915_gem_idle(dev);
 518                 if (error) {
 519                         dev_err(&dev->pdev->dev,
 520                                 "GEM idle failed, resume might fail\n");
 521                         return error;
 522                 }
 523
 524                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 525
 526                 drm_irq_uninstall(dev);
 527                 dev_priv->enable_hotplug_processing = false;
 528                 /*
 529                  * Disable CRTCs directly since we want to preserve sw state
 530                  * for _thaw.
 531                  */
 532                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 533                         dev_priv->display.crtc_disable(crtc);
 534
 535                 intel_modeset_suspend_hw(dev);
 536         }
 537
 538         i915_save_state(dev);
 539
 540         intel_opregion_fini(dev);
 541
 542         console_lock();
 543         intel_fbdev_set_suspend(dev, 1);
 544         console_unlock();
 545
 546         return 0;
 547 }
 548
 549 int i915_suspend(struct drm_device *dev, pm_message_t state)
 550 {
 551         int error;
 552
 553         if (!dev || !dev->dev_private) {
 554                 DRM_ERROR("dev: %p\n", dev);
 555                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 556                 return -ENODEV;
 557         }
 558
 559         if (state.event == PM_EVENT_PRETHAW)
 560                 return 0;
 561
 562
 563         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 564                 return 0;
 565
 566         error = i915_drm_freeze(dev);
 567         if (error)
 568                 return error;
 569
 570         if (state.event == PM_EVENT_SUSPEND) {
 571                 /* Shut down the device */
 572                 pci_disable_device(dev->pdev);
 573                 pci_set_power_state(dev->pdev, PCI_D3hot);
 574         }
 575
 576         return 0;
 577 }
 578
 579 void intel_console_resume(struct work_struct *work)
 580 {
 581         struct drm_i915_private *dev_priv =
 582                 container_of(work, struct drm_i915_private,
 583                              console_resume_work);
 584         struct drm_device *dev = dev_priv->dev;
 585
 586         console_lock();
 587         intel_fbdev_set_suspend(dev, 0);
 588         console_unlock();
 589 }
 590
 591 static void intel_resume_hotplug(struct drm_device *dev)
 592 {
 593         struct drm_mode_config *mode_config = &dev->mode_config;
 594         struct intel_encoder *encoder;
 595
 596         mutex_lock(&mode_config->mutex);
 597         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 598
 599         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 600                 if (encoder->hot_plug)
 601                         encoder->hot_plug(encoder);
 602
 603         mutex_unlock(&mode_config->mutex);
 604
 605         /* Just fire off a uevent and let userspace tell us what to do */
 606         drm_helper_hpd_irq_event(dev);
 607 }
 608
 609 static int __i915_drm_thaw(struct drm_device *dev)
 610 {
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612         int error = 0;
 613
 614         i915_restore_state(dev);
 615         intel_opregion_setup(dev);
 616
 617         /* KMS EnterVT equivalent */
 618         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 619                 intel_init_pch_refclk(dev);
 620
 621                 mutex_lock(&dev->struct_mutex);
 622                 dev_priv->mm.suspended = 0;
 623
 624                 error = i915_gem_init_hw(dev);
 625                 mutex_unlock(&dev->struct_mutex);
 626
 627                 /* We need working interrupts for modeset enabling ... */
 628                 drm_irq_install(dev);
 629
 630                 intel_modeset_init_hw(dev);
 631
 632                 drm_modeset_lock_all(dev);
 633                 intel_modeset_setup_hw_state(dev, true);
 634                 drm_modeset_unlock_all(dev);
 635
 636                 /*
 637                  * ... but also need to make sure that hotplug processing
 638                  * doesn't cause havoc. Like in the driver load code we don't
 639                  * bother with the tiny race here where we might loose hotplug
 640                  * notifications.
 641                  * */
 642                 intel_hpd_init(dev);
 643                 dev_priv->enable_hotplug_processing = true;
 644                 /* Config may have changed between suspend and resume */
 645                 intel_resume_hotplug(dev);
 646         }
 647
 648         intel_opregion_init(dev);
 649
 650         /*
 651          * The console lock can be pretty contented on resume due
 652          * to all the printk activity.  Try to keep it out of the hot
 653          * path of resume if possible.
 654          */
 655         if (console_trylock()) {
 656                 intel_fbdev_set_suspend(dev, 0);
 657                 console_unlock();
 658         } else {
 659                 schedule_work(&dev_priv->console_resume_work);
 660         }
 661
 662         mutex_lock(&dev_priv->modeset_restore_lock);
 663         dev_priv->modeset_restore = MODESET_DONE;
 664         mutex_unlock(&dev_priv->modeset_restore_lock);
 665         return error;
 666 }
 667
 668 static int i915_drm_thaw(struct drm_device *dev)
 669 {
 670         int error = 0;
 671
 672         intel_gt_reset(dev);
 673
 674         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 675                 mutex_lock(&dev->struct_mutex);
 676                 i915_gem_restore_gtt_mappings(dev);
 677                 mutex_unlock(&dev->struct_mutex);
 678         }
 679
 680         __i915_drm_thaw(dev);
 681
 682         return error;
 683 }
 684
 685 int i915_resume(struct drm_device *dev)
 686 {
 687         struct drm_i915_private *dev_priv = dev->dev_private;
 688         int ret;
 689
 690         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 691                 return 0;
 692
 693         if (pci_enable_device(dev->pdev))
 694                 return -EIO;
 695
 696         pci_set_master(dev->pdev);
 697
 698         intel_gt_reset(dev);
 699
 700         /*
 701          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 702          * earlier) need this since the BIOS might clear all our scratch PTEs.
 703          */
 704         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 705             !dev_priv->opregion.header) {
 706                 mutex_lock(&dev->struct_mutex);
 707                 i915_gem_restore_gtt_mappings(dev);
 708                 mutex_unlock(&dev->struct_mutex);
 709         }
 710
 711         ret = __i915_drm_thaw(dev);
 712         if (ret)
 713                 return ret;
 714
 715         drm_kms_helper_poll_enable(dev);
 716         return 0;
 717 }
 718
 719 static int i8xx_do_reset(struct drm_device *dev)
 720 {
 721         struct drm_i915_private *dev_priv = dev->dev_private;
 722
 723         if (IS_I85X(dev))
 724                 return -ENODEV;
 725
 726         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 727         POSTING_READ(D_STATE);
 728
 729         if (IS_I830(dev) || IS_845G(dev)) {
 730                 I915_WRITE(DEBUG_RESET_I830,
 731                            DEBUG_RESET_DISPLAY |
 732                            DEBUG_RESET_RENDER |
 733                            DEBUG_RESET_FULL);
 734                 POSTING_READ(DEBUG_RESET_I830);
 735                 msleep(1);
 736
 737                 I915_WRITE(DEBUG_RESET_I830, 0);
 738                 POSTING_READ(DEBUG_RESET_I830);
 739         }
 740
 741         msleep(1);
 742
 743         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 744         POSTING_READ(D_STATE);
 745
 746         return 0;
 747 }
 748
 749 static int i965_reset_complete(struct drm_device *dev)
 750 {
 751         u8 gdrst;
 752         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 753         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 754 }
 755
 756 static int i965_do_reset(struct drm_device *dev)
 757 {
 758         int ret;
 759         u8 gdrst;
 760
 761         /*
 762          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 763          * well as the reset bit (GR/bit 0).  Setting the GR bit
 764          * triggers the reset; when done, the hardware will clear it.
 765          */
 766         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 767         pci_write_config_byte(dev->pdev, I965_GDRST,
 768                               gdrst | GRDOM_RENDER |
 769                               GRDOM_RESET_ENABLE);
 770         ret =  wait_for(i965_reset_complete(dev), 500);
 771         if (ret)
 772                 return ret;
 773
 774         /* We can't reset render&media without also resetting display ... */
 775         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 776         pci_write_config_byte(dev->pdev, I965_GDRST,
 777                               gdrst | GRDOM_MEDIA |
 778                               GRDOM_RESET_ENABLE);
 779
 780         return wait_for(i965_reset_complete(dev), 500);
 781 }
 782
 783 static int ironlake_do_reset(struct drm_device *dev)
 784 {
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         u32 gdrst;
 787         int ret;
 788
 789         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 790         gdrst &= ~GRDOM_MASK;
 791         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 792                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 793         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 794         if (ret)
 795                 return ret;
 796
 797         /* We can't reset render&media without also resetting display ... */
 798         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 799         gdrst &= ~GRDOM_MASK;
 800         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 801                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 802         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 803 }
 804
 805 static int gen6_do_reset(struct drm_device *dev)
 806 {
 807         struct drm_i915_private *dev_priv = dev->dev_private;
 808         int     ret;
 809         unsigned long irqflags;
 810
 811         /* Hold gt_lock across reset to prevent any register access
 812          * with forcewake not set correctly
 813          */
 814         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 815
 816         /* Reset the chip */
 817
 818         /* GEN6_GDRST is not in the gt power well, no need to check
 819          * for fifo space for the write or forcewake the chip for
 820          * the read
 821          */
 822         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 823
 824         /* Spin waiting for the device to ack the reset request */
 825         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 826
 827         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 828         if (dev_priv->forcewake_count)
 829                 dev_priv->gt.force_wake_get(dev_priv);
 830         else
 831                 dev_priv->gt.force_wake_put(dev_priv);
 832
 833         /* Restore fifo count */
 834         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 835
 836         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 837         return ret;
 838 }
 839
 840 int intel_gpu_reset(struct drm_device *dev)
 841 {
 842         struct drm_i915_private *dev_priv = dev->dev_private;
 843         int ret = -ENODEV;
 844
 845         switch (INTEL_INFO(dev)->gen) {
 846         case 7:
 847         case 6:
 848                 ret = gen6_do_reset(dev);
 849                 break;
 850         case 5:
 851                 ret = ironlake_do_reset(dev);
 852                 break;
 853         case 4:
 854                 ret = i965_do_reset(dev);
 855                 break;
 856         case 2:
 857                 ret = i8xx_do_reset(dev);
 858                 break;
 859         }
 860
 861         /* Also reset the gpu hangman. */
 862         if (dev_priv->gpu_error.stop_rings) {
 863                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 864                 dev_priv->gpu_error.stop_rings = 0;
 865                 if (ret == -ENODEV) {
 866                         DRM_ERROR("Reset not implemented, but ignoring "
 867                                   "error for simulated gpu hangs\n");
 868                         ret = 0;
 869                 }
 870         }
 871
 872         return ret;
 873 }
 874
 875 /**
 876  * i915_reset - reset chip after a hang
 877  * @dev: drm device to reset
 878  *
 879  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 880  * reset or otherwise an error code.
 881  *
 882  * Procedure is fairly simple:
 883  *   - reset the chip using the reset reg
 884  *   - re-init context state
 885  *   - re-init hardware status page
 886  *   - re-init ring buffer
 887  *   - re-init interrupt state
 888  *   - re-init display
 889  */
 890 int i915_reset(struct drm_device *dev)
 891 {
 892         drm_i915_private_t *dev_priv = dev->dev_private;
 893         int ret;
 894
 895         if (!i915_try_reset)
 896                 return 0;
 897
 898         mutex_lock(&dev->struct_mutex);
 899
 900         i915_gem_reset(dev);
 901
 902         ret = -ENODEV;
 903         if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
 904                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 905         else
 906                 ret = intel_gpu_reset(dev);
 907
 908         dev_priv->gpu_error.last_reset = get_seconds();
 909         if (ret) {
 910                 DRM_ERROR("Failed to reset chip.\n");
 911                 mutex_unlock(&dev->struct_mutex);
 912                 return ret;
 913         }
 914
 915         /* Ok, now get things going again... */
 916
 917         /*
 918          * Everything depends on having the GTT running, so we need to start
 919          * there.  Fortunately we don't need to do this unless we reset the
 920          * chip at a PCI level.
 921          *
 922          * Next we need to restore the context, but we don't use those
 923          * yet either...
 924          *
 925          * Ring buffer needs to be re-initialized in the KMS case, or if X
 926          * was running at the time of the reset (i.e. we weren't VT
 927          * switched away).
 928          */
 929         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 930                         !dev_priv->mm.suspended) {
 931                 struct intel_ring_buffer *ring;
 932                 int i;
 933
 934                 dev_priv->mm.suspended = 0;
 935
 936                 i915_gem_init_swizzling(dev);
 937
 938                 for_each_ring(ring, dev_priv, i)
 939                         ring->init(ring);
 940
 941                 i915_gem_context_init(dev);
 942                 if (dev_priv->mm.aliasing_ppgtt) {
 943                         ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
 944                         if (ret)
 945                                 i915_gem_cleanup_aliasing_ppgtt(dev);
 946                 }
 947
 948                 /*
 949                  * It would make sense to re-init all the other hw state, at
 950                  * least the rps/rc6/emon init done within modeset_init_hw. For
 951                  * some unknown reason, this blows up my ilk, so don't.
 952                  */
 953
 954                 mutex_unlock(&dev->struct_mutex);
 955
 956                 drm_irq_uninstall(dev);
 957                 drm_irq_install(dev);
 958                 intel_hpd_init(dev);
 959         } else {
 960                 mutex_unlock(&dev->struct_mutex);
 961         }
 962
 963         return 0;
 964 }
 965
 966 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 967 {
 968         struct intel_device_info *intel_info =
 969                 (struct intel_device_info *) ent->driver_data;
 970
 971         /* Only bind to function 0 of the device. Early generations
 972          * used function 1 as a placeholder for multi-head. This causes
 973          * us confusion instead, especially on the systems where both
 974          * functions have the same PCI-ID!
 975          */
 976         if (PCI_FUNC(pdev->devfn))
 977                 return -ENODEV;
 978
 979         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 980          * implementation for gen3 (and only gen3) that used legacy drm maps
 981          * (gasp!) to share buffers between X and the client. Hence we need to
 982          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 983         if (intel_info->gen != 3) {
 984                 driver.driver_features &=
 985                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 986         } else if (!intel_agp_enabled) {
 987                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 988                 return -ENODEV;
 989         }
 990
 991         return drm_get_pci_dev(pdev, ent, &driver);
 992 }
 993
 994 static void
 995 i915_pci_remove(struct pci_dev *pdev)
 996 {
 997         struct drm_device *dev = pci_get_drvdata(pdev);
 998
 999         drm_put_dev(dev);
1000 }
1001
1002 static int i915_pm_suspend(struct device *dev)
1003 {
1004         struct pci_dev *pdev = to_pci_dev(dev);
1005         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1006         int error;
1007
1008         if (!drm_dev || !drm_dev->dev_private) {
1009                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1010                 return -ENODEV;
1011         }
1012
1013         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1014                 return 0;
1015
1016         error = i915_drm_freeze(drm_dev);
1017         if (error)
1018                 return error;
1019
1020         pci_disable_device(pdev);
1021         pci_set_power_state(pdev, PCI_D3hot);
1022
1023         return 0;
1024 }
1025
1026 static int i915_pm_resume(struct device *dev)
1027 {
1028         struct pci_dev *pdev = to_pci_dev(dev);
1029         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1030
1031         return i915_resume(drm_dev);
1032 }
1033
1034 static int i915_pm_freeze(struct device *dev)
1035 {
1036         struct pci_dev *pdev = to_pci_dev(dev);
1037         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1038
1039         if (!drm_dev || !drm_dev->dev_private) {
1040                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1041                 return -ENODEV;
1042         }
1043
1044         return i915_drm_freeze(drm_dev);
1045 }
1046
1047 static int i915_pm_thaw(struct device *dev)
1048 {
1049         struct pci_dev *pdev = to_pci_dev(dev);
1050         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1051
1052         return i915_drm_thaw(drm_dev);
1053 }
1054
1055 static int i915_pm_poweroff(struct device *dev)
1056 {
1057         struct pci_dev *pdev = to_pci_dev(dev);
1058         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1059
1060         return i915_drm_freeze(drm_dev);
1061 }
1062
1063 static const struct dev_pm_ops i915_pm_ops = {
1064         .suspend = i915_pm_suspend,
1065         .resume = i915_pm_resume,
1066         .freeze = i915_pm_freeze,
1067         .thaw = i915_pm_thaw,
1068         .poweroff = i915_pm_poweroff,
1069         .restore = i915_pm_resume,
1070 };
1071
1072 static const struct vm_operations_struct i915_gem_vm_ops = {
1073         .fault = i915_gem_fault,
1074         .open = drm_gem_vm_open,
1075         .close = drm_gem_vm_close,
1076 };
1077
1078 static const struct file_operations i915_driver_fops = {
1079         .owner = THIS_MODULE,
1080         .open = drm_open,
1081         .release = drm_release,
1082         .unlocked_ioctl = drm_ioctl,
1083         .mmap = drm_gem_mmap,
1084         .poll = drm_poll,
1085         .fasync = drm_fasync,
1086         .read = drm_read,
1087 #ifdef CONFIG_COMPAT
1088         .compat_ioctl = i915_compat_ioctl,
1089 #endif
1090         .llseek = noop_llseek,
1091 };
1092
1093 static struct drm_driver driver = {
1094         /* Don't use MTRRs here; the Xserver or userspace app should
1095          * deal with them for Intel hardware.
1096          */
1097         .driver_features =
1098             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1099             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1100         .load = i915_driver_load,
1101         .unload = i915_driver_unload,
1102         .open = i915_driver_open,
1103         .lastclose = i915_driver_lastclose,
1104         .preclose = i915_driver_preclose,
1105         .postclose = i915_driver_postclose,
1106
1107         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1108         .suspend = i915_suspend,
1109         .resume = i915_resume,
1110
1111         .device_is_agp = i915_driver_device_is_agp,
1112         .master_create = i915_master_create,
1113         .master_destroy = i915_master_destroy,
1114 #if defined(CONFIG_DEBUG_FS)
1115         .debugfs_init = i915_debugfs_init,
1116         .debugfs_cleanup = i915_debugfs_cleanup,
1117 #endif
1118         .gem_init_object = i915_gem_init_object,
1119         .gem_free_object = i915_gem_free_object,
1120         .gem_vm_ops = &i915_gem_vm_ops,
1121
1122         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1123         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1124         .gem_prime_export = i915_gem_prime_export,
1125         .gem_prime_import = i915_gem_prime_import,
1126
1127         .dumb_create = i915_gem_dumb_create,
1128         .dumb_map_offset = i915_gem_mmap_gtt,
1129         .dumb_destroy = i915_gem_dumb_destroy,
1130         .ioctls = i915_ioctls,
1131         .fops = &i915_driver_fops,
1132         .name = DRIVER_NAME,
1133         .desc = DRIVER_DESC,
1134         .date = DRIVER_DATE,
1135         .major = DRIVER_MAJOR,
1136         .minor = DRIVER_MINOR,
1137         .patchlevel = DRIVER_PATCHLEVEL,
1138 };
1139
1140 static struct pci_driver i915_pci_driver = {
1141         .name = DRIVER_NAME,
1142         .id_table = pciidlist,
1143         .probe = i915_pci_probe,
1144         .remove = i915_pci_remove,
1145         .driver.pm = &i915_pm_ops,
1146 };
1147
1148 static int __init i915_init(void)
1149 {
1150         driver.num_ioctls = i915_max_ioctl;
1151
1152         /*
1153          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1154          * explicitly disabled with the module pararmeter.
1155          *
1156          * Otherwise, just follow the parameter (defaulting to off).
1157          *
1158          * Allow optional vga_text_mode_force boot option to override
1159          * the default behavior.
1160          */
1161 #if defined(CONFIG_DRM_I915_KMS)
1162         if (i915_modeset != 0)
1163                 driver.driver_features |= DRIVER_MODESET;
1164 #endif
1165         if (i915_modeset == 1)
1166                 driver.driver_features |= DRIVER_MODESET;
1167
1168 #ifdef CONFIG_VGA_CONSOLE
1169         if (vgacon_text_force() && i915_modeset == -1)
1170                 driver.driver_features &= ~DRIVER_MODESET;
1171 #endif
1172
1173         if (!(driver.driver_features & DRIVER_MODESET))
1174                 driver.get_vblank_timestamp = NULL;
1175
1176         return drm_pci_init(&driver, &i915_pci_driver);
1177 }
1178
1179 static void __exit i915_exit(void)
1180 {
1181         drm_pci_exit(&driver, &i915_pci_driver);
1182 }
1183
1184 module_init(i915_init);
1185 module_exit(i915_exit);
1186
1187 MODULE_AUTHOR(DRIVER_AUTHOR);
1188 MODULE_DESCRIPTION(DRIVER_DESC);
1189 MODULE_LICENSE("GPL and additional rights");
1190
1191 /* We give fast paths for the really cool registers */
1192 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1193         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1194          ((reg) < 0x40000) &&            \
1195          ((reg) != FORCEWAKE))
1196 static void
1197 ilk_dummy_write(struct drm_i915_private *dev_priv)
1198 {
1199         /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
1200          * the chip from rc6 before touching it for real. MI_MODE is masked,
1201          * hence harmless to write 0 into. */
1202         I915_WRITE_NOTRACE(MI_MODE, 0);
1203 }
1204
1205 static void
1206 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1207 {
1208         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
1209             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1210                 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1211                           reg);
1212                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1213         }
1214 }
1215
1216 static void
1217 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1218 {
1219         if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
1220             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1221                 DRM_ERROR("Unclaimed write to %x\n", reg);
1222                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1223         }
1224 }
1225
1226 #define __i915_read(x, y) \
1227 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1228         u##x val = 0; \
1229         if (IS_GEN5(dev_priv->dev)) \
1230                 ilk_dummy_write(dev_priv); \
1231         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1232                 unsigned long irqflags; \
1233                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1234                 if (dev_priv->forcewake_count == 0) \
1235                         dev_priv->gt.force_wake_get(dev_priv); \
1236                 val = read##y(dev_priv->regs + reg); \
1237                 if (dev_priv->forcewake_count == 0) \
1238                         dev_priv->gt.force_wake_put(dev_priv); \
1239                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1240         } else { \
1241                 val = read##y(dev_priv->regs + reg); \
1242         } \
1243         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1244         return val; \
1245 }
1246
1247 __i915_read(8, b)
1248 __i915_read(16, w)
1249 __i915_read(32, l)
1250 __i915_read(64, q)
1251 #undef __i915_read
1252
1253 #define __i915_write(x, y) \
1254 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1255         u32 __fifo_ret = 0; \
1256         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1257         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1258                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1259         } \
1260         if (IS_GEN5(dev_priv->dev)) \
1261                 ilk_dummy_write(dev_priv); \
1262         hsw_unclaimed_reg_clear(dev_priv, reg); \
1263         write##y(val, dev_priv->regs + reg); \
1264         if (unlikely(__fifo_ret)) { \
1265                 gen6_gt_check_fifodbg(dev_priv); \
1266         } \
1267         hsw_unclaimed_reg_check(dev_priv, reg); \
1268 }
1269 __i915_write(8, b)
1270 __i915_write(16, w)
1271 __i915_write(32, l)
1272 __i915_write(64, q)
1273 #undef __i915_write
1274
1275 static const struct register_whitelist {
1276         uint64_t offset;
1277         uint32_t size;
1278         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1279 } whitelist[] = {
1280         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1281 };
1282
1283 int i915_reg_read_ioctl(struct drm_device *dev,
1284                         void *data, struct drm_file *file)
1285 {
1286         struct drm_i915_private *dev_priv = dev->dev_private;
1287         struct drm_i915_reg_read *reg = data;
1288         struct register_whitelist const *entry = whitelist;
1289         int i;
1290
1291         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1292                 if (entry->offset == reg->offset &&
1293                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1294                         break;
1295         }
1296
1297         if (i == ARRAY_SIZE(whitelist))
1298                 return -EINVAL;
1299
1300         switch (entry->size) {
1301         case 8:
1302                 reg->val = I915_READ64(reg->offset);
1303                 break;
1304         case 4:
1305                 reg->val = I915_READ(reg->offset);
1306                 break;
1307         case 2:
1308                 reg->val = I915_READ16(reg->offset);
1309                 break;
1310         case 1:
1311                 reg->val = I915_READ8(reg->offset);
1312                 break;
1313         default:
1314                 WARN_ON(1);
1315                 return -EINVAL;
1316         }
1317
1318         return 0;
1319 }