drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "sid.h"
  27 #include "r600_dpm.h"
  28 #include "si_dpm.h"
  29 #include "atom.h"
  30 #include <linux/math64.h>
  31 #include <linux/seq_file.h>
  32
  33 #define MC_CG_ARB_FREQ_F0           0x0a
  34 #define MC_CG_ARB_FREQ_F1           0x0b
  35 #define MC_CG_ARB_FREQ_F2           0x0c
  36 #define MC_CG_ARB_FREQ_F3           0x0d
  37
  38 #define SMC_RAM_END                 0x20000
  39
  40 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  41
  42 static const struct si_cac_config_reg cac_weights_tahiti[] =
  43 {
  44         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  45         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  46         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  48         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  49         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  55         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  57         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  58         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  60         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  62         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  63         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  64         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  66         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  67         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  76         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  79         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  80         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  82         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  83         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  85         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 104         { 0xFFFFFFFF }
 105 };
 106
 107 static const struct si_cac_config_reg lcac_tahiti[] =
 108 {
 109         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 110         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 111         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 113         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 115         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 117         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 119         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 123         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 125         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 127         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 129         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 133         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 137         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 139         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 141         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 143         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 145         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 147         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 149         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 151         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 153         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 155         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 157         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 161         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 163         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 165         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 167         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 169         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 173         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 175         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 177         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 179         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 183         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 185         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 187         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 189         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 191         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 195         { 0xFFFFFFFF }
 196
 197 };
 198
 199 static const struct si_cac_config_reg cac_override_tahiti[] =
 200 {
 201         { 0xFFFFFFFF }
 202 };
 203
 204 static const struct si_powertune_data powertune_data_tahiti =
 205 {
 206         ((1 << 16) | 27027),
 207         6,
 208         0,
 209         4,
 210         95,
 211         {
 212                 0UL,
 213                 0UL,
 214                 4521550UL,
 215                 309631529UL,
 216                 -1270850L,
 217                 4513710L,
 218                 40
 219         },
 220         595000000UL,
 221         12,
 222         {
 223                 0,
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0
 231         },
 232         true
 233 };
 234
 235 static const struct si_dte_data dte_data_tahiti =
 236 {
 237         { 1159409, 0, 0, 0, 0 },
 238         { 777, 0, 0, 0, 0 },
 239         2,
 240         54000,
 241         127000,
 242         25,
 243         2,
 244         10,
 245         13,
 246         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 247         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 248         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 249         85,
 250         false
 251 };
 252
 253 static const struct si_dte_data dte_data_tahiti_le =
 254 {
 255         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 256         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 257         0x5,
 258         0xAFC8,
 259         0x64,
 260         0x32,
 261         1,
 262         0,
 263         0x10,
 264         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 265         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 266         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 267         85,
 268         true
 269 };
 270
 271 static const struct si_dte_data dte_data_tahiti_pro =
 272 {
 273         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 274         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 275         5,
 276         45000,
 277         100,
 278         0xA,
 279         1,
 280         0,
 281         0x10,
 282         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 283         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 284         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 285         90,
 286         true
 287 };
 288
 289 static const struct si_dte_data dte_data_new_zealand =
 290 {
 291         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 292         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 293         0x5,
 294         0xAFC8,
 295         0x69,
 296         0x32,
 297         1,
 298         0,
 299         0x10,
 300         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 301         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 302         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 303         85,
 304         true
 305 };
 306
 307 static const struct si_dte_data dte_data_aruba_pro =
 308 {
 309         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 310         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 311         5,
 312         45000,
 313         100,
 314         0xA,
 315         1,
 316         0,
 317         0x10,
 318         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 319         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 320         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 321         90,
 322         true
 323 };
 324
 325 static const struct si_dte_data dte_data_malta =
 326 {
 327         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 328         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 329         5,
 330         45000,
 331         100,
 332         0xA,
 333         1,
 334         0,
 335         0x10,
 336         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 337         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 338         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 339         90,
 340         true
 341 };
 342
 343 struct si_cac_config_reg cac_weights_pitcairn[] =
 344 {
 345         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 346         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 347         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 348         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 349         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 350         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 351         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 352         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 353         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 354         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 355         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 356         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 357         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 358         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 359         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 360         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 361         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 363         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 364         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 365         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 366         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 367         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 368         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 369         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 370         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 371         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 372         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 373         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 374         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 376         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 377         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 378         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 379         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 380         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 381         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 382         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 383         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 384         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 385         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 405         { 0xFFFFFFFF }
 406 };
 407
 408 static const struct si_cac_config_reg lcac_pitcairn[] =
 409 {
 410         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 411         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 412         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 413         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 414         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 415         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 416         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 417         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 418         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 419         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 420         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 421         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 422         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 423         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 424         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 425         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 426         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 427         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 428         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 429         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 430         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 431         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 432         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 433         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 434         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 435         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 436         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 437         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 438         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 439         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 440         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 441         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 442         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 443         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 444         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 445         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 446         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 447         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 448         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 449         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 450         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 451         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 452         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 453         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 454         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 455         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 456         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 458         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 462         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 463         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 464         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 465         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 466         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 467         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 468         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 470         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 471         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 472         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 473         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 474         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 476         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 477         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 478         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 479         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 480         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 481         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 482         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 483         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 484         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 485         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 486         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 487         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 488         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 489         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 490         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 491         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 492         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 493         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 496         { 0xFFFFFFFF }
 497 };
 498
 499 static const struct si_cac_config_reg cac_override_pitcairn[] =
 500 {
 501     { 0xFFFFFFFF }
 502 };
 503
 504 static const struct si_powertune_data powertune_data_pitcairn =
 505 {
 506         ((1 << 16) | 27027),
 507         5,
 508         0,
 509         6,
 510         100,
 511         {
 512                 51600000UL,
 513                 1800000UL,
 514                 7194395UL,
 515                 309631529UL,
 516                 -1270850L,
 517                 4513710L,
 518                 100
 519         },
 520         117830498UL,
 521         12,
 522         {
 523                 0,
 524                 0,
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0
 531         },
 532         true
 533 };
 534
 535 static const struct si_dte_data dte_data_pitcairn =
 536 {
 537         { 0, 0, 0, 0, 0 },
 538         { 0, 0, 0, 0, 0 },
 539         0,
 540         0,
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 547         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         0,
 550         false
 551 };
 552
 553 static const struct si_dte_data dte_data_curacao_xt =
 554 {
 555         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 556         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 557         5,
 558         45000,
 559         100,
 560         0xA,
 561         1,
 562         0,
 563         0x10,
 564         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 565         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 566         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 567         90,
 568         true
 569 };
 570
 571 static const struct si_dte_data dte_data_curacao_pro =
 572 {
 573         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 574         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 575         5,
 576         45000,
 577         100,
 578         0xA,
 579         1,
 580         0,
 581         0x10,
 582         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 583         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 584         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 585         90,
 586         true
 587 };
 588
 589 static const struct si_dte_data dte_data_neptune_xt =
 590 {
 591         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 592         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 593         5,
 594         45000,
 595         100,
 596         0xA,
 597         1,
 598         0,
 599         0x10,
 600         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 601         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 602         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 603         90,
 604         true
 605 };
 606
 607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 608 {
 609         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 610         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 611         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 612         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 613         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 614         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 615         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 616         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 617         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 618         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 619         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 620         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 621         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 622         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 623         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 624         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 625         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 626         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 627         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 628         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 629         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 630         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 631         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 632         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 633         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 634         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 635         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 636         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 637         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 638         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 639         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 640         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 641         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 642         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 643         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 644         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 645         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 646         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 647         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 648         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 649         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 650         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 651         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 652         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 669         { 0xFFFFFFFF }
 670 };
 671
 672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 673 {
 674         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 675         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 676         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 677         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 678         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 679         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 680         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 681         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 682         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 683         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 684         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 685         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 686         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 687         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 688         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 689         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 690         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 691         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 692         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 693         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 694         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 695         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 696         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 697         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 698         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 699         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 700         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 701         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 702         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 703         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 704         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 705         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 706         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 707         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 708         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 709         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 710         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 711         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 712         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 713         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 714         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 715         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 716         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 717         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 734         { 0xFFFFFFFF }
 735 };
 736
 737 static const struct si_cac_config_reg cac_weights_heathrow[] =
 738 {
 739         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 740         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 741         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 743         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 745         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 746         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 747         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 748         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 749         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 750         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 752         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 753         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 754         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 755         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 756         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 757         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 758         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 759         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 760         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 761         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 762         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 763         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 764         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 765         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 766         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 767         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 768         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 769         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 770         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 771         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 772         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 773         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 774         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 775         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 776         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 777         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 778         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 779         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 780         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 781         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 782         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 799         { 0xFFFFFFFF }
 800 };
 801
 802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 803 {
 804         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 805         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 806         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 808         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 810         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 811         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 812         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 813         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 814         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 815         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 817         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 818         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 819         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 820         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 821         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 822         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 823         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 824         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 825         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 826         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 827         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 828         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 829         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 830         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 831         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 832         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 833         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 834         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 835         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 836         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 837         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 838         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 839         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 840         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 841         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 842         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 843         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 844         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 845         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 846         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 847         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 864         { 0xFFFFFFFF }
 865 };
 866
 867 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 868 {
 869         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 870         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 871         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 873         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 875         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 876         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 877         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 878         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 879         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 880         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 882         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 883         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 884         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 885         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 886         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 887         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 888         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 889         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 890         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 891         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 892         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 893         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 894         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 895         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 896         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 897         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 898         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 899         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 900         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 901         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 902         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 903         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 904         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 905         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 906         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 907         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 908         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 909         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 910         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 911         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 912         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 929         { 0xFFFFFFFF }
 930 };
 931
 932 static const struct si_cac_config_reg lcac_cape_verde[] =
 933 {
 934         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 935         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 936         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 937         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 938         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 939         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 940         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 941         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 942         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 943         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 944         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 947         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 948         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 949         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 950         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 951         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 952         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 953         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 954         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 959         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 962         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 963         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 964         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 965         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 966         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 967         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 968         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 969         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 970         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 971         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 972         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 973         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 974         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 975         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 976         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 979         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 980         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0xFFFFFFFF }
 989 };
 990
 991 static const struct si_cac_config_reg cac_override_cape_verde[] =
 992 {
 993     { 0xFFFFFFFF }
 994 };
 995
 996 static const struct si_powertune_data powertune_data_cape_verde =
 997 {
 998         ((1 << 16) | 0x6993),
 999         5,
1000         0,
1001         7,
1002         105,
1003         {
1004                 0UL,
1005                 0UL,
1006                 7194395UL,
1007                 309631529UL,
1008                 -1270850L,
1009                 4513710L,
1010                 100
1011         },
1012         117830498UL,
1013         12,
1014         {
1015                 0,
1016                 0,
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0
1023         },
1024         true
1025 };
1026
1027 static const struct si_dte_data dte_data_cape_verde =
1028 {
1029         { 0, 0, 0, 0, 0 },
1030         { 0, 0, 0, 0, 0 },
1031         0,
1032         0,
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         0,
1042         false
1043 };
1044
1045 static const struct si_dte_data dte_data_venus_xtx =
1046 {
1047         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1049         5,
1050         55000,
1051         0x69,
1052         0xA,
1053         1,
1054         0,
1055         0x3,
1056         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         90,
1060         true
1061 };
1062
1063 static const struct si_dte_data dte_data_venus_xt =
1064 {
1065         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1067         5,
1068         55000,
1069         0x69,
1070         0xA,
1071         1,
1072         0,
1073         0x3,
1074         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         90,
1078         true
1079 };
1080
1081 static const struct si_dte_data dte_data_venus_pro =
1082 {
1083         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1085         5,
1086         55000,
1087         0x69,
1088         0xA,
1089         1,
1090         0,
1091         0x3,
1092         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         90,
1096         true
1097 };
1098
1099 struct si_cac_config_reg cac_weights_oland[] =
1100 {
1101         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1102         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1103         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1104         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1105         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1106         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1107         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1108         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1110         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1111         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1112         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1113         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1114         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1115         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1116         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1117         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1118         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1119         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1120         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1121         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1122         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1123         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1124         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1125         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1126         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1127         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1128         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1130         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1131         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1132         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1133         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1134         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1135         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1136         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1137         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1138         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1139         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1141         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1142         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1161         { 0xFFFFFFFF }
1162 };
1163
1164 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1165 {
1166         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1167         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1168         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1169         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1170         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1171         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1172         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1173         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1175         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1176         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1177         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1178         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1179         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1180         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1181         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1182         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1183         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1184         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1185         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1186         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1187         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1188         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1189         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1190         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1191         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1192         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1193         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1194         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1195         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1196         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1197         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1199         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1200         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1201         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1202         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1204         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1206         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1207         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1213         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1226         { 0xFFFFFFFF }
1227 };
1228
1229 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1230 {
1231         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1232         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1233         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1235         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1238         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1240         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1241         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1242         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1244         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1245         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1246         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1247         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1248         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1249         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1250         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1251         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1252         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1253         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1254         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1255         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1256         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1257         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1258         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1259         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1260         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1261         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1262         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1264         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1265         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1266         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1267         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1269         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1271         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1272         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1278         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1291         { 0xFFFFFFFF }
1292 };
1293
1294 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1295 {
1296         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1297         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1298         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1300         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1303         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1305         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1306         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1307         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1309         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1310         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1311         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1312         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1313         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1314         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1315         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1316         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1317         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1318         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1319         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1320         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1321         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1322         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1323         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1324         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1325         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1326         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1327         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1329         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1330         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1331         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1332         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1334         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1336         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1337         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1343         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1356         { 0xFFFFFFFF }
1357 };
1358
1359 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1360 {
1361         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1362         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1363         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1365         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1368         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1370         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1371         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1372         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1374         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1375         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1376         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1377         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1378         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1379         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1380         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1381         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1382         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1383         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1384         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1385         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1386         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1387         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1388         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1389         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1391         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1392         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1394         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1395         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1396         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1397         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1399         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1401         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1402         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1408         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1421         { 0xFFFFFFFF }
1422 };
1423
1424 static const struct si_cac_config_reg lcac_oland[] =
1425 {
1426         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1437         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0xFFFFFFFF }
1469 };
1470
1471 static const struct si_cac_config_reg lcac_mars_pro[] =
1472 {
1473         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1474         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1478         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1484         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1502         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0xFFFFFFFF }
1516 };
1517
1518 static const struct si_cac_config_reg cac_override_oland[] =
1519 {
1520         { 0xFFFFFFFF }
1521 };
1522
1523 static const struct si_powertune_data powertune_data_oland =
1524 {
1525         ((1 << 16) | 0x6993),
1526         5,
1527         0,
1528         7,
1529         105,
1530         {
1531                 0UL,
1532                 0UL,
1533                 7194395UL,
1534                 309631529UL,
1535                 -1270850L,
1536                 4513710L,
1537                 100
1538         },
1539         117830498UL,
1540         12,
1541         {
1542                 0,
1543                 0,
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0
1550         },
1551         true
1552 };
1553
1554 static const struct si_powertune_data powertune_data_mars_pro =
1555 {
1556         ((1 << 16) | 0x6993),
1557         5,
1558         0,
1559         7,
1560         105,
1561         {
1562                 0UL,
1563                 0UL,
1564                 7194395UL,
1565                 309631529UL,
1566                 -1270850L,
1567                 4513710L,
1568                 100
1569         },
1570         117830498UL,
1571         12,
1572         {
1573                 0,
1574                 0,
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0
1581         },
1582         true
1583 };
1584
1585 static const struct si_dte_data dte_data_oland =
1586 {
1587         { 0, 0, 0, 0, 0 },
1588         { 0, 0, 0, 0, 0 },
1589         0,
1590         0,
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         0,
1600         false
1601 };
1602
1603 static const struct si_dte_data dte_data_mars_pro =
1604 {
1605         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1607         5,
1608         55000,
1609         105,
1610         0xA,
1611         1,
1612         0,
1613         0x10,
1614         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1617         90,
1618         true
1619 };
1620
1621 static const struct si_dte_data dte_data_sun_xt =
1622 {
1623         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1625         5,
1626         55000,
1627         105,
1628         0xA,
1629         1,
1630         0,
1631         0x10,
1632         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1635         90,
1636         true
1637 };
1638
1639
1640 static const struct si_cac_config_reg cac_weights_hainan[] =
1641 {
1642         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1643         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1644         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1645         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1646         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1647         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1648         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1649         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1652         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1653         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1654         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1655         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1656         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1657         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1660         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1661         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1662         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1663         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1664         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1665         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1666         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1668         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1669         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1673         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1677         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1678         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1679         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1680         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1681         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1682         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1684         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1685         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1702         { 0xFFFFFFFF }
1703 };
1704
1705 static const struct si_powertune_data powertune_data_hainan =
1706 {
1707         ((1 << 16) | 0x6993),
1708         5,
1709         0,
1710         9,
1711         105,
1712         {
1713                 0UL,
1714                 0UL,
1715                 7194395UL,
1716                 309631529UL,
1717                 -1270850L,
1718                 4513710L,
1719                 100
1720         },
1721         117830498UL,
1722         12,
1723         {
1724                 0,
1725                 0,
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0
1732         },
1733         true
1734 };
1735
1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1740
1741 static int si_populate_voltage_value(struct radeon_device *rdev,
1742                                      const struct atom_voltage_table *table,
1743                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1744 static int si_get_std_voltage_value(struct radeon_device *rdev,
1745                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1746                                     u16 *std_voltage);
1747 static int si_write_smc_soft_register(struct radeon_device *rdev,
1748                                       u16 reg_offset, u32 value);
1749 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1750                                          struct rv7xx_pl *pl,
1751                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1752 static int si_calculate_sclk_params(struct radeon_device *rdev,
1753                                     u32 engine_clock,
1754                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1755
1756 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1757 {
1758         struct si_power_info *pi = rdev->pm.dpm.priv;
1759
1760         return pi;
1761 }
1762
1763 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1764                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1765 {
1766         s64 kt, kv, leakage_w, i_leakage, vddc;
1767         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1768         s64 tmp;
1769
1770         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1771         vddc = div64_s64(drm_int2fixp(v), 1000);
1772         temperature = div64_s64(drm_int2fixp(t), 1000);
1773
1774         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1775         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1776         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1777         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1778         t_ref = drm_int2fixp(coeff->t_ref);
1779
1780         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1781         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1782         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1783         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1784
1785         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1786
1787         *leakage = drm_fixp2int(leakage_w * 1000);
1788 }
1789
1790 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1791                                              const struct ni_leakage_coeffients *coeff,
1792                                              u16 v,
1793                                              s32 t,
1794                                              u32 i_leakage,
1795                                              u32 *leakage)
1796 {
1797         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1798 }
1799
1800 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1801                                                const u32 fixed_kt, u16 v,
1802                                                u32 ileakage, u32 *leakage)
1803 {
1804         s64 kt, kv, leakage_w, i_leakage, vddc;
1805
1806         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1807         vddc = div64_s64(drm_int2fixp(v), 1000);
1808
1809         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1810         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1811                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1812
1813         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1814
1815         *leakage = drm_fixp2int(leakage_w * 1000);
1816 }
1817
1818 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1819                                        const struct ni_leakage_coeffients *coeff,
1820                                        const u32 fixed_kt,
1821                                        u16 v,
1822                                        u32 i_leakage,
1823                                        u32 *leakage)
1824 {
1825         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1826 }
1827
1828
1829 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1830                                    struct si_dte_data *dte_data)
1831 {
1832         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1833         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1834         u32 k = dte_data->k;
1835         u32 t_max = dte_data->max_t;
1836         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1837         u32 t_0 = dte_data->t0;
1838         u32 i;
1839
1840         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1841                 dte_data->tdep_count = 3;
1842
1843                 for (i = 0; i < k; i++) {
1844                         dte_data->r[i] =
1845                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1846                                 (p_limit2  * (u32)100);
1847                 }
1848
1849                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1850
1851                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1852                         dte_data->tdep_r[i] = dte_data->r[4];
1853                 }
1854         } else {
1855                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1856         }
1857 }
1858
1859 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1860 {
1861         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1862         struct si_power_info *si_pi = si_get_pi(rdev);
1863         bool update_dte_from_pl2 = false;
1864
1865         if (rdev->family == CHIP_TAHITI) {
1866                 si_pi->cac_weights = cac_weights_tahiti;
1867                 si_pi->lcac_config = lcac_tahiti;
1868                 si_pi->cac_override = cac_override_tahiti;
1869                 si_pi->powertune_data = &powertune_data_tahiti;
1870                 si_pi->dte_data = dte_data_tahiti;
1871
1872                 switch (rdev->pdev->device) {
1873                 case 0x6798:
1874                         si_pi->dte_data.enable_dte_by_default = true;
1875                         break;
1876                 case 0x6799:
1877                         si_pi->dte_data = dte_data_new_zealand;
1878                         break;
1879                 case 0x6790:
1880                 case 0x6791:
1881                 case 0x6792:
1882                 case 0x679E:
1883                         si_pi->dte_data = dte_data_aruba_pro;
1884                         update_dte_from_pl2 = true;
1885                         break;
1886                 case 0x679B:
1887                         si_pi->dte_data = dte_data_malta;
1888                         update_dte_from_pl2 = true;
1889                         break;
1890                 case 0x679A:
1891                         si_pi->dte_data = dte_data_tahiti_pro;
1892                         update_dte_from_pl2 = true;
1893                         break;
1894                 default:
1895                         if (si_pi->dte_data.enable_dte_by_default == true)
1896                                 DRM_ERROR("DTE is not enabled!\n");
1897                         break;
1898                 }
1899         } else if (rdev->family == CHIP_PITCAIRN) {
1900                 switch (rdev->pdev->device) {
1901                 case 0x6810:
1902                 case 0x6818:
1903                         si_pi->cac_weights = cac_weights_pitcairn;
1904                         si_pi->lcac_config = lcac_pitcairn;
1905                         si_pi->cac_override = cac_override_pitcairn;
1906                         si_pi->powertune_data = &powertune_data_pitcairn;
1907                         si_pi->dte_data = dte_data_curacao_xt;
1908                         update_dte_from_pl2 = true;
1909                         break;
1910                 case 0x6819:
1911                 case 0x6811:
1912                         si_pi->cac_weights = cac_weights_pitcairn;
1913                         si_pi->lcac_config = lcac_pitcairn;
1914                         si_pi->cac_override = cac_override_pitcairn;
1915                         si_pi->powertune_data = &powertune_data_pitcairn;
1916                         si_pi->dte_data = dte_data_curacao_pro;
1917                         update_dte_from_pl2 = true;
1918                         break;
1919                 case 0x6800:
1920                 case 0x6806:
1921                         si_pi->cac_weights = cac_weights_pitcairn;
1922                         si_pi->lcac_config = lcac_pitcairn;
1923                         si_pi->cac_override = cac_override_pitcairn;
1924                         si_pi->powertune_data = &powertune_data_pitcairn;
1925                         si_pi->dte_data = dte_data_neptune_xt;
1926                         update_dte_from_pl2 = true;
1927                         break;
1928                 default:
1929                         si_pi->cac_weights = cac_weights_pitcairn;
1930                         si_pi->lcac_config = lcac_pitcairn;
1931                         si_pi->cac_override = cac_override_pitcairn;
1932                         si_pi->powertune_data = &powertune_data_pitcairn;
1933                         si_pi->dte_data = dte_data_pitcairn;
1934                         break;
1935                 }
1936         } else if (rdev->family == CHIP_VERDE) {
1937                 si_pi->lcac_config = lcac_cape_verde;
1938                 si_pi->cac_override = cac_override_cape_verde;
1939                 si_pi->powertune_data = &powertune_data_cape_verde;
1940
1941                 switch (rdev->pdev->device) {
1942                 case 0x683B:
1943                 case 0x683F:
1944                 case 0x6829:
1945                 case 0x6835:
1946                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1947                         si_pi->dte_data = dte_data_cape_verde;
1948                         break;
1949                 case 0x6825:
1950                 case 0x6827:
1951                         si_pi->cac_weights = cac_weights_heathrow;
1952                         si_pi->dte_data = dte_data_cape_verde;
1953                         break;
1954                 case 0x6824:
1955                 case 0x682D:
1956                         si_pi->cac_weights = cac_weights_chelsea_xt;
1957                         si_pi->dte_data = dte_data_cape_verde;
1958                         break;
1959                 case 0x682F:
1960                         si_pi->cac_weights = cac_weights_chelsea_pro;
1961                         si_pi->dte_data = dte_data_cape_verde;
1962                         break;
1963                 case 0x6820:
1964                         si_pi->cac_weights = cac_weights_heathrow;
1965                         si_pi->dte_data = dte_data_venus_xtx;
1966                         break;
1967                 case 0x6821:
1968                         si_pi->cac_weights = cac_weights_heathrow;
1969                         si_pi->dte_data = dte_data_venus_xt;
1970                         break;
1971                 case 0x6823:
1972                         si_pi->cac_weights = cac_weights_chelsea_pro;
1973                         si_pi->dte_data = dte_data_venus_pro;
1974                         break;
1975                 case 0x682B:
1976                         si_pi->cac_weights = cac_weights_chelsea_pro;
1977                         si_pi->dte_data = dte_data_venus_pro;
1978                         break;
1979                 default:
1980                         si_pi->cac_weights = cac_weights_cape_verde;
1981                         si_pi->dte_data = dte_data_cape_verde;
1982                         break;
1983                 }
1984         } else if (rdev->family == CHIP_OLAND) {
1985                 switch (rdev->pdev->device) {
1986                 case 0x6601:
1987                 case 0x6621:
1988                 case 0x6603:
1989                         si_pi->cac_weights = cac_weights_mars_pro;
1990                         si_pi->lcac_config = lcac_mars_pro;
1991                         si_pi->cac_override = cac_override_oland;
1992                         si_pi->powertune_data = &powertune_data_mars_pro;
1993                         si_pi->dte_data = dte_data_mars_pro;
1994                         update_dte_from_pl2 = true;
1995                         break;
1996                 case 0x6600:
1997                 case 0x6606:
1998                 case 0x6620:
1999                         si_pi->cac_weights = cac_weights_mars_xt;
2000                         si_pi->lcac_config = lcac_mars_pro;
2001                         si_pi->cac_override = cac_override_oland;
2002                         si_pi->powertune_data = &powertune_data_mars_pro;
2003                         si_pi->dte_data = dte_data_mars_pro;
2004                         update_dte_from_pl2 = true;
2005                         break;
2006                 case 0x6611:
2007                         si_pi->cac_weights = cac_weights_oland_pro;
2008                         si_pi->lcac_config = lcac_mars_pro;
2009                         si_pi->cac_override = cac_override_oland;
2010                         si_pi->powertune_data = &powertune_data_mars_pro;
2011                         si_pi->dte_data = dte_data_mars_pro;
2012                         update_dte_from_pl2 = true;
2013                         break;
2014                 case 0x6610:
2015                         si_pi->cac_weights = cac_weights_oland_xt;
2016                         si_pi->lcac_config = lcac_mars_pro;
2017                         si_pi->cac_override = cac_override_oland;
2018                         si_pi->powertune_data = &powertune_data_mars_pro;
2019                         si_pi->dte_data = dte_data_mars_pro;
2020                         update_dte_from_pl2 = true;
2021                         break;
2022                 default:
2023                         si_pi->cac_weights = cac_weights_oland;
2024                         si_pi->lcac_config = lcac_oland;
2025                         si_pi->cac_override = cac_override_oland;
2026                         si_pi->powertune_data = &powertune_data_oland;
2027                         si_pi->dte_data = dte_data_oland;
2028                         break;
2029                 }
2030         } else if (rdev->family == CHIP_HAINAN) {
2031                 si_pi->cac_weights = cac_weights_hainan;
2032                 si_pi->lcac_config = lcac_oland;
2033                 si_pi->cac_override = cac_override_oland;
2034                 si_pi->powertune_data = &powertune_data_hainan;
2035                 si_pi->dte_data = dte_data_sun_xt;
2036                 update_dte_from_pl2 = true;
2037         } else {
2038                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2039                 return;
2040         }
2041
2042         ni_pi->enable_power_containment = false;
2043         ni_pi->enable_cac = false;
2044         ni_pi->enable_sq_ramping = false;
2045         si_pi->enable_dte = false;
2046
2047         if (si_pi->powertune_data->enable_powertune_by_default) {
2048                 ni_pi->enable_power_containment= true;
2049                 ni_pi->enable_cac = true;
2050                 if (si_pi->dte_data.enable_dte_by_default) {
2051                         si_pi->enable_dte = true;
2052                         if (update_dte_from_pl2)
2053                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2054
2055                 }
2056                 ni_pi->enable_sq_ramping = true;
2057         }
2058
2059         ni_pi->driver_calculate_cac_leakage = true;
2060         ni_pi->cac_configuration_required = true;
2061
2062         if (ni_pi->cac_configuration_required) {
2063                 ni_pi->support_cac_long_term_average = true;
2064                 si_pi->dyn_powertune_data.l2_lta_window_size =
2065                         si_pi->powertune_data->l2_lta_window_size_default;
2066                 si_pi->dyn_powertune_data.lts_truncate =
2067                         si_pi->powertune_data->lts_truncate_default;
2068         } else {
2069                 ni_pi->support_cac_long_term_average = false;
2070                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2071                 si_pi->dyn_powertune_data.lts_truncate = 0;
2072         }
2073
2074         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2075 }
2076
2077 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2078 {
2079         return 1;
2080 }
2081
2082 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2083 {
2084         u32 xclk;
2085         u32 wintime;
2086         u32 cac_window;
2087         u32 cac_window_size;
2088
2089         xclk = radeon_get_xclk(rdev);
2090
2091         if (xclk == 0)
2092                 return 0;
2093
2094         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2095         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2096
2097         wintime = (cac_window_size * 100) / xclk;
2098
2099         return wintime;
2100 }
2101
2102 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2103 {
2104         return power_in_watts;
2105 }
2106
2107 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2108                                             bool adjust_polarity,
2109                                             u32 tdp_adjustment,
2110                                             u32 *tdp_limit,
2111                                             u32 *near_tdp_limit)
2112 {
2113         u32 adjustment_delta, max_tdp_limit;
2114
2115         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2116                 return -EINVAL;
2117
2118         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2119
2120         if (adjust_polarity) {
2121                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2122                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2123         } else {
2124                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2125                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2126                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2127                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2128                 else
2129                         *near_tdp_limit = 0;
2130         }
2131
2132         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2133                 return -EINVAL;
2134         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2135                 return -EINVAL;
2136
2137         return 0;
2138 }
2139
2140 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2141                                       struct radeon_ps *radeon_state)
2142 {
2143         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2144         struct si_power_info *si_pi = si_get_pi(rdev);
2145
2146         if (ni_pi->enable_power_containment) {
2147                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2148                 PP_SIslands_PAPMParameters *papm_parm;
2149                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2150                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2151                 u32 tdp_limit;
2152                 u32 near_tdp_limit;
2153                 int ret;
2154
2155                 if (scaling_factor == 0)
2156                         return -EINVAL;
2157
2158                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2159
2160                 ret = si_calculate_adjusted_tdp_limits(rdev,
2161                                                        false, /* ??? */
2162                                                        rdev->pm.dpm.tdp_adjustment,
2163                                                        &tdp_limit,
2164                                                        &near_tdp_limit);
2165                 if (ret)
2166                         return ret;
2167
2168                 smc_table->dpm2Params.TDPLimit =
2169                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2170                 smc_table->dpm2Params.NearTDPLimit =
2171                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2172                 smc_table->dpm2Params.SafePowerLimit =
2173                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2174
2175                 ret = si_copy_bytes_to_smc(rdev,
2176                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2177                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2178                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2179                                            sizeof(u32) * 3,
2180                                            si_pi->sram_end);
2181                 if (ret)
2182                         return ret;
2183
2184                 if (si_pi->enable_ppm) {
2185                         papm_parm = &si_pi->papm_parm;
2186                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2187                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2188                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2189                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2190                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2191                         papm_parm->PlatformPowerLimit = 0xffffffff;
2192                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2193
2194                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2195                                                    (u8 *)papm_parm,
2196                                                    sizeof(PP_SIslands_PAPMParameters),
2197                                                    si_pi->sram_end);
2198                         if (ret)
2199                                 return ret;
2200                 }
2201         }
2202         return 0;
2203 }
2204
2205 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2206                                         struct radeon_ps *radeon_state)
2207 {
2208         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2209         struct si_power_info *si_pi = si_get_pi(rdev);
2210
2211         if (ni_pi->enable_power_containment) {
2212                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2213                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2214                 int ret;
2215
2216                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2217
2218                 smc_table->dpm2Params.NearTDPLimit =
2219                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2220                 smc_table->dpm2Params.SafePowerLimit =
2221                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2222
2223                 ret = si_copy_bytes_to_smc(rdev,
2224                                            (si_pi->state_table_start +
2225                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2226                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2227                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2228                                            sizeof(u32) * 2,
2229                                            si_pi->sram_end);
2230                 if (ret)
2231                         return ret;
2232         }
2233
2234         return 0;
2235 }
2236
2237 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2238                                                const u16 prev_std_vddc,
2239                                                const u16 curr_std_vddc)
2240 {
2241         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2242         u64 prev_vddc = (u64)prev_std_vddc;
2243         u64 curr_vddc = (u64)curr_std_vddc;
2244         u64 pwr_efficiency_ratio, n, d;
2245
2246         if ((prev_vddc == 0) || (curr_vddc == 0))
2247                 return 0;
2248
2249         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2250         d = prev_vddc * prev_vddc;
2251         pwr_efficiency_ratio = div64_u64(n, d);
2252
2253         if (pwr_efficiency_ratio > (u64)0xFFFF)
2254                 return 0;
2255
2256         return (u16)pwr_efficiency_ratio;
2257 }
2258
2259 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2260                                             struct radeon_ps *radeon_state)
2261 {
2262         struct si_power_info *si_pi = si_get_pi(rdev);
2263
2264         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2265             radeon_state->vclk && radeon_state->dclk)
2266                 return true;
2267
2268         return false;
2269 }
2270
2271 static int si_populate_power_containment_values(struct radeon_device *rdev,
2272                                                 struct radeon_ps *radeon_state,
2273                                                 SISLANDS_SMC_SWSTATE *smc_state)
2274 {
2275         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2276         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2277         struct ni_ps *state = ni_get_ps(radeon_state);
2278         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2279         u32 prev_sclk;
2280         u32 max_sclk;
2281         u32 min_sclk;
2282         u16 prev_std_vddc;
2283         u16 curr_std_vddc;
2284         int i;
2285         u16 pwr_efficiency_ratio;
2286         u8 max_ps_percent;
2287         bool disable_uvd_power_tune;
2288         int ret;
2289
2290         if (ni_pi->enable_power_containment == false)
2291                 return 0;
2292
2293         if (state->performance_level_count == 0)
2294                 return -EINVAL;
2295
2296         if (smc_state->levelCount != state->performance_level_count)
2297                 return -EINVAL;
2298
2299         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2300
2301         smc_state->levels[0].dpm2.MaxPS = 0;
2302         smc_state->levels[0].dpm2.NearTDPDec = 0;
2303         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2304         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2305         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2306
2307         for (i = 1; i < state->performance_level_count; i++) {
2308                 prev_sclk = state->performance_levels[i-1].sclk;
2309                 max_sclk  = state->performance_levels[i].sclk;
2310                 if (i == 1)
2311                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2312                 else
2313                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2314
2315                 if (prev_sclk > max_sclk)
2316                         return -EINVAL;
2317
2318                 if ((max_ps_percent == 0) ||
2319                     (prev_sclk == max_sclk) ||
2320                     disable_uvd_power_tune) {
2321                         min_sclk = max_sclk;
2322                 } else if (i == 1) {
2323                         min_sclk = prev_sclk;
2324                 } else {
2325                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2326                 }
2327
2328                 if (min_sclk < state->performance_levels[0].sclk)
2329                         min_sclk = state->performance_levels[0].sclk;
2330
2331                 if (min_sclk == 0)
2332                         return -EINVAL;
2333
2334                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2335                                                 state->performance_levels[i-1].vddc, &vddc);
2336                 if (ret)
2337                         return ret;
2338
2339                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2340                 if (ret)
2341                         return ret;
2342
2343                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2344                                                 state->performance_levels[i].vddc, &vddc);
2345                 if (ret)
2346                         return ret;
2347
2348                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2349                 if (ret)
2350                         return ret;
2351
2352                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2353                                                                            prev_std_vddc, curr_std_vddc);
2354
2355                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2356                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2357                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2358                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2359                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2360         }
2361
2362         return 0;
2363 }
2364
2365 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2366                                          struct radeon_ps *radeon_state,
2367                                          SISLANDS_SMC_SWSTATE *smc_state)
2368 {
2369         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2370         struct ni_ps *state = ni_get_ps(radeon_state);
2371         u32 sq_power_throttle, sq_power_throttle2;
2372         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2373         int i;
2374
2375         if (state->performance_level_count == 0)
2376                 return -EINVAL;
2377
2378         if (smc_state->levelCount != state->performance_level_count)
2379                 return -EINVAL;
2380
2381         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2382                 return -EINVAL;
2383
2384         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2385                 enable_sq_ramping = false;
2386
2387         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2388                 enable_sq_ramping = false;
2389
2390         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2391                 enable_sq_ramping = false;
2392
2393         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2394                 enable_sq_ramping = false;
2395
2396         if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2397                 enable_sq_ramping = false;
2398
2399         for (i = 0; i < state->performance_level_count; i++) {
2400                 sq_power_throttle = 0;
2401                 sq_power_throttle2 = 0;
2402
2403                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2404                     enable_sq_ramping) {
2405                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2406                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2407                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2408                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2409                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2410                 } else {
2411                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2412                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2413                 }
2414
2415                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2416                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2417         }
2418
2419         return 0;
2420 }
2421
2422 static int si_enable_power_containment(struct radeon_device *rdev,
2423                                        struct radeon_ps *radeon_new_state,
2424                                        bool enable)
2425 {
2426         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2427         PPSMC_Result smc_result;
2428         int ret = 0;
2429
2430         if (ni_pi->enable_power_containment) {
2431                 if (enable) {
2432                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2433                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2434                                 if (smc_result != PPSMC_Result_OK) {
2435                                         ret = -EINVAL;
2436                                         ni_pi->pc_enabled = false;
2437                                 } else {
2438                                         ni_pi->pc_enabled = true;
2439                                 }
2440                         }
2441                 } else {
2442                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2443                         if (smc_result != PPSMC_Result_OK)
2444                                 ret = -EINVAL;
2445                         ni_pi->pc_enabled = false;
2446                 }
2447         }
2448
2449         return ret;
2450 }
2451
2452 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2453 {
2454         struct si_power_info *si_pi = si_get_pi(rdev);
2455         int ret = 0;
2456         struct si_dte_data *dte_data = &si_pi->dte_data;
2457         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2458         u32 table_size;
2459         u8 tdep_count;
2460         u32 i;
2461
2462         if (dte_data == NULL)
2463                 si_pi->enable_dte = false;
2464
2465         if (si_pi->enable_dte == false)
2466                 return 0;
2467
2468         if (dte_data->k <= 0)
2469                 return -EINVAL;
2470
2471         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2472         if (dte_tables == NULL) {
2473                 si_pi->enable_dte = false;
2474                 return -ENOMEM;
2475         }
2476
2477         table_size = dte_data->k;
2478
2479         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2480                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2481
2482         tdep_count = dte_data->tdep_count;
2483         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2484                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2485
2486         dte_tables->K = cpu_to_be32(table_size);
2487         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2488         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2489         dte_tables->WindowSize = dte_data->window_size;
2490         dte_tables->temp_select = dte_data->temp_select;
2491         dte_tables->DTE_mode = dte_data->dte_mode;
2492         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2493
2494         if (tdep_count > 0)
2495                 table_size--;
2496
2497         for (i = 0; i < table_size; i++) {
2498                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2499                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2500         }
2501
2502         dte_tables->Tdep_count = tdep_count;
2503
2504         for (i = 0; i < (u32)tdep_count; i++) {
2505                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2506                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2507                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2508         }
2509
2510         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2511                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2512         kfree(dte_tables);
2513
2514         return ret;
2515 }
2516
2517 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2518                                           u16 *max, u16 *min)
2519 {
2520         struct si_power_info *si_pi = si_get_pi(rdev);
2521         struct radeon_cac_leakage_table *table =
2522                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2523         u32 i;
2524         u32 v0_loadline;
2525
2526
2527         if (table == NULL)
2528                 return -EINVAL;
2529
2530         *max = 0;
2531         *min = 0xFFFF;
2532
2533         for (i = 0; i < table->count; i++) {
2534                 if (table->entries[i].vddc > *max)
2535                         *max = table->entries[i].vddc;
2536                 if (table->entries[i].vddc < *min)
2537                         *min = table->entries[i].vddc;
2538         }
2539
2540         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2541                 return -EINVAL;
2542
2543         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2544
2545         if (v0_loadline > 0xFFFFUL)
2546                 return -EINVAL;
2547
2548         *min = (u16)v0_loadline;
2549
2550         if ((*min > *max) || (*max == 0) || (*min == 0))
2551                 return -EINVAL;
2552
2553         return 0;
2554 }
2555
2556 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2557 {
2558         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2559                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2560 }
2561
2562 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2563                                      PP_SIslands_CacConfig *cac_tables,
2564                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2565                                      u16 t0, u16 t_step)
2566 {
2567         struct si_power_info *si_pi = si_get_pi(rdev);
2568         u32 leakage;
2569         unsigned int i, j;
2570         s32 t;
2571         u32 smc_leakage;
2572         u32 scaling_factor;
2573         u16 voltage;
2574
2575         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2576
2577         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2578                 t = (1000 * (i * t_step + t0));
2579
2580                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2581                         voltage = vddc_max - (vddc_step * j);
2582
2583                         si_calculate_leakage_for_v_and_t(rdev,
2584                                                          &si_pi->powertune_data->leakage_coefficients,
2585                                                          voltage,
2586                                                          t,
2587                                                          si_pi->dyn_powertune_data.cac_leakage,
2588                                                          &leakage);
2589
2590                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2591
2592                         if (smc_leakage > 0xFFFF)
2593                                 smc_leakage = 0xFFFF;
2594
2595                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2596                                 cpu_to_be16((u16)smc_leakage);
2597                 }
2598         }
2599         return 0;
2600 }
2601
2602 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2603                                             PP_SIslands_CacConfig *cac_tables,
2604                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2605 {
2606         struct si_power_info *si_pi = si_get_pi(rdev);
2607         u32 leakage;
2608         unsigned int i, j;
2609         u32 smc_leakage;
2610         u32 scaling_factor;
2611         u16 voltage;
2612
2613         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2614
2615         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2616                 voltage = vddc_max - (vddc_step * j);
2617
2618                 si_calculate_leakage_for_v(rdev,
2619                                            &si_pi->powertune_data->leakage_coefficients,
2620                                            si_pi->powertune_data->fixed_kt,
2621                                            voltage,
2622                                            si_pi->dyn_powertune_data.cac_leakage,
2623                                            &leakage);
2624
2625                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2626
2627                 if (smc_leakage > 0xFFFF)
2628                         smc_leakage = 0xFFFF;
2629
2630                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2631                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2632                                 cpu_to_be16((u16)smc_leakage);
2633         }
2634         return 0;
2635 }
2636
2637 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2638 {
2639         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2640         struct si_power_info *si_pi = si_get_pi(rdev);
2641         PP_SIslands_CacConfig *cac_tables = NULL;
2642         u16 vddc_max, vddc_min, vddc_step;
2643         u16 t0, t_step;
2644         u32 load_line_slope, reg;
2645         int ret = 0;
2646         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2647
2648         if (ni_pi->enable_cac == false)
2649                 return 0;
2650
2651         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2652         if (!cac_tables)
2653                 return -ENOMEM;
2654
2655         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2656         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2657         WREG32(CG_CAC_CTRL, reg);
2658
2659         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2660         si_pi->dyn_powertune_data.dc_pwr_value =
2661                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2662         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2663         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2664
2665         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2666
2667         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2668         if (ret)
2669                 goto done_free;
2670
2671         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2672         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2673         t_step = 4;
2674         t0 = 60;
2675
2676         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2677                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2678                                                 vddc_max, vddc_min, vddc_step,
2679                                                 t0, t_step);
2680         else
2681                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2682                                                        vddc_max, vddc_min, vddc_step);
2683         if (ret)
2684                 goto done_free;
2685
2686         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2687
2688         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2689         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2690         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2691         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2692         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2693         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2694         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2695         cac_tables->calculation_repeats = cpu_to_be32(2);
2696         cac_tables->dc_cac = cpu_to_be32(0);
2697         cac_tables->log2_PG_LKG_SCALE = 12;
2698         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2699         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2700         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2701
2702         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2703                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2704
2705         if (ret)
2706                 goto done_free;
2707
2708         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2709
2710 done_free:
2711         if (ret) {
2712                 ni_pi->enable_cac = false;
2713                 ni_pi->enable_power_containment = false;
2714         }
2715
2716         kfree(cac_tables);
2717
2718         return 0;
2719 }
2720
2721 static int si_program_cac_config_registers(struct radeon_device *rdev,
2722                                            const struct si_cac_config_reg *cac_config_regs)
2723 {
2724         const struct si_cac_config_reg *config_regs = cac_config_regs;
2725         u32 data = 0, offset;
2726
2727         if (!config_regs)
2728                 return -EINVAL;
2729
2730         while (config_regs->offset != 0xFFFFFFFF) {
2731                 switch (config_regs->type) {
2732                 case SISLANDS_CACCONFIG_CGIND:
2733                         offset = SMC_CG_IND_START + config_regs->offset;
2734                         if (offset < SMC_CG_IND_END)
2735                                 data = RREG32_SMC(offset);
2736                         break;
2737                 default:
2738                         data = RREG32(config_regs->offset << 2);
2739                         break;
2740                 }
2741
2742                 data &= ~config_regs->mask;
2743                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2744
2745                 switch (config_regs->type) {
2746                 case SISLANDS_CACCONFIG_CGIND:
2747                         offset = SMC_CG_IND_START + config_regs->offset;
2748                         if (offset < SMC_CG_IND_END)
2749                                 WREG32_SMC(offset, data);
2750                         break;
2751                 default:
2752                         WREG32(config_regs->offset << 2, data);
2753                         break;
2754                 }
2755                 config_regs++;
2756         }
2757         return 0;
2758 }
2759
2760 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2761 {
2762         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2763         struct si_power_info *si_pi = si_get_pi(rdev);
2764         int ret;
2765
2766         if ((ni_pi->enable_cac == false) ||
2767             (ni_pi->cac_configuration_required == false))
2768                 return 0;
2769
2770         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2771         if (ret)
2772                 return ret;
2773         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2774         if (ret)
2775                 return ret;
2776         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2777         if (ret)
2778                 return ret;
2779
2780         return 0;
2781 }
2782
2783 static int si_enable_smc_cac(struct radeon_device *rdev,
2784                              struct radeon_ps *radeon_new_state,
2785                              bool enable)
2786 {
2787         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2788         struct si_power_info *si_pi = si_get_pi(rdev);
2789         PPSMC_Result smc_result;
2790         int ret = 0;
2791
2792         if (ni_pi->enable_cac) {
2793                 if (enable) {
2794                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2795                                 if (ni_pi->support_cac_long_term_average) {
2796                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2797                                         if (smc_result != PPSMC_Result_OK)
2798                                                 ni_pi->support_cac_long_term_average = false;
2799                                 }
2800
2801                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2802                                 if (smc_result != PPSMC_Result_OK) {
2803                                         ret = -EINVAL;
2804                                         ni_pi->cac_enabled = false;
2805                                 } else {
2806                                         ni_pi->cac_enabled = true;
2807                                 }
2808
2809                                 if (si_pi->enable_dte) {
2810                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2811                                         if (smc_result != PPSMC_Result_OK)
2812                                                 ret = -EINVAL;
2813                                 }
2814                         }
2815                 } else if (ni_pi->cac_enabled) {
2816                         if (si_pi->enable_dte)
2817                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2818
2819                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2820
2821                         ni_pi->cac_enabled = false;
2822
2823                         if (ni_pi->support_cac_long_term_average)
2824                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2825                 }
2826         }
2827         return ret;
2828 }
2829
2830 static int si_init_smc_spll_table(struct radeon_device *rdev)
2831 {
2832         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2833         struct si_power_info *si_pi = si_get_pi(rdev);
2834         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2835         SISLANDS_SMC_SCLK_VALUE sclk_params;
2836         u32 fb_div, p_div;
2837         u32 clk_s, clk_v;
2838         u32 sclk = 0;
2839         int ret = 0;
2840         u32 tmp;
2841         int i;
2842
2843         if (si_pi->spll_table_start == 0)
2844                 return -EINVAL;
2845
2846         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2847         if (spll_table == NULL)
2848                 return -ENOMEM;
2849
2850         for (i = 0; i < 256; i++) {
2851                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2852                 if (ret)
2853                         break;
2854
2855                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2856                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2857                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2858                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2859
2860                 fb_div &= ~0x00001FFF;
2861                 fb_div >>= 1;
2862                 clk_v >>= 6;
2863
2864                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2865                         ret = -EINVAL;
2866                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2867                         ret = -EINVAL;
2868                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2869                         ret = -EINVAL;
2870                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2871                         ret = -EINVAL;
2872
2873                 if (ret)
2874                         break;
2875
2876                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2877                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2878                 spll_table->freq[i] = cpu_to_be32(tmp);
2879
2880                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2881                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2882                 spll_table->ss[i] = cpu_to_be32(tmp);
2883
2884                 sclk += 512;
2885         }
2886
2887
2888         if (!ret)
2889                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2890                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2891                                            si_pi->sram_end);
2892
2893         if (ret)
2894                 ni_pi->enable_power_containment = false;
2895
2896         kfree(spll_table);
2897
2898         return ret;
2899 }
2900
2901 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2902                                         struct radeon_ps *rps)
2903 {
2904         struct ni_ps *ps = ni_get_ps(rps);
2905         struct radeon_clock_and_voltage_limits *max_limits;
2906         bool disable_mclk_switching;
2907         u32 mclk, sclk;
2908         u16 vddc, vddci;
2909         int i;
2910
2911         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2912             ni_dpm_vblank_too_short(rdev))
2913                 disable_mclk_switching = true;
2914         else
2915                 disable_mclk_switching = false;
2916
2917         if (rdev->pm.dpm.ac_power)
2918                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2919         else
2920                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2921
2922         for (i = ps->performance_level_count - 2; i >= 0; i--) {
2923                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2924                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2925         }
2926         if (rdev->pm.dpm.ac_power == false) {
2927                 for (i = 0; i < ps->performance_level_count; i++) {
2928                         if (ps->performance_levels[i].mclk > max_limits->mclk)
2929                                 ps->performance_levels[i].mclk = max_limits->mclk;
2930                         if (ps->performance_levels[i].sclk > max_limits->sclk)
2931                                 ps->performance_levels[i].sclk = max_limits->sclk;
2932                         if (ps->performance_levels[i].vddc > max_limits->vddc)
2933                                 ps->performance_levels[i].vddc = max_limits->vddc;
2934                         if (ps->performance_levels[i].vddci > max_limits->vddci)
2935                                 ps->performance_levels[i].vddci = max_limits->vddci;
2936                 }
2937         }
2938
2939         /* XXX validate the min clocks required for display */
2940
2941         if (disable_mclk_switching) {
2942                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
2943                 sclk = ps->performance_levels[0].sclk;
2944                 vddc = ps->performance_levels[0].vddc;
2945                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
2946         } else {
2947                 sclk = ps->performance_levels[0].sclk;
2948                 mclk = ps->performance_levels[0].mclk;
2949                 vddc = ps->performance_levels[0].vddc;
2950                 vddci = ps->performance_levels[0].vddci;
2951         }
2952
2953         /* adjusted low state */
2954         ps->performance_levels[0].sclk = sclk;
2955         ps->performance_levels[0].mclk = mclk;
2956         ps->performance_levels[0].vddc = vddc;
2957         ps->performance_levels[0].vddci = vddci;
2958
2959         for (i = 1; i < ps->performance_level_count; i++) {
2960                 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
2961                         ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
2962                 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
2963                         ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
2964         }
2965
2966         if (disable_mclk_switching) {
2967                 mclk = ps->performance_levels[0].mclk;
2968                 for (i = 1; i < ps->performance_level_count; i++) {
2969                         if (mclk < ps->performance_levels[i].mclk)
2970                                 mclk = ps->performance_levels[i].mclk;
2971                 }
2972                 for (i = 0; i < ps->performance_level_count; i++) {
2973                         ps->performance_levels[i].mclk = mclk;
2974                         ps->performance_levels[i].vddci = vddci;
2975                 }
2976         } else {
2977                 for (i = 1; i < ps->performance_level_count; i++) {
2978                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
2979                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
2980                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
2981                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
2982                 }
2983         }
2984
2985         for (i = 0; i < ps->performance_level_count; i++)
2986                 btc_adjust_clock_combinations(rdev, max_limits,
2987                                               &ps->performance_levels[i]);
2988
2989         for (i = 0; i < ps->performance_level_count; i++) {
2990                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2991                                                    ps->performance_levels[i].sclk,
2992                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
2993                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2994                                                    ps->performance_levels[i].mclk,
2995                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
2996                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2997                                                    ps->performance_levels[i].mclk,
2998                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
2999                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3000                                                    rdev->clock.current_dispclk,
3001                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3002         }
3003
3004         for (i = 0; i < ps->performance_level_count; i++) {
3005                 btc_apply_voltage_delta_rules(rdev,
3006                                               max_limits->vddc, max_limits->vddci,
3007                                               &ps->performance_levels[i].vddc,
3008                                               &ps->performance_levels[i].vddci);
3009         }
3010
3011         ps->dc_compatible = true;
3012         for (i = 0; i < ps->performance_level_count; i++) {
3013                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3014                         ps->dc_compatible = false;
3015         }
3016
3017 }
3018
3019 #if 0
3020 static int si_read_smc_soft_register(struct radeon_device *rdev,
3021                                      u16 reg_offset, u32 *value)
3022 {
3023         struct si_power_info *si_pi = si_get_pi(rdev);
3024
3025         return si_read_smc_sram_dword(rdev,
3026                                       si_pi->soft_regs_start + reg_offset, value,
3027                                       si_pi->sram_end);
3028 }
3029 #endif
3030
3031 static int si_write_smc_soft_register(struct radeon_device *rdev,
3032                                       u16 reg_offset, u32 value)
3033 {
3034         struct si_power_info *si_pi = si_get_pi(rdev);
3035
3036         return si_write_smc_sram_dword(rdev,
3037                                        si_pi->soft_regs_start + reg_offset,
3038                                        value, si_pi->sram_end);
3039 }
3040
3041 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3042 {
3043         bool ret = false;
3044         u32 tmp, width, row, column, bank, density;
3045         bool is_memory_gddr5, is_special;
3046
3047         tmp = RREG32(MC_SEQ_MISC0);
3048         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3049         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3050                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3051
3052         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3053         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3054
3055         tmp = RREG32(MC_ARB_RAMCFG);
3056         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3057         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3058         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3059
3060         density = (1 << (row + column - 20 + bank)) * width;
3061
3062         if ((rdev->pdev->device == 0x6819) &&
3063             is_memory_gddr5 && is_special && (density == 0x400))
3064                 ret = true;
3065
3066         return ret;
3067 }
3068
3069 static void si_get_leakage_vddc(struct radeon_device *rdev)
3070 {
3071         struct si_power_info *si_pi = si_get_pi(rdev);
3072         u16 vddc, count = 0;
3073         int i, ret;
3074
3075         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3076                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3077
3078                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3079                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3080                         si_pi->leakage_voltage.entries[count].leakage_index =
3081                                 SISLANDS_LEAKAGE_INDEX0 + i;
3082                         count++;
3083                 }
3084         }
3085         si_pi->leakage_voltage.count = count;
3086 }
3087
3088 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3089                                                      u32 index, u16 *leakage_voltage)
3090 {
3091         struct si_power_info *si_pi = si_get_pi(rdev);
3092         int i;
3093
3094         if (leakage_voltage == NULL)
3095                 return -EINVAL;
3096
3097         if ((index & 0xff00) != 0xff00)
3098                 return -EINVAL;
3099
3100         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3101                 return -EINVAL;
3102
3103         if (index < SISLANDS_LEAKAGE_INDEX0)
3104                 return -EINVAL;
3105
3106         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3107                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3108                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3109                         return 0;
3110                 }
3111         }
3112         return -EAGAIN;
3113 }
3114
3115 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3116 {
3117         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3118         bool want_thermal_protection;
3119         enum radeon_dpm_event_src dpm_event_src;
3120
3121         switch (sources) {
3122         case 0:
3123         default:
3124                 want_thermal_protection = false;
3125                 break;
3126         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3127                 want_thermal_protection = true;
3128                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3129                 break;
3130         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3131                 want_thermal_protection = true;
3132                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3133                 break;
3134         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3135               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3136                 want_thermal_protection = true;
3137                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3138                 break;
3139         }
3140
3141         if (want_thermal_protection) {
3142                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3143                 if (pi->thermal_protection)
3144                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3145         } else {
3146                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3147         }
3148 }
3149
3150 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3151                                            enum radeon_dpm_auto_throttle_src source,
3152                                            bool enable)
3153 {
3154         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3155
3156         if (enable) {
3157                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3158                         pi->active_auto_throttle_sources |= 1 << source;
3159                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3160                 }
3161         } else {
3162                 if (pi->active_auto_throttle_sources & (1 << source)) {
3163                         pi->active_auto_throttle_sources &= ~(1 << source);
3164                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3165                 }
3166         }
3167 }
3168
3169 static void si_start_dpm(struct radeon_device *rdev)
3170 {
3171         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3172 }
3173
3174 static void si_stop_dpm(struct radeon_device *rdev)
3175 {
3176         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3177 }
3178
3179 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3180 {
3181         if (enable)
3182                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3183         else
3184                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3185
3186 }
3187
3188 #if 0
3189 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3190                                                u32 thermal_level)
3191 {
3192         PPSMC_Result ret;
3193
3194         if (thermal_level == 0) {
3195                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3196                 if (ret == PPSMC_Result_OK)
3197                         return 0;
3198                 else
3199                         return -EINVAL;
3200         }
3201         return 0;
3202 }
3203
3204 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3205 {
3206         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3207 }
3208 #endif
3209
3210 #if 0
3211 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3212 {
3213         if (ac_power)
3214                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3215                         0 : -EINVAL;
3216
3217         return 0;
3218 }
3219 #endif
3220
3221 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3222                                                       PPSMC_Msg msg, u32 parameter)
3223 {
3224         WREG32(SMC_SCRATCH0, parameter);
3225         return si_send_msg_to_smc(rdev, msg);
3226 }
3227
3228 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3229 {
3230         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3231                 return -EINVAL;
3232
3233         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3234                 0 : -EINVAL;
3235 }
3236
3237 int si_dpm_force_performance_level(struct radeon_device *rdev,
3238                                    enum radeon_dpm_forced_level level)
3239 {
3240         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3241         struct ni_ps *ps = ni_get_ps(rps);
3242         u32 levels = ps->performance_level_count;
3243
3244         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3245                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3246                         return -EINVAL;
3247
3248                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3249                         return -EINVAL;
3250         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3251                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3252                         return -EINVAL;
3253
3254                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3255                         return -EINVAL;
3256         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3257                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3258                         return -EINVAL;
3259
3260                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3261                         return -EINVAL;
3262         }
3263
3264         rdev->pm.dpm.forced_level = level;
3265
3266         return 0;
3267 }
3268
3269 static int si_set_boot_state(struct radeon_device *rdev)
3270 {
3271         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3272                 0 : -EINVAL;
3273 }
3274
3275 static int si_set_sw_state(struct radeon_device *rdev)
3276 {
3277         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3278                 0 : -EINVAL;
3279 }
3280
3281 static int si_halt_smc(struct radeon_device *rdev)
3282 {
3283         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3284                 return -EINVAL;
3285
3286         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3287                 0 : -EINVAL;
3288 }
3289
3290 static int si_resume_smc(struct radeon_device *rdev)
3291 {
3292         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3293                 return -EINVAL;
3294
3295         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3296                 0 : -EINVAL;
3297 }
3298
3299 static void si_dpm_start_smc(struct radeon_device *rdev)
3300 {
3301         si_program_jump_on_start(rdev);
3302         si_start_smc(rdev);
3303         si_start_smc_clock(rdev);
3304 }
3305
3306 static void si_dpm_stop_smc(struct radeon_device *rdev)
3307 {
3308         si_reset_smc(rdev);
3309         si_stop_smc_clock(rdev);
3310 }
3311
3312 static int si_process_firmware_header(struct radeon_device *rdev)
3313 {
3314         struct si_power_info *si_pi = si_get_pi(rdev);
3315         u32 tmp;
3316         int ret;
3317
3318         ret = si_read_smc_sram_dword(rdev,
3319                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3320                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3321                                      &tmp, si_pi->sram_end);
3322         if (ret)
3323                 return ret;
3324
3325         si_pi->state_table_start = tmp;
3326
3327         ret = si_read_smc_sram_dword(rdev,
3328                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3329                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3330                                      &tmp, si_pi->sram_end);
3331         if (ret)
3332                 return ret;
3333
3334         si_pi->soft_regs_start = tmp;
3335
3336         ret = si_read_smc_sram_dword(rdev,
3337                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3338                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3339                                      &tmp, si_pi->sram_end);
3340         if (ret)
3341                 return ret;
3342
3343         si_pi->mc_reg_table_start = tmp;
3344
3345         ret = si_read_smc_sram_dword(rdev,
3346                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3347                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3348                                      &tmp, si_pi->sram_end);
3349         if (ret)
3350                 return ret;
3351
3352         si_pi->arb_table_start = tmp;
3353
3354         ret = si_read_smc_sram_dword(rdev,
3355                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3356                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3357                                      &tmp, si_pi->sram_end);
3358         if (ret)
3359                 return ret;
3360
3361         si_pi->cac_table_start = tmp;
3362
3363         ret = si_read_smc_sram_dword(rdev,
3364                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3365                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3366                                      &tmp, si_pi->sram_end);
3367         if (ret)
3368                 return ret;
3369
3370         si_pi->dte_table_start = tmp;
3371
3372         ret = si_read_smc_sram_dword(rdev,
3373                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3374                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3375                                      &tmp, si_pi->sram_end);
3376         if (ret)
3377                 return ret;
3378
3379         si_pi->spll_table_start = tmp;
3380
3381         ret = si_read_smc_sram_dword(rdev,
3382                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3383                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3384                                      &tmp, si_pi->sram_end);
3385         if (ret)
3386                 return ret;
3387
3388         si_pi->papm_cfg_table_start = tmp;
3389
3390         return ret;
3391 }
3392
3393 static void si_read_clock_registers(struct radeon_device *rdev)
3394 {
3395         struct si_power_info *si_pi = si_get_pi(rdev);
3396
3397         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3398         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3399         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3400         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3401         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3402         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3403         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3404         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3405         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3406         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3407         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3408         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3409         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3410         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3411         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3412 }
3413
3414 static void si_enable_thermal_protection(struct radeon_device *rdev,
3415                                           bool enable)
3416 {
3417         if (enable)
3418                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3419         else
3420                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3421 }
3422
3423 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3424 {
3425         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3426 }
3427
3428 #if 0
3429 static int si_enter_ulp_state(struct radeon_device *rdev)
3430 {
3431         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3432
3433         udelay(25000);
3434
3435         return 0;
3436 }
3437
3438 static int si_exit_ulp_state(struct radeon_device *rdev)
3439 {
3440         int i;
3441
3442         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3443
3444         udelay(7000);
3445
3446         for (i = 0; i < rdev->usec_timeout; i++) {
3447                 if (RREG32(SMC_RESP_0) == 1)
3448                         break;
3449                 udelay(1000);
3450         }
3451
3452         return 0;
3453 }
3454 #endif
3455
3456 static int si_notify_smc_display_change(struct radeon_device *rdev,
3457                                      bool has_display)
3458 {
3459         PPSMC_Msg msg = has_display ?
3460                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3461
3462         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3463                 0 : -EINVAL;
3464 }
3465
3466 static void si_program_response_times(struct radeon_device *rdev)
3467 {
3468         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3469         u32 vddc_dly, acpi_dly, vbi_dly;
3470         u32 reference_clock;
3471
3472         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3473
3474         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3475         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3476
3477         if (voltage_response_time == 0)
3478                 voltage_response_time = 1000;
3479
3480         acpi_delay_time = 15000;
3481         vbi_time_out = 100000;
3482
3483         reference_clock = radeon_get_xclk(rdev);
3484
3485         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3486         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3487         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3488
3489         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3490         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3491         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3492         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3493 }
3494
3495 static void si_program_ds_registers(struct radeon_device *rdev)
3496 {
3497         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3498         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3499
3500         if (eg_pi->sclk_deep_sleep) {
3501                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3502                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3503                          ~AUTOSCALE_ON_SS_CLEAR);
3504         }
3505 }
3506
3507 static void si_program_display_gap(struct radeon_device *rdev)
3508 {
3509         u32 tmp, pipe;
3510         int i;
3511
3512         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3513         if (rdev->pm.dpm.new_active_crtc_count > 0)
3514                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3515         else
3516                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3517
3518         if (rdev->pm.dpm.new_active_crtc_count > 1)
3519                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3520         else
3521                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3522
3523         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3524
3525         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3526         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3527
3528         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3529             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3530                 /* find the first active crtc */
3531                 for (i = 0; i < rdev->num_crtc; i++) {
3532                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3533                                 break;
3534                 }
3535                 if (i == rdev->num_crtc)
3536                         pipe = 0;
3537                 else
3538                         pipe = i;
3539
3540                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3541                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3542                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3543         }
3544
3545         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3546 }
3547
3548 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3549 {
3550         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3551
3552         if (enable) {
3553                 if (pi->sclk_ss)
3554                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3555         } else {
3556                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3557                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3558         }
3559 }
3560
3561 static void si_setup_bsp(struct radeon_device *rdev)
3562 {
3563         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3564         u32 xclk = radeon_get_xclk(rdev);
3565
3566         r600_calculate_u_and_p(pi->asi,
3567                                xclk,
3568                                16,
3569                                &pi->bsp,
3570                                &pi->bsu);
3571
3572         r600_calculate_u_and_p(pi->pasi,
3573                                xclk,
3574                                16,
3575                                &pi->pbsp,
3576                                &pi->pbsu);
3577
3578
3579         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3580         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3581
3582         WREG32(CG_BSP, pi->dsp);
3583 }
3584
3585 static void si_program_git(struct radeon_device *rdev)
3586 {
3587         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3588 }
3589
3590 static void si_program_tp(struct radeon_device *rdev)
3591 {
3592         int i;
3593         enum r600_td td = R600_TD_DFLT;
3594
3595         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3596                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3597
3598         if (td == R600_TD_AUTO)
3599                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3600         else
3601                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3602
3603         if (td == R600_TD_UP)
3604                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3605
3606         if (td == R600_TD_DOWN)
3607                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3608 }
3609
3610 static void si_program_tpp(struct radeon_device *rdev)
3611 {
3612         WREG32(CG_TPC, R600_TPC_DFLT);
3613 }
3614
3615 static void si_program_sstp(struct radeon_device *rdev)
3616 {
3617         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3618 }
3619
3620 static void si_enable_display_gap(struct radeon_device *rdev)
3621 {
3622         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3623
3624         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3625         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3626                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3627
3628         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3629         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3630                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3631         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3632 }
3633
3634 static void si_program_vc(struct radeon_device *rdev)
3635 {
3636         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3637
3638         WREG32(CG_FTV, pi->vrc);
3639 }
3640
3641 static void si_clear_vc(struct radeon_device *rdev)
3642 {
3643         WREG32(CG_FTV, 0);
3644 }
3645
3646 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3647 {
3648         u8 mc_para_index;
3649
3650         if (memory_clock < 10000)
3651                 mc_para_index = 0;
3652         else if (memory_clock >= 80000)
3653                 mc_para_index = 0x0f;
3654         else
3655                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3656         return mc_para_index;
3657 }
3658
3659 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3660 {
3661         u8 mc_para_index;
3662
3663         if (strobe_mode) {
3664                 if (memory_clock < 12500)
3665                         mc_para_index = 0x00;
3666                 else if (memory_clock > 47500)
3667                         mc_para_index = 0x0f;
3668                 else
3669                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3670         } else {
3671                 if (memory_clock < 65000)
3672                         mc_para_index = 0x00;
3673                 else if (memory_clock > 135000)
3674                         mc_para_index = 0x0f;
3675                 else
3676                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3677         }
3678         return mc_para_index;
3679 }
3680
3681 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3682 {
3683         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3684         bool strobe_mode = false;
3685         u8 result = 0;
3686
3687         if (mclk <= pi->mclk_strobe_mode_threshold)
3688                 strobe_mode = true;
3689
3690         if (pi->mem_gddr5)
3691                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3692         else
3693                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3694
3695         if (strobe_mode)
3696                 result |= SISLANDS_SMC_STROBE_ENABLE;
3697
3698         return result;
3699 }
3700
3701 static int si_upload_firmware(struct radeon_device *rdev)
3702 {
3703         struct si_power_info *si_pi = si_get_pi(rdev);
3704         int ret;
3705
3706         si_reset_smc(rdev);
3707         si_stop_smc_clock(rdev);
3708
3709         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3710
3711         return ret;
3712 }
3713
3714 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3715                                               const struct atom_voltage_table *table,
3716                                               const struct radeon_phase_shedding_limits_table *limits)
3717 {
3718         u32 data, num_bits, num_levels;
3719
3720         if ((table == NULL) || (limits == NULL))
3721                 return false;
3722
3723         data = table->mask_low;
3724
3725         num_bits = hweight32(data);
3726
3727         if (num_bits == 0)
3728                 return false;
3729
3730         num_levels = (1 << num_bits);
3731
3732         if (table->count != num_levels)
3733                 return false;
3734
3735         if (limits->count != (num_levels - 1))
3736                 return false;
3737
3738         return true;
3739 }
3740
3741 static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3742                                                      struct atom_voltage_table *voltage_table)
3743 {
3744         unsigned int i, diff;
3745
3746         if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS)
3747                 return;
3748
3749         diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS;
3750
3751         for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++)
3752                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3753
3754         voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS;
3755 }
3756
3757 static int si_construct_voltage_tables(struct radeon_device *rdev)
3758 {
3759         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3760         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3761         struct si_power_info *si_pi = si_get_pi(rdev);
3762         int ret;
3763
3764         ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3765                                             VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3766         if (ret)
3767                 return ret;
3768
3769         if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3770                 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table);
3771
3772         if (eg_pi->vddci_control) {
3773                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3774                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3775                 if (ret)
3776                         return ret;
3777
3778                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3779                         si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table);
3780         }
3781
3782         if (pi->mvdd_control) {
3783                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3784                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3785
3786                 if (ret) {
3787                         pi->mvdd_control = false;
3788                         return ret;
3789                 }
3790
3791                 if (si_pi->mvdd_voltage_table.count == 0) {
3792                         pi->mvdd_control = false;
3793                         return -EINVAL;
3794                 }
3795
3796                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3797                         si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table);
3798         }
3799
3800         if (si_pi->vddc_phase_shed_control) {
3801                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3802                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3803                 if (ret)
3804                         si_pi->vddc_phase_shed_control = false;
3805
3806                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3807                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3808                         si_pi->vddc_phase_shed_control = false;
3809         }
3810
3811         return 0;
3812 }
3813
3814 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3815                                           const struct atom_voltage_table *voltage_table,
3816                                           SISLANDS_SMC_STATETABLE *table)
3817 {
3818         unsigned int i;
3819
3820         for (i = 0; i < voltage_table->count; i++)
3821                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3822 }
3823
3824 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3825                                           SISLANDS_SMC_STATETABLE *table)
3826 {
3827         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3828         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3829         struct si_power_info *si_pi = si_get_pi(rdev);
3830         u8 i;
3831
3832         if (eg_pi->vddc_voltage_table.count) {
3833                 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3834                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3835                         cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3836
3837                 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3838                         if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3839                                 table->maxVDDCIndexInPPTable = i;
3840                                 break;
3841                         }
3842                 }
3843         }
3844
3845         if (eg_pi->vddci_voltage_table.count) {
3846                 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3847
3848                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3849                         cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3850         }
3851
3852
3853         if (si_pi->mvdd_voltage_table.count) {
3854                 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3855
3856                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3857                         cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3858         }
3859
3860         if (si_pi->vddc_phase_shed_control) {
3861                 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3862                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3863                         si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3864
3865                         table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3866                                 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3867
3868                         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3869                                                    (u32)si_pi->vddc_phase_shed_table.phase_delay);
3870                 } else {
3871                         si_pi->vddc_phase_shed_control = false;
3872                 }
3873         }
3874
3875         return 0;
3876 }
3877
3878 static int si_populate_voltage_value(struct radeon_device *rdev,
3879                                      const struct atom_voltage_table *table,
3880                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3881 {
3882         unsigned int i;
3883
3884         for (i = 0; i < table->count; i++) {
3885                 if (value <= table->entries[i].value) {
3886                         voltage->index = (u8)i;
3887                         voltage->value = cpu_to_be16(table->entries[i].value);
3888                         break;
3889                 }
3890         }
3891
3892         if (i >= table->count)
3893                 return -EINVAL;
3894
3895         return 0;
3896 }
3897
3898 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
3899                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3900 {
3901         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3902         struct si_power_info *si_pi = si_get_pi(rdev);
3903
3904         if (pi->mvdd_control) {
3905                 if (mclk <= pi->mvdd_split_frequency)
3906                         voltage->index = 0;
3907                 else
3908                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
3909
3910                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
3911         }
3912         return 0;
3913 }
3914
3915 static int si_get_std_voltage_value(struct radeon_device *rdev,
3916                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
3917                                     u16 *std_voltage)
3918 {
3919         u16 v_index;
3920         bool voltage_found = false;
3921         *std_voltage = be16_to_cpu(voltage->value);
3922
3923         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
3924                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
3925                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
3926                                 return -EINVAL;
3927
3928                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3929                                 if (be16_to_cpu(voltage->value) ==
3930                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3931                                         voltage_found = true;
3932                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3933                                                 *std_voltage =
3934                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3935                                         else
3936                                                 *std_voltage =
3937                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3938                                         break;
3939                                 }
3940                         }
3941
3942                         if (!voltage_found) {
3943                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3944                                         if (be16_to_cpu(voltage->value) <=
3945                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3946                                                 voltage_found = true;
3947                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3948                                                         *std_voltage =
3949                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3950                                                 else
3951                                                         *std_voltage =
3952                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3953                                                 break;
3954                                         }
3955                                 }
3956                         }
3957                 } else {
3958                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3959                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
3960                 }
3961         }
3962
3963         return 0;
3964 }
3965
3966 static int si_populate_std_voltage_value(struct radeon_device *rdev,
3967                                          u16 value, u8 index,
3968                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3969 {
3970         voltage->index = index;
3971         voltage->value = cpu_to_be16(value);
3972
3973         return 0;
3974 }
3975
3976 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
3977                                             const struct radeon_phase_shedding_limits_table *limits,
3978                                             u16 voltage, u32 sclk, u32 mclk,
3979                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
3980 {
3981         unsigned int i;
3982
3983         for (i = 0; i < limits->count; i++) {
3984                 if ((voltage <= limits->entries[i].voltage) &&
3985                     (sclk <= limits->entries[i].sclk) &&
3986                     (mclk <= limits->entries[i].mclk))
3987                         break;
3988         }
3989
3990         smc_voltage->phase_settings = (u8)i;
3991
3992         return 0;
3993 }
3994
3995 static int si_init_arb_table_index(struct radeon_device *rdev)
3996 {
3997         struct si_power_info *si_pi = si_get_pi(rdev);
3998         u32 tmp;
3999         int ret;
4000
4001         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4002         if (ret)
4003                 return ret;
4004
4005         tmp &= 0x00FFFFFF;
4006         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4007
4008         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4009 }
4010
4011 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4012 {
4013         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4014 }
4015
4016 static int si_reset_to_default(struct radeon_device *rdev)
4017 {
4018         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4019                 0 : -EINVAL;
4020 }
4021
4022 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4023 {
4024         struct si_power_info *si_pi = si_get_pi(rdev);
4025         u32 tmp;
4026         int ret;
4027
4028         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4029                                      &tmp, si_pi->sram_end);
4030         if (ret)
4031                 return ret;
4032
4033         tmp = (tmp >> 24) & 0xff;
4034
4035         if (tmp == MC_CG_ARB_FREQ_F0)
4036                 return 0;
4037
4038         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4039 }
4040
4041 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4042                                             u32 engine_clock)
4043 {
4044         u32 dram_rows;
4045         u32 dram_refresh_rate;
4046         u32 mc_arb_rfsh_rate;
4047         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4048
4049         if (tmp >= 4)
4050                 dram_rows = 16384;
4051         else
4052                 dram_rows = 1 << (tmp + 10);
4053
4054         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4055         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4056
4057         return mc_arb_rfsh_rate;
4058 }
4059
4060 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4061                                                 struct rv7xx_pl *pl,
4062                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4063 {
4064         u32 dram_timing;
4065         u32 dram_timing2;
4066         u32 burst_time;
4067
4068         arb_regs->mc_arb_rfsh_rate =
4069                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4070
4071         radeon_atom_set_engine_dram_timings(rdev,
4072                                             pl->sclk,
4073                                             pl->mclk);
4074
4075         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4076         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4077         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4078
4079         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4080         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4081         arb_regs->mc_arb_burst_time = (u8)burst_time;
4082
4083         return 0;
4084 }
4085
4086 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4087                                                   struct radeon_ps *radeon_state,
4088                                                   unsigned int first_arb_set)
4089 {
4090         struct si_power_info *si_pi = si_get_pi(rdev);
4091         struct ni_ps *state = ni_get_ps(radeon_state);
4092         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4093         int i, ret = 0;
4094
4095         for (i = 0; i < state->performance_level_count; i++) {
4096                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4097                 if (ret)
4098                         break;
4099                 ret = si_copy_bytes_to_smc(rdev,
4100                                            si_pi->arb_table_start +
4101                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4102                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4103                                            (u8 *)&arb_regs,
4104                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4105                                            si_pi->sram_end);
4106                 if (ret)
4107                         break;
4108         }
4109
4110         return ret;
4111 }
4112
4113 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4114                                                struct radeon_ps *radeon_new_state)
4115 {
4116         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4117                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4118 }
4119
4120 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4121                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4122 {
4123         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4124         struct si_power_info *si_pi = si_get_pi(rdev);
4125
4126         if (pi->mvdd_control)
4127                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4128                                                  si_pi->mvdd_bootup_value, voltage);
4129
4130         return 0;
4131 }
4132
4133 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4134                                          struct radeon_ps *radeon_initial_state,
4135                                          SISLANDS_SMC_STATETABLE *table)
4136 {
4137         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4138         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4139         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4140         struct si_power_info *si_pi = si_get_pi(rdev);
4141         u32 reg;
4142         int ret;
4143
4144         table->initialState.levels[0].mclk.vDLL_CNTL =
4145                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4146         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4147                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4148         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4149                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4150         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4151                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4152         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4153                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4154         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4155                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4156         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4157                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4158         table->initialState.levels[0].mclk.vMPLL_SS =
4159                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4160         table->initialState.levels[0].mclk.vMPLL_SS2 =
4161                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4162
4163         table->initialState.levels[0].mclk.mclk_value =
4164                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4165
4166         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4167                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4168         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4169                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4170         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4171                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4172         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4173                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4174         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4175                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4176         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4177                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4178
4179         table->initialState.levels[0].sclk.sclk_value =
4180                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4181
4182         table->initialState.levels[0].arbRefreshState =
4183                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4184
4185         table->initialState.levels[0].ACIndex = 0;
4186
4187         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4188                                         initial_state->performance_levels[0].vddc,
4189                                         &table->initialState.levels[0].vddc);
4190
4191         if (!ret) {
4192                 u16 std_vddc;
4193
4194                 ret = si_get_std_voltage_value(rdev,
4195                                                &table->initialState.levels[0].vddc,
4196                                                &std_vddc);
4197                 if (!ret)
4198                         si_populate_std_voltage_value(rdev, std_vddc,
4199                                                       table->initialState.levels[0].vddc.index,
4200                                                       &table->initialState.levels[0].std_vddc);
4201         }
4202
4203         if (eg_pi->vddci_control)
4204                 si_populate_voltage_value(rdev,
4205                                           &eg_pi->vddci_voltage_table,
4206                                           initial_state->performance_levels[0].vddci,
4207                                           &table->initialState.levels[0].vddci);
4208
4209         if (si_pi->vddc_phase_shed_control)
4210                 si_populate_phase_shedding_value(rdev,
4211                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4212                                                  initial_state->performance_levels[0].vddc,
4213                                                  initial_state->performance_levels[0].sclk,
4214                                                  initial_state->performance_levels[0].mclk,
4215                                                  &table->initialState.levels[0].vddc);
4216
4217         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4218
4219         reg = CG_R(0xffff) | CG_L(0);
4220         table->initialState.levels[0].aT = cpu_to_be32(reg);
4221
4222         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4223
4224         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4225
4226         if (pi->mem_gddr5) {
4227                 table->initialState.levels[0].strobeMode =
4228                         si_get_strobe_mode_settings(rdev,
4229                                                     initial_state->performance_levels[0].mclk);
4230
4231                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4232                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4233                 else
4234                         table->initialState.levels[0].mcFlags =  0;
4235         }
4236
4237         table->initialState.levelCount = 1;
4238
4239         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4240
4241         table->initialState.levels[0].dpm2.MaxPS = 0;
4242         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4243         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4244         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4245         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4246
4247         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4248         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4249
4250         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4251         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4252
4253         return 0;
4254 }
4255
4256 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4257                                       SISLANDS_SMC_STATETABLE *table)
4258 {
4259         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4260         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4261         struct si_power_info *si_pi = si_get_pi(rdev);
4262         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4263         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4264         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4265         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4266         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4267         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4268         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4269         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4270         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4271         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4272         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4273         u32 reg;
4274         int ret;
4275
4276         table->ACPIState = table->initialState;
4277
4278         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4279
4280         if (pi->acpi_vddc) {
4281                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4282                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4283                 if (!ret) {
4284                         u16 std_vddc;
4285
4286                         ret = si_get_std_voltage_value(rdev,
4287                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4288                         if (!ret)
4289                                 si_populate_std_voltage_value(rdev, std_vddc,
4290                                                               table->ACPIState.levels[0].vddc.index,
4291                                                               &table->ACPIState.levels[0].std_vddc);
4292                 }
4293                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4294
4295                 if (si_pi->vddc_phase_shed_control) {
4296                         si_populate_phase_shedding_value(rdev,
4297                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4298                                                          pi->acpi_vddc,
4299                                                          0,
4300                                                          0,
4301                                                          &table->ACPIState.levels[0].vddc);
4302                 }
4303         } else {
4304                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4305                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4306                 if (!ret) {
4307                         u16 std_vddc;
4308
4309                         ret = si_get_std_voltage_value(rdev,
4310                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4311
4312                         if (!ret)
4313                                 si_populate_std_voltage_value(rdev, std_vddc,
4314                                                               table->ACPIState.levels[0].vddc.index,
4315                                                               &table->ACPIState.levels[0].std_vddc);
4316                 }
4317                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4318                                                                                     si_pi->sys_pcie_mask,
4319                                                                                     si_pi->boot_pcie_gen,
4320                                                                                     RADEON_PCIE_GEN1);
4321
4322                 if (si_pi->vddc_phase_shed_control)
4323                         si_populate_phase_shedding_value(rdev,
4324                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4325                                                          pi->min_vddc_in_table,
4326                                                          0,
4327                                                          0,
4328                                                          &table->ACPIState.levels[0].vddc);
4329         }
4330
4331         if (pi->acpi_vddc) {
4332                 if (eg_pi->acpi_vddci)
4333                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4334                                                   eg_pi->acpi_vddci,
4335                                                   &table->ACPIState.levels[0].vddci);
4336         }
4337
4338         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4339         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4340
4341         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4342
4343         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4344         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4345
4346         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4347                 cpu_to_be32(dll_cntl);
4348         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4349                 cpu_to_be32(mclk_pwrmgt_cntl);
4350         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4351                 cpu_to_be32(mpll_ad_func_cntl);
4352         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4353                 cpu_to_be32(mpll_dq_func_cntl);
4354         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4355                 cpu_to_be32(mpll_func_cntl);
4356         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4357                 cpu_to_be32(mpll_func_cntl_1);
4358         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4359                 cpu_to_be32(mpll_func_cntl_2);
4360         table->ACPIState.levels[0].mclk.vMPLL_SS =
4361                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4362         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4363                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4364
4365         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4366                 cpu_to_be32(spll_func_cntl);
4367         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4368                 cpu_to_be32(spll_func_cntl_2);
4369         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4370                 cpu_to_be32(spll_func_cntl_3);
4371         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4372                 cpu_to_be32(spll_func_cntl_4);
4373
4374         table->ACPIState.levels[0].mclk.mclk_value = 0;
4375         table->ACPIState.levels[0].sclk.sclk_value = 0;
4376
4377         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4378
4379         if (eg_pi->dynamic_ac_timing)
4380                 table->ACPIState.levels[0].ACIndex = 0;
4381
4382         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4383         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4384         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4385         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4386         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4387
4388         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4389         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4390
4391         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4392         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4393
4394         return 0;
4395 }
4396
4397 static int si_populate_ulv_state(struct radeon_device *rdev,
4398                                  SISLANDS_SMC_SWSTATE *state)
4399 {
4400         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4401         struct si_power_info *si_pi = si_get_pi(rdev);
4402         struct si_ulv_param *ulv = &si_pi->ulv;
4403         u32 sclk_in_sr = 1350; /* ??? */
4404         int ret;
4405
4406         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4407                                             &state->levels[0]);
4408         if (!ret) {
4409                 if (eg_pi->sclk_deep_sleep) {
4410                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4411                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4412                         else
4413                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4414                 }
4415                 if (ulv->one_pcie_lane_in_ulv)
4416                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4417                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4418                 state->levels[0].ACIndex = 1;
4419                 state->levels[0].std_vddc = state->levels[0].vddc;
4420                 state->levelCount = 1;
4421
4422                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4423         }
4424
4425         return ret;
4426 }
4427
4428 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4429 {
4430         struct si_power_info *si_pi = si_get_pi(rdev);
4431         struct si_ulv_param *ulv = &si_pi->ulv;
4432         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4433         int ret;
4434
4435         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4436                                                    &arb_regs);
4437         if (ret)
4438                 return ret;
4439
4440         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4441                                    ulv->volt_change_delay);
4442
4443         ret = si_copy_bytes_to_smc(rdev,
4444                                    si_pi->arb_table_start +
4445                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4446                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4447                                    (u8 *)&arb_regs,
4448                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4449                                    si_pi->sram_end);
4450
4451         return ret;
4452 }
4453
4454 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4455 {
4456         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4457
4458         pi->mvdd_split_frequency = 30000;
4459 }
4460
4461 static int si_init_smc_table(struct radeon_device *rdev)
4462 {
4463         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4464         struct si_power_info *si_pi = si_get_pi(rdev);
4465         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4466         const struct si_ulv_param *ulv = &si_pi->ulv;
4467         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4468         int ret;
4469         u32 lane_width;
4470         u32 vr_hot_gpio;
4471
4472         si_populate_smc_voltage_tables(rdev, table);
4473
4474         switch (rdev->pm.int_thermal_type) {
4475         case THERMAL_TYPE_SI:
4476         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4477                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4478                 break;
4479         case THERMAL_TYPE_NONE:
4480                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4481                 break;
4482         default:
4483                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4484                 break;
4485         }
4486
4487         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4488                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4489
4490         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4491                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4492                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4493         }
4494
4495         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4496                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4497
4498         if (pi->mem_gddr5)
4499                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4500
4501         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4502                 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4503
4504         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4505                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4506                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4507                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4508                                            vr_hot_gpio);
4509         }
4510
4511         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4512         if (ret)
4513                 return ret;
4514
4515         ret = si_populate_smc_acpi_state(rdev, table);
4516         if (ret)
4517                 return ret;
4518
4519         table->driverState = table->initialState;
4520
4521         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4522                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4523         if (ret)
4524                 return ret;
4525
4526         if (ulv->supported && ulv->pl.vddc) {
4527                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4528                 if (ret)
4529                         return ret;
4530
4531                 ret = si_program_ulv_memory_timing_parameters(rdev);
4532                 if (ret)
4533                         return ret;
4534
4535                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4536                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4537
4538                 lane_width = radeon_get_pcie_lanes(rdev);
4539                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4540         } else {
4541                 table->ULVState = table->initialState;
4542         }
4543
4544         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4545                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4546                                     si_pi->sram_end);
4547 }
4548
4549 static int si_calculate_sclk_params(struct radeon_device *rdev,
4550                                     u32 engine_clock,
4551                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4552 {
4553         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4554         struct si_power_info *si_pi = si_get_pi(rdev);
4555         struct atom_clock_dividers dividers;
4556         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4557         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4558         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4559         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4560         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4561         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4562         u64 tmp;
4563         u32 reference_clock = rdev->clock.spll.reference_freq;
4564         u32 reference_divider;
4565         u32 fbdiv;
4566         int ret;
4567
4568         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4569                                              engine_clock, false, &dividers);
4570         if (ret)
4571                 return ret;
4572
4573         reference_divider = 1 + dividers.ref_div;
4574
4575         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4576         do_div(tmp, reference_clock);
4577         fbdiv = (u32) tmp;
4578
4579         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4580         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4581         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4582
4583         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4584         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4585
4586         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4587         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4588         spll_func_cntl_3 |= SPLL_DITHEN;
4589
4590         if (pi->sclk_ss) {
4591                 struct radeon_atom_ss ss;
4592                 u32 vco_freq = engine_clock * dividers.post_div;
4593
4594                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4595                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4596                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4597                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4598
4599                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4600                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4601                         cg_spll_spread_spectrum |= SSEN;
4602
4603                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4604                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4605                 }
4606         }
4607
4608         sclk->sclk_value = engine_clock;
4609         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4610         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4611         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4612         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4613         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4614         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4615
4616         return 0;
4617 }
4618
4619 static int si_populate_sclk_value(struct radeon_device *rdev,
4620                                   u32 engine_clock,
4621                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4622 {
4623         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4624         int ret;
4625
4626         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4627         if (!ret) {
4628                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4629                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4630                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4631                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4632                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4633                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4634                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4635         }
4636
4637         return ret;
4638 }
4639
4640 static int si_populate_mclk_value(struct radeon_device *rdev,
4641                                   u32 engine_clock,
4642                                   u32 memory_clock,
4643                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4644                                   bool strobe_mode,
4645                                   bool dll_state_on)
4646 {
4647         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4648         struct si_power_info *si_pi = si_get_pi(rdev);
4649         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4650         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4651         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4652         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4653         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4654         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4655         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4656         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4657         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4658         struct atom_mpll_param mpll_param;
4659         int ret;
4660
4661         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4662         if (ret)
4663                 return ret;
4664
4665         mpll_func_cntl &= ~BWCTRL_MASK;
4666         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4667
4668         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4669         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4670                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4671
4672         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4673         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4674
4675         if (pi->mem_gddr5) {
4676                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4677                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4678                         YCLK_POST_DIV(mpll_param.post_div);
4679         }
4680
4681         if (pi->mclk_ss) {
4682                 struct radeon_atom_ss ss;
4683                 u32 freq_nom;
4684                 u32 tmp;
4685                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4686
4687                 if (pi->mem_gddr5)
4688                         freq_nom = memory_clock * 4;
4689                 else
4690                         freq_nom = memory_clock * 2;
4691
4692                 tmp = freq_nom / reference_clock;
4693                 tmp = tmp * tmp;
4694                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4695                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4696                         u32 clks = reference_clock * 5 / ss.rate;
4697                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4698
4699                         mpll_ss1 &= ~CLKV_MASK;
4700                         mpll_ss1 |= CLKV(clkv);
4701
4702                         mpll_ss2 &= ~CLKS_MASK;
4703                         mpll_ss2 |= CLKS(clks);
4704                 }
4705         }
4706
4707         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4708         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4709
4710         if (dll_state_on)
4711                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4712         else
4713                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4714
4715         mclk->mclk_value = cpu_to_be32(memory_clock);
4716         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4717         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4718         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4719         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4720         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4721         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4722         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4723         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4724         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4725
4726         return 0;
4727 }
4728
4729 static void si_populate_smc_sp(struct radeon_device *rdev,
4730                                struct radeon_ps *radeon_state,
4731                                SISLANDS_SMC_SWSTATE *smc_state)
4732 {
4733         struct ni_ps *ps = ni_get_ps(radeon_state);
4734         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4735         int i;
4736
4737         for (i = 0; i < ps->performance_level_count - 1; i++)
4738                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4739
4740         smc_state->levels[ps->performance_level_count - 1].bSP =
4741                 cpu_to_be32(pi->psp);
4742 }
4743
4744 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4745                                          struct rv7xx_pl *pl,
4746                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4747 {
4748         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4749         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4750         struct si_power_info *si_pi = si_get_pi(rdev);
4751         int ret;
4752         bool dll_state_on;
4753         u16 std_vddc;
4754         bool gmc_pg = false;
4755
4756         if (eg_pi->pcie_performance_request &&
4757             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4758                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4759         else
4760                 level->gen2PCIE = (u8)pl->pcie_gen;
4761
4762         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4763         if (ret)
4764                 return ret;
4765
4766         level->mcFlags =  0;
4767
4768         if (pi->mclk_stutter_mode_threshold &&
4769             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4770             !eg_pi->uvd_enabled &&
4771             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4772             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4773                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4774
4775                 if (gmc_pg)
4776                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4777         }
4778
4779         if (pi->mem_gddr5) {
4780                 if (pl->mclk > pi->mclk_edc_enable_threshold)
4781                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4782
4783                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4784                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4785
4786                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4787
4788                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4789                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4790                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4791                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4792                         else
4793                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4794                 } else {
4795                         dll_state_on = false;
4796                 }
4797         } else {
4798                 level->strobeMode = si_get_strobe_mode_settings(rdev,
4799                                                                 pl->mclk);
4800
4801                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4802         }
4803
4804         ret = si_populate_mclk_value(rdev,
4805                                      pl->sclk,
4806                                      pl->mclk,
4807                                      &level->mclk,
4808                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4809         if (ret)
4810                 return ret;
4811
4812         ret = si_populate_voltage_value(rdev,
4813                                         &eg_pi->vddc_voltage_table,
4814                                         pl->vddc, &level->vddc);
4815         if (ret)
4816                 return ret;
4817
4818
4819         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4820         if (ret)
4821                 return ret;
4822
4823         ret = si_populate_std_voltage_value(rdev, std_vddc,
4824                                             level->vddc.index, &level->std_vddc);
4825         if (ret)
4826                 return ret;
4827
4828         if (eg_pi->vddci_control) {
4829                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4830                                                 pl->vddci, &level->vddci);
4831                 if (ret)
4832                         return ret;
4833         }
4834
4835         if (si_pi->vddc_phase_shed_control) {
4836                 ret = si_populate_phase_shedding_value(rdev,
4837                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4838                                                        pl->vddc,
4839                                                        pl->sclk,
4840                                                        pl->mclk,
4841                                                        &level->vddc);
4842                 if (ret)
4843                         return ret;
4844         }
4845
4846         level->MaxPoweredUpCU = si_pi->max_cu;
4847
4848         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4849
4850         return ret;
4851 }
4852
4853 static int si_populate_smc_t(struct radeon_device *rdev,
4854                              struct radeon_ps *radeon_state,
4855                              SISLANDS_SMC_SWSTATE *smc_state)
4856 {
4857         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4858         struct ni_ps *state = ni_get_ps(radeon_state);
4859         u32 a_t;
4860         u32 t_l, t_h;
4861         u32 high_bsp;
4862         int i, ret;
4863
4864         if (state->performance_level_count >= 9)
4865                 return -EINVAL;
4866
4867         if (state->performance_level_count < 2) {
4868                 a_t = CG_R(0xffff) | CG_L(0);
4869                 smc_state->levels[0].aT = cpu_to_be32(a_t);
4870                 return 0;
4871         }
4872
4873         smc_state->levels[0].aT = cpu_to_be32(0);
4874
4875         for (i = 0; i <= state->performance_level_count - 2; i++) {
4876                 ret = r600_calculate_at(
4877                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4878                         100 * R600_AH_DFLT,
4879                         state->performance_levels[i + 1].sclk,
4880                         state->performance_levels[i].sclk,
4881                         &t_l,
4882                         &t_h);
4883
4884                 if (ret) {
4885                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4886                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
4887                 }
4888
4889                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
4890                 a_t |= CG_R(t_l * pi->bsp / 20000);
4891                 smc_state->levels[i].aT = cpu_to_be32(a_t);
4892
4893                 high_bsp = (i == state->performance_level_count - 2) ?
4894                         pi->pbsp : pi->bsp;
4895                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
4896                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
4897         }
4898
4899         return 0;
4900 }
4901
4902 static int si_disable_ulv(struct radeon_device *rdev)
4903 {
4904         struct si_power_info *si_pi = si_get_pi(rdev);
4905         struct si_ulv_param *ulv = &si_pi->ulv;
4906
4907         if (ulv->supported)
4908                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
4909                         0 : -EINVAL;
4910
4911         return 0;
4912 }
4913
4914 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
4915                                        struct radeon_ps *radeon_state)
4916 {
4917         const struct si_power_info *si_pi = si_get_pi(rdev);
4918         const struct si_ulv_param *ulv = &si_pi->ulv;
4919         const struct ni_ps *state = ni_get_ps(radeon_state);
4920         int i;
4921
4922         if (state->performance_levels[0].mclk != ulv->pl.mclk)
4923                 return false;
4924
4925         /* XXX validate against display requirements! */
4926
4927         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
4928                 if (rdev->clock.current_dispclk <=
4929                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
4930                         if (ulv->pl.vddc <
4931                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
4932                                 return false;
4933                 }
4934         }
4935
4936         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
4937                 return false;
4938
4939         return true;
4940 }
4941
4942 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
4943                                                        struct radeon_ps *radeon_new_state)
4944 {
4945         const struct si_power_info *si_pi = si_get_pi(rdev);
4946         const struct si_ulv_param *ulv = &si_pi->ulv;
4947
4948         if (ulv->supported) {
4949                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
4950                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
4951                                 0 : -EINVAL;
4952         }
4953         return 0;
4954 }
4955
4956 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
4957                                          struct radeon_ps *radeon_state,
4958                                          SISLANDS_SMC_SWSTATE *smc_state)
4959 {
4960         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4961         struct ni_power_info *ni_pi = ni_get_pi(rdev);
4962         struct si_power_info *si_pi = si_get_pi(rdev);
4963         struct ni_ps *state = ni_get_ps(radeon_state);
4964         int i, ret;
4965         u32 threshold;
4966         u32 sclk_in_sr = 1350; /* ??? */
4967
4968         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
4969                 return -EINVAL;
4970
4971         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
4972
4973         if (radeon_state->vclk && radeon_state->dclk) {
4974                 eg_pi->uvd_enabled = true;
4975                 if (eg_pi->smu_uvd_hs)
4976                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
4977         } else {
4978                 eg_pi->uvd_enabled = false;
4979         }
4980
4981         if (state->dc_compatible)
4982                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
4983
4984         smc_state->levelCount = 0;
4985         for (i = 0; i < state->performance_level_count; i++) {
4986                 if (eg_pi->sclk_deep_sleep) {
4987                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
4988                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4989                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4990                                 else
4991                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4992                         }
4993                 }
4994
4995                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
4996                                                     &smc_state->levels[i]);
4997                 smc_state->levels[i].arbRefreshState =
4998                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
4999
5000                 if (ret)
5001                         return ret;
5002
5003                 if (ni_pi->enable_power_containment)
5004                         smc_state->levels[i].displayWatermark =
5005                                 (state->performance_levels[i].sclk < threshold) ?
5006                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5007                 else
5008                         smc_state->levels[i].displayWatermark = (i < 2) ?
5009                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5010
5011                 if (eg_pi->dynamic_ac_timing)
5012                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5013                 else
5014                         smc_state->levels[i].ACIndex = 0;
5015
5016                 smc_state->levelCount++;
5017         }
5018
5019         si_write_smc_soft_register(rdev,
5020                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5021                                    threshold / 512);
5022
5023         si_populate_smc_sp(rdev, radeon_state, smc_state);
5024
5025         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5026         if (ret)
5027                 ni_pi->enable_power_containment = false;
5028
5029         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5030         if (ret)
5031                 ni_pi->enable_sq_ramping = false;
5032
5033         return si_populate_smc_t(rdev, radeon_state, smc_state);
5034 }
5035
5036 static int si_upload_sw_state(struct radeon_device *rdev,
5037                               struct radeon_ps *radeon_new_state)
5038 {
5039         struct si_power_info *si_pi = si_get_pi(rdev);
5040         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5041         int ret;
5042         u32 address = si_pi->state_table_start +
5043                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5044         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5045                 ((new_state->performance_level_count - 1) *
5046                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5047         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5048
5049         memset(smc_state, 0, state_size);
5050
5051         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5052         if (ret)
5053                 return ret;
5054
5055         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5056                                    state_size, si_pi->sram_end);
5057
5058         return ret;
5059 }
5060
5061 static int si_upload_ulv_state(struct radeon_device *rdev)
5062 {
5063         struct si_power_info *si_pi = si_get_pi(rdev);
5064         struct si_ulv_param *ulv = &si_pi->ulv;
5065         int ret = 0;
5066
5067         if (ulv->supported && ulv->pl.vddc) {
5068                 u32 address = si_pi->state_table_start +
5069                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5070                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5071                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5072
5073                 memset(smc_state, 0, state_size);
5074
5075                 ret = si_populate_ulv_state(rdev, smc_state);
5076                 if (!ret)
5077                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5078                                                    state_size, si_pi->sram_end);
5079         }
5080
5081         return ret;
5082 }
5083
5084 static int si_upload_smc_data(struct radeon_device *rdev)
5085 {
5086         struct radeon_crtc *radeon_crtc = NULL;
5087         int i;
5088
5089         if (rdev->pm.dpm.new_active_crtc_count == 0)
5090                 return 0;
5091
5092         for (i = 0; i < rdev->num_crtc; i++) {
5093                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5094                         radeon_crtc = rdev->mode_info.crtcs[i];
5095                         break;
5096                 }
5097         }
5098
5099         if (radeon_crtc == NULL)
5100                 return 0;
5101
5102         if (radeon_crtc->line_time <= 0)
5103                 return 0;
5104
5105         if (si_write_smc_soft_register(rdev,
5106                                        SI_SMC_SOFT_REGISTER_crtc_index,
5107                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5108                 return 0;
5109
5110         if (si_write_smc_soft_register(rdev,
5111                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5112                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5113                 return 0;
5114
5115         if (si_write_smc_soft_register(rdev,
5116                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5117                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5118                 return 0;
5119
5120         return 0;
5121 }
5122
5123 static int si_set_mc_special_registers(struct radeon_device *rdev,
5124                                        struct si_mc_reg_table *table)
5125 {
5126         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5127         u8 i, j, k;
5128         u32 temp_reg;
5129
5130         for (i = 0, j = table->last; i < table->last; i++) {
5131                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5132                         return -EINVAL;
5133                 switch (table->mc_reg_address[i].s1 << 2) {
5134                 case MC_SEQ_MISC1:
5135                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5136                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5137                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5138                         for (k = 0; k < table->num_entries; k++)
5139                                 table->mc_reg_table_entry[k].mc_data[j] =
5140                                         ((temp_reg & 0xffff0000)) |
5141                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5142                         j++;
5143                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5144                                 return -EINVAL;
5145
5146                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5147                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5148                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5149                         for (k = 0; k < table->num_entries; k++) {
5150                                 table->mc_reg_table_entry[k].mc_data[j] =
5151                                         (temp_reg & 0xffff0000) |
5152                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5153                                 if (!pi->mem_gddr5)
5154                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5155                         }
5156                         j++;
5157                         if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5158                                 return -EINVAL;
5159
5160                         if (!pi->mem_gddr5) {
5161                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5162                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5163                                 for (k = 0; k < table->num_entries; k++)
5164                                         table->mc_reg_table_entry[k].mc_data[j] =
5165                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5166                                 j++;
5167                                 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5168                                         return -EINVAL;
5169                         }
5170                         break;
5171                 case MC_SEQ_RESERVE_M:
5172                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5173                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5174                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5175                         for(k = 0; k < table->num_entries; k++)
5176                                 table->mc_reg_table_entry[k].mc_data[j] =
5177                                         (temp_reg & 0xffff0000) |
5178                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5179                         j++;
5180                         if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5181                                 return -EINVAL;
5182                         break;
5183                 default:
5184                         break;
5185                 }
5186         }
5187
5188         table->last = j;
5189
5190         return 0;
5191 }
5192
5193 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5194 {
5195         bool result = true;
5196
5197         switch (in_reg) {
5198         case  MC_SEQ_RAS_TIMING >> 2:
5199                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5200                 break;
5201         case MC_SEQ_CAS_TIMING >> 2:
5202                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5203                 break;
5204         case MC_SEQ_MISC_TIMING >> 2:
5205                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5206                 break;
5207         case MC_SEQ_MISC_TIMING2 >> 2:
5208                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5209                 break;
5210         case MC_SEQ_RD_CTL_D0 >> 2:
5211                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5212                 break;
5213         case MC_SEQ_RD_CTL_D1 >> 2:
5214                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5215                 break;
5216         case MC_SEQ_WR_CTL_D0 >> 2:
5217                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5218                 break;
5219         case MC_SEQ_WR_CTL_D1 >> 2:
5220                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5221                 break;
5222         case MC_PMG_CMD_EMRS >> 2:
5223                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5224                 break;
5225         case MC_PMG_CMD_MRS >> 2:
5226                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5227                 break;
5228         case MC_PMG_CMD_MRS1 >> 2:
5229                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5230                 break;
5231         case MC_SEQ_PMG_TIMING >> 2:
5232                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5233                 break;
5234         case MC_PMG_CMD_MRS2 >> 2:
5235                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5236                 break;
5237         case MC_SEQ_WR_CTL_2 >> 2:
5238                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5239                 break;
5240         default:
5241                 result = false;
5242                 break;
5243         }
5244
5245         return result;
5246 }
5247
5248 static void si_set_valid_flag(struct si_mc_reg_table *table)
5249 {
5250         u8 i, j;
5251
5252         for (i = 0; i < table->last; i++) {
5253                 for (j = 1; j < table->num_entries; j++) {
5254                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5255                                 table->valid_flag |= 1 << i;
5256                                 break;
5257                         }
5258                 }
5259         }
5260 }
5261
5262 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5263 {
5264         u32 i;
5265         u16 address;
5266
5267         for (i = 0; i < table->last; i++)
5268                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5269                         address : table->mc_reg_address[i].s1;
5270
5271 }
5272
5273 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5274                                       struct si_mc_reg_table *si_table)
5275 {
5276         u8 i, j;
5277
5278         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5279                 return -EINVAL;
5280         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5281                 return -EINVAL;
5282
5283         for (i = 0; i < table->last; i++)
5284                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5285         si_table->last = table->last;
5286
5287         for (i = 0; i < table->num_entries; i++) {
5288                 si_table->mc_reg_table_entry[i].mclk_max =
5289                         table->mc_reg_table_entry[i].mclk_max;
5290                 for (j = 0; j < table->last; j++) {
5291                         si_table->mc_reg_table_entry[i].mc_data[j] =
5292                                 table->mc_reg_table_entry[i].mc_data[j];
5293                 }
5294         }
5295         si_table->num_entries = table->num_entries;
5296
5297         return 0;
5298 }
5299
5300 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5301 {
5302         struct si_power_info *si_pi = si_get_pi(rdev);
5303         struct atom_mc_reg_table *table;
5304         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5305         u8 module_index = rv770_get_memory_module_index(rdev);
5306         int ret;
5307
5308         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5309         if (!table)
5310                 return -ENOMEM;
5311
5312         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5313         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5314         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5315         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5316         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5317         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5318         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5319         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5320         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5321         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5322         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5323         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5324         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5325         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5326
5327         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5328         if (ret)
5329                 goto init_mc_done;
5330
5331         ret = si_copy_vbios_mc_reg_table(table, si_table);
5332         if (ret)
5333                 goto init_mc_done;
5334
5335         si_set_s0_mc_reg_index(si_table);
5336
5337         ret = si_set_mc_special_registers(rdev, si_table);
5338         if (ret)
5339                 goto init_mc_done;
5340
5341         si_set_valid_flag(si_table);
5342
5343 init_mc_done:
5344         kfree(table);
5345
5346         return ret;
5347
5348 }
5349
5350 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5351                                          SMC_SIslands_MCRegisters *mc_reg_table)
5352 {
5353         struct si_power_info *si_pi = si_get_pi(rdev);
5354         u32 i, j;
5355
5356         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5357                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5358                         if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
5359                                 break;
5360                         mc_reg_table->address[i].s0 =
5361                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5362                         mc_reg_table->address[i].s1 =
5363                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5364                         i++;
5365                 }
5366         }
5367         mc_reg_table->last = (u8)i;
5368 }
5369
5370 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5371                                     SMC_SIslands_MCRegisterSet *data,
5372                                     u32 num_entries, u32 valid_flag)
5373 {
5374         u32 i, j;
5375
5376         for(i = 0, j = 0; j < num_entries; j++) {
5377                 if (valid_flag & (1 << j)) {
5378                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5379                         i++;
5380                 }
5381         }
5382 }
5383
5384 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5385                                                  struct rv7xx_pl *pl,
5386                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5387 {
5388         struct si_power_info *si_pi = si_get_pi(rdev);
5389         u32 i = 0;
5390
5391         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5392                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5393                         break;
5394         }
5395
5396         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5397                 --i;
5398
5399         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5400                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5401                                 si_pi->mc_reg_table.valid_flag);
5402 }
5403
5404 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5405                                            struct radeon_ps *radeon_state,
5406                                            SMC_SIslands_MCRegisters *mc_reg_table)
5407 {
5408         struct ni_ps *state = ni_get_ps(radeon_state);
5409         int i;
5410
5411         for (i = 0; i < state->performance_level_count; i++) {
5412                 si_convert_mc_reg_table_entry_to_smc(rdev,
5413                                                      &state->performance_levels[i],
5414                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5415         }
5416 }
5417
5418 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5419                                     struct radeon_ps *radeon_boot_state)
5420 {
5421         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5422         struct si_power_info *si_pi = si_get_pi(rdev);
5423         struct si_ulv_param *ulv = &si_pi->ulv;
5424         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5425
5426         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5427
5428         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5429
5430         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5431
5432         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5433                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5434
5435         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5436                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5437                                 si_pi->mc_reg_table.last,
5438                                 si_pi->mc_reg_table.valid_flag);
5439
5440         if (ulv->supported && ulv->pl.vddc != 0)
5441                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5442                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5443         else
5444                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5445                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5446                                         si_pi->mc_reg_table.last,
5447                                         si_pi->mc_reg_table.valid_flag);
5448
5449         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5450
5451         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5452                                     (u8 *)smc_mc_reg_table,
5453                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5454 }
5455
5456 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5457                                   struct radeon_ps *radeon_new_state)
5458 {
5459         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5460         struct si_power_info *si_pi = si_get_pi(rdev);
5461         u32 address = si_pi->mc_reg_table_start +
5462                 offsetof(SMC_SIslands_MCRegisters,
5463                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5464         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5465
5466         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5467
5468         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5469
5470
5471         return si_copy_bytes_to_smc(rdev, address,
5472                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5473                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5474                                     si_pi->sram_end);
5475
5476 }
5477
5478 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5479 {
5480         if (enable)
5481                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5482         else
5483                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5484 }
5485
5486 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5487                                                       struct radeon_ps *radeon_state)
5488 {
5489         struct ni_ps *state = ni_get_ps(radeon_state);
5490         int i;
5491         u16 pcie_speed, max_speed = 0;
5492
5493         for (i = 0; i < state->performance_level_count; i++) {
5494                 pcie_speed = state->performance_levels[i].pcie_gen;
5495                 if (max_speed < pcie_speed)
5496                         max_speed = pcie_speed;
5497         }
5498         return max_speed;
5499 }
5500
5501 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5502 {
5503         u32 speed_cntl;
5504
5505         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5506         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5507
5508         return (u16)speed_cntl;
5509 }
5510
5511 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5512                                                              struct radeon_ps *radeon_new_state,
5513                                                              struct radeon_ps *radeon_current_state)
5514 {
5515         struct si_power_info *si_pi = si_get_pi(rdev);
5516         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5517         enum radeon_pcie_gen current_link_speed;
5518
5519         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5520                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5521         else
5522                 current_link_speed = si_pi->force_pcie_gen;
5523
5524         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5525         si_pi->pspp_notify_required = false;
5526         if (target_link_speed > current_link_speed) {
5527                 switch (target_link_speed) {
5528 #if defined(CONFIG_ACPI)
5529                 case RADEON_PCIE_GEN3:
5530                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5531                                 break;
5532                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5533                         if (current_link_speed == RADEON_PCIE_GEN2)
5534                                 break;
5535                 case RADEON_PCIE_GEN2:
5536                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5537                                 break;
5538 #endif
5539                 default:
5540                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5541                         break;
5542                 }
5543         } else {
5544                 if (target_link_speed < current_link_speed)
5545                         si_pi->pspp_notify_required = true;
5546         }
5547 }
5548
5549 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5550                                                            struct radeon_ps *radeon_new_state,
5551                                                            struct radeon_ps *radeon_current_state)
5552 {
5553         struct si_power_info *si_pi = si_get_pi(rdev);
5554         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5555         u8 request;
5556
5557         if (si_pi->pspp_notify_required) {
5558                 if (target_link_speed == RADEON_PCIE_GEN3)
5559                         request = PCIE_PERF_REQ_PECI_GEN3;
5560                 else if (target_link_speed == RADEON_PCIE_GEN2)
5561                         request = PCIE_PERF_REQ_PECI_GEN2;
5562                 else
5563                         request = PCIE_PERF_REQ_PECI_GEN1;
5564
5565                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5566                     (si_get_current_pcie_speed(rdev) > 0))
5567                         return;
5568
5569 #if defined(CONFIG_ACPI)
5570                 radeon_acpi_pcie_performance_request(rdev, request, false);
5571 #endif
5572         }
5573 }
5574
5575 #if 0
5576 static int si_ds_request(struct radeon_device *rdev,
5577                          bool ds_status_on, u32 count_write)
5578 {
5579         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5580
5581         if (eg_pi->sclk_deep_sleep) {
5582                 if (ds_status_on)
5583                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5584                                 PPSMC_Result_OK) ?
5585                                 0 : -EINVAL;
5586                 else
5587                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5588                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5589         }
5590         return 0;
5591 }
5592 #endif
5593
5594 static void si_set_max_cu_value(struct radeon_device *rdev)
5595 {
5596         struct si_power_info *si_pi = si_get_pi(rdev);
5597
5598         if (rdev->family == CHIP_VERDE) {
5599                 switch (rdev->pdev->device) {
5600                 case 0x6820:
5601                 case 0x6825:
5602                 case 0x6821:
5603                 case 0x6823:
5604                 case 0x6827:
5605                         si_pi->max_cu = 10;
5606                         break;
5607                 case 0x682D:
5608                 case 0x6824:
5609                 case 0x682F:
5610                 case 0x6826:
5611                         si_pi->max_cu = 8;
5612                         break;
5613                 case 0x6828:
5614                 case 0x6830:
5615                 case 0x6831:
5616                 case 0x6838:
5617                 case 0x6839:
5618                 case 0x683D:
5619                         si_pi->max_cu = 10;
5620                         break;
5621                 case 0x683B:
5622                 case 0x683F:
5623                 case 0x6829:
5624                         si_pi->max_cu = 8;
5625                         break;
5626                 default:
5627                         si_pi->max_cu = 0;
5628                         break;
5629                 }
5630         } else {
5631                 si_pi->max_cu = 0;
5632         }
5633 }
5634
5635 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5636                                                              struct radeon_clock_voltage_dependency_table *table)
5637 {
5638         u32 i;
5639         int j;
5640         u16 leakage_voltage;
5641
5642         if (table) {
5643                 for (i = 0; i < table->count; i++) {
5644                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5645                                                                           table->entries[i].v,
5646                                                                           &leakage_voltage)) {
5647                         case 0:
5648                                 table->entries[i].v = leakage_voltage;
5649                                 break;
5650                         case -EAGAIN:
5651                                 return -EINVAL;
5652                         case -EINVAL:
5653                         default:
5654                                 break;
5655                         }
5656                 }
5657
5658                 for (j = (table->count - 2); j >= 0; j--) {
5659                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5660                                 table->entries[j].v : table->entries[j + 1].v;
5661                 }
5662         }
5663         return 0;
5664 }
5665
5666 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5667 {
5668         int ret = 0;
5669
5670         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5671                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5672         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5673                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5674         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5675                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5676         return ret;
5677 }
5678
5679 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5680                                           struct radeon_ps *radeon_new_state,
5681                                           struct radeon_ps *radeon_current_state)
5682 {
5683         u32 lane_width;
5684         u32 new_lane_width =
5685                 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5686         u32 current_lane_width =
5687                 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5688
5689         if (new_lane_width != current_lane_width) {
5690                 radeon_set_pcie_lanes(rdev, new_lane_width);
5691                 lane_width = radeon_get_pcie_lanes(rdev);
5692                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5693         }
5694 }
5695
5696 void si_dpm_setup_asic(struct radeon_device *rdev)
5697 {
5698         rv770_get_memory_type(rdev);
5699         si_read_clock_registers(rdev);
5700         si_enable_acpi_power_management(rdev);
5701 }
5702
5703 static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5704                                         int min_temp, int max_temp)
5705 {
5706         int low_temp = 0 * 1000;
5707         int high_temp = 255 * 1000;
5708
5709         if (low_temp < min_temp)
5710                 low_temp = min_temp;
5711         if (high_temp > max_temp)
5712                 high_temp = max_temp;
5713         if (high_temp < low_temp) {
5714                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5715                 return -EINVAL;
5716         }
5717
5718         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5719         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5720         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5721
5722         rdev->pm.dpm.thermal.min_temp = low_temp;
5723         rdev->pm.dpm.thermal.max_temp = high_temp;
5724
5725         return 0;
5726 }
5727
5728 int si_dpm_enable(struct radeon_device *rdev)
5729 {
5730         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5731         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5732         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5733         int ret;
5734
5735         if (si_is_smc_running(rdev))
5736                 return -EINVAL;
5737         if (pi->voltage_control)
5738                 si_enable_voltage_control(rdev, true);
5739         if (pi->mvdd_control)
5740                 si_get_mvdd_configuration(rdev);
5741         if (pi->voltage_control) {
5742                 ret = si_construct_voltage_tables(rdev);
5743                 if (ret) {
5744                         DRM_ERROR("si_construct_voltage_tables failed\n");
5745                         return ret;
5746                 }
5747         }
5748         if (eg_pi->dynamic_ac_timing) {
5749                 ret = si_initialize_mc_reg_table(rdev);
5750                 if (ret)
5751                         eg_pi->dynamic_ac_timing = false;
5752         }
5753         if (pi->dynamic_ss)
5754                 si_enable_spread_spectrum(rdev, true);
5755         if (pi->thermal_protection)
5756                 si_enable_thermal_protection(rdev, true);
5757         si_setup_bsp(rdev);
5758         si_program_git(rdev);
5759         si_program_tp(rdev);
5760         si_program_tpp(rdev);
5761         si_program_sstp(rdev);
5762         si_enable_display_gap(rdev);
5763         si_program_vc(rdev);
5764         ret = si_upload_firmware(rdev);
5765         if (ret) {
5766                 DRM_ERROR("si_upload_firmware failed\n");
5767                 return ret;
5768         }
5769         ret = si_process_firmware_header(rdev);
5770         if (ret) {
5771                 DRM_ERROR("si_process_firmware_header failed\n");
5772                 return ret;
5773         }
5774         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5775         if (ret) {
5776                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5777                 return ret;
5778         }
5779         ret = si_init_smc_table(rdev);
5780         if (ret) {
5781                 DRM_ERROR("si_init_smc_table failed\n");
5782                 return ret;
5783         }
5784         ret = si_init_smc_spll_table(rdev);
5785         if (ret) {
5786                 DRM_ERROR("si_init_smc_spll_table failed\n");
5787                 return ret;
5788         }
5789         ret = si_init_arb_table_index(rdev);
5790         if (ret) {
5791                 DRM_ERROR("si_init_arb_table_index failed\n");
5792                 return ret;
5793         }
5794         if (eg_pi->dynamic_ac_timing) {
5795                 ret = si_populate_mc_reg_table(rdev, boot_ps);
5796                 if (ret) {
5797                         DRM_ERROR("si_populate_mc_reg_table failed\n");
5798                         return ret;
5799                 }
5800         }
5801         ret = si_initialize_smc_cac_tables(rdev);
5802         if (ret) {
5803                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5804                 return ret;
5805         }
5806         ret = si_initialize_hardware_cac_manager(rdev);
5807         if (ret) {
5808                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5809                 return ret;
5810         }
5811         ret = si_initialize_smc_dte_tables(rdev);
5812         if (ret) {
5813                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5814                 return ret;
5815         }
5816         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5817         if (ret) {
5818                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5819                 return ret;
5820         }
5821         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5822         if (ret) {
5823                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5824                 return ret;
5825         }
5826         si_program_response_times(rdev);
5827         si_program_ds_registers(rdev);
5828         si_dpm_start_smc(rdev);
5829         ret = si_notify_smc_display_change(rdev, false);
5830         if (ret) {
5831                 DRM_ERROR("si_notify_smc_display_change failed\n");
5832                 return ret;
5833         }
5834         si_enable_sclk_control(rdev, true);
5835         si_start_dpm(rdev);
5836
5837         if (rdev->irq.installed &&
5838             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5839                 PPSMC_Result result;
5840
5841                 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5842                 if (ret)
5843                         return ret;
5844                 rdev->irq.dpm_thermal = true;
5845                 radeon_irq_set(rdev);
5846                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5847
5848                 if (result != PPSMC_Result_OK)
5849                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5850         }
5851
5852         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5853
5854         ni_update_current_ps(rdev, boot_ps);
5855
5856         return 0;
5857 }
5858
5859 void si_dpm_disable(struct radeon_device *rdev)
5860 {
5861         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5862         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5863
5864         if (!si_is_smc_running(rdev))
5865                 return;
5866         si_disable_ulv(rdev);
5867         si_clear_vc(rdev);
5868         if (pi->thermal_protection)
5869                 si_enable_thermal_protection(rdev, false);
5870         si_enable_power_containment(rdev, boot_ps, false);
5871         si_enable_smc_cac(rdev, boot_ps, false);
5872         si_enable_spread_spectrum(rdev, false);
5873         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5874         si_stop_dpm(rdev);
5875         si_reset_to_default(rdev);
5876         si_dpm_stop_smc(rdev);
5877         si_force_switch_to_arb_f0(rdev);
5878
5879         ni_update_current_ps(rdev, boot_ps);
5880 }
5881
5882 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
5883 {
5884         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5885         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5886         struct radeon_ps *new_ps = &requested_ps;
5887
5888         ni_update_requested_ps(rdev, new_ps);
5889
5890         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
5891
5892         return 0;
5893 }
5894
5895 static int si_power_control_set_level(struct radeon_device *rdev)
5896 {
5897         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
5898         int ret;
5899
5900         ret = si_restrict_performance_levels_before_switch(rdev);
5901         if (ret)
5902                 return ret;
5903         ret = si_halt_smc(rdev);
5904         if (ret)
5905                 return ret;
5906         ret = si_populate_smc_tdp_limits(rdev, new_ps);
5907         if (ret)
5908                 return ret;
5909         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
5910         if (ret)
5911                 return ret;
5912         ret = si_resume_smc(rdev);
5913         if (ret)
5914                 return ret;
5915         ret = si_set_sw_state(rdev);
5916         if (ret)
5917                 return ret;
5918         return 0;
5919 }
5920
5921 int si_dpm_set_power_state(struct radeon_device *rdev)
5922 {
5923         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5924         struct radeon_ps *new_ps = &eg_pi->requested_rps;
5925         struct radeon_ps *old_ps = &eg_pi->current_rps;
5926         int ret;
5927
5928         ret = si_disable_ulv(rdev);
5929         if (ret) {
5930                 DRM_ERROR("si_disable_ulv failed\n");
5931                 return ret;
5932         }
5933         ret = si_restrict_performance_levels_before_switch(rdev);
5934         if (ret) {
5935                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
5936                 return ret;
5937         }
5938         if (eg_pi->pcie_performance_request)
5939                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5940         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
5941         ret = si_enable_power_containment(rdev, new_ps, false);
5942         if (ret) {
5943                 DRM_ERROR("si_enable_power_containment failed\n");
5944                 return ret;
5945         }
5946         ret = si_enable_smc_cac(rdev, new_ps, false);
5947         if (ret) {
5948                 DRM_ERROR("si_enable_smc_cac failed\n");
5949                 return ret;
5950         }
5951         ret = si_halt_smc(rdev);
5952         if (ret) {
5953                 DRM_ERROR("si_halt_smc failed\n");
5954                 return ret;
5955         }
5956         ret = si_upload_sw_state(rdev, new_ps);
5957         if (ret) {
5958                 DRM_ERROR("si_upload_sw_state failed\n");
5959                 return ret;
5960         }
5961         ret = si_upload_smc_data(rdev);
5962         if (ret) {
5963                 DRM_ERROR("si_upload_smc_data failed\n");
5964                 return ret;
5965         }
5966         ret = si_upload_ulv_state(rdev);
5967         if (ret) {
5968                 DRM_ERROR("si_upload_ulv_state failed\n");
5969                 return ret;
5970         }
5971         if (eg_pi->dynamic_ac_timing) {
5972                 ret = si_upload_mc_reg_table(rdev, new_ps);
5973                 if (ret) {
5974                         DRM_ERROR("si_upload_mc_reg_table failed\n");
5975                         return ret;
5976                 }
5977         }
5978         ret = si_program_memory_timing_parameters(rdev, new_ps);
5979         if (ret) {
5980                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
5981                 return ret;
5982         }
5983         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
5984
5985         ret = si_resume_smc(rdev);
5986         if (ret) {
5987                 DRM_ERROR("si_resume_smc failed\n");
5988                 return ret;
5989         }
5990         ret = si_set_sw_state(rdev);
5991         if (ret) {
5992                 DRM_ERROR("si_set_sw_state failed\n");
5993                 return ret;
5994         }
5995         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
5996         if (eg_pi->pcie_performance_request)
5997                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5998         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
5999         if (ret) {
6000                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6001                 return ret;
6002         }
6003         ret = si_enable_smc_cac(rdev, new_ps, true);
6004         if (ret) {
6005                 DRM_ERROR("si_enable_smc_cac failed\n");
6006                 return ret;
6007         }
6008         ret = si_enable_power_containment(rdev, new_ps, true);
6009         if (ret) {
6010                 DRM_ERROR("si_enable_power_containment failed\n");
6011                 return ret;
6012         }
6013
6014         ret = si_power_control_set_level(rdev);
6015         if (ret) {
6016                 DRM_ERROR("si_power_control_set_level failed\n");
6017                 return ret;
6018         }
6019
6020         ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
6021         if (ret) {
6022                 DRM_ERROR("si_dpm_force_performance_level failed\n");
6023                 return ret;
6024         }
6025
6026         return 0;
6027 }
6028
6029 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6030 {
6031         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6032         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6033
6034         ni_update_current_ps(rdev, new_ps);
6035 }
6036
6037
6038 void si_dpm_reset_asic(struct radeon_device *rdev)
6039 {
6040         si_restrict_performance_levels_before_switch(rdev);
6041         si_disable_ulv(rdev);
6042         si_set_boot_state(rdev);
6043 }
6044
6045 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6046 {
6047         si_program_display_gap(rdev);
6048 }
6049
6050 union power_info {
6051         struct _ATOM_POWERPLAY_INFO info;
6052         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6053         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6054         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6055         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6056         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6057 };
6058
6059 union pplib_clock_info {
6060         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6061         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6062         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6063         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6064         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6065 };
6066
6067 union pplib_power_state {
6068         struct _ATOM_PPLIB_STATE v1;
6069         struct _ATOM_PPLIB_STATE_V2 v2;
6070 };
6071
6072 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6073                                           struct radeon_ps *rps,
6074                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6075                                           u8 table_rev)
6076 {
6077         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6078         rps->class = le16_to_cpu(non_clock_info->usClassification);
6079         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6080
6081         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6082                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6083                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6084         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6085                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6086                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6087         } else {
6088                 rps->vclk = 0;
6089                 rps->dclk = 0;
6090         }
6091
6092         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6093                 rdev->pm.dpm.boot_ps = rps;
6094         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6095                 rdev->pm.dpm.uvd_ps = rps;
6096 }
6097
6098 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6099                                       struct radeon_ps *rps, int index,
6100                                       union pplib_clock_info *clock_info)
6101 {
6102         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6103         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6104         struct si_power_info *si_pi = si_get_pi(rdev);
6105         struct ni_ps *ps = ni_get_ps(rps);
6106         u16 leakage_voltage;
6107         struct rv7xx_pl *pl = &ps->performance_levels[index];
6108         int ret;
6109
6110         ps->performance_level_count = index + 1;
6111
6112         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6113         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6114         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6115         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6116
6117         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6118         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6119         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6120         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6121                                                  si_pi->sys_pcie_mask,
6122                                                  si_pi->boot_pcie_gen,
6123                                                  clock_info->si.ucPCIEGen);
6124
6125         /* patch up vddc if necessary */
6126         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6127                                                         &leakage_voltage);
6128         if (ret == 0)
6129                 pl->vddc = leakage_voltage;
6130
6131         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6132                 pi->acpi_vddc = pl->vddc;
6133                 eg_pi->acpi_vddci = pl->vddci;
6134                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6135         }
6136
6137         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6138             index == 0) {
6139                 /* XXX disable for A0 tahiti */
6140                 si_pi->ulv.supported = true;
6141                 si_pi->ulv.pl = *pl;
6142                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6143                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6144                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6145                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6146         }
6147
6148         if (pi->min_vddc_in_table > pl->vddc)
6149                 pi->min_vddc_in_table = pl->vddc;
6150
6151         if (pi->max_vddc_in_table < pl->vddc)
6152                 pi->max_vddc_in_table = pl->vddc;
6153
6154         /* patch up boot state */
6155         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6156                 u16 vddc, vddci, mvdd;
6157                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6158                 pl->mclk = rdev->clock.default_mclk;
6159                 pl->sclk = rdev->clock.default_sclk;
6160                 pl->vddc = vddc;
6161                 pl->vddci = vddci;
6162                 si_pi->mvdd_bootup_value = mvdd;
6163         }
6164
6165         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6166             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6167                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6168                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6169                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6170                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6171         }
6172 }
6173
6174 static int si_parse_power_table(struct radeon_device *rdev)
6175 {
6176         struct radeon_mode_info *mode_info = &rdev->mode_info;
6177         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6178         union pplib_power_state *power_state;
6179         int i, j, k, non_clock_array_index, clock_array_index;
6180         union pplib_clock_info *clock_info;
6181         struct _StateArray *state_array;
6182         struct _ClockInfoArray *clock_info_array;
6183         struct _NonClockInfoArray *non_clock_info_array;
6184         union power_info *power_info;
6185         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6186         u16 data_offset;
6187         u8 frev, crev;
6188         u8 *power_state_offset;
6189         struct ni_ps *ps;
6190
6191         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6192                                    &frev, &crev, &data_offset))
6193                 return -EINVAL;
6194         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6195
6196         state_array = (struct _StateArray *)
6197                 (mode_info->atom_context->bios + data_offset +
6198                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6199         clock_info_array = (struct _ClockInfoArray *)
6200                 (mode_info->atom_context->bios + data_offset +
6201                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6202         non_clock_info_array = (struct _NonClockInfoArray *)
6203                 (mode_info->atom_context->bios + data_offset +
6204                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6205
6206         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6207                                   state_array->ucNumEntries, GFP_KERNEL);
6208         if (!rdev->pm.dpm.ps)
6209                 return -ENOMEM;
6210         power_state_offset = (u8 *)state_array->states;
6211         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
6212         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
6213         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
6214         for (i = 0; i < state_array->ucNumEntries; i++) {
6215                 power_state = (union pplib_power_state *)power_state_offset;
6216                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6217                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6218                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6219                 if (!rdev->pm.power_state[i].clock_info)
6220                         return -EINVAL;
6221                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6222                 if (ps == NULL) {
6223                         kfree(rdev->pm.dpm.ps);
6224                         return -ENOMEM;
6225                 }
6226                 rdev->pm.dpm.ps[i].ps_priv = ps;
6227                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6228                                               non_clock_info,
6229                                               non_clock_info_array->ucEntrySize);
6230                 k = 0;
6231                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6232                         clock_array_index = power_state->v2.clockInfoIndex[j];
6233                         if (clock_array_index >= clock_info_array->ucNumEntries)
6234                                 continue;
6235                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6236                                 break;
6237                         clock_info = (union pplib_clock_info *)
6238                                 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6239                         si_parse_pplib_clock_info(rdev,
6240                                                   &rdev->pm.dpm.ps[i], k,
6241                                                   clock_info);
6242                         k++;
6243                 }
6244                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6245         }
6246         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6247         return 0;
6248 }
6249
6250 int si_dpm_init(struct radeon_device *rdev)
6251 {
6252         struct rv7xx_power_info *pi;
6253         struct evergreen_power_info *eg_pi;
6254         struct ni_power_info *ni_pi;
6255         struct si_power_info *si_pi;
6256         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
6257         u16 data_offset, size;
6258         u8 frev, crev;
6259         struct atom_clock_dividers dividers;
6260         int ret;
6261         u32 mask;
6262
6263         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6264         if (si_pi == NULL)
6265                 return -ENOMEM;
6266         rdev->pm.dpm.priv = si_pi;
6267         ni_pi = &si_pi->ni;
6268         eg_pi = &ni_pi->eg;
6269         pi = &eg_pi->rv7xx;
6270
6271         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6272         if (ret)
6273                 si_pi->sys_pcie_mask = 0;
6274         else
6275                 si_pi->sys_pcie_mask = mask;
6276         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6277         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6278
6279         si_set_max_cu_value(rdev);
6280
6281         rv770_get_max_vddc(rdev);
6282         si_get_leakage_vddc(rdev);
6283         si_patch_dependency_tables_based_on_leakage(rdev);
6284
6285         pi->acpi_vddc = 0;
6286         eg_pi->acpi_vddci = 0;
6287         pi->min_vddc_in_table = 0;
6288         pi->max_vddc_in_table = 0;
6289
6290         ret = si_parse_power_table(rdev);
6291         if (ret)
6292                 return ret;
6293         ret = r600_parse_extended_power_table(rdev);
6294         if (ret)
6295                 return ret;
6296
6297         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6298                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6299         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6300                 r600_free_extended_power_table(rdev);
6301                 return -ENOMEM;
6302         }
6303         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6304         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6305         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6306         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6307         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6308         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6309         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6310         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6311         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6312
6313         if (rdev->pm.dpm.voltage_response_time == 0)
6314                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6315         if (rdev->pm.dpm.backbias_response_time == 0)
6316                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6317
6318         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6319                                              0, false, &dividers);
6320         if (ret)
6321                 pi->ref_div = dividers.ref_div + 1;
6322         else
6323                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6324
6325         eg_pi->smu_uvd_hs = false;
6326
6327         pi->mclk_strobe_mode_threshold = 40000;
6328         if (si_is_special_1gb_platform(rdev))
6329                 pi->mclk_stutter_mode_threshold = 0;
6330         else
6331                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6332         pi->mclk_edc_enable_threshold = 40000;
6333         eg_pi->mclk_edc_wr_enable_threshold = 40000;
6334
6335         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6336
6337         pi->voltage_control =
6338                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6339
6340         pi->mvdd_control =
6341                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6342
6343         eg_pi->vddci_control =
6344                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6345
6346         si_pi->vddc_phase_shed_control =
6347                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6348
6349         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
6350                                    &frev, &crev, &data_offset)) {
6351                 pi->sclk_ss = true;
6352                 pi->mclk_ss = true;
6353                 pi->dynamic_ss = true;
6354         } else {
6355                 pi->sclk_ss = false;
6356                 pi->mclk_ss = false;
6357                 pi->dynamic_ss = true;
6358         }
6359
6360         pi->asi = RV770_ASI_DFLT;
6361         pi->pasi = CYPRESS_HASI_DFLT;
6362         pi->vrc = SISLANDS_VRC_DFLT;
6363
6364         pi->gfx_clock_gating = true;
6365
6366         eg_pi->sclk_deep_sleep = true;
6367         si_pi->sclk_deep_sleep_above_low = false;
6368
6369         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
6370                 pi->thermal_protection = true;
6371         else
6372                 pi->thermal_protection = false;
6373
6374         eg_pi->dynamic_ac_timing = true;
6375
6376         eg_pi->light_sleep = true;
6377 #if defined(CONFIG_ACPI)
6378         eg_pi->pcie_performance_request =
6379                 radeon_acpi_is_pcie_performance_request_supported(rdev);
6380 #else
6381         eg_pi->pcie_performance_request = false;
6382 #endif
6383
6384         si_pi->sram_end = SMC_RAM_END;
6385
6386         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6387         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6388         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6389         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6390         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6391         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6392         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6393
6394         si_initialize_powertune_defaults(rdev);
6395
6396         return 0;
6397 }
6398
6399 void si_dpm_fini(struct radeon_device *rdev)
6400 {
6401         int i;
6402
6403         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6404                 kfree(rdev->pm.dpm.ps[i].ps_priv);
6405         }
6406         kfree(rdev->pm.dpm.ps);
6407         kfree(rdev->pm.dpm.priv);
6408         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6409         r600_free_extended_power_table(rdev);
6410 }
6411
6412 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6413                                                     struct seq_file *m)
6414 {
6415         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
6416         struct ni_ps *ps = ni_get_ps(rps);
6417         struct rv7xx_pl *pl;
6418         u32 current_index =
6419                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6420                 CURRENT_STATE_INDEX_SHIFT;
6421
6422         if (current_index >= ps->performance_level_count) {
6423                 seq_printf(m, "invalid dpm profile %d\n", current_index);
6424         } else {
6425                 pl = &ps->performance_levels[current_index];
6426                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6427                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6428                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6429         }
6430 }