4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 select OLD_SIGSUSPEND3
62 The ARM series is a line of low-power-consumption RISC chip designs
63 licensed by ARM Ltd and targeted at embedded applications and
64 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
65 manufactured, but legacy ARM-based PC hardware remains popular in
66 Europe. There is an ARM Linux project with a web page at
67 <http://www.arm.linux.org.uk/>.
69 config ARM_HAS_SG_CHAIN
72 config NEED_SG_DMA_LENGTH
75 config ARM_DMA_USE_IOMMU
77 select ARM_HAS_SG_CHAIN
78 select NEED_SG_DMA_LENGTH
82 config ARM_DMA_IOMMU_ALIGNMENT
83 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
87 DMA mapping framework by default aligns all buffers to the smallest
88 PAGE_SIZE order which is greater than or equal to the requested buffer
89 size. This works well for buffers up to a few hundreds kilobytes, but
90 for larger buffers it just a waste of address space. Drivers which has
91 relatively small addressing window (like 64Mib) might run out of
92 virtual space with just a few allocations.
94 With this parameter you can specify the maximum PAGE_SIZE order for
95 DMA IOMMU buffers. Larger buffers will be aligned only to this
96 specified order. The order is expressed as a power of two multiplied
104 config MIGHT_HAVE_PCI
107 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config GENERIC_HWEIGHT
182 config GENERIC_CALIBRATE_DELAY
186 config ARCH_MAY_HAVE_PC_FDC
192 config NEED_DMA_MAP_STATE
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
198 config GENERIC_ISA_DMA
204 config NEED_RET_TO_USER
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
216 The base address of exception vectors.
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
275 bool "MMU-based Paged Memory Management Support"
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
293 select ARM_PATCH_PHYS_VIRT
296 select MULTI_IRQ_HANDLER
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
313 select VERSATILE_FPGA_IRQ
315 Support for ARM's Integrator platform.
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_TIMER_SP804
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
348 This enables support for ARM Ltd Versatile board.
352 select ARCH_REQUIRE_GPIOLIB
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
359 select PINCTRL_AT91 if USE_OF
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
365 bool "Broadcom BCM2835 family"
366 select ARCH_REQUIRE_GPIOLIB
368 select ARM_ERRATA_411920
369 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
375 select MULTI_IRQ_HANDLER
377 select PINCTRL_BCM2835
381 This enables support for the Broadcom BCM2835 SoC. This SoC is
382 use in the Raspberry Pi, and Roku 2 devices.
385 bool "Cavium Networks CNS3XXX family"
388 select GENERIC_CLOCKEVENTS
389 select MIGHT_HAVE_CACHE_L2X0
390 select MIGHT_HAVE_PCI
391 select PCI_DOMAINS if PCI
393 Support for Cavium Networks CNS3XXX platform.
396 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
397 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_CLOCKEVENTS
403 select MULTI_IRQ_HANDLER
404 select NEED_MACH_MEMORY_H
407 Support for Cirrus Logic 711x/721x/731x based boards.
410 bool "Cortina Systems Gemini"
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_USES_GETTIMEOFFSET
415 Support for the Cortina Systems Gemini family SoCs
419 select ARCH_REQUIRE_GPIOLIB
422 select GENERIC_CLOCKEVENTS
423 select GENERIC_IRQ_CHIP
424 select MIGHT_HAVE_CACHE_L2X0
430 Support for CSR SiRFprimaII/Marco/Polo platforms
434 select ARCH_USES_GETTIMEOFFSET
437 select NEED_MACH_IO_H
438 select NEED_MACH_MEMORY_H
441 This is an evaluation board for the StrongARM processor available
442 from Digital. It has limited hardware on-board, including an
443 Ethernet interface, two PCMCIA sockets, two serial ports and a
448 select ARCH_HAS_HOLES_MEMORYMODEL
449 select ARCH_REQUIRE_GPIOLIB
450 select ARCH_USES_GETTIMEOFFSET
455 select NEED_MACH_MEMORY_H
457 This enables support for the Cirrus EP93xx series of CPUs.
459 config ARCH_FOOTBRIDGE
463 select GENERIC_CLOCKEVENTS
465 select NEED_MACH_IO_H if !MMU
466 select NEED_MACH_MEMORY_H
468 Support for systems based on the DC21285 companion chip
469 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
472 bool "Freescale MXS-based"
473 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
479 select HAVE_CLK_PREPARE
480 select MULTI_IRQ_HANDLER
486 Support for Freescale MXS-based family of processors
489 bool "Hilscher NetX based"
493 select GENERIC_CLOCKEVENTS
495 This enables support for systems based on the Hilscher NetX Soc
498 bool "Hynix HMS720x-based"
499 select ARCH_USES_GETTIMEOFFSET
503 This enables support for systems based on the Hynix HMS720x
508 select ARCH_SUPPORTS_MSI
510 select NEED_MACH_MEMORY_H
511 select NEED_RET_TO_USER
516 Support for Intel's IOP13XX (XScale) family of processors.
521 select ARCH_REQUIRE_GPIOLIB
523 select NEED_MACH_GPIO_H
524 select NEED_RET_TO_USER
528 Support for Intel's 80219 and IOP32X (XScale) family of
534 select ARCH_REQUIRE_GPIOLIB
536 select NEED_MACH_GPIO_H
537 select NEED_RET_TO_USER
541 Support for Intel's IOP33X (XScale) family of processors.
546 select ARCH_HAS_DMA_SET_COHERENT_MASK
547 select ARCH_REQUIRE_GPIOLIB
550 select DMABOUNCE if PCI
551 select GENERIC_CLOCKEVENTS
552 select MIGHT_HAVE_PCI
553 select NEED_MACH_IO_H
555 Support for Intel's IXP4XX (XScale) family of processors.
559 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
562 select MIGHT_HAVE_PCI
565 select PLAT_ORION_LEGACY
566 select USB_ARCH_HAS_EHCI
569 Support for the Marvell Dove SoC 88AP510
572 bool "Marvell Kirkwood"
573 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
579 select PINCTRL_KIRKWOOD
580 select PLAT_ORION_LEGACY
583 Support for the following Marvell Kirkwood series SoCs:
584 88F6180, 88F6192 and 88F6281.
587 bool "Marvell MV78xx0"
588 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
592 select PLAT_ORION_LEGACY
595 Support for the following Marvell MV78xx0 series SoCs:
601 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
605 select PLAT_ORION_LEGACY
608 Support for the following Marvell Orion 5x series SoCs:
609 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
610 Orion-2 (5281), Orion-1-90 (6183).
613 bool "Marvell PXA168/910/MMP2"
615 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_ALLOCATOR
618 select GENERIC_CLOCKEVENTS
621 select NEED_MACH_GPIO_H
626 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
629 bool "Micrel/Kendin KS8695"
630 select ARCH_REQUIRE_GPIOLIB
633 select GENERIC_CLOCKEVENTS
634 select NEED_MACH_MEMORY_H
636 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
637 System-on-Chip devices.
640 bool "Nuvoton W90X900 CPU"
641 select ARCH_REQUIRE_GPIOLIB
645 select GENERIC_CLOCKEVENTS
647 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
648 At present, the w90x900 has been renamed nuc900, regarding
649 the ARM series product line, you can login the following
650 link address to know more.
652 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
653 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
657 select ARCH_REQUIRE_GPIOLIB
662 select GENERIC_CLOCKEVENTS
665 select USB_ARCH_HAS_OHCI
668 Support for the NXP LPC32XX family of processors
672 select ARCH_HAS_CPUFREQ
673 select ARCH_REQUIRE_GPIOLIB
678 select GENERIC_CLOCKEVENTS
681 select MIGHT_HAVE_CACHE_L2X0
686 This enables support for NVIDIA Tegra based systems (Tegra APX,
687 Tegra 6xx and Tegra 2 series).
690 bool "PXA2xx/PXA3xx-based"
692 select ARCH_HAS_CPUFREQ
694 select ARCH_REQUIRE_GPIOLIB
695 select ARM_CPU_SUSPEND if PM
699 select GENERIC_CLOCKEVENTS
702 select MULTI_IRQ_HANDLER
703 select NEED_MACH_GPIO_H
707 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
711 select ARCH_REQUIRE_GPIOLIB
713 select GENERIC_CLOCKEVENTS
716 Support for Qualcomm MSM/QSD based systems. This runs on the
717 apps processor of the MSM/QSD and depends on a shared memory
718 interface to the modem processor which runs the baseband
719 stack and controls some vital subsystems
720 (clock and power control, etc).
723 bool "Renesas SH-Mobile / R-Mobile"
725 select GENERIC_CLOCKEVENTS
727 select HAVE_MACH_CLKDEV
729 select MIGHT_HAVE_CACHE_L2X0
730 select MULTI_IRQ_HANDLER
731 select NEED_MACH_MEMORY_H
734 select PM_GENERIC_DOMAINS if PM
737 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
742 select ARCH_MAY_HAVE_PC_FDC
743 select ARCH_SPARSEMEM_ENABLE
744 select ARCH_USES_GETTIMEOFFSET
747 select HAVE_PATA_PLATFORM
749 select NEED_MACH_IO_H
750 select NEED_MACH_MEMORY_H
754 On the Acorn Risc-PC, Linux can support the internal IDE disk and
755 CD-ROM interface, serial and parallel port, and the floppy drive.
759 select ARCH_HAS_CPUFREQ
761 select ARCH_REQUIRE_GPIOLIB
762 select ARCH_SPARSEMEM_ENABLE
767 select GENERIC_CLOCKEVENTS
770 select NEED_MACH_GPIO_H
771 select NEED_MACH_MEMORY_H
774 Support for StrongARM 11x0 based boards.
777 bool "Samsung S3C24XX SoCs"
778 select ARCH_HAS_CPUFREQ
781 select GENERIC_CLOCKEVENTS
784 select HAVE_S3C2410_I2C if I2C
785 select HAVE_S3C2410_WATCHDOG if WATCHDOG
786 select HAVE_S3C_RTC if RTC_CLASS
787 select NEED_MACH_GPIO_H
788 select NEED_MACH_IO_H
790 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
791 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
792 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
793 Samsung SMDK2410 development board (and derivatives).
796 bool "Samsung S3C64XX"
797 select ARCH_HAS_CPUFREQ
798 select ARCH_REQUIRE_GPIOLIB
803 select GENERIC_CLOCKEVENTS
805 select HAVE_S3C2410_I2C if I2C
806 select HAVE_S3C2410_WATCHDOG if WATCHDOG
808 select NEED_MACH_GPIO_H
812 select S3C_GPIO_TRACK
813 select SAMSUNG_CLKSRC
814 select SAMSUNG_GPIOLIB_4BIT
815 select SAMSUNG_IRQ_VIC_TIMER
816 select USB_ARCH_HAS_OHCI
818 Samsung S3C64XX series based systems
821 bool "Samsung S5P6440 S5P6450"
825 select GENERIC_CLOCKEVENTS
827 select HAVE_S3C2410_I2C if I2C
828 select HAVE_S3C2410_WATCHDOG if WATCHDOG
829 select HAVE_S3C_RTC if RTC_CLASS
830 select NEED_MACH_GPIO_H
832 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
836 bool "Samsung S5PC100"
840 select GENERIC_CLOCKEVENTS
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
845 select HAVE_S3C_RTC if RTC_CLASS
846 select NEED_MACH_GPIO_H
848 Samsung S5PC100 series based systems
851 bool "Samsung S5PV210/S5PC110"
852 select ARCH_HAS_CPUFREQ
853 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_SPARSEMEM_ENABLE
858 select GENERIC_CLOCKEVENTS
860 select HAVE_S3C2410_I2C if I2C
861 select HAVE_S3C2410_WATCHDOG if WATCHDOG
862 select HAVE_S3C_RTC if RTC_CLASS
863 select NEED_MACH_GPIO_H
864 select NEED_MACH_MEMORY_H
866 Samsung S5PV210/S5PC110 series based systems
869 bool "Samsung EXYNOS"
870 select ARCH_HAS_CPUFREQ
871 select ARCH_HAS_HOLES_MEMORYMODEL
872 select ARCH_SPARSEMEM_ENABLE
876 select GENERIC_CLOCKEVENTS
878 select HAVE_S3C2410_I2C if I2C
879 select HAVE_S3C2410_WATCHDOG if WATCHDOG
880 select HAVE_S3C_RTC if RTC_CLASS
881 select NEED_MACH_GPIO_H
882 select NEED_MACH_MEMORY_H
884 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
888 select ARCH_USES_GETTIMEOFFSET
892 select NEED_MACH_MEMORY_H
897 Support for the StrongARM based Digital DNARD machine, also known
898 as "Shark" (<http://www.shark-linux.de/shark.html>).
901 bool "ST-Ericsson U300 Series"
903 select ARCH_REQUIRE_GPIOLIB
905 select ARM_PATCH_PHYS_VIRT
911 select GENERIC_CLOCKEVENTS
915 Support for ST-Ericsson U300 series mobile platforms.
918 bool "ST-Ericsson U8500 Series"
920 select ARCH_HAS_CPUFREQ
921 select ARCH_REQUIRE_GPIOLIB
925 select GENERIC_CLOCKEVENTS
927 select MIGHT_HAVE_CACHE_L2X0
930 Support for ST-Ericsson's Ux500 architecture
933 bool "STMicroelectronics Nomadik"
934 select ARCH_REQUIRE_GPIOLIB
937 select CLKSRC_NOMADIK_MTU
940 select GENERIC_CLOCKEVENTS
941 select MIGHT_HAVE_CACHE_L2X0
944 select PINCTRL_STN8815
947 Support for the Nomadik platform by ST-Ericsson
951 select ARCH_HAS_CPUFREQ
952 select ARCH_REQUIRE_GPIOLIB
957 select GENERIC_CLOCKEVENTS
960 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
964 select ARCH_HAS_HOLES_MEMORYMODEL
965 select ARCH_REQUIRE_GPIOLIB
967 select GENERIC_ALLOCATOR
968 select GENERIC_CLOCKEVENTS
969 select GENERIC_IRQ_CHIP
971 select NEED_MACH_GPIO_H
975 Support for TI's DaVinci platform.
980 select ARCH_HAS_CPUFREQ
981 select ARCH_HAS_HOLES_MEMORYMODEL
983 select ARCH_REQUIRE_GPIOLIB
986 select GENERIC_CLOCKEVENTS
987 select GENERIC_IRQ_CHIP
991 select NEED_MACH_IO_H if PCCARD
992 select NEED_MACH_MEMORY_H
994 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
998 menu "Multiple platform selection"
999 depends on ARCH_MULTIPLATFORM
1001 comment "CPU Core family selection"
1003 config ARCH_MULTI_V4
1004 bool "ARMv4 based platforms (FA526, StrongARM)"
1005 depends on !ARCH_MULTI_V6_V7
1006 select ARCH_MULTI_V4_V5
1008 config ARCH_MULTI_V4T
1009 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
1010 depends on !ARCH_MULTI_V6_V7
1011 select ARCH_MULTI_V4_V5
1013 config ARCH_MULTI_V5
1014 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1015 depends on !ARCH_MULTI_V6_V7
1016 select ARCH_MULTI_V4_V5
1018 config ARCH_MULTI_V4_V5
1021 config ARCH_MULTI_V6
1022 bool "ARMv6 based platforms (ARM11)"
1023 select ARCH_MULTI_V6_V7
1026 config ARCH_MULTI_V7
1027 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
1029 select ARCH_MULTI_V6_V7
1030 select ARCH_VEXPRESS
1033 config ARCH_MULTI_V6_V7
1036 config ARCH_MULTI_CPU_AUTO
1037 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1038 select ARCH_MULTI_V5
1043 # This is sorted alphabetically by mach-* pathname. However, plat-*
1044 # Kconfigs may be included either alphabetically (according to the
1045 # plat- suffix) or along side the corresponding mach-* source.
1047 source "arch/arm/mach-mvebu/Kconfig"
1049 source "arch/arm/mach-at91/Kconfig"
1051 source "arch/arm/mach-bcm/Kconfig"
1053 source "arch/arm/mach-clps711x/Kconfig"
1055 source "arch/arm/mach-cns3xxx/Kconfig"
1057 source "arch/arm/mach-davinci/Kconfig"
1059 source "arch/arm/mach-dove/Kconfig"
1061 source "arch/arm/mach-ep93xx/Kconfig"
1063 source "arch/arm/mach-footbridge/Kconfig"
1065 source "arch/arm/mach-gemini/Kconfig"
1067 source "arch/arm/mach-h720x/Kconfig"
1069 source "arch/arm/mach-highbank/Kconfig"
1071 source "arch/arm/mach-integrator/Kconfig"
1073 source "arch/arm/mach-iop32x/Kconfig"
1075 source "arch/arm/mach-iop33x/Kconfig"
1077 source "arch/arm/mach-iop13xx/Kconfig"
1079 source "arch/arm/mach-ixp4xx/Kconfig"
1081 source "arch/arm/mach-kirkwood/Kconfig"
1083 source "arch/arm/mach-ks8695/Kconfig"
1085 source "arch/arm/mach-msm/Kconfig"
1087 source "arch/arm/mach-mv78xx0/Kconfig"
1089 source "arch/arm/mach-imx/Kconfig"
1091 source "arch/arm/mach-mxs/Kconfig"
1093 source "arch/arm/mach-netx/Kconfig"
1095 source "arch/arm/mach-nomadik/Kconfig"
1097 source "arch/arm/plat-omap/Kconfig"
1099 source "arch/arm/mach-omap1/Kconfig"
1101 source "arch/arm/mach-omap2/Kconfig"
1103 source "arch/arm/mach-orion5x/Kconfig"
1105 source "arch/arm/mach-picoxcell/Kconfig"
1107 source "arch/arm/mach-pxa/Kconfig"
1108 source "arch/arm/plat-pxa/Kconfig"
1110 source "arch/arm/mach-mmp/Kconfig"
1112 source "arch/arm/mach-realview/Kconfig"
1114 source "arch/arm/mach-sa1100/Kconfig"
1116 source "arch/arm/plat-samsung/Kconfig"
1118 source "arch/arm/mach-socfpga/Kconfig"
1120 source "arch/arm/plat-spear/Kconfig"
1122 source "arch/arm/mach-s3c24xx/Kconfig"
1125 source "arch/arm/mach-s3c64xx/Kconfig"
1128 source "arch/arm/mach-s5p64x0/Kconfig"
1130 source "arch/arm/mach-s5pc100/Kconfig"
1132 source "arch/arm/mach-s5pv210/Kconfig"
1134 source "arch/arm/mach-exynos/Kconfig"
1136 source "arch/arm/mach-shmobile/Kconfig"
1138 source "arch/arm/mach-sunxi/Kconfig"
1140 source "arch/arm/mach-prima2/Kconfig"
1142 source "arch/arm/mach-tegra/Kconfig"
1144 source "arch/arm/mach-u300/Kconfig"
1146 source "arch/arm/mach-ux500/Kconfig"
1148 source "arch/arm/mach-versatile/Kconfig"
1150 source "arch/arm/mach-vexpress/Kconfig"
1151 source "arch/arm/plat-versatile/Kconfig"
1153 source "arch/arm/mach-virt/Kconfig"
1155 source "arch/arm/mach-vt8500/Kconfig"
1157 source "arch/arm/mach-w90x900/Kconfig"
1159 source "arch/arm/mach-zynq/Kconfig"
1161 # Definitions to make life easier
1167 select GENERIC_CLOCKEVENTS
1173 select GENERIC_IRQ_CHIP
1176 config PLAT_ORION_LEGACY
1183 config PLAT_VERSATILE
1186 config ARM_TIMER_SP804
1189 select HAVE_SCHED_CLOCK
1191 source arch/arm/mm/Kconfig
1195 default 16 if ARCH_EP93XX
1199 bool "Enable iWMMXt support"
1200 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1201 default y if PXA27x || PXA3xx || ARCH_MMP
1203 Enable support for iWMMXt context switching at run time if
1204 running on a CPU that supports it.
1208 depends on CPU_XSCALE
1211 config MULTI_IRQ_HANDLER
1214 Allow each machine to specify it's own IRQ handler at run time.
1217 source "arch/arm/Kconfig-nommu"
1220 config ARM_ERRATA_326103
1221 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1224 Executing a SWP instruction to read-only memory does not set bit 11
1225 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1226 treat the access as a read, preventing a COW from occurring and
1227 causing the faulting task to livelock.
1229 config ARM_ERRATA_411920
1230 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1231 depends on CPU_V6 || CPU_V6K
1233 Invalidation of the Instruction Cache operation can
1234 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1235 It does not affect the MPCore. This option enables the ARM Ltd.
1236 recommended workaround.
1238 config ARM_ERRATA_430973
1239 bool "ARM errata: Stale prediction on replaced interworking branch"
1242 This option enables the workaround for the 430973 Cortex-A8
1243 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1244 interworking branch is replaced with another code sequence at the
1245 same virtual address, whether due to self-modifying code or virtual
1246 to physical address re-mapping, Cortex-A8 does not recover from the
1247 stale interworking branch prediction. This results in Cortex-A8
1248 executing the new code sequence in the incorrect ARM or Thumb state.
1249 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1250 and also flushes the branch target cache at every context switch.
1251 Note that setting specific bits in the ACTLR register may not be
1252 available in non-secure mode.
1254 config ARM_ERRATA_458693
1255 bool "ARM errata: Processor deadlock when a false hazard is created"
1257 depends on !ARCH_MULTIPLATFORM
1259 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1260 erratum. For very specific sequences of memory operations, it is
1261 possible for a hazard condition intended for a cache line to instead
1262 be incorrectly associated with a different cache line. This false
1263 hazard might then cause a processor deadlock. The workaround enables
1264 the L1 caching of the NEON accesses and disables the PLD instruction
1265 in the ACTLR register. Note that setting specific bits in the ACTLR
1266 register may not be available in non-secure mode.
1268 config ARM_ERRATA_460075
1269 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1271 depends on !ARCH_MULTIPLATFORM
1273 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1274 erratum. Any asynchronous access to the L2 cache may encounter a
1275 situation in which recent store transactions to the L2 cache are lost
1276 and overwritten with stale memory contents from external memory. The
1277 workaround disables the write-allocate mode for the L2 cache via the
1278 ACTLR register. Note that setting specific bits in the ACTLR register
1279 may not be available in non-secure mode.
1281 config ARM_ERRATA_742230
1282 bool "ARM errata: DMB operation may be faulty"
1283 depends on CPU_V7 && SMP
1284 depends on !ARCH_MULTIPLATFORM
1286 This option enables the workaround for the 742230 Cortex-A9
1287 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1288 between two write operations may not ensure the correct visibility
1289 ordering of the two writes. This workaround sets a specific bit in
1290 the diagnostic register of the Cortex-A9 which causes the DMB
1291 instruction to behave as a DSB, ensuring the correct behaviour of
1294 config ARM_ERRATA_742231
1295 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1296 depends on CPU_V7 && SMP
1297 depends on !ARCH_MULTIPLATFORM
1299 This option enables the workaround for the 742231 Cortex-A9
1300 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1301 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1302 accessing some data located in the same cache line, may get corrupted
1303 data due to bad handling of the address hazard when the line gets
1304 replaced from one of the CPUs at the same time as another CPU is
1305 accessing it. This workaround sets specific bits in the diagnostic
1306 register of the Cortex-A9 which reduces the linefill issuing
1307 capabilities of the processor.
1309 config PL310_ERRATA_588369
1310 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1311 depends on CACHE_L2X0
1313 The PL310 L2 cache controller implements three types of Clean &
1314 Invalidate maintenance operations: by Physical Address
1315 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1316 They are architecturally defined to behave as the execution of a
1317 clean operation followed immediately by an invalidate operation,
1318 both performing to the same memory location. This functionality
1319 is not correctly implemented in PL310 as clean lines are not
1320 invalidated as a result of these operations.
1322 config ARM_ERRATA_720789
1323 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1326 This option enables the workaround for the 720789 Cortex-A9 (prior to
1327 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1328 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1329 As a consequence of this erratum, some TLB entries which should be
1330 invalidated are not, resulting in an incoherency in the system page
1331 tables. The workaround changes the TLB flushing routines to invalidate
1332 entries regardless of the ASID.
1334 config PL310_ERRATA_727915
1335 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1336 depends on CACHE_L2X0
1338 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1339 operation (offset 0x7FC). This operation runs in background so that
1340 PL310 can handle normal accesses while it is in progress. Under very
1341 rare circumstances, due to this erratum, write data can be lost when
1342 PL310 treats a cacheable write transaction during a Clean &
1343 Invalidate by Way operation.
1345 config ARM_ERRATA_743622
1346 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1348 depends on !ARCH_MULTIPLATFORM
1350 This option enables the workaround for the 743622 Cortex-A9
1351 (r2p*) erratum. Under very rare conditions, a faulty
1352 optimisation in the Cortex-A9 Store Buffer may lead to data
1353 corruption. This workaround sets a specific bit in the diagnostic
1354 register of the Cortex-A9 which disables the Store Buffer
1355 optimisation, preventing the defect from occurring. This has no
1356 visible impact on the overall performance or power consumption of the
1359 config ARM_ERRATA_751472
1360 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1362 depends on !ARCH_MULTIPLATFORM
1364 This option enables the workaround for the 751472 Cortex-A9 (prior
1365 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1366 completion of a following broadcasted operation if the second
1367 operation is received by a CPU before the ICIALLUIS has completed,
1368 potentially leading to corrupted entries in the cache or TLB.
1370 config PL310_ERRATA_753970
1371 bool "PL310 errata: cache sync operation may be faulty"
1372 depends on CACHE_PL310
1374 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1376 Under some condition the effect of cache sync operation on
1377 the store buffer still remains when the operation completes.
1378 This means that the store buffer is always asked to drain and
1379 this prevents it from merging any further writes. The workaround
1380 is to replace the normal offset of cache sync operation (0x730)
1381 by another offset targeting an unmapped PL310 register 0x740.
1382 This has the same effect as the cache sync operation: store buffer
1383 drain and waiting for all buffers empty.
1385 config ARM_ERRATA_754322
1386 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1389 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1390 r3p*) erratum. A speculative memory access may cause a page table walk
1391 which starts prior to an ASID switch but completes afterwards. This
1392 can populate the micro-TLB with a stale entry which may be hit with
1393 the new ASID. This workaround places two dsb instructions in the mm
1394 switching code so that no page table walks can cross the ASID switch.
1396 config ARM_ERRATA_754327
1397 bool "ARM errata: no automatic Store Buffer drain"
1398 depends on CPU_V7 && SMP
1400 This option enables the workaround for the 754327 Cortex-A9 (prior to
1401 r2p0) erratum. The Store Buffer does not have any automatic draining
1402 mechanism and therefore a livelock may occur if an external agent
1403 continuously polls a memory location waiting to observe an update.
1404 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1405 written polling loops from denying visibility of updates to memory.
1407 config ARM_ERRATA_364296
1408 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1409 depends on CPU_V6 && !SMP
1411 This options enables the workaround for the 364296 ARM1136
1412 r0p2 erratum (possible cache data corruption with
1413 hit-under-miss enabled). It sets the undocumented bit 31 in
1414 the auxiliary control register and the FI bit in the control
1415 register, thus disabling hit-under-miss without putting the
1416 processor into full low interrupt latency mode. ARM11MPCore
1419 config ARM_ERRATA_764369
1420 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1421 depends on CPU_V7 && SMP
1423 This option enables the workaround for erratum 764369
1424 affecting Cortex-A9 MPCore with two or more processors (all
1425 current revisions). Under certain timing circumstances, a data
1426 cache line maintenance operation by MVA targeting an Inner
1427 Shareable memory region may fail to proceed up to either the
1428 Point of Coherency or to the Point of Unification of the
1429 system. This workaround adds a DSB instruction before the
1430 relevant cache maintenance functions and sets a specific bit
1431 in the diagnostic control register of the SCU.
1433 config PL310_ERRATA_769419
1434 bool "PL310 errata: no automatic Store Buffer drain"
1435 depends on CACHE_L2X0
1437 On revisions of the PL310 prior to r3p2, the Store Buffer does
1438 not automatically drain. This can cause normal, non-cacheable
1439 writes to be retained when the memory system is idle, leading
1440 to suboptimal I/O performance for drivers using coherent DMA.
1441 This option adds a write barrier to the cpu_idle loop so that,
1442 on systems with an outer cache, the store buffer is drained
1445 config ARM_ERRATA_775420
1446 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1449 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1450 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1451 operation aborts with MMU exception, it might cause the processor
1452 to deadlock. This workaround puts DSB before executing ISB if
1453 an abort may occur on cache maintenance.
1457 source "arch/arm/common/Kconfig"
1467 Find out whether you have ISA slots on your motherboard. ISA is the
1468 name of a bus system, i.e. the way the CPU talks to the other stuff
1469 inside your box. Other bus systems are PCI, EISA, MicroChannel
1470 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1471 newer boards don't support it. If you have ISA, say Y, otherwise N.
1473 # Select ISA DMA controller support
1478 # Select ISA DMA interface
1483 bool "PCI support" if MIGHT_HAVE_PCI
1485 Find out whether you have a PCI motherboard. PCI is the name of a
1486 bus system, i.e. the way the CPU talks to the other stuff inside
1487 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1488 VESA. If you have PCI, say Y, otherwise N.
1494 config PCI_NANOENGINE
1495 bool "BSE nanoEngine PCI support"
1496 depends on SA1100_NANOENGINE
1498 Enable PCI on the BSE nanoEngine board.
1503 # Select the host bridge type
1504 config PCI_HOST_VIA82C505
1506 depends on PCI && ARCH_SHARK
1509 config PCI_HOST_ITE8152
1511 depends on PCI && MACH_ARMCORE
1515 source "drivers/pci/Kconfig"
1517 source "drivers/pcmcia/Kconfig"
1521 menu "Kernel Features"
1526 This option should be selected by machines which have an SMP-
1529 The only effect of this option is to make the SMP-related
1530 options available to the user for configuration.
1533 bool "Symmetric Multi-Processing"
1534 depends on CPU_V6K || CPU_V7
1535 depends on GENERIC_CLOCKEVENTS
1538 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1539 select USE_GENERIC_SMP_HELPERS
1541 This enables support for systems with more than one CPU. If you have
1542 a system with only one CPU, like most personal computers, say N. If
1543 you have a system with more than one CPU, say Y.
1545 If you say N here, the kernel will run on single and multiprocessor
1546 machines, but will use only one CPU of a multiprocessor machine. If
1547 you say Y here, the kernel will run on many, but not all, single
1548 processor machines. On a single processor machine, the kernel will
1549 run faster if you say N here.
1551 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1552 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1553 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1555 If you don't know what to do here, say N.
1558 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1559 depends on SMP && !XIP_KERNEL
1562 SMP kernels contain instructions which fail on non-SMP processors.
1563 Enabling this option allows the kernel to modify itself to make
1564 these instructions safe. Disabling it allows about 1K of space
1567 If you don't know what to do here, say Y.
1569 config ARM_CPU_TOPOLOGY
1570 bool "Support cpu topology definition"
1571 depends on SMP && CPU_V7
1574 Support ARM cpu topology definition. The MPIDR register defines
1575 affinity between processors which is then used to describe the cpu
1576 topology of an ARM System.
1579 bool "Multi-core scheduler support"
1580 depends on ARM_CPU_TOPOLOGY
1582 Multi-core scheduler support improves the CPU scheduler's decision
1583 making when dealing with multi-core CPU chips at a cost of slightly
1584 increased overhead in some places. If unsure say N here.
1587 bool "SMT scheduler support"
1588 depends on ARM_CPU_TOPOLOGY
1590 Improves the CPU scheduler's decision making when dealing with
1591 MultiThreading at a cost of slightly increased overhead in some
1592 places. If unsure say N here.
1597 This option enables support for the ARM system coherency unit
1599 config HAVE_ARM_ARCH_TIMER
1600 bool "Architected timer support"
1602 select ARM_ARCH_TIMER
1604 This option enables support for the ARM architected timer
1609 select CLKSRC_OF if OF
1611 This options enables support for the ARM timer and watchdog unit
1614 prompt "Memory split"
1617 Select the desired split between kernel and user memory.
1619 If you are not absolutely sure what you are doing, leave this
1623 bool "3G/1G user/kernel split"
1625 bool "2G/2G user/kernel split"
1627 bool "1G/3G user/kernel split"
1632 default 0x40000000 if VMSPLIT_1G
1633 default 0x80000000 if VMSPLIT_2G
1637 int "Maximum number of CPUs (2-32)"
1643 bool "Support for hot-pluggable CPUs"
1644 depends on SMP && HOTPLUG
1646 Say Y here to experiment with turning CPUs off and on. CPUs
1647 can be controlled through /sys/devices/system/cpu.
1650 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1653 Say Y here if you want Linux to communicate with system firmware
1654 implementing the PSCI specification for CPU-centric power
1655 management operations described in ARM document number ARM DEN
1656 0022A ("Power State Coordination Interface System Software on
1660 bool "Use local timer interrupts"
1663 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT)
1665 Enable support for local timers on SMP platforms, rather then the
1666 legacy IPI broadcast method. Local timers allows the system
1667 accounting to be spread across the timer interval, preventing a
1668 "thundering herd" at every timer tick.
1670 # The GPIO number here must be sorted by descending number. In case of
1671 # a multiplatform kernel, we just want the highest value required by the
1672 # selected platforms.
1675 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1676 default 512 if SOC_OMAP5
1677 default 355 if ARCH_U8500
1678 default 288 if ARCH_VT8500 || ARCH_SUNXI
1679 default 264 if MACH_H4700
1682 Maximum number of GPIOs in the system.
1684 If unsure, leave the default value.
1686 source kernel/Kconfig.preempt
1690 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1691 ARCH_S5PV210 || ARCH_EXYNOS4
1692 default AT91_TIMER_HZ if ARCH_AT91
1693 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1697 def_bool HIGH_RES_TIMERS
1699 config THUMB2_KERNEL
1700 bool "Compile the kernel in Thumb-2 mode"
1701 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1703 select ARM_ASM_UNIFIED
1706 By enabling this option, the kernel will be compiled in
1707 Thumb-2 mode. A compiler/assembler that understand the unified
1708 ARM-Thumb syntax is needed.
1712 config THUMB2_AVOID_R_ARM_THM_JUMP11
1713 bool "Work around buggy Thumb-2 short branch relocations in gas"
1714 depends on THUMB2_KERNEL && MODULES
1717 Various binutils versions can resolve Thumb-2 branches to
1718 locally-defined, preemptible global symbols as short-range "b.n"
1719 branch instructions.
1721 This is a problem, because there's no guarantee the final
1722 destination of the symbol, or any candidate locations for a
1723 trampoline, are within range of the branch. For this reason, the
1724 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1725 relocation in modules at all, and it makes little sense to add
1728 The symptom is that the kernel fails with an "unsupported
1729 relocation" error when loading some modules.
1731 Until fixed tools are available, passing
1732 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1733 code which hits this problem, at the cost of a bit of extra runtime
1734 stack usage in some cases.
1736 The problem is described in more detail at:
1737 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1739 Only Thumb-2 kernels are affected.
1741 Unless you are sure your tools don't have this problem, say Y.
1743 config ARM_ASM_UNIFIED
1747 bool "Use the ARM EABI to compile the kernel"
1749 This option allows for the kernel to be compiled using the latest
1750 ARM ABI (aka EABI). This is only useful if you are using a user
1751 space environment that is also compiled with EABI.
1753 Since there are major incompatibilities between the legacy ABI and
1754 EABI, especially with regard to structure member alignment, this
1755 option also changes the kernel syscall calling convention to
1756 disambiguate both ABIs and allow for backward compatibility support
1757 (selected with CONFIG_OABI_COMPAT).
1759 To use this you need GCC version 4.0.0 or later.
1762 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1763 depends on AEABI && !THUMB2_KERNEL
1766 This option preserves the old syscall interface along with the
1767 new (ARM EABI) one. It also provides a compatibility layer to
1768 intercept syscalls that have structure arguments which layout
1769 in memory differs between the legacy ABI and the new ARM EABI
1770 (only for non "thumb" binaries). This option adds a tiny
1771 overhead to all syscalls and produces a slightly larger kernel.
1772 If you know you'll be using only pure EABI user space then you
1773 can say N here. If this option is not selected and you attempt
1774 to execute a legacy ABI binary then the result will be
1775 UNPREDICTABLE (in fact it can be predicted that it won't work
1776 at all). If in doubt say Y.
1778 config ARCH_HAS_HOLES_MEMORYMODEL
1781 config ARCH_SPARSEMEM_ENABLE
1784 config ARCH_SPARSEMEM_DEFAULT
1785 def_bool ARCH_SPARSEMEM_ENABLE
1787 config ARCH_SELECT_MEMORY_MODEL
1788 def_bool ARCH_SPARSEMEM_ENABLE
1790 config HAVE_ARCH_PFN_VALID
1791 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1794 bool "High Memory Support"
1797 The address space of ARM processors is only 4 Gigabytes large
1798 and it has to accommodate user address space, kernel address
1799 space as well as some memory mapped IO. That means that, if you
1800 have a large amount of physical memory and/or IO, not all of the
1801 memory can be "permanently mapped" by the kernel. The physical
1802 memory that is not permanently mapped is called "high memory".
1804 Depending on the selected kernel/user memory split, minimum
1805 vmalloc space and actual amount of RAM, you may not need this
1806 option which should result in a slightly faster kernel.
1811 bool "Allocate 2nd-level pagetables from highmem"
1814 config HW_PERF_EVENTS
1815 bool "Enable hardware performance counter support for perf events"
1816 depends on PERF_EVENTS
1819 Enable hardware performance counter support for perf events. If
1820 disabled, perf events will use software events only.
1824 config FORCE_MAX_ZONEORDER
1825 int "Maximum zone order" if ARCH_SHMOBILE
1826 range 11 64 if ARCH_SHMOBILE
1827 default "12" if SOC_AM33XX
1828 default "9" if SA1111
1831 The kernel memory allocator divides physically contiguous memory
1832 blocks into "zones", where each zone is a power of two number of
1833 pages. This option selects the largest power of two that the kernel
1834 keeps in the memory allocator. If you need to allocate very large
1835 blocks of physically contiguous memory, then you may need to
1836 increase this value.
1838 This config option is actually maximum order plus one. For example,
1839 a value of 11 means that the largest free memory block is 2^10 pages.
1841 config ALIGNMENT_TRAP
1843 depends on CPU_CP15_MMU
1844 default y if !ARCH_EBSA110
1845 select HAVE_PROC_CPU if PROC_FS
1847 ARM processors cannot fetch/store information which is not
1848 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1849 address divisible by 4. On 32-bit ARM processors, these non-aligned
1850 fetch/store instructions will be emulated in software if you say
1851 here, which has a severe performance impact. This is necessary for
1852 correct operation of some network protocols. With an IP-only
1853 configuration it is safe to say N, otherwise say Y.
1855 config UACCESS_WITH_MEMCPY
1856 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1858 default y if CPU_FEROCEON
1860 Implement faster copy_to_user and clear_user methods for CPU
1861 cores where a 8-word STM instruction give significantly higher
1862 memory write throughput than a sequence of individual 32bit stores.
1864 A possible side effect is a slight increase in scheduling latency
1865 between threads sharing the same address space if they invoke
1866 such copy operations with large buffers.
1868 However, if the CPU data cache is using a write-allocate mode,
1869 this option is unlikely to provide any performance gain.
1873 prompt "Enable seccomp to safely compute untrusted bytecode"
1875 This kernel feature is useful for number crunching applications
1876 that may need to compute untrusted bytecode during their
1877 execution. By using pipes or other transports made available to
1878 the process as file descriptors supporting the read/write
1879 syscalls, it's possible to isolate those applications in
1880 their own address space using seccomp. Once seccomp is
1881 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1882 and the task is only allowed to execute a few safe syscalls
1883 defined by each seccomp mode.
1885 config CC_STACKPROTECTOR
1886 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1888 This option turns on the -fstack-protector GCC feature. This
1889 feature puts, at the beginning of functions, a canary value on
1890 the stack just before the return address, and validates
1891 the value just before actually returning. Stack based buffer
1892 overflows (that need to overwrite this return address) now also
1893 overwrite the canary, which gets detected and the attack is then
1894 neutralized via a kernel panic.
1895 This feature requires gcc version 4.2 or above.
1902 bool "Xen guest support on ARM (EXPERIMENTAL)"
1903 depends on ARM && AEABI && OF
1904 depends on CPU_V7 && !CPU_V6
1905 depends on !GENERIC_ATOMIC64
1907 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1914 bool "Flattened Device Tree support"
1917 select OF_EARLY_FLATTREE
1919 Include support for flattened device tree machine descriptions.
1922 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1925 This is the traditional way of passing data to the kernel at boot
1926 time. If you are solely relying on the flattened device tree (or
1927 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1928 to remove ATAGS support from your kernel binary. If unsure,
1931 config DEPRECATED_PARAM_STRUCT
1932 bool "Provide old way to pass kernel parameters"
1935 This was deprecated in 2001 and announced to live on for 5 years.
1936 Some old boot loaders still use this way.
1938 # Compressed boot loader in ROM. Yes, we really want to ask about
1939 # TEXT and BSS so we preserve their values in the config files.
1940 config ZBOOT_ROM_TEXT
1941 hex "Compressed ROM boot loader base address"
1944 The physical address at which the ROM-able zImage is to be
1945 placed in the target. Platforms which normally make use of
1946 ROM-able zImage formats normally set this to a suitable
1947 value in their defconfig file.
1949 If ZBOOT_ROM is not enabled, this has no effect.
1951 config ZBOOT_ROM_BSS
1952 hex "Compressed ROM boot loader BSS address"
1955 The base address of an area of read/write memory in the target
1956 for the ROM-able zImage which must be available while the
1957 decompressor is running. It must be large enough to hold the
1958 entire decompressed kernel plus an additional 128 KiB.
1959 Platforms which normally make use of ROM-able zImage formats
1960 normally set this to a suitable value in their defconfig file.
1962 If ZBOOT_ROM is not enabled, this has no effect.
1965 bool "Compressed boot loader in ROM/flash"
1966 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1968 Say Y here if you intend to execute your compressed kernel image
1969 (zImage) directly from ROM or flash. If unsure, say N.
1972 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1973 depends on ZBOOT_ROM && ARCH_SH7372
1974 default ZBOOT_ROM_NONE
1976 Include experimental SD/MMC loading code in the ROM-able zImage.
1977 With this enabled it is possible to write the ROM-able zImage
1978 kernel image to an MMC or SD card and boot the kernel straight
1979 from the reset vector. At reset the processor Mask ROM will load
1980 the first part of the ROM-able zImage which in turn loads the
1981 rest the kernel image to RAM.
1983 config ZBOOT_ROM_NONE
1984 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1986 Do not load image from SD or MMC
1988 config ZBOOT_ROM_MMCIF
1989 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1991 Load image from MMCIF hardware block.
1993 config ZBOOT_ROM_SH_MOBILE_SDHI
1994 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1996 Load image from SDHI hardware block
2000 config ARM_APPENDED_DTB
2001 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2002 depends on OF && !ZBOOT_ROM
2004 With this option, the boot code will look for a device tree binary
2005 (DTB) appended to zImage
2006 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2008 This is meant as a backward compatibility convenience for those
2009 systems with a bootloader that can't be upgraded to accommodate
2010 the documented boot protocol using a device tree.
2012 Beware that there is very little in terms of protection against
2013 this option being confused by leftover garbage in memory that might
2014 look like a DTB header after a reboot if no actual DTB is appended
2015 to zImage. Do not leave this option active in a production kernel
2016 if you don't intend to always append a DTB. Proper passing of the
2017 location into r2 of a bootloader provided DTB is always preferable
2020 config ARM_ATAG_DTB_COMPAT
2021 bool "Supplement the appended DTB with traditional ATAG information"
2022 depends on ARM_APPENDED_DTB
2024 Some old bootloaders can't be updated to a DTB capable one, yet
2025 they provide ATAGs with memory configuration, the ramdisk address,
2026 the kernel cmdline string, etc. Such information is dynamically
2027 provided by the bootloader and can't always be stored in a static
2028 DTB. To allow a device tree enabled kernel to be used with such
2029 bootloaders, this option allows zImage to extract the information
2030 from the ATAG list and store it at run time into the appended DTB.
2033 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2034 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2036 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2037 bool "Use bootloader kernel arguments if available"
2039 Uses the command-line options passed by the boot loader instead of
2040 the device tree bootargs property. If the boot loader doesn't provide
2041 any, the device tree bootargs property will be used.
2043 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2044 bool "Extend with bootloader kernel arguments"
2046 The command-line arguments provided by the boot loader will be
2047 appended to the the device tree bootargs property.
2052 string "Default kernel command string"
2055 On some architectures (EBSA110 and CATS), there is currently no way
2056 for the boot loader to pass arguments to the kernel. For these
2057 architectures, you should supply some command-line options at build
2058 time by entering them here. As a minimum, you should specify the
2059 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2062 prompt "Kernel command line type" if CMDLINE != ""
2063 default CMDLINE_FROM_BOOTLOADER
2066 config CMDLINE_FROM_BOOTLOADER
2067 bool "Use bootloader kernel arguments if available"
2069 Uses the command-line options passed by the boot loader. If
2070 the boot loader doesn't provide any, the default kernel command
2071 string provided in CMDLINE will be used.
2073 config CMDLINE_EXTEND
2074 bool "Extend bootloader kernel arguments"
2076 The command-line arguments provided by the boot loader will be
2077 appended to the default kernel command string.
2079 config CMDLINE_FORCE
2080 bool "Always use the default kernel command string"
2082 Always use the default kernel command string, even if the boot
2083 loader passes other arguments to the kernel.
2084 This is useful if you cannot or don't want to change the
2085 command-line options your boot loader passes to the kernel.
2089 bool "Kernel Execute-In-Place from ROM"
2090 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2092 Execute-In-Place allows the kernel to run from non-volatile storage
2093 directly addressable by the CPU, such as NOR flash. This saves RAM
2094 space since the text section of the kernel is not loaded from flash
2095 to RAM. Read-write sections, such as the data section and stack,
2096 are still copied to RAM. The XIP kernel is not compressed since
2097 it has to run directly from flash, so it will take more space to
2098 store it. The flash address used to link the kernel object files,
2099 and for storing it, is configuration dependent. Therefore, if you
2100 say Y here, you must know the proper physical address where to
2101 store the kernel image depending on your own flash memory usage.
2103 Also note that the make target becomes "make xipImage" rather than
2104 "make zImage" or "make Image". The final kernel binary to put in
2105 ROM memory will be arch/arm/boot/xipImage.
2109 config XIP_PHYS_ADDR
2110 hex "XIP Kernel Physical Location"
2111 depends on XIP_KERNEL
2112 default "0x00080000"
2114 This is the physical address in your flash memory the kernel will
2115 be linked for and stored to. This address is dependent on your
2119 bool "Kexec system call (EXPERIMENTAL)"
2120 depends on (!SMP || HOTPLUG_CPU)
2122 kexec is a system call that implements the ability to shutdown your
2123 current kernel, and to start another kernel. It is like a reboot
2124 but it is independent of the system firmware. And like a reboot
2125 you can start any kernel with it, not just Linux.
2127 It is an ongoing process to be certain the hardware in a machine
2128 is properly shutdown, so do not be surprised if this code does not
2129 initially work for you. It may help to enable device hotplugging
2133 bool "Export atags in procfs"
2134 depends on ATAGS && KEXEC
2137 Should the atags used to boot the kernel be exported in an "atags"
2138 file in procfs. Useful with kexec.
2141 bool "Build kdump crash kernel (EXPERIMENTAL)"
2143 Generate crash dump after being started by kexec. This should
2144 be normally only set in special crash dump kernels which are
2145 loaded in the main kernel with kexec-tools into a specially
2146 reserved region and then later executed after a crash by
2147 kdump/kexec. The crash dump kernel must be compiled to a
2148 memory address not used by the main kernel
2150 For more details see Documentation/kdump/kdump.txt
2152 config AUTO_ZRELADDR
2153 bool "Auto calculation of the decompressed kernel image address"
2154 depends on !ZBOOT_ROM && !ARCH_U300
2156 ZRELADDR is the physical address where the decompressed kernel
2157 image will be placed. If AUTO_ZRELADDR is selected, the address
2158 will be determined at run-time by masking the current IP with
2159 0xf8000000. This assumes the zImage being placed in the first 128MB
2160 from start of memory.
2164 menu "CPU Power Management"
2168 source "drivers/cpufreq/Kconfig"
2171 tristate "CPUfreq driver for i.MX CPUs"
2172 depends on ARCH_MXC && CPU_FREQ
2173 select CPU_FREQ_TABLE
2175 This enables the CPUfreq driver for i.MX CPUs.
2177 config CPU_FREQ_SA1100
2180 config CPU_FREQ_SA1110
2183 config CPU_FREQ_INTEGRATOR
2184 tristate "CPUfreq driver for ARM Integrator CPUs"
2185 depends on ARCH_INTEGRATOR && CPU_FREQ
2188 This enables the CPUfreq driver for ARM Integrator CPUs.
2190 For details, take a look at <file:Documentation/cpu-freq>.
2196 depends on CPU_FREQ && ARCH_PXA && PXA25x
2198 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2199 select CPU_FREQ_TABLE
2204 Internal configuration node for common cpufreq on Samsung SoC
2206 config CPU_FREQ_S3C24XX
2207 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2208 depends on ARCH_S3C24XX && CPU_FREQ
2211 This enables the CPUfreq driver for the Samsung S3C24XX family
2214 For details, take a look at <file:Documentation/cpu-freq>.
2218 config CPU_FREQ_S3C24XX_PLL
2219 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2220 depends on CPU_FREQ_S3C24XX
2222 Compile in support for changing the PLL frequency from the
2223 S3C24XX series CPUfreq driver. The PLL takes time to settle
2224 after a frequency change, so by default it is not enabled.
2226 This also means that the PLL tables for the selected CPU(s) will
2227 be built which may increase the size of the kernel image.
2229 config CPU_FREQ_S3C24XX_DEBUG
2230 bool "Debug CPUfreq Samsung driver core"
2231 depends on CPU_FREQ_S3C24XX
2233 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2235 config CPU_FREQ_S3C24XX_IODEBUG
2236 bool "Debug CPUfreq Samsung driver IO timing"
2237 depends on CPU_FREQ_S3C24XX
2239 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2241 config CPU_FREQ_S3C24XX_DEBUGFS
2242 bool "Export debugfs for CPUFreq"
2243 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2245 Export status information via debugfs.
2249 source "drivers/cpuidle/Kconfig"
2253 menu "Floating point emulation"
2255 comment "At least one emulation must be selected"
2258 bool "NWFPE math emulation"
2259 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2261 Say Y to include the NWFPE floating point emulator in the kernel.
2262 This is necessary to run most binaries. Linux does not currently
2263 support floating point hardware so you need to say Y here even if
2264 your machine has an FPA or floating point co-processor podule.
2266 You may say N here if you are going to load the Acorn FPEmulator
2267 early in the bootup.
2270 bool "Support extended precision"
2271 depends on FPE_NWFPE
2273 Say Y to include 80-bit support in the kernel floating-point
2274 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2275 Note that gcc does not generate 80-bit operations by default,
2276 so in most cases this option only enlarges the size of the
2277 floating point emulator without any good reason.
2279 You almost surely want to say N here.
2282 bool "FastFPE math emulation (EXPERIMENTAL)"
2283 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2285 Say Y here to include the FAST floating point emulator in the kernel.
2286 This is an experimental much faster emulator which now also has full
2287 precision for the mantissa. It does not support any exceptions.
2288 It is very simple, and approximately 3-6 times faster than NWFPE.
2290 It should be sufficient for most programs. It may be not suitable
2291 for scientific calculations, but you have to check this for yourself.
2292 If you do not feel you need a faster FP emulation you should better
2296 bool "VFP-format floating point maths"
2297 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2299 Say Y to include VFP support code in the kernel. This is needed
2300 if your hardware includes a VFP unit.
2302 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2303 release notes and additional status information.
2305 Say N if your target does not have VFP hardware.
2313 bool "Advanced SIMD (NEON) Extension support"
2314 depends on VFPv3 && CPU_V7
2316 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2321 menu "Userspace binary formats"
2323 source "fs/Kconfig.binfmt"
2326 tristate "RISC OS personality"
2329 Say Y here to include the kernel code necessary if you want to run
2330 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2331 experimental; if this sounds frightening, say N and sleep in peace.
2332 You can also say M here to compile this support as a module (which
2333 will be called arthur).
2337 menu "Power management options"
2339 source "kernel/power/Kconfig"
2341 config ARCH_SUSPEND_POSSIBLE
2342 depends on !ARCH_S5PC100
2343 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2344 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2347 config ARM_CPU_SUSPEND
2352 source "net/Kconfig"
2354 source "drivers/Kconfig"
2358 source "arch/arm/Kconfig.debug"
2360 source "security/Kconfig"
2362 source "crypto/Kconfig"
2364 source "lib/Kconfig"
2366 source "arch/arm/kvm/Kconfig"