2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
29 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
33 /* discrete uvd clocks */
34 #define CG_UPLL_FUNC_CNTL 0x634
35 # define UPLL_RESET_MASK 0x00000001
36 # define UPLL_SLEEP_MASK 0x00000002
37 # define UPLL_BYPASS_EN_MASK 0x00000004
38 # define UPLL_CTLREQ_MASK 0x00000008
39 # define UPLL_VCO_MODE_MASK 0x00000600
40 # define UPLL_REF_DIV_MASK 0x003F0000
41 # define UPLL_CTLACK_MASK 0x40000000
42 # define UPLL_CTLACK2_MASK 0x80000000
43 #define CG_UPLL_FUNC_CNTL_2 0x638
44 # define UPLL_PDIV_A(x) ((x) << 0)
45 # define UPLL_PDIV_A_MASK 0x0000007F
46 # define UPLL_PDIV_B(x) ((x) << 8)
47 # define UPLL_PDIV_B_MASK 0x00007F00
48 # define VCLK_SRC_SEL(x) ((x) << 20)
49 # define VCLK_SRC_SEL_MASK 0x01F00000
50 # define DCLK_SRC_SEL(x) ((x) << 25)
51 # define DCLK_SRC_SEL_MASK 0x3E000000
52 #define CG_UPLL_FUNC_CNTL_3 0x63C
53 # define UPLL_FB_DIV(x) ((x) << 0)
54 # define UPLL_FB_DIV_MASK 0x01FFFFFF
55 #define CG_UPLL_FUNC_CNTL_4 0x644
56 # define UPLL_SPARE_ISPARE9 0x00020000
57 #define CG_UPLL_FUNC_CNTL_5 0x648
58 # define RESET_ANTI_MUX_MASK 0x00000200
59 #define CG_UPLL_SPREAD_SPECTRUM 0x650
60 # define SSEN_MASK 0x00000001
62 #define CG_MULT_THERMAL_STATUS 0x714
63 #define ASIC_MAX_TEMP(x) ((x) << 0)
64 #define ASIC_MAX_TEMP_MASK 0x000001ff
65 #define ASIC_MAX_TEMP_SHIFT 0
66 #define CTF_TEMP(x) ((x) << 9)
67 #define CTF_TEMP_MASK 0x0003fe00
68 #define CTF_TEMP_SHIFT 9
70 #define SI_MAX_SH_GPRS 256
71 #define SI_MAX_TEMP_GPRS 16
72 #define SI_MAX_SH_THREADS 256
73 #define SI_MAX_SH_STACK_ENTRIES 4096
74 #define SI_MAX_FRC_EOV_CNT 16384
75 #define SI_MAX_BACKENDS 8
76 #define SI_MAX_BACKENDS_MASK 0xFF
77 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
78 #define SI_MAX_SIMDS 12
79 #define SI_MAX_SIMDS_MASK 0x0FFF
80 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
81 #define SI_MAX_PIPES 8
82 #define SI_MAX_PIPES_MASK 0xFF
83 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
84 #define SI_MAX_LDS_NUM 0xFFFF
86 #define SI_MAX_TCC_MASK 0xFFFF
88 #define VGA_HDP_CONTROL 0x328
89 #define VGA_MEMORY_DISABLE (1 << 4)
91 #define SPLL_CNTL_MODE 0x618
92 # define SPLL_REFCLK_SEL(x) ((x) << 8)
93 # define SPLL_REFCLK_SEL_MASK 0xFF00
95 #define MPLL_BYPASSCLK_SEL 0x65c
96 # define MPLL_CLKOUT_SEL(x) ((x) << 8)
97 # define MPLL_CLKOUT_SEL_MASK 0xFF00
99 #define CG_CLKPIN_CNTL 0x660
100 # define XTALIN_DIVIDE (1 << 1)
101 # define BCLK_AS_XCLK (1 << 2)
102 #define CG_CLKPIN_CNTL_2 0x664
103 # define FORCE_BIF_REFCLK_EN (1 << 3)
104 # define MUX_TCLK_TO_XCLK (1 << 8)
106 #define THM_CLK_CNTL 0x66c
107 # define CMON_CLK_SEL(x) ((x) << 0)
108 # define CMON_CLK_SEL_MASK 0xFF
109 # define TMON_CLK_SEL(x) ((x) << 8)
110 # define TMON_CLK_SEL_MASK 0xFF00
111 #define MISC_CLK_CNTL 0x670
112 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
113 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF
114 # define ZCLK_SEL(x) ((x) << 8)
115 # define ZCLK_SEL_MASK 0xFF00
117 #define DMIF_ADDR_CONFIG 0xBD4
119 #define DMIF_ADDR_CALC 0xC00
121 #define SRBM_STATUS 0xE50
122 #define GRBM_RQ_PENDING (1 << 5)
123 #define VMC_BUSY (1 << 8)
124 #define MCB_BUSY (1 << 9)
125 #define MCB_NON_DISPLAY_BUSY (1 << 10)
126 #define MCC_BUSY (1 << 11)
127 #define MCD_BUSY (1 << 12)
128 #define SEM_BUSY (1 << 14)
129 #define IH_BUSY (1 << 17)
131 #define SRBM_SOFT_RESET 0x0E60
132 #define SOFT_RESET_BIF (1 << 1)
133 #define SOFT_RESET_DC (1 << 5)
134 #define SOFT_RESET_DMA1 (1 << 6)
135 #define SOFT_RESET_GRBM (1 << 8)
136 #define SOFT_RESET_HDP (1 << 9)
137 #define SOFT_RESET_IH (1 << 10)
138 #define SOFT_RESET_MC (1 << 11)
139 #define SOFT_RESET_ROM (1 << 14)
140 #define SOFT_RESET_SEM (1 << 15)
141 #define SOFT_RESET_VMC (1 << 17)
142 #define SOFT_RESET_DMA (1 << 20)
143 #define SOFT_RESET_TST (1 << 21)
144 #define SOFT_RESET_REGBB (1 << 22)
145 #define SOFT_RESET_ORB (1 << 23)
147 #define CC_SYS_RB_BACKEND_DISABLE 0xe80
148 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
150 #define SRBM_STATUS2 0x0EC4
151 #define DMA_BUSY (1 << 5)
152 #define DMA1_BUSY (1 << 6)
154 #define VM_L2_CNTL 0x1400
155 #define ENABLE_L2_CACHE (1 << 0)
156 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
157 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
158 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
159 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
160 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
161 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
162 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
163 #define VM_L2_CNTL2 0x1404
164 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
165 #define INVALIDATE_L2_CACHE (1 << 1)
166 #define INVALIDATE_CACHE_MODE(x) ((x) << 26)
167 #define INVALIDATE_PTE_AND_PDE_CACHES 0
168 #define INVALIDATE_ONLY_PTE_CACHES 1
169 #define INVALIDATE_ONLY_PDE_CACHES 2
170 #define VM_L2_CNTL3 0x1408
171 #define BANK_SELECT(x) ((x) << 0)
172 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
173 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
174 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
175 #define VM_L2_STATUS 0x140C
176 #define L2_BUSY (1 << 0)
177 #define VM_CONTEXT0_CNTL 0x1410
178 #define ENABLE_CONTEXT (1 << 0)
179 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
180 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
181 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
182 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
183 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
184 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
185 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
186 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
187 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
188 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
189 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
190 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
191 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
192 #define VM_CONTEXT1_CNTL 0x1414
193 #define VM_CONTEXT0_CNTL2 0x1430
194 #define VM_CONTEXT1_CNTL2 0x1434
195 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
196 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
197 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
198 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
199 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
200 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
201 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
202 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
204 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
205 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
207 #define VM_INVALIDATE_REQUEST 0x1478
208 #define VM_INVALIDATE_RESPONSE 0x147c
210 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
211 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
213 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
214 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
215 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
216 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
217 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
218 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
219 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
220 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
221 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
222 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
224 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
225 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
227 #define MC_SHARED_CHMAP 0x2004
228 #define NOOFCHAN_SHIFT 12
229 #define NOOFCHAN_MASK 0x0000f000
230 #define MC_SHARED_CHREMAP 0x2008
232 #define MC_VM_FB_LOCATION 0x2024
233 #define MC_VM_AGP_TOP 0x2028
234 #define MC_VM_AGP_BOT 0x202C
235 #define MC_VM_AGP_BASE 0x2030
236 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
237 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
238 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
240 #define MC_VM_MX_L1_TLB_CNTL 0x2064
241 #define ENABLE_L1_TLB (1 << 0)
242 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
243 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
244 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
245 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
246 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
247 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
248 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
250 #define MC_SHARED_BLACKOUT_CNTL 0x20ac
252 #define MC_ARB_RAMCFG 0x2760
253 #define NOOFBANK_SHIFT 0
254 #define NOOFBANK_MASK 0x00000003
255 #define NOOFRANK_SHIFT 2
256 #define NOOFRANK_MASK 0x00000004
257 #define NOOFROWS_SHIFT 3
258 #define NOOFROWS_MASK 0x00000038
259 #define NOOFCOLS_SHIFT 6
260 #define NOOFCOLS_MASK 0x000000C0
261 #define CHANSIZE_SHIFT 8
262 #define CHANSIZE_MASK 0x00000100
263 #define CHANSIZE_OVERRIDE (1 << 11)
264 #define NOOFGROUPS_SHIFT 12
265 #define NOOFGROUPS_MASK 0x00001000
267 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
268 #define TRAIN_DONE_D0 (1 << 30)
269 #define TRAIN_DONE_D1 (1 << 31)
271 #define MC_SEQ_SUP_CNTL 0x28c8
272 #define RUN_MASK (1 << 0)
273 #define MC_SEQ_SUP_PGM 0x28cc
275 #define MC_IO_PAD_CNTL_D0 0x29d0
276 #define MEM_FALL_OUT_CMD (1 << 8)
278 #define MC_SEQ_MISC0 0x2a00
280 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44
281 #define MC_SEQ_IO_DEBUG_DATA 0x2a48
283 #define HDP_HOST_PATH_CNTL 0x2C00
284 #define HDP_NONSURFACE_BASE 0x2C04
285 #define HDP_NONSURFACE_INFO 0x2C08
286 #define HDP_NONSURFACE_SIZE 0x2C0C
288 #define HDP_ADDR_CONFIG 0x2F48
289 #define HDP_MISC_CNTL 0x2F4C
290 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
292 #define IH_RB_CNTL 0x3e00
293 # define IH_RB_ENABLE (1 << 0)
294 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
295 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
296 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
297 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
298 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
299 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
300 #define IH_RB_BASE 0x3e04
301 #define IH_RB_RPTR 0x3e08
302 #define IH_RB_WPTR 0x3e0c
303 # define RB_OVERFLOW (1 << 0)
304 # define WPTR_OFFSET_MASK 0x3fffc
305 #define IH_RB_WPTR_ADDR_HI 0x3e10
306 #define IH_RB_WPTR_ADDR_LO 0x3e14
307 #define IH_CNTL 0x3e18
308 # define ENABLE_INTR (1 << 0)
309 # define IH_MC_SWAP(x) ((x) << 1)
310 # define IH_MC_SWAP_NONE 0
311 # define IH_MC_SWAP_16BIT 1
312 # define IH_MC_SWAP_32BIT 2
313 # define IH_MC_SWAP_64BIT 3
314 # define RPTR_REARM (1 << 4)
315 # define MC_WRREQ_CREDIT(x) ((x) << 15)
316 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
317 # define MC_VMID(x) ((x) << 25)
319 #define CONFIG_MEMSIZE 0x5428
321 #define INTERRUPT_CNTL 0x5468
322 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
323 # define IH_DUMMY_RD_EN (1 << 1)
324 # define IH_REQ_NONSNOOP_EN (1 << 3)
325 # define GEN_IH_INT_EN (1 << 8)
326 #define INTERRUPT_CNTL2 0x546c
328 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
330 #define BIF_FB_EN 0x5490
331 #define FB_READ_EN (1 << 0)
332 #define FB_WRITE_EN (1 << 1)
334 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
336 #define DC_LB_MEMORY_SPLIT 0x6b0c
337 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
339 #define PRIORITY_A_CNT 0x6b18
340 #define PRIORITY_MARK_MASK 0x7fff
341 #define PRIORITY_OFF (1 << 16)
342 #define PRIORITY_ALWAYS_ON (1 << 20)
343 #define PRIORITY_B_CNT 0x6b1c
345 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
346 # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
347 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc
348 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
349 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
351 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
352 #define VLINE_STATUS 0x6bb8
353 # define VLINE_OCCURRED (1 << 0)
354 # define VLINE_ACK (1 << 4)
355 # define VLINE_STAT (1 << 12)
356 # define VLINE_INTERRUPT (1 << 16)
357 # define VLINE_INTERRUPT_TYPE (1 << 17)
358 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
359 #define VBLANK_STATUS 0x6bbc
360 # define VBLANK_OCCURRED (1 << 0)
361 # define VBLANK_ACK (1 << 4)
362 # define VBLANK_STAT (1 << 12)
363 # define VBLANK_INTERRUPT (1 << 16)
364 # define VBLANK_INTERRUPT_TYPE (1 << 17)
366 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
367 #define INT_MASK 0x6b40
368 # define VBLANK_INT_MASK (1 << 0)
369 # define VLINE_INT_MASK (1 << 4)
371 #define DISP_INTERRUPT_STATUS 0x60f4
372 # define LB_D1_VLINE_INTERRUPT (1 << 2)
373 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
374 # define DC_HPD1_INTERRUPT (1 << 17)
375 # define DC_HPD1_RX_INTERRUPT (1 << 18)
376 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
377 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
378 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
379 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
380 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
381 # define LB_D2_VLINE_INTERRUPT (1 << 2)
382 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
383 # define DC_HPD2_INTERRUPT (1 << 17)
384 # define DC_HPD2_RX_INTERRUPT (1 << 18)
385 # define DISP_TIMER_INTERRUPT (1 << 24)
386 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
387 # define LB_D3_VLINE_INTERRUPT (1 << 2)
388 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
389 # define DC_HPD3_INTERRUPT (1 << 17)
390 # define DC_HPD3_RX_INTERRUPT (1 << 18)
391 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
392 # define LB_D4_VLINE_INTERRUPT (1 << 2)
393 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
394 # define DC_HPD4_INTERRUPT (1 << 17)
395 # define DC_HPD4_RX_INTERRUPT (1 << 18)
396 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
397 # define LB_D5_VLINE_INTERRUPT (1 << 2)
398 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
399 # define DC_HPD5_INTERRUPT (1 << 17)
400 # define DC_HPD5_RX_INTERRUPT (1 << 18)
401 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
402 # define LB_D6_VLINE_INTERRUPT (1 << 2)
403 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
404 # define DC_HPD6_INTERRUPT (1 << 17)
405 # define DC_HPD6_RX_INTERRUPT (1 << 18)
407 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
408 #define GRPH_INT_STATUS 0x6858
409 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
410 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
411 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
412 #define GRPH_INT_CONTROL 0x685c
413 # define GRPH_PFLIP_INT_MASK (1 << 0)
414 # define GRPH_PFLIP_INT_TYPE (1 << 8)
416 #define DACA_AUTODETECT_INT_CONTROL 0x66c8
418 #define DC_HPD1_INT_STATUS 0x601c
419 #define DC_HPD2_INT_STATUS 0x6028
420 #define DC_HPD3_INT_STATUS 0x6034
421 #define DC_HPD4_INT_STATUS 0x6040
422 #define DC_HPD5_INT_STATUS 0x604c
423 #define DC_HPD6_INT_STATUS 0x6058
424 # define DC_HPDx_INT_STATUS (1 << 0)
425 # define DC_HPDx_SENSE (1 << 1)
426 # define DC_HPDx_RX_INT_STATUS (1 << 8)
428 #define DC_HPD1_INT_CONTROL 0x6020
429 #define DC_HPD2_INT_CONTROL 0x602c
430 #define DC_HPD3_INT_CONTROL 0x6038
431 #define DC_HPD4_INT_CONTROL 0x6044
432 #define DC_HPD5_INT_CONTROL 0x6050
433 #define DC_HPD6_INT_CONTROL 0x605c
434 # define DC_HPDx_INT_ACK (1 << 0)
435 # define DC_HPDx_INT_POLARITY (1 << 8)
436 # define DC_HPDx_INT_EN (1 << 16)
437 # define DC_HPDx_RX_INT_ACK (1 << 20)
438 # define DC_HPDx_RX_INT_EN (1 << 24)
440 #define DC_HPD1_CONTROL 0x6024
441 #define DC_HPD2_CONTROL 0x6030
442 #define DC_HPD3_CONTROL 0x603c
443 #define DC_HPD4_CONTROL 0x6048
444 #define DC_HPD5_CONTROL 0x6054
445 #define DC_HPD6_CONTROL 0x6060
446 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
447 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
448 # define DC_HPDx_EN (1 << 28)
450 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
451 #define CRTC_STATUS_FRAME_COUNT 0x6e98
453 #define GRBM_CNTL 0x8000
454 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
456 #define GRBM_STATUS2 0x8008
457 #define RLC_RQ_PENDING (1 << 0)
458 #define RLC_BUSY (1 << 8)
459 #define TC_BUSY (1 << 9)
461 #define GRBM_STATUS 0x8010
462 #define CMDFIFO_AVAIL_MASK 0x0000000F
463 #define RING2_RQ_PENDING (1 << 4)
464 #define SRBM_RQ_PENDING (1 << 5)
465 #define RING1_RQ_PENDING (1 << 6)
466 #define CF_RQ_PENDING (1 << 7)
467 #define PF_RQ_PENDING (1 << 8)
468 #define GDS_DMA_RQ_PENDING (1 << 9)
469 #define GRBM_EE_BUSY (1 << 10)
470 #define DB_CLEAN (1 << 12)
471 #define CB_CLEAN (1 << 13)
472 #define TA_BUSY (1 << 14)
473 #define GDS_BUSY (1 << 15)
474 #define VGT_BUSY (1 << 17)
475 #define IA_BUSY_NO_DMA (1 << 18)
476 #define IA_BUSY (1 << 19)
477 #define SX_BUSY (1 << 20)
478 #define SPI_BUSY (1 << 22)
479 #define BCI_BUSY (1 << 23)
480 #define SC_BUSY (1 << 24)
481 #define PA_BUSY (1 << 25)
482 #define DB_BUSY (1 << 26)
483 #define CP_COHERENCY_BUSY (1 << 28)
484 #define CP_BUSY (1 << 29)
485 #define CB_BUSY (1 << 30)
486 #define GUI_ACTIVE (1 << 31)
487 #define GRBM_STATUS_SE0 0x8014
488 #define GRBM_STATUS_SE1 0x8018
489 #define SE_DB_CLEAN (1 << 1)
490 #define SE_CB_CLEAN (1 << 2)
491 #define SE_BCI_BUSY (1 << 22)
492 #define SE_VGT_BUSY (1 << 23)
493 #define SE_PA_BUSY (1 << 24)
494 #define SE_TA_BUSY (1 << 25)
495 #define SE_SX_BUSY (1 << 26)
496 #define SE_SPI_BUSY (1 << 27)
497 #define SE_SC_BUSY (1 << 29)
498 #define SE_DB_BUSY (1 << 30)
499 #define SE_CB_BUSY (1 << 31)
501 #define GRBM_SOFT_RESET 0x8020
502 #define SOFT_RESET_CP (1 << 0)
503 #define SOFT_RESET_CB (1 << 1)
504 #define SOFT_RESET_RLC (1 << 2)
505 #define SOFT_RESET_DB (1 << 3)
506 #define SOFT_RESET_GDS (1 << 4)
507 #define SOFT_RESET_PA (1 << 5)
508 #define SOFT_RESET_SC (1 << 6)
509 #define SOFT_RESET_BCI (1 << 7)
510 #define SOFT_RESET_SPI (1 << 8)
511 #define SOFT_RESET_SX (1 << 10)
512 #define SOFT_RESET_TC (1 << 11)
513 #define SOFT_RESET_TA (1 << 12)
514 #define SOFT_RESET_VGT (1 << 14)
515 #define SOFT_RESET_IA (1 << 15)
517 #define GRBM_GFX_INDEX 0x802C
518 #define INSTANCE_INDEX(x) ((x) << 0)
519 #define SH_INDEX(x) ((x) << 8)
520 #define SE_INDEX(x) ((x) << 16)
521 #define SH_BROADCAST_WRITES (1 << 29)
522 #define INSTANCE_BROADCAST_WRITES (1 << 30)
523 #define SE_BROADCAST_WRITES (1 << 31)
525 #define GRBM_INT_CNTL 0x8060
526 # define RDERR_INT_ENABLE (1 << 0)
527 # define GUI_IDLE_INT_ENABLE (1 << 19)
529 #define CP_STRMOUT_CNTL 0x84FC
530 #define SCRATCH_REG0 0x8500
531 #define SCRATCH_REG1 0x8504
532 #define SCRATCH_REG2 0x8508
533 #define SCRATCH_REG3 0x850C
534 #define SCRATCH_REG4 0x8510
535 #define SCRATCH_REG5 0x8514
536 #define SCRATCH_REG6 0x8518
537 #define SCRATCH_REG7 0x851C
539 #define SCRATCH_UMSK 0x8540
540 #define SCRATCH_ADDR 0x8544
542 #define CP_SEM_WAIT_TIMER 0x85BC
544 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
546 #define CP_ME_CNTL 0x86D8
547 #define CP_CE_HALT (1 << 24)
548 #define CP_PFP_HALT (1 << 26)
549 #define CP_ME_HALT (1 << 28)
551 #define CP_COHER_CNTL2 0x85E8
553 #define CP_RB2_RPTR 0x86f8
554 #define CP_RB1_RPTR 0x86fc
555 #define CP_RB0_RPTR 0x8700
556 #define CP_RB_WPTR_DELAY 0x8704
558 #define CP_QUEUE_THRESHOLDS 0x8760
559 #define ROQ_IB1_START(x) ((x) << 0)
560 #define ROQ_IB2_START(x) ((x) << 8)
561 #define CP_MEQ_THRESHOLDS 0x8764
562 #define MEQ1_START(x) ((x) << 0)
563 #define MEQ2_START(x) ((x) << 8)
565 #define CP_PERFMON_CNTL 0x87FC
567 #define VGT_VTX_VECT_EJECT_REG 0x88B0
569 #define VGT_CACHE_INVALIDATION 0x88C4
570 #define CACHE_INVALIDATION(x) ((x) << 0)
574 #define AUTO_INVLD_EN(x) ((x) << 6)
578 #define ES_AND_GS_AUTO 3
579 #define VGT_ESGS_RING_SIZE 0x88C8
580 #define VGT_GSVS_RING_SIZE 0x88CC
582 #define VGT_GS_VERTEX_REUSE 0x88D4
584 #define VGT_PRIMITIVE_TYPE 0x8958
585 #define VGT_INDEX_TYPE 0x895C
587 #define VGT_NUM_INDICES 0x8970
588 #define VGT_NUM_INSTANCES 0x8974
590 #define VGT_TF_RING_SIZE 0x8988
592 #define VGT_HS_OFFCHIP_PARAM 0x89B0
594 #define VGT_TF_MEMORY_BASE 0x89B8
596 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
597 #define INACTIVE_CUS_MASK 0xFFFF0000
598 #define INACTIVE_CUS_SHIFT 16
599 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
601 #define PA_CL_ENHANCE 0x8A14
602 #define CLIP_VTX_REORDER_ENA (1 << 0)
603 #define NUM_CLIP_SEQ(x) ((x) << 1)
605 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
607 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
609 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
610 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
611 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
613 #define PA_SC_FIFO_SIZE 0x8BCC
614 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
615 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
616 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
617 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
619 #define PA_SC_ENHANCE 0x8BF0
621 #define SQ_CONFIG 0x8C00
623 #define SQC_CACHES 0x8C08
625 #define SX_DEBUG_1 0x9060
627 #define SPI_STATIC_THREAD_MGMT_1 0x90E0
628 #define SPI_STATIC_THREAD_MGMT_2 0x90E4
629 #define SPI_STATIC_THREAD_MGMT_3 0x90E8
630 #define SPI_PS_MAX_WAVE_ID 0x90EC
632 #define SPI_CONFIG_CNTL 0x9100
634 #define SPI_CONFIG_CNTL_1 0x913C
635 #define VTX_DONE_DELAY(x) ((x) << 0)
636 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
638 #define CGTS_TCC_DISABLE 0x9148
639 #define CGTS_USER_TCC_DISABLE 0x914C
640 #define TCC_DISABLE_MASK 0xFFFF0000
641 #define TCC_DISABLE_SHIFT 16
643 #define SPI_LB_CU_MASK 0x9354
645 #define TA_CNTL_AUX 0x9508
647 #define CC_RB_BACKEND_DISABLE 0x98F4
648 #define BACKEND_DISABLE(x) ((x) << 16)
649 #define GB_ADDR_CONFIG 0x98F8
650 #define NUM_PIPES(x) ((x) << 0)
651 #define NUM_PIPES_MASK 0x00000007
652 #define NUM_PIPES_SHIFT 0
653 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
654 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
655 #define PIPE_INTERLEAVE_SIZE_SHIFT 4
656 #define NUM_SHADER_ENGINES(x) ((x) << 12)
657 #define NUM_SHADER_ENGINES_MASK 0x00003000
658 #define NUM_SHADER_ENGINES_SHIFT 12
659 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
660 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
661 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16
662 #define NUM_GPUS(x) ((x) << 20)
663 #define NUM_GPUS_MASK 0x00700000
664 #define NUM_GPUS_SHIFT 20
665 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
666 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
667 #define MULTI_GPU_TILE_SIZE_SHIFT 24
668 #define ROW_SIZE(x) ((x) << 28)
669 #define ROW_SIZE_MASK 0x30000000
670 #define ROW_SIZE_SHIFT 28
672 #define GB_TILE_MODE0 0x9910
673 # define MICRO_TILE_MODE(x) ((x) << 0)
674 # define ADDR_SURF_DISPLAY_MICRO_TILING 0
675 # define ADDR_SURF_THIN_MICRO_TILING 1
676 # define ADDR_SURF_DEPTH_MICRO_TILING 2
677 # define ARRAY_MODE(x) ((x) << 2)
678 # define ARRAY_LINEAR_GENERAL 0
679 # define ARRAY_LINEAR_ALIGNED 1
680 # define ARRAY_1D_TILED_THIN1 2
681 # define ARRAY_2D_TILED_THIN1 4
682 # define PIPE_CONFIG(x) ((x) << 6)
683 # define ADDR_SURF_P2 0
684 # define ADDR_SURF_P4_8x16 4
685 # define ADDR_SURF_P4_16x16 5
686 # define ADDR_SURF_P4_16x32 6
687 # define ADDR_SURF_P4_32x32 7
688 # define ADDR_SURF_P8_16x16_8x16 8
689 # define ADDR_SURF_P8_16x32_8x16 9
690 # define ADDR_SURF_P8_32x32_8x16 10
691 # define ADDR_SURF_P8_16x32_16x16 11
692 # define ADDR_SURF_P8_32x32_16x16 12
693 # define ADDR_SURF_P8_32x32_16x32 13
694 # define ADDR_SURF_P8_32x64_32x32 14
695 # define TILE_SPLIT(x) ((x) << 11)
696 # define ADDR_SURF_TILE_SPLIT_64B 0
697 # define ADDR_SURF_TILE_SPLIT_128B 1
698 # define ADDR_SURF_TILE_SPLIT_256B 2
699 # define ADDR_SURF_TILE_SPLIT_512B 3
700 # define ADDR_SURF_TILE_SPLIT_1KB 4
701 # define ADDR_SURF_TILE_SPLIT_2KB 5
702 # define ADDR_SURF_TILE_SPLIT_4KB 6
703 # define BANK_WIDTH(x) ((x) << 14)
704 # define ADDR_SURF_BANK_WIDTH_1 0
705 # define ADDR_SURF_BANK_WIDTH_2 1
706 # define ADDR_SURF_BANK_WIDTH_4 2
707 # define ADDR_SURF_BANK_WIDTH_8 3
708 # define BANK_HEIGHT(x) ((x) << 16)
709 # define ADDR_SURF_BANK_HEIGHT_1 0
710 # define ADDR_SURF_BANK_HEIGHT_2 1
711 # define ADDR_SURF_BANK_HEIGHT_4 2
712 # define ADDR_SURF_BANK_HEIGHT_8 3
713 # define MACRO_TILE_ASPECT(x) ((x) << 18)
714 # define ADDR_SURF_MACRO_ASPECT_1 0
715 # define ADDR_SURF_MACRO_ASPECT_2 1
716 # define ADDR_SURF_MACRO_ASPECT_4 2
717 # define ADDR_SURF_MACRO_ASPECT_8 3
718 # define NUM_BANKS(x) ((x) << 20)
719 # define ADDR_SURF_2_BANK 0
720 # define ADDR_SURF_4_BANK 1
721 # define ADDR_SURF_8_BANK 2
722 # define ADDR_SURF_16_BANK 3
724 #define CB_PERFCOUNTER0_SELECT0 0x9a20
725 #define CB_PERFCOUNTER0_SELECT1 0x9a24
726 #define CB_PERFCOUNTER1_SELECT0 0x9a28
727 #define CB_PERFCOUNTER1_SELECT1 0x9a2c
728 #define CB_PERFCOUNTER2_SELECT0 0x9a30
729 #define CB_PERFCOUNTER2_SELECT1 0x9a34
730 #define CB_PERFCOUNTER3_SELECT0 0x9a38
731 #define CB_PERFCOUNTER3_SELECT1 0x9a3c
733 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
734 #define BACKEND_DISABLE_MASK 0x00FF0000
735 #define BACKEND_DISABLE_SHIFT 16
737 #define TCP_CHAN_STEER_LO 0xac0c
738 #define TCP_CHAN_STEER_HI 0xac10
740 #define CP_RB0_BASE 0xC100
741 #define CP_RB0_CNTL 0xC104
742 #define RB_BUFSZ(x) ((x) << 0)
743 #define RB_BLKSZ(x) ((x) << 8)
744 #define BUF_SWAP_32BIT (2 << 16)
745 #define RB_NO_UPDATE (1 << 27)
746 #define RB_RPTR_WR_ENA (1 << 31)
748 #define CP_RB0_RPTR_ADDR 0xC10C
749 #define CP_RB0_RPTR_ADDR_HI 0xC110
750 #define CP_RB0_WPTR 0xC114
752 #define CP_PFP_UCODE_ADDR 0xC150
753 #define CP_PFP_UCODE_DATA 0xC154
754 #define CP_ME_RAM_RADDR 0xC158
755 #define CP_ME_RAM_WADDR 0xC15C
756 #define CP_ME_RAM_DATA 0xC160
758 #define CP_CE_UCODE_ADDR 0xC168
759 #define CP_CE_UCODE_DATA 0xC16C
761 #define CP_RB1_BASE 0xC180
762 #define CP_RB1_CNTL 0xC184
763 #define CP_RB1_RPTR_ADDR 0xC188
764 #define CP_RB1_RPTR_ADDR_HI 0xC18C
765 #define CP_RB1_WPTR 0xC190
766 #define CP_RB2_BASE 0xC194
767 #define CP_RB2_CNTL 0xC198
768 #define CP_RB2_RPTR_ADDR 0xC19C
769 #define CP_RB2_RPTR_ADDR_HI 0xC1A0
770 #define CP_RB2_WPTR 0xC1A4
771 #define CP_INT_CNTL_RING0 0xC1A8
772 #define CP_INT_CNTL_RING1 0xC1AC
773 #define CP_INT_CNTL_RING2 0xC1B0
774 # define CNTX_BUSY_INT_ENABLE (1 << 19)
775 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
776 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21)
777 # define TIME_STAMP_INT_ENABLE (1 << 26)
778 # define CP_RINGID2_INT_ENABLE (1 << 29)
779 # define CP_RINGID1_INT_ENABLE (1 << 30)
780 # define CP_RINGID0_INT_ENABLE (1 << 31)
781 #define CP_INT_STATUS_RING0 0xC1B4
782 #define CP_INT_STATUS_RING1 0xC1B8
783 #define CP_INT_STATUS_RING2 0xC1BC
784 # define WAIT_MEM_SEM_INT_STAT (1 << 21)
785 # define TIME_STAMP_INT_STAT (1 << 26)
786 # define CP_RINGID2_INT_STAT (1 << 29)
787 # define CP_RINGID1_INT_STAT (1 << 30)
788 # define CP_RINGID0_INT_STAT (1 << 31)
790 #define CP_DEBUG 0xC1FC
792 #define RLC_CNTL 0xC300
793 # define RLC_ENABLE (1 << 0)
794 #define RLC_RL_BASE 0xC304
795 #define RLC_RL_SIZE 0xC308
796 #define RLC_LB_CNTL 0xC30C
797 # define LOAD_BALANCE_ENABLE (1 << 0)
798 #define RLC_SAVE_AND_RESTORE_BASE 0xC310
799 #define RLC_LB_CNTR_MAX 0xC314
800 #define RLC_LB_CNTR_INIT 0xC318
802 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320
804 #define RLC_UCODE_ADDR 0xC32C
805 #define RLC_UCODE_DATA 0xC330
807 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338
808 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C
809 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340
810 #define RLC_MC_CNTL 0xC344
811 #define RLC_UCODE_CNTL 0xC348
812 #define RLC_STAT 0xC34C
813 # define RLC_BUSY_STATUS (1 << 0)
814 # define GFX_POWER_STATUS (1 << 1)
815 # define GFX_CLOCK_STATUS (1 << 2)
816 # define GFX_LS_STATUS (1 << 3)
818 #define RLC_LB_INIT_CU_MASK 0xC41C
820 #define RLC_SERDES_MASTER_BUSY_0 0xC464
821 #define RLC_SERDES_MASTER_BUSY_1 0xC468
823 #define DB_DEPTH_INFO 0x2803c
825 #define PA_SC_RASTER_CONFIG 0x28350
826 # define RASTER_CONFIG_RB_MAP_0 0
827 # define RASTER_CONFIG_RB_MAP_1 1
828 # define RASTER_CONFIG_RB_MAP_2 2
829 # define RASTER_CONFIG_RB_MAP_3 3
831 #define VGT_EVENT_INITIATOR 0x28a90
832 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
833 # define SAMPLE_STREAMOUTSTATS2 (2 << 0)
834 # define SAMPLE_STREAMOUTSTATS3 (3 << 0)
835 # define CACHE_FLUSH_TS (4 << 0)
836 # define CACHE_FLUSH (6 << 0)
837 # define CS_PARTIAL_FLUSH (7 << 0)
838 # define VGT_STREAMOUT_RESET (10 << 0)
839 # define END_OF_PIPE_INCR_DE (11 << 0)
840 # define END_OF_PIPE_IB_END (12 << 0)
841 # define RST_PIX_CNT (13 << 0)
842 # define VS_PARTIAL_FLUSH (15 << 0)
843 # define PS_PARTIAL_FLUSH (16 << 0)
844 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
845 # define ZPASS_DONE (21 << 0)
846 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
847 # define PERFCOUNTER_START (23 << 0)
848 # define PERFCOUNTER_STOP (24 << 0)
849 # define PIPELINESTAT_START (25 << 0)
850 # define PIPELINESTAT_STOP (26 << 0)
851 # define PERFCOUNTER_SAMPLE (27 << 0)
852 # define SAMPLE_PIPELINESTAT (30 << 0)
853 # define SAMPLE_STREAMOUTSTATS (32 << 0)
854 # define RESET_VTX_CNT (33 << 0)
855 # define VGT_FLUSH (36 << 0)
856 # define BOTTOM_OF_PIPE_TS (40 << 0)
857 # define DB_CACHE_FLUSH_AND_INV (42 << 0)
858 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
859 # define FLUSH_AND_INV_DB_META (44 << 0)
860 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
861 # define FLUSH_AND_INV_CB_META (46 << 0)
862 # define CS_DONE (47 << 0)
863 # define PS_DONE (48 << 0)
864 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
865 # define THREAD_TRACE_START (51 << 0)
866 # define THREAD_TRACE_STOP (52 << 0)
867 # define THREAD_TRACE_FLUSH (54 << 0)
868 # define THREAD_TRACE_FINISH (55 << 0)
870 /* PIF PHY0 registers idx/data 0x8/0xc */
871 #define PB0_PIF_CNTL 0x10
872 # define LS2_EXIT_TIME(x) ((x) << 17)
873 # define LS2_EXIT_TIME_MASK (0x7 << 17)
874 # define LS2_EXIT_TIME_SHIFT 17
875 #define PB0_PIF_PAIRING 0x11
876 # define MULTI_PIF (1 << 25)
877 #define PB0_PIF_PWRDOWN_0 0x12
878 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
879 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
880 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
881 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
882 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
883 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
884 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
885 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
886 # define PLL_RAMP_UP_TIME_0_SHIFT 24
887 #define PB0_PIF_PWRDOWN_1 0x13
888 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
889 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
890 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
891 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
892 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
893 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
894 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
895 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
896 # define PLL_RAMP_UP_TIME_1_SHIFT 24
898 #define PB0_PIF_PWRDOWN_2 0x17
899 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7)
900 # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7)
901 # define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7
902 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10)
903 # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10)
904 # define PLL_POWER_STATE_IN_OFF_2_SHIFT 10
905 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24)
906 # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24)
907 # define PLL_RAMP_UP_TIME_2_SHIFT 24
908 #define PB0_PIF_PWRDOWN_3 0x18
909 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7)
910 # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7)
911 # define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7
912 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10)
913 # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10)
914 # define PLL_POWER_STATE_IN_OFF_3_SHIFT 10
915 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24)
916 # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24)
917 # define PLL_RAMP_UP_TIME_3_SHIFT 24
918 /* PIF PHY1 registers idx/data 0x10/0x14 */
919 #define PB1_PIF_CNTL 0x10
920 #define PB1_PIF_PAIRING 0x11
921 #define PB1_PIF_PWRDOWN_0 0x12
922 #define PB1_PIF_PWRDOWN_1 0x13
924 #define PB1_PIF_PWRDOWN_2 0x17
925 #define PB1_PIF_PWRDOWN_3 0x18
926 /* PCIE registers idx/data 0x30/0x34 */
927 #define PCIE_CNTL2 0x1c /* PCIE */
928 # define SLV_MEM_LS_EN (1 << 16)
929 # define MST_MEM_LS_EN (1 << 18)
930 # define REPLAY_MEM_LS_EN (1 << 19)
931 #define PCIE_LC_STATUS1 0x28 /* PCIE */
932 # define LC_REVERSE_RCVR (1 << 0)
933 # define LC_REVERSE_XMIT (1 << 1)
934 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
935 # define LC_OPERATING_LINK_WIDTH_SHIFT 2
936 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
937 # define LC_DETECTED_LINK_WIDTH_SHIFT 5
939 #define PCIE_P_CNTL 0x40 /* PCIE */
940 # define P_IGNORE_EDB_ERR (1 << 6)
942 /* PCIE PORT registers idx/data 0x38/0x3c */
943 #define PCIE_LC_CNTL 0xa0
944 # define LC_L0S_INACTIVITY(x) ((x) << 8)
945 # define LC_L0S_INACTIVITY_MASK (0xf << 8)
946 # define LC_L0S_INACTIVITY_SHIFT 8
947 # define LC_L1_INACTIVITY(x) ((x) << 12)
948 # define LC_L1_INACTIVITY_MASK (0xf << 12)
949 # define LC_L1_INACTIVITY_SHIFT 12
950 # define LC_PMI_TO_L1_DIS (1 << 16)
951 # define LC_ASPM_TO_L1_DIS (1 << 24)
952 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
953 # define LC_LINK_WIDTH_SHIFT 0
954 # define LC_LINK_WIDTH_MASK 0x7
955 # define LC_LINK_WIDTH_X0 0
956 # define LC_LINK_WIDTH_X1 1
957 # define LC_LINK_WIDTH_X2 2
958 # define LC_LINK_WIDTH_X4 3
959 # define LC_LINK_WIDTH_X8 4
960 # define LC_LINK_WIDTH_X16 6
961 # define LC_LINK_WIDTH_RD_SHIFT 4
962 # define LC_LINK_WIDTH_RD_MASK 0x70
963 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
964 # define LC_RECONFIG_NOW (1 << 8)
965 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
966 # define LC_RENEGOTIATE_EN (1 << 10)
967 # define LC_SHORT_RECONFIG_EN (1 << 11)
968 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
969 # define LC_UPCONFIGURE_DIS (1 << 13)
970 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
971 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
972 # define LC_DYN_LANES_PWR_STATE_SHIFT 21
973 #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */
974 # define LC_XMIT_N_FTS(x) ((x) << 0)
975 # define LC_XMIT_N_FTS_MASK (0xff << 0)
976 # define LC_XMIT_N_FTS_SHIFT 0
977 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
978 # define LC_N_FTS_MASK (0xff << 24)
979 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
980 # define LC_GEN2_EN_STRAP (1 << 0)
981 # define LC_GEN3_EN_STRAP (1 << 1)
982 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
983 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
984 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
985 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
986 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
987 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
988 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
989 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
990 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
991 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
992 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
993 # define LC_CURRENT_DATA_RATE_SHIFT 13
994 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
995 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
996 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
997 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
998 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
1000 #define PCIE_LC_CNTL2 0xb1
1001 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
1002 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
1004 #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */
1005 # define LC_GO_TO_RECOVERY (1 << 30)
1006 #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */
1007 # define LC_REDO_EQ (1 << 5)
1008 # define LC_SET_QUIESCE (1 << 13)
1013 #define UVD_UDEC_ADDR_CONFIG 0xEF4C
1014 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50
1015 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54
1016 #define UVD_RBC_RB_RPTR 0xF690
1017 #define UVD_RBC_RB_WPTR 0xF694
1022 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1023 (((reg) >> 2) & 0xFFFF) | \
1024 ((n) & 0x3FFF) << 16)
1025 #define CP_PACKET2 0x80000000
1026 #define PACKET2_PAD_SHIFT 0
1027 #define PACKET2_PAD_MASK (0x3fffffff << 0)
1029 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1031 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1032 (((op) & 0xFF) << 8) | \
1033 ((n) & 0x3FFF) << 16)
1035 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1037 /* Packet 3 types */
1038 #define PACKET3_NOP 0x10
1039 #define PACKET3_SET_BASE 0x11
1040 #define PACKET3_BASE_INDEX(x) ((x) << 0)
1041 #define GDS_PARTITION_BASE 2
1042 #define CE_PARTITION_BASE 3
1043 #define PACKET3_CLEAR_STATE 0x12
1044 #define PACKET3_INDEX_BUFFER_SIZE 0x13
1045 #define PACKET3_DISPATCH_DIRECT 0x15
1046 #define PACKET3_DISPATCH_INDIRECT 0x16
1047 #define PACKET3_ALLOC_GDS 0x1B
1048 #define PACKET3_WRITE_GDS_RAM 0x1C
1049 #define PACKET3_ATOMIC_GDS 0x1D
1050 #define PACKET3_ATOMIC 0x1E
1051 #define PACKET3_OCCLUSION_QUERY 0x1F
1052 #define PACKET3_SET_PREDICATION 0x20
1053 #define PACKET3_REG_RMW 0x21
1054 #define PACKET3_COND_EXEC 0x22
1055 #define PACKET3_PRED_EXEC 0x23
1056 #define PACKET3_DRAW_INDIRECT 0x24
1057 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
1058 #define PACKET3_INDEX_BASE 0x26
1059 #define PACKET3_DRAW_INDEX_2 0x27
1060 #define PACKET3_CONTEXT_CONTROL 0x28
1061 #define PACKET3_INDEX_TYPE 0x2A
1062 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1063 #define PACKET3_DRAW_INDEX_AUTO 0x2D
1064 #define PACKET3_DRAW_INDEX_IMMD 0x2E
1065 #define PACKET3_NUM_INSTANCES 0x2F
1066 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1067 #define PACKET3_INDIRECT_BUFFER_CONST 0x31
1068 #define PACKET3_INDIRECT_BUFFER 0x32
1069 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1070 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1071 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1072 #define PACKET3_WRITE_DATA 0x37
1073 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
1075 * 1 - memory (sync - via GRBM)
1079 * 5 - memory (async - direct)
1081 #define WR_ONE_ADDR (1 << 16)
1082 #define WR_CONFIRM (1 << 20)
1083 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1088 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1089 #define PACKET3_MEM_SEMAPHORE 0x39
1090 #define PACKET3_MPEG_INDEX 0x3A
1091 #define PACKET3_COPY_DW 0x3B
1092 #define PACKET3_WAIT_REG_MEM 0x3C
1093 #define PACKET3_MEM_WRITE 0x3D
1094 #define PACKET3_COPY_DATA 0x40
1095 #define PACKET3_CP_DMA 0x41
1097 * 2. SRC_ADDR_LO or DATA [31:0]
1098 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1100 * 4. DST_ADDR_LO [31:0]
1101 * 5. DST_ADDR_HI [7:0]
1102 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
1104 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1108 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
1112 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
1117 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1119 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
1120 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
1126 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1132 # define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1136 # define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1140 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1141 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1142 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
1143 #define PACKET3_PFP_SYNC_ME 0x42
1144 #define PACKET3_SURFACE_SYNC 0x43
1145 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1146 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1147 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1148 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1149 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1150 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1151 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1152 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1153 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1154 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1155 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1156 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1157 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1158 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1159 # define PACKET3_TC_ACTION_ENA (1 << 23)
1160 # define PACKET3_CB_ACTION_ENA (1 << 25)
1161 # define PACKET3_DB_ACTION_ENA (1 << 26)
1162 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1163 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1164 #define PACKET3_ME_INITIALIZE 0x44
1165 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1166 #define PACKET3_COND_WRITE 0x45
1167 #define PACKET3_EVENT_WRITE 0x46
1168 #define EVENT_TYPE(x) ((x) << 0)
1169 #define EVENT_INDEX(x) ((x) << 8)
1170 /* 0 - any non-TS event
1172 * 2 - SAMPLE_PIPELINESTAT
1173 * 3 - SAMPLE_STREAMOUTSTAT*
1174 * 4 - *S_PARTIAL_FLUSH
1177 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
1179 #define INV_L2 (1 << 20)
1180 /* INV TC L2 cache when EVENT_INDEX = 7 */
1181 #define PACKET3_EVENT_WRITE_EOP 0x47
1182 #define DATA_SEL(x) ((x) << 29)
1184 * 1 - send low 32bit data
1185 * 2 - send 64bit data
1186 * 3 - send 64bit counter value
1188 #define INT_SEL(x) ((x) << 24)
1190 * 1 - interrupt only (DATA_SEL = 0)
1191 * 2 - interrupt when data write is confirmed
1193 #define PACKET3_EVENT_WRITE_EOS 0x48
1194 #define PACKET3_PREAMBLE_CNTL 0x4A
1195 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1196 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1197 #define PACKET3_ONE_REG_WRITE 0x57
1198 #define PACKET3_LOAD_CONFIG_REG 0x5F
1199 #define PACKET3_LOAD_CONTEXT_REG 0x60
1200 #define PACKET3_LOAD_SH_REG 0x61
1201 #define PACKET3_SET_CONFIG_REG 0x68
1202 #define PACKET3_SET_CONFIG_REG_START 0x00008000
1203 #define PACKET3_SET_CONFIG_REG_END 0x0000b000
1204 #define PACKET3_SET_CONTEXT_REG 0x69
1205 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
1206 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
1207 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1208 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
1209 #define PACKET3_SET_SH_REG 0x76
1210 #define PACKET3_SET_SH_REG_START 0x0000b000
1211 #define PACKET3_SET_SH_REG_END 0x0000c000
1212 #define PACKET3_SET_SH_REG_OFFSET 0x77
1213 #define PACKET3_ME_WRITE 0x7A
1214 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
1215 #define PACKET3_SCRATCH_RAM_READ 0x7E
1216 #define PACKET3_CE_WRITE 0x7F
1217 #define PACKET3_LOAD_CONST_RAM 0x80
1218 #define PACKET3_WRITE_CONST_RAM 0x81
1219 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
1220 #define PACKET3_DUMP_CONST_RAM 0x83
1221 #define PACKET3_INCREMENT_CE_COUNTER 0x84
1222 #define PACKET3_INCREMENT_DE_COUNTER 0x85
1223 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
1224 #define PACKET3_WAIT_ON_DE_COUNTER 0x87
1225 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1226 #define PACKET3_SET_CE_DE_COUNTERS 0x89
1227 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
1228 #define PACKET3_SWITCH_BUFFER 0x8B
1230 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */
1231 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */
1232 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */
1234 #define DMA_RB_CNTL 0xd000
1235 # define DMA_RB_ENABLE (1 << 0)
1236 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
1237 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1238 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1239 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1240 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1241 #define DMA_RB_BASE 0xd004
1242 #define DMA_RB_RPTR 0xd008
1243 #define DMA_RB_WPTR 0xd00c
1245 #define DMA_RB_RPTR_ADDR_HI 0xd01c
1246 #define DMA_RB_RPTR_ADDR_LO 0xd020
1248 #define DMA_IB_CNTL 0xd024
1249 # define DMA_IB_ENABLE (1 << 0)
1250 # define DMA_IB_SWAP_ENABLE (1 << 4)
1251 #define DMA_IB_RPTR 0xd028
1252 #define DMA_CNTL 0xd02c
1253 # define TRAP_ENABLE (1 << 0)
1254 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1255 # define SEM_WAIT_INT_ENABLE (1 << 2)
1256 # define DATA_SWAP_ENABLE (1 << 3)
1257 # define FENCE_SWAP_ENABLE (1 << 4)
1258 # define CTXEMPTY_INT_ENABLE (1 << 28)
1259 #define DMA_STATUS_REG 0xd034
1260 # define DMA_IDLE (1 << 0)
1261 #define DMA_TILING_CONFIG 0xd0b8
1263 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \
1264 (((b) & 0x1) << 26) | \
1265 (((t) & 0x1) << 23) | \
1266 (((s) & 0x1) << 22) | \
1267 (((n) & 0xFFFFF) << 0))
1269 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \
1270 (((vmid) & 0xF) << 20) | \
1271 (((n) & 0xFFFFF) << 0))
1273 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
1276 (((n) & 0xFFFFF) << 0))
1278 /* async DMA Packet types */
1279 #define DMA_PACKET_WRITE 0x2
1280 #define DMA_PACKET_COPY 0x3
1281 #define DMA_PACKET_INDIRECT_BUFFER 0x4
1282 #define DMA_PACKET_SEMAPHORE 0x5
1283 #define DMA_PACKET_FENCE 0x6
1284 #define DMA_PACKET_TRAP 0x7
1285 #define DMA_PACKET_SRBM_WRITE 0x9
1286 #define DMA_PACKET_CONSTANT_FILL 0xd
1287 #define DMA_PACKET_NOP 0xf
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