drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  51 }
  52
  53 /**
  54  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  55  * @intel_dp: DP struct
  56  *
  57  * Returns true if the given DP struct corresponds to a PCH DP port attached
  58  * to an eDP panel, false otherwise.  Helpful for determining whether we
  59  * may need FDI resources for a given DP output or not.
  60  */
  61 static bool is_pch_edp(struct intel_dp *intel_dp)
  62 {
  63         return intel_dp->is_pch_edp;
  64 }
  65
  66 /**
  67  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  68  * @intel_dp: DP struct
  69  *
  70  * Returns true if the given DP struct corresponds to a CPU eDP port.
  71  */
  72 static bool is_cpu_edp(struct intel_dp *intel_dp)
  73 {
  74         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  75 }
  76
  77 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  78 {
  79         return container_of(intel_attached_encoder(connector),
  80                             struct intel_dp, base);
  81 }
  82
  83 /**
  84  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  85  * @encoder: DRM encoder
  86  *
  87  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  88  * by intel_display.c.
  89  */
  90 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  91 {
  92         struct intel_dp *intel_dp;
  93
  94         if (!encoder)
  95                 return false;
  96
  97         intel_dp = enc_to_intel_dp(encoder);
  98
  99         return is_pch_edp(intel_dp);
 100 }
 101
 102 static void intel_dp_link_down(struct intel_dp *intel_dp);
 103
 104 void
 105 intel_edp_link_config(struct intel_encoder *intel_encoder,
 106                        int *lane_num, int *link_bw)
 107 {
 108         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 109
 110         *lane_num = intel_dp->lane_count;
 111         *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 112 }
 113
 114 int
 115 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 116                        struct drm_display_mode *mode)
 117 {
 118         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 119         struct intel_connector *intel_connector = intel_dp->attached_connector;
 120
 121         if (intel_connector->panel.fixed_mode)
 122                 return intel_connector->panel.fixed_mode->clock;
 123         else
 124                 return mode->clock;
 125 }
 126
 127 static int
 128 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 129 {
 130         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 131
 132         switch (max_link_bw) {
 133         case DP_LINK_BW_1_62:
 134         case DP_LINK_BW_2_7:
 135                 break;
 136         default:
 137                 max_link_bw = DP_LINK_BW_1_62;
 138                 break;
 139         }
 140         return max_link_bw;
 141 }
 142
 143 static int
 144 intel_dp_link_clock(uint8_t link_bw)
 145 {
 146         if (link_bw == DP_LINK_BW_2_7)
 147                 return 270000;
 148         else
 149                 return 162000;
 150 }
 151
 152 /*
 153  * The units on the numbers in the next two are... bizarre.  Examples will
 154  * make it clearer; this one parallels an example in the eDP spec.
 155  *
 156  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 157  *
 158  *     270000 * 1 * 8 / 10 == 216000
 159  *
 160  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 161  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 162  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 163  * 119000.  At 18bpp that's 2142000 kilobits per second.
 164  *
 165  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 166  * get the result in decakilobits instead of kilobits.
 167  */
 168
 169 static int
 170 intel_dp_link_required(int pixel_clock, int bpp)
 171 {
 172         return (pixel_clock * bpp + 9) / 10;
 173 }
 174
 175 static int
 176 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 177 {
 178         return (max_link_clock * max_lanes * 8) / 10;
 179 }
 180
 181 static bool
 182 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 183                           struct drm_display_mode *mode,
 184                           bool adjust_mode)
 185 {
 186         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 187         int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 188         int max_rate, mode_rate;
 189
 190         mode_rate = intel_dp_link_required(mode->clock, 24);
 191         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 192
 193         if (mode_rate > max_rate) {
 194                 mode_rate = intel_dp_link_required(mode->clock, 18);
 195                 if (mode_rate > max_rate)
 196                         return false;
 197
 198                 if (adjust_mode)
 199                         mode->private_flags
 200                                 |= INTEL_MODE_DP_FORCE_6BPC;
 201
 202                 return true;
 203         }
 204
 205         return true;
 206 }
 207
 208 static int
 209 intel_dp_mode_valid(struct drm_connector *connector,
 210                     struct drm_display_mode *mode)
 211 {
 212         struct intel_dp *intel_dp = intel_attached_dp(connector);
 213         struct intel_connector *intel_connector = to_intel_connector(connector);
 214         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 215
 216         if (is_edp(intel_dp) && fixed_mode) {
 217                 if (mode->hdisplay > fixed_mode->hdisplay)
 218                         return MODE_PANEL;
 219
 220                 if (mode->vdisplay > fixed_mode->vdisplay)
 221                         return MODE_PANEL;
 222         }
 223
 224         if (!intel_dp_adjust_dithering(intel_dp, mode, false))
 225                 return MODE_CLOCK_HIGH;
 226
 227         if (mode->clock < 10000)
 228                 return MODE_CLOCK_LOW;
 229
 230         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 231                 return MODE_H_ILLEGAL;
 232
 233         return MODE_OK;
 234 }
 235
 236 static uint32_t
 237 pack_aux(uint8_t *src, int src_bytes)
 238 {
 239         int     i;
 240         uint32_t v = 0;
 241
 242         if (src_bytes > 4)
 243                 src_bytes = 4;
 244         for (i = 0; i < src_bytes; i++)
 245                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 246         return v;
 247 }
 248
 249 static void
 250 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 251 {
 252         int i;
 253         if (dst_bytes > 4)
 254                 dst_bytes = 4;
 255         for (i = 0; i < dst_bytes; i++)
 256                 dst[i] = src >> ((3-i) * 8);
 257 }
 258
 259 /* hrawclock is 1/4 the FSB frequency */
 260 static int
 261 intel_hrawclk(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         uint32_t clkcfg;
 265
 266         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 267         if (IS_VALLEYVIEW(dev))
 268                 return 200;
 269
 270         clkcfg = I915_READ(CLKCFG);
 271         switch (clkcfg & CLKCFG_FSB_MASK) {
 272         case CLKCFG_FSB_400:
 273                 return 100;
 274         case CLKCFG_FSB_533:
 275                 return 133;
 276         case CLKCFG_FSB_667:
 277                 return 166;
 278         case CLKCFG_FSB_800:
 279                 return 200;
 280         case CLKCFG_FSB_1067:
 281                 return 266;
 282         case CLKCFG_FSB_1333:
 283                 return 333;
 284         /* these two are just a guess; one of them might be right */
 285         case CLKCFG_FSB_1600:
 286         case CLKCFG_FSB_1600_ALT:
 287                 return 400;
 288         default:
 289                 return 133;
 290         }
 291 }
 292
 293 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 294 {
 295         struct drm_device *dev = intel_dp->base.base.dev;
 296         struct drm_i915_private *dev_priv = dev->dev_private;
 297
 298         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 299 }
 300
 301 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 302 {
 303         struct drm_device *dev = intel_dp->base.base.dev;
 304         struct drm_i915_private *dev_priv = dev->dev_private;
 305
 306         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 307 }
 308
 309 static void
 310 intel_dp_check_edp(struct intel_dp *intel_dp)
 311 {
 312         struct drm_device *dev = intel_dp->base.base.dev;
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314
 315         if (!is_edp(intel_dp))
 316                 return;
 317         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 318                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 319                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 320                               I915_READ(PCH_PP_STATUS),
 321                               I915_READ(PCH_PP_CONTROL));
 322         }
 323 }
 324
 325 static int
 326 intel_dp_aux_ch(struct intel_dp *intel_dp,
 327                 uint8_t *send, int send_bytes,
 328                 uint8_t *recv, int recv_size)
 329 {
 330         uint32_t output_reg = intel_dp->output_reg;
 331         struct drm_device *dev = intel_dp->base.base.dev;
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333         uint32_t ch_ctl = output_reg + 0x10;
 334         uint32_t ch_data = ch_ctl + 4;
 335         int i;
 336         int recv_bytes;
 337         uint32_t status;
 338         uint32_t aux_clock_divider;
 339         int try, precharge;
 340
 341         if (IS_HASWELL(dev)) {
 342                 switch (intel_dp->port) {
 343                 case PORT_A:
 344                         ch_ctl = DPA_AUX_CH_CTL;
 345                         ch_data = DPA_AUX_CH_DATA1;
 346                         break;
 347                 case PORT_B:
 348                         ch_ctl = PCH_DPB_AUX_CH_CTL;
 349                         ch_data = PCH_DPB_AUX_CH_DATA1;
 350                         break;
 351                 case PORT_C:
 352                         ch_ctl = PCH_DPC_AUX_CH_CTL;
 353                         ch_data = PCH_DPC_AUX_CH_DATA1;
 354                         break;
 355                 case PORT_D:
 356                         ch_ctl = PCH_DPD_AUX_CH_CTL;
 357                         ch_data = PCH_DPD_AUX_CH_DATA1;
 358                         break;
 359                 default:
 360                         BUG();
 361                 }
 362         }
 363
 364         intel_dp_check_edp(intel_dp);
 365         /* The clock divider is based off the hrawclk,
 366          * and would like to run at 2MHz. So, take the
 367          * hrawclk value and divide by 2 and use that
 368          *
 369          * Note that PCH attached eDP panels should use a 125MHz input
 370          * clock divider.
 371          */
 372         if (is_cpu_edp(intel_dp)) {
 373                 if (IS_VALLEYVIEW(dev))
 374                         aux_clock_divider = 100;
 375                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 376                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 377                 else
 378                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 379         } else if (HAS_PCH_SPLIT(dev))
 380                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 381         else
 382                 aux_clock_divider = intel_hrawclk(dev) / 2;
 383
 384         if (IS_GEN6(dev))
 385                 precharge = 3;
 386         else
 387                 precharge = 5;
 388
 389         /* Try to wait for any previous AUX channel activity */
 390         for (try = 0; try < 3; try++) {
 391                 status = I915_READ(ch_ctl);
 392                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 393                         break;
 394                 msleep(1);
 395         }
 396
 397         if (try == 3) {
 398                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 399                      I915_READ(ch_ctl));
 400                 return -EBUSY;
 401         }
 402
 403         /* Must try at least 3 times according to DP spec */
 404         for (try = 0; try < 5; try++) {
 405                 /* Load the send data into the aux channel data registers */
 406                 for (i = 0; i < send_bytes; i += 4)
 407                         I915_WRITE(ch_data + i,
 408                                    pack_aux(send + i, send_bytes - i));
 409
 410                 /* Send the command and wait for it to complete */
 411                 I915_WRITE(ch_ctl,
 412                            DP_AUX_CH_CTL_SEND_BUSY |
 413                            DP_AUX_CH_CTL_TIME_OUT_400us |
 414                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 415                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 416                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 417                            DP_AUX_CH_CTL_DONE |
 418                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 419                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 420                 for (;;) {
 421                         status = I915_READ(ch_ctl);
 422                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 423                                 break;
 424                         udelay(100);
 425                 }
 426
 427                 /* Clear done status and any errors */
 428                 I915_WRITE(ch_ctl,
 429                            status |
 430                            DP_AUX_CH_CTL_DONE |
 431                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 432                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 433
 434                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 435                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 436                         continue;
 437                 if (status & DP_AUX_CH_CTL_DONE)
 438                         break;
 439         }
 440
 441         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 442                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 443                 return -EBUSY;
 444         }
 445
 446         /* Check for timeout or receive error.
 447          * Timeouts occur when the sink is not connected
 448          */
 449         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 450                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 451                 return -EIO;
 452         }
 453
 454         /* Timeouts occur when the device isn't connected, so they're
 455          * "normal" -- don't fill the kernel log with these */
 456         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 457                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 458                 return -ETIMEDOUT;
 459         }
 460
 461         /* Unload any bytes sent back from the other side */
 462         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 463                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 464         if (recv_bytes > recv_size)
 465                 recv_bytes = recv_size;
 466
 467         for (i = 0; i < recv_bytes; i += 4)
 468                 unpack_aux(I915_READ(ch_data + i),
 469                            recv + i, recv_bytes - i);
 470
 471         return recv_bytes;
 472 }
 473
 474 /* Write data to the aux channel in native mode */
 475 static int
 476 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 477                           uint16_t address, uint8_t *send, int send_bytes)
 478 {
 479         int ret;
 480         uint8_t msg[20];
 481         int msg_bytes;
 482         uint8_t ack;
 483
 484         intel_dp_check_edp(intel_dp);
 485         if (send_bytes > 16)
 486                 return -1;
 487         msg[0] = AUX_NATIVE_WRITE << 4;
 488         msg[1] = address >> 8;
 489         msg[2] = address & 0xff;
 490         msg[3] = send_bytes - 1;
 491         memcpy(&msg[4], send, send_bytes);
 492         msg_bytes = send_bytes + 4;
 493         for (;;) {
 494                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 495                 if (ret < 0)
 496                         return ret;
 497                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 498                         break;
 499                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 500                         udelay(100);
 501                 else
 502                         return -EIO;
 503         }
 504         return send_bytes;
 505 }
 506
 507 /* Write a single byte to the aux channel in native mode */
 508 static int
 509 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 510                             uint16_t address, uint8_t byte)
 511 {
 512         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 513 }
 514
 515 /* read bytes from a native aux channel */
 516 static int
 517 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 518                          uint16_t address, uint8_t *recv, int recv_bytes)
 519 {
 520         uint8_t msg[4];
 521         int msg_bytes;
 522         uint8_t reply[20];
 523         int reply_bytes;
 524         uint8_t ack;
 525         int ret;
 526
 527         intel_dp_check_edp(intel_dp);
 528         msg[0] = AUX_NATIVE_READ << 4;
 529         msg[1] = address >> 8;
 530         msg[2] = address & 0xff;
 531         msg[3] = recv_bytes - 1;
 532
 533         msg_bytes = 4;
 534         reply_bytes = recv_bytes + 1;
 535
 536         for (;;) {
 537                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 538                                       reply, reply_bytes);
 539                 if (ret == 0)
 540                         return -EPROTO;
 541                 if (ret < 0)
 542                         return ret;
 543                 ack = reply[0];
 544                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 545                         memcpy(recv, reply + 1, ret - 1);
 546                         return ret - 1;
 547                 }
 548                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 549                         udelay(100);
 550                 else
 551                         return -EIO;
 552         }
 553 }
 554
 555 static int
 556 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 557                     uint8_t write_byte, uint8_t *read_byte)
 558 {
 559         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 560         struct intel_dp *intel_dp = container_of(adapter,
 561                                                 struct intel_dp,
 562                                                 adapter);
 563         uint16_t address = algo_data->address;
 564         uint8_t msg[5];
 565         uint8_t reply[2];
 566         unsigned retry;
 567         int msg_bytes;
 568         int reply_bytes;
 569         int ret;
 570
 571         intel_dp_check_edp(intel_dp);
 572         /* Set up the command byte */
 573         if (mode & MODE_I2C_READ)
 574                 msg[0] = AUX_I2C_READ << 4;
 575         else
 576                 msg[0] = AUX_I2C_WRITE << 4;
 577
 578         if (!(mode & MODE_I2C_STOP))
 579                 msg[0] |= AUX_I2C_MOT << 4;
 580
 581         msg[1] = address >> 8;
 582         msg[2] = address;
 583
 584         switch (mode) {
 585         case MODE_I2C_WRITE:
 586                 msg[3] = 0;
 587                 msg[4] = write_byte;
 588                 msg_bytes = 5;
 589                 reply_bytes = 1;
 590                 break;
 591         case MODE_I2C_READ:
 592                 msg[3] = 0;
 593                 msg_bytes = 4;
 594                 reply_bytes = 2;
 595                 break;
 596         default:
 597                 msg_bytes = 3;
 598                 reply_bytes = 1;
 599                 break;
 600         }
 601
 602         for (retry = 0; retry < 5; retry++) {
 603                 ret = intel_dp_aux_ch(intel_dp,
 604                                       msg, msg_bytes,
 605                                       reply, reply_bytes);
 606                 if (ret < 0) {
 607                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 608                         return ret;
 609                 }
 610
 611                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 612                 case AUX_NATIVE_REPLY_ACK:
 613                         /* I2C-over-AUX Reply field is only valid
 614                          * when paired with AUX ACK.
 615                          */
 616                         break;
 617                 case AUX_NATIVE_REPLY_NACK:
 618                         DRM_DEBUG_KMS("aux_ch native nack\n");
 619                         return -EREMOTEIO;
 620                 case AUX_NATIVE_REPLY_DEFER:
 621                         udelay(100);
 622                         continue;
 623                 default:
 624                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 625                                   reply[0]);
 626                         return -EREMOTEIO;
 627                 }
 628
 629                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 630                 case AUX_I2C_REPLY_ACK:
 631                         if (mode == MODE_I2C_READ) {
 632                                 *read_byte = reply[1];
 633                         }
 634                         return reply_bytes - 1;
 635                 case AUX_I2C_REPLY_NACK:
 636                         DRM_DEBUG_KMS("aux_i2c nack\n");
 637                         return -EREMOTEIO;
 638                 case AUX_I2C_REPLY_DEFER:
 639                         DRM_DEBUG_KMS("aux_i2c defer\n");
 640                         udelay(100);
 641                         break;
 642                 default:
 643                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 644                         return -EREMOTEIO;
 645                 }
 646         }
 647
 648         DRM_ERROR("too many retries, giving up\n");
 649         return -EREMOTEIO;
 650 }
 651
 652 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 653 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 654
 655 static int
 656 intel_dp_i2c_init(struct intel_dp *intel_dp,
 657                   struct intel_connector *intel_connector, const char *name)
 658 {
 659         int     ret;
 660
 661         DRM_DEBUG_KMS("i2c_init %s\n", name);
 662         intel_dp->algo.running = false;
 663         intel_dp->algo.address = 0;
 664         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 665
 666         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 667         intel_dp->adapter.owner = THIS_MODULE;
 668         intel_dp->adapter.class = I2C_CLASS_DDC;
 669         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 670         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 671         intel_dp->adapter.algo_data = &intel_dp->algo;
 672         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 673
 674         ironlake_edp_panel_vdd_on(intel_dp);
 675         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 676         ironlake_edp_panel_vdd_off(intel_dp, false);
 677         return ret;
 678 }
 679
 680 static bool
 681 intel_dp_mode_fixup(struct drm_encoder *encoder,
 682                     const struct drm_display_mode *mode,
 683                     struct drm_display_mode *adjusted_mode)
 684 {
 685         struct drm_device *dev = encoder->dev;
 686         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 687         struct intel_connector *intel_connector = intel_dp->attached_connector;
 688         int lane_count, clock;
 689         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 690         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 691         int bpp, mode_rate;
 692         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 693
 694         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 695                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 696                                        adjusted_mode);
 697                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 698                                         mode, adjusted_mode);
 699         }
 700
 701         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 702                 return false;
 703
 704         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 705                       "max bw %02x pixel clock %iKHz\n",
 706                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 707
 708         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
 709                 return false;
 710
 711         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 712         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 713
 714         for (clock = 0; clock <= max_clock; clock++) {
 715                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 716                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 717
 718                         if (mode_rate <= link_avail) {
 719                                 intel_dp->link_bw = bws[clock];
 720                                 intel_dp->lane_count = lane_count;
 721                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 722                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 723                                                 "count %d clock %d bpp %d\n",
 724                                        intel_dp->link_bw, intel_dp->lane_count,
 725                                        adjusted_mode->clock, bpp);
 726                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 727                                               mode_rate, link_avail);
 728                                 return true;
 729                         }
 730                 }
 731         }
 732
 733         return false;
 734 }
 735
 736 struct intel_dp_m_n {
 737         uint32_t        tu;
 738         uint32_t        gmch_m;
 739         uint32_t        gmch_n;
 740         uint32_t        link_m;
 741         uint32_t        link_n;
 742 };
 743
 744 static void
 745 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 746 {
 747         while (*num > 0xffffff || *den > 0xffffff) {
 748                 *num >>= 1;
 749                 *den >>= 1;
 750         }
 751 }
 752
 753 static void
 754 intel_dp_compute_m_n(int bpp,
 755                      int nlanes,
 756                      int pixel_clock,
 757                      int link_clock,
 758                      struct intel_dp_m_n *m_n)
 759 {
 760         m_n->tu = 64;
 761         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 762         m_n->gmch_n = link_clock * nlanes;
 763         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 764         m_n->link_m = pixel_clock;
 765         m_n->link_n = link_clock;
 766         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 767 }
 768
 769 void
 770 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 771                  struct drm_display_mode *adjusted_mode)
 772 {
 773         struct drm_device *dev = crtc->dev;
 774         struct intel_encoder *encoder;
 775         struct drm_i915_private *dev_priv = dev->dev_private;
 776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 777         int lane_count = 4;
 778         struct intel_dp_m_n m_n;
 779         int pipe = intel_crtc->pipe;
 780
 781         /*
 782          * Find the lane count in the intel_encoder private
 783          */
 784         for_each_encoder_on_crtc(dev, crtc, encoder) {
 785                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 786
 787                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 788                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 789                 {
 790                         lane_count = intel_dp->lane_count;
 791                         break;
 792                 }
 793         }
 794
 795         /*
 796          * Compute the GMCH and Link ratios. The '3' here is
 797          * the number of bytes_per_pixel post-LUT, which we always
 798          * set up for 8-bits of R/G/B, or 3 bytes total.
 799          */
 800         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 801                              mode->clock, adjusted_mode->clock, &m_n);
 802
 803         if (IS_HASWELL(dev)) {
 804                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 805                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 806                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 807                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 808         } else if (HAS_PCH_SPLIT(dev)) {
 809                 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 810                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 811                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 812                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 813         } else if (IS_VALLEYVIEW(dev)) {
 814                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 815                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 816                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 817                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 818         } else {
 819                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 820                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 821                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 822                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 823                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 824         }
 825 }
 826
 827 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 828 {
 829         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 830         intel_dp->link_configuration[0] = intel_dp->link_bw;
 831         intel_dp->link_configuration[1] = intel_dp->lane_count;
 832         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 833         /*
 834          * Check for DPCD version > 1.1 and enhanced framing support
 835          */
 836         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 837             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 838                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 839         }
 840 }
 841
 842 static void
 843 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 844                   struct drm_display_mode *adjusted_mode)
 845 {
 846         struct drm_device *dev = encoder->dev;
 847         struct drm_i915_private *dev_priv = dev->dev_private;
 848         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 849         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 851
 852         /*
 853          * There are four kinds of DP registers:
 854          *
 855          *      IBX PCH
 856          *      SNB CPU
 857          *      IVB CPU
 858          *      CPT PCH
 859          *
 860          * IBX PCH and CPU are the same for almost everything,
 861          * except that the CPU DP PLL is configured in this
 862          * register
 863          *
 864          * CPT PCH is quite different, having many bits moved
 865          * to the TRANS_DP_CTL register instead. That
 866          * configuration happens (oddly) in ironlake_pch_enable
 867          */
 868
 869         /* Preserve the BIOS-computed detected bit. This is
 870          * supposed to be read-only.
 871          */
 872         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 873
 874         /* Handle DP bits in common between all three register formats */
 875         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 876
 877         switch (intel_dp->lane_count) {
 878         case 1:
 879                 intel_dp->DP |= DP_PORT_WIDTH_1;
 880                 break;
 881         case 2:
 882                 intel_dp->DP |= DP_PORT_WIDTH_2;
 883                 break;
 884         case 4:
 885                 intel_dp->DP |= DP_PORT_WIDTH_4;
 886                 break;
 887         }
 888         if (intel_dp->has_audio) {
 889                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 890                                  pipe_name(intel_crtc->pipe));
 891                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 892                 intel_write_eld(encoder, adjusted_mode);
 893         }
 894
 895         intel_dp_init_link_config(intel_dp);
 896
 897         /* Split out the IBX/CPU vs CPT settings */
 898
 899         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 900                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 901                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 902                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 903                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 904                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 905
 906                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 907                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 908
 909                 intel_dp->DP |= intel_crtc->pipe << 29;
 910
 911                 /* don't miss out required setting for eDP */
 912                 if (adjusted_mode->clock < 200000)
 913                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 914                 else
 915                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 916         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 917                 intel_dp->DP |= intel_dp->color_range;
 918
 919                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 920                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 921                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 922                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 923                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 924
 925                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 926                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 927
 928                 if (intel_crtc->pipe == 1)
 929                         intel_dp->DP |= DP_PIPEB_SELECT;
 930
 931                 if (is_cpu_edp(intel_dp)) {
 932                         /* don't miss out required setting for eDP */
 933                         if (adjusted_mode->clock < 200000)
 934                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 935                         else
 936                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 937                 }
 938         } else {
 939                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 940         }
 941 }
 942
 943 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 944 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 945
 946 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 947 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 948
 949 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 950 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 951
 952 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 953                                        u32 mask,
 954                                        u32 value)
 955 {
 956         struct drm_device *dev = intel_dp->base.base.dev;
 957         struct drm_i915_private *dev_priv = dev->dev_private;
 958
 959         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 960                       mask, value,
 961                       I915_READ(PCH_PP_STATUS),
 962                       I915_READ(PCH_PP_CONTROL));
 963
 964         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 965                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 966                           I915_READ(PCH_PP_STATUS),
 967                           I915_READ(PCH_PP_CONTROL));
 968         }
 969 }
 970
 971 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 972 {
 973         DRM_DEBUG_KMS("Wait for panel power on\n");
 974         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 975 }
 976
 977 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 978 {
 979         DRM_DEBUG_KMS("Wait for panel power off time\n");
 980         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 981 }
 982
 983 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 984 {
 985         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 986         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 987 }
 988
 989
 990 /* Read the current pp_control value, unlocking the register if it
 991  * is locked
 992  */
 993
 994 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 995 {
 996         u32     control = I915_READ(PCH_PP_CONTROL);
 997
 998         control &= ~PANEL_UNLOCK_MASK;
 999         control |= PANEL_UNLOCK_REGS;
1000         return control;
1001 }
1002
1003 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1004 {
1005         struct drm_device *dev = intel_dp->base.base.dev;
1006         struct drm_i915_private *dev_priv = dev->dev_private;
1007         u32 pp;
1008
1009         if (!is_edp(intel_dp))
1010                 return;
1011         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1012
1013         WARN(intel_dp->want_panel_vdd,
1014              "eDP VDD already requested on\n");
1015
1016         intel_dp->want_panel_vdd = true;
1017
1018         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1019                 DRM_DEBUG_KMS("eDP VDD already on\n");
1020                 return;
1021         }
1022
1023         if (!ironlake_edp_have_panel_power(intel_dp))
1024                 ironlake_wait_panel_power_cycle(intel_dp);
1025
1026         pp = ironlake_get_pp_control(dev_priv);
1027         pp |= EDP_FORCE_VDD;
1028         I915_WRITE(PCH_PP_CONTROL, pp);
1029         POSTING_READ(PCH_PP_CONTROL);
1030         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1031                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1032
1033         /*
1034          * If the panel wasn't on, delay before accessing aux channel
1035          */
1036         if (!ironlake_edp_have_panel_power(intel_dp)) {
1037                 DRM_DEBUG_KMS("eDP was not running\n");
1038                 msleep(intel_dp->panel_power_up_delay);
1039         }
1040 }
1041
1042 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1043 {
1044         struct drm_device *dev = intel_dp->base.base.dev;
1045         struct drm_i915_private *dev_priv = dev->dev_private;
1046         u32 pp;
1047
1048         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1049                 pp = ironlake_get_pp_control(dev_priv);
1050                 pp &= ~EDP_FORCE_VDD;
1051                 I915_WRITE(PCH_PP_CONTROL, pp);
1052                 POSTING_READ(PCH_PP_CONTROL);
1053
1054                 /* Make sure sequencer is idle before allowing subsequent activity */
1055                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1056                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1057
1058                 msleep(intel_dp->panel_power_down_delay);
1059         }
1060 }
1061
1062 static void ironlake_panel_vdd_work(struct work_struct *__work)
1063 {
1064         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1065                                                  struct intel_dp, panel_vdd_work);
1066         struct drm_device *dev = intel_dp->base.base.dev;
1067
1068         mutex_lock(&dev->mode_config.mutex);
1069         ironlake_panel_vdd_off_sync(intel_dp);
1070         mutex_unlock(&dev->mode_config.mutex);
1071 }
1072
1073 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1074 {
1075         if (!is_edp(intel_dp))
1076                 return;
1077
1078         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1079         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1080
1081         intel_dp->want_panel_vdd = false;
1082
1083         if (sync) {
1084                 ironlake_panel_vdd_off_sync(intel_dp);
1085         } else {
1086                 /*
1087                  * Queue the timer to fire a long
1088                  * time from now (relative to the power down delay)
1089                  * to keep the panel power up across a sequence of operations
1090                  */
1091                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1092                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1093         }
1094 }
1095
1096 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1097 {
1098         struct drm_device *dev = intel_dp->base.base.dev;
1099         struct drm_i915_private *dev_priv = dev->dev_private;
1100         u32 pp;
1101
1102         if (!is_edp(intel_dp))
1103                 return;
1104
1105         DRM_DEBUG_KMS("Turn eDP power on\n");
1106
1107         if (ironlake_edp_have_panel_power(intel_dp)) {
1108                 DRM_DEBUG_KMS("eDP power already on\n");
1109                 return;
1110         }
1111
1112         ironlake_wait_panel_power_cycle(intel_dp);
1113
1114         pp = ironlake_get_pp_control(dev_priv);
1115         if (IS_GEN5(dev)) {
1116                 /* ILK workaround: disable reset around power sequence */
1117                 pp &= ~PANEL_POWER_RESET;
1118                 I915_WRITE(PCH_PP_CONTROL, pp);
1119                 POSTING_READ(PCH_PP_CONTROL);
1120         }
1121
1122         pp |= POWER_TARGET_ON;
1123         if (!IS_GEN5(dev))
1124                 pp |= PANEL_POWER_RESET;
1125
1126         I915_WRITE(PCH_PP_CONTROL, pp);
1127         POSTING_READ(PCH_PP_CONTROL);
1128
1129         ironlake_wait_panel_on(intel_dp);
1130
1131         if (IS_GEN5(dev)) {
1132                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1133                 I915_WRITE(PCH_PP_CONTROL, pp);
1134                 POSTING_READ(PCH_PP_CONTROL);
1135         }
1136 }
1137
1138 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1139 {
1140         struct drm_device *dev = intel_dp->base.base.dev;
1141         struct drm_i915_private *dev_priv = dev->dev_private;
1142         u32 pp;
1143
1144         if (!is_edp(intel_dp))
1145                 return;
1146
1147         DRM_DEBUG_KMS("Turn eDP power off\n");
1148
1149         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1150
1151         pp = ironlake_get_pp_control(dev_priv);
1152         /* We need to switch off panel power _and_ force vdd, for otherwise some
1153          * panels get very unhappy and cease to work. */
1154         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1155         I915_WRITE(PCH_PP_CONTROL, pp);
1156         POSTING_READ(PCH_PP_CONTROL);
1157
1158         intel_dp->want_panel_vdd = false;
1159
1160         ironlake_wait_panel_off(intel_dp);
1161 }
1162
1163 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1164 {
1165         struct drm_device *dev = intel_dp->base.base.dev;
1166         struct drm_i915_private *dev_priv = dev->dev_private;
1167         int pipe = to_intel_crtc(intel_dp->base.base.crtc)->pipe;
1168         u32 pp;
1169
1170         if (!is_edp(intel_dp))
1171                 return;
1172
1173         DRM_DEBUG_KMS("\n");
1174         /*
1175          * If we enable the backlight right away following a panel power
1176          * on, we may see slight flicker as the panel syncs with the eDP
1177          * link.  So delay a bit to make sure the image is solid before
1178          * allowing it to appear.
1179          */
1180         msleep(intel_dp->backlight_on_delay);
1181         pp = ironlake_get_pp_control(dev_priv);
1182         pp |= EDP_BLC_ENABLE;
1183         I915_WRITE(PCH_PP_CONTROL, pp);
1184         POSTING_READ(PCH_PP_CONTROL);
1185
1186         intel_panel_enable_backlight(dev, pipe);
1187 }
1188
1189 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1190 {
1191         struct drm_device *dev = intel_dp->base.base.dev;
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193         u32 pp;
1194
1195         if (!is_edp(intel_dp))
1196                 return;
1197
1198         intel_panel_disable_backlight(dev);
1199
1200         DRM_DEBUG_KMS("\n");
1201         pp = ironlake_get_pp_control(dev_priv);
1202         pp &= ~EDP_BLC_ENABLE;
1203         I915_WRITE(PCH_PP_CONTROL, pp);
1204         POSTING_READ(PCH_PP_CONTROL);
1205         msleep(intel_dp->backlight_off_delay);
1206 }
1207
1208 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1209 {
1210         struct drm_device *dev = intel_dp->base.base.dev;
1211         struct drm_crtc *crtc = intel_dp->base.base.crtc;
1212         struct drm_i915_private *dev_priv = dev->dev_private;
1213         u32 dpa_ctl;
1214
1215         assert_pipe_disabled(dev_priv,
1216                              to_intel_crtc(crtc)->pipe);
1217
1218         DRM_DEBUG_KMS("\n");
1219         dpa_ctl = I915_READ(DP_A);
1220         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1221         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1222
1223         /* We don't adjust intel_dp->DP while tearing down the link, to
1224          * facilitate link retraining (e.g. after hotplug). Hence clear all
1225          * enable bits here to ensure that we don't enable too much. */
1226         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1227         intel_dp->DP |= DP_PLL_ENABLE;
1228         I915_WRITE(DP_A, intel_dp->DP);
1229         POSTING_READ(DP_A);
1230         udelay(200);
1231 }
1232
1233 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1234 {
1235         struct drm_device *dev = intel_dp->base.base.dev;
1236         struct drm_crtc *crtc = intel_dp->base.base.crtc;
1237         struct drm_i915_private *dev_priv = dev->dev_private;
1238         u32 dpa_ctl;
1239
1240         assert_pipe_disabled(dev_priv,
1241                              to_intel_crtc(crtc)->pipe);
1242
1243         dpa_ctl = I915_READ(DP_A);
1244         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1245              "dp pll off, should be on\n");
1246         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1247
1248         /* We can't rely on the value tracked for the DP register in
1249          * intel_dp->DP because link_down must not change that (otherwise link
1250          * re-training will fail. */
1251         dpa_ctl &= ~DP_PLL_ENABLE;
1252         I915_WRITE(DP_A, dpa_ctl);
1253         POSTING_READ(DP_A);
1254         udelay(200);
1255 }
1256
1257 /* If the sink supports it, try to set the power state appropriately */
1258 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1259 {
1260         int ret, i;
1261
1262         /* Should have a valid DPCD by this point */
1263         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1264                 return;
1265
1266         if (mode != DRM_MODE_DPMS_ON) {
1267                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1268                                                   DP_SET_POWER_D3);
1269                 if (ret != 1)
1270                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1271         } else {
1272                 /*
1273                  * When turning on, we need to retry for 1ms to give the sink
1274                  * time to wake up.
1275                  */
1276                 for (i = 0; i < 3; i++) {
1277                         ret = intel_dp_aux_native_write_1(intel_dp,
1278                                                           DP_SET_POWER,
1279                                                           DP_SET_POWER_D0);
1280                         if (ret == 1)
1281                                 break;
1282                         msleep(1);
1283                 }
1284         }
1285 }
1286
1287 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1288                                   enum pipe *pipe)
1289 {
1290         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1291         struct drm_device *dev = encoder->base.dev;
1292         struct drm_i915_private *dev_priv = dev->dev_private;
1293         u32 tmp = I915_READ(intel_dp->output_reg);
1294
1295         if (!(tmp & DP_PORT_EN))
1296                 return false;
1297
1298         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1299                 *pipe = PORT_TO_PIPE_CPT(tmp);
1300         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1301                 *pipe = PORT_TO_PIPE(tmp);
1302         } else {
1303                 u32 trans_sel;
1304                 u32 trans_dp;
1305                 int i;
1306
1307                 switch (intel_dp->output_reg) {
1308                 case PCH_DP_B:
1309                         trans_sel = TRANS_DP_PORT_SEL_B;
1310                         break;
1311                 case PCH_DP_C:
1312                         trans_sel = TRANS_DP_PORT_SEL_C;
1313                         break;
1314                 case PCH_DP_D:
1315                         trans_sel = TRANS_DP_PORT_SEL_D;
1316                         break;
1317                 default:
1318                         return true;
1319                 }
1320
1321                 for_each_pipe(i) {
1322                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1323                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1324                                 *pipe = i;
1325                                 return true;
1326                         }
1327                 }
1328         }
1329
1330         DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1331
1332         return true;
1333 }
1334
1335 static void intel_disable_dp(struct intel_encoder *encoder)
1336 {
1337         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1338
1339         /* Make sure the panel is off before trying to change the mode. But also
1340          * ensure that we have vdd while we switch off the panel. */
1341         ironlake_edp_panel_vdd_on(intel_dp);
1342         ironlake_edp_backlight_off(intel_dp);
1343         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1344         ironlake_edp_panel_off(intel_dp);
1345
1346         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1347         if (!is_cpu_edp(intel_dp))
1348                 intel_dp_link_down(intel_dp);
1349 }
1350
1351 static void intel_post_disable_dp(struct intel_encoder *encoder)
1352 {
1353         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1354
1355         if (is_cpu_edp(intel_dp)) {
1356                 intel_dp_link_down(intel_dp);
1357                 ironlake_edp_pll_off(intel_dp);
1358         }
1359 }
1360
1361 static void intel_enable_dp(struct intel_encoder *encoder)
1362 {
1363         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1364         struct drm_device *dev = encoder->base.dev;
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1367
1368         if (WARN_ON(dp_reg & DP_PORT_EN))
1369                 return;
1370
1371         ironlake_edp_panel_vdd_on(intel_dp);
1372         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1373         intel_dp_start_link_train(intel_dp);
1374         ironlake_edp_panel_on(intel_dp);
1375         ironlake_edp_panel_vdd_off(intel_dp, true);
1376         intel_dp_complete_link_train(intel_dp);
1377         ironlake_edp_backlight_on(intel_dp);
1378 }
1379
1380 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1381 {
1382         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1383
1384         if (is_cpu_edp(intel_dp))
1385                 ironlake_edp_pll_on(intel_dp);
1386 }
1387
1388 /*
1389  * Native read with retry for link status and receiver capability reads for
1390  * cases where the sink may still be asleep.
1391  */
1392 static bool
1393 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1394                                uint8_t *recv, int recv_bytes)
1395 {
1396         int ret, i;
1397
1398         /*
1399          * Sinks are *supposed* to come up within 1ms from an off state,
1400          * but we're also supposed to retry 3 times per the spec.
1401          */
1402         for (i = 0; i < 3; i++) {
1403                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1404                                                recv_bytes);
1405                 if (ret == recv_bytes)
1406                         return true;
1407                 msleep(1);
1408         }
1409
1410         return false;
1411 }
1412
1413 /*
1414  * Fetch AUX CH registers 0x202 - 0x207 which contain
1415  * link status information
1416  */
1417 static bool
1418 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1419 {
1420         return intel_dp_aux_native_read_retry(intel_dp,
1421                                               DP_LANE0_1_STATUS,
1422                                               link_status,
1423                                               DP_LINK_STATUS_SIZE);
1424 }
1425
1426 #if 0
1427 static char     *voltage_names[] = {
1428         "0.4V", "0.6V", "0.8V", "1.2V"
1429 };
1430 static char     *pre_emph_names[] = {
1431         "0dB", "3.5dB", "6dB", "9.5dB"
1432 };
1433 static char     *link_train_names[] = {
1434         "pattern 1", "pattern 2", "idle", "off"
1435 };
1436 #endif
1437
1438 /*
1439  * These are source-specific values; current Intel hardware supports
1440  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1441  */
1442
1443 static uint8_t
1444 intel_dp_voltage_max(struct intel_dp *intel_dp)
1445 {
1446         struct drm_device *dev = intel_dp->base.base.dev;
1447
1448         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1449                 return DP_TRAIN_VOLTAGE_SWING_800;
1450         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1451                 return DP_TRAIN_VOLTAGE_SWING_1200;
1452         else
1453                 return DP_TRAIN_VOLTAGE_SWING_800;
1454 }
1455
1456 static uint8_t
1457 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1458 {
1459         struct drm_device *dev = intel_dp->base.base.dev;
1460
1461         if (IS_HASWELL(dev)) {
1462                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1463                 case DP_TRAIN_VOLTAGE_SWING_400:
1464                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1465                 case DP_TRAIN_VOLTAGE_SWING_600:
1466                         return DP_TRAIN_PRE_EMPHASIS_6;
1467                 case DP_TRAIN_VOLTAGE_SWING_800:
1468                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1469                 case DP_TRAIN_VOLTAGE_SWING_1200:
1470                 default:
1471                         return DP_TRAIN_PRE_EMPHASIS_0;
1472                 }
1473         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1474                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1475                 case DP_TRAIN_VOLTAGE_SWING_400:
1476                         return DP_TRAIN_PRE_EMPHASIS_6;
1477                 case DP_TRAIN_VOLTAGE_SWING_600:
1478                 case DP_TRAIN_VOLTAGE_SWING_800:
1479                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1480                 default:
1481                         return DP_TRAIN_PRE_EMPHASIS_0;
1482                 }
1483         } else {
1484                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1485                 case DP_TRAIN_VOLTAGE_SWING_400:
1486                         return DP_TRAIN_PRE_EMPHASIS_6;
1487                 case DP_TRAIN_VOLTAGE_SWING_600:
1488                         return DP_TRAIN_PRE_EMPHASIS_6;
1489                 case DP_TRAIN_VOLTAGE_SWING_800:
1490                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1491                 case DP_TRAIN_VOLTAGE_SWING_1200:
1492                 default:
1493                         return DP_TRAIN_PRE_EMPHASIS_0;
1494                 }
1495         }
1496 }
1497
1498 static void
1499 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1500 {
1501         uint8_t v = 0;
1502         uint8_t p = 0;
1503         int lane;
1504         uint8_t voltage_max;
1505         uint8_t preemph_max;
1506
1507         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1508                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1509                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1510
1511                 if (this_v > v)
1512                         v = this_v;
1513                 if (this_p > p)
1514                         p = this_p;
1515         }
1516
1517         voltage_max = intel_dp_voltage_max(intel_dp);
1518         if (v >= voltage_max)
1519                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1520
1521         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1522         if (p >= preemph_max)
1523                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1524
1525         for (lane = 0; lane < 4; lane++)
1526                 intel_dp->train_set[lane] = v | p;
1527 }
1528
1529 static uint32_t
1530 intel_dp_signal_levels(uint8_t train_set)
1531 {
1532         uint32_t        signal_levels = 0;
1533
1534         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1535         case DP_TRAIN_VOLTAGE_SWING_400:
1536         default:
1537                 signal_levels |= DP_VOLTAGE_0_4;
1538                 break;
1539         case DP_TRAIN_VOLTAGE_SWING_600:
1540                 signal_levels |= DP_VOLTAGE_0_6;
1541                 break;
1542         case DP_TRAIN_VOLTAGE_SWING_800:
1543                 signal_levels |= DP_VOLTAGE_0_8;
1544                 break;
1545         case DP_TRAIN_VOLTAGE_SWING_1200:
1546                 signal_levels |= DP_VOLTAGE_1_2;
1547                 break;
1548         }
1549         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1550         case DP_TRAIN_PRE_EMPHASIS_0:
1551         default:
1552                 signal_levels |= DP_PRE_EMPHASIS_0;
1553                 break;
1554         case DP_TRAIN_PRE_EMPHASIS_3_5:
1555                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1556                 break;
1557         case DP_TRAIN_PRE_EMPHASIS_6:
1558                 signal_levels |= DP_PRE_EMPHASIS_6;
1559                 break;
1560         case DP_TRAIN_PRE_EMPHASIS_9_5:
1561                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1562                 break;
1563         }
1564         return signal_levels;
1565 }
1566
1567 /* Gen6's DP voltage swing and pre-emphasis control */
1568 static uint32_t
1569 intel_gen6_edp_signal_levels(uint8_t train_set)
1570 {
1571         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1572                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1573         switch (signal_levels) {
1574         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1575         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1576                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1577         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1578                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1579         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1580         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1581                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1582         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1583         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1584                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1585         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1586         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1587                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1588         default:
1589                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1590                               "0x%x\n", signal_levels);
1591                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1592         }
1593 }
1594
1595 /* Gen7's DP voltage swing and pre-emphasis control */
1596 static uint32_t
1597 intel_gen7_edp_signal_levels(uint8_t train_set)
1598 {
1599         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1600                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1601         switch (signal_levels) {
1602         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1603                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1604         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1605                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1606         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1607                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1608
1609         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1610                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1611         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1612                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1613
1614         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1615                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1616         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1617                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1618
1619         default:
1620                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1621                               "0x%x\n", signal_levels);
1622                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1623         }
1624 }
1625
1626 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1627 static uint32_t
1628 intel_dp_signal_levels_hsw(uint8_t train_set)
1629 {
1630         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1631                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1632         switch (signal_levels) {
1633         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1634                 return DDI_BUF_EMP_400MV_0DB_HSW;
1635         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1636                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1637         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1638                 return DDI_BUF_EMP_400MV_6DB_HSW;
1639         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1640                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1641
1642         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1643                 return DDI_BUF_EMP_600MV_0DB_HSW;
1644         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1645                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1646         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1647                 return DDI_BUF_EMP_600MV_6DB_HSW;
1648
1649         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1650                 return DDI_BUF_EMP_800MV_0DB_HSW;
1651         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1652                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1653         default:
1654                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1655                               "0x%x\n", signal_levels);
1656                 return DDI_BUF_EMP_400MV_0DB_HSW;
1657         }
1658 }
1659
1660 static bool
1661 intel_dp_set_link_train(struct intel_dp *intel_dp,
1662                         uint32_t dp_reg_value,
1663                         uint8_t dp_train_pat)
1664 {
1665         struct drm_device *dev = intel_dp->base.base.dev;
1666         struct drm_i915_private *dev_priv = dev->dev_private;
1667         int ret;
1668         uint32_t temp;
1669
1670         if (IS_HASWELL(dev)) {
1671                 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1672
1673                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1674                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1675                 else
1676                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1677
1678                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1679                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1680                 case DP_TRAINING_PATTERN_DISABLE:
1681                         temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1682                         I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1683
1684                         if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1685                                       DP_TP_STATUS_IDLE_DONE), 1))
1686                                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1687
1688                         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1689                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1690
1691                         break;
1692                 case DP_TRAINING_PATTERN_1:
1693                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1694                         break;
1695                 case DP_TRAINING_PATTERN_2:
1696                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1697                         break;
1698                 case DP_TRAINING_PATTERN_3:
1699                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1700                         break;
1701                 }
1702                 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1703
1704         } else if (HAS_PCH_CPT(dev) &&
1705                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1706                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1707
1708                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1709                 case DP_TRAINING_PATTERN_DISABLE:
1710                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1711                         break;
1712                 case DP_TRAINING_PATTERN_1:
1713                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1714                         break;
1715                 case DP_TRAINING_PATTERN_2:
1716                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1717                         break;
1718                 case DP_TRAINING_PATTERN_3:
1719                         DRM_ERROR("DP training pattern 3 not supported\n");
1720                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1721                         break;
1722                 }
1723
1724         } else {
1725                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1726
1727                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1728                 case DP_TRAINING_PATTERN_DISABLE:
1729                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1730                         break;
1731                 case DP_TRAINING_PATTERN_1:
1732                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1733                         break;
1734                 case DP_TRAINING_PATTERN_2:
1735                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1736                         break;
1737                 case DP_TRAINING_PATTERN_3:
1738                         DRM_ERROR("DP training pattern 3 not supported\n");
1739                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1740                         break;
1741                 }
1742         }
1743
1744         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1745         POSTING_READ(intel_dp->output_reg);
1746
1747         intel_dp_aux_native_write_1(intel_dp,
1748                                     DP_TRAINING_PATTERN_SET,
1749                                     dp_train_pat);
1750
1751         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1752             DP_TRAINING_PATTERN_DISABLE) {
1753                 ret = intel_dp_aux_native_write(intel_dp,
1754                                                 DP_TRAINING_LANE0_SET,
1755                                                 intel_dp->train_set,
1756                                                 intel_dp->lane_count);
1757                 if (ret != intel_dp->lane_count)
1758                         return false;
1759         }
1760
1761         return true;
1762 }
1763
1764 /* Enable corresponding port and start training pattern 1 */
1765 void
1766 intel_dp_start_link_train(struct intel_dp *intel_dp)
1767 {
1768         struct drm_encoder *encoder = &intel_dp->base.base;
1769         struct drm_device *dev = encoder->dev;
1770         int i;
1771         uint8_t voltage;
1772         bool clock_recovery = false;
1773         int voltage_tries, loop_tries;
1774         uint32_t DP = intel_dp->DP;
1775
1776         if (IS_HASWELL(dev))
1777                 intel_ddi_prepare_link_retrain(encoder);
1778
1779         /* Write the link configuration data */
1780         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1781                                   intel_dp->link_configuration,
1782                                   DP_LINK_CONFIGURATION_SIZE);
1783
1784         DP |= DP_PORT_EN;
1785
1786         memset(intel_dp->train_set, 0, 4);
1787         voltage = 0xff;
1788         voltage_tries = 0;
1789         loop_tries = 0;
1790         clock_recovery = false;
1791         for (;;) {
1792                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1793                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1794                 uint32_t    signal_levels;
1795
1796                 if (IS_HASWELL(dev)) {
1797                         signal_levels = intel_dp_signal_levels_hsw(
1798                                                         intel_dp->train_set[0]);
1799                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1800                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1801                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1802                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1803                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1804                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1805                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1806                 } else {
1807                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1808                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1809                 }
1810                 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1811                               signal_levels);
1812
1813                 /* Set training pattern 1 */
1814                 if (!intel_dp_set_link_train(intel_dp, DP,
1815                                              DP_TRAINING_PATTERN_1 |
1816                                              DP_LINK_SCRAMBLING_DISABLE))
1817                         break;
1818
1819                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1820                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1821                         DRM_ERROR("failed to get link status\n");
1822                         break;
1823                 }
1824
1825                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1826                         DRM_DEBUG_KMS("clock recovery OK\n");
1827                         clock_recovery = true;
1828                         break;
1829                 }
1830
1831                 /* Check to see if we've tried the max voltage */
1832                 for (i = 0; i < intel_dp->lane_count; i++)
1833                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1834                                 break;
1835                 if (i == intel_dp->lane_count && voltage_tries == 5) {
1836                         if (++loop_tries == 5) {
1837                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1838                                 break;
1839                         }
1840                         memset(intel_dp->train_set, 0, 4);
1841                         voltage_tries = 0;
1842                         continue;
1843                 }
1844
1845                 /* Check to see if we've tried the same voltage 5 times */
1846                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1847                         voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1848                         voltage_tries = 0;
1849                 } else
1850                         ++voltage_tries;
1851
1852                 /* Compute new intel_dp->train_set as requested by target */
1853                 intel_get_adjust_train(intel_dp, link_status);
1854         }
1855
1856         intel_dp->DP = DP;
1857 }
1858
1859 void
1860 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1861 {
1862         struct drm_device *dev = intel_dp->base.base.dev;
1863         bool channel_eq = false;
1864         int tries, cr_tries;
1865         uint32_t DP = intel_dp->DP;
1866
1867         /* channel equalization */
1868         tries = 0;
1869         cr_tries = 0;
1870         channel_eq = false;
1871         for (;;) {
1872                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1873                 uint32_t    signal_levels;
1874                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1875
1876                 if (cr_tries > 5) {
1877                         DRM_ERROR("failed to train DP, aborting\n");
1878                         intel_dp_link_down(intel_dp);
1879                         break;
1880                 }
1881
1882                 if (IS_HASWELL(dev)) {
1883                         signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1884                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1885                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1886                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1887                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1888                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1889                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1890                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1891                 } else {
1892                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1893                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1894                 }
1895
1896                 /* channel eq pattern */
1897                 if (!intel_dp_set_link_train(intel_dp, DP,
1898                                              DP_TRAINING_PATTERN_2 |
1899                                              DP_LINK_SCRAMBLING_DISABLE))
1900                         break;
1901
1902                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1903                 if (!intel_dp_get_link_status(intel_dp, link_status))
1904                         break;
1905
1906                 /* Make sure clock is still ok */
1907                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1908                         intel_dp_start_link_train(intel_dp);
1909                         cr_tries++;
1910                         continue;
1911                 }
1912
1913                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1914                         channel_eq = true;
1915                         break;
1916                 }
1917
1918                 /* Try 5 times, then try clock recovery if that fails */
1919                 if (tries > 5) {
1920                         intel_dp_link_down(intel_dp);
1921                         intel_dp_start_link_train(intel_dp);
1922                         tries = 0;
1923                         cr_tries++;
1924                         continue;
1925                 }
1926
1927                 /* Compute new intel_dp->train_set as requested by target */
1928                 intel_get_adjust_train(intel_dp, link_status);
1929                 ++tries;
1930         }
1931
1932         if (channel_eq)
1933                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1934
1935         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1936 }
1937
1938 static void
1939 intel_dp_link_down(struct intel_dp *intel_dp)
1940 {
1941         struct drm_device *dev = intel_dp->base.base.dev;
1942         struct drm_i915_private *dev_priv = dev->dev_private;
1943         uint32_t DP = intel_dp->DP;
1944
1945         /*
1946          * DDI code has a strict mode set sequence and we should try to respect
1947          * it, otherwise we might hang the machine in many different ways. So we
1948          * really should be disabling the port only on a complete crtc_disable
1949          * sequence. This function is just called under two conditions on DDI
1950          * code:
1951          * - Link train failed while doing crtc_enable, and on this case we
1952          *   really should respect the mode set sequence and wait for a
1953          *   crtc_disable.
1954          * - Someone turned the monitor off and intel_dp_check_link_status
1955          *   called us. We don't need to disable the whole port on this case, so
1956          *   when someone turns the monitor on again,
1957          *   intel_ddi_prepare_link_retrain will take care of redoing the link
1958          *   train.
1959          */
1960         if (IS_HASWELL(dev))
1961                 return;
1962
1963         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1964                 return;
1965
1966         DRM_DEBUG_KMS("\n");
1967
1968         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1969                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1970                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1971         } else {
1972                 DP &= ~DP_LINK_TRAIN_MASK;
1973                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1974         }
1975         POSTING_READ(intel_dp->output_reg);
1976
1977         msleep(17);
1978
1979         if (HAS_PCH_IBX(dev) &&
1980             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1981                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1982
1983                 /* Hardware workaround: leaving our transcoder select
1984                  * set to transcoder B while it's off will prevent the
1985                  * corresponding HDMI output on transcoder A.
1986                  *
1987                  * Combine this with another hardware workaround:
1988                  * transcoder select bit can only be cleared while the
1989                  * port is enabled.
1990                  */
1991                 DP &= ~DP_PIPEB_SELECT;
1992                 I915_WRITE(intel_dp->output_reg, DP);
1993
1994                 /* Changes to enable or select take place the vblank
1995                  * after being written.
1996                  */
1997                 if (crtc == NULL) {
1998                         /* We can arrive here never having been attached
1999                          * to a CRTC, for instance, due to inheriting
2000                          * random state from the BIOS.
2001                          *
2002                          * If the pipe is not running, play safe and
2003                          * wait for the clocks to stabilise before
2004                          * continuing.
2005                          */
2006                         POSTING_READ(intel_dp->output_reg);
2007                         msleep(50);
2008                 } else
2009                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2010         }
2011
2012         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2013         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2014         POSTING_READ(intel_dp->output_reg);
2015         msleep(intel_dp->panel_power_down_delay);
2016 }
2017
2018 static bool
2019 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2020 {
2021         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2022                                            sizeof(intel_dp->dpcd)) == 0)
2023                 return false; /* aux transfer failed */
2024
2025         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2026                 return false; /* DPCD not present */
2027
2028         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2029               DP_DWN_STRM_PORT_PRESENT))
2030                 return true; /* native DP sink */
2031
2032         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2033                 return true; /* no per-port downstream info */
2034
2035         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2036                                            intel_dp->downstream_ports,
2037                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2038                 return false; /* downstream port status fetch failed */
2039
2040         return true;
2041 }
2042
2043 static void
2044 intel_dp_probe_oui(struct intel_dp *intel_dp)
2045 {
2046         u8 buf[3];
2047
2048         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2049                 return;
2050
2051         ironlake_edp_panel_vdd_on(intel_dp);
2052
2053         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2054                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2055                               buf[0], buf[1], buf[2]);
2056
2057         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2058                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2059                               buf[0], buf[1], buf[2]);
2060
2061         ironlake_edp_panel_vdd_off(intel_dp, false);
2062 }
2063
2064 static bool
2065 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2066 {
2067         int ret;
2068
2069         ret = intel_dp_aux_native_read_retry(intel_dp,
2070                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2071                                              sink_irq_vector, 1);
2072         if (!ret)
2073                 return false;
2074
2075         return true;
2076 }
2077
2078 static void
2079 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2080 {
2081         /* NAK by default */
2082         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2083 }
2084
2085 /*
2086  * According to DP spec
2087  * 5.1.2:
2088  *  1. Read DPCD
2089  *  2. Configure link according to Receiver Capabilities
2090  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2091  *  4. Check link status on receipt of hot-plug interrupt
2092  */
2093
2094 static void
2095 intel_dp_check_link_status(struct intel_dp *intel_dp)
2096 {
2097         u8 sink_irq_vector;
2098         u8 link_status[DP_LINK_STATUS_SIZE];
2099
2100         if (!intel_dp->base.connectors_active)
2101                 return;
2102
2103         if (WARN_ON(!intel_dp->base.base.crtc))
2104                 return;
2105
2106         /* Try to read receiver status if the link appears to be up */
2107         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2108                 intel_dp_link_down(intel_dp);
2109                 return;
2110         }
2111
2112         /* Now read the DPCD to see if it's actually running */
2113         if (!intel_dp_get_dpcd(intel_dp)) {
2114                 intel_dp_link_down(intel_dp);
2115                 return;
2116         }
2117
2118         /* Try to read the source of the interrupt */
2119         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2120             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2121                 /* Clear interrupt source */
2122                 intel_dp_aux_native_write_1(intel_dp,
2123                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2124                                             sink_irq_vector);
2125
2126                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2127                         intel_dp_handle_test_request(intel_dp);
2128                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2129                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2130         }
2131
2132         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2133                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2134                               drm_get_encoder_name(&intel_dp->base.base));
2135                 intel_dp_start_link_train(intel_dp);
2136                 intel_dp_complete_link_train(intel_dp);
2137         }
2138 }
2139
2140 /* XXX this is probably wrong for multiple downstream ports */
2141 static enum drm_connector_status
2142 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2143 {
2144         uint8_t *dpcd = intel_dp->dpcd;
2145         bool hpd;
2146         uint8_t type;
2147
2148         if (!intel_dp_get_dpcd(intel_dp))
2149                 return connector_status_disconnected;
2150
2151         /* if there's no downstream port, we're done */
2152         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2153                 return connector_status_connected;
2154
2155         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2156         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2157         if (hpd) {
2158                 uint8_t reg;
2159                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2160                                                     &reg, 1))
2161                         return connector_status_unknown;
2162                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2163                                               : connector_status_disconnected;
2164         }
2165
2166         /* If no HPD, poke DDC gently */
2167         if (drm_probe_ddc(&intel_dp->adapter))
2168                 return connector_status_connected;
2169
2170         /* Well we tried, say unknown for unreliable port types */
2171         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2172         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2173                 return connector_status_unknown;
2174
2175         /* Anything else is out of spec, warn and ignore */
2176         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2177         return connector_status_disconnected;
2178 }
2179
2180 static enum drm_connector_status
2181 ironlake_dp_detect(struct intel_dp *intel_dp)
2182 {
2183         enum drm_connector_status status;
2184
2185         /* Can't disconnect eDP, but you can close the lid... */
2186         if (is_edp(intel_dp)) {
2187                 status = intel_panel_detect(intel_dp->base.base.dev);
2188                 if (status == connector_status_unknown)
2189                         status = connector_status_connected;
2190                 return status;
2191         }
2192
2193         return intel_dp_detect_dpcd(intel_dp);
2194 }
2195
2196 static enum drm_connector_status
2197 g4x_dp_detect(struct intel_dp *intel_dp)
2198 {
2199         struct drm_device *dev = intel_dp->base.base.dev;
2200         struct drm_i915_private *dev_priv = dev->dev_private;
2201         uint32_t bit;
2202
2203         switch (intel_dp->output_reg) {
2204         case DP_B:
2205                 bit = DPB_HOTPLUG_LIVE_STATUS;
2206                 break;
2207         case DP_C:
2208                 bit = DPC_HOTPLUG_LIVE_STATUS;
2209                 break;
2210         case DP_D:
2211                 bit = DPD_HOTPLUG_LIVE_STATUS;
2212                 break;
2213         default:
2214                 return connector_status_unknown;
2215         }
2216
2217         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2218                 return connector_status_disconnected;
2219
2220         return intel_dp_detect_dpcd(intel_dp);
2221 }
2222
2223 static struct edid *
2224 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2225 {
2226         struct intel_connector *intel_connector = to_intel_connector(connector);
2227
2228         /* use cached edid if we have one */
2229         if (intel_connector->edid) {
2230                 struct edid *edid;
2231                 int size;
2232
2233                 /* invalid edid */
2234                 if (IS_ERR(intel_connector->edid))
2235                         return NULL;
2236
2237                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2238                 edid = kmalloc(size, GFP_KERNEL);
2239                 if (!edid)
2240                         return NULL;
2241
2242                 memcpy(edid, intel_connector->edid, size);
2243                 return edid;
2244         }
2245
2246         return drm_get_edid(connector, adapter);
2247 }
2248
2249 static int
2250 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2251 {
2252         struct intel_connector *intel_connector = to_intel_connector(connector);
2253
2254         /* use cached edid if we have one */
2255         if (intel_connector->edid) {
2256                 /* invalid edid */
2257                 if (IS_ERR(intel_connector->edid))
2258                         return 0;
2259
2260                 return intel_connector_update_modes(connector,
2261                                                     intel_connector->edid);
2262         }
2263
2264         return intel_ddc_get_modes(connector, adapter);
2265 }
2266
2267
2268 /**
2269  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2270  *
2271  * \return true if DP port is connected.
2272  * \return false if DP port is disconnected.
2273  */
2274 static enum drm_connector_status
2275 intel_dp_detect(struct drm_connector *connector, bool force)
2276 {
2277         struct intel_dp *intel_dp = intel_attached_dp(connector);
2278         struct drm_device *dev = intel_dp->base.base.dev;
2279         enum drm_connector_status status;
2280         struct edid *edid = NULL;
2281
2282         intel_dp->has_audio = false;
2283
2284         if (HAS_PCH_SPLIT(dev))
2285                 status = ironlake_dp_detect(intel_dp);
2286         else
2287                 status = g4x_dp_detect(intel_dp);
2288
2289         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2290                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2291                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2292                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2293
2294         if (status != connector_status_connected)
2295                 return status;
2296
2297         intel_dp_probe_oui(intel_dp);
2298
2299         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2300                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2301         } else {
2302                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2303                 if (edid) {
2304                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2305                         kfree(edid);
2306                 }
2307         }
2308
2309         return connector_status_connected;
2310 }
2311
2312 static int intel_dp_get_modes(struct drm_connector *connector)
2313 {
2314         struct intel_dp *intel_dp = intel_attached_dp(connector);
2315         struct intel_connector *intel_connector = to_intel_connector(connector);
2316         struct drm_device *dev = intel_dp->base.base.dev;
2317         int ret;
2318
2319         /* We should parse the EDID data and find out if it has an audio sink
2320          */
2321
2322         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2323         if (ret)
2324                 return ret;
2325
2326         /* if eDP has no EDID, fall back to fixed mode */
2327         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2328                 struct drm_display_mode *mode;
2329                 mode = drm_mode_duplicate(dev,
2330                                           intel_connector->panel.fixed_mode);
2331                 if (mode) {
2332                         drm_mode_probed_add(connector, mode);
2333                         return 1;
2334                 }
2335         }
2336         return 0;
2337 }
2338
2339 static bool
2340 intel_dp_detect_audio(struct drm_connector *connector)
2341 {
2342         struct intel_dp *intel_dp = intel_attached_dp(connector);
2343         struct edid *edid;
2344         bool has_audio = false;
2345
2346         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2347         if (edid) {
2348                 has_audio = drm_detect_monitor_audio(edid);
2349                 kfree(edid);
2350         }
2351
2352         return has_audio;
2353 }
2354
2355 static int
2356 intel_dp_set_property(struct drm_connector *connector,
2357                       struct drm_property *property,
2358                       uint64_t val)
2359 {
2360         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2361         struct intel_dp *intel_dp = intel_attached_dp(connector);
2362         int ret;
2363
2364         ret = drm_connector_property_set_value(connector, property, val);
2365         if (ret)
2366                 return ret;
2367
2368         if (property == dev_priv->force_audio_property) {
2369                 int i = val;
2370                 bool has_audio;
2371
2372                 if (i == intel_dp->force_audio)
2373                         return 0;
2374
2375                 intel_dp->force_audio = i;
2376
2377                 if (i == HDMI_AUDIO_AUTO)
2378                         has_audio = intel_dp_detect_audio(connector);
2379                 else
2380                         has_audio = (i == HDMI_AUDIO_ON);
2381
2382                 if (has_audio == intel_dp->has_audio)
2383                         return 0;
2384
2385                 intel_dp->has_audio = has_audio;
2386                 goto done;
2387         }
2388
2389         if (property == dev_priv->broadcast_rgb_property) {
2390                 if (val == !!intel_dp->color_range)
2391                         return 0;
2392
2393                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2394                 goto done;
2395         }
2396
2397         return -EINVAL;
2398
2399 done:
2400         if (intel_dp->base.base.crtc) {
2401                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2402                 intel_set_mode(crtc, &crtc->mode,
2403                                crtc->x, crtc->y, crtc->fb);
2404         }
2405
2406         return 0;
2407 }
2408
2409 static void
2410 intel_dp_destroy(struct drm_connector *connector)
2411 {
2412         struct drm_device *dev = connector->dev;
2413         struct intel_dp *intel_dp = intel_attached_dp(connector);
2414         struct intel_connector *intel_connector = to_intel_connector(connector);
2415
2416         if (!IS_ERR_OR_NULL(intel_connector->edid))
2417                 kfree(intel_connector->edid);
2418
2419         if (is_edp(intel_dp)) {
2420                 intel_panel_destroy_backlight(dev);
2421                 intel_panel_fini(&intel_connector->panel);
2422         }
2423
2424         drm_sysfs_connector_remove(connector);
2425         drm_connector_cleanup(connector);
2426         kfree(connector);
2427 }
2428
2429 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2430 {
2431         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2432
2433         i2c_del_adapter(&intel_dp->adapter);
2434         drm_encoder_cleanup(encoder);
2435         if (is_edp(intel_dp)) {
2436                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2437                 ironlake_panel_vdd_off_sync(intel_dp);
2438         }
2439         kfree(intel_dp);
2440 }
2441
2442 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2443         .mode_fixup = intel_dp_mode_fixup,
2444         .mode_set = intel_dp_mode_set,
2445         .disable = intel_encoder_noop,
2446 };
2447
2448 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2449         .mode_fixup = intel_dp_mode_fixup,
2450         .mode_set = intel_ddi_mode_set,
2451         .disable = intel_encoder_noop,
2452 };
2453
2454 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2455         .dpms = intel_connector_dpms,
2456         .detect = intel_dp_detect,
2457         .fill_modes = drm_helper_probe_single_connector_modes,
2458         .set_property = intel_dp_set_property,
2459         .destroy = intel_dp_destroy,
2460 };
2461
2462 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2463         .get_modes = intel_dp_get_modes,
2464         .mode_valid = intel_dp_mode_valid,
2465         .best_encoder = intel_best_encoder,
2466 };
2467
2468 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2469         .destroy = intel_dp_encoder_destroy,
2470 };
2471
2472 static void
2473 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2474 {
2475         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2476
2477         intel_dp_check_link_status(intel_dp);
2478 }
2479
2480 /* Return which DP Port should be selected for Transcoder DP control */
2481 int
2482 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2483 {
2484         struct drm_device *dev = crtc->dev;
2485         struct intel_encoder *encoder;
2486
2487         for_each_encoder_on_crtc(dev, crtc, encoder) {
2488                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2489
2490                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2491                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2492                         return intel_dp->output_reg;
2493         }
2494
2495         return -1;
2496 }
2497
2498 /* check the VBT to see whether the eDP is on DP-D port */
2499 bool intel_dpd_is_edp(struct drm_device *dev)
2500 {
2501         struct drm_i915_private *dev_priv = dev->dev_private;
2502         struct child_device_config *p_child;
2503         int i;
2504
2505         if (!dev_priv->child_dev_num)
2506                 return false;
2507
2508         for (i = 0; i < dev_priv->child_dev_num; i++) {
2509                 p_child = dev_priv->child_dev + i;
2510
2511                 if (p_child->dvo_port == PORT_IDPD &&
2512                     p_child->device_type == DEVICE_TYPE_eDP)
2513                         return true;
2514         }
2515         return false;
2516 }
2517
2518 static void
2519 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2520 {
2521         intel_attach_force_audio_property(connector);
2522         intel_attach_broadcast_rgb_property(connector);
2523 }
2524
2525 void
2526 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2527 {
2528         struct drm_i915_private *dev_priv = dev->dev_private;
2529         struct drm_connector *connector;
2530         struct intel_dp *intel_dp;
2531         struct intel_encoder *intel_encoder;
2532         struct intel_connector *intel_connector;
2533         struct drm_display_mode *fixed_mode = NULL;
2534         const char *name = NULL;
2535         int type;
2536
2537         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2538         if (!intel_dp)
2539                 return;
2540
2541         intel_dp->output_reg = output_reg;
2542         intel_dp->port = port;
2543         /* Preserve the current hw state. */
2544         intel_dp->DP = I915_READ(intel_dp->output_reg);
2545
2546         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2547         if (!intel_connector) {
2548                 kfree(intel_dp);
2549                 return;
2550         }
2551         intel_encoder = &intel_dp->base;
2552         intel_dp->attached_connector = intel_connector;
2553
2554         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2555                 if (intel_dpd_is_edp(dev))
2556                         intel_dp->is_pch_edp = true;
2557
2558         /*
2559          * FIXME : We need to initialize built-in panels before external panels.
2560          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2561          */
2562         if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2563                 type = DRM_MODE_CONNECTOR_eDP;
2564                 intel_encoder->type = INTEL_OUTPUT_EDP;
2565         } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2566                 type = DRM_MODE_CONNECTOR_eDP;
2567                 intel_encoder->type = INTEL_OUTPUT_EDP;
2568         } else {
2569                 type = DRM_MODE_CONNECTOR_DisplayPort;
2570                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2571         }
2572
2573         connector = &intel_connector->base;
2574         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2575         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2576
2577         connector->polled = DRM_CONNECTOR_POLL_HPD;
2578
2579         intel_encoder->cloneable = false;
2580
2581         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2582                           ironlake_panel_vdd_work);
2583
2584         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2585
2586         connector->interlace_allowed = true;
2587         connector->doublescan_allowed = 0;
2588
2589         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2590                          DRM_MODE_ENCODER_TMDS);
2591
2592         if (IS_HASWELL(dev))
2593                 drm_encoder_helper_add(&intel_encoder->base,
2594                                        &intel_dp_helper_funcs_hsw);
2595         else
2596                 drm_encoder_helper_add(&intel_encoder->base,
2597                                        &intel_dp_helper_funcs);
2598
2599         intel_connector_attach_encoder(intel_connector, intel_encoder);
2600         drm_sysfs_connector_add(connector);
2601
2602         if (IS_HASWELL(dev)) {
2603                 intel_encoder->enable = intel_enable_ddi;
2604                 intel_encoder->pre_enable = intel_ddi_pre_enable;
2605                 intel_encoder->disable = intel_disable_ddi;
2606                 intel_encoder->post_disable = intel_ddi_post_disable;
2607                 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2608         } else {
2609                 intel_encoder->enable = intel_enable_dp;
2610                 intel_encoder->pre_enable = intel_pre_enable_dp;
2611                 intel_encoder->disable = intel_disable_dp;
2612                 intel_encoder->post_disable = intel_post_disable_dp;
2613                 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2614         }
2615         intel_connector->get_hw_state = intel_connector_get_hw_state;
2616
2617         /* Set up the DDC bus. */
2618         switch (port) {
2619         case PORT_A:
2620                 name = "DPDDC-A";
2621                 break;
2622         case PORT_B:
2623                 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2624                 name = "DPDDC-B";
2625                 break;
2626         case PORT_C:
2627                 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2628                 name = "DPDDC-C";
2629                 break;
2630         case PORT_D:
2631                 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2632                 name = "DPDDC-D";
2633                 break;
2634         default:
2635                 WARN(1, "Invalid port %c\n", port_name(port));
2636                 break;
2637         }
2638
2639         /* Cache some DPCD data in the eDP case */
2640         if (is_edp(intel_dp)) {
2641                 struct edp_power_seq    cur, vbt, spec, final;
2642                 u32 pp_on, pp_off, pp_div, pp;
2643
2644                 /* Workaround: Need to write PP_CONTROL with the unlock key as
2645                  * the very first thing. */
2646                 pp = ironlake_get_pp_control(dev_priv);
2647                 I915_WRITE(PCH_PP_CONTROL, pp);
2648
2649                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2650                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2651                 pp_div = I915_READ(PCH_PP_DIVISOR);
2652
2653                 /* Pull timing values out of registers */
2654                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2655                         PANEL_POWER_UP_DELAY_SHIFT;
2656
2657                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2658                         PANEL_LIGHT_ON_DELAY_SHIFT;
2659
2660                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2661                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2662
2663                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2664                         PANEL_POWER_DOWN_DELAY_SHIFT;
2665
2666                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2667                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2668
2669                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2670                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2671
2672                 vbt = dev_priv->edp.pps;
2673
2674                 /* Upper limits from eDP 1.3 spec. Note that we use the clunky
2675                  * units of our hw here, which are all in 100usec. */
2676                 spec.t1_t3 = 210 * 10;
2677                 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2678                 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2679                 spec.t10 = 500 * 10;
2680                 /* This one is special and actually in units of 100ms, but zero
2681                  * based in the hw (so we need to add 100 ms). But the sw vbt
2682                  * table multiplies it with 1000 to make it in units of 100usec,
2683                  * too. */
2684                 spec.t11_t12 = (510 + 100) * 10;
2685
2686                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2687                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2688
2689                 /* Use the max of the register settings and vbt. If both are
2690                  * unset, fall back to the spec limits. */
2691 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2692                                                spec.field : \
2693                                                max(cur.field, vbt.field))
2694                 assign_final(t1_t3);
2695                 assign_final(t8);
2696                 assign_final(t9);
2697                 assign_final(t10);
2698                 assign_final(t11_t12);
2699 #undef assign_final
2700
2701 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2702                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2703                 intel_dp->backlight_on_delay = get_delay(t8);
2704                 intel_dp->backlight_off_delay = get_delay(t9);
2705                 intel_dp->panel_power_down_delay = get_delay(t10);
2706                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2707 #undef get_delay
2708
2709                 /* And finally store the new values in the power sequencer. */
2710                 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2711                         (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2712                 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2713                          (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2714                 /* Compute the divisor for the pp clock, simply match the Bspec
2715                  * formula. */
2716                 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2717                                 << PP_REFERENCE_DIVIDER_SHIFT;
2718                 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2719                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2720
2721                 /* Haswell doesn't have any port selection bits for the panel
2722                  * power sequence any more. */
2723                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2724                         if (is_cpu_edp(intel_dp))
2725                                 pp_on |= PANEL_POWER_PORT_DP_A;
2726                         else
2727                                 pp_on |= PANEL_POWER_PORT_DP_D;
2728                 }
2729
2730                 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2731                 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2732                 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2733
2734
2735                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2736                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2737                               intel_dp->panel_power_cycle_delay);
2738
2739                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2740                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2741
2742                 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2743                               I915_READ(PCH_PP_ON_DELAYS),
2744                               I915_READ(PCH_PP_OFF_DELAYS),
2745                               I915_READ(PCH_PP_DIVISOR));
2746         }
2747
2748         intel_dp_i2c_init(intel_dp, intel_connector, name);
2749
2750         if (is_edp(intel_dp)) {
2751                 bool ret;
2752                 struct drm_display_mode *scan;
2753                 struct edid *edid;
2754
2755                 ironlake_edp_panel_vdd_on(intel_dp);
2756                 ret = intel_dp_get_dpcd(intel_dp);
2757                 ironlake_edp_panel_vdd_off(intel_dp, false);
2758
2759                 if (ret) {
2760                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2761                                 dev_priv->no_aux_handshake =
2762                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2763                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2764                 } else {
2765                         /* if this fails, presume the device is a ghost */
2766                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2767                         intel_dp_encoder_destroy(&intel_dp->base.base);
2768                         intel_dp_destroy(&intel_connector->base);
2769                         return;
2770                 }
2771
2772                 ironlake_edp_panel_vdd_on(intel_dp);
2773                 edid = drm_get_edid(connector, &intel_dp->adapter);
2774                 if (edid) {
2775                         if (drm_add_edid_modes(connector, edid)) {
2776                                 drm_mode_connector_update_edid_property(connector, edid);
2777                                 drm_edid_to_eld(connector, edid);
2778                         } else {
2779                                 kfree(edid);
2780                                 edid = ERR_PTR(-EINVAL);
2781                         }
2782                 } else {
2783                         edid = ERR_PTR(-ENOENT);
2784                 }
2785                 intel_connector->edid = edid;
2786
2787                 /* prefer fixed mode from EDID if available */
2788                 list_for_each_entry(scan, &connector->probed_modes, head) {
2789                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2790                                 fixed_mode = drm_mode_duplicate(dev, scan);
2791                                 break;
2792                         }
2793                 }
2794
2795                 /* fallback to VBT if available for eDP */
2796                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2797                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2798                         if (fixed_mode)
2799                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2800                 }
2801
2802                 ironlake_edp_panel_vdd_off(intel_dp, false);
2803         }
2804
2805         intel_encoder->hot_plug = intel_dp_hot_plug;
2806
2807         if (is_edp(intel_dp)) {
2808                 intel_panel_init(&intel_connector->panel, fixed_mode);
2809                 intel_panel_setup_backlight(connector);
2810         }
2811
2812         intel_dp_add_properties(intel_dp, connector);
2813
2814         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2815          * 0xd.  Failure to do so will result in spurious interrupts being
2816          * generated on the port when a cable is not attached.
2817          */
2818         if (IS_G4X(dev) && !IS_GM45(dev)) {
2819                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2820                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2821         }
2822 }