4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O
13 * APIC code. In particular, we now have separate
14 * handlers for edge and level triggered
16 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
17 * allocation PCI to vector mapping, shared PCI
19 * 00/10/27 D. Mosberger Document things a bit more to make them more
20 * understandable. Clean up much of the old
22 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts
23 * and fixes for ACPI S5(SoftOff) support.
24 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
25 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt
26 * vectors in iosapic_set_affinity(),
27 * initializations for /proc/irq/#/smp_affinity
28 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
29 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
30 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to
31 * IOSAPIC mapping error
32 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
33 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system
34 * interrupt, vector, etc.)
35 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's
37 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
38 * Remove iosapic_address & gsi_base from
39 * external interfaces. Rationalize
40 * __init/__devinit attributes.
41 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
42 * Updated to work with irq migration necessary
46 * Here is what the interrupt logic between a PCI device and the kernel looks
49 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
50 * INTD). The device is uniquely identified by its bus-, and slot-number
51 * (the function number does not matter here because all functions share
52 * the same interrupt lines).
54 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
55 * controller. Multiple interrupt lines may have to share the same
56 * IOSAPIC pin (if they're level triggered and use the same polarity).
57 * Each interrupt line has a unique Global System Interrupt (GSI) number
58 * which can be calculated as the sum of the controller's base GSI number
59 * and the IOSAPIC pin number to which the line connects.
61 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
62 * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then
65 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is
66 * used as architecture-independent interrupt handling mechanism in Linux.
67 * As an IRQ is a number, we have to have
68 * IA-64 interrupt vector number <-> IRQ number mapping. On smaller
69 * systems, we use one-to-one mapping between IA-64 vector and IRQ. A
70 * platform can implement platform_irq_to_vector(irq) and
71 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
72 * Please see also include/asm-ia64/hw_irq.h for those APIs.
74 * To sum up, there are three levels of mappings involved:
76 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
78 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
79 * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ
80 * (isa_irq) is the only exception in this source code.
83 #include <linux/acpi.h>
84 #include <linux/init.h>
85 #include <linux/irq.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/pci.h>
89 #include <linux/smp.h>
90 #include <linux/string.h>
91 #include <linux/bootmem.h>
93 #include <asm/delay.h>
94 #include <asm/hw_irq.h>
96 #include <asm/iosapic.h>
97 #include <asm/machvec.h>
98 #include <asm/processor.h>
99 #include <asm/ptrace.h>
100 #include <asm/system.h>
102 #undef DEBUG_INTERRUPT_ROUTING
104 #ifdef DEBUG_INTERRUPT_ROUTING
105 #define DBG(fmt...) printk(fmt)
110 #define NR_PREALLOCATE_RTE_ENTRIES \
111 (PAGE_SIZE / sizeof(struct iosapic_rte_info))
112 #define RTE_PREALLOCATED (1)
114 static DEFINE_SPINLOCK(iosapic_lock);
117 * These tables map IA-64 vectors to the IOSAPIC pin that generates this
123 static struct iosapic {
124 char __iomem *addr; /* base address of IOSAPIC */
125 unsigned int gsi_base; /* GSI base */
126 unsigned short num_rte; /* # of RTEs on this IOSAPIC */
127 int rtes_inuse; /* # of RTEs in use on this IOSAPIC */
129 unsigned short node; /* numa node association via pxm */
131 spinlock_t lock; /* lock for indirect reg access */
132 } iosapic_lists[NR_IOSAPICS];
134 struct iosapic_rte_info {
135 struct list_head rte_list; /* RTEs sharing the same vector */
136 char rte_index; /* IOSAPIC RTE index */
137 int refcnt; /* reference counter */
138 unsigned int flags; /* flags */
139 struct iosapic *iosapic;
140 } ____cacheline_aligned;
142 static struct iosapic_intr_info {
143 struct list_head rtes; /* RTEs using this vector (empty =>
144 * not an IOSAPIC interrupt) */
145 int count; /* # of RTEs that shares this vector */
146 u32 low32; /* current value of low word of
147 * Redirection table entry */
148 unsigned int dest; /* destination CPU physical ID */
149 unsigned char dmode : 3; /* delivery mode (see iosapic.h) */
150 unsigned char polarity: 1; /* interrupt polarity
152 unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
153 } iosapic_intr_info[NR_IRQS];
155 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
157 static int iosapic_kmalloc_ok;
158 static LIST_HEAD(free_rte_list);
161 iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
165 spin_lock_irqsave(&iosapic->lock, flags);
166 __iosapic_write(iosapic->addr, reg, val);
167 spin_unlock_irqrestore(&iosapic->lock, flags);
171 * Find an IOSAPIC associated with a GSI
174 find_iosapic (unsigned int gsi)
178 for (i = 0; i < NR_IOSAPICS; i++) {
179 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
180 iosapic_lists[i].num_rte)
187 static inline int __gsi_to_irq(unsigned int gsi)
190 struct iosapic_intr_info *info;
191 struct iosapic_rte_info *rte;
193 for (irq = 0; irq < NR_IRQS; irq++) {
194 info = &iosapic_intr_info[irq];
195 list_for_each_entry(rte, &info->rtes, rte_list)
196 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
203 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
204 * entry exists, return -1.
207 gsi_to_vector (unsigned int gsi)
209 int irq = __gsi_to_irq(gsi);
210 if (check_irq_used(irq) < 0)
212 return irq_to_vector(irq);
216 gsi_to_irq (unsigned int gsi)
221 spin_lock_irqsave(&iosapic_lock, flags);
222 irq = __gsi_to_irq(gsi);
223 spin_unlock_irqrestore(&iosapic_lock, flags);
227 static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi)
229 struct iosapic_rte_info *rte;
231 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
232 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
238 set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
240 unsigned long pol, trigger, dmode;
244 struct iosapic_rte_info *rte;
245 ia64_vector vector = irq_to_vector(irq);
247 DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
249 rte = find_rte(irq, gsi);
251 return; /* not an IOSAPIC interrupt */
253 rte_index = rte->rte_index;
254 pol = iosapic_intr_info[irq].polarity;
255 trigger = iosapic_intr_info[irq].trigger;
256 dmode = iosapic_intr_info[irq].dmode;
258 redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
261 set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
264 low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
265 (trigger << IOSAPIC_TRIGGER_SHIFT) |
266 (dmode << IOSAPIC_DELIVERY_SHIFT) |
267 ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
270 /* dest contains both id and eid */
271 high32 = (dest << IOSAPIC_DEST_SHIFT);
273 iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
274 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
275 iosapic_intr_info[irq].low32 = low32;
276 iosapic_intr_info[irq].dest = dest;
280 nop (unsigned int irq)
288 kexec_disable_iosapic(void)
290 struct iosapic_intr_info *info;
291 struct iosapic_rte_info *rte;
295 for (irq = 0; irq < NR_IRQS; irq++) {
296 info = &iosapic_intr_info[irq];
297 vec = irq_to_vector(irq);
298 list_for_each_entry(rte, &info->rtes,
300 iosapic_write(rte->iosapic,
301 IOSAPIC_RTE_LOW(rte->rte_index),
303 iosapic_eoi(rte->iosapic->addr, vec);
310 mask_irq (unsigned int irq)
314 struct iosapic_rte_info *rte;
316 if (list_empty(&iosapic_intr_info[irq].rtes))
317 return; /* not an IOSAPIC interrupt! */
319 /* set only the mask bit */
320 low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
321 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
322 rte_index = rte->rte_index;
323 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
328 unmask_irq (unsigned int irq)
332 struct iosapic_rte_info *rte;
334 if (list_empty(&iosapic_intr_info[irq].rtes))
335 return; /* not an IOSAPIC interrupt! */
337 low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK;
338 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
339 rte_index = rte->rte_index;
340 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
346 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
351 int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
352 struct iosapic_rte_info *rte;
353 struct iosapic *iosapic;
355 irq &= (~IA64_IRQ_REDIRECTED);
357 cpus_and(mask, mask, cpu_online_map);
358 if (cpus_empty(mask))
361 if (reassign_irq_vector(irq, first_cpu(mask)))
364 dest = cpu_physical_id(first_cpu(mask));
366 if (list_empty(&iosapic_intr_info[irq].rtes))
367 return; /* not an IOSAPIC interrupt */
369 set_irq_affinity_info(irq, dest, redir);
371 /* dest contains both id and eid */
372 high32 = dest << IOSAPIC_DEST_SHIFT;
374 low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
376 /* change delivery mode to lowest priority */
377 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
379 /* change delivery mode to fixed */
380 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
381 low32 &= IOSAPIC_VECTOR_MASK;
382 low32 |= irq_to_vector(irq);
384 iosapic_intr_info[irq].low32 = low32;
385 iosapic_intr_info[irq].dest = dest;
386 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
387 iosapic = rte->iosapic;
388 rte_index = rte->rte_index;
389 iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
390 iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
396 * Handlers for level-triggered interrupts.
400 iosapic_startup_level_irq (unsigned int irq)
407 iosapic_end_level_irq (unsigned int irq)
409 ia64_vector vec = irq_to_vector(irq);
410 struct iosapic_rte_info *rte;
411 int do_unmask_irq = 0;
413 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
418 list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
419 iosapic_eoi(rte->iosapic->addr, vec);
421 if (unlikely(do_unmask_irq)) {
422 move_masked_irq(irq);
427 #define iosapic_shutdown_level_irq mask_irq
428 #define iosapic_enable_level_irq unmask_irq
429 #define iosapic_disable_level_irq mask_irq
430 #define iosapic_ack_level_irq nop
432 struct irq_chip irq_type_iosapic_level = {
433 .name = "IO-SAPIC-level",
434 .startup = iosapic_startup_level_irq,
435 .shutdown = iosapic_shutdown_level_irq,
436 .enable = iosapic_enable_level_irq,
437 .disable = iosapic_disable_level_irq,
438 .ack = iosapic_ack_level_irq,
439 .end = iosapic_end_level_irq,
441 .unmask = unmask_irq,
442 .set_affinity = iosapic_set_affinity
446 * Handlers for edge-triggered interrupts.
450 iosapic_startup_edge_irq (unsigned int irq)
454 * IOSAPIC simply drops interrupts pended while the
455 * corresponding pin was masked, so we can't know if an
456 * interrupt is pending already. Let's hope not...
462 iosapic_ack_edge_irq (unsigned int irq)
464 irq_desc_t *idesc = irq_desc + irq;
466 move_native_irq(irq);
468 * Once we have recorded IRQ_PENDING already, we can mask the
469 * interrupt for real. This prevents IRQ storms from unhandled
472 if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
473 (IRQ_PENDING|IRQ_DISABLED))
477 #define iosapic_enable_edge_irq unmask_irq
478 #define iosapic_disable_edge_irq nop
479 #define iosapic_end_edge_irq nop
481 struct irq_chip irq_type_iosapic_edge = {
482 .name = "IO-SAPIC-edge",
483 .startup = iosapic_startup_edge_irq,
484 .shutdown = iosapic_disable_edge_irq,
485 .enable = iosapic_enable_edge_irq,
486 .disable = iosapic_disable_edge_irq,
487 .ack = iosapic_ack_edge_irq,
488 .end = iosapic_end_edge_irq,
490 .unmask = unmask_irq,
491 .set_affinity = iosapic_set_affinity
495 iosapic_version (char __iomem *addr)
498 * IOSAPIC Version Register return 32 bit structure like:
500 * unsigned int version : 8;
501 * unsigned int reserved1 : 8;
502 * unsigned int max_redir : 8;
503 * unsigned int reserved2 : 8;
506 return __iosapic_read(addr, IOSAPIC_VERSION);
509 static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
511 int i, irq = -ENOSPC, min_count = -1;
512 struct iosapic_intr_info *info;
515 * shared vectors for edge-triggered interrupts are not
518 if (trigger == IOSAPIC_EDGE)
521 for (i = 0; i <= NR_IRQS; i++) {
522 info = &iosapic_intr_info[i];
523 if (info->trigger == trigger && info->polarity == pol &&
524 (info->dmode == IOSAPIC_FIXED ||
525 info->dmode == IOSAPIC_LOWEST_PRIORITY) &&
526 can_request_irq(i, IRQF_SHARED)) {
527 if (min_count == -1 || info->count < min_count) {
529 min_count = info->count;
537 * if the given vector is already owned by other,
538 * assign a new vector for the other and make the vector available
541 iosapic_reassign_vector (int irq)
545 if (!list_empty(&iosapic_intr_info[irq].rtes)) {
546 new_irq = create_irq();
548 panic("%s: out of interrupt vectors!\n", __FUNCTION__);
549 printk(KERN_INFO "Reassigning vector %d to %d\n",
550 irq_to_vector(irq), irq_to_vector(new_irq));
551 memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq],
552 sizeof(struct iosapic_intr_info));
553 INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes);
554 list_move(iosapic_intr_info[irq].rtes.next,
555 &iosapic_intr_info[new_irq].rtes);
556 memset(&iosapic_intr_info[irq], 0,
557 sizeof(struct iosapic_intr_info));
558 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
559 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
563 static struct iosapic_rte_info *iosapic_alloc_rte (void)
566 struct iosapic_rte_info *rte;
567 int preallocated = 0;
569 if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
570 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
571 NR_PREALLOCATE_RTE_ENTRIES);
574 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
575 list_add(&rte->rte_list, &free_rte_list);
578 if (!list_empty(&free_rte_list)) {
579 rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
581 list_del(&rte->rte_list);
584 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
589 memset(rte, 0, sizeof(struct iosapic_rte_info));
591 rte->flags |= RTE_PREALLOCATED;
596 static void iosapic_free_rte (struct iosapic_rte_info *rte)
598 if (rte->flags & RTE_PREALLOCATED)
599 list_add_tail(&rte->rte_list, &free_rte_list);
604 static inline int irq_is_shared (int irq)
606 return (iosapic_intr_info[irq].count > 1);
610 register_intr (unsigned int gsi, int irq, unsigned char delivery,
611 unsigned long polarity, unsigned long trigger)
614 struct hw_interrupt_type *irq_type;
616 struct iosapic_rte_info *rte;
618 index = find_iosapic(gsi);
620 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
625 rte = find_rte(irq, gsi);
627 rte = iosapic_alloc_rte();
629 printk(KERN_WARNING "%s: cannot allocate memory\n",
634 rte->iosapic = &iosapic_lists[index];
635 rte->rte_index = gsi - rte->iosapic->gsi_base;
637 list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes);
638 iosapic_intr_info[irq].count++;
639 iosapic_lists[index].rtes_inuse++;
641 else if (rte->refcnt == NO_REF_RTE) {
642 struct iosapic_intr_info *info = &iosapic_intr_info[irq];
643 if (info->count > 0 &&
644 (info->trigger != trigger || info->polarity != polarity)){
646 "%s: cannot override the interrupt\n",
651 iosapic_intr_info[irq].count++;
652 iosapic_lists[index].rtes_inuse++;
655 iosapic_intr_info[irq].polarity = polarity;
656 iosapic_intr_info[irq].dmode = delivery;
657 iosapic_intr_info[irq].trigger = trigger;
659 if (trigger == IOSAPIC_EDGE)
660 irq_type = &irq_type_iosapic_edge;
662 irq_type = &irq_type_iosapic_level;
664 idesc = irq_desc + irq;
665 if (idesc->chip != irq_type) {
666 if (idesc->chip != &no_irq_type)
668 "%s: changing vector %d from %s to %s\n",
669 __FUNCTION__, irq_to_vector(irq),
670 idesc->chip->name, irq_type->name);
671 idesc->chip = irq_type;
677 get_target_cpu (unsigned int gsi, int irq)
681 extern int cpe_vector;
682 cpumask_t domain = irq_to_domain(irq);
685 * In case of vector shared by multiple RTEs, all RTEs that
686 * share the vector need to use the same destination CPU.
688 if (!list_empty(&iosapic_intr_info[irq].rtes))
689 return iosapic_intr_info[irq].dest;
692 * If the platform supports redirection via XTP, let it
693 * distribute interrupts.
695 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
696 return cpu_physical_id(smp_processor_id());
699 * Some interrupts (ACPI SCI, for instance) are registered
700 * before the BSP is marked as online.
702 if (!cpu_online(smp_processor_id()))
703 return cpu_physical_id(smp_processor_id());
706 if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR)
707 return get_cpei_target_cpu();
712 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
715 iosapic_index = find_iosapic(gsi);
716 if (iosapic_index < 0 ||
717 iosapic_lists[iosapic_index].node == MAX_NUMNODES)
718 goto skip_numa_setup;
720 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
721 cpus_and(cpu_mask, cpu_mask, domain);
722 for_each_cpu_mask(numa_cpu, cpu_mask) {
723 if (!cpu_online(numa_cpu))
724 cpu_clear(numa_cpu, cpu_mask);
727 num_cpus = cpus_weight(cpu_mask);
730 goto skip_numa_setup;
732 /* Use irq assignment to distribute across cpus in node */
733 cpu_index = irq % num_cpus;
735 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
736 numa_cpu = next_cpu(numa_cpu, cpu_mask);
738 if (numa_cpu != NR_CPUS)
739 return cpu_physical_id(numa_cpu);
744 * Otherwise, round-robin interrupt vectors across all the
745 * processors. (It'd be nice if we could be smarter in the
749 if (++cpu >= NR_CPUS)
751 } while (!cpu_online(cpu) || !cpu_isset(cpu, domain));
753 return cpu_physical_id(cpu);
754 #else /* CONFIG_SMP */
755 return cpu_physical_id(smp_processor_id());
760 * ACPI can describe IOSAPIC interrupts via static tables and namespace
761 * methods. This provides an interface to register those interrupts and
762 * program the IOSAPIC RTE.
765 iosapic_register_intr (unsigned int gsi,
766 unsigned long polarity, unsigned long trigger)
768 int irq, mask = 1, err;
771 struct iosapic_rte_info *rte;
775 * If this GSI has already been registered (i.e., it's a
776 * shared interrupt, or we lost a race to register it),
777 * don't touch the RTE.
779 spin_lock_irqsave(&iosapic_lock, flags);
780 irq = __gsi_to_irq(gsi);
782 rte = find_rte(irq, gsi);
783 if(iosapic_intr_info[irq].count == 0) {
784 assign_irq_vector(irq);
785 dynamic_irq_init(irq);
786 } else if (rte->refcnt != NO_REF_RTE) {
788 goto unlock_iosapic_lock;
793 /* If vector is running out, we try to find a sharable vector */
795 irq = iosapic_find_sharable_irq(trigger, polarity);
797 goto unlock_iosapic_lock;
800 spin_lock(&irq_desc[irq].lock);
801 dest = get_target_cpu(gsi, irq);
802 err = register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY,
810 * If the vector is shared and already unmasked for other
811 * interrupt sources, don't mask it.
813 low32 = iosapic_intr_info[irq].low32;
814 if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK))
816 set_rte(gsi, irq, dest, mask);
818 printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
819 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
820 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
821 cpu_logical_id(dest), dest, irq_to_vector(irq));
823 spin_unlock(&irq_desc[irq].lock);
825 spin_unlock_irqrestore(&iosapic_lock, flags);
830 iosapic_unregister_intr (unsigned int gsi)
836 unsigned long trigger, polarity;
838 struct iosapic_rte_info *rte;
841 * If the irq associated with the gsi is not found,
842 * iosapic_unregister_intr() is unbalanced. We need to check
843 * this again after getting locks.
845 irq = gsi_to_irq(gsi);
847 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
853 spin_lock_irqsave(&iosapic_lock, flags);
854 if ((rte = find_rte(irq, gsi)) == NULL) {
855 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
861 if (--rte->refcnt > 0)
864 idesc = irq_desc + irq;
865 rte->refcnt = NO_REF_RTE;
867 /* Mask the interrupt */
868 low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK;
869 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32);
871 iosapic_intr_info[irq].count--;
872 index = find_iosapic(gsi);
873 iosapic_lists[index].rtes_inuse--;
874 WARN_ON(iosapic_lists[index].rtes_inuse < 0);
876 trigger = iosapic_intr_info[irq].trigger;
877 polarity = iosapic_intr_info[irq].polarity;
878 dest = iosapic_intr_info[irq].dest;
880 "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
881 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
882 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
883 cpu_logical_id(dest), dest, irq_to_vector(irq));
885 if (iosapic_intr_info[irq].count == 0) {
888 cpus_setall(idesc->affinity);
890 /* Clear the interrupt information */
891 iosapic_intr_info[irq].dest = 0;
892 iosapic_intr_info[irq].dmode = 0;
893 iosapic_intr_info[irq].polarity = 0;
894 iosapic_intr_info[irq].trigger = 0;
895 iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
897 /* Destroy and reserve IRQ */
898 destroy_and_reserve_irq(irq);
901 spin_unlock_irqrestore(&iosapic_lock, flags);
905 * ACPI calls this when it finds an entry for a platform interrupt.
908 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
909 int iosapic_vector, u16 eid, u16 id,
910 unsigned long polarity, unsigned long trigger)
912 static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
913 unsigned char delivery;
914 int irq, vector, mask = 0;
915 unsigned int dest = ((id << 8) | eid) & 0xffff;
918 case ACPI_INTERRUPT_PMI:
919 irq = vector = iosapic_vector;
920 bind_irq_vector(irq, vector, CPU_MASK_ALL);
922 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
923 * we need to make sure the vector is available
925 iosapic_reassign_vector(irq);
926 delivery = IOSAPIC_PMI;
928 case ACPI_INTERRUPT_INIT:
931 panic("%s: out of interrupt vectors!\n", __FUNCTION__);
932 vector = irq_to_vector(irq);
933 delivery = IOSAPIC_INIT;
935 case ACPI_INTERRUPT_CPEI:
936 irq = vector = IA64_CPE_VECTOR;
937 BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
938 delivery = IOSAPIC_LOWEST_PRIORITY;
942 printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__,
947 register_intr(gsi, irq, delivery, polarity, trigger);
950 "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
952 int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
953 int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
954 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
955 cpu_logical_id(dest), dest, vector);
957 set_rte(gsi, irq, dest, mask);
962 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
965 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
966 unsigned long polarity,
967 unsigned long trigger)
970 unsigned int dest = cpu_physical_id(smp_processor_id());
972 irq = vector = isa_irq_to_vector(isa_irq);
973 BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
974 register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
976 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
977 isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
978 polarity == IOSAPIC_POL_HIGH ? "high" : "low",
979 cpu_logical_id(dest), dest, vector);
981 set_rte(gsi, irq, dest, 1);
985 iosapic_system_init (int system_pcat_compat)
989 for (irq = 0; irq < NR_IRQS; ++irq) {
990 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
992 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
994 iosapic_intr_info[irq].count = 0;
997 pcat_compat = system_pcat_compat;
1000 * Disable the compatibility mode interrupts (8259 style),
1001 * needs IN/OUT support enabled.
1004 "%s: Disabling PC-AT compatible 8259 interrupts\n",
1012 iosapic_alloc (void)
1016 for (index = 0; index < NR_IOSAPICS; index++)
1017 if (!iosapic_lists[index].addr)
1020 printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__);
1025 iosapic_free (int index)
1027 memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
1031 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1034 unsigned int gsi_end, base, end;
1036 /* check gsi range */
1037 gsi_end = gsi_base + ((ver >> 16) & 0xff);
1038 for (index = 0; index < NR_IOSAPICS; index++) {
1039 if (!iosapic_lists[index].addr)
1042 base = iosapic_lists[index].gsi_base;
1043 end = base + iosapic_lists[index].num_rte - 1;
1045 if (gsi_end < base || end < gsi_base)
1054 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1056 int num_rte, err, index;
1057 unsigned int isa_irq, ver;
1059 unsigned long flags;
1061 spin_lock_irqsave(&iosapic_lock, flags);
1062 index = find_iosapic(gsi_base);
1064 spin_unlock_irqrestore(&iosapic_lock, flags);
1068 addr = ioremap(phys_addr, 0);
1069 ver = iosapic_version(addr);
1070 if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1072 spin_unlock_irqrestore(&iosapic_lock, flags);
1077 * The MAX_REDIR register holds the highest input pin number
1078 * (starting from 0). We add 1 so that we can use it for
1079 * number of pins (= RTEs)
1081 num_rte = ((ver >> 16) & 0xff) + 1;
1083 index = iosapic_alloc();
1084 iosapic_lists[index].addr = addr;
1085 iosapic_lists[index].gsi_base = gsi_base;
1086 iosapic_lists[index].num_rte = num_rte;
1088 iosapic_lists[index].node = MAX_NUMNODES;
1090 spin_lock_init(&iosapic_lists[index].lock);
1091 spin_unlock_irqrestore(&iosapic_lock, flags);
1093 if ((gsi_base == 0) && pcat_compat) {
1095 * Map the legacy ISA devices into the IOSAPIC data. Some of
1096 * these may get reprogrammed later on with data from the ACPI
1097 * Interrupt Source Override table.
1099 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1100 iosapic_override_isa_irq(isa_irq, isa_irq,
1107 #ifdef CONFIG_HOTPLUG
1109 iosapic_remove (unsigned int gsi_base)
1112 unsigned long flags;
1114 spin_lock_irqsave(&iosapic_lock, flags);
1115 index = find_iosapic(gsi_base);
1117 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1118 __FUNCTION__, gsi_base);
1122 if (iosapic_lists[index].rtes_inuse) {
1124 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1125 __FUNCTION__, gsi_base);
1129 iounmap(iosapic_lists[index].addr);
1130 iosapic_free(index);
1132 spin_unlock_irqrestore(&iosapic_lock, flags);
1135 #endif /* CONFIG_HOTPLUG */
1139 map_iosapic_to_node(unsigned int gsi_base, int node)
1143 index = find_iosapic(gsi_base);
1145 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1146 __FUNCTION__, gsi_base);
1149 iosapic_lists[index].node = node;
1154 static int __init iosapic_enable_kmalloc (void)
1156 iosapic_kmalloc_ok = 1;
1159 core_initcall (iosapic_enable_kmalloc);