drivers/gpu/drm/radeon/radeon_uvd.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Christian König <deathsimple@vodafone.de>
  29  */
  30
  31 #include <linux/firmware.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35
  36 #include "radeon.h"
  37 #include "r600d.h"
  38
  39 /* 1 second timeout */
  40 #define UVD_IDLE_TIMEOUT_MS     1000
  41
  42 /* Firmware Names */
  43 #define FIRMWARE_RV710          "radeon/RV710_uvd.bin"
  44 #define FIRMWARE_CYPRESS        "radeon/CYPRESS_uvd.bin"
  45 #define FIRMWARE_SUMO           "radeon/SUMO_uvd.bin"
  46 #define FIRMWARE_TAHITI         "radeon/TAHITI_uvd.bin"
  47 #define FIRMWARE_BONAIRE        "radeon/BONAIRE_uvd.bin"
  48
  49 MODULE_FIRMWARE(FIRMWARE_RV710);
  50 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
  51 MODULE_FIRMWARE(FIRMWARE_SUMO);
  52 MODULE_FIRMWARE(FIRMWARE_TAHITI);
  53 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
  54
  55 static void radeon_uvd_idle_work_handler(struct work_struct *work);
  56
  57 int radeon_uvd_init(struct radeon_device *rdev)
  58 {
  59         unsigned long bo_size;
  60         const char *fw_name;
  61         int i, r;
  62
  63         INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
  64
  65         switch (rdev->family) {
  66         case CHIP_RV710:
  67         case CHIP_RV730:
  68         case CHIP_RV740:
  69                 fw_name = FIRMWARE_RV710;
  70                 break;
  71
  72         case CHIP_CYPRESS:
  73         case CHIP_HEMLOCK:
  74         case CHIP_JUNIPER:
  75         case CHIP_REDWOOD:
  76         case CHIP_CEDAR:
  77                 fw_name = FIRMWARE_CYPRESS;
  78                 break;
  79
  80         case CHIP_SUMO:
  81         case CHIP_SUMO2:
  82         case CHIP_PALM:
  83         case CHIP_CAYMAN:
  84         case CHIP_BARTS:
  85         case CHIP_TURKS:
  86         case CHIP_CAICOS:
  87                 fw_name = FIRMWARE_SUMO;
  88                 break;
  89
  90         case CHIP_TAHITI:
  91         case CHIP_VERDE:
  92         case CHIP_PITCAIRN:
  93         case CHIP_ARUBA:
  94                 fw_name = FIRMWARE_TAHITI;
  95                 break;
  96
  97         case CHIP_BONAIRE:
  98         case CHIP_KABINI:
  99         case CHIP_KAVERI:
 100                 fw_name = FIRMWARE_BONAIRE;
 101                 break;
 102
 103         default:
 104                 return -EINVAL;
 105         }
 106
 107         r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
 108         if (r) {
 109                 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
 110                         fw_name);
 111                 return r;
 112         }
 113
 114         bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
 115                   RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
 116         r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
 117                              RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
 118         if (r) {
 119                 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
 120                 return r;
 121         }
 122
 123         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 124         if (r) {
 125                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 126                 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
 127                 return r;
 128         }
 129
 130         r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
 131                           &rdev->uvd.gpu_addr);
 132         if (r) {
 133                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 134                 radeon_bo_unref(&rdev->uvd.vcpu_bo);
 135                 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
 136                 return r;
 137         }
 138
 139         r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
 140         if (r) {
 141                 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
 142                 return r;
 143         }
 144
 145         radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 146
 147         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 148                 atomic_set(&rdev->uvd.handles[i], 0);
 149                 rdev->uvd.filp[i] = NULL;
 150         }
 151
 152         return 0;
 153 }
 154
 155 void radeon_uvd_fini(struct radeon_device *rdev)
 156 {
 157         int r;
 158
 159         if (rdev->uvd.vcpu_bo == NULL)
 160                 return;
 161
 162         r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
 163         if (!r) {
 164                 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
 165                 radeon_bo_unpin(rdev->uvd.vcpu_bo);
 166                 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
 167         }
 168
 169         radeon_bo_unref(&rdev->uvd.vcpu_bo);
 170
 171         release_firmware(rdev->uvd_fw);
 172 }
 173
 174 int radeon_uvd_suspend(struct radeon_device *rdev)
 175 {
 176         unsigned size;
 177         void *ptr;
 178         int i;
 179
 180         if (rdev->uvd.vcpu_bo == NULL)
 181                 return 0;
 182
 183         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 184                 if (atomic_read(&rdev->uvd.handles[i]))
 185                         break;
 186
 187         if (i == RADEON_MAX_UVD_HANDLES)
 188                 return 0;
 189
 190         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 191         size -= rdev->uvd_fw->size;
 192
 193         ptr = rdev->uvd.cpu_addr;
 194         ptr += rdev->uvd_fw->size;
 195
 196         rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
 197         memcpy(rdev->uvd.saved_bo, ptr, size);
 198
 199         return 0;
 200 }
 201
 202 int radeon_uvd_resume(struct radeon_device *rdev)
 203 {
 204         unsigned size;
 205         void *ptr;
 206
 207         if (rdev->uvd.vcpu_bo == NULL)
 208                 return -EINVAL;
 209
 210         memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 211
 212         size = radeon_bo_size(rdev->uvd.vcpu_bo);
 213         size -= rdev->uvd_fw->size;
 214
 215         ptr = rdev->uvd.cpu_addr;
 216         ptr += rdev->uvd_fw->size;
 217
 218         if (rdev->uvd.saved_bo != NULL) {
 219                 memcpy(ptr, rdev->uvd.saved_bo, size);
 220                 kfree(rdev->uvd.saved_bo);
 221                 rdev->uvd.saved_bo = NULL;
 222         } else
 223                 memset(ptr, 0, size);
 224
 225         return 0;
 226 }
 227
 228 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
 229 {
 230         rbo->placement.fpfn = 0 >> PAGE_SHIFT;
 231         rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 232 }
 233
 234 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 235 {
 236         int i, r;
 237         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 238                 if (rdev->uvd.filp[i] == filp) {
 239                         uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
 240                         struct radeon_fence *fence;
 241
 242                         r = radeon_uvd_get_destroy_msg(rdev,
 243                                 R600_RING_TYPE_UVD_INDEX, handle, &fence);
 244                         if (r) {
 245                                 DRM_ERROR("Error destroying UVD (%d)!\n", r);
 246                                 continue;
 247                         }
 248
 249                         radeon_fence_wait(fence, false);
 250                         radeon_fence_unref(&fence);
 251
 252                         rdev->uvd.filp[i] = NULL;
 253                         atomic_set(&rdev->uvd.handles[i], 0);
 254                 }
 255         }
 256 }
 257
 258 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
 259 {
 260         unsigned stream_type = msg[4];
 261         unsigned width = msg[6];
 262         unsigned height = msg[7];
 263         unsigned dpb_size = msg[9];
 264         unsigned pitch = msg[28];
 265
 266         unsigned width_in_mb = width / 16;
 267         unsigned height_in_mb = ALIGN(height / 16, 2);
 268
 269         unsigned image_size, tmp, min_dpb_size;
 270
 271         image_size = width * height;
 272         image_size += image_size / 2;
 273         image_size = ALIGN(image_size, 1024);
 274
 275         switch (stream_type) {
 276         case 0: /* H264 */
 277
 278                 /* reference picture buffer */
 279                 min_dpb_size = image_size * 17;
 280
 281                 /* macroblock context buffer */
 282                 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
 283
 284                 /* IT surface buffer */
 285                 min_dpb_size += width_in_mb * height_in_mb * 32;
 286                 break;
 287
 288         case 1: /* VC1 */
 289
 290                 /* reference picture buffer */
 291                 min_dpb_size = image_size * 3;
 292
 293                 /* CONTEXT_BUFFER */
 294                 min_dpb_size += width_in_mb * height_in_mb * 128;
 295
 296                 /* IT surface buffer */
 297                 min_dpb_size += width_in_mb * 64;
 298
 299                 /* DB surface buffer */
 300                 min_dpb_size += width_in_mb * 128;
 301
 302                 /* BP */
 303                 tmp = max(width_in_mb, height_in_mb);
 304                 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
 305                 break;
 306
 307         case 3: /* MPEG2 */
 308
 309                 /* reference picture buffer */
 310                 min_dpb_size = image_size * 3;
 311                 break;
 312
 313         case 4: /* MPEG4 */
 314
 315                 /* reference picture buffer */
 316                 min_dpb_size = image_size * 3;
 317
 318                 /* CM */
 319                 min_dpb_size += width_in_mb * height_in_mb * 64;
 320
 321                 /* IT surface buffer */
 322                 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
 323                 break;
 324
 325         default:
 326                 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
 327                 return -EINVAL;
 328         }
 329
 330         if (width > pitch) {
 331                 DRM_ERROR("Invalid UVD decoding target pitch!\n");
 332                 return -EINVAL;
 333         }
 334
 335         if (dpb_size < min_dpb_size) {
 336                 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
 337                           dpb_size, min_dpb_size);
 338                 return -EINVAL;
 339         }
 340
 341         buf_sizes[0x1] = dpb_size;
 342         buf_sizes[0x2] = image_size;
 343         return 0;
 344 }
 345
 346 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
 347                              unsigned offset, unsigned buf_sizes[])
 348 {
 349         int32_t *msg, msg_type, handle;
 350         void *ptr;
 351
 352         int i, r;
 353
 354         if (offset & 0x3F) {
 355                 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
 356                 return -EINVAL;
 357         }
 358
 359         r = radeon_bo_kmap(bo, &ptr);
 360         if (r)
 361                 return r;
 362
 363         msg = ptr + offset;
 364
 365         msg_type = msg[1];
 366         handle = msg[2];
 367
 368         if (handle == 0) {
 369                 DRM_ERROR("Invalid UVD handle!\n");
 370                 return -EINVAL;
 371         }
 372
 373         if (msg_type == 1) {
 374                 /* it's a decode msg, calc buffer sizes */
 375                 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
 376                 radeon_bo_kunmap(bo);
 377                 if (r)
 378                         return r;
 379
 380         } else if (msg_type == 2) {
 381                 /* it's a destroy msg, free the handle */
 382                 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
 383                         atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
 384                 radeon_bo_kunmap(bo);
 385                 return 0;
 386         } else {
 387                 /* it's a create msg, no special handling needed */
 388                 radeon_bo_kunmap(bo);
 389         }
 390
 391         /* create or decode, validate the handle */
 392         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 393                 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
 394                         return 0;
 395         }
 396
 397         /* handle not found try to alloc a new one */
 398         for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
 399                 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
 400                         p->rdev->uvd.filp[i] = p->filp;
 401                         return 0;
 402                 }
 403         }
 404
 405         DRM_ERROR("No more free UVD handles!\n");
 406         return -EINVAL;
 407 }
 408
 409 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
 410                                int data0, int data1,
 411                                unsigned buf_sizes[])
 412 {
 413         struct radeon_cs_chunk *relocs_chunk;
 414         struct radeon_cs_reloc *reloc;
 415         unsigned idx, cmd, offset;
 416         uint64_t start, end;
 417         int r;
 418
 419         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 420         offset = radeon_get_ib_value(p, data0);
 421         idx = radeon_get_ib_value(p, data1);
 422         if (idx >= relocs_chunk->length_dw) {
 423                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 424                           idx, relocs_chunk->length_dw);
 425                 return -EINVAL;
 426         }
 427
 428         reloc = p->relocs_ptr[(idx / 4)];
 429         start = reloc->lobj.gpu_offset;
 430         end = start + radeon_bo_size(reloc->robj);
 431         start += offset;
 432
 433         p->ib.ptr[data0] = start & 0xFFFFFFFF;
 434         p->ib.ptr[data1] = start >> 32;
 435
 436         cmd = radeon_get_ib_value(p, p->idx) >> 1;
 437
 438         if (cmd < 0x4) {
 439                 if ((end - start) < buf_sizes[cmd]) {
 440                         DRM_ERROR("buffer to small (%d / %d)!\n",
 441                                   (unsigned)(end - start), buf_sizes[cmd]);
 442                         return -EINVAL;
 443                 }
 444
 445         } else if (cmd != 0x100) {
 446                 DRM_ERROR("invalid UVD command %X!\n", cmd);
 447                 return -EINVAL;
 448         }
 449
 450         if ((start >> 28) != (end >> 28)) {
 451                 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
 452                           start, end);
 453                 return -EINVAL;
 454         }
 455
 456         /* TODO: is this still necessary on NI+ ? */
 457         if ((cmd == 0 || cmd == 0x3) &&
 458             (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
 459                 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
 460                           start, end);
 461                 return -EINVAL;
 462         }
 463
 464         if (cmd == 0) {
 465                 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
 466                 if (r)
 467                         return r;
 468         }
 469
 470         return 0;
 471 }
 472
 473 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
 474                              struct radeon_cs_packet *pkt,
 475                              int *data0, int *data1,
 476                              unsigned buf_sizes[])
 477 {
 478         int i, r;
 479
 480         p->idx++;
 481         for (i = 0; i <= pkt->count; ++i) {
 482                 switch (pkt->reg + i*4) {
 483                 case UVD_GPCOM_VCPU_DATA0:
 484                         *data0 = p->idx;
 485                         break;
 486                 case UVD_GPCOM_VCPU_DATA1:
 487                         *data1 = p->idx;
 488                         break;
 489                 case UVD_GPCOM_VCPU_CMD:
 490                         r = radeon_uvd_cs_reloc(p, *data0, *data1, buf_sizes);
 491                         if (r)
 492                                 return r;
 493                         break;
 494                 case UVD_ENGINE_CNTL:
 495                         break;
 496                 default:
 497                         DRM_ERROR("Invalid reg 0x%X!\n",
 498                                   pkt->reg + i*4);
 499                         return -EINVAL;
 500                 }
 501                 p->idx++;
 502         }
 503         return 0;
 504 }
 505
 506 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
 507 {
 508         struct radeon_cs_packet pkt;
 509         int r, data0 = 0, data1 = 0;
 510
 511         /* minimum buffer sizes */
 512         unsigned buf_sizes[] = {
 513                 [0x00000000]    =       2048,
 514                 [0x00000001]    =       32 * 1024 * 1024,
 515                 [0x00000002]    =       2048 * 1152 * 3,
 516                 [0x00000003]    =       2048,
 517         };
 518
 519         if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
 520                 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
 521                           p->chunks[p->chunk_ib_idx].length_dw);
 522                 return -EINVAL;
 523         }
 524
 525         if (p->chunk_relocs_idx == -1) {
 526                 DRM_ERROR("No relocation chunk !\n");
 527                 return -EINVAL;
 528         }
 529
 530
 531         do {
 532                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
 533                 if (r)
 534                         return r;
 535                 switch (pkt.type) {
 536                 case RADEON_PACKET_TYPE0:
 537                         r = radeon_uvd_cs_reg(p, &pkt, &data0,
 538                                               &data1, buf_sizes);
 539                         if (r)
 540                                 return r;
 541                         break;
 542                 case RADEON_PACKET_TYPE2:
 543                         p->idx += pkt.count + 2;
 544                         break;
 545                 default:
 546                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
 547                         return -EINVAL;
 548                 }
 549         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
 550         return 0;
 551 }
 552
 553 static int radeon_uvd_send_msg(struct radeon_device *rdev,
 554                                int ring, struct radeon_bo *bo,
 555                                struct radeon_fence **fence)
 556 {
 557         struct ttm_validate_buffer tv;
 558         struct ww_acquire_ctx ticket;
 559         struct list_head head;
 560         struct radeon_ib ib;
 561         uint64_t addr;
 562         int i, r;
 563
 564         memset(&tv, 0, sizeof(tv));
 565         tv.bo = &bo->tbo;
 566
 567         INIT_LIST_HEAD(&head);
 568         list_add(&tv.head, &head);
 569
 570         r = ttm_eu_reserve_buffers(&ticket, &head);
 571         if (r)
 572                 return r;
 573
 574         radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_VRAM);
 575         radeon_uvd_force_into_uvd_segment(bo);
 576
 577         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 578         if (r)
 579                 goto err;
 580
 581         r = radeon_ib_get(rdev, ring, &ib, NULL, 16);
 582         if (r)
 583                 goto err;
 584
 585         addr = radeon_bo_gpu_offset(bo);
 586         ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
 587         ib.ptr[1] = addr;
 588         ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
 589         ib.ptr[3] = addr >> 32;
 590         ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
 591         ib.ptr[5] = 0;
 592         for (i = 6; i < 16; ++i)
 593                 ib.ptr[i] = PACKET2(0);
 594         ib.length_dw = 16;
 595
 596         r = radeon_ib_schedule(rdev, &ib, NULL);
 597         if (r)
 598                 goto err;
 599         ttm_eu_fence_buffer_objects(&ticket, &head, ib.fence);
 600
 601         if (fence)
 602                 *fence = radeon_fence_ref(ib.fence);
 603
 604         radeon_ib_free(rdev, &ib);
 605         radeon_bo_unref(&bo);
 606         return 0;
 607
 608 err:
 609         ttm_eu_backoff_reservation(&ticket, &head);
 610         return r;
 611 }
 612
 613 /* multiple fence commands without any stream commands in between can
 614    crash the vcpu so just try to emmit a dummy create/destroy msg to
 615    avoid this */
 616 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 617                               uint32_t handle, struct radeon_fence **fence)
 618 {
 619         struct radeon_bo *bo;
 620         uint32_t *msg;
 621         int r, i;
 622
 623         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 624                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 625         if (r)
 626                 return r;
 627
 628         r = radeon_bo_reserve(bo, false);
 629         if (r) {
 630                 radeon_bo_unref(&bo);
 631                 return r;
 632         }
 633
 634         r = radeon_bo_kmap(bo, (void **)&msg);
 635         if (r) {
 636                 radeon_bo_unreserve(bo);
 637                 radeon_bo_unref(&bo);
 638                 return r;
 639         }
 640
 641         /* stitch together an UVD create msg */
 642         msg[0] = cpu_to_le32(0x00000de4);
 643         msg[1] = cpu_to_le32(0x00000000);
 644         msg[2] = cpu_to_le32(handle);
 645         msg[3] = cpu_to_le32(0x00000000);
 646         msg[4] = cpu_to_le32(0x00000000);
 647         msg[5] = cpu_to_le32(0x00000000);
 648         msg[6] = cpu_to_le32(0x00000000);
 649         msg[7] = cpu_to_le32(0x00000780);
 650         msg[8] = cpu_to_le32(0x00000440);
 651         msg[9] = cpu_to_le32(0x00000000);
 652         msg[10] = cpu_to_le32(0x01b37000);
 653         for (i = 11; i < 1024; ++i)
 654                 msg[i] = cpu_to_le32(0x0);
 655
 656         radeon_bo_kunmap(bo);
 657         radeon_bo_unreserve(bo);
 658
 659         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 660 }
 661
 662 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 663                                uint32_t handle, struct radeon_fence **fence)
 664 {
 665         struct radeon_bo *bo;
 666         uint32_t *msg;
 667         int r, i;
 668
 669         r = radeon_bo_create(rdev, 1024, PAGE_SIZE, true,
 670                              RADEON_GEM_DOMAIN_VRAM, NULL, &bo);
 671         if (r)
 672                 return r;
 673
 674         r = radeon_bo_reserve(bo, false);
 675         if (r) {
 676                 radeon_bo_unref(&bo);
 677                 return r;
 678         }
 679
 680         r = radeon_bo_kmap(bo, (void **)&msg);
 681         if (r) {
 682                 radeon_bo_unreserve(bo);
 683                 radeon_bo_unref(&bo);
 684                 return r;
 685         }
 686
 687         /* stitch together an UVD destroy msg */
 688         msg[0] = cpu_to_le32(0x00000de4);
 689         msg[1] = cpu_to_le32(0x00000002);
 690         msg[2] = cpu_to_le32(handle);
 691         msg[3] = cpu_to_le32(0x00000000);
 692         for (i = 4; i < 1024; ++i)
 693                 msg[i] = cpu_to_le32(0x0);
 694
 695         radeon_bo_kunmap(bo);
 696         radeon_bo_unreserve(bo);
 697
 698         return radeon_uvd_send_msg(rdev, ring, bo, fence);
 699 }
 700
 701 static void radeon_uvd_idle_work_handler(struct work_struct *work)
 702 {
 703         struct radeon_device *rdev =
 704                 container_of(work, struct radeon_device, uvd.idle_work.work);
 705
 706         if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
 707                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 708                         mutex_lock(&rdev->pm.mutex);
 709                         rdev->pm.dpm.uvd_active = false;
 710                         mutex_unlock(&rdev->pm.mutex);
 711                         radeon_pm_compute_clocks(rdev);
 712                 } else {
 713                         radeon_set_uvd_clocks(rdev, 0, 0);
 714                 }
 715         } else {
 716                 schedule_delayed_work(&rdev->uvd.idle_work,
 717                                       msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 718         }
 719 }
 720
 721 void radeon_uvd_note_usage(struct radeon_device *rdev)
 722 {
 723         bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
 724         set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
 725                                             msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
 726         if (set_clocks) {
 727                 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
 728                         /* XXX pick SD/HD/MVC */
 729                         radeon_dpm_enable_power_state(rdev, POWER_STATE_TYPE_INTERNAL_UVD);
 730                 } else {
 731                         radeon_set_uvd_clocks(rdev, 53300, 40000);
 732                 }
 733         }
 734 }
 735
 736 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
 737                                               unsigned target_freq,
 738                                               unsigned pd_min,
 739                                               unsigned pd_even)
 740 {
 741         unsigned post_div = vco_freq / target_freq;
 742
 743         /* adjust to post divider minimum value */
 744         if (post_div < pd_min)
 745                 post_div = pd_min;
 746
 747         /* we alway need a frequency less than or equal the target */
 748         if ((vco_freq / post_div) > target_freq)
 749                 post_div += 1;
 750
 751         /* post dividers above a certain value must be even */
 752         if (post_div > pd_even && post_div % 2)
 753                 post_div += 1;
 754
 755         return post_div;
 756 }
 757
 758 /**
 759  * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
 760  *
 761  * @rdev: radeon_device pointer
 762  * @vclk: wanted VCLK
 763  * @dclk: wanted DCLK
 764  * @vco_min: minimum VCO frequency
 765  * @vco_max: maximum VCO frequency
 766  * @fb_factor: factor to multiply vco freq with
 767  * @fb_mask: limit and bitmask for feedback divider
 768  * @pd_min: post divider minimum
 769  * @pd_max: post divider maximum
 770  * @pd_even: post divider must be even above this value
 771  * @optimal_fb_div: resulting feedback divider
 772  * @optimal_vclk_div: resulting vclk post divider
 773  * @optimal_dclk_div: resulting dclk post divider
 774  *
 775  * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
 776  * Returns zero on success -EINVAL on error.
 777  */
 778 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
 779                                   unsigned vclk, unsigned dclk,
 780                                   unsigned vco_min, unsigned vco_max,
 781                                   unsigned fb_factor, unsigned fb_mask,
 782                                   unsigned pd_min, unsigned pd_max,
 783                                   unsigned pd_even,
 784                                   unsigned *optimal_fb_div,
 785                                   unsigned *optimal_vclk_div,
 786                                   unsigned *optimal_dclk_div)
 787 {
 788         unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
 789
 790         /* start off with something large */
 791         unsigned optimal_score = ~0;
 792
 793         /* loop through vco from low to high */
 794         vco_min = max(max(vco_min, vclk), dclk);
 795         for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
 796
 797                 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
 798                 unsigned vclk_div, dclk_div, score;
 799
 800                 do_div(fb_div, ref_freq);
 801
 802                 /* fb div out of range ? */
 803                 if (fb_div > fb_mask)
 804                         break; /* it can oly get worse */
 805
 806                 fb_div &= fb_mask;
 807
 808                 /* calc vclk divider with current vco freq */
 809                 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
 810                                                          pd_min, pd_even);
 811                 if (vclk_div > pd_max)
 812                         break; /* vco is too big, it has to stop */
 813
 814                 /* calc dclk divider with current vco freq */
 815                 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
 816                                                          pd_min, pd_even);
 817                 if (vclk_div > pd_max)
 818                         break; /* vco is too big, it has to stop */
 819
 820                 /* calc score with current vco freq */
 821                 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
 822
 823                 /* determine if this vco setting is better than current optimal settings */
 824                 if (score < optimal_score) {
 825                         *optimal_fb_div = fb_div;
 826                         *optimal_vclk_div = vclk_div;
 827                         *optimal_dclk_div = dclk_div;
 828                         optimal_score = score;
 829                         if (optimal_score == 0)
 830                                 break; /* it can't get better than this */
 831                 }
 832         }
 833
 834         /* did we found a valid setup ? */
 835         if (optimal_score == ~0)
 836                 return -EINVAL;
 837
 838         return 0;
 839 }
 840
 841 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
 842                                 unsigned cg_upll_func_cntl)
 843 {
 844         unsigned i;
 845
 846         /* make sure UPLL_CTLREQ is deasserted */
 847         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 848
 849         mdelay(10);
 850
 851         /* assert UPLL_CTLREQ */
 852         WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
 853
 854         /* wait for CTLACK and CTLACK2 to get asserted */
 855         for (i = 0; i < 100; ++i) {
 856                 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
 857                 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
 858                         break;
 859                 mdelay(10);
 860         }
 861
 862         /* deassert UPLL_CTLREQ */
 863         WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
 864
 865         if (i == 100) {
 866                 DRM_ERROR("Timeout setting UVD clocks!\n");
 867                 return -ETIMEDOUT;
 868         }
 869
 870         return 0;
 871 }