drivers/staging/xgifb/vb_init.c

   1 #include <linux/delay.h>
   2 #include <linux/vmalloc.h>
   3
   4 #include "XGIfb.h"
   5 #include "vb_def.h"
   6 #include "vb_util.h"
   7 #include "vb_setmode.h"
   8 #include "vb_init.h"
   9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
  10         { 16, 0x45},
  11         {  8, 0x35},
  12         {  4, 0x31},
  13         {  2, 0x21} };
  14
  15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
  16         { 128, 0x5D},
  17         { 64, 0x59},
  18         { 64, 0x4D},
  19         { 32, 0x55},
  20         { 32, 0x49},
  21         { 32, 0x3D},
  22         { 16, 0x51},
  23         { 16, 0x45},
  24         { 16, 0x39},
  25         {  8, 0x41},
  26         {  8, 0x35},
  27         {  4, 0x31} };
  28
  29 #define XGIFB_ROM_SIZE  65536
  30
  31 static unsigned char
  32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  33                        struct vb_device_info *pVBInfo)
  34 {
  35         unsigned char data, temp;
  36
  37         if (HwDeviceExtension->jChipType < XG20) {
  38                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  39                 if (data == 0)
  40                         data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  41                                    0x02) >> 1;
  42                 return data;
  43         } else if (HwDeviceExtension->jChipType == XG27) {
  44                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  45                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  46                 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
  47                         data = 0; /* DDR */
  48                 else
  49                         data = 1; /* DDRII */
  50                 return data;
  51         } else if (HwDeviceExtension->jChipType == XG21) {
  52                 /* Independent GPIO control */
  53                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  54                 udelay(800);
  55                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  56                 /* GPIOF 0:DVI 1:DVO */
  57                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  58                 /* HOTPLUG_SUPPORT */
  59                 /* for current XG20 & XG21, GPIOH is floating, driver will
  60                  * fix DDR temporarily */
  61                 if (temp & 0x01) /* DVI read GPIOH */
  62                         data = 1; /* DDRII */
  63                 else
  64                         data = 0; /* DDR */
  65                 /* ~HOTPLUG_SUPPORT */
  66                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  67                 return data;
  68         } else {
  69                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  70
  71                 if (data == 1)
  72                         data++;
  73
  74                 return data;
  75         }
  76 }
  77
  78 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  79                                  struct vb_device_info *pVBInfo)
  80 {
  81         xgifb_reg_set(P3c4, 0x18, 0x01);
  82         xgifb_reg_set(P3c4, 0x19, 0x20);
  83         xgifb_reg_set(P3c4, 0x16, 0x00);
  84         xgifb_reg_set(P3c4, 0x16, 0x80);
  85
  86         mdelay(3);
  87         xgifb_reg_set(P3c4, 0x18, 0x00);
  88         xgifb_reg_set(P3c4, 0x19, 0x20);
  89         xgifb_reg_set(P3c4, 0x16, 0x00);
  90         xgifb_reg_set(P3c4, 0x16, 0x80);
  91
  92         udelay(60);
  93         xgifb_reg_set(P3c4,
  94                       0x18,
  95                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
  96         xgifb_reg_set(P3c4, 0x19, 0x01);
  97         xgifb_reg_set(P3c4, 0x16, 0x03);
  98         xgifb_reg_set(P3c4, 0x16, 0x83);
  99         mdelay(1);
 100         xgifb_reg_set(P3c4, 0x1B, 0x03);
 101         udelay(500);
 102         xgifb_reg_set(P3c4,
 103                       0x18,
 104                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 105         xgifb_reg_set(P3c4, 0x19, 0x00);
 106         xgifb_reg_set(P3c4, 0x16, 0x03);
 107         xgifb_reg_set(P3c4, 0x16, 0x83);
 108         xgifb_reg_set(P3c4, 0x1B, 0x00);
 109 }
 110
 111 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
 112                 struct vb_device_info *pVBInfo)
 113 {
 114
 115         xgifb_reg_set(pVBInfo->P3c4,
 116                       0x28,
 117                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 118         xgifb_reg_set(pVBInfo->P3c4,
 119                       0x29,
 120                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 121         xgifb_reg_set(pVBInfo->P3c4,
 122                       0x2A,
 123                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 124
 125         xgifb_reg_set(pVBInfo->P3c4,
 126                       0x2E,
 127                       XGI340_ECLKData[pVBInfo->ram_type].SR2E);
 128         xgifb_reg_set(pVBInfo->P3c4,
 129                       0x2F,
 130                       XGI340_ECLKData[pVBInfo->ram_type].SR2F);
 131         xgifb_reg_set(pVBInfo->P3c4,
 132                       0x30,
 133                       XGI340_ECLKData[pVBInfo->ram_type].SR30);
 134 }
 135
 136 static void XGINew_DDRII_Bootup_XG27(
 137                         struct xgi_hw_device_info *HwDeviceExtension,
 138                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 139 {
 140         unsigned long P3d4 = P3c4 + 0x10;
 141         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 142         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 143
 144         /* Set Double Frequency */
 145         xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
 146
 147         udelay(200);
 148
 149         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 150         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 151         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 152         udelay(15);
 153         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 154         udelay(15);
 155
 156         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 157         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 158         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 159         udelay(15);
 160         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 161         udelay(15);
 162
 163         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 164         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 165         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 166         udelay(30);
 167         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 168         udelay(15);
 169
 170         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 171         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 172         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 173         udelay(30);
 174         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 175         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 176
 177         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 178         udelay(60);
 179         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 180
 181         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 182         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 183         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 184
 185         udelay(30);
 186         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 187         udelay(15);
 188
 189         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 190         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 191         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 192         udelay(30);
 193         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 194         udelay(15);
 195
 196         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 197         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 198         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 199         udelay(30);
 200         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 201         udelay(15);
 202
 203         /* Set SR1B refresh control 000:close; 010:open */
 204         xgifb_reg_set(P3c4, 0x1B, 0x04);
 205         udelay(200);
 206
 207 }
 208
 209 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 210                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 211 {
 212         unsigned long P3d4 = P3c4 + 0x10;
 213
 214         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 215         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 216
 217         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 218
 219         udelay(200);
 220         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 221         xgifb_reg_set(P3c4, 0x19, 0x80);
 222         xgifb_reg_set(P3c4, 0x16, 0x05);
 223         xgifb_reg_set(P3c4, 0x16, 0x85);
 224
 225         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 226         xgifb_reg_set(P3c4, 0x19, 0xC0);
 227         xgifb_reg_set(P3c4, 0x16, 0x05);
 228         xgifb_reg_set(P3c4, 0x16, 0x85);
 229
 230         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 231         xgifb_reg_set(P3c4, 0x19, 0x40);
 232         xgifb_reg_set(P3c4, 0x16, 0x05);
 233         xgifb_reg_set(P3c4, 0x16, 0x85);
 234
 235         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 236         xgifb_reg_set(P3c4, 0x19, 0x02);
 237         xgifb_reg_set(P3c4, 0x16, 0x05);
 238         xgifb_reg_set(P3c4, 0x16, 0x85);
 239
 240         udelay(15);
 241         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 242         udelay(30);
 243         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 244         udelay(100);
 245
 246         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 247         xgifb_reg_set(P3c4, 0x19, 0x00);
 248         xgifb_reg_set(P3c4, 0x16, 0x05);
 249         xgifb_reg_set(P3c4, 0x16, 0x85);
 250
 251         udelay(200);
 252 }
 253
 254 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 255                                   struct vb_device_info *pVBInfo)
 256 {
 257         xgifb_reg_set(P3c4, 0x18, 0x01);
 258         xgifb_reg_set(P3c4, 0x19, 0x40);
 259         xgifb_reg_set(P3c4, 0x16, 0x00);
 260         xgifb_reg_set(P3c4, 0x16, 0x80);
 261         udelay(60);
 262
 263         xgifb_reg_set(P3c4, 0x18, 0x00);
 264         xgifb_reg_set(P3c4, 0x19, 0x40);
 265         xgifb_reg_set(P3c4, 0x16, 0x00);
 266         xgifb_reg_set(P3c4, 0x16, 0x80);
 267         udelay(60);
 268         xgifb_reg_set(P3c4,
 269                       0x18,
 270                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 271         xgifb_reg_set(P3c4, 0x19, 0x01);
 272         xgifb_reg_set(P3c4, 0x16, 0x03);
 273         xgifb_reg_set(P3c4, 0x16, 0x83);
 274         mdelay(1);
 275         xgifb_reg_set(P3c4, 0x1B, 0x03);
 276         udelay(500);
 277         xgifb_reg_set(P3c4,
 278                       0x18,
 279                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 280         xgifb_reg_set(P3c4, 0x19, 0x00);
 281         xgifb_reg_set(P3c4, 0x16, 0x03);
 282         xgifb_reg_set(P3c4, 0x16, 0x83);
 283         xgifb_reg_set(P3c4, 0x1B, 0x00);
 284 }
 285
 286 static void XGINew_DDR1x_DefaultRegister(
 287                 struct xgi_hw_device_info *HwDeviceExtension,
 288                 unsigned long Port, struct vb_device_info *pVBInfo)
 289 {
 290         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 291
 292         if (HwDeviceExtension->jChipType >= XG20) {
 293                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 294                 xgifb_reg_set(P3d4,
 295                               0x82,
 296                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 297                 xgifb_reg_set(P3d4,
 298                               0x85,
 299                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 300                 xgifb_reg_set(P3d4,
 301                               0x86,
 302                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 303
 304                 xgifb_reg_set(P3d4, 0x98, 0x01);
 305                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 306
 307                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 308         } else {
 309                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 310
 311                 switch (HwDeviceExtension->jChipType) {
 312                 case XG42:
 313                         /* CR82 */
 314                         xgifb_reg_set(P3d4,
 315                                       0x82,
 316                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 317                         /* CR85 */
 318                         xgifb_reg_set(P3d4,
 319                                       0x85,
 320                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 321                         /* CR86 */
 322                         xgifb_reg_set(P3d4,
 323                                       0x86,
 324                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 325                         break;
 326                 default:
 327                         xgifb_reg_set(P3d4, 0x82, 0x88);
 328                         xgifb_reg_set(P3d4, 0x86, 0x00);
 329                         /* Insert read command for delay */
 330                         xgifb_reg_get(P3d4, 0x86);
 331                         xgifb_reg_set(P3d4, 0x86, 0x88);
 332                         xgifb_reg_get(P3d4, 0x86);
 333                         xgifb_reg_set(P3d4,
 334                                       0x86,
 335                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 336                         xgifb_reg_set(P3d4, 0x82, 0x77);
 337                         xgifb_reg_set(P3d4, 0x85, 0x00);
 338
 339                         /* Insert read command for delay */
 340                         xgifb_reg_get(P3d4, 0x85);
 341                         xgifb_reg_set(P3d4, 0x85, 0x88);
 342
 343                         /* Insert read command for delay */
 344                         xgifb_reg_get(P3d4, 0x85);
 345                         /* CR85 */
 346                         xgifb_reg_set(P3d4,
 347                                       0x85,
 348                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 349                         /* CR82 */
 350                         xgifb_reg_set(P3d4,
 351                                       0x82,
 352                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 353                         break;
 354                 }
 355
 356                 xgifb_reg_set(P3d4, 0x97, 0x00);
 357                 xgifb_reg_set(P3d4, 0x98, 0x01);
 358                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 359                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 360         }
 361 }
 362
 363 static void XGINew_DDR2_DefaultRegister(
 364                 struct xgi_hw_device_info *HwDeviceExtension,
 365                 unsigned long Port, struct vb_device_info *pVBInfo)
 366 {
 367         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 368
 369         /* keep following setting sequence, each setting in
 370          * the same reg insert idle */
 371         xgifb_reg_set(P3d4, 0x82, 0x77);
 372         xgifb_reg_set(P3d4, 0x86, 0x00);
 373         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 374         xgifb_reg_set(P3d4, 0x86, 0x88);
 375         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 376         /* CR86 */
 377         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 378         xgifb_reg_set(P3d4, 0x82, 0x77);
 379         xgifb_reg_set(P3d4, 0x85, 0x00);
 380         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 381         xgifb_reg_set(P3d4, 0x85, 0x88);
 382         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 383         xgifb_reg_set(P3d4,
 384                       0x85,
 385                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 386         if (HwDeviceExtension->jChipType == XG27)
 387                 /* CR82 */
 388                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 389         else
 390                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 391
 392         xgifb_reg_set(P3d4, 0x98, 0x01);
 393         xgifb_reg_set(P3d4, 0x9A, 0x02);
 394         if (HwDeviceExtension->jChipType == XG27)
 395                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 396         else
 397                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 398 }
 399
 400 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
 401         u8 shift_factor, u8 mask1, u8 mask2)
 402 {
 403         u8 j;
 404         for (j = 0; j < 4; j++) {
 405                 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
 406                 xgifb_reg_set(P3d4, reg, temp2);
 407                 xgifb_reg_get(P3d4, reg);
 408                 temp2 &= mask1;
 409                 temp2 += mask2;
 410         }
 411 }
 412
 413 static void XGINew_SetDRAMDefaultRegister340(
 414                 struct xgi_hw_device_info *HwDeviceExtension,
 415                 unsigned long Port, struct vb_device_info *pVBInfo)
 416 {
 417         unsigned char temp, temp1, temp2, temp3, j, k;
 418
 419         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 420
 421         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 422         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 423         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 424         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 425
 426         /* CR6B DQS fine tune delay */
 427         temp = 0xaa;
 428         XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
 429
 430         /* CR6E DQM fine tune delay */
 431         XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
 432
 433         temp3 = 0;
 434         for (k = 0; k < 4; k++) {
 435                 /* CR6E_D[1:0] select channel */
 436                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 437                 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
 438                 temp3 += 0x01;
 439         }
 440
 441         xgifb_reg_set(P3d4,
 442                       0x80,
 443                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 444         xgifb_reg_set(P3d4,
 445                       0x81,
 446                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 447
 448         temp2 = 0x80;
 449         /* CR89 terminator type select */
 450         XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
 451
 452         temp = 0;
 453         temp1 = temp & 0x03;
 454         temp2 |= temp1;
 455         xgifb_reg_set(P3d4, 0x89, temp2);
 456
 457         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 458         temp1 = temp & 0x0F;
 459         temp2 = (temp >> 4) & 0x07;
 460         temp3 = temp & 0x80;
 461         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 462         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 463         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 464         xgifb_reg_set(P3d4,
 465                       0x41,
 466                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 467
 468         if (HwDeviceExtension->jChipType == XG27)
 469                 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
 470
 471         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 472                 xgifb_reg_set(P3d4, (0x90 + j),
 473                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 474
 475         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 476                 xgifb_reg_set(P3d4, (0xC3 + j),
 477                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 478
 479         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 480                 xgifb_reg_set(P3d4, (0x8A + j),
 481                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 482
 483         if (HwDeviceExtension->jChipType == XG42)
 484                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 485
 486         xgifb_reg_set(P3d4,
 487                       0x59,
 488                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 489
 490         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 491         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 492         xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
 493         if (pVBInfo->ram_type) {
 494                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 495                 if (HwDeviceExtension->jChipType == XG27)
 496                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 497
 498         } else {
 499                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 500         }
 501         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 502
 503         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 504         if (temp == 0) {
 505                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 506         } else {
 507                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 508                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 509         }
 510         xgifb_reg_set(P3c4,
 511                       0x1B,
 512                       pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
 513 }
 514
 515
 516 static unsigned short XGINew_SetDRAMSize20Reg(
 517                 unsigned short dram_size,
 518                 struct vb_device_info *pVBInfo)
 519 {
 520         unsigned short data = 0, memsize = 0;
 521         int RankSize;
 522         unsigned char ChannelNo;
 523
 524         RankSize = dram_size * pVBInfo->ram_bus / 8;
 525         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 526         data &= 0x80;
 527
 528         if (data == 0x80)
 529                 RankSize *= 2;
 530
 531         data = 0;
 532
 533         if (pVBInfo->ram_channel == 3)
 534                 ChannelNo = 4;
 535         else
 536                 ChannelNo = pVBInfo->ram_channel;
 537
 538         if (ChannelNo * RankSize <= 256) {
 539                 while ((RankSize >>= 1) > 0)
 540                         data += 0x10;
 541
 542                 memsize = data >> 4;
 543
 544                 /* Fix DRAM Sizing Error */
 545                 xgifb_reg_set(pVBInfo->P3c4,
 546                               0x14,
 547                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 548                                 (data & 0xF0));
 549                 udelay(15);
 550         }
 551         return memsize;
 552 }
 553
 554 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 555                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 556 {
 557         int i;
 558         unsigned long Position = 0;
 559         void __iomem *fbaddr = pVBInfo->FBAddr;
 560
 561         writel(Position, fbaddr + Position);
 562
 563         for (i = StartAddr; i <= StopAddr; i++) {
 564                 Position = 1 << i;
 565                 writel(Position, fbaddr + Position);
 566         }
 567
 568         udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */
 569
 570         Position = 0;
 571
 572         if (readl(fbaddr + Position) != Position)
 573                 return 0;
 574
 575         for (i = StartAddr; i <= StopAddr; i++) {
 576                 Position = 1 << i;
 577                 if (readl(fbaddr + Position) != Position)
 578                         return 0;
 579         }
 580         return 1;
 581 }
 582
 583 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 584 {
 585         unsigned char data;
 586
 587         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 588
 589         if ((data & 0x10) == 0) {
 590                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 591                 data = (data & 0x02) >> 1;
 592                 return data;
 593         } else {
 594                 return data & 0x01;
 595         }
 596 }
 597
 598 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 599                 struct vb_device_info *pVBInfo)
 600 {
 601         unsigned char data;
 602
 603         switch (HwDeviceExtension->jChipType) {
 604         case XG20:
 605         case XG21:
 606                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 607                 data = data & 0x01;
 608                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 609
 610                 if (data == 0) { /* Single_32_16 */
 611
 612                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 613                                         > 0x1000000) {
 614
 615                                 pVBInfo->ram_bus = 32; /* 32 bits */
 616                                 /* 22bit + 2 rank + 32bit */
 617                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 618                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 619                                 udelay(15);
 620
 621                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 622                                         return;
 623
 624                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 625                                     0x800000) {
 626                                         /* 22bit + 1 rank + 32bit */
 627                                         xgifb_reg_set(pVBInfo->P3c4,
 628                                                       0x13,
 629                                                       0x31);
 630                                         xgifb_reg_set(pVBInfo->P3c4,
 631                                                       0x14,
 632                                                       0x42);
 633                                         udelay(15);
 634
 635                                         if (XGINew_ReadWriteRest(23,
 636                                                                  23,
 637                                                                  pVBInfo) == 1)
 638                                                 return;
 639                                 }
 640                         }
 641
 642                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 643                             0x800000) {
 644                                 pVBInfo->ram_bus = 16; /* 16 bits */
 645                                 /* 22bit + 2 rank + 16bit */
 646                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 647                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 648                                 udelay(15);
 649
 650                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 651                                         return;
 652                                 else
 653                                         xgifb_reg_set(pVBInfo->P3c4,
 654                                                       0x13,
 655                                                       0x31);
 656                                 udelay(15);
 657                         }
 658
 659                 } else { /* Dual_16_8 */
 660                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 661                             0x800000) {
 662                                 pVBInfo->ram_bus = 16; /* 16 bits */
 663                                 /* (0x31:12x8x2) 22bit + 2 rank */
 664                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 665                                 /* 0x41:16Mx16 bit*/
 666                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 667                                 udelay(15);
 668
 669                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 670                                         return;
 671
 672                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 673                                     0x400000) {
 674                                         /* (0x31:12x8x2) 22bit + 1 rank */
 675                                         xgifb_reg_set(pVBInfo->P3c4,
 676                                                       0x13,
 677                                                       0x31);
 678                                         /* 0x31:8Mx16 bit*/
 679                                         xgifb_reg_set(pVBInfo->P3c4,
 680                                                       0x14,
 681                                                       0x31);
 682                                         udelay(15);
 683
 684                                         if (XGINew_ReadWriteRest(22,
 685                                                                  22,
 686                                                                  pVBInfo) == 1)
 687                                                 return;
 688                                 }
 689                         }
 690
 691                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 692                             0x400000) {
 693                                 pVBInfo->ram_bus = 8; /* 8 bits */
 694                                 /* (0x31:12x8x2) 22bit + 2 rank */
 695                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 696                                 /* 0x30:8Mx8 bit*/
 697                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 698                                 udelay(15);
 699
 700                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 701                                         return;
 702                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 703                                         xgifb_reg_set(pVBInfo->P3c4,
 704                                                       0x13,
 705                                                       0x31);
 706                                 udelay(15);
 707                         }
 708                 }
 709                 break;
 710
 711         case XG27:
 712                 pVBInfo->ram_bus = 16; /* 16 bits */
 713                 pVBInfo->ram_channel = 1; /* Single channel */
 714                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 715                 break;
 716         case XG42:
 717                 /*
 718                  XG42 SR14 D[3] Reserve
 719                  D[2] = 1, Dual Channel
 720                  = 0, Single Channel
 721
 722                  It's Different from Other XG40 Series.
 723                  */
 724                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 725                         pVBInfo->ram_bus = 32; /* 32 bits */
 726                         pVBInfo->ram_channel = 2; /* 2 Channel */
 727                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 728                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 729
 730                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 731                                 return;
 732
 733                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 734                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 735                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 736                                 return;
 737
 738                         pVBInfo->ram_channel = 1; /* Single Channel */
 739                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 740                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 741
 742                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 743                                 return;
 744                         else {
 745                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 746                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 747                         }
 748                 } else { /* DDR */
 749                         pVBInfo->ram_bus = 64; /* 64 bits */
 750                         pVBInfo->ram_channel = 1; /* 1 channels */
 751                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 752                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 753
 754                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 755                                 return;
 756                         else {
 757                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 758                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 759                         }
 760                 }
 761
 762                 break;
 763
 764         default: /* XG40 */
 765
 766                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 767                         pVBInfo->ram_bus = 32; /* 32 bits */
 768                         pVBInfo->ram_channel = 3;
 769                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 770                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 771
 772                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 773                                 return;
 774
 775                         pVBInfo->ram_channel = 2; /* 2 channels */
 776                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 777
 778                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 779                                 return;
 780
 781                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 782                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 783
 784                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 785                                 pVBInfo->ram_channel = 3; /* 4 channels */
 786                         } else {
 787                                 pVBInfo->ram_channel = 2; /* 2 channels */
 788                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 789                         }
 790                 } else { /* DDR */
 791                         pVBInfo->ram_bus = 64; /* 64 bits */
 792                         pVBInfo->ram_channel = 2; /* 2 channels */
 793                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 794                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 795
 796                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
 797                                 return;
 798                         } else {
 799                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 800                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 801                         }
 802                 }
 803                 break;
 804         }
 805 }
 806
 807 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
 808                 struct vb_device_info *pVBInfo)
 809 {
 810         u8 i, size;
 811         unsigned short memsize, start_addr;
 812         const unsigned short (*dram_table)[2];
 813
 814         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
 815         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
 816         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
 817
 818         if (HwDeviceExtension->jChipType >= XG20) {
 819                 dram_table = XGINew_DDRDRAM_TYPE20;
 820                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
 821                 start_addr = 5;
 822         } else {
 823                 dram_table = XGINew_DDRDRAM_TYPE340;
 824                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
 825                 start_addr = 9;
 826         }
 827
 828         for (i = 0; i < size; i++) {
 829                 /* SetDRAMSizingType */
 830                 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
 831                 udelay(15); /* should delay 50 ns */
 832
 833                 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
 834
 835                 if (memsize == 0)
 836                         continue;
 837
 838                 memsize += (pVBInfo->ram_channel - 2) + 20;
 839                 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 840                         (unsigned long) (1 << memsize))
 841                         continue;
 842
 843                 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
 844                         return 1;
 845         }
 846         return 0;
 847 }
 848
 849 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
 850                 struct xgi_hw_device_info *HwDeviceExtension,
 851                 struct vb_device_info *pVBInfo)
 852 {
 853         unsigned short data;
 854
 855         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
 856
 857         XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
 858
 859         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 860         /* disable read cache */
 861         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
 862         XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
 863
 864         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
 865         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 866         /* enable read cache */
 867         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
 868 }
 869
 870 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
 871 {
 872         void __iomem *rom_address;
 873         u8 *rom_copy;
 874
 875         rom_address = pci_map_rom(dev, rom_size);
 876         if (rom_address == NULL)
 877                 return NULL;
 878
 879         rom_copy = vzalloc(XGIFB_ROM_SIZE);
 880         if (rom_copy == NULL)
 881                 goto done;
 882
 883         *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
 884         memcpy_fromio(rom_copy, rom_address, *rom_size);
 885
 886 done:
 887         pci_unmap_rom(dev, rom_address);
 888         return rom_copy;
 889 }
 890
 891 static bool xgifb_read_vbios(struct pci_dev *pdev,
 892                               struct vb_device_info *pVBInfo)
 893 {
 894         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
 895         u8 *vbios;
 896         unsigned long i;
 897         unsigned char j;
 898         struct XGI21_LVDSCapStruct *lvds;
 899         size_t vbios_size;
 900         int entry;
 901
 902         vbios = xgifb_copy_rom(pdev, &vbios_size);
 903         if (vbios == NULL) {
 904                 dev_err(&pdev->dev, "Video BIOS not available\n");
 905                 return false;
 906         }
 907         if (vbios_size <= 0x65)
 908                 goto error;
 909         /*
 910          * The user can ignore the LVDS bit in the BIOS and force the display
 911          * type.
 912          */
 913         if (!(vbios[0x65] & 0x1) &&
 914             (!xgifb_info->display2_force ||
 915              xgifb_info->display2 != XGIFB_DISP_LCD)) {
 916                 vfree(vbios);
 917                 return false;
 918         }
 919         if (vbios_size <= 0x317)
 920                 goto error;
 921         i = vbios[0x316] | (vbios[0x317] << 8);
 922         if (vbios_size <= i - 1)
 923                 goto error;
 924         j = vbios[i - 1];
 925         if (j == 0)
 926                 goto error;
 927         if (j == 0xff)
 928                 j = 1;
 929         /*
 930          * Read the LVDS table index scratch register set by the BIOS.
 931          */
 932         entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
 933         if (entry >= j)
 934                 entry = 0;
 935         i += entry * 25;
 936         lvds = &xgifb_info->lvds_data;
 937         if (vbios_size <= i + 24)
 938                 goto error;
 939         lvds->LVDS_Capability   = vbios[i]      | (vbios[i + 1] << 8);
 940         lvds->LVDSHT            = vbios[i + 2]  | (vbios[i + 3] << 8);
 941         lvds->LVDSVT            = vbios[i + 4]  | (vbios[i + 5] << 8);
 942         lvds->LVDSHDE           = vbios[i + 6]  | (vbios[i + 7] << 8);
 943         lvds->LVDSVDE           = vbios[i + 8]  | (vbios[i + 9] << 8);
 944         lvds->LVDSHFP           = vbios[i + 10] | (vbios[i + 11] << 8);
 945         lvds->LVDSVFP           = vbios[i + 12] | (vbios[i + 13] << 8);
 946         lvds->LVDSHSYNC         = vbios[i + 14] | (vbios[i + 15] << 8);
 947         lvds->LVDSVSYNC         = vbios[i + 16] | (vbios[i + 17] << 8);
 948         lvds->VCLKData1         = vbios[i + 18];
 949         lvds->VCLKData2         = vbios[i + 19];
 950         lvds->PSC_S1            = vbios[i + 20];
 951         lvds->PSC_S2            = vbios[i + 21];
 952         lvds->PSC_S3            = vbios[i + 22];
 953         lvds->PSC_S4            = vbios[i + 23];
 954         lvds->PSC_S5            = vbios[i + 24];
 955         vfree(vbios);
 956         return true;
 957 error:
 958         dev_err(&pdev->dev, "Video BIOS corrupted\n");
 959         vfree(vbios);
 960         return false;
 961 }
 962
 963 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
 964                 struct vb_device_info *pVBInfo)
 965 {
 966         unsigned short tempbx = 0, temp, tempcx, CR3CData;
 967
 968         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
 969
 970         if (temp & Monitor1Sense)
 971                 tempbx |= ActiveCRT1;
 972         if (temp & LCDSense)
 973                 tempbx |= ActiveLCD;
 974         if (temp & Monitor2Sense)
 975                 tempbx |= ActiveCRT2;
 976         if (temp & TVSense) {
 977                 tempbx |= ActiveTV;
 978                 if (temp & AVIDEOSense)
 979                         tempbx |= (ActiveAVideo << 8);
 980                 if (temp & SVIDEOSense)
 981                         tempbx |= (ActiveSVideo << 8);
 982                 if (temp & SCARTSense)
 983                         tempbx |= (ActiveSCART << 8);
 984                 if (temp & HiTVSense)
 985                         tempbx |= (ActiveHiTV << 8);
 986                 if (temp & YPbPrSense)
 987                         tempbx |= (ActiveYPbPr << 8);
 988         }
 989
 990         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 991         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
 992
 993         if (tempbx & tempcx) {
 994                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
 995                 if (!(CR3CData & DisplayDeviceFromCMOS))
 996                         tempcx = 0x1FF0;
 997         } else {
 998                 tempcx = 0x1FF0;
 999         }
1000
1001         tempbx &= tempcx;
1002         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1003         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1004 }
1005
1006 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1007                 struct vb_device_info *pVBInfo)
1008 {
1009         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1010
1011         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1012         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1013         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1014
1015         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1016                 if (temp & ActiveCRT2)
1017                         tempcl = SetCRT2ToRAMDAC;
1018         }
1019
1020         if (temp & ActiveLCD) {
1021                 tempcl |= SetCRT2ToLCD;
1022                 if (temp & DriverMode) {
1023                         if (temp & ActiveTV) {
1024                                 tempch = SetToLCDA | EnableDualEdge;
1025                                 temp ^= SetCRT2ToLCD;
1026
1027                                 if ((temp >> 8) & ActiveAVideo)
1028                                         tempcl |= SetCRT2ToAVIDEO;
1029                                 if ((temp >> 8) & ActiveSVideo)
1030                                         tempcl |= SetCRT2ToSVIDEO;
1031                                 if ((temp >> 8) & ActiveSCART)
1032                                         tempcl |= SetCRT2ToSCART;
1033
1034                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1035                                         if ((temp >> 8) & ActiveHiTV)
1036                                                 tempcl |= SetCRT2ToHiVision;
1037                                 }
1038
1039                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1040                                         if ((temp >> 8) & ActiveYPbPr)
1041                                                 tempch |= SetYPbPr;
1042                                 }
1043                         }
1044                 }
1045         } else {
1046                 if ((temp >> 8) & ActiveAVideo)
1047                         tempcl |= SetCRT2ToAVIDEO;
1048                 if ((temp >> 8) & ActiveSVideo)
1049                         tempcl |= SetCRT2ToSVIDEO;
1050                 if ((temp >> 8) & ActiveSCART)
1051                         tempcl |= SetCRT2ToSCART;
1052
1053                 if (pVBInfo->IF_DEF_HiVision == 1) {
1054                         if ((temp >> 8) & ActiveHiTV)
1055                                 tempcl |= SetCRT2ToHiVision;
1056                 }
1057
1058                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1059                         if ((temp >> 8) & ActiveYPbPr)
1060                                 tempch |= SetYPbPr;
1061                 }
1062         }
1063
1064         tempcl |= SetSimuScanMode;
1065         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1066                         || (temp & ActiveCRT2)))
1067                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1068         if ((temp & ActiveLCD) && (temp & ActiveTV))
1069                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1070         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1071
1072         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1073         CR31Data &= ~(SetNotSimuMode >> 8);
1074         if (!(temp & ActiveCRT1))
1075                 CR31Data |= (SetNotSimuMode >> 8);
1076         CR31Data &= ~(DisableCRT2Display >> 8);
1077         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1078                 CR31Data |= (DisableCRT2Display >> 8);
1079         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1080
1081         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1082         CR38Data &= ~SetYPbPr;
1083         CR38Data |= tempch;
1084         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1085
1086 }
1087
1088 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1089                                                         *HwDeviceExtension,
1090                                       struct vb_device_info *pVBInfo)
1091 {
1092         unsigned short temp;
1093
1094         /* add lcd sense */
1095         if (HwDeviceExtension->ulCRT2LCDType == LCD_UNKNOWN) {
1096                 return 0;
1097         } else {
1098                 temp = (unsigned short) HwDeviceExtension->ulCRT2LCDType;
1099                 switch (HwDeviceExtension->ulCRT2LCDType) {
1100                 case LCD_INVALID:
1101                 case LCD_800x600:
1102                 case LCD_1024x768:
1103                 case LCD_1280x1024:
1104                         break;
1105
1106                 case LCD_640x480:
1107                 case LCD_1024x600:
1108                 case LCD_1152x864:
1109                 case LCD_1280x960:
1110                 case LCD_1152x768:
1111                         temp = 0;
1112                         break;
1113
1114                 case LCD_1400x1050:
1115                 case LCD_1280x768:
1116                 case LCD_1600x1200:
1117                         break;
1118
1119                 case LCD_1920x1440:
1120                 case LCD_2048x1536:
1121                         temp = 0;
1122                         break;
1123
1124                 default:
1125                         break;
1126                 }
1127                 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1128                 return 1;
1129         }
1130 }
1131
1132 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1133                 struct vb_device_info *pVBInfo)
1134 {
1135         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1136         unsigned char Temp;
1137
1138         if (xgifb_read_vbios(pdev, pVBInfo)) { /* For XG21 LVDS */
1139                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1140                 /* LVDS on chip */
1141                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1142         } else {
1143                 /* Enable GPIOA/B read  */
1144                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1145                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1146                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1147                         XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1148                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1149                         /* Enable read GPIOF */
1150                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1151                         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1152                         if (!Temp)
1153                                 xgifb_reg_and_or(pVBInfo->P3d4,
1154                                                  0x38,
1155                                                  ~0xE0,
1156                                                  0x80); /* TMDS on chip */
1157                         else
1158                                 xgifb_reg_and_or(pVBInfo->P3d4,
1159                                                  0x38,
1160                                                  ~0xE0,
1161                                                  0xA0); /* Only DVO on chip */
1162                         /* Disable read GPIOF */
1163                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1164                 }
1165         }
1166 }
1167
1168 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1169                 struct vb_device_info *pVBInfo)
1170 {
1171         unsigned char Temp, bCR4A;
1172
1173         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1174         /* Enable GPIOA/B/C read  */
1175         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1176         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1177         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1178
1179         if (Temp <= 0x02) {
1180                 /* LVDS setting */
1181                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1182                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1183         } else {
1184                 /* TMDS/DVO setting */
1185                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1186         }
1187         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1188
1189 }
1190
1191 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1192 {
1193         unsigned char CR38, CR4A, temp;
1194
1195         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1196         /* enable GPIOE read */
1197         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1198         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1199         temp = 0;
1200         if ((CR38 & 0xE0) > 0x80) {
1201                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1202                 temp &= 0x08;
1203                 temp >>= 3;
1204         }
1205
1206         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1207
1208         return temp;
1209 }
1210
1211 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1212 {
1213         unsigned char CR4A, temp;
1214
1215         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1216         /* enable GPIOA/B/C read */
1217         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1218         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1219         if (temp <= 2)
1220                 temp &= 0x03;
1221         else
1222                 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1223
1224         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1225
1226         return temp;
1227 }
1228
1229 unsigned char XGIInitNew(struct pci_dev *pdev)
1230 {
1231         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1232         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1233         struct vb_device_info VBINF;
1234         struct vb_device_info *pVBInfo = &VBINF;
1235         unsigned char i, temp = 0, temp1;
1236
1237         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1238
1239         if (pVBInfo->FBAddr == NULL) {
1240                 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1241                 return 0;
1242         }
1243
1244         XGIRegInit(pVBInfo, xgifb_info->vga_base);
1245
1246         outb(0x67, pVBInfo->P3c2);
1247
1248         if (HwDeviceExtension->jChipType < XG20)
1249                 /* Run XGI_GetVBType before InitTo330Pointer */
1250                 XGI_GetVBType(pVBInfo);
1251
1252         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1253
1254         /* Openkey */
1255         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1256
1257         /* GetXG21Sense (GPIO) */
1258         if (HwDeviceExtension->jChipType == XG21)
1259                 XGINew_GetXG21Sense(pdev, pVBInfo);
1260
1261         if (HwDeviceExtension->jChipType == XG27)
1262                 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1263
1264         /* Reset Extended register */
1265
1266         for (i = 0x06; i < 0x20; i++)
1267                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1268
1269         for (i = 0x21; i <= 0x27; i++)
1270                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1271
1272         for (i = 0x31; i <= 0x3B; i++)
1273                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1274
1275         /* Auto over driver for XG42 */
1276         if (HwDeviceExtension->jChipType == XG42)
1277                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1278
1279         for (i = 0x79; i <= 0x7C; i++)
1280                 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1281
1282         if (HwDeviceExtension->jChipType >= XG20)
1283                 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1284
1285         /* SetDefExt1Regs begin */
1286         xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1287         if (HwDeviceExtension->jChipType == XG27) {
1288                 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1289                 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1290         }
1291         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1292         xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1293         /* Frame buffer can read/write SR20 */
1294         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1295         /* H/W request for slow corner chip */
1296         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1297         if (HwDeviceExtension->jChipType == XG27)
1298                 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1299
1300         if (HwDeviceExtension->jChipType < XG20) {
1301                 u32 Temp;
1302
1303                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1304                 for (i = 0x47; i <= 0x4C; i++)
1305                         xgifb_reg_set(pVBInfo->P3d4,
1306                                       i,
1307                                       XGI340_AGPReg[i - 0x47]);
1308
1309                 for (i = 0x70; i <= 0x71; i++)
1310                         xgifb_reg_set(pVBInfo->P3d4,
1311                                       i,
1312                                       XGI340_AGPReg[6 + i - 0x70]);
1313
1314                 for (i = 0x74; i <= 0x77; i++)
1315                         xgifb_reg_set(pVBInfo->P3d4,
1316                                       i,
1317                                       XGI340_AGPReg[8 + i - 0x74]);
1318
1319                 pci_read_config_dword(pdev, 0x50, &Temp);
1320                 Temp >>= 20;
1321                 Temp &= 0xF;
1322
1323                 if (Temp == 1)
1324                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1325         } /* != XG20 */
1326
1327         /* Set PCI */
1328         xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1329         xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1330         xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1331
1332         if (HwDeviceExtension->jChipType < XG20) {
1333                 /* Set VB */
1334                 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1335                 /* disable VideoCapture */
1336                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1337                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1338                 /* chk if BCLK>=100MHz */
1339                 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1340                 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1341
1342                 xgifb_reg_set(pVBInfo->Part1Port,
1343                               0x02, XGI330_CRT2Data_1_2);
1344
1345                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1346         } /* != XG20 */
1347
1348         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1349
1350         if ((HwDeviceExtension->jChipType == XG42) &&
1351             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1352                 /* Not DDR */
1353                 xgifb_reg_set(pVBInfo->P3c4,
1354                               0x31,
1355                               (XGI330_SR31 & 0x3F) | 0x40);
1356                 xgifb_reg_set(pVBInfo->P3c4,
1357                               0x32,
1358                               (XGI330_SR32 & 0xFC) | 0x01);
1359         } else {
1360                 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1361                 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1362         }
1363         xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1364
1365         if (HwDeviceExtension->jChipType < XG20) {
1366                 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1367                         xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1368                         xgifb_reg_set(pVBInfo->Part4Port,
1369                                       0x0D, XGI330_CRT2Data_4_D);
1370                         xgifb_reg_set(pVBInfo->Part4Port,
1371                                       0x0E, XGI330_CRT2Data_4_E);
1372                         xgifb_reg_set(pVBInfo->Part4Port,
1373                                       0x10, XGI330_CRT2Data_4_10);
1374                         xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1375                         XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1376                 }
1377         } /* != XG20 */
1378
1379         XGI_SenseCRT1(pVBInfo);
1380
1381         if (HwDeviceExtension->jChipType == XG21) {
1382
1383                 xgifb_reg_and_or(pVBInfo->P3d4,
1384                                  0x32,
1385                                  ~Monitor1Sense,
1386                                  Monitor1Sense); /* Z9 default has CRT */
1387                 temp = GetXG21FPBits(pVBInfo);
1388                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1389
1390         }
1391         if (HwDeviceExtension->jChipType == XG27) {
1392                 xgifb_reg_and_or(pVBInfo->P3d4,
1393                                  0x32,
1394                                  ~Monitor1Sense,
1395                                  Monitor1Sense); /* Z9 default has CRT */
1396                 temp = GetXG27FPBits(pVBInfo);
1397                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1398         }
1399
1400         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1401
1402         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1403                                          pVBInfo->P3d4,
1404                                          pVBInfo);
1405
1406         XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1407
1408         xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1409         xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1410
1411         XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1412         XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1413
1414         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1415
1416         return 1;
1417 } /* end of init */