arch/ia64/kernel/iosapic.c

   1 /*
   2  * I/O SAPIC support.
   3  *
   4  * Copyright (C) 1999 Intel Corp.
   5  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   6  * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
   7  * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
   8  *      David Mosberger-Tang <davidm@hpl.hp.com>
   9  * Copyright (C) 1999 VA Linux Systems
  10  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  11  *
  12  * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O
  13  *                              APIC code.  In particular, we now have separate
  14  *                              handlers for edge and level triggered
  15  *                              interrupts.
  16  * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
  17  *                              allocation PCI to vector mapping, shared PCI
  18  *                              interrupts.
  19  * 00/10/27     D. Mosberger    Document things a bit more to make them more
  20  *                              understandable.  Clean up much of the old
  21  *                              IOSAPIC cruft.
  22  * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts
  23  *                              and fixes for ACPI S5(SoftOff) support.
  24  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
  25  * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt
  26  *                              vectors in iosapic_set_affinity(),
  27  *                              initializations for /proc/irq/#/smp_affinity
  28  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
  29  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
  30  * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to
  31  *                              IOSAPIC mapping error
  32  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
  33  * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system
  34  *                              interrupt, vector, etc.)
  35  * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's
  36  *                              pci_irq code.
  37  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
  38  *                              Remove iosapic_address & gsi_base from
  39  *                              external interfaces.  Rationalize
  40  *                              __init/__devinit attributes.
  41  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
  42  *                              Updated to work with irq migration necessary
  43  *                              for CPU Hotplug
  44  */
  45 /*
  46  * Here is what the interrupt logic between a PCI device and the kernel looks
  47  * like:
  48  *
  49  * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
  50  *     INTD).  The device is uniquely identified by its bus-, and slot-number
  51  *     (the function number does not matter here because all functions share
  52  *     the same interrupt lines).
  53  *
  54  * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
  55  *     controller.  Multiple interrupt lines may have to share the same
  56  *     IOSAPIC pin (if they're level triggered and use the same polarity).
  57  *     Each interrupt line has a unique Global System Interrupt (GSI) number
  58  *     which can be calculated as the sum of the controller's base GSI number
  59  *     and the IOSAPIC pin number to which the line connects.
  60  *
  61  * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
  62  * IOSAPIC pin into the IA-64 interrupt vector.  This interrupt vector is then
  63  * sent to the CPU.
  64  *
  65  * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is
  66  *     used as architecture-independent interrupt handling mechanism in Linux.
  67  *     As an IRQ is a number, we have to have
  68  *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
  69  *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
  70  *     platform can implement platform_irq_to_vector(irq) and
  71  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
  72  *     Please see also include/asm-ia64/hw_irq.h for those APIs.
  73  *
  74  * To sum up, there are three levels of mappings involved:
  75  *
  76  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  77  *
  78  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
  79  * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
  80  * (isa_irq) is the only exception in this source code.
  81  */
  82
  83 #include <linux/acpi.h>
  84 #include <linux/init.h>
  85 #include <linux/irq.h>
  86 #include <linux/kernel.h>
  87 #include <linux/list.h>
  88 #include <linux/pci.h>
  89 #include <linux/smp.h>
  90 #include <linux/string.h>
  91 #include <linux/bootmem.h>
  92
  93 #include <asm/delay.h>
  94 #include <asm/hw_irq.h>
  95 #include <asm/io.h>
  96 #include <asm/iosapic.h>
  97 #include <asm/machvec.h>
  98 #include <asm/processor.h>
  99 #include <asm/ptrace.h>
 100 #include <asm/system.h>
 101
 102 #undef DEBUG_INTERRUPT_ROUTING
 103
 104 #ifdef DEBUG_INTERRUPT_ROUTING
 105 #define DBG(fmt...)     printk(fmt)
 106 #else
 107 #define DBG(fmt...)
 108 #endif
 109
 110 #define NR_PREALLOCATE_RTE_ENTRIES \
 111         (PAGE_SIZE / sizeof(struct iosapic_rte_info))
 112 #define RTE_PREALLOCATED        (1)
 113
 114 static DEFINE_SPINLOCK(iosapic_lock);
 115
 116 /*
 117  * These tables map IA-64 vectors to the IOSAPIC pin that generates this
 118  * vector.
 119  */
 120 static struct iosapic {
 121         char __iomem    *addr;          /* base address of IOSAPIC */
 122         unsigned int    gsi_base;       /* GSI base */
 123         unsigned short  num_rte;        /* # of RTEs on this IOSAPIC */
 124         int             rtes_inuse;     /* # of RTEs in use on this IOSAPIC */
 125 #ifdef CONFIG_NUMA
 126         unsigned short  node;           /* numa node association via pxm */
 127 #endif
 128         spinlock_t      lock;           /* lock for indirect reg access */
 129 } iosapic_lists[NR_IOSAPICS];
 130
 131 struct iosapic_rte_info {
 132         struct list_head rte_list;      /* RTEs sharing the same vector */
 133         char            rte_index;      /* IOSAPIC RTE index */
 134         int             refcnt;         /* reference counter */
 135         unsigned int    flags;          /* flags */
 136         struct iosapic  *iosapic;
 137 } ____cacheline_aligned;
 138
 139 static struct iosapic_intr_info {
 140         struct list_head rtes;          /* RTEs using this vector (empty =>
 141                                          * not an IOSAPIC interrupt) */
 142         int             count;          /* # of RTEs that shares this vector */
 143         u32             low32;          /* current value of low word of
 144                                          * Redirection table entry */
 145         unsigned int    dest;           /* destination CPU physical ID */
 146         unsigned char   dmode   : 3;    /* delivery mode (see iosapic.h) */
 147         unsigned char   polarity: 1;    /* interrupt polarity
 148                                          * (see iosapic.h) */
 149         unsigned char   trigger : 1;    /* trigger mode (see iosapic.h) */
 150 } iosapic_intr_info[NR_IRQS];
 151
 152 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
 153
 154 static int iosapic_kmalloc_ok;
 155 static LIST_HEAD(free_rte_list);
 156
 157 static inline void
 158 iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
 159 {
 160         unsigned long flags;
 161
 162         spin_lock_irqsave(&iosapic->lock, flags);
 163         __iosapic_write(iosapic->addr, reg, val);
 164         spin_unlock_irqrestore(&iosapic->lock, flags);
 165 }
 166
 167 /*
 168  * Find an IOSAPIC associated with a GSI
 169  */
 170 static inline int
 171 find_iosapic (unsigned int gsi)
 172 {
 173         int i;
 174
 175         for (i = 0; i < NR_IOSAPICS; i++) {
 176                 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
 177                     iosapic_lists[i].num_rte)
 178                         return i;
 179         }
 180
 181         return -1;
 182 }
 183
 184 static inline int __gsi_to_irq(unsigned int gsi)
 185 {
 186         int irq;
 187         struct iosapic_intr_info *info;
 188         struct iosapic_rte_info *rte;
 189
 190         for (irq = 0; irq < NR_IRQS; irq++) {
 191                 info = &iosapic_intr_info[irq];
 192                 list_for_each_entry(rte, &info->rtes, rte_list)
 193                         if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 194                                 return irq;
 195         }
 196         return -1;
 197 }
 198
 199 /*
 200  * Translate GSI number to the corresponding IA-64 interrupt vector.  If no
 201  * entry exists, return -1.
 202  */
 203 inline int
 204 gsi_to_vector (unsigned int gsi)
 205 {
 206         int irq = __gsi_to_irq(gsi);
 207         if (irq < 0)
 208                 return -1;
 209         return irq_to_vector(irq);
 210 }
 211
 212 int
 213 gsi_to_irq (unsigned int gsi)
 214 {
 215         unsigned long flags;
 216         int irq;
 217
 218         spin_lock_irqsave(&iosapic_lock, flags);
 219         irq = __gsi_to_irq(gsi);
 220         spin_unlock_irqrestore(&iosapic_lock, flags);
 221         return irq;
 222 }
 223
 224 static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi)
 225 {
 226         struct iosapic_rte_info *rte;
 227
 228         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
 229                 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 230                         return rte;
 231         return NULL;
 232 }
 233
 234 static void
 235 set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
 236 {
 237         unsigned long pol, trigger, dmode;
 238         u32 low32, high32;
 239         int rte_index;
 240         char redir;
 241         struct iosapic_rte_info *rte;
 242         ia64_vector vector = irq_to_vector(irq);
 243
 244         DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
 245
 246         rte = find_rte(irq, gsi);
 247         if (!rte)
 248                 return;         /* not an IOSAPIC interrupt */
 249
 250         rte_index = rte->rte_index;
 251         pol     = iosapic_intr_info[irq].polarity;
 252         trigger = iosapic_intr_info[irq].trigger;
 253         dmode   = iosapic_intr_info[irq].dmode;
 254
 255         redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
 256
 257 #ifdef CONFIG_SMP
 258         set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
 259 #endif
 260
 261         low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 262                  (trigger << IOSAPIC_TRIGGER_SHIFT) |
 263                  (dmode << IOSAPIC_DELIVERY_SHIFT) |
 264                  ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
 265                  vector);
 266
 267         /* dest contains both id and eid */
 268         high32 = (dest << IOSAPIC_DEST_SHIFT);
 269
 270         iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
 271         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 272         iosapic_intr_info[irq].low32 = low32;
 273         iosapic_intr_info[irq].dest = dest;
 274 }
 275
 276 static void
 277 nop (unsigned int irq)
 278 {
 279         /* do nothing... */
 280 }
 281
 282
 283 #ifdef CONFIG_KEXEC
 284 void
 285 kexec_disable_iosapic(void)
 286 {
 287         struct iosapic_intr_info *info;
 288         struct iosapic_rte_info *rte;
 289         ia64_vector vec;
 290         int irq;
 291
 292         for (irq = 0; irq < NR_IRQS; irq++) {
 293                 info = &iosapic_intr_info[irq];
 294                 vec = irq_to_vector(irq);
 295                 list_for_each_entry(rte, &info->rtes,
 296                                 rte_list) {
 297                         iosapic_write(rte->iosapic,
 298                                         IOSAPIC_RTE_LOW(rte->rte_index),
 299                                         IOSAPIC_MASK|vec);
 300                         iosapic_eoi(rte->iosapic->addr, vec);
 301                 }
 302         }
 303 }
 304 #endif
 305
 306 static void
 307 mask_irq (unsigned int irq)
 308 {
 309         u32 low32;
 310         int rte_index;
 311         struct iosapic_rte_info *rte;
 312
 313         if (list_empty(&iosapic_intr_info[irq].rtes))
 314                 return;                 /* not an IOSAPIC interrupt! */
 315
 316         /* set only the mask bit */
 317         low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
 318         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 319                 rte_index = rte->rte_index;
 320                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 321         }
 322 }
 323
 324 static void
 325 unmask_irq (unsigned int irq)
 326 {
 327         u32 low32;
 328         int rte_index;
 329         struct iosapic_rte_info *rte;
 330
 331         if (list_empty(&iosapic_intr_info[irq].rtes))
 332                 return;                 /* not an IOSAPIC interrupt! */
 333
 334         low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK;
 335         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 336                 rte_index = rte->rte_index;
 337                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 338         }
 339 }
 340
 341
 342 static void
 343 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
 344 {
 345 #ifdef CONFIG_SMP
 346         u32 high32, low32;
 347         int dest, rte_index;
 348         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
 349         struct iosapic_rte_info *rte;
 350         struct iosapic *iosapic;
 351
 352         irq &= (~IA64_IRQ_REDIRECTED);
 353
 354         if (cpus_empty(mask))
 355                 return;
 356
 357         dest = cpu_physical_id(first_cpu(mask));
 358
 359         if (list_empty(&iosapic_intr_info[irq].rtes))
 360                 return;                 /* not an IOSAPIC interrupt */
 361
 362         set_irq_affinity_info(irq, dest, redir);
 363
 364         /* dest contains both id and eid */
 365         high32 = dest << IOSAPIC_DEST_SHIFT;
 366
 367         low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
 368         if (redir)
 369                 /* change delivery mode to lowest priority */
 370                 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
 371         else
 372                 /* change delivery mode to fixed */
 373                 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 374
 375         iosapic_intr_info[irq].low32 = low32;
 376         iosapic_intr_info[irq].dest = dest;
 377         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 378                 iosapic = rte->iosapic;
 379                 rte_index = rte->rte_index;
 380                 iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
 381                 iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 382         }
 383 #endif
 384 }
 385
 386 /*
 387  * Handlers for level-triggered interrupts.
 388  */
 389
 390 static unsigned int
 391 iosapic_startup_level_irq (unsigned int irq)
 392 {
 393         unmask_irq(irq);
 394         return 0;
 395 }
 396
 397 static void
 398 iosapic_end_level_irq (unsigned int irq)
 399 {
 400         ia64_vector vec = irq_to_vector(irq);
 401         struct iosapic_rte_info *rte;
 402
 403         move_native_irq(irq);
 404         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
 405                 iosapic_eoi(rte->iosapic->addr, vec);
 406 }
 407
 408 #define iosapic_shutdown_level_irq      mask_irq
 409 #define iosapic_enable_level_irq        unmask_irq
 410 #define iosapic_disable_level_irq       mask_irq
 411 #define iosapic_ack_level_irq           nop
 412
 413 struct irq_chip irq_type_iosapic_level = {
 414         .name =         "IO-SAPIC-level",
 415         .startup =      iosapic_startup_level_irq,
 416         .shutdown =     iosapic_shutdown_level_irq,
 417         .enable =       iosapic_enable_level_irq,
 418         .disable =      iosapic_disable_level_irq,
 419         .ack =          iosapic_ack_level_irq,
 420         .end =          iosapic_end_level_irq,
 421         .mask =         mask_irq,
 422         .unmask =       unmask_irq,
 423         .set_affinity = iosapic_set_affinity
 424 };
 425
 426 /*
 427  * Handlers for edge-triggered interrupts.
 428  */
 429
 430 static unsigned int
 431 iosapic_startup_edge_irq (unsigned int irq)
 432 {
 433         unmask_irq(irq);
 434         /*
 435          * IOSAPIC simply drops interrupts pended while the
 436          * corresponding pin was masked, so we can't know if an
 437          * interrupt is pending already.  Let's hope not...
 438          */
 439         return 0;
 440 }
 441
 442 static void
 443 iosapic_ack_edge_irq (unsigned int irq)
 444 {
 445         irq_desc_t *idesc = irq_desc + irq;
 446
 447         move_native_irq(irq);
 448         /*
 449          * Once we have recorded IRQ_PENDING already, we can mask the
 450          * interrupt for real. This prevents IRQ storms from unhandled
 451          * devices.
 452          */
 453         if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
 454             (IRQ_PENDING|IRQ_DISABLED))
 455                 mask_irq(irq);
 456 }
 457
 458 #define iosapic_enable_edge_irq         unmask_irq
 459 #define iosapic_disable_edge_irq        nop
 460 #define iosapic_end_edge_irq            nop
 461
 462 struct irq_chip irq_type_iosapic_edge = {
 463         .name =         "IO-SAPIC-edge",
 464         .startup =      iosapic_startup_edge_irq,
 465         .shutdown =     iosapic_disable_edge_irq,
 466         .enable =       iosapic_enable_edge_irq,
 467         .disable =      iosapic_disable_edge_irq,
 468         .ack =          iosapic_ack_edge_irq,
 469         .end =          iosapic_end_edge_irq,
 470         .mask =         mask_irq,
 471         .unmask =       unmask_irq,
 472         .set_affinity = iosapic_set_affinity
 473 };
 474
 475 unsigned int
 476 iosapic_version (char __iomem *addr)
 477 {
 478         /*
 479          * IOSAPIC Version Register return 32 bit structure like:
 480          * {
 481          *      unsigned int version   : 8;
 482          *      unsigned int reserved1 : 8;
 483          *      unsigned int max_redir : 8;
 484          *      unsigned int reserved2 : 8;
 485          * }
 486          */
 487         return __iosapic_read(addr, IOSAPIC_VERSION);
 488 }
 489
 490 static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
 491 {
 492         int i, irq = -ENOSPC, min_count = -1;
 493         struct iosapic_intr_info *info;
 494
 495         /*
 496          * shared vectors for edge-triggered interrupts are not
 497          * supported yet
 498          */
 499         if (trigger == IOSAPIC_EDGE)
 500                 return -EINVAL;
 501
 502         for (i = 0; i <= NR_IRQS; i++) {
 503                 info = &iosapic_intr_info[i];
 504                 if (info->trigger == trigger && info->polarity == pol &&
 505                     (info->dmode == IOSAPIC_FIXED || info->dmode ==
 506                      IOSAPIC_LOWEST_PRIORITY)) {
 507                         if (min_count == -1 || info->count < min_count) {
 508                                 irq = i;
 509                                 min_count = info->count;
 510                         }
 511                 }
 512         }
 513         return irq;
 514 }
 515
 516 /*
 517  * if the given vector is already owned by other,
 518  *  assign a new vector for the other and make the vector available
 519  */
 520 static void __init
 521 iosapic_reassign_vector (int irq)
 522 {
 523         int new_irq;
 524
 525         if (!list_empty(&iosapic_intr_info[irq].rtes)) {
 526                 new_irq = create_irq();
 527                 if (new_irq < 0)
 528                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 529                 printk(KERN_INFO "Reassigning vector %d to %d\n",
 530                        irq_to_vector(irq), irq_to_vector(new_irq));
 531                 memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq],
 532                        sizeof(struct iosapic_intr_info));
 533                 INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes);
 534                 list_move(iosapic_intr_info[irq].rtes.next,
 535                           &iosapic_intr_info[new_irq].rtes);
 536                 memset(&iosapic_intr_info[irq], 0,
 537                        sizeof(struct iosapic_intr_info));
 538                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
 539                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 540         }
 541 }
 542
 543 static struct iosapic_rte_info *iosapic_alloc_rte (void)
 544 {
 545         int i;
 546         struct iosapic_rte_info *rte;
 547         int preallocated = 0;
 548
 549         if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
 550                 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
 551                                     NR_PREALLOCATE_RTE_ENTRIES);
 552                 if (!rte)
 553                         return NULL;
 554                 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
 555                         list_add(&rte->rte_list, &free_rte_list);
 556         }
 557
 558         if (!list_empty(&free_rte_list)) {
 559                 rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
 560                                  rte_list);
 561                 list_del(&rte->rte_list);
 562                 preallocated++;
 563         } else {
 564                 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
 565                 if (!rte)
 566                         return NULL;
 567         }
 568
 569         memset(rte, 0, sizeof(struct iosapic_rte_info));
 570         if (preallocated)
 571                 rte->flags |= RTE_PREALLOCATED;
 572
 573         return rte;
 574 }
 575
 576 static void iosapic_free_rte (struct iosapic_rte_info *rte)
 577 {
 578         if (rte->flags & RTE_PREALLOCATED)
 579                 list_add_tail(&rte->rte_list, &free_rte_list);
 580         else
 581                 kfree(rte);
 582 }
 583
 584 static inline int irq_is_shared (int irq)
 585 {
 586         return (iosapic_intr_info[irq].count > 1);
 587 }
 588
 589 static int
 590 register_intr (unsigned int gsi, int irq, unsigned char delivery,
 591                unsigned long polarity, unsigned long trigger)
 592 {
 593         irq_desc_t *idesc;
 594         struct hw_interrupt_type *irq_type;
 595         int index;
 596         struct iosapic_rte_info *rte;
 597
 598         index = find_iosapic(gsi);
 599         if (index < 0) {
 600                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
 601                        __FUNCTION__, gsi);
 602                 return -ENODEV;
 603         }
 604
 605         rte = find_rte(irq, gsi);
 606         if (!rte) {
 607                 rte = iosapic_alloc_rte();
 608                 if (!rte) {
 609                         printk(KERN_WARNING "%s: cannot allocate memory\n",
 610                                __FUNCTION__);
 611                         return -ENOMEM;
 612                 }
 613
 614                 rte->iosapic    = &iosapic_lists[index];
 615                 rte->rte_index  = gsi - rte->iosapic->gsi_base;
 616                 rte->refcnt++;
 617                 list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes);
 618                 iosapic_intr_info[irq].count++;
 619                 iosapic_lists[index].rtes_inuse++;
 620         }
 621         else if (irq_is_shared(irq)) {
 622                 struct iosapic_intr_info *info = &iosapic_intr_info[irq];
 623                 if (info->trigger != trigger || info->polarity != polarity) {
 624                         printk (KERN_WARNING
 625                                 "%s: cannot override the interrupt\n",
 626                                 __FUNCTION__);
 627                         return -EINVAL;
 628                 }
 629         }
 630
 631         iosapic_intr_info[irq].polarity = polarity;
 632         iosapic_intr_info[irq].dmode    = delivery;
 633         iosapic_intr_info[irq].trigger  = trigger;
 634
 635         if (trigger == IOSAPIC_EDGE)
 636                 irq_type = &irq_type_iosapic_edge;
 637         else
 638                 irq_type = &irq_type_iosapic_level;
 639
 640         idesc = irq_desc + irq;
 641         if (idesc->chip != irq_type) {
 642                 if (idesc->chip != &no_irq_type)
 643                         printk(KERN_WARNING
 644                                "%s: changing vector %d from %s to %s\n",
 645                                __FUNCTION__, irq_to_vector(irq),
 646                                idesc->chip->name, irq_type->name);
 647                 idesc->chip = irq_type;
 648         }
 649         return 0;
 650 }
 651
 652 static unsigned int
 653 get_target_cpu (unsigned int gsi, int irq)
 654 {
 655 #ifdef CONFIG_SMP
 656         static int cpu = -1;
 657         extern int cpe_vector;
 658
 659         /*
 660          * In case of vector shared by multiple RTEs, all RTEs that
 661          * share the vector need to use the same destination CPU.
 662          */
 663         if (!list_empty(&iosapic_intr_info[irq].rtes))
 664                 return iosapic_intr_info[irq].dest;
 665
 666         /*
 667          * If the platform supports redirection via XTP, let it
 668          * distribute interrupts.
 669          */
 670         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
 671                 return cpu_physical_id(smp_processor_id());
 672
 673         /*
 674          * Some interrupts (ACPI SCI, for instance) are registered
 675          * before the BSP is marked as online.
 676          */
 677         if (!cpu_online(smp_processor_id()))
 678                 return cpu_physical_id(smp_processor_id());
 679
 680 #ifdef CONFIG_ACPI
 681         if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR)
 682                 return get_cpei_target_cpu();
 683 #endif
 684
 685 #ifdef CONFIG_NUMA
 686         {
 687                 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
 688                 cpumask_t cpu_mask;
 689
 690                 iosapic_index = find_iosapic(gsi);
 691                 if (iosapic_index < 0 ||
 692                     iosapic_lists[iosapic_index].node == MAX_NUMNODES)
 693                         goto skip_numa_setup;
 694
 695                 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
 696
 697                 for_each_cpu_mask(numa_cpu, cpu_mask) {
 698                         if (!cpu_online(numa_cpu))
 699                                 cpu_clear(numa_cpu, cpu_mask);
 700                 }
 701
 702                 num_cpus = cpus_weight(cpu_mask);
 703
 704                 if (!num_cpus)
 705                         goto skip_numa_setup;
 706
 707                 /* Use irq assignment to distribute across cpus in node */
 708                 cpu_index = irq % num_cpus;
 709
 710                 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
 711                         numa_cpu = next_cpu(numa_cpu, cpu_mask);
 712
 713                 if (numa_cpu != NR_CPUS)
 714                         return cpu_physical_id(numa_cpu);
 715         }
 716 skip_numa_setup:
 717 #endif
 718         /*
 719          * Otherwise, round-robin interrupt vectors across all the
 720          * processors.  (It'd be nice if we could be smarter in the
 721          * case of NUMA.)
 722          */
 723         do {
 724                 if (++cpu >= NR_CPUS)
 725                         cpu = 0;
 726         } while (!cpu_online(cpu));
 727
 728         return cpu_physical_id(cpu);
 729 #else  /* CONFIG_SMP */
 730         return cpu_physical_id(smp_processor_id());
 731 #endif
 732 }
 733
 734 /*
 735  * ACPI can describe IOSAPIC interrupts via static tables and namespace
 736  * methods.  This provides an interface to register those interrupts and
 737  * program the IOSAPIC RTE.
 738  */
 739 int
 740 iosapic_register_intr (unsigned int gsi,
 741                        unsigned long polarity, unsigned long trigger)
 742 {
 743         int irq, mask = 1, err;
 744         unsigned int dest;
 745         unsigned long flags;
 746         struct iosapic_rte_info *rte;
 747         u32 low32;
 748
 749         /*
 750          * If this GSI has already been registered (i.e., it's a
 751          * shared interrupt, or we lost a race to register it),
 752          * don't touch the RTE.
 753          */
 754         spin_lock_irqsave(&iosapic_lock, flags);
 755         irq = __gsi_to_irq(gsi);
 756         if (irq > 0) {
 757                 rte = find_rte(irq, gsi);
 758                 rte->refcnt++;
 759                 goto unlock_iosapic_lock;
 760         }
 761
 762         /* If vector is running out, we try to find a sharable vector */
 763         irq = create_irq();
 764         if (irq < 0) {
 765                 irq = iosapic_find_sharable_irq(trigger, polarity);
 766                 if (irq < 0)
 767                         goto unlock_iosapic_lock;
 768         }
 769
 770         spin_lock(&irq_desc[irq].lock);
 771         dest = get_target_cpu(gsi, irq);
 772         err = register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY,
 773                             polarity, trigger);
 774         if (err < 0) {
 775                 irq = err;
 776                 goto unlock_all;
 777         }
 778
 779         /*
 780          * If the vector is shared and already unmasked for other
 781          * interrupt sources, don't mask it.
 782          */
 783         low32 = iosapic_intr_info[irq].low32;
 784         if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK))
 785                 mask = 0;
 786         set_rte(gsi, irq, dest, mask);
 787
 788         printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
 789                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 790                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 791                cpu_logical_id(dest), dest, irq_to_vector(irq));
 792  unlock_all:
 793         spin_unlock(&irq_desc[irq].lock);
 794  unlock_iosapic_lock:
 795         spin_unlock_irqrestore(&iosapic_lock, flags);
 796         return irq;
 797 }
 798
 799 void
 800 iosapic_unregister_intr (unsigned int gsi)
 801 {
 802         unsigned long flags;
 803         int irq, index;
 804         irq_desc_t *idesc;
 805         u32 low32;
 806         unsigned long trigger, polarity;
 807         unsigned int dest;
 808         struct iosapic_rte_info *rte;
 809
 810         /*
 811          * If the irq associated with the gsi is not found,
 812          * iosapic_unregister_intr() is unbalanced. We need to check
 813          * this again after getting locks.
 814          */
 815         irq = gsi_to_irq(gsi);
 816         if (irq < 0) {
 817                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 818                        gsi);
 819                 WARN_ON(1);
 820                 return;
 821         }
 822
 823         spin_lock_irqsave(&iosapic_lock, flags);
 824         if ((rte = find_rte(irq, gsi)) == NULL) {
 825                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 826                        gsi);
 827                 WARN_ON(1);
 828                 goto out;
 829         }
 830
 831         if (--rte->refcnt > 0)
 832                 goto out;
 833
 834         /* Remove the rte entry from the list */
 835         idesc = irq_desc + irq;
 836         spin_lock(&idesc->lock);
 837         list_del(&rte->rte_list);
 838         spin_unlock(&idesc->lock);
 839
 840         /* Mask the interrupt */
 841         low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK;
 842         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32);
 843
 844         iosapic_intr_info[irq].count--;
 845         iosapic_free_rte(rte);
 846         index = find_iosapic(gsi);
 847         iosapic_lists[index].rtes_inuse--;
 848         WARN_ON(iosapic_lists[index].rtes_inuse < 0);
 849
 850         trigger  = iosapic_intr_info[irq].trigger;
 851         polarity = iosapic_intr_info[irq].polarity;
 852         dest     = iosapic_intr_info[irq].dest;
 853         printk(KERN_INFO
 854                "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
 855                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 856                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 857                cpu_logical_id(dest), dest, irq_to_vector(irq));
 858
 859         if (list_empty(&iosapic_intr_info[irq].rtes)) {
 860                 /* Sanity check */
 861                 BUG_ON(iosapic_intr_info[irq].count);
 862 #ifdef CONFIG_SMP
 863                 /* Clear affinity */
 864                 cpus_setall(idesc->affinity);
 865 #endif
 866                 /* Clear the interrupt information */
 867                 memset(&iosapic_intr_info[irq], 0,
 868                        sizeof(struct iosapic_intr_info));
 869                 iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
 870                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 871
 872                 /* Destroy IRQ */
 873                 destroy_irq(irq);
 874         }
 875  out:
 876         spin_unlock_irqrestore(&iosapic_lock, flags);
 877 }
 878
 879 /*
 880  * ACPI calls this when it finds an entry for a platform interrupt.
 881  */
 882 int __init
 883 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
 884                                 int iosapic_vector, u16 eid, u16 id,
 885                                 unsigned long polarity, unsigned long trigger)
 886 {
 887         static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
 888         unsigned char delivery;
 889         int irq, vector, mask = 0;
 890         unsigned int dest = ((id << 8) | eid) & 0xffff;
 891
 892         switch (int_type) {
 893               case ACPI_INTERRUPT_PMI:
 894                 vector = iosapic_vector;
 895                 irq = vector;           /* FIXME */
 896                 /*
 897                  * since PMI vector is alloc'd by FW(ACPI) not by kernel,
 898                  * we need to make sure the vector is available
 899                  */
 900                 iosapic_reassign_vector(irq);
 901                 delivery = IOSAPIC_PMI;
 902                 break;
 903               case ACPI_INTERRUPT_INIT:
 904                 irq = create_irq();
 905                 if (irq < 0)
 906                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 907                 vector = irq_to_vector(irq);
 908                 delivery = IOSAPIC_INIT;
 909                 break;
 910               case ACPI_INTERRUPT_CPEI:
 911                 vector = IA64_CPE_VECTOR;
 912                 irq = vector;           /* FIXME */
 913                 delivery = IOSAPIC_LOWEST_PRIORITY;
 914                 mask = 1;
 915                 break;
 916               default:
 917                 printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__,
 918                        int_type);
 919                 return -1;
 920         }
 921
 922         register_intr(gsi, irq, delivery, polarity, trigger);
 923
 924         printk(KERN_INFO
 925                "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
 926                " vector %d\n",
 927                int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
 928                int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 929                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 930                cpu_logical_id(dest), dest, vector);
 931
 932         set_rte(gsi, irq, dest, mask);
 933         return vector;
 934 }
 935
 936 /*
 937  * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
 938  */
 939 void __devinit
 940 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
 941                           unsigned long polarity,
 942                           unsigned long trigger)
 943 {
 944         int vector, irq;
 945         unsigned int dest = cpu_physical_id(smp_processor_id());
 946
 947         vector = isa_irq_to_vector(isa_irq);
 948         irq = vector;   /* FIXME */
 949         register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
 950
 951         DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
 952             isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
 953             polarity == IOSAPIC_POL_HIGH ? "high" : "low",
 954             cpu_logical_id(dest), dest, vector);
 955
 956         set_rte(gsi, irq, dest, 1);
 957 }
 958
 959 void __init
 960 iosapic_system_init (int system_pcat_compat)
 961 {
 962         int irq;
 963
 964         for (irq = 0; irq < NR_IRQS; ++irq) {
 965                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
 966                 /* mark as unused */
 967                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 968         }
 969
 970         pcat_compat = system_pcat_compat;
 971         if (pcat_compat) {
 972                 /*
 973                  * Disable the compatibility mode interrupts (8259 style),
 974                  * needs IN/OUT support enabled.
 975                  */
 976                 printk(KERN_INFO
 977                        "%s: Disabling PC-AT compatible 8259 interrupts\n",
 978                        __FUNCTION__);
 979                 outb(0xff, 0xA1);
 980                 outb(0xff, 0x21);
 981         }
 982 }
 983
 984 static inline int
 985 iosapic_alloc (void)
 986 {
 987         int index;
 988
 989         for (index = 0; index < NR_IOSAPICS; index++)
 990                 if (!iosapic_lists[index].addr)
 991                         return index;
 992
 993         printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__);
 994         return -1;
 995 }
 996
 997 static inline void
 998 iosapic_free (int index)
 999 {
1000         memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
1001 }
1002
1003 static inline int
1004 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1005 {
1006         int index;
1007         unsigned int gsi_end, base, end;
1008
1009         /* check gsi range */
1010         gsi_end = gsi_base + ((ver >> 16) & 0xff);
1011         for (index = 0; index < NR_IOSAPICS; index++) {
1012                 if (!iosapic_lists[index].addr)
1013                         continue;
1014
1015                 base = iosapic_lists[index].gsi_base;
1016                 end  = base + iosapic_lists[index].num_rte - 1;
1017
1018                 if (gsi_end < base || end < gsi_base)
1019                         continue; /* OK */
1020
1021                 return -EBUSY;
1022         }
1023         return 0;
1024 }
1025
1026 int __devinit
1027 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1028 {
1029         int num_rte, err, index;
1030         unsigned int isa_irq, ver;
1031         char __iomem *addr;
1032         unsigned long flags;
1033
1034         spin_lock_irqsave(&iosapic_lock, flags);
1035         index = find_iosapic(gsi_base);
1036         if (index >= 0) {
1037                 spin_unlock_irqrestore(&iosapic_lock, flags);
1038                 return -EBUSY;
1039         }
1040
1041         addr = ioremap(phys_addr, 0);
1042         ver = iosapic_version(addr);
1043         if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1044                 iounmap(addr);
1045                 spin_unlock_irqrestore(&iosapic_lock, flags);
1046                 return err;
1047         }
1048
1049         /*
1050          * The MAX_REDIR register holds the highest input pin number
1051          * (starting from 0).  We add 1 so that we can use it for
1052          * number of pins (= RTEs)
1053          */
1054         num_rte = ((ver >> 16) & 0xff) + 1;
1055
1056         index = iosapic_alloc();
1057         iosapic_lists[index].addr = addr;
1058         iosapic_lists[index].gsi_base = gsi_base;
1059         iosapic_lists[index].num_rte = num_rte;
1060 #ifdef CONFIG_NUMA
1061         iosapic_lists[index].node = MAX_NUMNODES;
1062 #endif
1063         spin_lock_init(&iosapic_lists[index].lock);
1064         spin_unlock_irqrestore(&iosapic_lock, flags);
1065
1066         if ((gsi_base == 0) && pcat_compat) {
1067                 /*
1068                  * Map the legacy ISA devices into the IOSAPIC data.  Some of
1069                  * these may get reprogrammed later on with data from the ACPI
1070                  * Interrupt Source Override table.
1071                  */
1072                 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1073                         iosapic_override_isa_irq(isa_irq, isa_irq,
1074                                                  IOSAPIC_POL_HIGH,
1075                                                  IOSAPIC_EDGE);
1076         }
1077         return 0;
1078 }
1079
1080 #ifdef CONFIG_HOTPLUG
1081 int
1082 iosapic_remove (unsigned int gsi_base)
1083 {
1084         int index, err = 0;
1085         unsigned long flags;
1086
1087         spin_lock_irqsave(&iosapic_lock, flags);
1088         index = find_iosapic(gsi_base);
1089         if (index < 0) {
1090                 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1091                        __FUNCTION__, gsi_base);
1092                 goto out;
1093         }
1094
1095         if (iosapic_lists[index].rtes_inuse) {
1096                 err = -EBUSY;
1097                 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1098                        __FUNCTION__, gsi_base);
1099                 goto out;
1100         }
1101
1102         iounmap(iosapic_lists[index].addr);
1103         iosapic_free(index);
1104  out:
1105         spin_unlock_irqrestore(&iosapic_lock, flags);
1106         return err;
1107 }
1108 #endif /* CONFIG_HOTPLUG */
1109
1110 #ifdef CONFIG_NUMA
1111 void __devinit
1112 map_iosapic_to_node(unsigned int gsi_base, int node)
1113 {
1114         int index;
1115
1116         index = find_iosapic(gsi_base);
1117         if (index < 0) {
1118                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1119                        __FUNCTION__, gsi_base);
1120                 return;
1121         }
1122         iosapic_lists[index].node = node;
1123         return;
1124 }
1125 #endif
1126
1127 static int __init iosapic_enable_kmalloc (void)
1128 {
1129         iosapic_kmalloc_ok = 1;
1130         return 0;
1131 }
1132 core_initcall (iosapic_enable_kmalloc);