drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 static void assert_pll(struct drm_i915_private *dev_priv,
 896                        enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 911
 912 /* For ILK+ */
 913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 914                            struct intel_pch_pll *pll,
 915                            struct intel_crtc *crtc,
 916                            bool state)
 917 {
 918         u32 val;
 919         bool cur_state;
 920
 921         if (HAS_PCH_LPT(dev_priv->dev)) {
 922                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 923                 return;
 924         }
 925
 926         if (WARN (!pll,
 927                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 928                 return;
 929
 930         val = I915_READ(pll->pll_reg);
 931         cur_state = !!(val & DPLL_VCO_ENABLE);
 932         WARN(cur_state != state,
 933              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 934              pll->pll_reg, state_string(state), state_string(cur_state), val);
 935
 936         /* Make sure the selected PLL is correctly attached to the transcoder */
 937         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 938                 u32 pch_dpll;
 939
 940                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 941                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 942                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 943                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 944                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 945                         cur_state = !!(val >> (4*crtc->pipe + 3));
 946                         WARN(cur_state != state,
 947                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 948                              pll->pll_reg == _PCH_DPLL_B,
 949                              state_string(state),
 950                              pipe_name(crtc->pipe),
 951                              val);
 952                 }
 953         }
 954 }
 955 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 956 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 957
 958 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 959                           enum pipe pipe, bool state)
 960 {
 961         int reg;
 962         u32 val;
 963         bool cur_state;
 964         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 965                                                                       pipe);
 966
 967         if (HAS_DDI(dev_priv->dev)) {
 968                 /* DDI does not have a specific FDI_TX register */
 969                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 970                 val = I915_READ(reg);
 971                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 972         } else {
 973                 reg = FDI_TX_CTL(pipe);
 974                 val = I915_READ(reg);
 975                 cur_state = !!(val & FDI_TX_ENABLE);
 976         }
 977         WARN(cur_state != state,
 978              "FDI TX state assertion failure (expected %s, current %s)\n",
 979              state_string(state), state_string(cur_state));
 980 }
 981 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 982 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 983
 984 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 985                           enum pipe pipe, bool state)
 986 {
 987         int reg;
 988         u32 val;
 989         bool cur_state;
 990
 991         reg = FDI_RX_CTL(pipe);
 992         val = I915_READ(reg);
 993         cur_state = !!(val & FDI_RX_ENABLE);
 994         WARN(cur_state != state,
 995              "FDI RX state assertion failure (expected %s, current %s)\n",
 996              state_string(state), state_string(cur_state));
 997 }
 998 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 999 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         /* ILK FDI PLL is always enabled */
1008         if (dev_priv->info->gen == 5)
1009                 return;
1010
1011         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1012         if (HAS_DDI(dev_priv->dev))
1013                 return;
1014
1015         reg = FDI_TX_CTL(pipe);
1016         val = I915_READ(reg);
1017         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018 }
1019
1020 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         reg = FDI_RX_CTL(pipe);
1027         val = I915_READ(reg);
1028         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029 }
1030
1031 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032                                   enum pipe pipe)
1033 {
1034         int pp_reg, lvds_reg;
1035         u32 val;
1036         enum pipe panel_pipe = PIPE_A;
1037         bool locked = true;
1038
1039         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040                 pp_reg = PCH_PP_CONTROL;
1041                 lvds_reg = PCH_LVDS;
1042         } else {
1043                 pp_reg = PP_CONTROL;
1044                 lvds_reg = LVDS;
1045         }
1046
1047         val = I915_READ(pp_reg);
1048         if (!(val & PANEL_POWER_ON) ||
1049             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050                 locked = false;
1051
1052         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053                 panel_pipe = PIPE_B;
1054
1055         WARN(panel_pipe == pipe && locked,
1056              "panel assertion failure, pipe %c regs locked\n",
1057              pipe_name(pipe));
1058 }
1059
1060 void assert_pipe(struct drm_i915_private *dev_priv,
1061                  enum pipe pipe, bool state)
1062 {
1063         int reg;
1064         u32 val;
1065         bool cur_state;
1066         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067                                                                       pipe);
1068
1069         /* if we need the pipe A quirk it must be always on */
1070         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071                 state = true;
1072
1073         if (!intel_display_power_enabled(dev_priv->dev,
1074                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1075                 cur_state = false;
1076         } else {
1077                 reg = PIPECONF(cpu_transcoder);
1078                 val = I915_READ(reg);
1079                 cur_state = !!(val & PIPECONF_ENABLE);
1080         }
1081
1082         WARN(cur_state != state,
1083              "pipe %c assertion failure (expected %s, current %s)\n",
1084              pipe_name(pipe), state_string(state), state_string(cur_state));
1085 }
1086
1087 static void assert_plane(struct drm_i915_private *dev_priv,
1088                          enum plane plane, bool state)
1089 {
1090         int reg;
1091         u32 val;
1092         bool cur_state;
1093
1094         reg = DSPCNTR(plane);
1095         val = I915_READ(reg);
1096         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097         WARN(cur_state != state,
1098              "plane %c assertion failure (expected %s, current %s)\n",
1099              plane_name(plane), state_string(state), state_string(cur_state));
1100 }
1101
1102 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
1105 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106                                    enum pipe pipe)
1107 {
1108         struct drm_device *dev = dev_priv->dev;
1109         int reg, i;
1110         u32 val;
1111         int cur_pipe;
1112
1113         /* Primary planes are fixed to pipes on gen4+ */
1114         if (INTEL_INFO(dev)->gen >= 4) {
1115                 reg = DSPCNTR(pipe);
1116                 val = I915_READ(reg);
1117                 WARN((val & DISPLAY_PLANE_ENABLE),
1118                      "plane %c assertion failure, should be disabled but not\n",
1119                      plane_name(pipe));
1120                 return;
1121         }
1122
1123         /* Need to check both planes against the pipe */
1124         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1125                 reg = DSPCNTR(i);
1126                 val = I915_READ(reg);
1127                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1128                         DISPPLANE_SEL_PIPE_SHIFT;
1129                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1130                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1131                      plane_name(i), pipe_name(pipe));
1132         }
1133 }
1134
1135 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1136                                     enum pipe pipe)
1137 {
1138         struct drm_device *dev = dev_priv->dev;
1139         int reg, i;
1140         u32 val;
1141
1142         if (IS_VALLEYVIEW(dev)) {
1143                 for (i = 0; i < dev_priv->num_plane; i++) {
1144                         reg = SPCNTR(pipe, i);
1145                         val = I915_READ(reg);
1146                         WARN((val & SP_ENABLE),
1147                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1148                              sprite_name(pipe, i), pipe_name(pipe));
1149                 }
1150         } else if (INTEL_INFO(dev)->gen >= 7) {
1151                 reg = SPRCTL(pipe);
1152                 val = I915_READ(reg);
1153                 WARN((val & SPRITE_ENABLE),
1154                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1155                      plane_name(pipe), pipe_name(pipe));
1156         } else if (INTEL_INFO(dev)->gen >= 5) {
1157                 reg = DVSCNTR(pipe);
1158                 val = I915_READ(reg);
1159                 WARN((val & DVS_ENABLE),
1160                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1161                      plane_name(pipe), pipe_name(pipe));
1162         }
1163 }
1164
1165 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1166 {
1167         u32 val;
1168         bool enabled;
1169
1170         if (HAS_PCH_LPT(dev_priv->dev)) {
1171                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1172                 return;
1173         }
1174
1175         val = I915_READ(PCH_DREF_CONTROL);
1176         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1177                             DREF_SUPERSPREAD_SOURCE_MASK));
1178         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1179 }
1180
1181 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1182                                            enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186         bool enabled;
1187
1188         reg = PCH_TRANSCONF(pipe);
1189         val = I915_READ(reg);
1190         enabled = !!(val & TRANS_ENABLE);
1191         WARN(enabled,
1192              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1193              pipe_name(pipe));
1194 }
1195
1196 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1197                             enum pipe pipe, u32 port_sel, u32 val)
1198 {
1199         if ((val & DP_PORT_EN) == 0)
1200                 return false;
1201
1202         if (HAS_PCH_CPT(dev_priv->dev)) {
1203                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1204                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1205                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1206                         return false;
1207         } else {
1208                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1209                         return false;
1210         }
1211         return true;
1212 }
1213
1214 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1215                               enum pipe pipe, u32 val)
1216 {
1217         if ((val & SDVO_ENABLE) == 0)
1218                 return false;
1219
1220         if (HAS_PCH_CPT(dev_priv->dev)) {
1221                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1222                         return false;
1223         } else {
1224                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1225                         return false;
1226         }
1227         return true;
1228 }
1229
1230 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1231                               enum pipe pipe, u32 val)
1232 {
1233         if ((val & LVDS_PORT_EN) == 0)
1234                 return false;
1235
1236         if (HAS_PCH_CPT(dev_priv->dev)) {
1237                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238                         return false;
1239         } else {
1240                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1241                         return false;
1242         }
1243         return true;
1244 }
1245
1246 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1247                               enum pipe pipe, u32 val)
1248 {
1249         if ((val & ADPA_DAC_ENABLE) == 0)
1250                 return false;
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1253                         return false;
1254         } else {
1255                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1256                         return false;
1257         }
1258         return true;
1259 }
1260
1261 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1262                                    enum pipe pipe, int reg, u32 port_sel)
1263 {
1264         u32 val = I915_READ(reg);
1265         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1266              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1267              reg, pipe_name(pipe));
1268
1269         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1270              && (val & DP_PIPEB_SELECT),
1271              "IBX PCH dp port still using transcoder B\n");
1272 }
1273
1274 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1275                                      enum pipe pipe, int reg)
1276 {
1277         u32 val = I915_READ(reg);
1278         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1279              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1280              reg, pipe_name(pipe));
1281
1282         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1283              && (val & SDVO_PIPE_B_SELECT),
1284              "IBX PCH hdmi port still using transcoder B\n");
1285 }
1286
1287 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1288                                       enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val;
1292
1293         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1294         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1295         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1296
1297         reg = PCH_ADPA;
1298         val = I915_READ(reg);
1299         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1300              "PCH VGA enabled on transcoder %c, should be disabled\n",
1301              pipe_name(pipe));
1302
1303         reg = PCH_LVDS;
1304         val = I915_READ(reg);
1305         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1306              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1307              pipe_name(pipe));
1308
1309         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1310         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1311         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1312 }
1313
1314 /**
1315  * intel_enable_pll - enable a PLL
1316  * @dev_priv: i915 private structure
1317  * @pipe: pipe PLL to enable
1318  *
1319  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1320  * make sure the PLL reg is writable first though, since the panel write
1321  * protect mechanism may be enabled.
1322  *
1323  * Note!  This is for pre-ILK only.
1324  *
1325  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1326  */
1327 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1328 {
1329         int reg;
1330         u32 val;
1331
1332         assert_pipe_disabled(dev_priv, pipe);
1333
1334         /* No really, not for ILK+ */
1335         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1336
1337         /* PLL is protected by panel, make sure we can write it */
1338         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1339                 assert_panel_unlocked(dev_priv, pipe);
1340
1341         reg = DPLL(pipe);
1342         val = I915_READ(reg);
1343         val |= DPLL_VCO_ENABLE;
1344
1345         /* We do this three times for luck */
1346         I915_WRITE(reg, val);
1347         POSTING_READ(reg);
1348         udelay(150); /* wait for warmup */
1349         I915_WRITE(reg, val);
1350         POSTING_READ(reg);
1351         udelay(150); /* wait for warmup */
1352         I915_WRITE(reg, val);
1353         POSTING_READ(reg);
1354         udelay(150); /* wait for warmup */
1355 }
1356
1357 /**
1358  * intel_disable_pll - disable a PLL
1359  * @dev_priv: i915 private structure
1360  * @pipe: pipe PLL to disable
1361  *
1362  * Disable the PLL for @pipe, making sure the pipe is off first.
1363  *
1364  * Note!  This is for pre-ILK only.
1365  */
1366 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1367 {
1368         int reg;
1369         u32 val;
1370
1371         /* Don't disable pipe A or pipe A PLLs if needed */
1372         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1373                 return;
1374
1375         /* Make sure the pipe isn't still relying on us */
1376         assert_pipe_disabled(dev_priv, pipe);
1377
1378         reg = DPLL(pipe);
1379         val = I915_READ(reg);
1380         val &= ~DPLL_VCO_ENABLE;
1381         I915_WRITE(reg, val);
1382         POSTING_READ(reg);
1383 }
1384
1385 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1386 {
1387         u32 port_mask;
1388
1389         if (!port)
1390                 port_mask = DPLL_PORTB_READY_MASK;
1391         else
1392                 port_mask = DPLL_PORTC_READY_MASK;
1393
1394         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1395                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1396                      'B' + port, I915_READ(DPLL(0)));
1397 }
1398
1399 /**
1400  * ironlake_enable_pch_pll - enable PCH PLL
1401  * @dev_priv: i915 private structure
1402  * @pipe: pipe PLL to enable
1403  *
1404  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1405  * drives the transcoder clock.
1406  */
1407 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1408 {
1409         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1410         struct intel_pch_pll *pll;
1411         int reg;
1412         u32 val;
1413
1414         /* PCH PLLs only available on ILK, SNB and IVB */
1415         BUG_ON(dev_priv->info->gen < 5);
1416         pll = intel_crtc->pch_pll;
1417         if (pll == NULL)
1418                 return;
1419
1420         if (WARN_ON(pll->refcount == 0))
1421                 return;
1422
1423         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1424                       pll->pll_reg, pll->active, pll->on,
1425                       intel_crtc->base.base.id);
1426
1427         /* PCH refclock must be enabled first */
1428         assert_pch_refclk_enabled(dev_priv);
1429
1430         if (pll->active++ && pll->on) {
1431                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1432                 return;
1433         }
1434
1435         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1436
1437         reg = pll->pll_reg;
1438         val = I915_READ(reg);
1439         val |= DPLL_VCO_ENABLE;
1440         I915_WRITE(reg, val);
1441         POSTING_READ(reg);
1442         udelay(200);
1443
1444         pll->on = true;
1445 }
1446
1447 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1448 {
1449         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1450         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1451         int reg;
1452         u32 val;
1453
1454         /* PCH only available on ILK+ */
1455         BUG_ON(dev_priv->info->gen < 5);
1456         if (pll == NULL)
1457                return;
1458
1459         if (WARN_ON(pll->refcount == 0))
1460                 return;
1461
1462         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1463                       pll->pll_reg, pll->active, pll->on,
1464                       intel_crtc->base.base.id);
1465
1466         if (WARN_ON(pll->active == 0)) {
1467                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1468                 return;
1469         }
1470
1471         if (--pll->active) {
1472                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1473                 return;
1474         }
1475
1476         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1477
1478         /* Make sure transcoder isn't still depending on us */
1479         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1480
1481         reg = pll->pll_reg;
1482         val = I915_READ(reg);
1483         val &= ~DPLL_VCO_ENABLE;
1484         I915_WRITE(reg, val);
1485         POSTING_READ(reg);
1486         udelay(200);
1487
1488         pll->on = false;
1489 }
1490
1491 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1492                                            enum pipe pipe)
1493 {
1494         struct drm_device *dev = dev_priv->dev;
1495         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1496         uint32_t reg, val, pipeconf_val;
1497
1498         /* PCH only available on ILK+ */
1499         BUG_ON(dev_priv->info->gen < 5);
1500
1501         /* Make sure PCH DPLL is enabled */
1502         assert_pch_pll_enabled(dev_priv,
1503                                to_intel_crtc(crtc)->pch_pll,
1504                                to_intel_crtc(crtc));
1505
1506         /* FDI must be feeding us bits for PCH ports */
1507         assert_fdi_tx_enabled(dev_priv, pipe);
1508         assert_fdi_rx_enabled(dev_priv, pipe);
1509
1510         if (HAS_PCH_CPT(dev)) {
1511                 /* Workaround: Set the timing override bit before enabling the
1512                  * pch transcoder. */
1513                 reg = TRANS_CHICKEN2(pipe);
1514                 val = I915_READ(reg);
1515                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1516                 I915_WRITE(reg, val);
1517         }
1518
1519         reg = PCH_TRANSCONF(pipe);
1520         val = I915_READ(reg);
1521         pipeconf_val = I915_READ(PIPECONF(pipe));
1522
1523         if (HAS_PCH_IBX(dev_priv->dev)) {
1524                 /*
1525                  * make the BPC in transcoder be consistent with
1526                  * that in pipeconf reg.
1527                  */
1528                 val &= ~PIPECONF_BPC_MASK;
1529                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1530         }
1531
1532         val &= ~TRANS_INTERLACE_MASK;
1533         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1534                 if (HAS_PCH_IBX(dev_priv->dev) &&
1535                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1536                         val |= TRANS_LEGACY_INTERLACED_ILK;
1537                 else
1538                         val |= TRANS_INTERLACED;
1539         else
1540                 val |= TRANS_PROGRESSIVE;
1541
1542         I915_WRITE(reg, val | TRANS_ENABLE);
1543         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1544                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1545 }
1546
1547 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1548                                       enum transcoder cpu_transcoder)
1549 {
1550         u32 val, pipeconf_val;
1551
1552         /* PCH only available on ILK+ */
1553         BUG_ON(dev_priv->info->gen < 5);
1554
1555         /* FDI must be feeding us bits for PCH ports */
1556         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1557         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1558
1559         /* Workaround: set timing override bit. */
1560         val = I915_READ(_TRANSA_CHICKEN2);
1561         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1562         I915_WRITE(_TRANSA_CHICKEN2, val);
1563
1564         val = TRANS_ENABLE;
1565         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1566
1567         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1568             PIPECONF_INTERLACED_ILK)
1569                 val |= TRANS_INTERLACED;
1570         else
1571                 val |= TRANS_PROGRESSIVE;
1572
1573         I915_WRITE(LPT_TRANSCONF, val);
1574         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1575                 DRM_ERROR("Failed to enable PCH transcoder\n");
1576 }
1577
1578 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1579                                             enum pipe pipe)
1580 {
1581         struct drm_device *dev = dev_priv->dev;
1582         uint32_t reg, val;
1583
1584         /* FDI relies on the transcoder */
1585         assert_fdi_tx_disabled(dev_priv, pipe);
1586         assert_fdi_rx_disabled(dev_priv, pipe);
1587
1588         /* Ports must be off as well */
1589         assert_pch_ports_disabled(dev_priv, pipe);
1590
1591         reg = PCH_TRANSCONF(pipe);
1592         val = I915_READ(reg);
1593         val &= ~TRANS_ENABLE;
1594         I915_WRITE(reg, val);
1595         /* wait for PCH transcoder off, transcoder state */
1596         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1597                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1598
1599         if (!HAS_PCH_IBX(dev)) {
1600                 /* Workaround: Clear the timing override chicken bit again. */
1601                 reg = TRANS_CHICKEN2(pipe);
1602                 val = I915_READ(reg);
1603                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1604                 I915_WRITE(reg, val);
1605         }
1606 }
1607
1608 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1609 {
1610         u32 val;
1611
1612         val = I915_READ(LPT_TRANSCONF);
1613         val &= ~TRANS_ENABLE;
1614         I915_WRITE(LPT_TRANSCONF, val);
1615         /* wait for PCH transcoder off, transcoder state */
1616         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1617                 DRM_ERROR("Failed to disable PCH transcoder\n");
1618
1619         /* Workaround: clear timing override bit. */
1620         val = I915_READ(_TRANSA_CHICKEN2);
1621         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1622         I915_WRITE(_TRANSA_CHICKEN2, val);
1623 }
1624
1625 /**
1626  * intel_enable_pipe - enable a pipe, asserting requirements
1627  * @dev_priv: i915 private structure
1628  * @pipe: pipe to enable
1629  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1630  *
1631  * Enable @pipe, making sure that various hardware specific requirements
1632  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1633  *
1634  * @pipe should be %PIPE_A or %PIPE_B.
1635  *
1636  * Will wait until the pipe is actually running (i.e. first vblank) before
1637  * returning.
1638  */
1639 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1640                               bool pch_port)
1641 {
1642         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1643                                                                       pipe);
1644         enum pipe pch_transcoder;
1645         int reg;
1646         u32 val;
1647
1648         assert_planes_disabled(dev_priv, pipe);
1649         assert_sprites_disabled(dev_priv, pipe);
1650
1651         if (HAS_PCH_LPT(dev_priv->dev))
1652                 pch_transcoder = TRANSCODER_A;
1653         else
1654                 pch_transcoder = pipe;
1655
1656         /*
1657          * A pipe without a PLL won't actually be able to drive bits from
1658          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1659          * need the check.
1660          */
1661         if (!HAS_PCH_SPLIT(dev_priv->dev))
1662                 assert_pll_enabled(dev_priv, pipe);
1663         else {
1664                 if (pch_port) {
1665                         /* if driving the PCH, we need FDI enabled */
1666                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1667                         assert_fdi_tx_pll_enabled(dev_priv,
1668                                                   (enum pipe) cpu_transcoder);
1669                 }
1670                 /* FIXME: assert CPU port conditions for SNB+ */
1671         }
1672
1673         reg = PIPECONF(cpu_transcoder);
1674         val = I915_READ(reg);
1675         if (val & PIPECONF_ENABLE)
1676                 return;
1677
1678         I915_WRITE(reg, val | PIPECONF_ENABLE);
1679         intel_wait_for_vblank(dev_priv->dev, pipe);
1680 }
1681
1682 /**
1683  * intel_disable_pipe - disable a pipe, asserting requirements
1684  * @dev_priv: i915 private structure
1685  * @pipe: pipe to disable
1686  *
1687  * Disable @pipe, making sure that various hardware specific requirements
1688  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1689  *
1690  * @pipe should be %PIPE_A or %PIPE_B.
1691  *
1692  * Will wait until the pipe has shut down before returning.
1693  */
1694 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1695                                enum pipe pipe)
1696 {
1697         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1698                                                                       pipe);
1699         int reg;
1700         u32 val;
1701
1702         /*
1703          * Make sure planes won't keep trying to pump pixels to us,
1704          * or we might hang the display.
1705          */
1706         assert_planes_disabled(dev_priv, pipe);
1707         assert_sprites_disabled(dev_priv, pipe);
1708
1709         /* Don't disable pipe A or pipe A PLLs if needed */
1710         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1711                 return;
1712
1713         reg = PIPECONF(cpu_transcoder);
1714         val = I915_READ(reg);
1715         if ((val & PIPECONF_ENABLE) == 0)
1716                 return;
1717
1718         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1719         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1720 }
1721
1722 /*
1723  * Plane regs are double buffered, going from enabled->disabled needs a
1724  * trigger in order to latch.  The display address reg provides this.
1725  */
1726 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1727                                       enum plane plane)
1728 {
1729         if (dev_priv->info->gen >= 4)
1730                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1731         else
1732                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1733 }
1734
1735 /**
1736  * intel_enable_plane - enable a display plane on a given pipe
1737  * @dev_priv: i915 private structure
1738  * @plane: plane to enable
1739  * @pipe: pipe being fed
1740  *
1741  * Enable @plane on @pipe, making sure that @pipe is running first.
1742  */
1743 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1744                                enum plane plane, enum pipe pipe)
1745 {
1746         int reg;
1747         u32 val;
1748
1749         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750         assert_pipe_enabled(dev_priv, pipe);
1751
1752         reg = DSPCNTR(plane);
1753         val = I915_READ(reg);
1754         if (val & DISPLAY_PLANE_ENABLE)
1755                 return;
1756
1757         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1758         intel_flush_display_plane(dev_priv, plane);
1759         intel_wait_for_vblank(dev_priv->dev, pipe);
1760 }
1761
1762 /**
1763  * intel_disable_plane - disable a display plane
1764  * @dev_priv: i915 private structure
1765  * @plane: plane to disable
1766  * @pipe: pipe consuming the data
1767  *
1768  * Disable @plane; should be an independent operation.
1769  */
1770 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1771                                 enum plane plane, enum pipe pipe)
1772 {
1773         int reg;
1774         u32 val;
1775
1776         reg = DSPCNTR(plane);
1777         val = I915_READ(reg);
1778         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1779                 return;
1780
1781         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1782         intel_flush_display_plane(dev_priv, plane);
1783         intel_wait_for_vblank(dev_priv->dev, pipe);
1784 }
1785
1786 static bool need_vtd_wa(struct drm_device *dev)
1787 {
1788 #ifdef CONFIG_INTEL_IOMMU
1789         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1790                 return true;
1791 #endif
1792         return false;
1793 }
1794
1795 int
1796 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1797                            struct drm_i915_gem_object *obj,
1798                            struct intel_ring_buffer *pipelined)
1799 {
1800         struct drm_i915_private *dev_priv = dev->dev_private;
1801         u32 alignment;
1802         int ret;
1803
1804         switch (obj->tiling_mode) {
1805         case I915_TILING_NONE:
1806                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1807                         alignment = 128 * 1024;
1808                 else if (INTEL_INFO(dev)->gen >= 4)
1809                         alignment = 4 * 1024;
1810                 else
1811                         alignment = 64 * 1024;
1812                 break;
1813         case I915_TILING_X:
1814                 /* pin() will align the object as required by fence */
1815                 alignment = 0;
1816                 break;
1817         case I915_TILING_Y:
1818                 /* Despite that we check this in framebuffer_init userspace can
1819                  * screw us over and change the tiling after the fact. Only
1820                  * pinned buffers can't change their tiling. */
1821                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1822                 return -EINVAL;
1823         default:
1824                 BUG();
1825         }
1826
1827         /* Note that the w/a also requires 64 PTE of padding following the
1828          * bo. We currently fill all unused PTE with the shadow page and so
1829          * we should always have valid PTE following the scanout preventing
1830          * the VT-d warning.
1831          */
1832         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1833                 alignment = 256 * 1024;
1834
1835         dev_priv->mm.interruptible = false;
1836         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1837         if (ret)
1838                 goto err_interruptible;
1839
1840         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841          * fence, whereas 965+ only requires a fence if using
1842          * framebuffer compression.  For simplicity, we always install
1843          * a fence as the cost is not that onerous.
1844          */
1845         ret = i915_gem_object_get_fence(obj);
1846         if (ret)
1847                 goto err_unpin;
1848
1849         i915_gem_object_pin_fence(obj);
1850
1851         dev_priv->mm.interruptible = true;
1852         return 0;
1853
1854 err_unpin:
1855         i915_gem_object_unpin(obj);
1856 err_interruptible:
1857         dev_priv->mm.interruptible = true;
1858         return ret;
1859 }
1860
1861 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1862 {
1863         i915_gem_object_unpin_fence(obj);
1864         i915_gem_object_unpin(obj);
1865 }
1866
1867 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868  * is assumed to be a power-of-two. */
1869 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1870                                              unsigned int tiling_mode,
1871                                              unsigned int cpp,
1872                                              unsigned int pitch)
1873 {
1874         if (tiling_mode != I915_TILING_NONE) {
1875                 unsigned int tile_rows, tiles;
1876
1877                 tile_rows = *y / 8;
1878                 *y %= 8;
1879
1880                 tiles = *x / (512/cpp);
1881                 *x %= 512/cpp;
1882
1883                 return tile_rows * pitch * 8 + tiles * 4096;
1884         } else {
1885                 unsigned int offset;
1886
1887                 offset = *y * pitch + *x * cpp;
1888                 *y = 0;
1889                 *x = (offset & 4095) / cpp;
1890                 return offset & -4096;
1891         }
1892 }
1893
1894 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1895                              int x, int y)
1896 {
1897         struct drm_device *dev = crtc->dev;
1898         struct drm_i915_private *dev_priv = dev->dev_private;
1899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900         struct intel_framebuffer *intel_fb;
1901         struct drm_i915_gem_object *obj;
1902         int plane = intel_crtc->plane;
1903         unsigned long linear_offset;
1904         u32 dspcntr;
1905         u32 reg;
1906
1907         switch (plane) {
1908         case 0:
1909         case 1:
1910                 break;
1911         default:
1912                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1913                 return -EINVAL;
1914         }
1915
1916         intel_fb = to_intel_framebuffer(fb);
1917         obj = intel_fb->obj;
1918
1919         reg = DSPCNTR(plane);
1920         dspcntr = I915_READ(reg);
1921         /* Mask out pixel format bits in case we change it */
1922         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1923         switch (fb->pixel_format) {
1924         case DRM_FORMAT_C8:
1925                 dspcntr |= DISPPLANE_8BPP;
1926                 break;
1927         case DRM_FORMAT_XRGB1555:
1928         case DRM_FORMAT_ARGB1555:
1929                 dspcntr |= DISPPLANE_BGRX555;
1930                 break;
1931         case DRM_FORMAT_RGB565:
1932                 dspcntr |= DISPPLANE_BGRX565;
1933                 break;
1934         case DRM_FORMAT_XRGB8888:
1935         case DRM_FORMAT_ARGB8888:
1936                 dspcntr |= DISPPLANE_BGRX888;
1937                 break;
1938         case DRM_FORMAT_XBGR8888:
1939         case DRM_FORMAT_ABGR8888:
1940                 dspcntr |= DISPPLANE_RGBX888;
1941                 break;
1942         case DRM_FORMAT_XRGB2101010:
1943         case DRM_FORMAT_ARGB2101010:
1944                 dspcntr |= DISPPLANE_BGRX101010;
1945                 break;
1946         case DRM_FORMAT_XBGR2101010:
1947         case DRM_FORMAT_ABGR2101010:
1948                 dspcntr |= DISPPLANE_RGBX101010;
1949                 break;
1950         default:
1951                 BUG();
1952         }
1953
1954         if (INTEL_INFO(dev)->gen >= 4) {
1955                 if (obj->tiling_mode != I915_TILING_NONE)
1956                         dspcntr |= DISPPLANE_TILED;
1957                 else
1958                         dspcntr &= ~DISPPLANE_TILED;
1959         }
1960
1961         I915_WRITE(reg, dspcntr);
1962
1963         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1964
1965         if (INTEL_INFO(dev)->gen >= 4) {
1966                 intel_crtc->dspaddr_offset =
1967                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1968                                                        fb->bits_per_pixel / 8,
1969                                                        fb->pitches[0]);
1970                 linear_offset -= intel_crtc->dspaddr_offset;
1971         } else {
1972                 intel_crtc->dspaddr_offset = linear_offset;
1973         }
1974
1975         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1976                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1977         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1978         if (INTEL_INFO(dev)->gen >= 4) {
1979                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1980                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1981                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1982                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1983         } else
1984                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1985         POSTING_READ(reg);
1986
1987         return 0;
1988 }
1989
1990 static int ironlake_update_plane(struct drm_crtc *crtc,
1991                                  struct drm_framebuffer *fb, int x, int y)
1992 {
1993         struct drm_device *dev = crtc->dev;
1994         struct drm_i915_private *dev_priv = dev->dev_private;
1995         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1996         struct intel_framebuffer *intel_fb;
1997         struct drm_i915_gem_object *obj;
1998         int plane = intel_crtc->plane;
1999         unsigned long linear_offset;
2000         u32 dspcntr;
2001         u32 reg;
2002
2003         switch (plane) {
2004         case 0:
2005         case 1:
2006         case 2:
2007                 break;
2008         default:
2009                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2010                 return -EINVAL;
2011         }
2012
2013         intel_fb = to_intel_framebuffer(fb);
2014         obj = intel_fb->obj;
2015
2016         reg = DSPCNTR(plane);
2017         dspcntr = I915_READ(reg);
2018         /* Mask out pixel format bits in case we change it */
2019         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2020         switch (fb->pixel_format) {
2021         case DRM_FORMAT_C8:
2022                 dspcntr |= DISPPLANE_8BPP;
2023                 break;
2024         case DRM_FORMAT_RGB565:
2025                 dspcntr |= DISPPLANE_BGRX565;
2026                 break;
2027         case DRM_FORMAT_XRGB8888:
2028         case DRM_FORMAT_ARGB8888:
2029                 dspcntr |= DISPPLANE_BGRX888;
2030                 break;
2031         case DRM_FORMAT_XBGR8888:
2032         case DRM_FORMAT_ABGR8888:
2033                 dspcntr |= DISPPLANE_RGBX888;
2034                 break;
2035         case DRM_FORMAT_XRGB2101010:
2036         case DRM_FORMAT_ARGB2101010:
2037                 dspcntr |= DISPPLANE_BGRX101010;
2038                 break;
2039         case DRM_FORMAT_XBGR2101010:
2040         case DRM_FORMAT_ABGR2101010:
2041                 dspcntr |= DISPPLANE_RGBX101010;
2042                 break;
2043         default:
2044                 BUG();
2045         }
2046
2047         if (obj->tiling_mode != I915_TILING_NONE)
2048                 dspcntr |= DISPPLANE_TILED;
2049         else
2050                 dspcntr &= ~DISPPLANE_TILED;
2051
2052         /* must disable */
2053         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2054
2055         I915_WRITE(reg, dspcntr);
2056
2057         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2058         intel_crtc->dspaddr_offset =
2059                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2060                                                fb->bits_per_pixel / 8,
2061                                                fb->pitches[0]);
2062         linear_offset -= intel_crtc->dspaddr_offset;
2063
2064         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2066         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2067         I915_MODIFY_DISPBASE(DSPSURF(plane),
2068                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2069         if (IS_HASWELL(dev)) {
2070                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2071         } else {
2072                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2073                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2074         }
2075         POSTING_READ(reg);
2076
2077         return 0;
2078 }
2079
2080 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2081 static int
2082 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2083                            int x, int y, enum mode_set_atomic state)
2084 {
2085         struct drm_device *dev = crtc->dev;
2086         struct drm_i915_private *dev_priv = dev->dev_private;
2087
2088         if (dev_priv->display.disable_fbc)
2089                 dev_priv->display.disable_fbc(dev);
2090         intel_increase_pllclock(crtc);
2091
2092         return dev_priv->display.update_plane(crtc, fb, x, y);
2093 }
2094
2095 void intel_display_handle_reset(struct drm_device *dev)
2096 {
2097         struct drm_i915_private *dev_priv = dev->dev_private;
2098         struct drm_crtc *crtc;
2099
2100         /*
2101          * Flips in the rings have been nuked by the reset,
2102          * so complete all pending flips so that user space
2103          * will get its events and not get stuck.
2104          *
2105          * Also update the base address of all primary
2106          * planes to the the last fb to make sure we're
2107          * showing the correct fb after a reset.
2108          *
2109          * Need to make two loops over the crtcs so that we
2110          * don't try to grab a crtc mutex before the
2111          * pending_flip_queue really got woken up.
2112          */
2113
2114         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2115                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2116                 enum plane plane = intel_crtc->plane;
2117
2118                 intel_prepare_page_flip(dev, plane);
2119                 intel_finish_page_flip_plane(dev, plane);
2120         }
2121
2122         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2123                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124
2125                 mutex_lock(&crtc->mutex);
2126                 if (intel_crtc->active)
2127                         dev_priv->display.update_plane(crtc, crtc->fb,
2128                                                        crtc->x, crtc->y);
2129                 mutex_unlock(&crtc->mutex);
2130         }
2131 }
2132
2133 static int
2134 intel_finish_fb(struct drm_framebuffer *old_fb)
2135 {
2136         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2137         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2138         bool was_interruptible = dev_priv->mm.interruptible;
2139         int ret;
2140
2141         /* Big Hammer, we also need to ensure that any pending
2142          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2143          * current scanout is retired before unpinning the old
2144          * framebuffer.
2145          *
2146          * This should only fail upon a hung GPU, in which case we
2147          * can safely continue.
2148          */
2149         dev_priv->mm.interruptible = false;
2150         ret = i915_gem_object_finish_gpu(obj);
2151         dev_priv->mm.interruptible = was_interruptible;
2152
2153         return ret;
2154 }
2155
2156 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2157 {
2158         struct drm_device *dev = crtc->dev;
2159         struct drm_i915_master_private *master_priv;
2160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2161
2162         if (!dev->primary->master)
2163                 return;
2164
2165         master_priv = dev->primary->master->driver_priv;
2166         if (!master_priv->sarea_priv)
2167                 return;
2168
2169         switch (intel_crtc->pipe) {
2170         case 0:
2171                 master_priv->sarea_priv->pipeA_x = x;
2172                 master_priv->sarea_priv->pipeA_y = y;
2173                 break;
2174         case 1:
2175                 master_priv->sarea_priv->pipeB_x = x;
2176                 master_priv->sarea_priv->pipeB_y = y;
2177                 break;
2178         default:
2179                 break;
2180         }
2181 }
2182
2183 static int
2184 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2185                     struct drm_framebuffer *fb)
2186 {
2187         struct drm_device *dev = crtc->dev;
2188         struct drm_i915_private *dev_priv = dev->dev_private;
2189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2190         struct drm_framebuffer *old_fb;
2191         int ret;
2192
2193         /* no fb bound */
2194         if (!fb) {
2195                 DRM_ERROR("No FB bound\n");
2196                 return 0;
2197         }
2198
2199         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2200                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2201                           plane_name(intel_crtc->plane),
2202                           INTEL_INFO(dev)->num_pipes);
2203                 return -EINVAL;
2204         }
2205
2206         mutex_lock(&dev->struct_mutex);
2207         ret = intel_pin_and_fence_fb_obj(dev,
2208                                          to_intel_framebuffer(fb)->obj,
2209                                          NULL);
2210         if (ret != 0) {
2211                 mutex_unlock(&dev->struct_mutex);
2212                 DRM_ERROR("pin & fence failed\n");
2213                 return ret;
2214         }
2215
2216         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2217         if (ret) {
2218                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2219                 mutex_unlock(&dev->struct_mutex);
2220                 DRM_ERROR("failed to update base address\n");
2221                 return ret;
2222         }
2223
2224         old_fb = crtc->fb;
2225         crtc->fb = fb;
2226         crtc->x = x;
2227         crtc->y = y;
2228
2229         if (old_fb) {
2230                 if (intel_crtc->active && old_fb != fb)
2231                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2232                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2233         }
2234
2235         intel_update_fbc(dev);
2236         mutex_unlock(&dev->struct_mutex);
2237
2238         intel_crtc_update_sarea_pos(crtc, x, y);
2239
2240         return 0;
2241 }
2242
2243 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2244 {
2245         struct drm_device *dev = crtc->dev;
2246         struct drm_i915_private *dev_priv = dev->dev_private;
2247         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2248         int pipe = intel_crtc->pipe;
2249         u32 reg, temp;
2250
2251         /* enable normal train */
2252         reg = FDI_TX_CTL(pipe);
2253         temp = I915_READ(reg);
2254         if (IS_IVYBRIDGE(dev)) {
2255                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2256                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2257         } else {
2258                 temp &= ~FDI_LINK_TRAIN_NONE;
2259                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2260         }
2261         I915_WRITE(reg, temp);
2262
2263         reg = FDI_RX_CTL(pipe);
2264         temp = I915_READ(reg);
2265         if (HAS_PCH_CPT(dev)) {
2266                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2268         } else {
2269                 temp &= ~FDI_LINK_TRAIN_NONE;
2270                 temp |= FDI_LINK_TRAIN_NONE;
2271         }
2272         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2273
2274         /* wait one idle pattern time */
2275         POSTING_READ(reg);
2276         udelay(1000);
2277
2278         /* IVB wants error correction enabled */
2279         if (IS_IVYBRIDGE(dev))
2280                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2281                            FDI_FE_ERRC_ENABLE);
2282 }
2283
2284 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2285 {
2286         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2287 }
2288
2289 static void ivb_modeset_global_resources(struct drm_device *dev)
2290 {
2291         struct drm_i915_private *dev_priv = dev->dev_private;
2292         struct intel_crtc *pipe_B_crtc =
2293                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2294         struct intel_crtc *pipe_C_crtc =
2295                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2296         uint32_t temp;
2297
2298         /*
2299          * When everything is off disable fdi C so that we could enable fdi B
2300          * with all lanes. Note that we don't care about enabled pipes without
2301          * an enabled pch encoder.
2302          */
2303         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2304             !pipe_has_enabled_pch(pipe_C_crtc)) {
2305                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2306                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2307
2308                 temp = I915_READ(SOUTH_CHICKEN1);
2309                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2310                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2311                 I915_WRITE(SOUTH_CHICKEN1, temp);
2312         }
2313 }
2314
2315 /* The FDI link training functions for ILK/Ibexpeak. */
2316 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2317 {
2318         struct drm_device *dev = crtc->dev;
2319         struct drm_i915_private *dev_priv = dev->dev_private;
2320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2321         int pipe = intel_crtc->pipe;
2322         int plane = intel_crtc->plane;
2323         u32 reg, temp, tries;
2324
2325         /* FDI needs bits from pipe & plane first */
2326         assert_pipe_enabled(dev_priv, pipe);
2327         assert_plane_enabled(dev_priv, plane);
2328
2329         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2330            for train result */
2331         reg = FDI_RX_IMR(pipe);
2332         temp = I915_READ(reg);
2333         temp &= ~FDI_RX_SYMBOL_LOCK;
2334         temp &= ~FDI_RX_BIT_LOCK;
2335         I915_WRITE(reg, temp);
2336         I915_READ(reg);
2337         udelay(150);
2338
2339         /* enable CPU FDI TX and PCH FDI RX */
2340         reg = FDI_TX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2343         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2344         temp &= ~FDI_LINK_TRAIN_NONE;
2345         temp |= FDI_LINK_TRAIN_PATTERN_1;
2346         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2347
2348         reg = FDI_RX_CTL(pipe);
2349         temp = I915_READ(reg);
2350         temp &= ~FDI_LINK_TRAIN_NONE;
2351         temp |= FDI_LINK_TRAIN_PATTERN_1;
2352         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2353
2354         POSTING_READ(reg);
2355         udelay(150);
2356
2357         /* Ironlake workaround, enable clock pointer after FDI enable*/
2358         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2359         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2360                    FDI_RX_PHASE_SYNC_POINTER_EN);
2361
2362         reg = FDI_RX_IIR(pipe);
2363         for (tries = 0; tries < 5; tries++) {
2364                 temp = I915_READ(reg);
2365                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367                 if ((temp & FDI_RX_BIT_LOCK)) {
2368                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2369                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2370                         break;
2371                 }
2372         }
2373         if (tries == 5)
2374                 DRM_ERROR("FDI train 1 fail!\n");
2375
2376         /* Train 2 */
2377         reg = FDI_TX_CTL(pipe);
2378         temp = I915_READ(reg);
2379         temp &= ~FDI_LINK_TRAIN_NONE;
2380         temp |= FDI_LINK_TRAIN_PATTERN_2;
2381         I915_WRITE(reg, temp);
2382
2383         reg = FDI_RX_CTL(pipe);
2384         temp = I915_READ(reg);
2385         temp &= ~FDI_LINK_TRAIN_NONE;
2386         temp |= FDI_LINK_TRAIN_PATTERN_2;
2387         I915_WRITE(reg, temp);
2388
2389         POSTING_READ(reg);
2390         udelay(150);
2391
2392         reg = FDI_RX_IIR(pipe);
2393         for (tries = 0; tries < 5; tries++) {
2394                 temp = I915_READ(reg);
2395                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2396
2397                 if (temp & FDI_RX_SYMBOL_LOCK) {
2398                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2399                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2400                         break;
2401                 }
2402         }
2403         if (tries == 5)
2404                 DRM_ERROR("FDI train 2 fail!\n");
2405
2406         DRM_DEBUG_KMS("FDI train done\n");
2407
2408 }
2409
2410 static const int snb_b_fdi_train_param[] = {
2411         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2412         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2413         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2414         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2415 };
2416
2417 /* The FDI link training functions for SNB/Cougarpoint. */
2418 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2419 {
2420         struct drm_device *dev = crtc->dev;
2421         struct drm_i915_private *dev_priv = dev->dev_private;
2422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423         int pipe = intel_crtc->pipe;
2424         u32 reg, temp, i, retry;
2425
2426         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2427            for train result */
2428         reg = FDI_RX_IMR(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_RX_SYMBOL_LOCK;
2431         temp &= ~FDI_RX_BIT_LOCK;
2432         I915_WRITE(reg, temp);
2433
2434         POSTING_READ(reg);
2435         udelay(150);
2436
2437         /* enable CPU FDI TX and PCH FDI RX */
2438         reg = FDI_TX_CTL(pipe);
2439         temp = I915_READ(reg);
2440         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2441         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2442         temp &= ~FDI_LINK_TRAIN_NONE;
2443         temp |= FDI_LINK_TRAIN_PATTERN_1;
2444         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2445         /* SNB-B */
2446         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2447         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2448
2449         I915_WRITE(FDI_RX_MISC(pipe),
2450                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2451
2452         reg = FDI_RX_CTL(pipe);
2453         temp = I915_READ(reg);
2454         if (HAS_PCH_CPT(dev)) {
2455                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2456                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2457         } else {
2458                 temp &= ~FDI_LINK_TRAIN_NONE;
2459                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2460         }
2461         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2462
2463         POSTING_READ(reg);
2464         udelay(150);
2465
2466         for (i = 0; i < 4; i++) {
2467                 reg = FDI_TX_CTL(pipe);
2468                 temp = I915_READ(reg);
2469                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470                 temp |= snb_b_fdi_train_param[i];
2471                 I915_WRITE(reg, temp);
2472
2473                 POSTING_READ(reg);
2474                 udelay(500);
2475
2476                 for (retry = 0; retry < 5; retry++) {
2477                         reg = FDI_RX_IIR(pipe);
2478                         temp = I915_READ(reg);
2479                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2480                         if (temp & FDI_RX_BIT_LOCK) {
2481                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2482                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2483                                 break;
2484                         }
2485                         udelay(50);
2486                 }
2487                 if (retry < 5)
2488                         break;
2489         }
2490         if (i == 4)
2491                 DRM_ERROR("FDI train 1 fail!\n");
2492
2493         /* Train 2 */
2494         reg = FDI_TX_CTL(pipe);
2495         temp = I915_READ(reg);
2496         temp &= ~FDI_LINK_TRAIN_NONE;
2497         temp |= FDI_LINK_TRAIN_PATTERN_2;
2498         if (IS_GEN6(dev)) {
2499                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2500                 /* SNB-B */
2501                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2502         }
2503         I915_WRITE(reg, temp);
2504
2505         reg = FDI_RX_CTL(pipe);
2506         temp = I915_READ(reg);
2507         if (HAS_PCH_CPT(dev)) {
2508                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2509                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2510         } else {
2511                 temp &= ~FDI_LINK_TRAIN_NONE;
2512                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2513         }
2514         I915_WRITE(reg, temp);
2515
2516         POSTING_READ(reg);
2517         udelay(150);
2518
2519         for (i = 0; i < 4; i++) {
2520                 reg = FDI_TX_CTL(pipe);
2521                 temp = I915_READ(reg);
2522                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2523                 temp |= snb_b_fdi_train_param[i];
2524                 I915_WRITE(reg, temp);
2525
2526                 POSTING_READ(reg);
2527                 udelay(500);
2528
2529                 for (retry = 0; retry < 5; retry++) {
2530                         reg = FDI_RX_IIR(pipe);
2531                         temp = I915_READ(reg);
2532                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533                         if (temp & FDI_RX_SYMBOL_LOCK) {
2534                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2535                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2536                                 break;
2537                         }
2538                         udelay(50);
2539                 }
2540                 if (retry < 5)
2541                         break;
2542         }
2543         if (i == 4)
2544                 DRM_ERROR("FDI train 2 fail!\n");
2545
2546         DRM_DEBUG_KMS("FDI train done.\n");
2547 }
2548
2549 /* Manual link training for Ivy Bridge A0 parts */
2550 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2551 {
2552         struct drm_device *dev = crtc->dev;
2553         struct drm_i915_private *dev_priv = dev->dev_private;
2554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2555         int pipe = intel_crtc->pipe;
2556         u32 reg, temp, i;
2557
2558         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2559            for train result */
2560         reg = FDI_RX_IMR(pipe);
2561         temp = I915_READ(reg);
2562         temp &= ~FDI_RX_SYMBOL_LOCK;
2563         temp &= ~FDI_RX_BIT_LOCK;
2564         I915_WRITE(reg, temp);
2565
2566         POSTING_READ(reg);
2567         udelay(150);
2568
2569         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2570                       I915_READ(FDI_RX_IIR(pipe)));
2571
2572         /* enable CPU FDI TX and PCH FDI RX */
2573         reg = FDI_TX_CTL(pipe);
2574         temp = I915_READ(reg);
2575         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2576         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2577         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2578         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2579         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2580         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2581         temp |= FDI_COMPOSITE_SYNC;
2582         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2583
2584         I915_WRITE(FDI_RX_MISC(pipe),
2585                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2586
2587         reg = FDI_RX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         temp &= ~FDI_LINK_TRAIN_AUTO;
2590         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2592         temp |= FDI_COMPOSITE_SYNC;
2593         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2594
2595         POSTING_READ(reg);
2596         udelay(150);
2597
2598         for (i = 0; i < 4; i++) {
2599                 reg = FDI_TX_CTL(pipe);
2600                 temp = I915_READ(reg);
2601                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602                 temp |= snb_b_fdi_train_param[i];
2603                 I915_WRITE(reg, temp);
2604
2605                 POSTING_READ(reg);
2606                 udelay(500);
2607
2608                 reg = FDI_RX_IIR(pipe);
2609                 temp = I915_READ(reg);
2610                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2611
2612                 if (temp & FDI_RX_BIT_LOCK ||
2613                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2614                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2615                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2616                         break;
2617                 }
2618         }
2619         if (i == 4)
2620                 DRM_ERROR("FDI train 1 fail!\n");
2621
2622         /* Train 2 */
2623         reg = FDI_TX_CTL(pipe);
2624         temp = I915_READ(reg);
2625         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2626         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2627         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2629         I915_WRITE(reg, temp);
2630
2631         reg = FDI_RX_CTL(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2635         I915_WRITE(reg, temp);
2636
2637         POSTING_READ(reg);
2638         udelay(150);
2639
2640         for (i = 0; i < 4; i++) {
2641                 reg = FDI_TX_CTL(pipe);
2642                 temp = I915_READ(reg);
2643                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2644                 temp |= snb_b_fdi_train_param[i];
2645                 I915_WRITE(reg, temp);
2646
2647                 POSTING_READ(reg);
2648                 udelay(500);
2649
2650                 reg = FDI_RX_IIR(pipe);
2651                 temp = I915_READ(reg);
2652                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2653
2654                 if (temp & FDI_RX_SYMBOL_LOCK) {
2655                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2656                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2657                         break;
2658                 }
2659         }
2660         if (i == 4)
2661                 DRM_ERROR("FDI train 2 fail!\n");
2662
2663         DRM_DEBUG_KMS("FDI train done.\n");
2664 }
2665
2666 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2667 {
2668         struct drm_device *dev = intel_crtc->base.dev;
2669         struct drm_i915_private *dev_priv = dev->dev_private;
2670         int pipe = intel_crtc->pipe;
2671         u32 reg, temp;
2672
2673
2674         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2675         reg = FDI_RX_CTL(pipe);
2676         temp = I915_READ(reg);
2677         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2678         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2679         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2680         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2681
2682         POSTING_READ(reg);
2683         udelay(200);
2684
2685         /* Switch from Rawclk to PCDclk */
2686         temp = I915_READ(reg);
2687         I915_WRITE(reg, temp | FDI_PCDCLK);
2688
2689         POSTING_READ(reg);
2690         udelay(200);
2691
2692         /* Enable CPU FDI TX PLL, always on for Ironlake */
2693         reg = FDI_TX_CTL(pipe);
2694         temp = I915_READ(reg);
2695         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2696                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2697
2698                 POSTING_READ(reg);
2699                 udelay(100);
2700         }
2701 }
2702
2703 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2704 {
2705         struct drm_device *dev = intel_crtc->base.dev;
2706         struct drm_i915_private *dev_priv = dev->dev_private;
2707         int pipe = intel_crtc->pipe;
2708         u32 reg, temp;
2709
2710         /* Switch from PCDclk to Rawclk */
2711         reg = FDI_RX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2714
2715         /* Disable CPU FDI TX PLL */
2716         reg = FDI_TX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2719
2720         POSTING_READ(reg);
2721         udelay(100);
2722
2723         reg = FDI_RX_CTL(pipe);
2724         temp = I915_READ(reg);
2725         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2726
2727         /* Wait for the clocks to turn off. */
2728         POSTING_READ(reg);
2729         udelay(100);
2730 }
2731
2732 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2733 {
2734         struct drm_device *dev = crtc->dev;
2735         struct drm_i915_private *dev_priv = dev->dev_private;
2736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2737         int pipe = intel_crtc->pipe;
2738         u32 reg, temp;
2739
2740         /* disable CPU FDI tx and PCH FDI rx */
2741         reg = FDI_TX_CTL(pipe);
2742         temp = I915_READ(reg);
2743         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2744         POSTING_READ(reg);
2745
2746         reg = FDI_RX_CTL(pipe);
2747         temp = I915_READ(reg);
2748         temp &= ~(0x7 << 16);
2749         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2750         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2751
2752         POSTING_READ(reg);
2753         udelay(100);
2754
2755         /* Ironlake workaround, disable clock pointer after downing FDI */
2756         if (HAS_PCH_IBX(dev)) {
2757                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2758         }
2759
2760         /* still set train pattern 1 */
2761         reg = FDI_TX_CTL(pipe);
2762         temp = I915_READ(reg);
2763         temp &= ~FDI_LINK_TRAIN_NONE;
2764         temp |= FDI_LINK_TRAIN_PATTERN_1;
2765         I915_WRITE(reg, temp);
2766
2767         reg = FDI_RX_CTL(pipe);
2768         temp = I915_READ(reg);
2769         if (HAS_PCH_CPT(dev)) {
2770                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2771                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2772         } else {
2773                 temp &= ~FDI_LINK_TRAIN_NONE;
2774                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2775         }
2776         /* BPC in FDI rx is consistent with that in PIPECONF */
2777         temp &= ~(0x07 << 16);
2778         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2779         I915_WRITE(reg, temp);
2780
2781         POSTING_READ(reg);
2782         udelay(100);
2783 }
2784
2785 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2786 {
2787         struct drm_device *dev = crtc->dev;
2788         struct drm_i915_private *dev_priv = dev->dev_private;
2789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2790         unsigned long flags;
2791         bool pending;
2792
2793         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2794             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2795                 return false;
2796
2797         spin_lock_irqsave(&dev->event_lock, flags);
2798         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2799         spin_unlock_irqrestore(&dev->event_lock, flags);
2800
2801         return pending;
2802 }
2803
2804 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2805 {
2806         struct drm_device *dev = crtc->dev;
2807         struct drm_i915_private *dev_priv = dev->dev_private;
2808
2809         if (crtc->fb == NULL)
2810                 return;
2811
2812         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2813
2814         wait_event(dev_priv->pending_flip_queue,
2815                    !intel_crtc_has_pending_flip(crtc));
2816
2817         mutex_lock(&dev->struct_mutex);
2818         intel_finish_fb(crtc->fb);
2819         mutex_unlock(&dev->struct_mutex);
2820 }
2821
2822 /* Program iCLKIP clock to the desired frequency */
2823 static void lpt_program_iclkip(struct drm_crtc *crtc)
2824 {
2825         struct drm_device *dev = crtc->dev;
2826         struct drm_i915_private *dev_priv = dev->dev_private;
2827         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2828         u32 temp;
2829
2830         mutex_lock(&dev_priv->dpio_lock);
2831
2832         /* It is necessary to ungate the pixclk gate prior to programming
2833          * the divisors, and gate it back when it is done.
2834          */
2835         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2836
2837         /* Disable SSCCTL */
2838         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2839                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2840                                 SBI_SSCCTL_DISABLE,
2841                         SBI_ICLK);
2842
2843         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2844         if (crtc->mode.clock == 20000) {
2845                 auxdiv = 1;
2846                 divsel = 0x41;
2847                 phaseinc = 0x20;
2848         } else {
2849                 /* The iCLK virtual clock root frequency is in MHz,
2850                  * but the crtc->mode.clock in in KHz. To get the divisors,
2851                  * it is necessary to divide one by another, so we
2852                  * convert the virtual clock precision to KHz here for higher
2853                  * precision.
2854                  */
2855                 u32 iclk_virtual_root_freq = 172800 * 1000;
2856                 u32 iclk_pi_range = 64;
2857                 u32 desired_divisor, msb_divisor_value, pi_value;
2858
2859                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2860                 msb_divisor_value = desired_divisor / iclk_pi_range;
2861                 pi_value = desired_divisor % iclk_pi_range;
2862
2863                 auxdiv = 0;
2864                 divsel = msb_divisor_value - 2;
2865                 phaseinc = pi_value;
2866         }
2867
2868         /* This should not happen with any sane values */
2869         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2870                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2871         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2872                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2873
2874         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2875                         crtc->mode.clock,
2876                         auxdiv,
2877                         divsel,
2878                         phasedir,
2879                         phaseinc);
2880
2881         /* Program SSCDIVINTPHASE6 */
2882         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2883         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2884         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2885         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2886         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2887         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2888         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2889         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2890
2891         /* Program SSCAUXDIV */
2892         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2893         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2894         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2895         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2896
2897         /* Enable modulator and associated divider */
2898         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2899         temp &= ~SBI_SSCCTL_DISABLE;
2900         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2901
2902         /* Wait for initialization time */
2903         udelay(24);
2904
2905         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2906
2907         mutex_unlock(&dev_priv->dpio_lock);
2908 }
2909
2910 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2911                                                 enum pipe pch_transcoder)
2912 {
2913         struct drm_device *dev = crtc->base.dev;
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2916
2917         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2918                    I915_READ(HTOTAL(cpu_transcoder)));
2919         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2920                    I915_READ(HBLANK(cpu_transcoder)));
2921         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2922                    I915_READ(HSYNC(cpu_transcoder)));
2923
2924         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2925                    I915_READ(VTOTAL(cpu_transcoder)));
2926         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2927                    I915_READ(VBLANK(cpu_transcoder)));
2928         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2929                    I915_READ(VSYNC(cpu_transcoder)));
2930         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2931                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2932 }
2933
2934 /*
2935  * Enable PCH resources required for PCH ports:
2936  *   - PCH PLLs
2937  *   - FDI training & RX/TX
2938  *   - update transcoder timings
2939  *   - DP transcoding bits
2940  *   - transcoder
2941  */
2942 static void ironlake_pch_enable(struct drm_crtc *crtc)
2943 {
2944         struct drm_device *dev = crtc->dev;
2945         struct drm_i915_private *dev_priv = dev->dev_private;
2946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2947         int pipe = intel_crtc->pipe;
2948         u32 reg, temp;
2949
2950         assert_pch_transcoder_disabled(dev_priv, pipe);
2951
2952         /* Write the TU size bits before fdi link training, so that error
2953          * detection works. */
2954         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2955                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2956
2957         /* For PCH output, training FDI link */
2958         dev_priv->display.fdi_link_train(crtc);
2959
2960         /* XXX: pch pll's can be enabled any time before we enable the PCH
2961          * transcoder, and we actually should do this to not upset any PCH
2962          * transcoder that already use the clock when we share it.
2963          *
2964          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2965          * unconditionally resets the pll - we need that to have the right LVDS
2966          * enable sequence. */
2967         ironlake_enable_pch_pll(intel_crtc);
2968
2969         if (HAS_PCH_CPT(dev)) {
2970                 u32 sel;
2971
2972                 temp = I915_READ(PCH_DPLL_SEL);
2973                 switch (pipe) {
2974                 default:
2975                 case 0:
2976                         temp |= TRANSA_DPLL_ENABLE;
2977                         sel = TRANSA_DPLLB_SEL;
2978                         break;
2979                 case 1:
2980                         temp |= TRANSB_DPLL_ENABLE;
2981                         sel = TRANSB_DPLLB_SEL;
2982                         break;
2983                 case 2:
2984                         temp |= TRANSC_DPLL_ENABLE;
2985                         sel = TRANSC_DPLLB_SEL;
2986                         break;
2987                 }
2988                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2989                         temp |= sel;
2990                 else
2991                         temp &= ~sel;
2992                 I915_WRITE(PCH_DPLL_SEL, temp);
2993         }
2994
2995         /* set transcoder timing, panel must allow it */
2996         assert_panel_unlocked(dev_priv, pipe);
2997         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2998
2999         intel_fdi_normal_train(crtc);
3000
3001         /* For PCH DP, enable TRANS_DP_CTL */
3002         if (HAS_PCH_CPT(dev) &&
3003             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3004              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3005                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3006                 reg = TRANS_DP_CTL(pipe);
3007                 temp = I915_READ(reg);
3008                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3009                           TRANS_DP_SYNC_MASK |
3010                           TRANS_DP_BPC_MASK);
3011                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3012                          TRANS_DP_ENH_FRAMING);
3013                 temp |= bpc << 9; /* same format but at 11:9 */
3014
3015                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3016                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3017                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3018                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3019
3020                 switch (intel_trans_dp_port_sel(crtc)) {
3021                 case PCH_DP_B:
3022                         temp |= TRANS_DP_PORT_SEL_B;
3023                         break;
3024                 case PCH_DP_C:
3025                         temp |= TRANS_DP_PORT_SEL_C;
3026                         break;
3027                 case PCH_DP_D:
3028                         temp |= TRANS_DP_PORT_SEL_D;
3029                         break;
3030                 default:
3031                         BUG();
3032                 }
3033
3034                 I915_WRITE(reg, temp);
3035         }
3036
3037         ironlake_enable_pch_transcoder(dev_priv, pipe);
3038 }
3039
3040 static void lpt_pch_enable(struct drm_crtc *crtc)
3041 {
3042         struct drm_device *dev = crtc->dev;
3043         struct drm_i915_private *dev_priv = dev->dev_private;
3044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3045         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3046
3047         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3048
3049         lpt_program_iclkip(crtc);
3050
3051         /* Set transcoder timing. */
3052         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3053
3054         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3055 }
3056
3057 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3058 {
3059         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3060
3061         if (pll == NULL)
3062                 return;
3063
3064         if (pll->refcount == 0) {
3065                 WARN(1, "bad PCH PLL refcount\n");
3066                 return;
3067         }
3068
3069         --pll->refcount;
3070         intel_crtc->pch_pll = NULL;
3071 }
3072
3073 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3074 {
3075         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3076         struct intel_pch_pll *pll;
3077         int i;
3078
3079         pll = intel_crtc->pch_pll;
3080         if (pll) {
3081                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3082                               intel_crtc->base.base.id, pll->pll_reg);
3083                 goto prepare;
3084         }
3085
3086         if (HAS_PCH_IBX(dev_priv->dev)) {
3087                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3088                 i = intel_crtc->pipe;
3089                 pll = &dev_priv->pch_plls[i];
3090
3091                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3092                               intel_crtc->base.base.id, pll->pll_reg);
3093
3094                 goto found;
3095         }
3096
3097         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3098                 pll = &dev_priv->pch_plls[i];
3099
3100                 /* Only want to check enabled timings first */
3101                 if (pll->refcount == 0)
3102                         continue;
3103
3104                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3105                     fp == I915_READ(pll->fp0_reg)) {
3106                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3107                                       intel_crtc->base.base.id,
3108                                       pll->pll_reg, pll->refcount, pll->active);
3109
3110                         goto found;
3111                 }
3112         }
3113
3114         /* Ok no matching timings, maybe there's a free one? */
3115         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116                 pll = &dev_priv->pch_plls[i];
3117                 if (pll->refcount == 0) {
3118                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3119                                       intel_crtc->base.base.id, pll->pll_reg);
3120                         goto found;
3121                 }
3122         }
3123
3124         return NULL;
3125
3126 found:
3127         intel_crtc->pch_pll = pll;
3128         pll->refcount++;
3129         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3130 prepare: /* separate function? */
3131         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3132
3133         /* Wait for the clocks to stabilize before rewriting the regs */
3134         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3135         POSTING_READ(pll->pll_reg);
3136         udelay(150);
3137
3138         I915_WRITE(pll->fp0_reg, fp);
3139         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3140         pll->on = false;
3141         return pll;
3142 }
3143
3144 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3145 {
3146         struct drm_i915_private *dev_priv = dev->dev_private;
3147         int dslreg = PIPEDSL(pipe);
3148         u32 temp;
3149
3150         temp = I915_READ(dslreg);
3151         udelay(500);
3152         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3153                 if (wait_for(I915_READ(dslreg) != temp, 5))
3154                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3155         }
3156 }
3157
3158 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3159 {
3160         struct drm_device *dev = crtc->base.dev;
3161         struct drm_i915_private *dev_priv = dev->dev_private;
3162         int pipe = crtc->pipe;
3163
3164         if (crtc->config.pch_pfit.size) {
3165                 /* Force use of hard-coded filter coefficients
3166                  * as some pre-programmed values are broken,
3167                  * e.g. x201.
3168                  */
3169                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3170                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3171                                                  PF_PIPE_SEL_IVB(pipe));
3172                 else
3173                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3174                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3175                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3176         }
3177 }
3178
3179 static void intel_enable_planes(struct drm_crtc *crtc)
3180 {
3181         struct drm_device *dev = crtc->dev;
3182         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3183         struct intel_plane *intel_plane;
3184
3185         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3186                 if (intel_plane->pipe == pipe)
3187                         intel_plane_restore(&intel_plane->base);
3188 }
3189
3190 static void intel_disable_planes(struct drm_crtc *crtc)
3191 {
3192         struct drm_device *dev = crtc->dev;
3193         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3194         struct intel_plane *intel_plane;
3195
3196         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3197                 if (intel_plane->pipe == pipe)
3198                         intel_plane_disable(&intel_plane->base);
3199 }
3200
3201 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3202 {
3203         struct drm_device *dev = crtc->dev;
3204         struct drm_i915_private *dev_priv = dev->dev_private;
3205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3206         struct intel_encoder *encoder;
3207         int pipe = intel_crtc->pipe;
3208         int plane = intel_crtc->plane;
3209         u32 temp;
3210
3211         WARN_ON(!crtc->enabled);
3212
3213         if (intel_crtc->active)
3214                 return;
3215
3216         intel_crtc->active = true;
3217
3218         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3219         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3220
3221         intel_update_watermarks(dev);
3222
3223         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3224                 temp = I915_READ(PCH_LVDS);
3225                 if ((temp & LVDS_PORT_EN) == 0)
3226                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3227         }
3228
3229
3230         if (intel_crtc->config.has_pch_encoder) {
3231                 /* Note: FDI PLL enabling _must_ be done before we enable the
3232                  * cpu pipes, hence this is separate from all the other fdi/pch
3233                  * enabling. */
3234                 ironlake_fdi_pll_enable(intel_crtc);
3235         } else {
3236                 assert_fdi_tx_disabled(dev_priv, pipe);
3237                 assert_fdi_rx_disabled(dev_priv, pipe);
3238         }
3239
3240         for_each_encoder_on_crtc(dev, crtc, encoder)
3241                 if (encoder->pre_enable)
3242                         encoder->pre_enable(encoder);
3243
3244         /* Enable panel fitting for LVDS */
3245         ironlake_pfit_enable(intel_crtc);
3246
3247         /*
3248          * On ILK+ LUT must be loaded before the pipe is running but with
3249          * clocks enabled
3250          */
3251         intel_crtc_load_lut(crtc);
3252
3253         intel_enable_pipe(dev_priv, pipe,
3254                           intel_crtc->config.has_pch_encoder);
3255         intel_enable_plane(dev_priv, plane, pipe);
3256         intel_enable_planes(crtc);
3257         intel_crtc_update_cursor(crtc, true);
3258
3259         if (intel_crtc->config.has_pch_encoder)
3260                 ironlake_pch_enable(crtc);
3261
3262         mutex_lock(&dev->struct_mutex);
3263         intel_update_fbc(dev);
3264         mutex_unlock(&dev->struct_mutex);
3265
3266         for_each_encoder_on_crtc(dev, crtc, encoder)
3267                 encoder->enable(encoder);
3268
3269         if (HAS_PCH_CPT(dev))
3270                 cpt_verify_modeset(dev, intel_crtc->pipe);
3271
3272         /*
3273          * There seems to be a race in PCH platform hw (at least on some
3274          * outputs) where an enabled pipe still completes any pageflip right
3275          * away (as if the pipe is off) instead of waiting for vblank. As soon
3276          * as the first vblank happend, everything works as expected. Hence just
3277          * wait for one vblank before returning to avoid strange things
3278          * happening.
3279          */
3280         intel_wait_for_vblank(dev, intel_crtc->pipe);
3281 }
3282
3283 /* IPS only exists on ULT machines and is tied to pipe A. */
3284 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3285 {
3286         return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3287 }
3288
3289 static void hsw_enable_ips(struct intel_crtc *crtc)
3290 {
3291         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3292
3293         if (!crtc->config.ips_enabled)
3294                 return;
3295
3296         /* We can only enable IPS after we enable a plane and wait for a vblank.
3297          * We guarantee that the plane is enabled by calling intel_enable_ips
3298          * only after intel_enable_plane. And intel_enable_plane already waits
3299          * for a vblank, so all we need to do here is to enable the IPS bit. */
3300         assert_plane_enabled(dev_priv, crtc->plane);
3301         I915_WRITE(IPS_CTL, IPS_ENABLE);
3302 }
3303
3304 static void hsw_disable_ips(struct intel_crtc *crtc)
3305 {
3306         struct drm_device *dev = crtc->base.dev;
3307         struct drm_i915_private *dev_priv = dev->dev_private;
3308
3309         if (!crtc->config.ips_enabled)
3310                 return;
3311
3312         assert_plane_enabled(dev_priv, crtc->plane);
3313         I915_WRITE(IPS_CTL, 0);
3314
3315         /* We need to wait for a vblank before we can disable the plane. */
3316         intel_wait_for_vblank(dev, crtc->pipe);
3317 }
3318
3319 static void haswell_crtc_enable(struct drm_crtc *crtc)
3320 {
3321         struct drm_device *dev = crtc->dev;
3322         struct drm_i915_private *dev_priv = dev->dev_private;
3323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3324         struct intel_encoder *encoder;
3325         int pipe = intel_crtc->pipe;
3326         int plane = intel_crtc->plane;
3327
3328         WARN_ON(!crtc->enabled);
3329
3330         if (intel_crtc->active)
3331                 return;
3332
3333         intel_crtc->active = true;
3334
3335         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3336         if (intel_crtc->config.has_pch_encoder)
3337                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3338
3339         intel_update_watermarks(dev);
3340
3341         if (intel_crtc->config.has_pch_encoder)
3342                 dev_priv->display.fdi_link_train(crtc);
3343
3344         for_each_encoder_on_crtc(dev, crtc, encoder)
3345                 if (encoder->pre_enable)
3346                         encoder->pre_enable(encoder);
3347
3348         intel_ddi_enable_pipe_clock(intel_crtc);
3349
3350         /* Enable panel fitting for eDP */
3351         ironlake_pfit_enable(intel_crtc);
3352
3353         /*
3354          * On ILK+ LUT must be loaded before the pipe is running but with
3355          * clocks enabled
3356          */
3357         intel_crtc_load_lut(crtc);
3358
3359         intel_ddi_set_pipe_settings(crtc);
3360         intel_ddi_enable_transcoder_func(crtc);
3361
3362         intel_enable_pipe(dev_priv, pipe,
3363                           intel_crtc->config.has_pch_encoder);
3364         intel_enable_plane(dev_priv, plane, pipe);
3365         intel_enable_planes(crtc);
3366         intel_crtc_update_cursor(crtc, true);
3367
3368         hsw_enable_ips(intel_crtc);
3369
3370         if (intel_crtc->config.has_pch_encoder)
3371                 lpt_pch_enable(crtc);
3372
3373         mutex_lock(&dev->struct_mutex);
3374         intel_update_fbc(dev);
3375         mutex_unlock(&dev->struct_mutex);
3376
3377         for_each_encoder_on_crtc(dev, crtc, encoder)
3378                 encoder->enable(encoder);
3379
3380         /*
3381          * There seems to be a race in PCH platform hw (at least on some
3382          * outputs) where an enabled pipe still completes any pageflip right
3383          * away (as if the pipe is off) instead of waiting for vblank. As soon
3384          * as the first vblank happend, everything works as expected. Hence just
3385          * wait for one vblank before returning to avoid strange things
3386          * happening.
3387          */
3388         intel_wait_for_vblank(dev, intel_crtc->pipe);
3389 }
3390
3391 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3392 {
3393         struct drm_device *dev = crtc->base.dev;
3394         struct drm_i915_private *dev_priv = dev->dev_private;
3395         int pipe = crtc->pipe;
3396
3397         /* To avoid upsetting the power well on haswell only disable the pfit if
3398          * it's in use. The hw state code will make sure we get this right. */
3399         if (crtc->config.pch_pfit.size) {
3400                 I915_WRITE(PF_CTL(pipe), 0);
3401                 I915_WRITE(PF_WIN_POS(pipe), 0);
3402                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3403         }
3404 }
3405
3406 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3407 {
3408         struct drm_device *dev = crtc->dev;
3409         struct drm_i915_private *dev_priv = dev->dev_private;
3410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411         struct intel_encoder *encoder;
3412         int pipe = intel_crtc->pipe;
3413         int plane = intel_crtc->plane;
3414         u32 reg, temp;
3415
3416
3417         if (!intel_crtc->active)
3418                 return;
3419
3420         for_each_encoder_on_crtc(dev, crtc, encoder)
3421                 encoder->disable(encoder);
3422
3423         intel_crtc_wait_for_pending_flips(crtc);
3424         drm_vblank_off(dev, pipe);
3425
3426         if (dev_priv->cfb_plane == plane)
3427                 intel_disable_fbc(dev);
3428
3429         intel_crtc_update_cursor(crtc, false);
3430         intel_disable_planes(crtc);
3431         intel_disable_plane(dev_priv, plane, pipe);
3432
3433         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3434         intel_disable_pipe(dev_priv, pipe);
3435
3436         ironlake_pfit_disable(intel_crtc);
3437
3438         for_each_encoder_on_crtc(dev, crtc, encoder)
3439                 if (encoder->post_disable)
3440                         encoder->post_disable(encoder);
3441
3442         ironlake_fdi_disable(crtc);
3443
3444         ironlake_disable_pch_transcoder(dev_priv, pipe);
3445         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3446
3447         if (HAS_PCH_CPT(dev)) {
3448                 /* disable TRANS_DP_CTL */
3449                 reg = TRANS_DP_CTL(pipe);
3450                 temp = I915_READ(reg);
3451                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3452                 temp |= TRANS_DP_PORT_SEL_NONE;
3453                 I915_WRITE(reg, temp);
3454
3455                 /* disable DPLL_SEL */
3456                 temp = I915_READ(PCH_DPLL_SEL);
3457                 switch (pipe) {
3458                 case 0:
3459                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3460                         break;
3461                 case 1:
3462                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3463                         break;
3464                 case 2:
3465                         /* C shares PLL A or B */
3466                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3467                         break;
3468                 default:
3469                         BUG(); /* wtf */
3470                 }
3471                 I915_WRITE(PCH_DPLL_SEL, temp);
3472         }
3473
3474         /* disable PCH DPLL */
3475         intel_disable_pch_pll(intel_crtc);
3476
3477         ironlake_fdi_pll_disable(intel_crtc);
3478
3479         intel_crtc->active = false;
3480         intel_update_watermarks(dev);
3481
3482         mutex_lock(&dev->struct_mutex);
3483         intel_update_fbc(dev);
3484         mutex_unlock(&dev->struct_mutex);
3485 }
3486
3487 static void haswell_crtc_disable(struct drm_crtc *crtc)
3488 {
3489         struct drm_device *dev = crtc->dev;
3490         struct drm_i915_private *dev_priv = dev->dev_private;
3491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3492         struct intel_encoder *encoder;
3493         int pipe = intel_crtc->pipe;
3494         int plane = intel_crtc->plane;
3495         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3496
3497         if (!intel_crtc->active)
3498                 return;
3499
3500         for_each_encoder_on_crtc(dev, crtc, encoder)
3501                 encoder->disable(encoder);
3502
3503         intel_crtc_wait_for_pending_flips(crtc);
3504         drm_vblank_off(dev, pipe);
3505
3506         /* FBC must be disabled before disabling the plane on HSW. */
3507         if (dev_priv->cfb_plane == plane)
3508                 intel_disable_fbc(dev);
3509
3510         hsw_disable_ips(intel_crtc);
3511
3512         intel_crtc_update_cursor(crtc, false);
3513         intel_disable_planes(crtc);
3514         intel_disable_plane(dev_priv, plane, pipe);
3515
3516         if (intel_crtc->config.has_pch_encoder)
3517                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3518         intel_disable_pipe(dev_priv, pipe);
3519
3520         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3521
3522         ironlake_pfit_disable(intel_crtc);
3523
3524         intel_ddi_disable_pipe_clock(intel_crtc);
3525
3526         for_each_encoder_on_crtc(dev, crtc, encoder)
3527                 if (encoder->post_disable)
3528                         encoder->post_disable(encoder);
3529
3530         if (intel_crtc->config.has_pch_encoder) {
3531                 lpt_disable_pch_transcoder(dev_priv);
3532                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3533                 intel_ddi_fdi_disable(crtc);
3534         }
3535
3536         intel_crtc->active = false;
3537         intel_update_watermarks(dev);
3538
3539         mutex_lock(&dev->struct_mutex);
3540         intel_update_fbc(dev);
3541         mutex_unlock(&dev->struct_mutex);
3542 }
3543
3544 static void ironlake_crtc_off(struct drm_crtc *crtc)
3545 {
3546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3547         intel_put_pch_pll(intel_crtc);
3548 }
3549
3550 static void haswell_crtc_off(struct drm_crtc *crtc)
3551 {
3552         intel_ddi_put_crtc_pll(crtc);
3553 }
3554
3555 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3556 {
3557         if (!enable && intel_crtc->overlay) {
3558                 struct drm_device *dev = intel_crtc->base.dev;
3559                 struct drm_i915_private *dev_priv = dev->dev_private;
3560
3561                 mutex_lock(&dev->struct_mutex);
3562                 dev_priv->mm.interruptible = false;
3563                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3564                 dev_priv->mm.interruptible = true;
3565                 mutex_unlock(&dev->struct_mutex);
3566         }
3567
3568         /* Let userspace switch the overlay on again. In most cases userspace
3569          * has to recompute where to put it anyway.
3570          */
3571 }
3572
3573 /**
3574  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3575  * cursor plane briefly if not already running after enabling the display
3576  * plane.
3577  * This workaround avoids occasional blank screens when self refresh is
3578  * enabled.
3579  */
3580 static void
3581 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3582 {
3583         u32 cntl = I915_READ(CURCNTR(pipe));
3584
3585         if ((cntl & CURSOR_MODE) == 0) {
3586                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3587
3588                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3589                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3590                 intel_wait_for_vblank(dev_priv->dev, pipe);
3591                 I915_WRITE(CURCNTR(pipe), cntl);
3592                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3593                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3594         }
3595 }
3596
3597 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3598 {
3599         struct drm_device *dev = crtc->base.dev;
3600         struct drm_i915_private *dev_priv = dev->dev_private;
3601         struct intel_crtc_config *pipe_config = &crtc->config;
3602
3603         if (!crtc->config.gmch_pfit.control)
3604                 return;
3605
3606         /*
3607          * The panel fitter should only be adjusted whilst the pipe is disabled,
3608          * according to register description and PRM.
3609          */
3610         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3611         assert_pipe_disabled(dev_priv, crtc->pipe);
3612
3613         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3614         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3615
3616         /* Border color in case we don't scale up to the full screen. Black by
3617          * default, change to something else for debugging. */
3618         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3619 }
3620
3621 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3622 {
3623         struct drm_device *dev = crtc->dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626         struct intel_encoder *encoder;
3627         int pipe = intel_crtc->pipe;
3628         int plane = intel_crtc->plane;
3629
3630         WARN_ON(!crtc->enabled);
3631
3632         if (intel_crtc->active)
3633                 return;
3634
3635         intel_crtc->active = true;
3636         intel_update_watermarks(dev);
3637
3638         mutex_lock(&dev_priv->dpio_lock);
3639
3640         for_each_encoder_on_crtc(dev, crtc, encoder)
3641                 if (encoder->pre_pll_enable)
3642                         encoder->pre_pll_enable(encoder);
3643
3644         intel_enable_pll(dev_priv, pipe);
3645
3646         for_each_encoder_on_crtc(dev, crtc, encoder)
3647                 if (encoder->pre_enable)
3648                         encoder->pre_enable(encoder);
3649
3650         /* VLV wants encoder enabling _before_ the pipe is up. */
3651         for_each_encoder_on_crtc(dev, crtc, encoder)
3652                 encoder->enable(encoder);
3653
3654         /* Enable panel fitting for eDP */
3655         i9xx_pfit_enable(intel_crtc);
3656
3657         intel_crtc_load_lut(crtc);
3658
3659         intel_enable_pipe(dev_priv, pipe, false);
3660         intel_enable_plane(dev_priv, plane, pipe);
3661         intel_enable_planes(crtc);
3662         intel_crtc_update_cursor(crtc, true);
3663
3664         intel_update_fbc(dev);
3665
3666         mutex_unlock(&dev_priv->dpio_lock);
3667 }
3668
3669 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3670 {
3671         struct drm_device *dev = crtc->dev;
3672         struct drm_i915_private *dev_priv = dev->dev_private;
3673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3674         struct intel_encoder *encoder;
3675         int pipe = intel_crtc->pipe;
3676         int plane = intel_crtc->plane;
3677
3678         WARN_ON(!crtc->enabled);
3679
3680         if (intel_crtc->active)
3681                 return;
3682
3683         intel_crtc->active = true;
3684         intel_update_watermarks(dev);
3685
3686         intel_enable_pll(dev_priv, pipe);
3687
3688         for_each_encoder_on_crtc(dev, crtc, encoder)
3689                 if (encoder->pre_enable)
3690                         encoder->pre_enable(encoder);
3691
3692         /* Enable panel fitting for LVDS */
3693         i9xx_pfit_enable(intel_crtc);
3694
3695         intel_crtc_load_lut(crtc);
3696
3697         intel_enable_pipe(dev_priv, pipe, false);
3698         intel_enable_plane(dev_priv, plane, pipe);
3699         intel_enable_planes(crtc);
3700         intel_crtc_update_cursor(crtc, true);
3701         if (IS_G4X(dev))
3702                 g4x_fixup_plane(dev_priv, pipe);
3703
3704         /* Give the overlay scaler a chance to enable if it's on this pipe */
3705         intel_crtc_dpms_overlay(intel_crtc, true);
3706
3707         intel_update_fbc(dev);
3708
3709         for_each_encoder_on_crtc(dev, crtc, encoder)
3710                 encoder->enable(encoder);
3711 }
3712
3713 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3714 {
3715         struct drm_device *dev = crtc->base.dev;
3716         struct drm_i915_private *dev_priv = dev->dev_private;
3717
3718         if (!crtc->config.gmch_pfit.control)
3719                 return;
3720
3721         assert_pipe_disabled(dev_priv, crtc->pipe);
3722
3723         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3724                          I915_READ(PFIT_CONTROL));
3725         I915_WRITE(PFIT_CONTROL, 0);
3726 }
3727
3728 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3729 {
3730         struct drm_device *dev = crtc->dev;
3731         struct drm_i915_private *dev_priv = dev->dev_private;
3732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3733         struct intel_encoder *encoder;
3734         int pipe = intel_crtc->pipe;
3735         int plane = intel_crtc->plane;
3736
3737         if (!intel_crtc->active)
3738                 return;
3739
3740         for_each_encoder_on_crtc(dev, crtc, encoder)
3741                 encoder->disable(encoder);
3742
3743         /* Give the overlay scaler a chance to disable if it's on this pipe */
3744         intel_crtc_wait_for_pending_flips(crtc);
3745         drm_vblank_off(dev, pipe);
3746
3747         if (dev_priv->cfb_plane == plane)
3748                 intel_disable_fbc(dev);
3749
3750         intel_crtc_dpms_overlay(intel_crtc, false);
3751         intel_crtc_update_cursor(crtc, false);
3752         intel_disable_planes(crtc);
3753         intel_disable_plane(dev_priv, plane, pipe);
3754
3755         intel_disable_pipe(dev_priv, pipe);
3756
3757         i9xx_pfit_disable(intel_crtc);
3758
3759         for_each_encoder_on_crtc(dev, crtc, encoder)
3760                 if (encoder->post_disable)
3761                         encoder->post_disable(encoder);
3762
3763         intel_disable_pll(dev_priv, pipe);
3764
3765         intel_crtc->active = false;
3766         intel_update_fbc(dev);
3767         intel_update_watermarks(dev);
3768 }
3769
3770 static void i9xx_crtc_off(struct drm_crtc *crtc)
3771 {
3772 }
3773
3774 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3775                                     bool enabled)
3776 {
3777         struct drm_device *dev = crtc->dev;
3778         struct drm_i915_master_private *master_priv;
3779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3780         int pipe = intel_crtc->pipe;
3781
3782         if (!dev->primary->master)
3783                 return;
3784
3785         master_priv = dev->primary->master->driver_priv;
3786         if (!master_priv->sarea_priv)
3787                 return;
3788
3789         switch (pipe) {
3790         case 0:
3791                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3792                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3793                 break;
3794         case 1:
3795                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3796                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3797                 break;
3798         default:
3799                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3800                 break;
3801         }
3802 }
3803
3804 /**
3805  * Sets the power management mode of the pipe and plane.
3806  */
3807 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3808 {
3809         struct drm_device *dev = crtc->dev;
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811         struct intel_encoder *intel_encoder;
3812         bool enable = false;
3813
3814         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3815                 enable |= intel_encoder->connectors_active;
3816
3817         if (enable)
3818                 dev_priv->display.crtc_enable(crtc);
3819         else
3820                 dev_priv->display.crtc_disable(crtc);
3821
3822         intel_crtc_update_sarea(crtc, enable);
3823 }
3824
3825 static void intel_crtc_disable(struct drm_crtc *crtc)
3826 {
3827         struct drm_device *dev = crtc->dev;
3828         struct drm_connector *connector;
3829         struct drm_i915_private *dev_priv = dev->dev_private;
3830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831
3832         /* crtc should still be enabled when we disable it. */
3833         WARN_ON(!crtc->enabled);
3834
3835         dev_priv->display.crtc_disable(crtc);
3836         intel_crtc->eld_vld = false;
3837         intel_crtc_update_sarea(crtc, false);
3838         dev_priv->display.off(crtc);
3839
3840         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3841         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3842
3843         if (crtc->fb) {
3844                 mutex_lock(&dev->struct_mutex);
3845                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3846                 mutex_unlock(&dev->struct_mutex);
3847                 crtc->fb = NULL;
3848         }
3849
3850         /* Update computed state. */
3851         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3852                 if (!connector->encoder || !connector->encoder->crtc)
3853                         continue;
3854
3855                 if (connector->encoder->crtc != crtc)
3856                         continue;
3857
3858                 connector->dpms = DRM_MODE_DPMS_OFF;
3859                 to_intel_encoder(connector->encoder)->connectors_active = false;
3860         }
3861 }
3862
3863 void intel_modeset_disable(struct drm_device *dev)
3864 {
3865         struct drm_crtc *crtc;
3866
3867         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3868                 if (crtc->enabled)
3869                         intel_crtc_disable(crtc);
3870         }
3871 }
3872
3873 void intel_encoder_destroy(struct drm_encoder *encoder)
3874 {
3875         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3876
3877         drm_encoder_cleanup(encoder);
3878         kfree(intel_encoder);
3879 }
3880
3881 /* Simple dpms helper for encodres with just one connector, no cloning and only
3882  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3883  * state of the entire output pipe. */
3884 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3885 {
3886         if (mode == DRM_MODE_DPMS_ON) {
3887                 encoder->connectors_active = true;
3888
3889                 intel_crtc_update_dpms(encoder->base.crtc);
3890         } else {
3891                 encoder->connectors_active = false;
3892
3893                 intel_crtc_update_dpms(encoder->base.crtc);
3894         }
3895 }
3896
3897 /* Cross check the actual hw state with our own modeset state tracking (and it's
3898  * internal consistency). */
3899 static void intel_connector_check_state(struct intel_connector *connector)
3900 {
3901         if (connector->get_hw_state(connector)) {
3902                 struct intel_encoder *encoder = connector->encoder;
3903                 struct drm_crtc *crtc;
3904                 bool encoder_enabled;
3905                 enum pipe pipe;
3906
3907                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3908                               connector->base.base.id,
3909                               drm_get_connector_name(&connector->base));
3910
3911                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3912                      "wrong connector dpms state\n");
3913                 WARN(connector->base.encoder != &encoder->base,
3914                      "active connector not linked to encoder\n");
3915                 WARN(!encoder->connectors_active,
3916                      "encoder->connectors_active not set\n");
3917
3918                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3919                 WARN(!encoder_enabled, "encoder not enabled\n");
3920                 if (WARN_ON(!encoder->base.crtc))
3921                         return;
3922
3923                 crtc = encoder->base.crtc;
3924
3925                 WARN(!crtc->enabled, "crtc not enabled\n");
3926                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3927                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3928                      "encoder active on the wrong pipe\n");
3929         }
3930 }
3931
3932 /* Even simpler default implementation, if there's really no special case to
3933  * consider. */
3934 void intel_connector_dpms(struct drm_connector *connector, int mode)
3935 {
3936         struct intel_encoder *encoder = intel_attached_encoder(connector);
3937
3938         /* All the simple cases only support two dpms states. */
3939         if (mode != DRM_MODE_DPMS_ON)
3940                 mode = DRM_MODE_DPMS_OFF;
3941
3942         if (mode == connector->dpms)
3943                 return;
3944
3945         connector->dpms = mode;
3946
3947         /* Only need to change hw state when actually enabled */
3948         if (encoder->base.crtc)
3949                 intel_encoder_dpms(encoder, mode);
3950         else
3951                 WARN_ON(encoder->connectors_active != false);
3952
3953         intel_modeset_check_state(connector->dev);
3954 }
3955
3956 /* Simple connector->get_hw_state implementation for encoders that support only
3957  * one connector and no cloning and hence the encoder state determines the state
3958  * of the connector. */
3959 bool intel_connector_get_hw_state(struct intel_connector *connector)
3960 {
3961         enum pipe pipe = 0;
3962         struct intel_encoder *encoder = connector->encoder;
3963
3964         return encoder->get_hw_state(encoder, &pipe);
3965 }
3966
3967 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3968                                      struct intel_crtc_config *pipe_config)
3969 {
3970         struct drm_i915_private *dev_priv = dev->dev_private;
3971         struct intel_crtc *pipe_B_crtc =
3972                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3973
3974         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3975                       pipe_name(pipe), pipe_config->fdi_lanes);
3976         if (pipe_config->fdi_lanes > 4) {
3977                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3978                               pipe_name(pipe), pipe_config->fdi_lanes);
3979                 return false;
3980         }
3981
3982         if (IS_HASWELL(dev)) {
3983                 if (pipe_config->fdi_lanes > 2) {
3984                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3985                                       pipe_config->fdi_lanes);
3986                         return false;
3987                 } else {
3988                         return true;
3989                 }
3990         }
3991
3992         if (INTEL_INFO(dev)->num_pipes == 2)
3993                 return true;
3994
3995         /* Ivybridge 3 pipe is really complicated */
3996         switch (pipe) {
3997         case PIPE_A:
3998                 return true;
3999         case PIPE_B:
4000                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4001                     pipe_config->fdi_lanes > 2) {
4002                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4003                                       pipe_name(pipe), pipe_config->fdi_lanes);
4004                         return false;
4005                 }
4006                 return true;
4007         case PIPE_C:
4008                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4009                     pipe_B_crtc->config.fdi_lanes <= 2) {
4010                         if (pipe_config->fdi_lanes > 2) {
4011                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4012                                               pipe_name(pipe), pipe_config->fdi_lanes);
4013                                 return false;
4014                         }
4015                 } else {
4016                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4017                         return false;
4018                 }
4019                 return true;
4020         default:
4021                 BUG();
4022         }
4023 }
4024
4025 #define RETRY 1
4026 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4027                                        struct intel_crtc_config *pipe_config)
4028 {
4029         struct drm_device *dev = intel_crtc->base.dev;
4030         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4031         int lane, link_bw, fdi_dotclock;
4032         bool setup_ok, needs_recompute = false;
4033
4034 retry:
4035         /* FDI is a binary signal running at ~2.7GHz, encoding
4036          * each output octet as 10 bits. The actual frequency
4037          * is stored as a divider into a 100MHz clock, and the
4038          * mode pixel clock is stored in units of 1KHz.
4039          * Hence the bw of each lane in terms of the mode signal
4040          * is:
4041          */
4042         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4043
4044         fdi_dotclock = adjusted_mode->clock;
4045         fdi_dotclock /= pipe_config->pixel_multiplier;
4046
4047         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4048                                            pipe_config->pipe_bpp);
4049
4050         pipe_config->fdi_lanes = lane;
4051
4052         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4053                                link_bw, &pipe_config->fdi_m_n);
4054
4055         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4056                                             intel_crtc->pipe, pipe_config);
4057         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4058                 pipe_config->pipe_bpp -= 2*3;
4059                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4060                               pipe_config->pipe_bpp);
4061                 needs_recompute = true;
4062                 pipe_config->bw_constrained = true;
4063
4064                 goto retry;
4065         }
4066
4067         if (needs_recompute)
4068                 return RETRY;
4069
4070         return setup_ok ? 0 : -EINVAL;
4071 }
4072
4073 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4074                                    struct intel_crtc_config *pipe_config)
4075 {
4076         pipe_config->ips_enabled = i915_enable_ips &&
4077                                    hsw_crtc_supports_ips(crtc) &&
4078                                    pipe_config->pipe_bpp == 24;
4079 }
4080
4081 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4082                                      struct intel_crtc_config *pipe_config)
4083 {
4084         struct drm_device *dev = crtc->dev;
4085         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4087
4088         if (HAS_PCH_SPLIT(dev)) {
4089                 /* FDI link clock is fixed at 2.7G */
4090                 if (pipe_config->requested_mode.clock * 3
4091                     > IRONLAKE_FDI_FREQ * 4)
4092                         return -EINVAL;
4093         }
4094
4095         /* All interlaced capable intel hw wants timings in frames. Note though
4096          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4097          * timings, so we need to be careful not to clobber these.*/
4098         if (!pipe_config->timings_set)
4099                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4100
4101         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4102          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4103          */
4104         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4105                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4106                 return -EINVAL;
4107
4108         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4109                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4110         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4111                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4112                  * for lvds. */
4113                 pipe_config->pipe_bpp = 8*3;
4114         }
4115
4116         if (IS_HASWELL(dev))
4117                 hsw_compute_ips_config(intel_crtc, pipe_config);
4118
4119         if (pipe_config->has_pch_encoder)
4120                 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
4121
4122         return 0;
4123 }
4124
4125 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4126 {
4127         return 400000; /* FIXME */
4128 }
4129
4130 static int i945_get_display_clock_speed(struct drm_device *dev)
4131 {
4132         return 400000;
4133 }
4134
4135 static int i915_get_display_clock_speed(struct drm_device *dev)
4136 {
4137         return 333000;
4138 }
4139
4140 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4141 {
4142         return 200000;
4143 }
4144
4145 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4146 {
4147         u16 gcfgc = 0;
4148
4149         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4150
4151         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4152                 return 133000;
4153         else {
4154                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4155                 case GC_DISPLAY_CLOCK_333_MHZ:
4156                         return 333000;
4157                 default:
4158                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4159                         return 190000;
4160                 }
4161         }
4162 }
4163
4164 static int i865_get_display_clock_speed(struct drm_device *dev)
4165 {
4166         return 266000;
4167 }
4168
4169 static int i855_get_display_clock_speed(struct drm_device *dev)
4170 {
4171         u16 hpllcc = 0;
4172         /* Assume that the hardware is in the high speed state.  This
4173          * should be the default.
4174          */
4175         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4176         case GC_CLOCK_133_200:
4177         case GC_CLOCK_100_200:
4178                 return 200000;
4179         case GC_CLOCK_166_250:
4180                 return 250000;
4181         case GC_CLOCK_100_133:
4182                 return 133000;
4183         }
4184
4185         /* Shouldn't happen */
4186         return 0;
4187 }
4188
4189 static int i830_get_display_clock_speed(struct drm_device *dev)
4190 {
4191         return 133000;
4192 }
4193
4194 static void
4195 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4196 {
4197         while (*num > DATA_LINK_M_N_MASK ||
4198                *den > DATA_LINK_M_N_MASK) {
4199                 *num >>= 1;
4200                 *den >>= 1;
4201         }
4202 }
4203
4204 static void compute_m_n(unsigned int m, unsigned int n,
4205                         uint32_t *ret_m, uint32_t *ret_n)
4206 {
4207         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4208         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4209         intel_reduce_m_n_ratio(ret_m, ret_n);
4210 }
4211
4212 void
4213 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4214                        int pixel_clock, int link_clock,
4215                        struct intel_link_m_n *m_n)
4216 {
4217         m_n->tu = 64;
4218
4219         compute_m_n(bits_per_pixel * pixel_clock,
4220                     link_clock * nlanes * 8,
4221                     &m_n->gmch_m, &m_n->gmch_n);
4222
4223         compute_m_n(pixel_clock, link_clock,
4224                     &m_n->link_m, &m_n->link_n);
4225 }
4226
4227 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4228 {
4229         if (i915_panel_use_ssc >= 0)
4230                 return i915_panel_use_ssc != 0;
4231         return dev_priv->vbt.lvds_use_ssc
4232                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4233 }
4234
4235 static int vlv_get_refclk(struct drm_crtc *crtc)
4236 {
4237         struct drm_device *dev = crtc->dev;
4238         struct drm_i915_private *dev_priv = dev->dev_private;
4239         int refclk = 27000; /* for DP & HDMI */
4240
4241         return 100000; /* only one validated so far */
4242
4243         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4244                 refclk = 96000;
4245         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4246                 if (intel_panel_use_ssc(dev_priv))
4247                         refclk = 100000;
4248                 else
4249                         refclk = 96000;
4250         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4251                 refclk = 100000;
4252         }
4253
4254         return refclk;
4255 }
4256
4257 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4258 {
4259         struct drm_device *dev = crtc->dev;
4260         struct drm_i915_private *dev_priv = dev->dev_private;
4261         int refclk;
4262
4263         if (IS_VALLEYVIEW(dev)) {
4264                 refclk = vlv_get_refclk(crtc);
4265         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4266             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4267                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4268                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4269                               refclk / 1000);
4270         } else if (!IS_GEN2(dev)) {
4271                 refclk = 96000;
4272         } else {
4273                 refclk = 48000;
4274         }
4275
4276         return refclk;
4277 }
4278
4279 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4280 {
4281         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4282 }
4283
4284 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4285 {
4286         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4287 }
4288
4289 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4290                                      intel_clock_t *reduced_clock)
4291 {
4292         struct drm_device *dev = crtc->base.dev;
4293         struct drm_i915_private *dev_priv = dev->dev_private;
4294         int pipe = crtc->pipe;
4295         u32 fp, fp2 = 0;
4296
4297         if (IS_PINEVIEW(dev)) {
4298                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4299                 if (reduced_clock)
4300                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4301         } else {
4302                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4303                 if (reduced_clock)
4304                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4305         }
4306
4307         I915_WRITE(FP0(pipe), fp);
4308
4309         crtc->lowfreq_avail = false;
4310         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4311             reduced_clock && i915_powersave) {
4312                 I915_WRITE(FP1(pipe), fp2);
4313                 crtc->lowfreq_avail = true;
4314         } else {
4315                 I915_WRITE(FP1(pipe), fp);
4316         }
4317 }
4318
4319 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4320 {
4321         u32 reg_val;
4322
4323         /*
4324          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4325          * and set it to a reasonable value instead.
4326          */
4327         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4328         reg_val &= 0xffffff00;
4329         reg_val |= 0x00000030;
4330         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4331
4332         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4333         reg_val &= 0x8cffffff;
4334         reg_val = 0x8c000000;
4335         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4336
4337         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4338         reg_val &= 0xffffff00;
4339         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4340
4341         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4342         reg_val &= 0x00ffffff;
4343         reg_val |= 0xb0000000;
4344         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4345 }
4346
4347 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4348                                          struct intel_link_m_n *m_n)
4349 {
4350         struct drm_device *dev = crtc->base.dev;
4351         struct drm_i915_private *dev_priv = dev->dev_private;
4352         int pipe = crtc->pipe;
4353
4354         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4355         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4356         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4357         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4358 }
4359
4360 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4361                                          struct intel_link_m_n *m_n)
4362 {
4363         struct drm_device *dev = crtc->base.dev;
4364         struct drm_i915_private *dev_priv = dev->dev_private;
4365         int pipe = crtc->pipe;
4366         enum transcoder transcoder = crtc->config.cpu_transcoder;
4367
4368         if (INTEL_INFO(dev)->gen >= 5) {
4369                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4370                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4371                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4372                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4373         } else {
4374                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4375                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4376                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4377                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4378         }
4379 }
4380
4381 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4382 {
4383         if (crtc->config.has_pch_encoder)
4384                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4385         else
4386                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4387 }
4388
4389 static void vlv_update_pll(struct intel_crtc *crtc)
4390 {
4391         struct drm_device *dev = crtc->base.dev;
4392         struct drm_i915_private *dev_priv = dev->dev_private;
4393         struct intel_encoder *encoder;
4394         int pipe = crtc->pipe;
4395         u32 dpll, mdiv;
4396         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4397         bool is_hdmi;
4398         u32 coreclk, reg_val, dpll_md;
4399
4400         mutex_lock(&dev_priv->dpio_lock);
4401
4402         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4403
4404         bestn = crtc->config.dpll.n;
4405         bestm1 = crtc->config.dpll.m1;
4406         bestm2 = crtc->config.dpll.m2;
4407         bestp1 = crtc->config.dpll.p1;
4408         bestp2 = crtc->config.dpll.p2;
4409
4410         /* See eDP HDMI DPIO driver vbios notes doc */
4411
4412         /* PLL B needs special handling */
4413         if (pipe)
4414                 vlv_pllb_recal_opamp(dev_priv);
4415
4416         /* Set up Tx target for periodic Rcomp update */
4417         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4418
4419         /* Disable target IRef on PLL */
4420         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4421         reg_val &= 0x00ffffff;
4422         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4423
4424         /* Disable fast lock */
4425         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4426
4427         /* Set idtafcrecal before PLL is enabled */
4428         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4429         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4430         mdiv |= ((bestn << DPIO_N_SHIFT));
4431         mdiv |= (1 << DPIO_K_SHIFT);
4432
4433         /*
4434          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4435          * but we don't support that).
4436          * Note: don't use the DAC post divider as it seems unstable.
4437          */
4438         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4439         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4440
4441         mdiv |= DPIO_ENABLE_CALIBRATION;
4442         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4443
4444         /* Set HBR and RBR LPF coefficients */
4445         if (crtc->config.port_clock == 162000 ||
4446             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4447                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4448                                  0x005f0021);
4449         else
4450                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4451                                  0x00d0000f);
4452
4453         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4454             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4455                 /* Use SSC source */
4456                 if (!pipe)
4457                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4458                                          0x0df40000);
4459                 else
4460                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4461                                          0x0df70000);
4462         } else { /* HDMI or VGA */
4463                 /* Use bend source */
4464                 if (!pipe)
4465                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4466                                          0x0df70000);
4467                 else
4468                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4469                                          0x0df40000);
4470         }
4471
4472         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4473         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4474         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4475             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4476                 coreclk |= 0x01000000;
4477         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4478
4479         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4480
4481         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4482                 if (encoder->pre_pll_enable)
4483                         encoder->pre_pll_enable(encoder);
4484
4485         /* Enable DPIO clock input */
4486         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4487                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4488         if (pipe)
4489                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4490
4491         dpll |= DPLL_VCO_ENABLE;
4492         I915_WRITE(DPLL(pipe), dpll);
4493         POSTING_READ(DPLL(pipe));
4494         udelay(150);
4495
4496         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4497                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4498
4499         dpll_md = (crtc->config.pixel_multiplier - 1)
4500                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4501         I915_WRITE(DPLL_MD(pipe), dpll_md);
4502         POSTING_READ(DPLL_MD(pipe));
4503
4504         if (crtc->config.has_dp_encoder)
4505                 intel_dp_set_m_n(crtc);
4506
4507         mutex_unlock(&dev_priv->dpio_lock);
4508 }
4509
4510 static void i9xx_update_pll(struct intel_crtc *crtc,
4511                             intel_clock_t *reduced_clock,
4512                             int num_connectors)
4513 {
4514         struct drm_device *dev = crtc->base.dev;
4515         struct drm_i915_private *dev_priv = dev->dev_private;
4516         struct intel_encoder *encoder;
4517         int pipe = crtc->pipe;
4518         u32 dpll;
4519         bool is_sdvo;
4520         struct dpll *clock = &crtc->config.dpll;
4521
4522         i9xx_update_pll_dividers(crtc, reduced_clock);
4523
4524         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4525                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4526
4527         dpll = DPLL_VGA_MODE_DIS;
4528
4529         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4530                 dpll |= DPLLB_MODE_LVDS;
4531         else
4532                 dpll |= DPLLB_MODE_DAC_SERIAL;
4533
4534         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4535                 dpll |= (crtc->config.pixel_multiplier - 1)
4536                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4537         }
4538
4539         if (is_sdvo)
4540                 dpll |= DPLL_DVO_HIGH_SPEED;
4541
4542         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4543                 dpll |= DPLL_DVO_HIGH_SPEED;
4544
4545         /* compute bitmask from p1 value */
4546         if (IS_PINEVIEW(dev))
4547                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4548         else {
4549                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4550                 if (IS_G4X(dev) && reduced_clock)
4551                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4552         }
4553         switch (clock->p2) {
4554         case 5:
4555                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4556                 break;
4557         case 7:
4558                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4559                 break;
4560         case 10:
4561                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4562                 break;
4563         case 14:
4564                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4565                 break;
4566         }
4567         if (INTEL_INFO(dev)->gen >= 4)
4568                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4569
4570         if (crtc->config.sdvo_tv_clock)
4571                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4572         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4573                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4574                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4575         else
4576                 dpll |= PLL_REF_INPUT_DREFCLK;
4577
4578         dpll |= DPLL_VCO_ENABLE;
4579         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4580         POSTING_READ(DPLL(pipe));
4581         udelay(150);
4582
4583         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4584                 if (encoder->pre_pll_enable)
4585                         encoder->pre_pll_enable(encoder);
4586
4587         if (crtc->config.has_dp_encoder)
4588                 intel_dp_set_m_n(crtc);
4589
4590         I915_WRITE(DPLL(pipe), dpll);
4591
4592         /* Wait for the clocks to stabilize. */
4593         POSTING_READ(DPLL(pipe));
4594         udelay(150);
4595
4596         if (INTEL_INFO(dev)->gen >= 4) {
4597                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4598                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4599                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4600         } else {
4601                 /* The pixel multiplier can only be updated once the
4602                  * DPLL is enabled and the clocks are stable.
4603                  *
4604                  * So write it again.
4605                  */
4606                 I915_WRITE(DPLL(pipe), dpll);
4607         }
4608 }
4609
4610 static void i8xx_update_pll(struct intel_crtc *crtc,
4611                             intel_clock_t *reduced_clock,
4612                             int num_connectors)
4613 {
4614         struct drm_device *dev = crtc->base.dev;
4615         struct drm_i915_private *dev_priv = dev->dev_private;
4616         struct intel_encoder *encoder;
4617         int pipe = crtc->pipe;
4618         u32 dpll;
4619         struct dpll *clock = &crtc->config.dpll;
4620
4621         i9xx_update_pll_dividers(crtc, reduced_clock);
4622
4623         dpll = DPLL_VGA_MODE_DIS;
4624
4625         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4626                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4627         } else {
4628                 if (clock->p1 == 2)
4629                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4630                 else
4631                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4632                 if (clock->p2 == 4)
4633                         dpll |= PLL_P2_DIVIDE_BY_4;
4634         }
4635
4636         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4637                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4638                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4639         else
4640                 dpll |= PLL_REF_INPUT_DREFCLK;
4641
4642         dpll |= DPLL_VCO_ENABLE;
4643         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4644         POSTING_READ(DPLL(pipe));
4645         udelay(150);
4646
4647         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4648                 if (encoder->pre_pll_enable)
4649                         encoder->pre_pll_enable(encoder);
4650
4651         I915_WRITE(DPLL(pipe), dpll);
4652
4653         /* Wait for the clocks to stabilize. */
4654         POSTING_READ(DPLL(pipe));
4655         udelay(150);
4656
4657         /* The pixel multiplier can only be updated once the
4658          * DPLL is enabled and the clocks are stable.
4659          *
4660          * So write it again.
4661          */
4662         I915_WRITE(DPLL(pipe), dpll);
4663 }
4664
4665 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4666 {
4667         struct drm_device *dev = intel_crtc->base.dev;
4668         struct drm_i915_private *dev_priv = dev->dev_private;
4669         enum pipe pipe = intel_crtc->pipe;
4670         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4671         struct drm_display_mode *adjusted_mode =
4672                 &intel_crtc->config.adjusted_mode;
4673         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4674         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4675
4676         /* We need to be careful not to changed the adjusted mode, for otherwise
4677          * the hw state checker will get angry at the mismatch. */
4678         crtc_vtotal = adjusted_mode->crtc_vtotal;
4679         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4680
4681         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4682                 /* the chip adds 2 halflines automatically */
4683                 crtc_vtotal -= 1;
4684                 crtc_vblank_end -= 1;
4685                 vsyncshift = adjusted_mode->crtc_hsync_start
4686                              - adjusted_mode->crtc_htotal / 2;
4687         } else {
4688                 vsyncshift = 0;
4689         }
4690
4691         if (INTEL_INFO(dev)->gen > 3)
4692                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4693
4694         I915_WRITE(HTOTAL(cpu_transcoder),
4695                    (adjusted_mode->crtc_hdisplay - 1) |
4696                    ((adjusted_mode->crtc_htotal - 1) << 16));
4697         I915_WRITE(HBLANK(cpu_transcoder),
4698                    (adjusted_mode->crtc_hblank_start - 1) |
4699                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4700         I915_WRITE(HSYNC(cpu_transcoder),
4701                    (adjusted_mode->crtc_hsync_start - 1) |
4702                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4703
4704         I915_WRITE(VTOTAL(cpu_transcoder),
4705                    (adjusted_mode->crtc_vdisplay - 1) |
4706                    ((crtc_vtotal - 1) << 16));
4707         I915_WRITE(VBLANK(cpu_transcoder),
4708                    (adjusted_mode->crtc_vblank_start - 1) |
4709                    ((crtc_vblank_end - 1) << 16));
4710         I915_WRITE(VSYNC(cpu_transcoder),
4711                    (adjusted_mode->crtc_vsync_start - 1) |
4712                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4713
4714         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4715          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4716          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4717          * bits. */
4718         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4719             (pipe == PIPE_B || pipe == PIPE_C))
4720                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4721
4722         /* pipesrc controls the size that is scaled from, which should
4723          * always be the user's requested size.
4724          */
4725         I915_WRITE(PIPESRC(pipe),
4726                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4727 }
4728
4729 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4730                                    struct intel_crtc_config *pipe_config)
4731 {
4732         struct drm_device *dev = crtc->base.dev;
4733         struct drm_i915_private *dev_priv = dev->dev_private;
4734         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4735         uint32_t tmp;
4736
4737         tmp = I915_READ(HTOTAL(cpu_transcoder));
4738         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4739         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4740         tmp = I915_READ(HBLANK(cpu_transcoder));
4741         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4742         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4743         tmp = I915_READ(HSYNC(cpu_transcoder));
4744         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4745         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4746
4747         tmp = I915_READ(VTOTAL(cpu_transcoder));
4748         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4749         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4750         tmp = I915_READ(VBLANK(cpu_transcoder));
4751         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4752         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4753         tmp = I915_READ(VSYNC(cpu_transcoder));
4754         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4755         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4756
4757         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4758                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4759                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4760                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4761         }
4762
4763         tmp = I915_READ(PIPESRC(crtc->pipe));
4764         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4765         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4766 }
4767
4768 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4769 {
4770         struct drm_device *dev = intel_crtc->base.dev;
4771         struct drm_i915_private *dev_priv = dev->dev_private;
4772         uint32_t pipeconf;
4773
4774         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4775
4776         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4777                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4778                  * core speed.
4779                  *
4780                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4781                  * pipe == 0 check?
4782                  */
4783                 if (intel_crtc->config.requested_mode.clock >
4784                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4785                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4786                 else
4787                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4788         }
4789
4790         /* only g4x and later have fancy bpc/dither controls */
4791         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4792                 pipeconf &= ~(PIPECONF_BPC_MASK |
4793                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4794
4795                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4796                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4797                         pipeconf |= PIPECONF_DITHER_EN |
4798                                     PIPECONF_DITHER_TYPE_SP;
4799
4800                 switch (intel_crtc->config.pipe_bpp) {
4801                 case 18:
4802                         pipeconf |= PIPECONF_6BPC;
4803                         break;
4804                 case 24:
4805                         pipeconf |= PIPECONF_8BPC;
4806                         break;
4807                 case 30:
4808                         pipeconf |= PIPECONF_10BPC;
4809                         break;
4810                 default:
4811                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4812                         BUG();
4813                 }
4814         }
4815
4816         if (HAS_PIPE_CXSR(dev)) {
4817                 if (intel_crtc->lowfreq_avail) {
4818                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4819                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4820                 } else {
4821                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4822                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4823                 }
4824         }
4825
4826         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4827         if (!IS_GEN2(dev) &&
4828             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4829                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4830         else
4831                 pipeconf |= PIPECONF_PROGRESSIVE;
4832
4833         if (IS_VALLEYVIEW(dev)) {
4834                 if (intel_crtc->config.limited_color_range)
4835                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4836                 else
4837                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4838         }
4839
4840         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4841         POSTING_READ(PIPECONF(intel_crtc->pipe));
4842 }
4843
4844 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4845                               int x, int y,
4846                               struct drm_framebuffer *fb)
4847 {
4848         struct drm_device *dev = crtc->dev;
4849         struct drm_i915_private *dev_priv = dev->dev_private;
4850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4851         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4852         int pipe = intel_crtc->pipe;
4853         int plane = intel_crtc->plane;
4854         int refclk, num_connectors = 0;
4855         intel_clock_t clock, reduced_clock;
4856         u32 dspcntr;
4857         bool ok, has_reduced_clock = false;
4858         bool is_lvds = false;
4859         struct intel_encoder *encoder;
4860         const intel_limit_t *limit;
4861         int ret;
4862
4863         for_each_encoder_on_crtc(dev, crtc, encoder) {
4864                 switch (encoder->type) {
4865                 case INTEL_OUTPUT_LVDS:
4866                         is_lvds = true;
4867                         break;
4868                 }
4869
4870                 num_connectors++;
4871         }
4872
4873         refclk = i9xx_get_refclk(crtc, num_connectors);
4874
4875         /*
4876          * Returns a set of divisors for the desired target clock with the given
4877          * refclk, or FALSE.  The returned values represent the clock equation:
4878          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4879          */
4880         limit = intel_limit(crtc, refclk);
4881         ok = dev_priv->display.find_dpll(limit, crtc,
4882                                          intel_crtc->config.port_clock,
4883                                          refclk, NULL, &clock);
4884         if (!ok && !intel_crtc->config.clock_set) {
4885                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4886                 return -EINVAL;
4887         }
4888
4889         /* Ensure that the cursor is valid for the new mode before changing... */
4890         intel_crtc_update_cursor(crtc, true);
4891
4892         if (is_lvds && dev_priv->lvds_downclock_avail) {
4893                 /*
4894                  * Ensure we match the reduced clock's P to the target clock.
4895                  * If the clocks don't match, we can't switch the display clock
4896                  * by using the FP0/FP1. In such case we will disable the LVDS
4897                  * downclock feature.
4898                 */
4899                 has_reduced_clock =
4900                         dev_priv->display.find_dpll(limit, crtc,
4901                                                     dev_priv->lvds_downclock,
4902                                                     refclk, &clock,
4903                                                     &reduced_clock);
4904         }
4905         /* Compat-code for transition, will disappear. */
4906         if (!intel_crtc->config.clock_set) {
4907                 intel_crtc->config.dpll.n = clock.n;
4908                 intel_crtc->config.dpll.m1 = clock.m1;
4909                 intel_crtc->config.dpll.m2 = clock.m2;
4910                 intel_crtc->config.dpll.p1 = clock.p1;
4911                 intel_crtc->config.dpll.p2 = clock.p2;
4912         }
4913
4914         if (IS_GEN2(dev))
4915                 i8xx_update_pll(intel_crtc,
4916                                 has_reduced_clock ? &reduced_clock : NULL,
4917                                 num_connectors);
4918         else if (IS_VALLEYVIEW(dev))
4919                 vlv_update_pll(intel_crtc);
4920         else
4921                 i9xx_update_pll(intel_crtc,
4922                                 has_reduced_clock ? &reduced_clock : NULL,
4923                                 num_connectors);
4924
4925         /* Set up the display plane register */
4926         dspcntr = DISPPLANE_GAMMA_ENABLE;
4927
4928         if (!IS_VALLEYVIEW(dev)) {
4929                 if (pipe == 0)
4930                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4931                 else
4932                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4933         }
4934
4935         intel_set_pipe_timings(intel_crtc);
4936
4937         /* pipesrc and dspsize control the size that is scaled from,
4938          * which should always be the user's requested size.
4939          */
4940         I915_WRITE(DSPSIZE(plane),
4941                    ((mode->vdisplay - 1) << 16) |
4942                    (mode->hdisplay - 1));
4943         I915_WRITE(DSPPOS(plane), 0);
4944
4945         i9xx_set_pipeconf(intel_crtc);
4946
4947         I915_WRITE(DSPCNTR(plane), dspcntr);
4948         POSTING_READ(DSPCNTR(plane));
4949
4950         ret = intel_pipe_set_base(crtc, x, y, fb);
4951
4952         intel_update_watermarks(dev);
4953
4954         return ret;
4955 }
4956
4957 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4958                                  struct intel_crtc_config *pipe_config)
4959 {
4960         struct drm_device *dev = crtc->base.dev;
4961         struct drm_i915_private *dev_priv = dev->dev_private;
4962         uint32_t tmp;
4963
4964         tmp = I915_READ(PFIT_CONTROL);
4965
4966         if (INTEL_INFO(dev)->gen < 4) {
4967                 if (crtc->pipe != PIPE_B)
4968                         return;
4969
4970                 /* gen2/3 store dither state in pfit control, needs to match */
4971                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4972         } else {
4973                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4974                         return;
4975         }
4976
4977         if (!(tmp & PFIT_ENABLE))
4978                 return;
4979
4980         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4981         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4982         if (INTEL_INFO(dev)->gen < 5)
4983                 pipe_config->gmch_pfit.lvds_border_bits =
4984                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4985 }
4986
4987 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4988                                  struct intel_crtc_config *pipe_config)
4989 {
4990         struct drm_device *dev = crtc->base.dev;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         uint32_t tmp;
4993
4994         pipe_config->cpu_transcoder = crtc->pipe;
4995
4996         tmp = I915_READ(PIPECONF(crtc->pipe));
4997         if (!(tmp & PIPECONF_ENABLE))
4998                 return false;
4999
5000         intel_get_pipe_timings(crtc, pipe_config);
5001
5002         i9xx_get_pfit_config(crtc, pipe_config);
5003
5004         if (INTEL_INFO(dev)->gen >= 4) {
5005                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5006                 pipe_config->pixel_multiplier =
5007                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5008                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5009         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5010                 tmp = I915_READ(DPLL(crtc->pipe));
5011                 pipe_config->pixel_multiplier =
5012                         ((tmp & SDVO_MULTIPLIER_MASK)
5013                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5014         } else {
5015                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5016                  * port and will be fixed up in the encoder->get_config
5017                  * function. */
5018                 pipe_config->pixel_multiplier = 1;
5019         }
5020
5021         return true;
5022 }
5023
5024 static void ironlake_init_pch_refclk(struct drm_device *dev)
5025 {
5026         struct drm_i915_private *dev_priv = dev->dev_private;
5027         struct drm_mode_config *mode_config = &dev->mode_config;
5028         struct intel_encoder *encoder;
5029         u32 val, final;
5030         bool has_lvds = false;
5031         bool has_cpu_edp = false;
5032         bool has_panel = false;
5033         bool has_ck505 = false;
5034         bool can_ssc = false;
5035
5036         /* We need to take the global config into account */
5037         list_for_each_entry(encoder, &mode_config->encoder_list,
5038                             base.head) {
5039                 switch (encoder->type) {
5040                 case INTEL_OUTPUT_LVDS:
5041                         has_panel = true;
5042                         has_lvds = true;
5043                         break;
5044                 case INTEL_OUTPUT_EDP:
5045                         has_panel = true;
5046                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5047                                 has_cpu_edp = true;
5048                         break;
5049                 }
5050         }
5051
5052         if (HAS_PCH_IBX(dev)) {
5053                 has_ck505 = dev_priv->vbt.display_clock_mode;
5054                 can_ssc = has_ck505;
5055         } else {
5056                 has_ck505 = false;
5057                 can_ssc = true;
5058         }
5059
5060         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5061                       has_panel, has_lvds, has_ck505);
5062
5063         /* Ironlake: try to setup display ref clock before DPLL
5064          * enabling. This is only under driver's control after
5065          * PCH B stepping, previous chipset stepping should be
5066          * ignoring this setting.
5067          */
5068         val = I915_READ(PCH_DREF_CONTROL);
5069
5070         /* As we must carefully and slowly disable/enable each source in turn,
5071          * compute the final state we want first and check if we need to
5072          * make any changes at all.
5073          */
5074         final = val;
5075         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5076         if (has_ck505)
5077                 final |= DREF_NONSPREAD_CK505_ENABLE;
5078         else
5079                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5080
5081         final &= ~DREF_SSC_SOURCE_MASK;
5082         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5083         final &= ~DREF_SSC1_ENABLE;
5084
5085         if (has_panel) {
5086                 final |= DREF_SSC_SOURCE_ENABLE;
5087
5088                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5089                         final |= DREF_SSC1_ENABLE;
5090
5091                 if (has_cpu_edp) {
5092                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5093                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5094                         else
5095                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5096                 } else
5097                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5098         } else {
5099                 final |= DREF_SSC_SOURCE_DISABLE;
5100                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5101         }
5102
5103         if (final == val)
5104                 return;
5105
5106         /* Always enable nonspread source */
5107         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5108
5109         if (has_ck505)
5110                 val |= DREF_NONSPREAD_CK505_ENABLE;
5111         else
5112                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5113
5114         if (has_panel) {
5115                 val &= ~DREF_SSC_SOURCE_MASK;
5116                 val |= DREF_SSC_SOURCE_ENABLE;
5117
5118                 /* SSC must be turned on before enabling the CPU output  */
5119                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5120                         DRM_DEBUG_KMS("Using SSC on panel\n");
5121                         val |= DREF_SSC1_ENABLE;
5122                 } else
5123                         val &= ~DREF_SSC1_ENABLE;
5124
5125                 /* Get SSC going before enabling the outputs */
5126                 I915_WRITE(PCH_DREF_CONTROL, val);
5127                 POSTING_READ(PCH_DREF_CONTROL);
5128                 udelay(200);
5129
5130                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5131
5132                 /* Enable CPU source on CPU attached eDP */
5133                 if (has_cpu_edp) {
5134                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5135                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5136                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5137                         }
5138                         else
5139                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5140                 } else
5141                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5142
5143                 I915_WRITE(PCH_DREF_CONTROL, val);
5144                 POSTING_READ(PCH_DREF_CONTROL);
5145                 udelay(200);
5146         } else {
5147                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5148
5149                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5150
5151                 /* Turn off CPU output */
5152                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5153
5154                 I915_WRITE(PCH_DREF_CONTROL, val);
5155                 POSTING_READ(PCH_DREF_CONTROL);
5156                 udelay(200);
5157
5158                 /* Turn off the SSC source */
5159                 val &= ~DREF_SSC_SOURCE_MASK;
5160                 val |= DREF_SSC_SOURCE_DISABLE;
5161
5162                 /* Turn off SSC1 */
5163                 val &= ~DREF_SSC1_ENABLE;
5164
5165                 I915_WRITE(PCH_DREF_CONTROL, val);
5166                 POSTING_READ(PCH_DREF_CONTROL);
5167                 udelay(200);
5168         }
5169
5170         BUG_ON(val != final);
5171 }
5172
5173 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5174 static void lpt_init_pch_refclk(struct drm_device *dev)
5175 {
5176         struct drm_i915_private *dev_priv = dev->dev_private;
5177         struct drm_mode_config *mode_config = &dev->mode_config;
5178         struct intel_encoder *encoder;
5179         bool has_vga = false;
5180         bool is_sdv = false;
5181         u32 tmp;
5182
5183         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5184                 switch (encoder->type) {
5185                 case INTEL_OUTPUT_ANALOG:
5186                         has_vga = true;
5187                         break;
5188                 }
5189         }
5190
5191         if (!has_vga)
5192                 return;
5193
5194         mutex_lock(&dev_priv->dpio_lock);
5195
5196         /* XXX: Rip out SDV support once Haswell ships for real. */
5197         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5198                 is_sdv = true;
5199
5200         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5201         tmp &= ~SBI_SSCCTL_DISABLE;
5202         tmp |= SBI_SSCCTL_PATHALT;
5203         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5204
5205         udelay(24);
5206
5207         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5208         tmp &= ~SBI_SSCCTL_PATHALT;
5209         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5210
5211         if (!is_sdv) {
5212                 tmp = I915_READ(SOUTH_CHICKEN2);
5213                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5214                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5215
5216                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5217                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5218                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5219
5220                 tmp = I915_READ(SOUTH_CHICKEN2);
5221                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5222                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5223
5224                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5225                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5226                                        100))
5227                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5228         }
5229
5230         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5231         tmp &= ~(0xFF << 24);
5232         tmp |= (0x12 << 24);
5233         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5234
5235         if (is_sdv) {
5236                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5237                 tmp |= 0x7FFF;
5238                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5239         }
5240
5241         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5242         tmp |= (1 << 11);
5243         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5244
5245         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5246         tmp |= (1 << 11);
5247         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5248
5249         if (is_sdv) {
5250                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5251                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5252                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5253
5254                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5255                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5256                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5257
5258                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5259                 tmp |= (0x3F << 8);
5260                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5261
5262                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5263                 tmp |= (0x3F << 8);
5264                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5265         }
5266
5267         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5268         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5269         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5270
5271         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5272         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5273         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5274
5275         if (!is_sdv) {
5276                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5277                 tmp &= ~(7 << 13);
5278                 tmp |= (5 << 13);
5279                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5280
5281                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5282                 tmp &= ~(7 << 13);
5283                 tmp |= (5 << 13);
5284                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5285         }
5286
5287         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5288         tmp &= ~0xFF;
5289         tmp |= 0x1C;
5290         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5291
5292         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5293         tmp &= ~0xFF;
5294         tmp |= 0x1C;
5295         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5296
5297         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5298         tmp &= ~(0xFF << 16);
5299         tmp |= (0x1C << 16);
5300         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5301
5302         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5303         tmp &= ~(0xFF << 16);
5304         tmp |= (0x1C << 16);
5305         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5306
5307         if (!is_sdv) {
5308                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5309                 tmp |= (1 << 27);
5310                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5311
5312                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5313                 tmp |= (1 << 27);
5314                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5315
5316                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5317                 tmp &= ~(0xF << 28);
5318                 tmp |= (4 << 28);
5319                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5320
5321                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5322                 tmp &= ~(0xF << 28);
5323                 tmp |= (4 << 28);
5324                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5325         }
5326
5327         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5328         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5329         tmp |= SBI_DBUFF0_ENABLE;
5330         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5331
5332         mutex_unlock(&dev_priv->dpio_lock);
5333 }
5334
5335 /*
5336  * Initialize reference clocks when the driver loads
5337  */
5338 void intel_init_pch_refclk(struct drm_device *dev)
5339 {
5340         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5341                 ironlake_init_pch_refclk(dev);
5342         else if (HAS_PCH_LPT(dev))
5343                 lpt_init_pch_refclk(dev);
5344 }
5345
5346 static int ironlake_get_refclk(struct drm_crtc *crtc)
5347 {
5348         struct drm_device *dev = crtc->dev;
5349         struct drm_i915_private *dev_priv = dev->dev_private;
5350         struct intel_encoder *encoder;
5351         int num_connectors = 0;
5352         bool is_lvds = false;
5353
5354         for_each_encoder_on_crtc(dev, crtc, encoder) {
5355                 switch (encoder->type) {
5356                 case INTEL_OUTPUT_LVDS:
5357                         is_lvds = true;
5358                         break;
5359                 }
5360                 num_connectors++;
5361         }
5362
5363         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5364                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5365                               dev_priv->vbt.lvds_ssc_freq);
5366                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5367         }
5368
5369         return 120000;
5370 }
5371
5372 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5373 {
5374         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376         int pipe = intel_crtc->pipe;
5377         uint32_t val;
5378
5379         val = I915_READ(PIPECONF(pipe));
5380
5381         val &= ~PIPECONF_BPC_MASK;
5382         switch (intel_crtc->config.pipe_bpp) {
5383         case 18:
5384                 val |= PIPECONF_6BPC;
5385                 break;
5386         case 24:
5387                 val |= PIPECONF_8BPC;
5388                 break;
5389         case 30:
5390                 val |= PIPECONF_10BPC;
5391                 break;
5392         case 36:
5393                 val |= PIPECONF_12BPC;
5394                 break;
5395         default:
5396                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5397                 BUG();
5398         }
5399
5400         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5401         if (intel_crtc->config.dither)
5402                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5403
5404         val &= ~PIPECONF_INTERLACE_MASK;
5405         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5406                 val |= PIPECONF_INTERLACED_ILK;
5407         else
5408                 val |= PIPECONF_PROGRESSIVE;
5409
5410         if (intel_crtc->config.limited_color_range)
5411                 val |= PIPECONF_COLOR_RANGE_SELECT;
5412         else
5413                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5414
5415         I915_WRITE(PIPECONF(pipe), val);
5416         POSTING_READ(PIPECONF(pipe));
5417 }
5418
5419 /*
5420  * Set up the pipe CSC unit.
5421  *
5422  * Currently only full range RGB to limited range RGB conversion
5423  * is supported, but eventually this should handle various
5424  * RGB<->YCbCr scenarios as well.
5425  */
5426 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5427 {
5428         struct drm_device *dev = crtc->dev;
5429         struct drm_i915_private *dev_priv = dev->dev_private;
5430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5431         int pipe = intel_crtc->pipe;
5432         uint16_t coeff = 0x7800; /* 1.0 */
5433
5434         /*
5435          * TODO: Check what kind of values actually come out of the pipe
5436          * with these coeff/postoff values and adjust to get the best
5437          * accuracy. Perhaps we even need to take the bpc value into
5438          * consideration.
5439          */
5440
5441         if (intel_crtc->config.limited_color_range)
5442                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5443
5444         /*
5445          * GY/GU and RY/RU should be the other way around according
5446          * to BSpec, but reality doesn't agree. Just set them up in
5447          * a way that results in the correct picture.
5448          */
5449         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5450         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5451
5452         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5453         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5454
5455         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5456         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5457
5458         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5459         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5460         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5461
5462         if (INTEL_INFO(dev)->gen > 6) {
5463                 uint16_t postoff = 0;
5464
5465                 if (intel_crtc->config.limited_color_range)
5466                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5467
5468                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5469                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5470                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5471
5472                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5473         } else {
5474                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5475
5476                 if (intel_crtc->config.limited_color_range)
5477                         mode |= CSC_BLACK_SCREEN_OFFSET;
5478
5479                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5480         }
5481 }
5482
5483 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5484 {
5485         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5487         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5488         uint32_t val;
5489
5490         val = I915_READ(PIPECONF(cpu_transcoder));
5491
5492         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5493         if (intel_crtc->config.dither)
5494                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5495
5496         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5497         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5498                 val |= PIPECONF_INTERLACED_ILK;
5499         else
5500                 val |= PIPECONF_PROGRESSIVE;
5501
5502         I915_WRITE(PIPECONF(cpu_transcoder), val);
5503         POSTING_READ(PIPECONF(cpu_transcoder));
5504 }
5505
5506 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5507                                     intel_clock_t *clock,
5508                                     bool *has_reduced_clock,
5509                                     intel_clock_t *reduced_clock)
5510 {
5511         struct drm_device *dev = crtc->dev;
5512         struct drm_i915_private *dev_priv = dev->dev_private;
5513         struct intel_encoder *intel_encoder;
5514         int refclk;
5515         const intel_limit_t *limit;
5516         bool ret, is_lvds = false;
5517
5518         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5519                 switch (intel_encoder->type) {
5520                 case INTEL_OUTPUT_LVDS:
5521                         is_lvds = true;
5522                         break;
5523                 }
5524         }
5525
5526         refclk = ironlake_get_refclk(crtc);
5527
5528         /*
5529          * Returns a set of divisors for the desired target clock with the given
5530          * refclk, or FALSE.  The returned values represent the clock equation:
5531          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5532          */
5533         limit = intel_limit(crtc, refclk);
5534         ret = dev_priv->display.find_dpll(limit, crtc,
5535                                           to_intel_crtc(crtc)->config.port_clock,
5536                                           refclk, NULL, clock);
5537         if (!ret)
5538                 return false;
5539
5540         if (is_lvds && dev_priv->lvds_downclock_avail) {
5541                 /*
5542                  * Ensure we match the reduced clock's P to the target clock.
5543                  * If the clocks don't match, we can't switch the display clock
5544                  * by using the FP0/FP1. In such case we will disable the LVDS
5545                  * downclock feature.
5546                 */
5547                 *has_reduced_clock =
5548                         dev_priv->display.find_dpll(limit, crtc,
5549                                                     dev_priv->lvds_downclock,
5550                                                     refclk, clock,
5551                                                     reduced_clock);
5552         }
5553
5554         return true;
5555 }
5556
5557 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5558 {
5559         struct drm_i915_private *dev_priv = dev->dev_private;
5560         uint32_t temp;
5561
5562         temp = I915_READ(SOUTH_CHICKEN1);
5563         if (temp & FDI_BC_BIFURCATION_SELECT)
5564                 return;
5565
5566         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5567         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5568
5569         temp |= FDI_BC_BIFURCATION_SELECT;
5570         DRM_DEBUG_KMS("enabling fdi C rx\n");
5571         I915_WRITE(SOUTH_CHICKEN1, temp);
5572         POSTING_READ(SOUTH_CHICKEN1);
5573 }
5574
5575 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5576 {
5577         struct drm_device *dev = intel_crtc->base.dev;
5578         struct drm_i915_private *dev_priv = dev->dev_private;
5579
5580         switch (intel_crtc->pipe) {
5581         case PIPE_A:
5582                 break;
5583         case PIPE_B:
5584                 if (intel_crtc->config.fdi_lanes > 2)
5585                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5586                 else
5587                         cpt_enable_fdi_bc_bifurcation(dev);
5588
5589                 break;
5590         case PIPE_C:
5591                 cpt_enable_fdi_bc_bifurcation(dev);
5592
5593                 break;
5594         default:
5595                 BUG();
5596         }
5597 }
5598
5599 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5600 {
5601         /*
5602          * Account for spread spectrum to avoid
5603          * oversubscribing the link. Max center spread
5604          * is 2.5%; use 5% for safety's sake.
5605          */
5606         u32 bps = target_clock * bpp * 21 / 20;
5607         return bps / (link_bw * 8) + 1;
5608 }
5609
5610 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5611 {
5612         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5613 }
5614
5615 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5616                                       u32 *fp,
5617                                       intel_clock_t *reduced_clock, u32 *fp2)
5618 {
5619         struct drm_crtc *crtc = &intel_crtc->base;
5620         struct drm_device *dev = crtc->dev;
5621         struct drm_i915_private *dev_priv = dev->dev_private;
5622         struct intel_encoder *intel_encoder;
5623         uint32_t dpll;
5624         int factor, num_connectors = 0;
5625         bool is_lvds = false, is_sdvo = false;
5626
5627         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5628                 switch (intel_encoder->type) {
5629                 case INTEL_OUTPUT_LVDS:
5630                         is_lvds = true;
5631                         break;
5632                 case INTEL_OUTPUT_SDVO:
5633                 case INTEL_OUTPUT_HDMI:
5634                         is_sdvo = true;
5635                         break;
5636                 }
5637
5638                 num_connectors++;
5639         }
5640
5641         /* Enable autotuning of the PLL clock (if permissible) */
5642         factor = 21;
5643         if (is_lvds) {
5644                 if ((intel_panel_use_ssc(dev_priv) &&
5645                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5646                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5647                         factor = 25;
5648         } else if (intel_crtc->config.sdvo_tv_clock)
5649                 factor = 20;
5650
5651         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5652                 *fp |= FP_CB_TUNE;
5653
5654         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5655                 *fp2 |= FP_CB_TUNE;
5656
5657         dpll = 0;
5658
5659         if (is_lvds)
5660                 dpll |= DPLLB_MODE_LVDS;
5661         else
5662                 dpll |= DPLLB_MODE_DAC_SERIAL;
5663
5664         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5665                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5666
5667         if (is_sdvo)
5668                 dpll |= DPLL_DVO_HIGH_SPEED;
5669         if (intel_crtc->config.has_dp_encoder)
5670                 dpll |= DPLL_DVO_HIGH_SPEED;
5671
5672         /* compute bitmask from p1 value */
5673         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5674         /* also FPA1 */
5675         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5676
5677         switch (intel_crtc->config.dpll.p2) {
5678         case 5:
5679                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5680                 break;
5681         case 7:
5682                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5683                 break;
5684         case 10:
5685                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5686                 break;
5687         case 14:
5688                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5689                 break;
5690         }
5691
5692         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5693                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5694         else
5695                 dpll |= PLL_REF_INPUT_DREFCLK;
5696
5697         return dpll;
5698 }
5699
5700 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5701                                   int x, int y,
5702                                   struct drm_framebuffer *fb)
5703 {
5704         struct drm_device *dev = crtc->dev;
5705         struct drm_i915_private *dev_priv = dev->dev_private;
5706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5707         int pipe = intel_crtc->pipe;
5708         int plane = intel_crtc->plane;
5709         int num_connectors = 0;
5710         intel_clock_t clock, reduced_clock;
5711         u32 dpll = 0, fp = 0, fp2 = 0;
5712         bool ok, has_reduced_clock = false;
5713         bool is_lvds = false;
5714         struct intel_encoder *encoder;
5715         int ret;
5716
5717         for_each_encoder_on_crtc(dev, crtc, encoder) {
5718                 switch (encoder->type) {
5719                 case INTEL_OUTPUT_LVDS:
5720                         is_lvds = true;
5721                         break;
5722                 }
5723
5724                 num_connectors++;
5725         }
5726
5727         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5728              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5729
5730         ok = ironlake_compute_clocks(crtc, &clock,
5731                                      &has_reduced_clock, &reduced_clock);
5732         if (!ok && !intel_crtc->config.clock_set) {
5733                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5734                 return -EINVAL;
5735         }
5736         /* Compat-code for transition, will disappear. */
5737         if (!intel_crtc->config.clock_set) {
5738                 intel_crtc->config.dpll.n = clock.n;
5739                 intel_crtc->config.dpll.m1 = clock.m1;
5740                 intel_crtc->config.dpll.m2 = clock.m2;
5741                 intel_crtc->config.dpll.p1 = clock.p1;
5742                 intel_crtc->config.dpll.p2 = clock.p2;
5743         }
5744
5745         /* Ensure that the cursor is valid for the new mode before changing... */
5746         intel_crtc_update_cursor(crtc, true);
5747
5748         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5749         if (intel_crtc->config.has_pch_encoder) {
5750                 struct intel_pch_pll *pll;
5751
5752                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5753                 if (has_reduced_clock)
5754                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5755
5756                 dpll = ironlake_compute_dpll(intel_crtc,
5757                                              &fp, &reduced_clock,
5758                                              has_reduced_clock ? &fp2 : NULL);
5759
5760                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5761                 if (pll == NULL) {
5762                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5763                                          pipe_name(pipe));
5764                         return -EINVAL;
5765                 }
5766         } else
5767                 intel_put_pch_pll(intel_crtc);
5768
5769         if (intel_crtc->config.has_dp_encoder)
5770                 intel_dp_set_m_n(intel_crtc);
5771
5772         for_each_encoder_on_crtc(dev, crtc, encoder)
5773                 if (encoder->pre_pll_enable)
5774                         encoder->pre_pll_enable(encoder);
5775
5776         if (intel_crtc->pch_pll) {
5777                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5778
5779                 /* Wait for the clocks to stabilize. */
5780                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5781                 udelay(150);
5782
5783                 /* The pixel multiplier can only be updated once the
5784                  * DPLL is enabled and the clocks are stable.
5785                  *
5786                  * So write it again.
5787                  */
5788                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5789         }
5790
5791         intel_crtc->lowfreq_avail = false;
5792         if (intel_crtc->pch_pll) {
5793                 if (is_lvds && has_reduced_clock && i915_powersave) {
5794                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5795                         intel_crtc->lowfreq_avail = true;
5796                 } else {
5797                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5798                 }
5799         }
5800
5801         intel_set_pipe_timings(intel_crtc);
5802
5803         if (intel_crtc->config.has_pch_encoder) {
5804                 intel_cpu_transcoder_set_m_n(intel_crtc,
5805                                              &intel_crtc->config.fdi_m_n);
5806         }
5807
5808         if (IS_IVYBRIDGE(dev))
5809                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5810
5811         ironlake_set_pipeconf(crtc);
5812
5813         /* Set up the display plane register */
5814         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5815         POSTING_READ(DSPCNTR(plane));
5816
5817         ret = intel_pipe_set_base(crtc, x, y, fb);
5818
5819         intel_update_watermarks(dev);
5820
5821         return ret;
5822 }
5823
5824 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5825                                         struct intel_crtc_config *pipe_config)
5826 {
5827         struct drm_device *dev = crtc->base.dev;
5828         struct drm_i915_private *dev_priv = dev->dev_private;
5829         enum transcoder transcoder = pipe_config->cpu_transcoder;
5830
5831         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5832         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5833         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5834                                         & ~TU_SIZE_MASK;
5835         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5836         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5837                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5838 }
5839
5840 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5841                                      struct intel_crtc_config *pipe_config)
5842 {
5843         struct drm_device *dev = crtc->base.dev;
5844         struct drm_i915_private *dev_priv = dev->dev_private;
5845         uint32_t tmp;
5846
5847         tmp = I915_READ(PF_CTL(crtc->pipe));
5848
5849         if (tmp & PF_ENABLE) {
5850                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5851                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5852
5853                 /* We currently do not free assignements of panel fitters on
5854                  * ivb/hsw (since we don't use the higher upscaling modes which
5855                  * differentiates them) so just WARN about this case for now. */
5856                 if (IS_GEN7(dev)) {
5857                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5858                                 PF_PIPE_SEL_IVB(crtc->pipe));
5859                 }
5860         }
5861 }
5862
5863 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5864                                      struct intel_crtc_config *pipe_config)
5865 {
5866         struct drm_device *dev = crtc->base.dev;
5867         struct drm_i915_private *dev_priv = dev->dev_private;
5868         uint32_t tmp;
5869
5870         pipe_config->cpu_transcoder = crtc->pipe;
5871
5872         tmp = I915_READ(PIPECONF(crtc->pipe));
5873         if (!(tmp & PIPECONF_ENABLE))
5874                 return false;
5875
5876         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5877                 pipe_config->has_pch_encoder = true;
5878
5879                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5880                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5881                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5882
5883                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5884
5885                 /* XXX: Can't properly read out the pch dpll pixel multiplier
5886                  * since we don't have state tracking for pch clocks yet. */
5887                 pipe_config->pixel_multiplier = 1;
5888         } else {
5889                 pipe_config->pixel_multiplier = 1;
5890         }
5891
5892         intel_get_pipe_timings(crtc, pipe_config);
5893
5894         ironlake_get_pfit_config(crtc, pipe_config);
5895
5896         return true;
5897 }
5898
5899 static void haswell_modeset_global_resources(struct drm_device *dev)
5900 {
5901         bool enable = false;
5902         struct intel_crtc *crtc;
5903
5904         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5905                 if (!crtc->base.enabled)
5906                         continue;
5907
5908                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5909                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5910                         enable = true;
5911         }
5912
5913         intel_set_power_well(dev, enable);
5914 }
5915
5916 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5917                                  int x, int y,
5918                                  struct drm_framebuffer *fb)
5919 {
5920         struct drm_device *dev = crtc->dev;
5921         struct drm_i915_private *dev_priv = dev->dev_private;
5922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5923         int plane = intel_crtc->plane;
5924         int ret;
5925
5926         if (!intel_ddi_pll_mode_set(crtc))
5927                 return -EINVAL;
5928
5929         /* Ensure that the cursor is valid for the new mode before changing... */
5930         intel_crtc_update_cursor(crtc, true);
5931
5932         if (intel_crtc->config.has_dp_encoder)
5933                 intel_dp_set_m_n(intel_crtc);
5934
5935         intel_crtc->lowfreq_avail = false;
5936
5937         intel_set_pipe_timings(intel_crtc);
5938
5939         if (intel_crtc->config.has_pch_encoder) {
5940                 intel_cpu_transcoder_set_m_n(intel_crtc,
5941                                              &intel_crtc->config.fdi_m_n);
5942         }
5943
5944         haswell_set_pipeconf(crtc);
5945
5946         intel_set_pipe_csc(crtc);
5947
5948         /* Set up the display plane register */
5949         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5950         POSTING_READ(DSPCNTR(plane));
5951
5952         ret = intel_pipe_set_base(crtc, x, y, fb);
5953
5954         intel_update_watermarks(dev);
5955
5956         return ret;
5957 }
5958
5959 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5960                                     struct intel_crtc_config *pipe_config)
5961 {
5962         struct drm_device *dev = crtc->base.dev;
5963         struct drm_i915_private *dev_priv = dev->dev_private;
5964         enum intel_display_power_domain pfit_domain;
5965         uint32_t tmp;
5966
5967         pipe_config->cpu_transcoder = crtc->pipe;
5968         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5969         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5970                 enum pipe trans_edp_pipe;
5971                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5972                 default:
5973                         WARN(1, "unknown pipe linked to edp transcoder\n");
5974                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5975                 case TRANS_DDI_EDP_INPUT_A_ON:
5976                         trans_edp_pipe = PIPE_A;
5977                         break;
5978                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5979                         trans_edp_pipe = PIPE_B;
5980                         break;
5981                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5982                         trans_edp_pipe = PIPE_C;
5983                         break;
5984                 }
5985
5986                 if (trans_edp_pipe == crtc->pipe)
5987                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5988         }
5989
5990         if (!intel_display_power_enabled(dev,
5991                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5992                 return false;
5993
5994         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5995         if (!(tmp & PIPECONF_ENABLE))
5996                 return false;
5997
5998         /*
5999          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6000          * DDI E. So just check whether this pipe is wired to DDI E and whether
6001          * the PCH transcoder is on.
6002          */
6003         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6004         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6005             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6006                 pipe_config->has_pch_encoder = true;
6007
6008                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6009                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6010                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6011
6012                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6013         }
6014
6015         intel_get_pipe_timings(crtc, pipe_config);
6016
6017         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6018         if (intel_display_power_enabled(dev, pfit_domain))
6019                 ironlake_get_pfit_config(crtc, pipe_config);
6020
6021         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6022                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6023
6024         pipe_config->pixel_multiplier = 1;
6025
6026         return true;
6027 }
6028
6029 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6030                                int x, int y,
6031                                struct drm_framebuffer *fb)
6032 {
6033         struct drm_device *dev = crtc->dev;
6034         struct drm_i915_private *dev_priv = dev->dev_private;
6035         struct drm_encoder_helper_funcs *encoder_funcs;
6036         struct intel_encoder *encoder;
6037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6038         struct drm_display_mode *adjusted_mode =
6039                 &intel_crtc->config.adjusted_mode;
6040         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6041         int pipe = intel_crtc->pipe;
6042         int ret;
6043
6044         drm_vblank_pre_modeset(dev, pipe);
6045
6046         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6047
6048         drm_vblank_post_modeset(dev, pipe);
6049
6050         if (ret != 0)
6051                 return ret;
6052
6053         for_each_encoder_on_crtc(dev, crtc, encoder) {
6054                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6055                         encoder->base.base.id,
6056                         drm_get_encoder_name(&encoder->base),
6057                         mode->base.id, mode->name);
6058                 if (encoder->mode_set) {
6059                         encoder->mode_set(encoder);
6060                 } else {
6061                         encoder_funcs = encoder->base.helper_private;
6062                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6063                 }
6064         }
6065
6066         return 0;
6067 }
6068
6069 static bool intel_eld_uptodate(struct drm_connector *connector,
6070                                int reg_eldv, uint32_t bits_eldv,
6071                                int reg_elda, uint32_t bits_elda,
6072                                int reg_edid)
6073 {
6074         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6075         uint8_t *eld = connector->eld;
6076         uint32_t i;
6077
6078         i = I915_READ(reg_eldv);
6079         i &= bits_eldv;
6080
6081         if (!eld[0])
6082                 return !i;
6083
6084         if (!i)
6085                 return false;
6086
6087         i = I915_READ(reg_elda);
6088         i &= ~bits_elda;
6089         I915_WRITE(reg_elda, i);
6090
6091         for (i = 0; i < eld[2]; i++)
6092                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6093                         return false;
6094
6095         return true;
6096 }
6097
6098 static void g4x_write_eld(struct drm_connector *connector,
6099                           struct drm_crtc *crtc)
6100 {
6101         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6102         uint8_t *eld = connector->eld;
6103         uint32_t eldv;
6104         uint32_t len;
6105         uint32_t i;
6106
6107         i = I915_READ(G4X_AUD_VID_DID);
6108
6109         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6110                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6111         else
6112                 eldv = G4X_ELDV_DEVCTG;
6113
6114         if (intel_eld_uptodate(connector,
6115                                G4X_AUD_CNTL_ST, eldv,
6116                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6117                                G4X_HDMIW_HDMIEDID))
6118                 return;
6119
6120         i = I915_READ(G4X_AUD_CNTL_ST);
6121         i &= ~(eldv | G4X_ELD_ADDR);
6122         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6123         I915_WRITE(G4X_AUD_CNTL_ST, i);
6124
6125         if (!eld[0])
6126                 return;
6127
6128         len = min_t(uint8_t, eld[2], len);
6129         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6130         for (i = 0; i < len; i++)
6131                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6132
6133         i = I915_READ(G4X_AUD_CNTL_ST);
6134         i |= eldv;
6135         I915_WRITE(G4X_AUD_CNTL_ST, i);
6136 }
6137
6138 static void haswell_write_eld(struct drm_connector *connector,
6139                                      struct drm_crtc *crtc)
6140 {
6141         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6142         uint8_t *eld = connector->eld;
6143         struct drm_device *dev = crtc->dev;
6144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6145         uint32_t eldv;
6146         uint32_t i;
6147         int len;
6148         int pipe = to_intel_crtc(crtc)->pipe;
6149         int tmp;
6150
6151         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6152         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6153         int aud_config = HSW_AUD_CFG(pipe);
6154         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6155
6156
6157         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6158
6159         /* Audio output enable */
6160         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6161         tmp = I915_READ(aud_cntrl_st2);
6162         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6163         I915_WRITE(aud_cntrl_st2, tmp);
6164
6165         /* Wait for 1 vertical blank */
6166         intel_wait_for_vblank(dev, pipe);
6167
6168         /* Set ELD valid state */
6169         tmp = I915_READ(aud_cntrl_st2);
6170         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6171         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6172         I915_WRITE(aud_cntrl_st2, tmp);
6173         tmp = I915_READ(aud_cntrl_st2);
6174         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6175
6176         /* Enable HDMI mode */
6177         tmp = I915_READ(aud_config);
6178         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6179         /* clear N_programing_enable and N_value_index */
6180         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6181         I915_WRITE(aud_config, tmp);
6182
6183         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6184
6185         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6186         intel_crtc->eld_vld = true;
6187
6188         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6189                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6190                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6191                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6192         } else
6193                 I915_WRITE(aud_config, 0);
6194
6195         if (intel_eld_uptodate(connector,
6196                                aud_cntrl_st2, eldv,
6197                                aud_cntl_st, IBX_ELD_ADDRESS,
6198                                hdmiw_hdmiedid))
6199                 return;
6200
6201         i = I915_READ(aud_cntrl_st2);
6202         i &= ~eldv;
6203         I915_WRITE(aud_cntrl_st2, i);
6204
6205         if (!eld[0])
6206                 return;
6207
6208         i = I915_READ(aud_cntl_st);
6209         i &= ~IBX_ELD_ADDRESS;
6210         I915_WRITE(aud_cntl_st, i);
6211         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6212         DRM_DEBUG_DRIVER("port num:%d\n", i);
6213
6214         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6215         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6216         for (i = 0; i < len; i++)
6217                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6218
6219         i = I915_READ(aud_cntrl_st2);
6220         i |= eldv;
6221         I915_WRITE(aud_cntrl_st2, i);
6222
6223 }
6224
6225 static void ironlake_write_eld(struct drm_connector *connector,
6226                                      struct drm_crtc *crtc)
6227 {
6228         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6229         uint8_t *eld = connector->eld;
6230         uint32_t eldv;
6231         uint32_t i;
6232         int len;
6233         int hdmiw_hdmiedid;
6234         int aud_config;
6235         int aud_cntl_st;
6236         int aud_cntrl_st2;
6237         int pipe = to_intel_crtc(crtc)->pipe;
6238
6239         if (HAS_PCH_IBX(connector->dev)) {
6240                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6241                 aud_config = IBX_AUD_CFG(pipe);
6242                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6243                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6244         } else {
6245                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6246                 aud_config = CPT_AUD_CFG(pipe);
6247                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6248                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6249         }
6250
6251         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6252
6253         i = I915_READ(aud_cntl_st);
6254         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6255         if (!i) {
6256                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6257                 /* operate blindly on all ports */
6258                 eldv = IBX_ELD_VALIDB;
6259                 eldv |= IBX_ELD_VALIDB << 4;
6260                 eldv |= IBX_ELD_VALIDB << 8;
6261         } else {
6262                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6263                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6264         }
6265
6266         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6267                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6268                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6269                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6270         } else
6271                 I915_WRITE(aud_config, 0);
6272
6273         if (intel_eld_uptodate(connector,
6274                                aud_cntrl_st2, eldv,
6275                                aud_cntl_st, IBX_ELD_ADDRESS,
6276                                hdmiw_hdmiedid))
6277                 return;
6278
6279         i = I915_READ(aud_cntrl_st2);
6280         i &= ~eldv;
6281         I915_WRITE(aud_cntrl_st2, i);
6282
6283         if (!eld[0])
6284                 return;
6285
6286         i = I915_READ(aud_cntl_st);
6287         i &= ~IBX_ELD_ADDRESS;
6288         I915_WRITE(aud_cntl_st, i);
6289
6290         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6291         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6292         for (i = 0; i < len; i++)
6293                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6294
6295         i = I915_READ(aud_cntrl_st2);
6296         i |= eldv;
6297         I915_WRITE(aud_cntrl_st2, i);
6298 }
6299
6300 void intel_write_eld(struct drm_encoder *encoder,
6301                      struct drm_display_mode *mode)
6302 {
6303         struct drm_crtc *crtc = encoder->crtc;
6304         struct drm_connector *connector;
6305         struct drm_device *dev = encoder->dev;
6306         struct drm_i915_private *dev_priv = dev->dev_private;
6307
6308         connector = drm_select_eld(encoder, mode);
6309         if (!connector)
6310                 return;
6311
6312         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6313                          connector->base.id,
6314                          drm_get_connector_name(connector),
6315                          connector->encoder->base.id,
6316                          drm_get_encoder_name(connector->encoder));
6317
6318         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6319
6320         if (dev_priv->display.write_eld)
6321                 dev_priv->display.write_eld(connector, crtc);
6322 }
6323
6324 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6325 void intel_crtc_load_lut(struct drm_crtc *crtc)
6326 {
6327         struct drm_device *dev = crtc->dev;
6328         struct drm_i915_private *dev_priv = dev->dev_private;
6329         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6330         enum pipe pipe = intel_crtc->pipe;
6331         int palreg = PALETTE(pipe);
6332         int i;
6333         bool reenable_ips = false;
6334
6335         /* The clocks have to be on to load the palette. */
6336         if (!crtc->enabled || !intel_crtc->active)
6337                 return;
6338
6339         if (!HAS_PCH_SPLIT(dev_priv->dev))
6340                 assert_pll_enabled(dev_priv, pipe);
6341
6342         /* use legacy palette for Ironlake */
6343         if (HAS_PCH_SPLIT(dev))
6344                 palreg = LGC_PALETTE(pipe);
6345
6346         /* Workaround : Do not read or write the pipe palette/gamma data while
6347          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6348          */
6349         if (intel_crtc->config.ips_enabled &&
6350             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6351              GAMMA_MODE_MODE_SPLIT)) {
6352                 hsw_disable_ips(intel_crtc);
6353                 reenable_ips = true;
6354         }
6355
6356         for (i = 0; i < 256; i++) {
6357                 I915_WRITE(palreg + 4 * i,
6358                            (intel_crtc->lut_r[i] << 16) |
6359                            (intel_crtc->lut_g[i] << 8) |
6360                            intel_crtc->lut_b[i]);
6361         }
6362
6363         if (reenable_ips)
6364                 hsw_enable_ips(intel_crtc);
6365 }
6366
6367 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6368 {
6369         struct drm_device *dev = crtc->dev;
6370         struct drm_i915_private *dev_priv = dev->dev_private;
6371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6372         bool visible = base != 0;
6373         u32 cntl;
6374
6375         if (intel_crtc->cursor_visible == visible)
6376                 return;
6377
6378         cntl = I915_READ(_CURACNTR);
6379         if (visible) {
6380                 /* On these chipsets we can only modify the base whilst
6381                  * the cursor is disabled.
6382                  */
6383                 I915_WRITE(_CURABASE, base);
6384
6385                 cntl &= ~(CURSOR_FORMAT_MASK);
6386                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6387                 cntl |= CURSOR_ENABLE |
6388                         CURSOR_GAMMA_ENABLE |
6389                         CURSOR_FORMAT_ARGB;
6390         } else
6391                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6392         I915_WRITE(_CURACNTR, cntl);
6393
6394         intel_crtc->cursor_visible = visible;
6395 }
6396
6397 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6398 {
6399         struct drm_device *dev = crtc->dev;
6400         struct drm_i915_private *dev_priv = dev->dev_private;
6401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6402         int pipe = intel_crtc->pipe;
6403         bool visible = base != 0;
6404
6405         if (intel_crtc->cursor_visible != visible) {
6406                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6407                 if (base) {
6408                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6409                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6410                         cntl |= pipe << 28; /* Connect to correct pipe */
6411                 } else {
6412                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6413                         cntl |= CURSOR_MODE_DISABLE;
6414                 }
6415                 I915_WRITE(CURCNTR(pipe), cntl);
6416
6417                 intel_crtc->cursor_visible = visible;
6418         }
6419         /* and commit changes on next vblank */
6420         I915_WRITE(CURBASE(pipe), base);
6421 }
6422
6423 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6424 {
6425         struct drm_device *dev = crtc->dev;
6426         struct drm_i915_private *dev_priv = dev->dev_private;
6427         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6428         int pipe = intel_crtc->pipe;
6429         bool visible = base != 0;
6430
6431         if (intel_crtc->cursor_visible != visible) {
6432                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6433                 if (base) {
6434                         cntl &= ~CURSOR_MODE;
6435                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6436                 } else {
6437                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6438                         cntl |= CURSOR_MODE_DISABLE;
6439                 }
6440                 if (IS_HASWELL(dev))
6441                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6442                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6443
6444                 intel_crtc->cursor_visible = visible;
6445         }
6446         /* and commit changes on next vblank */
6447         I915_WRITE(CURBASE_IVB(pipe), base);
6448 }
6449
6450 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6451 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6452                                      bool on)
6453 {
6454         struct drm_device *dev = crtc->dev;
6455         struct drm_i915_private *dev_priv = dev->dev_private;
6456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6457         int pipe = intel_crtc->pipe;
6458         int x = intel_crtc->cursor_x;
6459         int y = intel_crtc->cursor_y;
6460         u32 base, pos;
6461         bool visible;
6462
6463         pos = 0;
6464
6465         if (on && crtc->enabled && crtc->fb) {
6466                 base = intel_crtc->cursor_addr;
6467                 if (x > (int) crtc->fb->width)
6468                         base = 0;
6469
6470                 if (y > (int) crtc->fb->height)
6471                         base = 0;
6472         } else
6473                 base = 0;
6474
6475         if (x < 0) {
6476                 if (x + intel_crtc->cursor_width < 0)
6477                         base = 0;
6478
6479                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6480                 x = -x;
6481         }
6482         pos |= x << CURSOR_X_SHIFT;
6483
6484         if (y < 0) {
6485                 if (y + intel_crtc->cursor_height < 0)
6486                         base = 0;
6487
6488                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6489                 y = -y;
6490         }
6491         pos |= y << CURSOR_Y_SHIFT;
6492
6493         visible = base != 0;
6494         if (!visible && !intel_crtc->cursor_visible)
6495                 return;
6496
6497         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6498                 I915_WRITE(CURPOS_IVB(pipe), pos);
6499                 ivb_update_cursor(crtc, base);
6500         } else {
6501                 I915_WRITE(CURPOS(pipe), pos);
6502                 if (IS_845G(dev) || IS_I865G(dev))
6503                         i845_update_cursor(crtc, base);
6504                 else
6505                         i9xx_update_cursor(crtc, base);
6506         }
6507 }
6508
6509 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6510                                  struct drm_file *file,
6511                                  uint32_t handle,
6512                                  uint32_t width, uint32_t height)
6513 {
6514         struct drm_device *dev = crtc->dev;
6515         struct drm_i915_private *dev_priv = dev->dev_private;
6516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6517         struct drm_i915_gem_object *obj;
6518         uint32_t addr;
6519         int ret;
6520
6521         /* if we want to turn off the cursor ignore width and height */
6522         if (!handle) {
6523                 DRM_DEBUG_KMS("cursor off\n");
6524                 addr = 0;
6525                 obj = NULL;
6526                 mutex_lock(&dev->struct_mutex);
6527                 goto finish;
6528         }
6529
6530         /* Currently we only support 64x64 cursors */
6531         if (width != 64 || height != 64) {
6532                 DRM_ERROR("we currently only support 64x64 cursors\n");
6533                 return -EINVAL;
6534         }
6535
6536         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6537         if (&obj->base == NULL)
6538                 return -ENOENT;
6539
6540         if (obj->base.size < width * height * 4) {
6541                 DRM_ERROR("buffer is to small\n");
6542                 ret = -ENOMEM;
6543                 goto fail;
6544         }
6545
6546         /* we only need to pin inside GTT if cursor is non-phy */
6547         mutex_lock(&dev->struct_mutex);
6548         if (!dev_priv->info->cursor_needs_physical) {
6549                 unsigned alignment;
6550
6551                 if (obj->tiling_mode) {
6552                         DRM_ERROR("cursor cannot be tiled\n");
6553                         ret = -EINVAL;
6554                         goto fail_locked;
6555                 }
6556
6557                 /* Note that the w/a also requires 2 PTE of padding following
6558                  * the bo. We currently fill all unused PTE with the shadow
6559                  * page and so we should always have valid PTE following the
6560                  * cursor preventing the VT-d warning.
6561                  */
6562                 alignment = 0;
6563                 if (need_vtd_wa(dev))
6564                         alignment = 64*1024;
6565
6566                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6567                 if (ret) {
6568                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6569                         goto fail_locked;
6570                 }
6571
6572                 ret = i915_gem_object_put_fence(obj);
6573                 if (ret) {
6574                         DRM_ERROR("failed to release fence for cursor");
6575                         goto fail_unpin;
6576                 }
6577
6578                 addr = obj->gtt_offset;
6579         } else {
6580                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6581                 ret = i915_gem_attach_phys_object(dev, obj,
6582                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6583                                                   align);
6584                 if (ret) {
6585                         DRM_ERROR("failed to attach phys object\n");
6586                         goto fail_locked;
6587                 }
6588                 addr = obj->phys_obj->handle->busaddr;
6589         }
6590
6591         if (IS_GEN2(dev))
6592                 I915_WRITE(CURSIZE, (height << 12) | width);
6593
6594  finish:
6595         if (intel_crtc->cursor_bo) {
6596                 if (dev_priv->info->cursor_needs_physical) {
6597                         if (intel_crtc->cursor_bo != obj)
6598                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6599                 } else
6600                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6601                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6602         }
6603
6604         mutex_unlock(&dev->struct_mutex);
6605
6606         intel_crtc->cursor_addr = addr;
6607         intel_crtc->cursor_bo = obj;
6608         intel_crtc->cursor_width = width;
6609         intel_crtc->cursor_height = height;
6610
6611         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6612
6613         return 0;
6614 fail_unpin:
6615         i915_gem_object_unpin(obj);
6616 fail_locked:
6617         mutex_unlock(&dev->struct_mutex);
6618 fail:
6619         drm_gem_object_unreference_unlocked(&obj->base);
6620         return ret;
6621 }
6622
6623 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6624 {
6625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6626
6627         intel_crtc->cursor_x = x;
6628         intel_crtc->cursor_y = y;
6629
6630         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6631
6632         return 0;
6633 }
6634
6635 /** Sets the color ramps on behalf of RandR */
6636 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6637                                  u16 blue, int regno)
6638 {
6639         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6640
6641         intel_crtc->lut_r[regno] = red >> 8;
6642         intel_crtc->lut_g[regno] = green >> 8;
6643         intel_crtc->lut_b[regno] = blue >> 8;
6644 }
6645
6646 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6647                              u16 *blue, int regno)
6648 {
6649         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6650
6651         *red = intel_crtc->lut_r[regno] << 8;
6652         *green = intel_crtc->lut_g[regno] << 8;
6653         *blue = intel_crtc->lut_b[regno] << 8;
6654 }
6655
6656 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6657                                  u16 *blue, uint32_t start, uint32_t size)
6658 {
6659         int end = (start + size > 256) ? 256 : start + size, i;
6660         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6661
6662         for (i = start; i < end; i++) {
6663                 intel_crtc->lut_r[i] = red[i] >> 8;
6664                 intel_crtc->lut_g[i] = green[i] >> 8;
6665                 intel_crtc->lut_b[i] = blue[i] >> 8;
6666         }
6667
6668         intel_crtc_load_lut(crtc);
6669 }
6670
6671 /* VESA 640x480x72Hz mode to set on the pipe */
6672 static struct drm_display_mode load_detect_mode = {
6673         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6674                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6675 };
6676
6677 static struct drm_framebuffer *
6678 intel_framebuffer_create(struct drm_device *dev,
6679                          struct drm_mode_fb_cmd2 *mode_cmd,
6680                          struct drm_i915_gem_object *obj)
6681 {
6682         struct intel_framebuffer *intel_fb;
6683         int ret;
6684
6685         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6686         if (!intel_fb) {
6687                 drm_gem_object_unreference_unlocked(&obj->base);
6688                 return ERR_PTR(-ENOMEM);
6689         }
6690
6691         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6692         if (ret) {
6693                 drm_gem_object_unreference_unlocked(&obj->base);
6694                 kfree(intel_fb);
6695                 return ERR_PTR(ret);
6696         }
6697
6698         return &intel_fb->base;
6699 }
6700
6701 static u32
6702 intel_framebuffer_pitch_for_width(int width, int bpp)
6703 {
6704         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6705         return ALIGN(pitch, 64);
6706 }
6707
6708 static u32
6709 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6710 {
6711         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6712         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6713 }
6714
6715 static struct drm_framebuffer *
6716 intel_framebuffer_create_for_mode(struct drm_device *dev,
6717                                   struct drm_display_mode *mode,
6718                                   int depth, int bpp)
6719 {
6720         struct drm_i915_gem_object *obj;
6721         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6722
6723         obj = i915_gem_alloc_object(dev,
6724                                     intel_framebuffer_size_for_mode(mode, bpp));
6725         if (obj == NULL)
6726                 return ERR_PTR(-ENOMEM);
6727
6728         mode_cmd.width = mode->hdisplay;
6729         mode_cmd.height = mode->vdisplay;
6730         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6731                                                                 bpp);
6732         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6733
6734         return intel_framebuffer_create(dev, &mode_cmd, obj);
6735 }
6736
6737 static struct drm_framebuffer *
6738 mode_fits_in_fbdev(struct drm_device *dev,
6739                    struct drm_display_mode *mode)
6740 {
6741         struct drm_i915_private *dev_priv = dev->dev_private;
6742         struct drm_i915_gem_object *obj;
6743         struct drm_framebuffer *fb;
6744
6745         if (dev_priv->fbdev == NULL)
6746                 return NULL;
6747
6748         obj = dev_priv->fbdev->ifb.obj;
6749         if (obj == NULL)
6750                 return NULL;
6751
6752         fb = &dev_priv->fbdev->ifb.base;
6753         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6754                                                                fb->bits_per_pixel))
6755                 return NULL;
6756
6757         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6758                 return NULL;
6759
6760         return fb;
6761 }
6762
6763 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6764                                 struct drm_display_mode *mode,
6765                                 struct intel_load_detect_pipe *old)
6766 {
6767         struct intel_crtc *intel_crtc;
6768         struct intel_encoder *intel_encoder =
6769                 intel_attached_encoder(connector);
6770         struct drm_crtc *possible_crtc;
6771         struct drm_encoder *encoder = &intel_encoder->base;
6772         struct drm_crtc *crtc = NULL;
6773         struct drm_device *dev = encoder->dev;
6774         struct drm_framebuffer *fb;
6775         int i = -1;
6776
6777         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6778                       connector->base.id, drm_get_connector_name(connector),
6779                       encoder->base.id, drm_get_encoder_name(encoder));
6780
6781         /*
6782          * Algorithm gets a little messy:
6783          *
6784          *   - if the connector already has an assigned crtc, use it (but make
6785          *     sure it's on first)
6786          *
6787          *   - try to find the first unused crtc that can drive this connector,
6788          *     and use that if we find one
6789          */
6790
6791         /* See if we already have a CRTC for this connector */
6792         if (encoder->crtc) {
6793                 crtc = encoder->crtc;
6794
6795                 mutex_lock(&crtc->mutex);
6796
6797                 old->dpms_mode = connector->dpms;
6798                 old->load_detect_temp = false;
6799
6800                 /* Make sure the crtc and connector are running */
6801                 if (connector->dpms != DRM_MODE_DPMS_ON)
6802                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6803
6804                 return true;
6805         }
6806
6807         /* Find an unused one (if possible) */
6808         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6809                 i++;
6810                 if (!(encoder->possible_crtcs & (1 << i)))
6811                         continue;
6812                 if (!possible_crtc->enabled) {
6813                         crtc = possible_crtc;
6814                         break;
6815                 }
6816         }
6817
6818         /*
6819          * If we didn't find an unused CRTC, don't use any.
6820          */
6821         if (!crtc) {
6822                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6823                 return false;
6824         }
6825
6826         mutex_lock(&crtc->mutex);
6827         intel_encoder->new_crtc = to_intel_crtc(crtc);
6828         to_intel_connector(connector)->new_encoder = intel_encoder;
6829
6830         intel_crtc = to_intel_crtc(crtc);
6831         old->dpms_mode = connector->dpms;
6832         old->load_detect_temp = true;
6833         old->release_fb = NULL;
6834
6835         if (!mode)
6836                 mode = &load_detect_mode;
6837
6838         /* We need a framebuffer large enough to accommodate all accesses
6839          * that the plane may generate whilst we perform load detection.
6840          * We can not rely on the fbcon either being present (we get called
6841          * during its initialisation to detect all boot displays, or it may
6842          * not even exist) or that it is large enough to satisfy the
6843          * requested mode.
6844          */
6845         fb = mode_fits_in_fbdev(dev, mode);
6846         if (fb == NULL) {
6847                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6848                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6849                 old->release_fb = fb;
6850         } else
6851                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6852         if (IS_ERR(fb)) {
6853                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6854                 mutex_unlock(&crtc->mutex);
6855                 return false;
6856         }
6857
6858         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6859                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6860                 if (old->release_fb)
6861                         old->release_fb->funcs->destroy(old->release_fb);
6862                 mutex_unlock(&crtc->mutex);
6863                 return false;
6864         }
6865
6866         /* let the connector get through one full cycle before testing */
6867         intel_wait_for_vblank(dev, intel_crtc->pipe);
6868         return true;
6869 }
6870
6871 void intel_release_load_detect_pipe(struct drm_connector *connector,
6872                                     struct intel_load_detect_pipe *old)
6873 {
6874         struct intel_encoder *intel_encoder =
6875                 intel_attached_encoder(connector);
6876         struct drm_encoder *encoder = &intel_encoder->base;
6877         struct drm_crtc *crtc = encoder->crtc;
6878
6879         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6880                       connector->base.id, drm_get_connector_name(connector),
6881                       encoder->base.id, drm_get_encoder_name(encoder));
6882
6883         if (old->load_detect_temp) {
6884                 to_intel_connector(connector)->new_encoder = NULL;
6885                 intel_encoder->new_crtc = NULL;
6886                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6887
6888                 if (old->release_fb) {
6889                         drm_framebuffer_unregister_private(old->release_fb);
6890                         drm_framebuffer_unreference(old->release_fb);
6891                 }
6892
6893                 mutex_unlock(&crtc->mutex);
6894                 return;
6895         }
6896
6897         /* Switch crtc and encoder back off if necessary */
6898         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6899                 connector->funcs->dpms(connector, old->dpms_mode);
6900
6901         mutex_unlock(&crtc->mutex);
6902 }
6903
6904 /* Returns the clock of the currently programmed mode of the given pipe. */
6905 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6906 {
6907         struct drm_i915_private *dev_priv = dev->dev_private;
6908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6909         int pipe = intel_crtc->pipe;
6910         u32 dpll = I915_READ(DPLL(pipe));
6911         u32 fp;
6912         intel_clock_t clock;
6913
6914         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6915                 fp = I915_READ(FP0(pipe));
6916         else
6917                 fp = I915_READ(FP1(pipe));
6918
6919         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6920         if (IS_PINEVIEW(dev)) {
6921                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6922                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6923         } else {
6924                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6925                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6926         }
6927
6928         if (!IS_GEN2(dev)) {
6929                 if (IS_PINEVIEW(dev))
6930                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6931                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6932                 else
6933                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6934                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6935
6936                 switch (dpll & DPLL_MODE_MASK) {
6937                 case DPLLB_MODE_DAC_SERIAL:
6938                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6939                                 5 : 10;
6940                         break;
6941                 case DPLLB_MODE_LVDS:
6942                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6943                                 7 : 14;
6944                         break;
6945                 default:
6946                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6947                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6948                         return 0;
6949                 }
6950
6951                 if (IS_PINEVIEW(dev))
6952                         pineview_clock(96000, &clock);
6953                 else
6954                         i9xx_clock(96000, &clock);
6955         } else {
6956                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6957
6958                 if (is_lvds) {
6959                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6960                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6961                         clock.p2 = 14;
6962
6963                         if ((dpll & PLL_REF_INPUT_MASK) ==
6964                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6965                                 /* XXX: might not be 66MHz */
6966                                 i9xx_clock(66000, &clock);
6967                         } else
6968                                 i9xx_clock(48000, &clock);
6969                 } else {
6970                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6971                                 clock.p1 = 2;
6972                         else {
6973                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6974                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6975                         }
6976                         if (dpll & PLL_P2_DIVIDE_BY_4)
6977                                 clock.p2 = 4;
6978                         else
6979                                 clock.p2 = 2;
6980
6981                         i9xx_clock(48000, &clock);
6982                 }
6983         }
6984
6985         /* XXX: It would be nice to validate the clocks, but we can't reuse
6986          * i830PllIsValid() because it relies on the xf86_config connector
6987          * configuration being accurate, which it isn't necessarily.
6988          */
6989
6990         return clock.dot;
6991 }
6992
6993 /** Returns the currently programmed mode of the given pipe. */
6994 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6995                                              struct drm_crtc *crtc)
6996 {
6997         struct drm_i915_private *dev_priv = dev->dev_private;
6998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6999         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7000         struct drm_display_mode *mode;
7001         int htot = I915_READ(HTOTAL(cpu_transcoder));
7002         int hsync = I915_READ(HSYNC(cpu_transcoder));
7003         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7004         int vsync = I915_READ(VSYNC(cpu_transcoder));
7005
7006         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7007         if (!mode)
7008                 return NULL;
7009
7010         mode->clock = intel_crtc_clock_get(dev, crtc);
7011         mode->hdisplay = (htot & 0xffff) + 1;
7012         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7013         mode->hsync_start = (hsync & 0xffff) + 1;
7014         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7015         mode->vdisplay = (vtot & 0xffff) + 1;
7016         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7017         mode->vsync_start = (vsync & 0xffff) + 1;
7018         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7019
7020         drm_mode_set_name(mode);
7021
7022         return mode;
7023 }
7024
7025 static void intel_increase_pllclock(struct drm_crtc *crtc)
7026 {
7027         struct drm_device *dev = crtc->dev;
7028         drm_i915_private_t *dev_priv = dev->dev_private;
7029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7030         int pipe = intel_crtc->pipe;
7031         int dpll_reg = DPLL(pipe);
7032         int dpll;
7033
7034         if (HAS_PCH_SPLIT(dev))
7035                 return;
7036
7037         if (!dev_priv->lvds_downclock_avail)
7038                 return;
7039
7040         dpll = I915_READ(dpll_reg);
7041         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7042                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7043
7044                 assert_panel_unlocked(dev_priv, pipe);
7045
7046                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7047                 I915_WRITE(dpll_reg, dpll);
7048                 intel_wait_for_vblank(dev, pipe);
7049
7050                 dpll = I915_READ(dpll_reg);
7051                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7052                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7053         }
7054 }
7055
7056 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7057 {
7058         struct drm_device *dev = crtc->dev;
7059         drm_i915_private_t *dev_priv = dev->dev_private;
7060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7061
7062         if (HAS_PCH_SPLIT(dev))
7063                 return;
7064
7065         if (!dev_priv->lvds_downclock_avail)
7066                 return;
7067
7068         /*
7069          * Since this is called by a timer, we should never get here in
7070          * the manual case.
7071          */
7072         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7073                 int pipe = intel_crtc->pipe;
7074                 int dpll_reg = DPLL(pipe);
7075                 int dpll;
7076
7077                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7078
7079                 assert_panel_unlocked(dev_priv, pipe);
7080
7081                 dpll = I915_READ(dpll_reg);
7082                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7083                 I915_WRITE(dpll_reg, dpll);
7084                 intel_wait_for_vblank(dev, pipe);
7085                 dpll = I915_READ(dpll_reg);
7086                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7087                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7088         }
7089
7090 }
7091
7092 void intel_mark_busy(struct drm_device *dev)
7093 {
7094         i915_update_gfx_val(dev->dev_private);
7095 }
7096
7097 void intel_mark_idle(struct drm_device *dev)
7098 {
7099         struct drm_crtc *crtc;
7100
7101         if (!i915_powersave)
7102                 return;
7103
7104         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7105                 if (!crtc->fb)
7106                         continue;
7107
7108                 intel_decrease_pllclock(crtc);
7109         }
7110 }
7111
7112 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7113 {
7114         struct drm_device *dev = obj->base.dev;
7115         struct drm_crtc *crtc;
7116
7117         if (!i915_powersave)
7118                 return;
7119
7120         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7121                 if (!crtc->fb)
7122                         continue;
7123
7124                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7125                         intel_increase_pllclock(crtc);
7126         }
7127 }
7128
7129 static void intel_crtc_destroy(struct drm_crtc *crtc)
7130 {
7131         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7132         struct drm_device *dev = crtc->dev;
7133         struct intel_unpin_work *work;
7134         unsigned long flags;
7135
7136         spin_lock_irqsave(&dev->event_lock, flags);
7137         work = intel_crtc->unpin_work;
7138         intel_crtc->unpin_work = NULL;
7139         spin_unlock_irqrestore(&dev->event_lock, flags);
7140
7141         if (work) {
7142                 cancel_work_sync(&work->work);
7143                 kfree(work);
7144         }
7145
7146         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7147
7148         drm_crtc_cleanup(crtc);
7149
7150         kfree(intel_crtc);
7151 }
7152
7153 static void intel_unpin_work_fn(struct work_struct *__work)
7154 {
7155         struct intel_unpin_work *work =
7156                 container_of(__work, struct intel_unpin_work, work);
7157         struct drm_device *dev = work->crtc->dev;
7158
7159         mutex_lock(&dev->struct_mutex);
7160         intel_unpin_fb_obj(work->old_fb_obj);
7161         drm_gem_object_unreference(&work->pending_flip_obj->base);
7162         drm_gem_object_unreference(&work->old_fb_obj->base);
7163
7164         intel_update_fbc(dev);
7165         mutex_unlock(&dev->struct_mutex);
7166
7167         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7168         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7169
7170         kfree(work);
7171 }
7172
7173 static void do_intel_finish_page_flip(struct drm_device *dev,
7174                                       struct drm_crtc *crtc)
7175 {
7176         drm_i915_private_t *dev_priv = dev->dev_private;
7177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7178         struct intel_unpin_work *work;
7179         unsigned long flags;
7180
7181         /* Ignore early vblank irqs */
7182         if (intel_crtc == NULL)
7183                 return;
7184
7185         spin_lock_irqsave(&dev->event_lock, flags);
7186         work = intel_crtc->unpin_work;
7187
7188         /* Ensure we don't miss a work->pending update ... */
7189         smp_rmb();
7190
7191         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7192                 spin_unlock_irqrestore(&dev->event_lock, flags);
7193                 return;
7194         }
7195
7196         /* and that the unpin work is consistent wrt ->pending. */
7197         smp_rmb();
7198
7199         intel_crtc->unpin_work = NULL;
7200
7201         if (work->event)
7202                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7203
7204         drm_vblank_put(dev, intel_crtc->pipe);
7205
7206         spin_unlock_irqrestore(&dev->event_lock, flags);
7207
7208         wake_up_all(&dev_priv->pending_flip_queue);
7209
7210         queue_work(dev_priv->wq, &work->work);
7211
7212         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7213 }
7214
7215 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7216 {
7217         drm_i915_private_t *dev_priv = dev->dev_private;
7218         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7219
7220         do_intel_finish_page_flip(dev, crtc);
7221 }
7222
7223 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7224 {
7225         drm_i915_private_t *dev_priv = dev->dev_private;
7226         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7227
7228         do_intel_finish_page_flip(dev, crtc);
7229 }
7230
7231 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7232 {
7233         drm_i915_private_t *dev_priv = dev->dev_private;
7234         struct intel_crtc *intel_crtc =
7235                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7236         unsigned long flags;
7237
7238         /* NB: An MMIO update of the plane base pointer will also
7239          * generate a page-flip completion irq, i.e. every modeset
7240          * is also accompanied by a spurious intel_prepare_page_flip().
7241          */
7242         spin_lock_irqsave(&dev->event_lock, flags);
7243         if (intel_crtc->unpin_work)
7244                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7245         spin_unlock_irqrestore(&dev->event_lock, flags);
7246 }
7247
7248 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7249 {
7250         /* Ensure that the work item is consistent when activating it ... */
7251         smp_wmb();
7252         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7253         /* and that it is marked active as soon as the irq could fire. */
7254         smp_wmb();
7255 }
7256
7257 static int intel_gen2_queue_flip(struct drm_device *dev,
7258                                  struct drm_crtc *crtc,
7259                                  struct drm_framebuffer *fb,
7260                                  struct drm_i915_gem_object *obj)
7261 {
7262         struct drm_i915_private *dev_priv = dev->dev_private;
7263         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7264         u32 flip_mask;
7265         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7266         int ret;
7267
7268         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7269         if (ret)
7270                 goto err;
7271
7272         ret = intel_ring_begin(ring, 6);
7273         if (ret)
7274                 goto err_unpin;
7275
7276         /* Can't queue multiple flips, so wait for the previous
7277          * one to finish before executing the next.
7278          */
7279         if (intel_crtc->plane)
7280                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7281         else
7282                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7283         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7284         intel_ring_emit(ring, MI_NOOP);
7285         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7286                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7287         intel_ring_emit(ring, fb->pitches[0]);
7288         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7289         intel_ring_emit(ring, 0); /* aux display base address, unused */
7290
7291         intel_mark_page_flip_active(intel_crtc);
7292         intel_ring_advance(ring);
7293         return 0;
7294
7295 err_unpin:
7296         intel_unpin_fb_obj(obj);
7297 err:
7298         return ret;
7299 }
7300
7301 static int intel_gen3_queue_flip(struct drm_device *dev,
7302                                  struct drm_crtc *crtc,
7303                                  struct drm_framebuffer *fb,
7304                                  struct drm_i915_gem_object *obj)
7305 {
7306         struct drm_i915_private *dev_priv = dev->dev_private;
7307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7308         u32 flip_mask;
7309         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7310         int ret;
7311
7312         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7313         if (ret)
7314                 goto err;
7315
7316         ret = intel_ring_begin(ring, 6);
7317         if (ret)
7318                 goto err_unpin;
7319
7320         if (intel_crtc->plane)
7321                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7322         else
7323                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7324         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7325         intel_ring_emit(ring, MI_NOOP);
7326         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7327                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7328         intel_ring_emit(ring, fb->pitches[0]);
7329         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7330         intel_ring_emit(ring, MI_NOOP);
7331
7332         intel_mark_page_flip_active(intel_crtc);
7333         intel_ring_advance(ring);
7334         return 0;
7335
7336 err_unpin:
7337         intel_unpin_fb_obj(obj);
7338 err:
7339         return ret;
7340 }
7341
7342 static int intel_gen4_queue_flip(struct drm_device *dev,
7343                                  struct drm_crtc *crtc,
7344                                  struct drm_framebuffer *fb,
7345                                  struct drm_i915_gem_object *obj)
7346 {
7347         struct drm_i915_private *dev_priv = dev->dev_private;
7348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7349         uint32_t pf, pipesrc;
7350         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7351         int ret;
7352
7353         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7354         if (ret)
7355                 goto err;
7356
7357         ret = intel_ring_begin(ring, 4);
7358         if (ret)
7359                 goto err_unpin;
7360
7361         /* i965+ uses the linear or tiled offsets from the
7362          * Display Registers (which do not change across a page-flip)
7363          * so we need only reprogram the base address.
7364          */
7365         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7366                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7367         intel_ring_emit(ring, fb->pitches[0]);
7368         intel_ring_emit(ring,
7369                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7370                         obj->tiling_mode);
7371
7372         /* XXX Enabling the panel-fitter across page-flip is so far
7373          * untested on non-native modes, so ignore it for now.
7374          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7375          */
7376         pf = 0;
7377         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7378         intel_ring_emit(ring, pf | pipesrc);
7379
7380         intel_mark_page_flip_active(intel_crtc);
7381         intel_ring_advance(ring);
7382         return 0;
7383
7384 err_unpin:
7385         intel_unpin_fb_obj(obj);
7386 err:
7387         return ret;
7388 }
7389
7390 static int intel_gen6_queue_flip(struct drm_device *dev,
7391                                  struct drm_crtc *crtc,
7392                                  struct drm_framebuffer *fb,
7393                                  struct drm_i915_gem_object *obj)
7394 {
7395         struct drm_i915_private *dev_priv = dev->dev_private;
7396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7397         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7398         uint32_t pf, pipesrc;
7399         int ret;
7400
7401         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7402         if (ret)
7403                 goto err;
7404
7405         ret = intel_ring_begin(ring, 4);
7406         if (ret)
7407                 goto err_unpin;
7408
7409         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7410                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7411         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7412         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7413
7414         /* Contrary to the suggestions in the documentation,
7415          * "Enable Panel Fitter" does not seem to be required when page
7416          * flipping with a non-native mode, and worse causes a normal
7417          * modeset to fail.
7418          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7419          */
7420         pf = 0;
7421         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7422         intel_ring_emit(ring, pf | pipesrc);
7423
7424         intel_mark_page_flip_active(intel_crtc);
7425         intel_ring_advance(ring);
7426         return 0;
7427
7428 err_unpin:
7429         intel_unpin_fb_obj(obj);
7430 err:
7431         return ret;
7432 }
7433
7434 /*
7435  * On gen7 we currently use the blit ring because (in early silicon at least)
7436  * the render ring doesn't give us interrpts for page flip completion, which
7437  * means clients will hang after the first flip is queued.  Fortunately the
7438  * blit ring generates interrupts properly, so use it instead.
7439  */
7440 static int intel_gen7_queue_flip(struct drm_device *dev,
7441                                  struct drm_crtc *crtc,
7442                                  struct drm_framebuffer *fb,
7443                                  struct drm_i915_gem_object *obj)
7444 {
7445         struct drm_i915_private *dev_priv = dev->dev_private;
7446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7447         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7448         uint32_t plane_bit = 0;
7449         int ret;
7450
7451         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7452         if (ret)
7453                 goto err;
7454
7455         switch(intel_crtc->plane) {
7456         case PLANE_A:
7457                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7458                 break;
7459         case PLANE_B:
7460                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7461                 break;
7462         case PLANE_C:
7463                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7464                 break;
7465         default:
7466                 WARN_ONCE(1, "unknown plane in flip command\n");
7467                 ret = -ENODEV;
7468                 goto err_unpin;
7469         }
7470
7471         ret = intel_ring_begin(ring, 4);
7472         if (ret)
7473                 goto err_unpin;
7474
7475         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7476         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7477         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7478         intel_ring_emit(ring, (MI_NOOP));
7479
7480         intel_mark_page_flip_active(intel_crtc);
7481         intel_ring_advance(ring);
7482         return 0;
7483
7484 err_unpin:
7485         intel_unpin_fb_obj(obj);
7486 err:
7487         return ret;
7488 }
7489
7490 static int intel_default_queue_flip(struct drm_device *dev,
7491                                     struct drm_crtc *crtc,
7492                                     struct drm_framebuffer *fb,
7493                                     struct drm_i915_gem_object *obj)
7494 {
7495         return -ENODEV;
7496 }
7497
7498 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7499                                 struct drm_framebuffer *fb,
7500                                 struct drm_pending_vblank_event *event)
7501 {
7502         struct drm_device *dev = crtc->dev;
7503         struct drm_i915_private *dev_priv = dev->dev_private;
7504         struct drm_framebuffer *old_fb = crtc->fb;
7505         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7507         struct intel_unpin_work *work;
7508         unsigned long flags;
7509         int ret;
7510
7511         /* Can't change pixel format via MI display flips. */
7512         if (fb->pixel_format != crtc->fb->pixel_format)
7513                 return -EINVAL;
7514
7515         /*
7516          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7517          * Note that pitch changes could also affect these register.
7518          */
7519         if (INTEL_INFO(dev)->gen > 3 &&
7520             (fb->offsets[0] != crtc->fb->offsets[0] ||
7521              fb->pitches[0] != crtc->fb->pitches[0]))
7522                 return -EINVAL;
7523
7524         work = kzalloc(sizeof *work, GFP_KERNEL);
7525         if (work == NULL)
7526                 return -ENOMEM;
7527
7528         work->event = event;
7529         work->crtc = crtc;
7530         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7531         INIT_WORK(&work->work, intel_unpin_work_fn);
7532
7533         ret = drm_vblank_get(dev, intel_crtc->pipe);
7534         if (ret)
7535                 goto free_work;
7536
7537         /* We borrow the event spin lock for protecting unpin_work */
7538         spin_lock_irqsave(&dev->event_lock, flags);
7539         if (intel_crtc->unpin_work) {
7540                 spin_unlock_irqrestore(&dev->event_lock, flags);
7541                 kfree(work);
7542                 drm_vblank_put(dev, intel_crtc->pipe);
7543
7544                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7545                 return -EBUSY;
7546         }
7547         intel_crtc->unpin_work = work;
7548         spin_unlock_irqrestore(&dev->event_lock, flags);
7549
7550         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7551                 flush_workqueue(dev_priv->wq);
7552
7553         ret = i915_mutex_lock_interruptible(dev);
7554         if (ret)
7555                 goto cleanup;
7556
7557         /* Reference the objects for the scheduled work. */
7558         drm_gem_object_reference(&work->old_fb_obj->base);
7559         drm_gem_object_reference(&obj->base);
7560
7561         crtc->fb = fb;
7562
7563         work->pending_flip_obj = obj;
7564
7565         work->enable_stall_check = true;
7566
7567         atomic_inc(&intel_crtc->unpin_work_count);
7568         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7569
7570         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7571         if (ret)
7572                 goto cleanup_pending;
7573
7574         intel_disable_fbc(dev);
7575         intel_mark_fb_busy(obj);
7576         mutex_unlock(&dev->struct_mutex);
7577
7578         trace_i915_flip_request(intel_crtc->plane, obj);
7579
7580         return 0;
7581
7582 cleanup_pending:
7583         atomic_dec(&intel_crtc->unpin_work_count);
7584         crtc->fb = old_fb;
7585         drm_gem_object_unreference(&work->old_fb_obj->base);
7586         drm_gem_object_unreference(&obj->base);
7587         mutex_unlock(&dev->struct_mutex);
7588
7589 cleanup:
7590         spin_lock_irqsave(&dev->event_lock, flags);
7591         intel_crtc->unpin_work = NULL;
7592         spin_unlock_irqrestore(&dev->event_lock, flags);
7593
7594         drm_vblank_put(dev, intel_crtc->pipe);
7595 free_work:
7596         kfree(work);
7597
7598         return ret;
7599 }
7600
7601 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7602         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7603         .load_lut = intel_crtc_load_lut,
7604 };
7605
7606 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7607                                   struct drm_crtc *crtc)
7608 {
7609         struct drm_device *dev;
7610         struct drm_crtc *tmp;
7611         int crtc_mask = 1;
7612
7613         WARN(!crtc, "checking null crtc?\n");
7614
7615         dev = crtc->dev;
7616
7617         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7618                 if (tmp == crtc)
7619                         break;
7620                 crtc_mask <<= 1;
7621         }
7622
7623         if (encoder->possible_crtcs & crtc_mask)
7624                 return true;
7625         return false;
7626 }
7627
7628 /**
7629  * intel_modeset_update_staged_output_state
7630  *
7631  * Updates the staged output configuration state, e.g. after we've read out the
7632  * current hw state.
7633  */
7634 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7635 {
7636         struct intel_encoder *encoder;
7637         struct intel_connector *connector;
7638
7639         list_for_each_entry(connector, &dev->mode_config.connector_list,
7640                             base.head) {
7641                 connector->new_encoder =
7642                         to_intel_encoder(connector->base.encoder);
7643         }
7644
7645         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7646                             base.head) {
7647                 encoder->new_crtc =
7648                         to_intel_crtc(encoder->base.crtc);
7649         }
7650 }
7651
7652 /**
7653  * intel_modeset_commit_output_state
7654  *
7655  * This function copies the stage display pipe configuration to the real one.
7656  */
7657 static void intel_modeset_commit_output_state(struct drm_device *dev)
7658 {
7659         struct intel_encoder *encoder;
7660         struct intel_connector *connector;
7661
7662         list_for_each_entry(connector, &dev->mode_config.connector_list,
7663                             base.head) {
7664                 connector->base.encoder = &connector->new_encoder->base;
7665         }
7666
7667         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7668                             base.head) {
7669                 encoder->base.crtc = &encoder->new_crtc->base;
7670         }
7671 }
7672
7673 static void
7674 connected_sink_compute_bpp(struct intel_connector * connector,
7675                            struct intel_crtc_config *pipe_config)
7676 {
7677         int bpp = pipe_config->pipe_bpp;
7678
7679         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7680                 connector->base.base.id,
7681                 drm_get_connector_name(&connector->base));
7682
7683         /* Don't use an invalid EDID bpc value */
7684         if (connector->base.display_info.bpc &&
7685             connector->base.display_info.bpc * 3 < bpp) {
7686                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7687                               bpp, connector->base.display_info.bpc*3);
7688                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7689         }
7690
7691         /* Clamp bpp to 8 on screens without EDID 1.4 */
7692         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7693                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7694                               bpp);
7695                 pipe_config->pipe_bpp = 24;
7696         }
7697 }
7698
7699 static int
7700 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7701                           struct drm_framebuffer *fb,
7702                           struct intel_crtc_config *pipe_config)
7703 {
7704         struct drm_device *dev = crtc->base.dev;
7705         struct intel_connector *connector;
7706         int bpp;
7707
7708         switch (fb->pixel_format) {
7709         case DRM_FORMAT_C8:
7710                 bpp = 8*3; /* since we go through a colormap */
7711                 break;
7712         case DRM_FORMAT_XRGB1555:
7713         case DRM_FORMAT_ARGB1555:
7714                 /* checked in intel_framebuffer_init already */
7715                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7716                         return -EINVAL;
7717         case DRM_FORMAT_RGB565:
7718                 bpp = 6*3; /* min is 18bpp */
7719                 break;
7720         case DRM_FORMAT_XBGR8888:
7721         case DRM_FORMAT_ABGR8888:
7722                 /* checked in intel_framebuffer_init already */
7723                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7724                         return -EINVAL;
7725         case DRM_FORMAT_XRGB8888:
7726         case DRM_FORMAT_ARGB8888:
7727                 bpp = 8*3;
7728                 break;
7729         case DRM_FORMAT_XRGB2101010:
7730         case DRM_FORMAT_ARGB2101010:
7731         case DRM_FORMAT_XBGR2101010:
7732         case DRM_FORMAT_ABGR2101010:
7733                 /* checked in intel_framebuffer_init already */
7734                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7735                         return -EINVAL;
7736                 bpp = 10*3;
7737                 break;
7738         /* TODO: gen4+ supports 16 bpc floating point, too. */
7739         default:
7740                 DRM_DEBUG_KMS("unsupported depth\n");
7741                 return -EINVAL;
7742         }
7743
7744         pipe_config->pipe_bpp = bpp;
7745
7746         /* Clamp display bpp to EDID value */
7747         list_for_each_entry(connector, &dev->mode_config.connector_list,
7748                             base.head) {
7749                 if (!connector->new_encoder ||
7750                     connector->new_encoder->new_crtc != crtc)
7751                         continue;
7752
7753                 connected_sink_compute_bpp(connector, pipe_config);
7754         }
7755
7756         return bpp;
7757 }
7758
7759 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7760                                    struct intel_crtc_config *pipe_config,
7761                                    const char *context)
7762 {
7763         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7764                       context, pipe_name(crtc->pipe));
7765
7766         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7767         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7768                       pipe_config->pipe_bpp, pipe_config->dither);
7769         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7770                       pipe_config->has_pch_encoder,
7771                       pipe_config->fdi_lanes,
7772                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7773                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7774                       pipe_config->fdi_m_n.tu);
7775         DRM_DEBUG_KMS("requested mode:\n");
7776         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7777         DRM_DEBUG_KMS("adjusted mode:\n");
7778         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7779         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7780                       pipe_config->gmch_pfit.control,
7781                       pipe_config->gmch_pfit.pgm_ratios,
7782                       pipe_config->gmch_pfit.lvds_border_bits);
7783         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7784                       pipe_config->pch_pfit.pos,
7785                       pipe_config->pch_pfit.size);
7786         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7787 }
7788
7789 static bool check_encoder_cloning(struct drm_crtc *crtc)
7790 {
7791         int num_encoders = 0;
7792         bool uncloneable_encoders = false;
7793         struct intel_encoder *encoder;
7794
7795         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7796                             base.head) {
7797                 if (&encoder->new_crtc->base != crtc)
7798                         continue;
7799
7800                 num_encoders++;
7801                 if (!encoder->cloneable)
7802                         uncloneable_encoders = true;
7803         }
7804
7805         return !(num_encoders > 1 && uncloneable_encoders);
7806 }
7807
7808 static struct intel_crtc_config *
7809 intel_modeset_pipe_config(struct drm_crtc *crtc,
7810                           struct drm_framebuffer *fb,
7811                           struct drm_display_mode *mode)
7812 {
7813         struct drm_device *dev = crtc->dev;
7814         struct drm_encoder_helper_funcs *encoder_funcs;
7815         struct intel_encoder *encoder;
7816         struct intel_crtc_config *pipe_config;
7817         int plane_bpp, ret = -EINVAL;
7818         bool retry = true;
7819
7820         if (!check_encoder_cloning(crtc)) {
7821                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7822                 return ERR_PTR(-EINVAL);
7823         }
7824
7825         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7826         if (!pipe_config)
7827                 return ERR_PTR(-ENOMEM);
7828
7829         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7830         drm_mode_copy(&pipe_config->requested_mode, mode);
7831         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7832
7833         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7834          * plane pixel format and any sink constraints into account. Returns the
7835          * source plane bpp so that dithering can be selected on mismatches
7836          * after encoders and crtc also have had their say. */
7837         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7838                                               fb, pipe_config);
7839         if (plane_bpp < 0)
7840                 goto fail;
7841
7842 encoder_retry:
7843         /* Ensure the port clock defaults are reset when retrying. */
7844         pipe_config->port_clock = 0;
7845         pipe_config->pixel_multiplier = 1;
7846
7847         /* Pass our mode to the connectors and the CRTC to give them a chance to
7848          * adjust it according to limitations or connector properties, and also
7849          * a chance to reject the mode entirely.
7850          */
7851         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7852                             base.head) {
7853
7854                 if (&encoder->new_crtc->base != crtc)
7855                         continue;
7856
7857                 if (encoder->compute_config) {
7858                         if (!(encoder->compute_config(encoder, pipe_config))) {
7859                                 DRM_DEBUG_KMS("Encoder config failure\n");
7860                                 goto fail;
7861                         }
7862
7863                         continue;
7864                 }
7865
7866                 encoder_funcs = encoder->base.helper_private;
7867                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7868                                                 &pipe_config->requested_mode,
7869                                                 &pipe_config->adjusted_mode))) {
7870                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7871                         goto fail;
7872                 }
7873         }
7874
7875         /* Set default port clock if not overwritten by the encoder. Needs to be
7876          * done afterwards in case the encoder adjusts the mode. */
7877         if (!pipe_config->port_clock)
7878                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7879
7880         ret = intel_crtc_compute_config(crtc, pipe_config);
7881         if (ret < 0) {
7882                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7883                 goto fail;
7884         }
7885
7886         if (ret == RETRY) {
7887                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7888                         ret = -EINVAL;
7889                         goto fail;
7890                 }
7891
7892                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7893                 retry = false;
7894                 goto encoder_retry;
7895         }
7896
7897         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7898         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7899                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7900
7901         return pipe_config;
7902 fail:
7903         kfree(pipe_config);
7904         return ERR_PTR(ret);
7905 }
7906
7907 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7908  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7909 static void
7910 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7911                              unsigned *prepare_pipes, unsigned *disable_pipes)
7912 {
7913         struct intel_crtc *intel_crtc;
7914         struct drm_device *dev = crtc->dev;
7915         struct intel_encoder *encoder;
7916         struct intel_connector *connector;
7917         struct drm_crtc *tmp_crtc;
7918
7919         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7920
7921         /* Check which crtcs have changed outputs connected to them, these need
7922          * to be part of the prepare_pipes mask. We don't (yet) support global
7923          * modeset across multiple crtcs, so modeset_pipes will only have one
7924          * bit set at most. */
7925         list_for_each_entry(connector, &dev->mode_config.connector_list,
7926                             base.head) {
7927                 if (connector->base.encoder == &connector->new_encoder->base)
7928                         continue;
7929
7930                 if (connector->base.encoder) {
7931                         tmp_crtc = connector->base.encoder->crtc;
7932
7933                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7934                 }
7935
7936                 if (connector->new_encoder)
7937                         *prepare_pipes |=
7938                                 1 << connector->new_encoder->new_crtc->pipe;
7939         }
7940
7941         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7942                             base.head) {
7943                 if (encoder->base.crtc == &encoder->new_crtc->base)
7944                         continue;
7945
7946                 if (encoder->base.crtc) {
7947                         tmp_crtc = encoder->base.crtc;
7948
7949                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7950                 }
7951
7952                 if (encoder->new_crtc)
7953                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7954         }
7955
7956         /* Check for any pipes that will be fully disabled ... */
7957         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7958                             base.head) {
7959                 bool used = false;
7960
7961                 /* Don't try to disable disabled crtcs. */
7962                 if (!intel_crtc->base.enabled)
7963                         continue;
7964
7965                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7966                                     base.head) {
7967                         if (encoder->new_crtc == intel_crtc)
7968                                 used = true;
7969                 }
7970
7971                 if (!used)
7972                         *disable_pipes |= 1 << intel_crtc->pipe;
7973         }
7974
7975
7976         /* set_mode is also used to update properties on life display pipes. */
7977         intel_crtc = to_intel_crtc(crtc);
7978         if (crtc->enabled)
7979                 *prepare_pipes |= 1 << intel_crtc->pipe;
7980
7981         /*
7982          * For simplicity do a full modeset on any pipe where the output routing
7983          * changed. We could be more clever, but that would require us to be
7984          * more careful with calling the relevant encoder->mode_set functions.
7985          */
7986         if (*prepare_pipes)
7987                 *modeset_pipes = *prepare_pipes;
7988
7989         /* ... and mask these out. */
7990         *modeset_pipes &= ~(*disable_pipes);
7991         *prepare_pipes &= ~(*disable_pipes);
7992
7993         /*
7994          * HACK: We don't (yet) fully support global modesets. intel_set_config
7995          * obies this rule, but the modeset restore mode of
7996          * intel_modeset_setup_hw_state does not.
7997          */
7998         *modeset_pipes &= 1 << intel_crtc->pipe;
7999         *prepare_pipes &= 1 << intel_crtc->pipe;
8000
8001         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8002                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8003 }
8004
8005 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8006 {
8007         struct drm_encoder *encoder;
8008         struct drm_device *dev = crtc->dev;
8009
8010         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8011                 if (encoder->crtc == crtc)
8012                         return true;
8013
8014         return false;
8015 }
8016
8017 static void
8018 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8019 {
8020         struct intel_encoder *intel_encoder;
8021         struct intel_crtc *intel_crtc;
8022         struct drm_connector *connector;
8023
8024         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8025                             base.head) {
8026                 if (!intel_encoder->base.crtc)
8027                         continue;
8028
8029                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8030
8031                 if (prepare_pipes & (1 << intel_crtc->pipe))
8032                         intel_encoder->connectors_active = false;
8033         }
8034
8035         intel_modeset_commit_output_state(dev);
8036
8037         /* Update computed state. */
8038         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8039                             base.head) {
8040                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8041         }
8042
8043         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8044                 if (!connector->encoder || !connector->encoder->crtc)
8045                         continue;
8046
8047                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8048
8049                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8050                         struct drm_property *dpms_property =
8051                                 dev->mode_config.dpms_property;
8052
8053                         connector->dpms = DRM_MODE_DPMS_ON;
8054                         drm_object_property_set_value(&connector->base,
8055                                                          dpms_property,
8056                                                          DRM_MODE_DPMS_ON);
8057
8058                         intel_encoder = to_intel_encoder(connector->encoder);
8059                         intel_encoder->connectors_active = true;
8060                 }
8061         }
8062
8063 }
8064
8065 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8066         list_for_each_entry((intel_crtc), \
8067                             &(dev)->mode_config.crtc_list, \
8068                             base.head) \
8069                 if (mask & (1 <<(intel_crtc)->pipe))
8070
8071 static bool
8072 intel_pipe_config_compare(struct drm_device *dev,
8073                           struct intel_crtc_config *current_config,
8074                           struct intel_crtc_config *pipe_config)
8075 {
8076 #define PIPE_CONF_CHECK_I(name) \
8077         if (current_config->name != pipe_config->name) { \
8078                 DRM_ERROR("mismatch in " #name " " \
8079                           "(expected %i, found %i)\n", \
8080                           current_config->name, \
8081                           pipe_config->name); \
8082                 return false; \
8083         }
8084
8085 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8086         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8087                 DRM_ERROR("mismatch in " #name " " \
8088                           "(expected %i, found %i)\n", \
8089                           current_config->name & (mask), \
8090                           pipe_config->name & (mask)); \
8091                 return false; \
8092         }
8093
8094 #define PIPE_CONF_QUIRK(quirk)  \
8095         ((current_config->quirks | pipe_config->quirks) & (quirk))
8096
8097         PIPE_CONF_CHECK_I(cpu_transcoder);
8098
8099         PIPE_CONF_CHECK_I(has_pch_encoder);
8100         PIPE_CONF_CHECK_I(fdi_lanes);
8101         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8102         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8103         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8104         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8105         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8106
8107         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8108         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8109         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8110         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8111         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8112         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8113
8114         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8115         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8116         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8117         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8118         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8119         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8120
8121         if (!HAS_PCH_SPLIT(dev))
8122                 PIPE_CONF_CHECK_I(pixel_multiplier);
8123
8124         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8125                               DRM_MODE_FLAG_INTERLACE);
8126
8127         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8128                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8129                                       DRM_MODE_FLAG_PHSYNC);
8130                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8131                                       DRM_MODE_FLAG_NHSYNC);
8132                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8133                                       DRM_MODE_FLAG_PVSYNC);
8134                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8135                                       DRM_MODE_FLAG_NVSYNC);
8136         }
8137
8138         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8139         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8140
8141         PIPE_CONF_CHECK_I(gmch_pfit.control);
8142         /* pfit ratios are autocomputed by the hw on gen4+ */
8143         if (INTEL_INFO(dev)->gen < 4)
8144                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8145         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8146         PIPE_CONF_CHECK_I(pch_pfit.pos);
8147         PIPE_CONF_CHECK_I(pch_pfit.size);
8148
8149         PIPE_CONF_CHECK_I(ips_enabled);
8150
8151 #undef PIPE_CONF_CHECK_I
8152 #undef PIPE_CONF_CHECK_FLAGS
8153 #undef PIPE_CONF_QUIRK
8154
8155         return true;
8156 }
8157
8158 void
8159 intel_modeset_check_state(struct drm_device *dev)
8160 {
8161         drm_i915_private_t *dev_priv = dev->dev_private;
8162         struct intel_crtc *crtc;
8163         struct intel_encoder *encoder;
8164         struct intel_connector *connector;
8165         struct intel_crtc_config pipe_config;
8166
8167         list_for_each_entry(connector, &dev->mode_config.connector_list,
8168                             base.head) {
8169                 /* This also checks the encoder/connector hw state with the
8170                  * ->get_hw_state callbacks. */
8171                 intel_connector_check_state(connector);
8172
8173                 WARN(&connector->new_encoder->base != connector->base.encoder,
8174                      "connector's staged encoder doesn't match current encoder\n");
8175         }
8176
8177         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8178                             base.head) {
8179                 bool enabled = false;
8180                 bool active = false;
8181                 enum pipe pipe, tracked_pipe;
8182
8183                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8184                               encoder->base.base.id,
8185                               drm_get_encoder_name(&encoder->base));
8186
8187                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8188                      "encoder's stage crtc doesn't match current crtc\n");
8189                 WARN(encoder->connectors_active && !encoder->base.crtc,
8190                      "encoder's active_connectors set, but no crtc\n");
8191
8192                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8193                                     base.head) {
8194                         if (connector->base.encoder != &encoder->base)
8195                                 continue;
8196                         enabled = true;
8197                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8198                                 active = true;
8199                 }
8200                 WARN(!!encoder->base.crtc != enabled,
8201                      "encoder's enabled state mismatch "
8202                      "(expected %i, found %i)\n",
8203                      !!encoder->base.crtc, enabled);
8204                 WARN(active && !encoder->base.crtc,
8205                      "active encoder with no crtc\n");
8206
8207                 WARN(encoder->connectors_active != active,
8208                      "encoder's computed active state doesn't match tracked active state "
8209                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8210
8211                 active = encoder->get_hw_state(encoder, &pipe);
8212                 WARN(active != encoder->connectors_active,
8213                      "encoder's hw state doesn't match sw tracking "
8214                      "(expected %i, found %i)\n",
8215                      encoder->connectors_active, active);
8216
8217                 if (!encoder->base.crtc)
8218                         continue;
8219
8220                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8221                 WARN(active && pipe != tracked_pipe,
8222                      "active encoder's pipe doesn't match"
8223                      "(expected %i, found %i)\n",
8224                      tracked_pipe, pipe);
8225
8226         }
8227
8228         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8229                             base.head) {
8230                 bool enabled = false;
8231                 bool active = false;
8232
8233                 memset(&pipe_config, 0, sizeof(pipe_config));
8234
8235                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8236                               crtc->base.base.id);
8237
8238                 WARN(crtc->active && !crtc->base.enabled,
8239                      "active crtc, but not enabled in sw tracking\n");
8240
8241                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8242                                     base.head) {
8243                         if (encoder->base.crtc != &crtc->base)
8244                                 continue;
8245                         enabled = true;
8246                         if (encoder->connectors_active)
8247                                 active = true;
8248                 }
8249
8250                 WARN(active != crtc->active,
8251                      "crtc's computed active state doesn't match tracked active state "
8252                      "(expected %i, found %i)\n", active, crtc->active);
8253                 WARN(enabled != crtc->base.enabled,
8254                      "crtc's computed enabled state doesn't match tracked enabled state "
8255                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8256
8257                 active = dev_priv->display.get_pipe_config(crtc,
8258                                                            &pipe_config);
8259                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8260                                     base.head) {
8261                         if (encoder->base.crtc != &crtc->base)
8262                                 continue;
8263                         if (encoder->get_config)
8264                                 encoder->get_config(encoder, &pipe_config);
8265                 }
8266
8267                 WARN(crtc->active != active,
8268                      "crtc active state doesn't match with hw state "
8269                      "(expected %i, found %i)\n", crtc->active, active);
8270
8271                 if (active &&
8272                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8273                         WARN(1, "pipe state doesn't match!\n");
8274                         intel_dump_pipe_config(crtc, &pipe_config,
8275                                                "[hw state]");
8276                         intel_dump_pipe_config(crtc, &crtc->config,
8277                                                "[sw state]");
8278                 }
8279         }
8280 }
8281
8282 static int __intel_set_mode(struct drm_crtc *crtc,
8283                             struct drm_display_mode *mode,
8284                             int x, int y, struct drm_framebuffer *fb)
8285 {
8286         struct drm_device *dev = crtc->dev;
8287         drm_i915_private_t *dev_priv = dev->dev_private;
8288         struct drm_display_mode *saved_mode, *saved_hwmode;
8289         struct intel_crtc_config *pipe_config = NULL;
8290         struct intel_crtc *intel_crtc;
8291         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8292         int ret = 0;
8293
8294         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8295         if (!saved_mode)
8296                 return -ENOMEM;
8297         saved_hwmode = saved_mode + 1;
8298
8299         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8300                                      &prepare_pipes, &disable_pipes);
8301
8302         *saved_hwmode = crtc->hwmode;
8303         *saved_mode = crtc->mode;
8304
8305         /* Hack: Because we don't (yet) support global modeset on multiple
8306          * crtcs, we don't keep track of the new mode for more than one crtc.
8307          * Hence simply check whether any bit is set in modeset_pipes in all the
8308          * pieces of code that are not yet converted to deal with mutliple crtcs
8309          * changing their mode at the same time. */
8310         if (modeset_pipes) {
8311                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8312                 if (IS_ERR(pipe_config)) {
8313                         ret = PTR_ERR(pipe_config);
8314                         pipe_config = NULL;
8315
8316                         goto out;
8317                 }
8318                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8319                                        "[modeset]");
8320         }
8321
8322         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8323                 intel_crtc_disable(&intel_crtc->base);
8324
8325         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8326                 if (intel_crtc->base.enabled)
8327                         dev_priv->display.crtc_disable(&intel_crtc->base);
8328         }
8329
8330         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8331          * to set it here already despite that we pass it down the callchain.
8332          */
8333         if (modeset_pipes) {
8334                 crtc->mode = *mode;
8335                 /* mode_set/enable/disable functions rely on a correct pipe
8336                  * config. */
8337                 to_intel_crtc(crtc)->config = *pipe_config;
8338         }
8339
8340         /* Only after disabling all output pipelines that will be changed can we
8341          * update the the output configuration. */
8342         intel_modeset_update_state(dev, prepare_pipes);
8343
8344         if (dev_priv->display.modeset_global_resources)
8345                 dev_priv->display.modeset_global_resources(dev);
8346
8347         /* Set up the DPLL and any encoders state that needs to adjust or depend
8348          * on the DPLL.
8349          */
8350         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8351                 ret = intel_crtc_mode_set(&intel_crtc->base,
8352                                           x, y, fb);
8353                 if (ret)
8354                         goto done;
8355         }
8356
8357         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8358         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8359                 dev_priv->display.crtc_enable(&intel_crtc->base);
8360
8361         if (modeset_pipes) {
8362                 /* Store real post-adjustment hardware mode. */
8363                 crtc->hwmode = pipe_config->adjusted_mode;
8364
8365                 /* Calculate and store various constants which
8366                  * are later needed by vblank and swap-completion
8367                  * timestamping. They are derived from true hwmode.
8368                  */
8369                 drm_calc_timestamping_constants(crtc);
8370         }
8371
8372         /* FIXME: add subpixel order */
8373 done:
8374         if (ret && crtc->enabled) {
8375                 crtc->hwmode = *saved_hwmode;
8376                 crtc->mode = *saved_mode;
8377         }
8378
8379 out:
8380         kfree(pipe_config);
8381         kfree(saved_mode);
8382         return ret;
8383 }
8384
8385 int intel_set_mode(struct drm_crtc *crtc,
8386                      struct drm_display_mode *mode,
8387                      int x, int y, struct drm_framebuffer *fb)
8388 {
8389         int ret;
8390
8391         ret = __intel_set_mode(crtc, mode, x, y, fb);
8392
8393         if (ret == 0)
8394                 intel_modeset_check_state(crtc->dev);
8395
8396         return ret;
8397 }
8398
8399 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8400 {
8401         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8402 }
8403
8404 #undef for_each_intel_crtc_masked
8405
8406 static void intel_set_config_free(struct intel_set_config *config)
8407 {
8408         if (!config)
8409                 return;
8410
8411         kfree(config->save_connector_encoders);
8412         kfree(config->save_encoder_crtcs);
8413         kfree(config);
8414 }
8415
8416 static int intel_set_config_save_state(struct drm_device *dev,
8417                                        struct intel_set_config *config)
8418 {
8419         struct drm_encoder *encoder;
8420         struct drm_connector *connector;
8421         int count;
8422
8423         config->save_encoder_crtcs =
8424                 kcalloc(dev->mode_config.num_encoder,
8425                         sizeof(struct drm_crtc *), GFP_KERNEL);
8426         if (!config->save_encoder_crtcs)
8427                 return -ENOMEM;
8428
8429         config->save_connector_encoders =
8430                 kcalloc(dev->mode_config.num_connector,
8431                         sizeof(struct drm_encoder *), GFP_KERNEL);
8432         if (!config->save_connector_encoders)
8433                 return -ENOMEM;
8434
8435         /* Copy data. Note that driver private data is not affected.
8436          * Should anything bad happen only the expected state is
8437          * restored, not the drivers personal bookkeeping.
8438          */
8439         count = 0;
8440         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8441                 config->save_encoder_crtcs[count++] = encoder->crtc;
8442         }
8443
8444         count = 0;
8445         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8446                 config->save_connector_encoders[count++] = connector->encoder;
8447         }
8448
8449         return 0;
8450 }
8451
8452 static void intel_set_config_restore_state(struct drm_device *dev,
8453                                            struct intel_set_config *config)
8454 {
8455         struct intel_encoder *encoder;
8456         struct intel_connector *connector;
8457         int count;
8458
8459         count = 0;
8460         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8461                 encoder->new_crtc =
8462                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8463         }
8464
8465         count = 0;
8466         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8467                 connector->new_encoder =
8468                         to_intel_encoder(config->save_connector_encoders[count++]);
8469         }
8470 }
8471
8472 static void
8473 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8474                                       struct intel_set_config *config)
8475 {
8476
8477         /* We should be able to check here if the fb has the same properties
8478          * and then just flip_or_move it */
8479         if (set->crtc->fb != set->fb) {
8480                 /* If we have no fb then treat it as a full mode set */
8481                 if (set->crtc->fb == NULL) {
8482                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8483                         config->mode_changed = true;
8484                 } else if (set->fb == NULL) {
8485                         config->mode_changed = true;
8486                 } else if (set->fb->pixel_format !=
8487                            set->crtc->fb->pixel_format) {
8488                         config->mode_changed = true;
8489                 } else
8490                         config->fb_changed = true;
8491         }
8492
8493         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8494                 config->fb_changed = true;
8495
8496         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8497                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8498                 drm_mode_debug_printmodeline(&set->crtc->mode);
8499                 drm_mode_debug_printmodeline(set->mode);
8500                 config->mode_changed = true;
8501         }
8502 }
8503
8504 static int
8505 intel_modeset_stage_output_state(struct drm_device *dev,
8506                                  struct drm_mode_set *set,
8507                                  struct intel_set_config *config)
8508 {
8509         struct drm_crtc *new_crtc;
8510         struct intel_connector *connector;
8511         struct intel_encoder *encoder;
8512         int count, ro;
8513
8514         /* The upper layers ensure that we either disable a crtc or have a list
8515          * of connectors. For paranoia, double-check this. */
8516         WARN_ON(!set->fb && (set->num_connectors != 0));
8517         WARN_ON(set->fb && (set->num_connectors == 0));
8518
8519         count = 0;
8520         list_for_each_entry(connector, &dev->mode_config.connector_list,
8521                             base.head) {
8522                 /* Otherwise traverse passed in connector list and get encoders
8523                  * for them. */
8524                 for (ro = 0; ro < set->num_connectors; ro++) {
8525                         if (set->connectors[ro] == &connector->base) {
8526                                 connector->new_encoder = connector->encoder;
8527                                 break;
8528                         }
8529                 }
8530
8531                 /* If we disable the crtc, disable all its connectors. Also, if
8532                  * the connector is on the changing crtc but not on the new
8533                  * connector list, disable it. */
8534                 if ((!set->fb || ro == set->num_connectors) &&
8535                     connector->base.encoder &&
8536                     connector->base.encoder->crtc == set->crtc) {
8537                         connector->new_encoder = NULL;
8538
8539                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8540                                 connector->base.base.id,
8541                                 drm_get_connector_name(&connector->base));
8542                 }
8543
8544
8545                 if (&connector->new_encoder->base != connector->base.encoder) {
8546                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8547                         config->mode_changed = true;
8548                 }
8549         }
8550         /* connector->new_encoder is now updated for all connectors. */
8551
8552         /* Update crtc of enabled connectors. */
8553         count = 0;
8554         list_for_each_entry(connector, &dev->mode_config.connector_list,
8555                             base.head) {
8556                 if (!connector->new_encoder)
8557                         continue;
8558
8559                 new_crtc = connector->new_encoder->base.crtc;
8560
8561                 for (ro = 0; ro < set->num_connectors; ro++) {
8562                         if (set->connectors[ro] == &connector->base)
8563                                 new_crtc = set->crtc;
8564                 }
8565
8566                 /* Make sure the new CRTC will work with the encoder */
8567                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8568                                            new_crtc)) {
8569                         return -EINVAL;
8570                 }
8571                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8572
8573                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8574                         connector->base.base.id,
8575                         drm_get_connector_name(&connector->base),
8576                         new_crtc->base.id);
8577         }
8578
8579         /* Check for any encoders that needs to be disabled. */
8580         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8581                             base.head) {
8582                 list_for_each_entry(connector,
8583                                     &dev->mode_config.connector_list,
8584                                     base.head) {
8585                         if (connector->new_encoder == encoder) {
8586                                 WARN_ON(!connector->new_encoder->new_crtc);
8587
8588                                 goto next_encoder;
8589                         }
8590                 }
8591                 encoder->new_crtc = NULL;
8592 next_encoder:
8593                 /* Only now check for crtc changes so we don't miss encoders
8594                  * that will be disabled. */
8595                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8596                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8597                         config->mode_changed = true;
8598                 }
8599         }
8600         /* Now we've also updated encoder->new_crtc for all encoders. */
8601
8602         return 0;
8603 }
8604
8605 static int intel_crtc_set_config(struct drm_mode_set *set)
8606 {
8607         struct drm_device *dev;
8608         struct drm_mode_set save_set;
8609         struct intel_set_config *config;
8610         int ret;
8611
8612         BUG_ON(!set);
8613         BUG_ON(!set->crtc);
8614         BUG_ON(!set->crtc->helper_private);
8615
8616         /* Enforce sane interface api - has been abused by the fb helper. */
8617         BUG_ON(!set->mode && set->fb);
8618         BUG_ON(set->fb && set->num_connectors == 0);
8619
8620         if (set->fb) {
8621                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8622                                 set->crtc->base.id, set->fb->base.id,
8623                                 (int)set->num_connectors, set->x, set->y);
8624         } else {
8625                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8626         }
8627
8628         dev = set->crtc->dev;
8629
8630         ret = -ENOMEM;
8631         config = kzalloc(sizeof(*config), GFP_KERNEL);
8632         if (!config)
8633                 goto out_config;
8634
8635         ret = intel_set_config_save_state(dev, config);
8636         if (ret)
8637                 goto out_config;
8638
8639         save_set.crtc = set->crtc;
8640         save_set.mode = &set->crtc->mode;
8641         save_set.x = set->crtc->x;
8642         save_set.y = set->crtc->y;
8643         save_set.fb = set->crtc->fb;
8644
8645         /* Compute whether we need a full modeset, only an fb base update or no
8646          * change at all. In the future we might also check whether only the
8647          * mode changed, e.g. for LVDS where we only change the panel fitter in
8648          * such cases. */
8649         intel_set_config_compute_mode_changes(set, config);
8650
8651         ret = intel_modeset_stage_output_state(dev, set, config);
8652         if (ret)
8653                 goto fail;
8654
8655         if (config->mode_changed) {
8656                 ret = intel_set_mode(set->crtc, set->mode,
8657                                      set->x, set->y, set->fb);
8658                 if (ret) {
8659                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8660                                   set->crtc->base.id, ret);
8661                         goto fail;
8662                 }
8663         } else if (config->fb_changed) {
8664                 intel_crtc_wait_for_pending_flips(set->crtc);
8665
8666                 ret = intel_pipe_set_base(set->crtc,
8667                                           set->x, set->y, set->fb);
8668         }
8669
8670         intel_set_config_free(config);
8671
8672         return 0;
8673
8674 fail:
8675         intel_set_config_restore_state(dev, config);
8676
8677         /* Try to restore the config */
8678         if (config->mode_changed &&
8679             intel_set_mode(save_set.crtc, save_set.mode,
8680                            save_set.x, save_set.y, save_set.fb))
8681                 DRM_ERROR("failed to restore config after modeset failure\n");
8682
8683 out_config:
8684         intel_set_config_free(config);
8685         return ret;
8686 }
8687
8688 static const struct drm_crtc_funcs intel_crtc_funcs = {
8689         .cursor_set = intel_crtc_cursor_set,
8690         .cursor_move = intel_crtc_cursor_move,
8691         .gamma_set = intel_crtc_gamma_set,
8692         .set_config = intel_crtc_set_config,
8693         .destroy = intel_crtc_destroy,
8694         .page_flip = intel_crtc_page_flip,
8695 };
8696
8697 static void intel_cpu_pll_init(struct drm_device *dev)
8698 {
8699         if (HAS_DDI(dev))
8700                 intel_ddi_pll_init(dev);
8701 }
8702
8703 static void intel_pch_pll_init(struct drm_device *dev)
8704 {
8705         drm_i915_private_t *dev_priv = dev->dev_private;
8706         int i;
8707
8708         if (dev_priv->num_pch_pll == 0) {
8709                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8710                 return;
8711         }
8712
8713         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8714                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8715                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8716                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8717         }
8718 }
8719
8720 static void intel_crtc_init(struct drm_device *dev, int pipe)
8721 {
8722         drm_i915_private_t *dev_priv = dev->dev_private;
8723         struct intel_crtc *intel_crtc;
8724         int i;
8725
8726         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8727         if (intel_crtc == NULL)
8728                 return;
8729
8730         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8731
8732         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8733         for (i = 0; i < 256; i++) {
8734                 intel_crtc->lut_r[i] = i;
8735                 intel_crtc->lut_g[i] = i;
8736                 intel_crtc->lut_b[i] = i;
8737         }
8738
8739         /* Swap pipes & planes for FBC on pre-965 */
8740         intel_crtc->pipe = pipe;
8741         intel_crtc->plane = pipe;
8742         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8743                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8744                 intel_crtc->plane = !pipe;
8745         }
8746
8747         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8748                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8749         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8750         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8751
8752         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8753 }
8754
8755 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8756                                 struct drm_file *file)
8757 {
8758         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8759         struct drm_mode_object *drmmode_obj;
8760         struct intel_crtc *crtc;
8761
8762         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8763                 return -ENODEV;
8764
8765         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8766                         DRM_MODE_OBJECT_CRTC);
8767
8768         if (!drmmode_obj) {
8769                 DRM_ERROR("no such CRTC id\n");
8770                 return -EINVAL;
8771         }
8772
8773         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8774         pipe_from_crtc_id->pipe = crtc->pipe;
8775
8776         return 0;
8777 }
8778
8779 static int intel_encoder_clones(struct intel_encoder *encoder)
8780 {
8781         struct drm_device *dev = encoder->base.dev;
8782         struct intel_encoder *source_encoder;
8783         int index_mask = 0;
8784         int entry = 0;
8785
8786         list_for_each_entry(source_encoder,
8787                             &dev->mode_config.encoder_list, base.head) {
8788
8789                 if (encoder == source_encoder)
8790                         index_mask |= (1 << entry);
8791
8792                 /* Intel hw has only one MUX where enocoders could be cloned. */
8793                 if (encoder->cloneable && source_encoder->cloneable)
8794                         index_mask |= (1 << entry);
8795
8796                 entry++;
8797         }
8798
8799         return index_mask;
8800 }
8801
8802 static bool has_edp_a(struct drm_device *dev)
8803 {
8804         struct drm_i915_private *dev_priv = dev->dev_private;
8805
8806         if (!IS_MOBILE(dev))
8807                 return false;
8808
8809         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8810                 return false;
8811
8812         if (IS_GEN5(dev) &&
8813             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8814                 return false;
8815
8816         return true;
8817 }
8818
8819 static void intel_setup_outputs(struct drm_device *dev)
8820 {
8821         struct drm_i915_private *dev_priv = dev->dev_private;
8822         struct intel_encoder *encoder;
8823         bool dpd_is_edp = false;
8824         bool has_lvds;
8825
8826         has_lvds = intel_lvds_init(dev);
8827         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8828                 /* disable the panel fitter on everything but LVDS */
8829                 I915_WRITE(PFIT_CONTROL, 0);
8830         }
8831
8832         if (!IS_ULT(dev))
8833                 intel_crt_init(dev);
8834
8835         if (HAS_DDI(dev)) {
8836                 int found;
8837
8838                 /* Haswell uses DDI functions to detect digital outputs */
8839                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8840                 /* DDI A only supports eDP */
8841                 if (found)
8842                         intel_ddi_init(dev, PORT_A);
8843
8844                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8845                  * register */
8846                 found = I915_READ(SFUSE_STRAP);
8847
8848                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8849                         intel_ddi_init(dev, PORT_B);
8850                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8851                         intel_ddi_init(dev, PORT_C);
8852                 if (found & SFUSE_STRAP_DDID_DETECTED)
8853                         intel_ddi_init(dev, PORT_D);
8854         } else if (HAS_PCH_SPLIT(dev)) {
8855                 int found;
8856                 dpd_is_edp = intel_dpd_is_edp(dev);
8857
8858                 if (has_edp_a(dev))
8859                         intel_dp_init(dev, DP_A, PORT_A);
8860
8861                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8862                         /* PCH SDVOB multiplex with HDMIB */
8863                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8864                         if (!found)
8865                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8866                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8867                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8868                 }
8869
8870                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8871                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8872
8873                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8874                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8875
8876                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8877                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8878
8879                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8880                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8881         } else if (IS_VALLEYVIEW(dev)) {
8882                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8883                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8884                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8885
8886                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8887                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8888                                         PORT_B);
8889                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8890                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8891                 }
8892         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8893                 bool found = false;
8894
8895                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8896                         DRM_DEBUG_KMS("probing SDVOB\n");
8897                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8898                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8899                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8900                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8901                         }
8902
8903                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
8904                                 intel_dp_init(dev, DP_B, PORT_B);
8905                 }
8906
8907                 /* Before G4X SDVOC doesn't have its own detect register */
8908
8909                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8910                         DRM_DEBUG_KMS("probing SDVOC\n");
8911                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8912                 }
8913
8914                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8915
8916                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8917                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8918                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8919                         }
8920                         if (SUPPORTS_INTEGRATED_DP(dev))
8921                                 intel_dp_init(dev, DP_C, PORT_C);
8922                 }
8923
8924                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8925                     (I915_READ(DP_D) & DP_DETECTED))
8926                         intel_dp_init(dev, DP_D, PORT_D);
8927         } else if (IS_GEN2(dev))
8928                 intel_dvo_init(dev);
8929
8930         if (SUPPORTS_TV(dev))
8931                 intel_tv_init(dev);
8932
8933         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8934                 encoder->base.possible_crtcs = encoder->crtc_mask;
8935                 encoder->base.possible_clones =
8936                         intel_encoder_clones(encoder);
8937         }
8938
8939         intel_init_pch_refclk(dev);
8940
8941         drm_helper_move_panel_connectors_to_head(dev);
8942 }
8943
8944 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8945 {
8946         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8947
8948         drm_framebuffer_cleanup(fb);
8949         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8950
8951         kfree(intel_fb);
8952 }
8953
8954 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8955                                                 struct drm_file *file,
8956                                                 unsigned int *handle)
8957 {
8958         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8959         struct drm_i915_gem_object *obj = intel_fb->obj;
8960
8961         return drm_gem_handle_create(file, &obj->base, handle);
8962 }
8963
8964 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8965         .destroy = intel_user_framebuffer_destroy,
8966         .create_handle = intel_user_framebuffer_create_handle,
8967 };
8968
8969 int intel_framebuffer_init(struct drm_device *dev,
8970                            struct intel_framebuffer *intel_fb,
8971                            struct drm_mode_fb_cmd2 *mode_cmd,
8972                            struct drm_i915_gem_object *obj)
8973 {
8974         int ret;
8975
8976         if (obj->tiling_mode == I915_TILING_Y) {
8977                 DRM_DEBUG("hardware does not support tiling Y\n");
8978                 return -EINVAL;
8979         }
8980
8981         if (mode_cmd->pitches[0] & 63) {
8982                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8983                           mode_cmd->pitches[0]);
8984                 return -EINVAL;
8985         }
8986
8987         /* FIXME <= Gen4 stride limits are bit unclear */
8988         if (mode_cmd->pitches[0] > 32768) {
8989                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8990                           mode_cmd->pitches[0]);
8991                 return -EINVAL;
8992         }
8993
8994         if (obj->tiling_mode != I915_TILING_NONE &&
8995             mode_cmd->pitches[0] != obj->stride) {
8996                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8997                           mode_cmd->pitches[0], obj->stride);
8998                 return -EINVAL;
8999         }
9000
9001         /* Reject formats not supported by any plane early. */
9002         switch (mode_cmd->pixel_format) {
9003         case DRM_FORMAT_C8:
9004         case DRM_FORMAT_RGB565:
9005         case DRM_FORMAT_XRGB8888:
9006         case DRM_FORMAT_ARGB8888:
9007                 break;
9008         case DRM_FORMAT_XRGB1555:
9009         case DRM_FORMAT_ARGB1555:
9010                 if (INTEL_INFO(dev)->gen > 3) {
9011                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9012                         return -EINVAL;
9013                 }
9014                 break;
9015         case DRM_FORMAT_XBGR8888:
9016         case DRM_FORMAT_ABGR8888:
9017         case DRM_FORMAT_XRGB2101010:
9018         case DRM_FORMAT_ARGB2101010:
9019         case DRM_FORMAT_XBGR2101010:
9020         case DRM_FORMAT_ABGR2101010:
9021                 if (INTEL_INFO(dev)->gen < 4) {
9022                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9023                         return -EINVAL;
9024                 }
9025                 break;
9026         case DRM_FORMAT_YUYV:
9027         case DRM_FORMAT_UYVY:
9028         case DRM_FORMAT_YVYU:
9029         case DRM_FORMAT_VYUY:
9030                 if (INTEL_INFO(dev)->gen < 5) {
9031                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9032                         return -EINVAL;
9033                 }
9034                 break;
9035         default:
9036                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
9037                 return -EINVAL;
9038         }
9039
9040         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9041         if (mode_cmd->offsets[0] != 0)
9042                 return -EINVAL;
9043
9044         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9045         intel_fb->obj = obj;
9046
9047         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9048         if (ret) {
9049                 DRM_ERROR("framebuffer init failed %d\n", ret);
9050                 return ret;
9051         }
9052
9053         return 0;
9054 }
9055
9056 static struct drm_framebuffer *
9057 intel_user_framebuffer_create(struct drm_device *dev,
9058                               struct drm_file *filp,
9059                               struct drm_mode_fb_cmd2 *mode_cmd)
9060 {
9061         struct drm_i915_gem_object *obj;
9062
9063         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9064                                                 mode_cmd->handles[0]));
9065         if (&obj->base == NULL)
9066                 return ERR_PTR(-ENOENT);
9067
9068         return intel_framebuffer_create(dev, mode_cmd, obj);
9069 }
9070
9071 static const struct drm_mode_config_funcs intel_mode_funcs = {
9072         .fb_create = intel_user_framebuffer_create,
9073         .output_poll_changed = intel_fb_output_poll_changed,
9074 };
9075
9076 /* Set up chip specific display functions */
9077 static void intel_init_display(struct drm_device *dev)
9078 {
9079         struct drm_i915_private *dev_priv = dev->dev_private;
9080
9081         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9082                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9083         else if (IS_VALLEYVIEW(dev))
9084                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9085         else if (IS_PINEVIEW(dev))
9086                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9087         else
9088                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9089
9090         if (HAS_DDI(dev)) {
9091                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9092                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9093                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9094                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9095                 dev_priv->display.off = haswell_crtc_off;
9096                 dev_priv->display.update_plane = ironlake_update_plane;
9097         } else if (HAS_PCH_SPLIT(dev)) {
9098                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9099                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9100                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9101                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9102                 dev_priv->display.off = ironlake_crtc_off;
9103                 dev_priv->display.update_plane = ironlake_update_plane;
9104         } else if (IS_VALLEYVIEW(dev)) {
9105                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9106                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9107                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9108                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9109                 dev_priv->display.off = i9xx_crtc_off;
9110                 dev_priv->display.update_plane = i9xx_update_plane;
9111         } else {
9112                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9113                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9114                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9115                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9116                 dev_priv->display.off = i9xx_crtc_off;
9117                 dev_priv->display.update_plane = i9xx_update_plane;
9118         }
9119
9120         /* Returns the core display clock speed */
9121         if (IS_VALLEYVIEW(dev))
9122                 dev_priv->display.get_display_clock_speed =
9123                         valleyview_get_display_clock_speed;
9124         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9125                 dev_priv->display.get_display_clock_speed =
9126                         i945_get_display_clock_speed;
9127         else if (IS_I915G(dev))
9128                 dev_priv->display.get_display_clock_speed =
9129                         i915_get_display_clock_speed;
9130         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9131                 dev_priv->display.get_display_clock_speed =
9132                         i9xx_misc_get_display_clock_speed;
9133         else if (IS_I915GM(dev))
9134                 dev_priv->display.get_display_clock_speed =
9135                         i915gm_get_display_clock_speed;
9136         else if (IS_I865G(dev))
9137                 dev_priv->display.get_display_clock_speed =
9138                         i865_get_display_clock_speed;
9139         else if (IS_I85X(dev))
9140                 dev_priv->display.get_display_clock_speed =
9141                         i855_get_display_clock_speed;
9142         else /* 852, 830 */
9143                 dev_priv->display.get_display_clock_speed =
9144                         i830_get_display_clock_speed;
9145
9146         if (HAS_PCH_SPLIT(dev)) {
9147                 if (IS_GEN5(dev)) {
9148                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9149                         dev_priv->display.write_eld = ironlake_write_eld;
9150                 } else if (IS_GEN6(dev)) {
9151                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9152                         dev_priv->display.write_eld = ironlake_write_eld;
9153                 } else if (IS_IVYBRIDGE(dev)) {
9154                         /* FIXME: detect B0+ stepping and use auto training */
9155                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9156                         dev_priv->display.write_eld = ironlake_write_eld;
9157                         dev_priv->display.modeset_global_resources =
9158                                 ivb_modeset_global_resources;
9159                 } else if (IS_HASWELL(dev)) {
9160                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9161                         dev_priv->display.write_eld = haswell_write_eld;
9162                         dev_priv->display.modeset_global_resources =
9163                                 haswell_modeset_global_resources;
9164                 }
9165         } else if (IS_G4X(dev)) {
9166                 dev_priv->display.write_eld = g4x_write_eld;
9167         }
9168
9169         /* Default just returns -ENODEV to indicate unsupported */
9170         dev_priv->display.queue_flip = intel_default_queue_flip;
9171
9172         switch (INTEL_INFO(dev)->gen) {
9173         case 2:
9174                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9175                 break;
9176
9177         case 3:
9178                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9179                 break;
9180
9181         case 4:
9182         case 5:
9183                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9184                 break;
9185
9186         case 6:
9187                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9188                 break;
9189         case 7:
9190                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9191                 break;
9192         }
9193 }
9194
9195 /*
9196  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9197  * resume, or other times.  This quirk makes sure that's the case for
9198  * affected systems.
9199  */
9200 static void quirk_pipea_force(struct drm_device *dev)
9201 {
9202         struct drm_i915_private *dev_priv = dev->dev_private;
9203
9204         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9205         DRM_INFO("applying pipe a force quirk\n");
9206 }
9207
9208 /*
9209  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9210  */
9211 static void quirk_ssc_force_disable(struct drm_device *dev)
9212 {
9213         struct drm_i915_private *dev_priv = dev->dev_private;
9214         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9215         DRM_INFO("applying lvds SSC disable quirk\n");
9216 }
9217
9218 /*
9219  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9220  * brightness value
9221  */
9222 static void quirk_invert_brightness(struct drm_device *dev)
9223 {
9224         struct drm_i915_private *dev_priv = dev->dev_private;
9225         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9226         DRM_INFO("applying inverted panel brightness quirk\n");
9227 }
9228
9229 struct intel_quirk {
9230         int device;
9231         int subsystem_vendor;
9232         int subsystem_device;
9233         void (*hook)(struct drm_device *dev);
9234 };
9235
9236 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9237 struct intel_dmi_quirk {
9238         void (*hook)(struct drm_device *dev);
9239         const struct dmi_system_id (*dmi_id_list)[];
9240 };
9241
9242 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9243 {
9244         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9245         return 1;
9246 }
9247
9248 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9249         {
9250                 .dmi_id_list = &(const struct dmi_system_id[]) {
9251                         {
9252                                 .callback = intel_dmi_reverse_brightness,
9253                                 .ident = "NCR Corporation",
9254                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9255                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9256                                 },
9257                         },
9258                         { }  /* terminating entry */
9259                 },
9260                 .hook = quirk_invert_brightness,
9261         },
9262 };
9263
9264 static struct intel_quirk intel_quirks[] = {
9265         /* HP Mini needs pipe A force quirk (LP: #322104) */
9266         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9267
9268         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9269         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9270
9271         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9272         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9273
9274         /* 830/845 need to leave pipe A & dpll A up */
9275         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9276         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9277
9278         /* Lenovo U160 cannot use SSC on LVDS */
9279         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9280
9281         /* Sony Vaio Y cannot use SSC on LVDS */
9282         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9283
9284         /* Acer Aspire 5734Z must invert backlight brightness */
9285         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9286
9287         /* Acer/eMachines G725 */
9288         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9289
9290         /* Acer/eMachines e725 */
9291         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9292
9293         /* Acer/Packard Bell NCL20 */
9294         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9295
9296         /* Acer Aspire 4736Z */
9297         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9298 };
9299
9300 static void intel_init_quirks(struct drm_device *dev)
9301 {
9302         struct pci_dev *d = dev->pdev;
9303         int i;
9304
9305         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9306                 struct intel_quirk *q = &intel_quirks[i];
9307
9308                 if (d->device == q->device &&
9309                     (d->subsystem_vendor == q->subsystem_vendor ||
9310                      q->subsystem_vendor == PCI_ANY_ID) &&
9311                     (d->subsystem_device == q->subsystem_device ||
9312                      q->subsystem_device == PCI_ANY_ID))
9313                         q->hook(dev);
9314         }
9315         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9316                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9317                         intel_dmi_quirks[i].hook(dev);
9318         }
9319 }
9320
9321 /* Disable the VGA plane that we never use */
9322 static void i915_disable_vga(struct drm_device *dev)
9323 {
9324         struct drm_i915_private *dev_priv = dev->dev_private;
9325         u8 sr1;
9326         u32 vga_reg = i915_vgacntrl_reg(dev);
9327
9328         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9329         outb(SR01, VGA_SR_INDEX);
9330         sr1 = inb(VGA_SR_DATA);
9331         outb(sr1 | 1<<5, VGA_SR_DATA);
9332         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9333         udelay(300);
9334
9335         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9336         POSTING_READ(vga_reg);
9337 }
9338
9339 void intel_modeset_init_hw(struct drm_device *dev)
9340 {
9341         intel_init_power_well(dev);
9342
9343         intel_prepare_ddi(dev);
9344
9345         intel_init_clock_gating(dev);
9346
9347         mutex_lock(&dev->struct_mutex);
9348         intel_enable_gt_powersave(dev);
9349         mutex_unlock(&dev->struct_mutex);
9350 }
9351
9352 void intel_modeset_suspend_hw(struct drm_device *dev)
9353 {
9354         intel_suspend_hw(dev);
9355 }
9356
9357 void intel_modeset_init(struct drm_device *dev)
9358 {
9359         struct drm_i915_private *dev_priv = dev->dev_private;
9360         int i, j, ret;
9361
9362         drm_mode_config_init(dev);
9363
9364         dev->mode_config.min_width = 0;
9365         dev->mode_config.min_height = 0;
9366
9367         dev->mode_config.preferred_depth = 24;
9368         dev->mode_config.prefer_shadow = 1;
9369
9370         dev->mode_config.funcs = &intel_mode_funcs;
9371
9372         intel_init_quirks(dev);
9373
9374         intel_init_pm(dev);
9375
9376         if (INTEL_INFO(dev)->num_pipes == 0)
9377                 return;
9378
9379         intel_init_display(dev);
9380
9381         if (IS_GEN2(dev)) {
9382                 dev->mode_config.max_width = 2048;
9383                 dev->mode_config.max_height = 2048;
9384         } else if (IS_GEN3(dev)) {
9385                 dev->mode_config.max_width = 4096;
9386                 dev->mode_config.max_height = 4096;
9387         } else {
9388                 dev->mode_config.max_width = 8192;
9389                 dev->mode_config.max_height = 8192;
9390         }
9391         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9392
9393         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9394                       INTEL_INFO(dev)->num_pipes,
9395                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9396
9397         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9398                 intel_crtc_init(dev, i);
9399                 for (j = 0; j < dev_priv->num_plane; j++) {
9400                         ret = intel_plane_init(dev, i, j);
9401                         if (ret)
9402                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9403                                               pipe_name(i), sprite_name(i, j), ret);
9404                 }
9405         }
9406
9407         intel_cpu_pll_init(dev);
9408         intel_pch_pll_init(dev);
9409
9410         /* Just disable it once at startup */
9411         i915_disable_vga(dev);
9412         intel_setup_outputs(dev);
9413
9414         /* Just in case the BIOS is doing something questionable. */
9415         intel_disable_fbc(dev);
9416 }
9417
9418 static void
9419 intel_connector_break_all_links(struct intel_connector *connector)
9420 {
9421         connector->base.dpms = DRM_MODE_DPMS_OFF;
9422         connector->base.encoder = NULL;
9423         connector->encoder->connectors_active = false;
9424         connector->encoder->base.crtc = NULL;
9425 }
9426
9427 static void intel_enable_pipe_a(struct drm_device *dev)
9428 {
9429         struct intel_connector *connector;
9430         struct drm_connector *crt = NULL;
9431         struct intel_load_detect_pipe load_detect_temp;
9432
9433         /* We can't just switch on the pipe A, we need to set things up with a
9434          * proper mode and output configuration. As a gross hack, enable pipe A
9435          * by enabling the load detect pipe once. */
9436         list_for_each_entry(connector,
9437                             &dev->mode_config.connector_list,
9438                             base.head) {
9439                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9440                         crt = &connector->base;
9441                         break;
9442                 }
9443         }
9444
9445         if (!crt)
9446                 return;
9447
9448         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9449                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9450
9451
9452 }
9453
9454 static bool
9455 intel_check_plane_mapping(struct intel_crtc *crtc)
9456 {
9457         struct drm_device *dev = crtc->base.dev;
9458         struct drm_i915_private *dev_priv = dev->dev_private;
9459         u32 reg, val;
9460
9461         if (INTEL_INFO(dev)->num_pipes == 1)
9462                 return true;
9463
9464         reg = DSPCNTR(!crtc->plane);
9465         val = I915_READ(reg);
9466
9467         if ((val & DISPLAY_PLANE_ENABLE) &&
9468             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9469                 return false;
9470
9471         return true;
9472 }
9473
9474 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9475 {
9476         struct drm_device *dev = crtc->base.dev;
9477         struct drm_i915_private *dev_priv = dev->dev_private;
9478         u32 reg;
9479
9480         /* Clear any frame start delays used for debugging left by the BIOS */
9481         reg = PIPECONF(crtc->config.cpu_transcoder);
9482         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9483
9484         /* We need to sanitize the plane -> pipe mapping first because this will
9485          * disable the crtc (and hence change the state) if it is wrong. Note
9486          * that gen4+ has a fixed plane -> pipe mapping.  */
9487         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9488                 struct intel_connector *connector;
9489                 bool plane;
9490
9491                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9492                               crtc->base.base.id);
9493
9494                 /* Pipe has the wrong plane attached and the plane is active.
9495                  * Temporarily change the plane mapping and disable everything
9496                  * ...  */
9497                 plane = crtc->plane;
9498                 crtc->plane = !plane;
9499                 dev_priv->display.crtc_disable(&crtc->base);
9500                 crtc->plane = plane;
9501
9502                 /* ... and break all links. */
9503                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9504                                     base.head) {
9505                         if (connector->encoder->base.crtc != &crtc->base)
9506                                 continue;
9507
9508                         intel_connector_break_all_links(connector);
9509                 }
9510
9511                 WARN_ON(crtc->active);
9512                 crtc->base.enabled = false;
9513         }
9514
9515         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9516             crtc->pipe == PIPE_A && !crtc->active) {
9517                 /* BIOS forgot to enable pipe A, this mostly happens after
9518                  * resume. Force-enable the pipe to fix this, the update_dpms
9519                  * call below we restore the pipe to the right state, but leave
9520                  * the required bits on. */
9521                 intel_enable_pipe_a(dev);
9522         }
9523
9524         /* Adjust the state of the output pipe according to whether we
9525          * have active connectors/encoders. */
9526         intel_crtc_update_dpms(&crtc->base);
9527
9528         if (crtc->active != crtc->base.enabled) {
9529                 struct intel_encoder *encoder;
9530
9531                 /* This can happen either due to bugs in the get_hw_state
9532                  * functions or because the pipe is force-enabled due to the
9533                  * pipe A quirk. */
9534                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9535                               crtc->base.base.id,
9536                               crtc->base.enabled ? "enabled" : "disabled",
9537                               crtc->active ? "enabled" : "disabled");
9538
9539                 crtc->base.enabled = crtc->active;
9540
9541                 /* Because we only establish the connector -> encoder ->
9542                  * crtc links if something is active, this means the
9543                  * crtc is now deactivated. Break the links. connector
9544                  * -> encoder links are only establish when things are
9545                  *  actually up, hence no need to break them. */
9546                 WARN_ON(crtc->active);
9547
9548                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9549                         WARN_ON(encoder->connectors_active);
9550                         encoder->base.crtc = NULL;
9551                 }
9552         }
9553 }
9554
9555 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9556 {
9557         struct intel_connector *connector;
9558         struct drm_device *dev = encoder->base.dev;
9559
9560         /* We need to check both for a crtc link (meaning that the
9561          * encoder is active and trying to read from a pipe) and the
9562          * pipe itself being active. */
9563         bool has_active_crtc = encoder->base.crtc &&
9564                 to_intel_crtc(encoder->base.crtc)->active;
9565
9566         if (encoder->connectors_active && !has_active_crtc) {
9567                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9568                               encoder->base.base.id,
9569                               drm_get_encoder_name(&encoder->base));
9570
9571                 /* Connector is active, but has no active pipe. This is
9572                  * fallout from our resume register restoring. Disable
9573                  * the encoder manually again. */
9574                 if (encoder->base.crtc) {
9575                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9576                                       encoder->base.base.id,
9577                                       drm_get_encoder_name(&encoder->base));
9578                         encoder->disable(encoder);
9579                 }
9580
9581                 /* Inconsistent output/port/pipe state happens presumably due to
9582                  * a bug in one of the get_hw_state functions. Or someplace else
9583                  * in our code, like the register restore mess on resume. Clamp
9584                  * things to off as a safer default. */
9585                 list_for_each_entry(connector,
9586                                     &dev->mode_config.connector_list,
9587                                     base.head) {
9588                         if (connector->encoder != encoder)
9589                                 continue;
9590
9591                         intel_connector_break_all_links(connector);
9592                 }
9593         }
9594         /* Enabled encoders without active connectors will be fixed in
9595          * the crtc fixup. */
9596 }
9597
9598 void i915_redisable_vga(struct drm_device *dev)
9599 {
9600         struct drm_i915_private *dev_priv = dev->dev_private;
9601         u32 vga_reg = i915_vgacntrl_reg(dev);
9602
9603         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9604                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9605                 i915_disable_vga(dev);
9606         }
9607 }
9608
9609 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9610  * and i915 state tracking structures. */
9611 void intel_modeset_setup_hw_state(struct drm_device *dev,
9612                                   bool force_restore)
9613 {
9614         struct drm_i915_private *dev_priv = dev->dev_private;
9615         enum pipe pipe;
9616         struct drm_plane *plane;
9617         struct intel_crtc *crtc;
9618         struct intel_encoder *encoder;
9619         struct intel_connector *connector;
9620
9621         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9622                             base.head) {
9623                 memset(&crtc->config, 0, sizeof(crtc->config));
9624
9625                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9626                                                                  &crtc->config);
9627
9628                 crtc->base.enabled = crtc->active;
9629
9630                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9631                               crtc->base.base.id,
9632                               crtc->active ? "enabled" : "disabled");
9633         }
9634
9635         if (HAS_DDI(dev))
9636                 intel_ddi_setup_hw_pll_state(dev);
9637
9638         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9639                             base.head) {
9640                 pipe = 0;
9641
9642                 if (encoder->get_hw_state(encoder, &pipe)) {
9643                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9644                         encoder->base.crtc = &crtc->base;
9645                         if (encoder->get_config)
9646                                 encoder->get_config(encoder, &crtc->config);
9647                 } else {
9648                         encoder->base.crtc = NULL;
9649                 }
9650
9651                 encoder->connectors_active = false;
9652                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9653                               encoder->base.base.id,
9654                               drm_get_encoder_name(&encoder->base),
9655                               encoder->base.crtc ? "enabled" : "disabled",
9656                               pipe);
9657         }
9658
9659         list_for_each_entry(connector, &dev->mode_config.connector_list,
9660                             base.head) {
9661                 if (connector->get_hw_state(connector)) {
9662                         connector->base.dpms = DRM_MODE_DPMS_ON;
9663                         connector->encoder->connectors_active = true;
9664                         connector->base.encoder = &connector->encoder->base;
9665                 } else {
9666                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9667                         connector->base.encoder = NULL;
9668                 }
9669                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9670                               connector->base.base.id,
9671                               drm_get_connector_name(&connector->base),
9672                               connector->base.encoder ? "enabled" : "disabled");
9673         }
9674
9675         /* HW state is read out, now we need to sanitize this mess. */
9676         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9677                             base.head) {
9678                 intel_sanitize_encoder(encoder);
9679         }
9680
9681         for_each_pipe(pipe) {
9682                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9683                 intel_sanitize_crtc(crtc);
9684                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9685         }
9686
9687         if (force_restore) {
9688                 /*
9689                  * We need to use raw interfaces for restoring state to avoid
9690                  * checking (bogus) intermediate states.
9691                  */
9692                 for_each_pipe(pipe) {
9693                         struct drm_crtc *crtc =
9694                                 dev_priv->pipe_to_crtc_mapping[pipe];
9695
9696                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9697                                          crtc->fb);
9698                 }
9699                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9700                         intel_plane_restore(plane);
9701
9702                 i915_redisable_vga(dev);
9703         } else {
9704                 intel_modeset_update_staged_output_state(dev);
9705         }
9706
9707         intel_modeset_check_state(dev);
9708
9709         drm_mode_config_reset(dev);
9710 }
9711
9712 void intel_modeset_gem_init(struct drm_device *dev)
9713 {
9714         intel_modeset_init_hw(dev);
9715
9716         intel_setup_overlay(dev);
9717
9718         intel_modeset_setup_hw_state(dev, false);
9719 }
9720
9721 void intel_modeset_cleanup(struct drm_device *dev)
9722 {
9723         struct drm_i915_private *dev_priv = dev->dev_private;
9724         struct drm_crtc *crtc;
9725         struct intel_crtc *intel_crtc;
9726
9727         /*
9728          * Interrupts and polling as the first thing to avoid creating havoc.
9729          * Too much stuff here (turning of rps, connectors, ...) would
9730          * experience fancy races otherwise.
9731          */
9732         drm_irq_uninstall(dev);
9733         cancel_work_sync(&dev_priv->hotplug_work);
9734         /*
9735          * Due to the hpd irq storm handling the hotplug work can re-arm the
9736          * poll handlers. Hence disable polling after hpd handling is shut down.
9737          */
9738         drm_kms_helper_poll_fini(dev);
9739
9740         mutex_lock(&dev->struct_mutex);
9741
9742         intel_unregister_dsm_handler();
9743
9744         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9745                 /* Skip inactive CRTCs */
9746                 if (!crtc->fb)
9747                         continue;
9748
9749                 intel_crtc = to_intel_crtc(crtc);
9750                 intel_increase_pllclock(crtc);
9751         }
9752
9753         intel_disable_fbc(dev);
9754
9755         intel_disable_gt_powersave(dev);
9756
9757         ironlake_teardown_rc6(dev);
9758
9759         mutex_unlock(&dev->struct_mutex);
9760
9761         /* flush any delayed tasks or pending work */
9762         flush_scheduled_work();
9763
9764         /* destroy backlight, if any, before the connectors */
9765         intel_panel_destroy_backlight(dev);
9766
9767         drm_mode_config_cleanup(dev);
9768
9769         intel_cleanup_overlay(dev);
9770 }
9771
9772 /*
9773  * Return which encoder is currently attached for connector.
9774  */
9775 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9776 {
9777         return &intel_attached_encoder(connector)->base;
9778 }
9779
9780 void intel_connector_attach_encoder(struct intel_connector *connector,
9781                                     struct intel_encoder *encoder)
9782 {
9783         connector->encoder = encoder;
9784         drm_mode_connector_attach_encoder(&connector->base,
9785                                           &encoder->base);
9786 }
9787
9788 /*
9789  * set vga decode state - true == enable VGA decode
9790  */
9791 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9792 {
9793         struct drm_i915_private *dev_priv = dev->dev_private;
9794         u16 gmch_ctrl;
9795
9796         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9797         if (state)
9798                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9799         else
9800                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9801         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9802         return 0;
9803 }
9804
9805 #ifdef CONFIG_DEBUG_FS
9806 #include <linux/seq_file.h>
9807
9808 struct intel_display_error_state {
9809
9810         u32 power_well_driver;
9811
9812         struct intel_cursor_error_state {
9813                 u32 control;
9814                 u32 position;
9815                 u32 base;
9816                 u32 size;
9817         } cursor[I915_MAX_PIPES];
9818
9819         struct intel_pipe_error_state {
9820                 enum transcoder cpu_transcoder;
9821                 u32 conf;
9822                 u32 source;
9823
9824                 u32 htotal;
9825                 u32 hblank;
9826                 u32 hsync;
9827                 u32 vtotal;
9828                 u32 vblank;
9829                 u32 vsync;
9830         } pipe[I915_MAX_PIPES];
9831
9832         struct intel_plane_error_state {
9833                 u32 control;
9834                 u32 stride;
9835                 u32 size;
9836                 u32 pos;
9837                 u32 addr;
9838                 u32 surface;
9839                 u32 tile_offset;
9840         } plane[I915_MAX_PIPES];
9841 };
9842
9843 struct intel_display_error_state *
9844 intel_display_capture_error_state(struct drm_device *dev)
9845 {
9846         drm_i915_private_t *dev_priv = dev->dev_private;
9847         struct intel_display_error_state *error;
9848         enum transcoder cpu_transcoder;
9849         int i;
9850
9851         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9852         if (error == NULL)
9853                 return NULL;
9854
9855         if (HAS_POWER_WELL(dev))
9856                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9857
9858         for_each_pipe(i) {
9859                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9860                 error->pipe[i].cpu_transcoder = cpu_transcoder;
9861
9862                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9863                         error->cursor[i].control = I915_READ(CURCNTR(i));
9864                         error->cursor[i].position = I915_READ(CURPOS(i));
9865                         error->cursor[i].base = I915_READ(CURBASE(i));
9866                 } else {
9867                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9868                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9869                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9870                 }
9871
9872                 error->plane[i].control = I915_READ(DSPCNTR(i));
9873                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9874                 if (INTEL_INFO(dev)->gen <= 3) {
9875                         error->plane[i].size = I915_READ(DSPSIZE(i));
9876                         error->plane[i].pos = I915_READ(DSPPOS(i));
9877                 }
9878                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9879                         error->plane[i].addr = I915_READ(DSPADDR(i));
9880                 if (INTEL_INFO(dev)->gen >= 4) {
9881                         error->plane[i].surface = I915_READ(DSPSURF(i));
9882                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9883                 }
9884
9885                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9886                 error->pipe[i].source = I915_READ(PIPESRC(i));
9887                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9888                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9889                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9890                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9891                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9892                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9893         }
9894
9895         /* In the code above we read the registers without checking if the power
9896          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9897          * prevent the next I915_WRITE from detecting it and printing an error
9898          * message. */
9899         if (HAS_POWER_WELL(dev))
9900                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9901
9902         return error;
9903 }
9904
9905 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9906
9907 void
9908 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9909                                 struct drm_device *dev,
9910                                 struct intel_display_error_state *error)
9911 {
9912         int i;
9913
9914         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9915         if (HAS_POWER_WELL(dev))
9916                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9917                            error->power_well_driver);
9918         for_each_pipe(i) {
9919                 err_printf(m, "Pipe [%d]:\n", i);
9920                 err_printf(m, "  CPU transcoder: %c\n",
9921                            transcoder_name(error->pipe[i].cpu_transcoder));
9922                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9923                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9924                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9925                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9926                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9927                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9928                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9929                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9930
9931                 err_printf(m, "Plane [%d]:\n", i);
9932                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9933                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9934                 if (INTEL_INFO(dev)->gen <= 3) {
9935                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9936                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
9937                 }
9938                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9939                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9940                 if (INTEL_INFO(dev)->gen >= 4) {
9941                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9942                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9943                 }
9944
9945                 err_printf(m, "Cursor [%d]:\n", i);
9946                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9947                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
9948                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9949         }
9950 }
9951 #endif