drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 static void assert_pll(struct drm_i915_private *dev_priv,
 896                        enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 911
 912 /* For ILK+ */
 913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 914                            struct intel_pch_pll *pll,
 915                            struct intel_crtc *crtc,
 916                            bool state)
 917 {
 918         u32 val;
 919         bool cur_state;
 920
 921         if (HAS_PCH_LPT(dev_priv->dev)) {
 922                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 923                 return;
 924         }
 925
 926         if (WARN (!pll,
 927                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 928                 return;
 929
 930         val = I915_READ(pll->pll_reg);
 931         cur_state = !!(val & DPLL_VCO_ENABLE);
 932         WARN(cur_state != state,
 933              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 934              pll->pll_reg, state_string(state), state_string(cur_state), val);
 935
 936         /* Make sure the selected PLL is correctly attached to the transcoder */
 937         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 938                 u32 pch_dpll;
 939
 940                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 941                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 942                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 943                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 944                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 945                         cur_state = !!(val >> (4*crtc->pipe + 3));
 946                         WARN(cur_state != state,
 947                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 948                              pll->pll_reg == _PCH_DPLL_B,
 949                              state_string(state),
 950                              pipe_name(crtc->pipe),
 951                              val);
 952                 }
 953         }
 954 }
 955 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 956 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 957
 958 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 959                           enum pipe pipe, bool state)
 960 {
 961         int reg;
 962         u32 val;
 963         bool cur_state;
 964         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 965                                                                       pipe);
 966
 967         if (HAS_DDI(dev_priv->dev)) {
 968                 /* DDI does not have a specific FDI_TX register */
 969                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 970                 val = I915_READ(reg);
 971                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 972         } else {
 973                 reg = FDI_TX_CTL(pipe);
 974                 val = I915_READ(reg);
 975                 cur_state = !!(val & FDI_TX_ENABLE);
 976         }
 977         WARN(cur_state != state,
 978              "FDI TX state assertion failure (expected %s, current %s)\n",
 979              state_string(state), state_string(cur_state));
 980 }
 981 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 982 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 983
 984 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 985                           enum pipe pipe, bool state)
 986 {
 987         int reg;
 988         u32 val;
 989         bool cur_state;
 990
 991         reg = FDI_RX_CTL(pipe);
 992         val = I915_READ(reg);
 993         cur_state = !!(val & FDI_RX_ENABLE);
 994         WARN(cur_state != state,
 995              "FDI RX state assertion failure (expected %s, current %s)\n",
 996              state_string(state), state_string(cur_state));
 997 }
 998 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 999 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         /* ILK FDI PLL is always enabled */
1008         if (dev_priv->info->gen == 5)
1009                 return;
1010
1011         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1012         if (HAS_DDI(dev_priv->dev))
1013                 return;
1014
1015         reg = FDI_TX_CTL(pipe);
1016         val = I915_READ(reg);
1017         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018 }
1019
1020 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         reg = FDI_RX_CTL(pipe);
1027         val = I915_READ(reg);
1028         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029 }
1030
1031 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032                                   enum pipe pipe)
1033 {
1034         int pp_reg, lvds_reg;
1035         u32 val;
1036         enum pipe panel_pipe = PIPE_A;
1037         bool locked = true;
1038
1039         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040                 pp_reg = PCH_PP_CONTROL;
1041                 lvds_reg = PCH_LVDS;
1042         } else {
1043                 pp_reg = PP_CONTROL;
1044                 lvds_reg = LVDS;
1045         }
1046
1047         val = I915_READ(pp_reg);
1048         if (!(val & PANEL_POWER_ON) ||
1049             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050                 locked = false;
1051
1052         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053                 panel_pipe = PIPE_B;
1054
1055         WARN(panel_pipe == pipe && locked,
1056              "panel assertion failure, pipe %c regs locked\n",
1057              pipe_name(pipe));
1058 }
1059
1060 void assert_pipe(struct drm_i915_private *dev_priv,
1061                  enum pipe pipe, bool state)
1062 {
1063         int reg;
1064         u32 val;
1065         bool cur_state;
1066         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067                                                                       pipe);
1068
1069         /* if we need the pipe A quirk it must be always on */
1070         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071                 state = true;
1072
1073         if (!intel_display_power_enabled(dev_priv->dev,
1074                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1075                 cur_state = false;
1076         } else {
1077                 reg = PIPECONF(cpu_transcoder);
1078                 val = I915_READ(reg);
1079                 cur_state = !!(val & PIPECONF_ENABLE);
1080         }
1081
1082         WARN(cur_state != state,
1083              "pipe %c assertion failure (expected %s, current %s)\n",
1084              pipe_name(pipe), state_string(state), state_string(cur_state));
1085 }
1086
1087 static void assert_plane(struct drm_i915_private *dev_priv,
1088                          enum plane plane, bool state)
1089 {
1090         int reg;
1091         u32 val;
1092         bool cur_state;
1093
1094         reg = DSPCNTR(plane);
1095         val = I915_READ(reg);
1096         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097         WARN(cur_state != state,
1098              "plane %c assertion failure (expected %s, current %s)\n",
1099              plane_name(plane), state_string(state), state_string(cur_state));
1100 }
1101
1102 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
1105 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106                                    enum pipe pipe)
1107 {
1108         int reg, i;
1109         u32 val;
1110         int cur_pipe;
1111
1112         /* Planes are fixed to pipes on ILK+ */
1113         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1114                 reg = DSPCNTR(pipe);
1115                 val = I915_READ(reg);
1116                 WARN((val & DISPLAY_PLANE_ENABLE),
1117                      "plane %c assertion failure, should be disabled but not\n",
1118                      plane_name(pipe));
1119                 return;
1120         }
1121
1122         /* Need to check both planes against the pipe */
1123         for (i = 0; i < 2; i++) {
1124                 reg = DSPCNTR(i);
1125                 val = I915_READ(reg);
1126                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1127                         DISPPLANE_SEL_PIPE_SHIFT;
1128                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1129                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1130                      plane_name(i), pipe_name(pipe));
1131         }
1132 }
1133
1134 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1135                                     enum pipe pipe)
1136 {
1137         int reg, i;
1138         u32 val;
1139
1140         if (!IS_VALLEYVIEW(dev_priv->dev))
1141                 return;
1142
1143         /* Need to check both planes against the pipe */
1144         for (i = 0; i < dev_priv->num_plane; i++) {
1145                 reg = SPCNTR(pipe, i);
1146                 val = I915_READ(reg);
1147                 WARN((val & SP_ENABLE),
1148                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1149                      sprite_name(pipe, i), pipe_name(pipe));
1150         }
1151 }
1152
1153 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1154 {
1155         u32 val;
1156         bool enabled;
1157
1158         if (HAS_PCH_LPT(dev_priv->dev)) {
1159                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1160                 return;
1161         }
1162
1163         val = I915_READ(PCH_DREF_CONTROL);
1164         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1165                             DREF_SUPERSPREAD_SOURCE_MASK));
1166         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1167 }
1168
1169 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1170                                            enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174         bool enabled;
1175
1176         reg = PCH_TRANSCONF(pipe);
1177         val = I915_READ(reg);
1178         enabled = !!(val & TRANS_ENABLE);
1179         WARN(enabled,
1180              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1181              pipe_name(pipe));
1182 }
1183
1184 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1185                             enum pipe pipe, u32 port_sel, u32 val)
1186 {
1187         if ((val & DP_PORT_EN) == 0)
1188                 return false;
1189
1190         if (HAS_PCH_CPT(dev_priv->dev)) {
1191                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1192                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1193                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1194                         return false;
1195         } else {
1196                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1197                         return false;
1198         }
1199         return true;
1200 }
1201
1202 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1203                               enum pipe pipe, u32 val)
1204 {
1205         if ((val & SDVO_ENABLE) == 0)
1206                 return false;
1207
1208         if (HAS_PCH_CPT(dev_priv->dev)) {
1209                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1210                         return false;
1211         } else {
1212                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1213                         return false;
1214         }
1215         return true;
1216 }
1217
1218 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1219                               enum pipe pipe, u32 val)
1220 {
1221         if ((val & LVDS_PORT_EN) == 0)
1222                 return false;
1223
1224         if (HAS_PCH_CPT(dev_priv->dev)) {
1225                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1226                         return false;
1227         } else {
1228                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1229                         return false;
1230         }
1231         return true;
1232 }
1233
1234 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1235                               enum pipe pipe, u32 val)
1236 {
1237         if ((val & ADPA_DAC_ENABLE) == 0)
1238                 return false;
1239         if (HAS_PCH_CPT(dev_priv->dev)) {
1240                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1241                         return false;
1242         } else {
1243                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1244                         return false;
1245         }
1246         return true;
1247 }
1248
1249 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1250                                    enum pipe pipe, int reg, u32 port_sel)
1251 {
1252         u32 val = I915_READ(reg);
1253         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1254              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1255              reg, pipe_name(pipe));
1256
1257         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1258              && (val & DP_PIPEB_SELECT),
1259              "IBX PCH dp port still using transcoder B\n");
1260 }
1261
1262 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1263                                      enum pipe pipe, int reg)
1264 {
1265         u32 val = I915_READ(reg);
1266         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1267              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1268              reg, pipe_name(pipe));
1269
1270         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1271              && (val & SDVO_PIPE_B_SELECT),
1272              "IBX PCH hdmi port still using transcoder B\n");
1273 }
1274
1275 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1276                                       enum pipe pipe)
1277 {
1278         int reg;
1279         u32 val;
1280
1281         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1282         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1283         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1284
1285         reg = PCH_ADPA;
1286         val = I915_READ(reg);
1287         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1288              "PCH VGA enabled on transcoder %c, should be disabled\n",
1289              pipe_name(pipe));
1290
1291         reg = PCH_LVDS;
1292         val = I915_READ(reg);
1293         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1294              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1295              pipe_name(pipe));
1296
1297         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1298         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1299         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1300 }
1301
1302 /**
1303  * intel_enable_pll - enable a PLL
1304  * @dev_priv: i915 private structure
1305  * @pipe: pipe PLL to enable
1306  *
1307  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1308  * make sure the PLL reg is writable first though, since the panel write
1309  * protect mechanism may be enabled.
1310  *
1311  * Note!  This is for pre-ILK only.
1312  *
1313  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1314  */
1315 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1316 {
1317         int reg;
1318         u32 val;
1319
1320         assert_pipe_disabled(dev_priv, pipe);
1321
1322         /* No really, not for ILK+ */
1323         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1324
1325         /* PLL is protected by panel, make sure we can write it */
1326         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1327                 assert_panel_unlocked(dev_priv, pipe);
1328
1329         reg = DPLL(pipe);
1330         val = I915_READ(reg);
1331         val |= DPLL_VCO_ENABLE;
1332
1333         /* We do this three times for luck */
1334         I915_WRITE(reg, val);
1335         POSTING_READ(reg);
1336         udelay(150); /* wait for warmup */
1337         I915_WRITE(reg, val);
1338         POSTING_READ(reg);
1339         udelay(150); /* wait for warmup */
1340         I915_WRITE(reg, val);
1341         POSTING_READ(reg);
1342         udelay(150); /* wait for warmup */
1343 }
1344
1345 /**
1346  * intel_disable_pll - disable a PLL
1347  * @dev_priv: i915 private structure
1348  * @pipe: pipe PLL to disable
1349  *
1350  * Disable the PLL for @pipe, making sure the pipe is off first.
1351  *
1352  * Note!  This is for pre-ILK only.
1353  */
1354 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1355 {
1356         int reg;
1357         u32 val;
1358
1359         /* Don't disable pipe A or pipe A PLLs if needed */
1360         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361                 return;
1362
1363         /* Make sure the pipe isn't still relying on us */
1364         assert_pipe_disabled(dev_priv, pipe);
1365
1366         reg = DPLL(pipe);
1367         val = I915_READ(reg);
1368         val &= ~DPLL_VCO_ENABLE;
1369         I915_WRITE(reg, val);
1370         POSTING_READ(reg);
1371 }
1372
1373 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1374 {
1375         u32 port_mask;
1376
1377         if (!port)
1378                 port_mask = DPLL_PORTB_READY_MASK;
1379         else
1380                 port_mask = DPLL_PORTC_READY_MASK;
1381
1382         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1383                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1384                      'B' + port, I915_READ(DPLL(0)));
1385 }
1386
1387 /**
1388  * ironlake_enable_pch_pll - enable PCH PLL
1389  * @dev_priv: i915 private structure
1390  * @pipe: pipe PLL to enable
1391  *
1392  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1393  * drives the transcoder clock.
1394  */
1395 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1396 {
1397         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1398         struct intel_pch_pll *pll;
1399         int reg;
1400         u32 val;
1401
1402         /* PCH PLLs only available on ILK, SNB and IVB */
1403         BUG_ON(dev_priv->info->gen < 5);
1404         pll = intel_crtc->pch_pll;
1405         if (pll == NULL)
1406                 return;
1407
1408         if (WARN_ON(pll->refcount == 0))
1409                 return;
1410
1411         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1412                       pll->pll_reg, pll->active, pll->on,
1413                       intel_crtc->base.base.id);
1414
1415         /* PCH refclock must be enabled first */
1416         assert_pch_refclk_enabled(dev_priv);
1417
1418         if (pll->active++ && pll->on) {
1419                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1420                 return;
1421         }
1422
1423         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1424
1425         reg = pll->pll_reg;
1426         val = I915_READ(reg);
1427         val |= DPLL_VCO_ENABLE;
1428         I915_WRITE(reg, val);
1429         POSTING_READ(reg);
1430         udelay(200);
1431
1432         pll->on = true;
1433 }
1434
1435 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1436 {
1437         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1438         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1439         int reg;
1440         u32 val;
1441
1442         /* PCH only available on ILK+ */
1443         BUG_ON(dev_priv->info->gen < 5);
1444         if (pll == NULL)
1445                return;
1446
1447         if (WARN_ON(pll->refcount == 0))
1448                 return;
1449
1450         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1451                       pll->pll_reg, pll->active, pll->on,
1452                       intel_crtc->base.base.id);
1453
1454         if (WARN_ON(pll->active == 0)) {
1455                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1456                 return;
1457         }
1458
1459         if (--pll->active) {
1460                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1461                 return;
1462         }
1463
1464         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1465
1466         /* Make sure transcoder isn't still depending on us */
1467         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1468
1469         reg = pll->pll_reg;
1470         val = I915_READ(reg);
1471         val &= ~DPLL_VCO_ENABLE;
1472         I915_WRITE(reg, val);
1473         POSTING_READ(reg);
1474         udelay(200);
1475
1476         pll->on = false;
1477 }
1478
1479 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1480                                            enum pipe pipe)
1481 {
1482         struct drm_device *dev = dev_priv->dev;
1483         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1484         uint32_t reg, val, pipeconf_val;
1485
1486         /* PCH only available on ILK+ */
1487         BUG_ON(dev_priv->info->gen < 5);
1488
1489         /* Make sure PCH DPLL is enabled */
1490         assert_pch_pll_enabled(dev_priv,
1491                                to_intel_crtc(crtc)->pch_pll,
1492                                to_intel_crtc(crtc));
1493
1494         /* FDI must be feeding us bits for PCH ports */
1495         assert_fdi_tx_enabled(dev_priv, pipe);
1496         assert_fdi_rx_enabled(dev_priv, pipe);
1497
1498         if (HAS_PCH_CPT(dev)) {
1499                 /* Workaround: Set the timing override bit before enabling the
1500                  * pch transcoder. */
1501                 reg = TRANS_CHICKEN2(pipe);
1502                 val = I915_READ(reg);
1503                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1504                 I915_WRITE(reg, val);
1505         }
1506
1507         reg = PCH_TRANSCONF(pipe);
1508         val = I915_READ(reg);
1509         pipeconf_val = I915_READ(PIPECONF(pipe));
1510
1511         if (HAS_PCH_IBX(dev_priv->dev)) {
1512                 /*
1513                  * make the BPC in transcoder be consistent with
1514                  * that in pipeconf reg.
1515                  */
1516                 val &= ~PIPECONF_BPC_MASK;
1517                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1518         }
1519
1520         val &= ~TRANS_INTERLACE_MASK;
1521         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1522                 if (HAS_PCH_IBX(dev_priv->dev) &&
1523                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1524                         val |= TRANS_LEGACY_INTERLACED_ILK;
1525                 else
1526                         val |= TRANS_INTERLACED;
1527         else
1528                 val |= TRANS_PROGRESSIVE;
1529
1530         I915_WRITE(reg, val | TRANS_ENABLE);
1531         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1532                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1533 }
1534
1535 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1536                                       enum transcoder cpu_transcoder)
1537 {
1538         u32 val, pipeconf_val;
1539
1540         /* PCH only available on ILK+ */
1541         BUG_ON(dev_priv->info->gen < 5);
1542
1543         /* FDI must be feeding us bits for PCH ports */
1544         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1545         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1546
1547         /* Workaround: set timing override bit. */
1548         val = I915_READ(_TRANSA_CHICKEN2);
1549         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1550         I915_WRITE(_TRANSA_CHICKEN2, val);
1551
1552         val = TRANS_ENABLE;
1553         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1554
1555         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1556             PIPECONF_INTERLACED_ILK)
1557                 val |= TRANS_INTERLACED;
1558         else
1559                 val |= TRANS_PROGRESSIVE;
1560
1561         I915_WRITE(LPT_TRANSCONF, val);
1562         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1563                 DRM_ERROR("Failed to enable PCH transcoder\n");
1564 }
1565
1566 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1567                                             enum pipe pipe)
1568 {
1569         struct drm_device *dev = dev_priv->dev;
1570         uint32_t reg, val;
1571
1572         /* FDI relies on the transcoder */
1573         assert_fdi_tx_disabled(dev_priv, pipe);
1574         assert_fdi_rx_disabled(dev_priv, pipe);
1575
1576         /* Ports must be off as well */
1577         assert_pch_ports_disabled(dev_priv, pipe);
1578
1579         reg = PCH_TRANSCONF(pipe);
1580         val = I915_READ(reg);
1581         val &= ~TRANS_ENABLE;
1582         I915_WRITE(reg, val);
1583         /* wait for PCH transcoder off, transcoder state */
1584         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1585                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1586
1587         if (!HAS_PCH_IBX(dev)) {
1588                 /* Workaround: Clear the timing override chicken bit again. */
1589                 reg = TRANS_CHICKEN2(pipe);
1590                 val = I915_READ(reg);
1591                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1592                 I915_WRITE(reg, val);
1593         }
1594 }
1595
1596 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1597 {
1598         u32 val;
1599
1600         val = I915_READ(LPT_TRANSCONF);
1601         val &= ~TRANS_ENABLE;
1602         I915_WRITE(LPT_TRANSCONF, val);
1603         /* wait for PCH transcoder off, transcoder state */
1604         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1605                 DRM_ERROR("Failed to disable PCH transcoder\n");
1606
1607         /* Workaround: clear timing override bit. */
1608         val = I915_READ(_TRANSA_CHICKEN2);
1609         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1610         I915_WRITE(_TRANSA_CHICKEN2, val);
1611 }
1612
1613 /**
1614  * intel_enable_pipe - enable a pipe, asserting requirements
1615  * @dev_priv: i915 private structure
1616  * @pipe: pipe to enable
1617  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1618  *
1619  * Enable @pipe, making sure that various hardware specific requirements
1620  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1621  *
1622  * @pipe should be %PIPE_A or %PIPE_B.
1623  *
1624  * Will wait until the pipe is actually running (i.e. first vblank) before
1625  * returning.
1626  */
1627 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1628                               bool pch_port)
1629 {
1630         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1631                                                                       pipe);
1632         enum pipe pch_transcoder;
1633         int reg;
1634         u32 val;
1635
1636         assert_planes_disabled(dev_priv, pipe);
1637         assert_sprites_disabled(dev_priv, pipe);
1638
1639         if (HAS_PCH_LPT(dev_priv->dev))
1640                 pch_transcoder = TRANSCODER_A;
1641         else
1642                 pch_transcoder = pipe;
1643
1644         /*
1645          * A pipe without a PLL won't actually be able to drive bits from
1646          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1647          * need the check.
1648          */
1649         if (!HAS_PCH_SPLIT(dev_priv->dev))
1650                 assert_pll_enabled(dev_priv, pipe);
1651         else {
1652                 if (pch_port) {
1653                         /* if driving the PCH, we need FDI enabled */
1654                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1655                         assert_fdi_tx_pll_enabled(dev_priv,
1656                                                   (enum pipe) cpu_transcoder);
1657                 }
1658                 /* FIXME: assert CPU port conditions for SNB+ */
1659         }
1660
1661         reg = PIPECONF(cpu_transcoder);
1662         val = I915_READ(reg);
1663         if (val & PIPECONF_ENABLE)
1664                 return;
1665
1666         I915_WRITE(reg, val | PIPECONF_ENABLE);
1667         intel_wait_for_vblank(dev_priv->dev, pipe);
1668 }
1669
1670 /**
1671  * intel_disable_pipe - disable a pipe, asserting requirements
1672  * @dev_priv: i915 private structure
1673  * @pipe: pipe to disable
1674  *
1675  * Disable @pipe, making sure that various hardware specific requirements
1676  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1677  *
1678  * @pipe should be %PIPE_A or %PIPE_B.
1679  *
1680  * Will wait until the pipe has shut down before returning.
1681  */
1682 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1683                                enum pipe pipe)
1684 {
1685         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1686                                                                       pipe);
1687         int reg;
1688         u32 val;
1689
1690         /*
1691          * Make sure planes won't keep trying to pump pixels to us,
1692          * or we might hang the display.
1693          */
1694         assert_planes_disabled(dev_priv, pipe);
1695         assert_sprites_disabled(dev_priv, pipe);
1696
1697         /* Don't disable pipe A or pipe A PLLs if needed */
1698         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699                 return;
1700
1701         reg = PIPECONF(cpu_transcoder);
1702         val = I915_READ(reg);
1703         if ((val & PIPECONF_ENABLE) == 0)
1704                 return;
1705
1706         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1707         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1708 }
1709
1710 /*
1711  * Plane regs are double buffered, going from enabled->disabled needs a
1712  * trigger in order to latch.  The display address reg provides this.
1713  */
1714 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1715                                       enum plane plane)
1716 {
1717         if (dev_priv->info->gen >= 4)
1718                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1719         else
1720                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1721 }
1722
1723 /**
1724  * intel_enable_plane - enable a display plane on a given pipe
1725  * @dev_priv: i915 private structure
1726  * @plane: plane to enable
1727  * @pipe: pipe being fed
1728  *
1729  * Enable @plane on @pipe, making sure that @pipe is running first.
1730  */
1731 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1732                                enum plane plane, enum pipe pipe)
1733 {
1734         int reg;
1735         u32 val;
1736
1737         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1738         assert_pipe_enabled(dev_priv, pipe);
1739
1740         reg = DSPCNTR(plane);
1741         val = I915_READ(reg);
1742         if (val & DISPLAY_PLANE_ENABLE)
1743                 return;
1744
1745         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1746         intel_flush_display_plane(dev_priv, plane);
1747         intel_wait_for_vblank(dev_priv->dev, pipe);
1748 }
1749
1750 /**
1751  * intel_disable_plane - disable a display plane
1752  * @dev_priv: i915 private structure
1753  * @plane: plane to disable
1754  * @pipe: pipe consuming the data
1755  *
1756  * Disable @plane; should be an independent operation.
1757  */
1758 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1759                                 enum plane plane, enum pipe pipe)
1760 {
1761         int reg;
1762         u32 val;
1763
1764         reg = DSPCNTR(plane);
1765         val = I915_READ(reg);
1766         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1767                 return;
1768
1769         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1770         intel_flush_display_plane(dev_priv, plane);
1771         intel_wait_for_vblank(dev_priv->dev, pipe);
1772 }
1773
1774 static bool need_vtd_wa(struct drm_device *dev)
1775 {
1776 #ifdef CONFIG_INTEL_IOMMU
1777         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1778                 return true;
1779 #endif
1780         return false;
1781 }
1782
1783 int
1784 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1785                            struct drm_i915_gem_object *obj,
1786                            struct intel_ring_buffer *pipelined)
1787 {
1788         struct drm_i915_private *dev_priv = dev->dev_private;
1789         u32 alignment;
1790         int ret;
1791
1792         switch (obj->tiling_mode) {
1793         case I915_TILING_NONE:
1794                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1795                         alignment = 128 * 1024;
1796                 else if (INTEL_INFO(dev)->gen >= 4)
1797                         alignment = 4 * 1024;
1798                 else
1799                         alignment = 64 * 1024;
1800                 break;
1801         case I915_TILING_X:
1802                 /* pin() will align the object as required by fence */
1803                 alignment = 0;
1804                 break;
1805         case I915_TILING_Y:
1806                 /* Despite that we check this in framebuffer_init userspace can
1807                  * screw us over and change the tiling after the fact. Only
1808                  * pinned buffers can't change their tiling. */
1809                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1810                 return -EINVAL;
1811         default:
1812                 BUG();
1813         }
1814
1815         /* Note that the w/a also requires 64 PTE of padding following the
1816          * bo. We currently fill all unused PTE with the shadow page and so
1817          * we should always have valid PTE following the scanout preventing
1818          * the VT-d warning.
1819          */
1820         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1821                 alignment = 256 * 1024;
1822
1823         dev_priv->mm.interruptible = false;
1824         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1825         if (ret)
1826                 goto err_interruptible;
1827
1828         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1829          * fence, whereas 965+ only requires a fence if using
1830          * framebuffer compression.  For simplicity, we always install
1831          * a fence as the cost is not that onerous.
1832          */
1833         ret = i915_gem_object_get_fence(obj);
1834         if (ret)
1835                 goto err_unpin;
1836
1837         i915_gem_object_pin_fence(obj);
1838
1839         dev_priv->mm.interruptible = true;
1840         return 0;
1841
1842 err_unpin:
1843         i915_gem_object_unpin(obj);
1844 err_interruptible:
1845         dev_priv->mm.interruptible = true;
1846         return ret;
1847 }
1848
1849 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1850 {
1851         i915_gem_object_unpin_fence(obj);
1852         i915_gem_object_unpin(obj);
1853 }
1854
1855 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1856  * is assumed to be a power-of-two. */
1857 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1858                                              unsigned int tiling_mode,
1859                                              unsigned int cpp,
1860                                              unsigned int pitch)
1861 {
1862         if (tiling_mode != I915_TILING_NONE) {
1863                 unsigned int tile_rows, tiles;
1864
1865                 tile_rows = *y / 8;
1866                 *y %= 8;
1867
1868                 tiles = *x / (512/cpp);
1869                 *x %= 512/cpp;
1870
1871                 return tile_rows * pitch * 8 + tiles * 4096;
1872         } else {
1873                 unsigned int offset;
1874
1875                 offset = *y * pitch + *x * cpp;
1876                 *y = 0;
1877                 *x = (offset & 4095) / cpp;
1878                 return offset & -4096;
1879         }
1880 }
1881
1882 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1883                              int x, int y)
1884 {
1885         struct drm_device *dev = crtc->dev;
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1888         struct intel_framebuffer *intel_fb;
1889         struct drm_i915_gem_object *obj;
1890         int plane = intel_crtc->plane;
1891         unsigned long linear_offset;
1892         u32 dspcntr;
1893         u32 reg;
1894
1895         switch (plane) {
1896         case 0:
1897         case 1:
1898                 break;
1899         default:
1900                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1901                 return -EINVAL;
1902         }
1903
1904         intel_fb = to_intel_framebuffer(fb);
1905         obj = intel_fb->obj;
1906
1907         reg = DSPCNTR(plane);
1908         dspcntr = I915_READ(reg);
1909         /* Mask out pixel format bits in case we change it */
1910         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1911         switch (fb->pixel_format) {
1912         case DRM_FORMAT_C8:
1913                 dspcntr |= DISPPLANE_8BPP;
1914                 break;
1915         case DRM_FORMAT_XRGB1555:
1916         case DRM_FORMAT_ARGB1555:
1917                 dspcntr |= DISPPLANE_BGRX555;
1918                 break;
1919         case DRM_FORMAT_RGB565:
1920                 dspcntr |= DISPPLANE_BGRX565;
1921                 break;
1922         case DRM_FORMAT_XRGB8888:
1923         case DRM_FORMAT_ARGB8888:
1924                 dspcntr |= DISPPLANE_BGRX888;
1925                 break;
1926         case DRM_FORMAT_XBGR8888:
1927         case DRM_FORMAT_ABGR8888:
1928                 dspcntr |= DISPPLANE_RGBX888;
1929                 break;
1930         case DRM_FORMAT_XRGB2101010:
1931         case DRM_FORMAT_ARGB2101010:
1932                 dspcntr |= DISPPLANE_BGRX101010;
1933                 break;
1934         case DRM_FORMAT_XBGR2101010:
1935         case DRM_FORMAT_ABGR2101010:
1936                 dspcntr |= DISPPLANE_RGBX101010;
1937                 break;
1938         default:
1939                 BUG();
1940         }
1941
1942         if (INTEL_INFO(dev)->gen >= 4) {
1943                 if (obj->tiling_mode != I915_TILING_NONE)
1944                         dspcntr |= DISPPLANE_TILED;
1945                 else
1946                         dspcntr &= ~DISPPLANE_TILED;
1947         }
1948
1949         I915_WRITE(reg, dspcntr);
1950
1951         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1952
1953         if (INTEL_INFO(dev)->gen >= 4) {
1954                 intel_crtc->dspaddr_offset =
1955                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1956                                                        fb->bits_per_pixel / 8,
1957                                                        fb->pitches[0]);
1958                 linear_offset -= intel_crtc->dspaddr_offset;
1959         } else {
1960                 intel_crtc->dspaddr_offset = linear_offset;
1961         }
1962
1963         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1964                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1965         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1966         if (INTEL_INFO(dev)->gen >= 4) {
1967                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1968                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1969                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1970                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1971         } else
1972                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1973         POSTING_READ(reg);
1974
1975         return 0;
1976 }
1977
1978 static int ironlake_update_plane(struct drm_crtc *crtc,
1979                                  struct drm_framebuffer *fb, int x, int y)
1980 {
1981         struct drm_device *dev = crtc->dev;
1982         struct drm_i915_private *dev_priv = dev->dev_private;
1983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984         struct intel_framebuffer *intel_fb;
1985         struct drm_i915_gem_object *obj;
1986         int plane = intel_crtc->plane;
1987         unsigned long linear_offset;
1988         u32 dspcntr;
1989         u32 reg;
1990
1991         switch (plane) {
1992         case 0:
1993         case 1:
1994         case 2:
1995                 break;
1996         default:
1997                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1998                 return -EINVAL;
1999         }
2000
2001         intel_fb = to_intel_framebuffer(fb);
2002         obj = intel_fb->obj;
2003
2004         reg = DSPCNTR(plane);
2005         dspcntr = I915_READ(reg);
2006         /* Mask out pixel format bits in case we change it */
2007         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2008         switch (fb->pixel_format) {
2009         case DRM_FORMAT_C8:
2010                 dspcntr |= DISPPLANE_8BPP;
2011                 break;
2012         case DRM_FORMAT_RGB565:
2013                 dspcntr |= DISPPLANE_BGRX565;
2014                 break;
2015         case DRM_FORMAT_XRGB8888:
2016         case DRM_FORMAT_ARGB8888:
2017                 dspcntr |= DISPPLANE_BGRX888;
2018                 break;
2019         case DRM_FORMAT_XBGR8888:
2020         case DRM_FORMAT_ABGR8888:
2021                 dspcntr |= DISPPLANE_RGBX888;
2022                 break;
2023         case DRM_FORMAT_XRGB2101010:
2024         case DRM_FORMAT_ARGB2101010:
2025                 dspcntr |= DISPPLANE_BGRX101010;
2026                 break;
2027         case DRM_FORMAT_XBGR2101010:
2028         case DRM_FORMAT_ABGR2101010:
2029                 dspcntr |= DISPPLANE_RGBX101010;
2030                 break;
2031         default:
2032                 BUG();
2033         }
2034
2035         if (obj->tiling_mode != I915_TILING_NONE)
2036                 dspcntr |= DISPPLANE_TILED;
2037         else
2038                 dspcntr &= ~DISPPLANE_TILED;
2039
2040         /* must disable */
2041         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2042
2043         I915_WRITE(reg, dspcntr);
2044
2045         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2046         intel_crtc->dspaddr_offset =
2047                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2048                                                fb->bits_per_pixel / 8,
2049                                                fb->pitches[0]);
2050         linear_offset -= intel_crtc->dspaddr_offset;
2051
2052         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2053                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2054         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2055         I915_MODIFY_DISPBASE(DSPSURF(plane),
2056                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2057         if (IS_HASWELL(dev)) {
2058                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2059         } else {
2060                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2061                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2062         }
2063         POSTING_READ(reg);
2064
2065         return 0;
2066 }
2067
2068 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2069 static int
2070 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2071                            int x, int y, enum mode_set_atomic state)
2072 {
2073         struct drm_device *dev = crtc->dev;
2074         struct drm_i915_private *dev_priv = dev->dev_private;
2075
2076         if (dev_priv->display.disable_fbc)
2077                 dev_priv->display.disable_fbc(dev);
2078         intel_increase_pllclock(crtc);
2079
2080         return dev_priv->display.update_plane(crtc, fb, x, y);
2081 }
2082
2083 void intel_display_handle_reset(struct drm_device *dev)
2084 {
2085         struct drm_i915_private *dev_priv = dev->dev_private;
2086         struct drm_crtc *crtc;
2087
2088         /*
2089          * Flips in the rings have been nuked by the reset,
2090          * so complete all pending flips so that user space
2091          * will get its events and not get stuck.
2092          *
2093          * Also update the base address of all primary
2094          * planes to the the last fb to make sure we're
2095          * showing the correct fb after a reset.
2096          *
2097          * Need to make two loops over the crtcs so that we
2098          * don't try to grab a crtc mutex before the
2099          * pending_flip_queue really got woken up.
2100          */
2101
2102         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2103                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2104                 enum plane plane = intel_crtc->plane;
2105
2106                 intel_prepare_page_flip(dev, plane);
2107                 intel_finish_page_flip_plane(dev, plane);
2108         }
2109
2110         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2111                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2112
2113                 mutex_lock(&crtc->mutex);
2114                 if (intel_crtc->active)
2115                         dev_priv->display.update_plane(crtc, crtc->fb,
2116                                                        crtc->x, crtc->y);
2117                 mutex_unlock(&crtc->mutex);
2118         }
2119 }
2120
2121 static int
2122 intel_finish_fb(struct drm_framebuffer *old_fb)
2123 {
2124         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2125         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2126         bool was_interruptible = dev_priv->mm.interruptible;
2127         int ret;
2128
2129         /* Big Hammer, we also need to ensure that any pending
2130          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2131          * current scanout is retired before unpinning the old
2132          * framebuffer.
2133          *
2134          * This should only fail upon a hung GPU, in which case we
2135          * can safely continue.
2136          */
2137         dev_priv->mm.interruptible = false;
2138         ret = i915_gem_object_finish_gpu(obj);
2139         dev_priv->mm.interruptible = was_interruptible;
2140
2141         return ret;
2142 }
2143
2144 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2145 {
2146         struct drm_device *dev = crtc->dev;
2147         struct drm_i915_master_private *master_priv;
2148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149
2150         if (!dev->primary->master)
2151                 return;
2152
2153         master_priv = dev->primary->master->driver_priv;
2154         if (!master_priv->sarea_priv)
2155                 return;
2156
2157         switch (intel_crtc->pipe) {
2158         case 0:
2159                 master_priv->sarea_priv->pipeA_x = x;
2160                 master_priv->sarea_priv->pipeA_y = y;
2161                 break;
2162         case 1:
2163                 master_priv->sarea_priv->pipeB_x = x;
2164                 master_priv->sarea_priv->pipeB_y = y;
2165                 break;
2166         default:
2167                 break;
2168         }
2169 }
2170
2171 static int
2172 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2173                     struct drm_framebuffer *fb)
2174 {
2175         struct drm_device *dev = crtc->dev;
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178         struct drm_framebuffer *old_fb;
2179         int ret;
2180
2181         /* no fb bound */
2182         if (!fb) {
2183                 DRM_ERROR("No FB bound\n");
2184                 return 0;
2185         }
2186
2187         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2188                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2189                           plane_name(intel_crtc->plane),
2190                           INTEL_INFO(dev)->num_pipes);
2191                 return -EINVAL;
2192         }
2193
2194         mutex_lock(&dev->struct_mutex);
2195         ret = intel_pin_and_fence_fb_obj(dev,
2196                                          to_intel_framebuffer(fb)->obj,
2197                                          NULL);
2198         if (ret != 0) {
2199                 mutex_unlock(&dev->struct_mutex);
2200                 DRM_ERROR("pin & fence failed\n");
2201                 return ret;
2202         }
2203
2204         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2205         if (ret) {
2206                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2207                 mutex_unlock(&dev->struct_mutex);
2208                 DRM_ERROR("failed to update base address\n");
2209                 return ret;
2210         }
2211
2212         old_fb = crtc->fb;
2213         crtc->fb = fb;
2214         crtc->x = x;
2215         crtc->y = y;
2216
2217         if (old_fb) {
2218                 if (intel_crtc->active && old_fb != fb)
2219                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2220                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2221         }
2222
2223         intel_update_fbc(dev);
2224         mutex_unlock(&dev->struct_mutex);
2225
2226         intel_crtc_update_sarea_pos(crtc, x, y);
2227
2228         return 0;
2229 }
2230
2231 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2232 {
2233         struct drm_device *dev = crtc->dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236         int pipe = intel_crtc->pipe;
2237         u32 reg, temp;
2238
2239         /* enable normal train */
2240         reg = FDI_TX_CTL(pipe);
2241         temp = I915_READ(reg);
2242         if (IS_IVYBRIDGE(dev)) {
2243                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2244                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2245         } else {
2246                 temp &= ~FDI_LINK_TRAIN_NONE;
2247                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2248         }
2249         I915_WRITE(reg, temp);
2250
2251         reg = FDI_RX_CTL(pipe);
2252         temp = I915_READ(reg);
2253         if (HAS_PCH_CPT(dev)) {
2254                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2255                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2256         } else {
2257                 temp &= ~FDI_LINK_TRAIN_NONE;
2258                 temp |= FDI_LINK_TRAIN_NONE;
2259         }
2260         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2261
2262         /* wait one idle pattern time */
2263         POSTING_READ(reg);
2264         udelay(1000);
2265
2266         /* IVB wants error correction enabled */
2267         if (IS_IVYBRIDGE(dev))
2268                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2269                            FDI_FE_ERRC_ENABLE);
2270 }
2271
2272 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2273 {
2274         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2275 }
2276
2277 static void ivb_modeset_global_resources(struct drm_device *dev)
2278 {
2279         struct drm_i915_private *dev_priv = dev->dev_private;
2280         struct intel_crtc *pipe_B_crtc =
2281                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2282         struct intel_crtc *pipe_C_crtc =
2283                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2284         uint32_t temp;
2285
2286         /*
2287          * When everything is off disable fdi C so that we could enable fdi B
2288          * with all lanes. Note that we don't care about enabled pipes without
2289          * an enabled pch encoder.
2290          */
2291         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2292             !pipe_has_enabled_pch(pipe_C_crtc)) {
2293                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2294                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2295
2296                 temp = I915_READ(SOUTH_CHICKEN1);
2297                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2298                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2299                 I915_WRITE(SOUTH_CHICKEN1, temp);
2300         }
2301 }
2302
2303 /* The FDI link training functions for ILK/Ibexpeak. */
2304 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2305 {
2306         struct drm_device *dev = crtc->dev;
2307         struct drm_i915_private *dev_priv = dev->dev_private;
2308         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309         int pipe = intel_crtc->pipe;
2310         int plane = intel_crtc->plane;
2311         u32 reg, temp, tries;
2312
2313         /* FDI needs bits from pipe & plane first */
2314         assert_pipe_enabled(dev_priv, pipe);
2315         assert_plane_enabled(dev_priv, plane);
2316
2317         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2318            for train result */
2319         reg = FDI_RX_IMR(pipe);
2320         temp = I915_READ(reg);
2321         temp &= ~FDI_RX_SYMBOL_LOCK;
2322         temp &= ~FDI_RX_BIT_LOCK;
2323         I915_WRITE(reg, temp);
2324         I915_READ(reg);
2325         udelay(150);
2326
2327         /* enable CPU FDI TX and PCH FDI RX */
2328         reg = FDI_TX_CTL(pipe);
2329         temp = I915_READ(reg);
2330         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2331         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2332         temp &= ~FDI_LINK_TRAIN_NONE;
2333         temp |= FDI_LINK_TRAIN_PATTERN_1;
2334         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2335
2336         reg = FDI_RX_CTL(pipe);
2337         temp = I915_READ(reg);
2338         temp &= ~FDI_LINK_TRAIN_NONE;
2339         temp |= FDI_LINK_TRAIN_PATTERN_1;
2340         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2341
2342         POSTING_READ(reg);
2343         udelay(150);
2344
2345         /* Ironlake workaround, enable clock pointer after FDI enable*/
2346         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2347         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2348                    FDI_RX_PHASE_SYNC_POINTER_EN);
2349
2350         reg = FDI_RX_IIR(pipe);
2351         for (tries = 0; tries < 5; tries++) {
2352                 temp = I915_READ(reg);
2353                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2354
2355                 if ((temp & FDI_RX_BIT_LOCK)) {
2356                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2357                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2358                         break;
2359                 }
2360         }
2361         if (tries == 5)
2362                 DRM_ERROR("FDI train 1 fail!\n");
2363
2364         /* Train 2 */
2365         reg = FDI_TX_CTL(pipe);
2366         temp = I915_READ(reg);
2367         temp &= ~FDI_LINK_TRAIN_NONE;
2368         temp |= FDI_LINK_TRAIN_PATTERN_2;
2369         I915_WRITE(reg, temp);
2370
2371         reg = FDI_RX_CTL(pipe);
2372         temp = I915_READ(reg);
2373         temp &= ~FDI_LINK_TRAIN_NONE;
2374         temp |= FDI_LINK_TRAIN_PATTERN_2;
2375         I915_WRITE(reg, temp);
2376
2377         POSTING_READ(reg);
2378         udelay(150);
2379
2380         reg = FDI_RX_IIR(pipe);
2381         for (tries = 0; tries < 5; tries++) {
2382                 temp = I915_READ(reg);
2383                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2384
2385                 if (temp & FDI_RX_SYMBOL_LOCK) {
2386                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2387                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2388                         break;
2389                 }
2390         }
2391         if (tries == 5)
2392                 DRM_ERROR("FDI train 2 fail!\n");
2393
2394         DRM_DEBUG_KMS("FDI train done\n");
2395
2396 }
2397
2398 static const int snb_b_fdi_train_param[] = {
2399         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2400         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2401         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2402         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2403 };
2404
2405 /* The FDI link training functions for SNB/Cougarpoint. */
2406 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2407 {
2408         struct drm_device *dev = crtc->dev;
2409         struct drm_i915_private *dev_priv = dev->dev_private;
2410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411         int pipe = intel_crtc->pipe;
2412         u32 reg, temp, i, retry;
2413
2414         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2415            for train result */
2416         reg = FDI_RX_IMR(pipe);
2417         temp = I915_READ(reg);
2418         temp &= ~FDI_RX_SYMBOL_LOCK;
2419         temp &= ~FDI_RX_BIT_LOCK;
2420         I915_WRITE(reg, temp);
2421
2422         POSTING_READ(reg);
2423         udelay(150);
2424
2425         /* enable CPU FDI TX and PCH FDI RX */
2426         reg = FDI_TX_CTL(pipe);
2427         temp = I915_READ(reg);
2428         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2429         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2430         temp &= ~FDI_LINK_TRAIN_NONE;
2431         temp |= FDI_LINK_TRAIN_PATTERN_1;
2432         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2433         /* SNB-B */
2434         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2435         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2436
2437         I915_WRITE(FDI_RX_MISC(pipe),
2438                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2439
2440         reg = FDI_RX_CTL(pipe);
2441         temp = I915_READ(reg);
2442         if (HAS_PCH_CPT(dev)) {
2443                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2444                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2445         } else {
2446                 temp &= ~FDI_LINK_TRAIN_NONE;
2447                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448         }
2449         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2450
2451         POSTING_READ(reg);
2452         udelay(150);
2453
2454         for (i = 0; i < 4; i++) {
2455                 reg = FDI_TX_CTL(pipe);
2456                 temp = I915_READ(reg);
2457                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2458                 temp |= snb_b_fdi_train_param[i];
2459                 I915_WRITE(reg, temp);
2460
2461                 POSTING_READ(reg);
2462                 udelay(500);
2463
2464                 for (retry = 0; retry < 5; retry++) {
2465                         reg = FDI_RX_IIR(pipe);
2466                         temp = I915_READ(reg);
2467                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468                         if (temp & FDI_RX_BIT_LOCK) {
2469                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2470                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2471                                 break;
2472                         }
2473                         udelay(50);
2474                 }
2475                 if (retry < 5)
2476                         break;
2477         }
2478         if (i == 4)
2479                 DRM_ERROR("FDI train 1 fail!\n");
2480
2481         /* Train 2 */
2482         reg = FDI_TX_CTL(pipe);
2483         temp = I915_READ(reg);
2484         temp &= ~FDI_LINK_TRAIN_NONE;
2485         temp |= FDI_LINK_TRAIN_PATTERN_2;
2486         if (IS_GEN6(dev)) {
2487                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2488                 /* SNB-B */
2489                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2490         }
2491         I915_WRITE(reg, temp);
2492
2493         reg = FDI_RX_CTL(pipe);
2494         temp = I915_READ(reg);
2495         if (HAS_PCH_CPT(dev)) {
2496                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2498         } else {
2499                 temp &= ~FDI_LINK_TRAIN_NONE;
2500                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501         }
2502         I915_WRITE(reg, temp);
2503
2504         POSTING_READ(reg);
2505         udelay(150);
2506
2507         for (i = 0; i < 4; i++) {
2508                 reg = FDI_TX_CTL(pipe);
2509                 temp = I915_READ(reg);
2510                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511                 temp |= snb_b_fdi_train_param[i];
2512                 I915_WRITE(reg, temp);
2513
2514                 POSTING_READ(reg);
2515                 udelay(500);
2516
2517                 for (retry = 0; retry < 5; retry++) {
2518                         reg = FDI_RX_IIR(pipe);
2519                         temp = I915_READ(reg);
2520                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521                         if (temp & FDI_RX_SYMBOL_LOCK) {
2522                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2523                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2524                                 break;
2525                         }
2526                         udelay(50);
2527                 }
2528                 if (retry < 5)
2529                         break;
2530         }
2531         if (i == 4)
2532                 DRM_ERROR("FDI train 2 fail!\n");
2533
2534         DRM_DEBUG_KMS("FDI train done.\n");
2535 }
2536
2537 /* Manual link training for Ivy Bridge A0 parts */
2538 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2539 {
2540         struct drm_device *dev = crtc->dev;
2541         struct drm_i915_private *dev_priv = dev->dev_private;
2542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543         int pipe = intel_crtc->pipe;
2544         u32 reg, temp, i;
2545
2546         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2547            for train result */
2548         reg = FDI_RX_IMR(pipe);
2549         temp = I915_READ(reg);
2550         temp &= ~FDI_RX_SYMBOL_LOCK;
2551         temp &= ~FDI_RX_BIT_LOCK;
2552         I915_WRITE(reg, temp);
2553
2554         POSTING_READ(reg);
2555         udelay(150);
2556
2557         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2558                       I915_READ(FDI_RX_IIR(pipe)));
2559
2560         /* enable CPU FDI TX and PCH FDI RX */
2561         reg = FDI_TX_CTL(pipe);
2562         temp = I915_READ(reg);
2563         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2564         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2565         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2566         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2567         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2568         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2569         temp |= FDI_COMPOSITE_SYNC;
2570         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2571
2572         I915_WRITE(FDI_RX_MISC(pipe),
2573                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2574
2575         reg = FDI_RX_CTL(pipe);
2576         temp = I915_READ(reg);
2577         temp &= ~FDI_LINK_TRAIN_AUTO;
2578         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2580         temp |= FDI_COMPOSITE_SYNC;
2581         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2582
2583         POSTING_READ(reg);
2584         udelay(150);
2585
2586         for (i = 0; i < 4; i++) {
2587                 reg = FDI_TX_CTL(pipe);
2588                 temp = I915_READ(reg);
2589                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590                 temp |= snb_b_fdi_train_param[i];
2591                 I915_WRITE(reg, temp);
2592
2593                 POSTING_READ(reg);
2594                 udelay(500);
2595
2596                 reg = FDI_RX_IIR(pipe);
2597                 temp = I915_READ(reg);
2598                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2599
2600                 if (temp & FDI_RX_BIT_LOCK ||
2601                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2602                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2603                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2604                         break;
2605                 }
2606         }
2607         if (i == 4)
2608                 DRM_ERROR("FDI train 1 fail!\n");
2609
2610         /* Train 2 */
2611         reg = FDI_TX_CTL(pipe);
2612         temp = I915_READ(reg);
2613         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2614         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2615         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2617         I915_WRITE(reg, temp);
2618
2619         reg = FDI_RX_CTL(pipe);
2620         temp = I915_READ(reg);
2621         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2622         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2623         I915_WRITE(reg, temp);
2624
2625         POSTING_READ(reg);
2626         udelay(150);
2627
2628         for (i = 0; i < 4; i++) {
2629                 reg = FDI_TX_CTL(pipe);
2630                 temp = I915_READ(reg);
2631                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632                 temp |= snb_b_fdi_train_param[i];
2633                 I915_WRITE(reg, temp);
2634
2635                 POSTING_READ(reg);
2636                 udelay(500);
2637
2638                 reg = FDI_RX_IIR(pipe);
2639                 temp = I915_READ(reg);
2640                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2641
2642                 if (temp & FDI_RX_SYMBOL_LOCK) {
2643                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2644                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2645                         break;
2646                 }
2647         }
2648         if (i == 4)
2649                 DRM_ERROR("FDI train 2 fail!\n");
2650
2651         DRM_DEBUG_KMS("FDI train done.\n");
2652 }
2653
2654 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2655 {
2656         struct drm_device *dev = intel_crtc->base.dev;
2657         struct drm_i915_private *dev_priv = dev->dev_private;
2658         int pipe = intel_crtc->pipe;
2659         u32 reg, temp;
2660
2661
2662         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2663         reg = FDI_RX_CTL(pipe);
2664         temp = I915_READ(reg);
2665         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2666         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2667         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2668         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2669
2670         POSTING_READ(reg);
2671         udelay(200);
2672
2673         /* Switch from Rawclk to PCDclk */
2674         temp = I915_READ(reg);
2675         I915_WRITE(reg, temp | FDI_PCDCLK);
2676
2677         POSTING_READ(reg);
2678         udelay(200);
2679
2680         /* Enable CPU FDI TX PLL, always on for Ironlake */
2681         reg = FDI_TX_CTL(pipe);
2682         temp = I915_READ(reg);
2683         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2684                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2685
2686                 POSTING_READ(reg);
2687                 udelay(100);
2688         }
2689 }
2690
2691 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2692 {
2693         struct drm_device *dev = intel_crtc->base.dev;
2694         struct drm_i915_private *dev_priv = dev->dev_private;
2695         int pipe = intel_crtc->pipe;
2696         u32 reg, temp;
2697
2698         /* Switch from PCDclk to Rawclk */
2699         reg = FDI_RX_CTL(pipe);
2700         temp = I915_READ(reg);
2701         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2702
2703         /* Disable CPU FDI TX PLL */
2704         reg = FDI_TX_CTL(pipe);
2705         temp = I915_READ(reg);
2706         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2707
2708         POSTING_READ(reg);
2709         udelay(100);
2710
2711         reg = FDI_RX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2714
2715         /* Wait for the clocks to turn off. */
2716         POSTING_READ(reg);
2717         udelay(100);
2718 }
2719
2720 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2721 {
2722         struct drm_device *dev = crtc->dev;
2723         struct drm_i915_private *dev_priv = dev->dev_private;
2724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2725         int pipe = intel_crtc->pipe;
2726         u32 reg, temp;
2727
2728         /* disable CPU FDI tx and PCH FDI rx */
2729         reg = FDI_TX_CTL(pipe);
2730         temp = I915_READ(reg);
2731         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2732         POSTING_READ(reg);
2733
2734         reg = FDI_RX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         temp &= ~(0x7 << 16);
2737         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2738         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2739
2740         POSTING_READ(reg);
2741         udelay(100);
2742
2743         /* Ironlake workaround, disable clock pointer after downing FDI */
2744         if (HAS_PCH_IBX(dev)) {
2745                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2746         }
2747
2748         /* still set train pattern 1 */
2749         reg = FDI_TX_CTL(pipe);
2750         temp = I915_READ(reg);
2751         temp &= ~FDI_LINK_TRAIN_NONE;
2752         temp |= FDI_LINK_TRAIN_PATTERN_1;
2753         I915_WRITE(reg, temp);
2754
2755         reg = FDI_RX_CTL(pipe);
2756         temp = I915_READ(reg);
2757         if (HAS_PCH_CPT(dev)) {
2758                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2759                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2760         } else {
2761                 temp &= ~FDI_LINK_TRAIN_NONE;
2762                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2763         }
2764         /* BPC in FDI rx is consistent with that in PIPECONF */
2765         temp &= ~(0x07 << 16);
2766         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2767         I915_WRITE(reg, temp);
2768
2769         POSTING_READ(reg);
2770         udelay(100);
2771 }
2772
2773 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         unsigned long flags;
2779         bool pending;
2780
2781         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2782             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2783                 return false;
2784
2785         spin_lock_irqsave(&dev->event_lock, flags);
2786         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2787         spin_unlock_irqrestore(&dev->event_lock, flags);
2788
2789         return pending;
2790 }
2791
2792 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2793 {
2794         struct drm_device *dev = crtc->dev;
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796
2797         if (crtc->fb == NULL)
2798                 return;
2799
2800         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2801
2802         wait_event(dev_priv->pending_flip_queue,
2803                    !intel_crtc_has_pending_flip(crtc));
2804
2805         mutex_lock(&dev->struct_mutex);
2806         intel_finish_fb(crtc->fb);
2807         mutex_unlock(&dev->struct_mutex);
2808 }
2809
2810 /* Program iCLKIP clock to the desired frequency */
2811 static void lpt_program_iclkip(struct drm_crtc *crtc)
2812 {
2813         struct drm_device *dev = crtc->dev;
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2816         u32 temp;
2817
2818         mutex_lock(&dev_priv->dpio_lock);
2819
2820         /* It is necessary to ungate the pixclk gate prior to programming
2821          * the divisors, and gate it back when it is done.
2822          */
2823         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2824
2825         /* Disable SSCCTL */
2826         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2827                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2828                                 SBI_SSCCTL_DISABLE,
2829                         SBI_ICLK);
2830
2831         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2832         if (crtc->mode.clock == 20000) {
2833                 auxdiv = 1;
2834                 divsel = 0x41;
2835                 phaseinc = 0x20;
2836         } else {
2837                 /* The iCLK virtual clock root frequency is in MHz,
2838                  * but the crtc->mode.clock in in KHz. To get the divisors,
2839                  * it is necessary to divide one by another, so we
2840                  * convert the virtual clock precision to KHz here for higher
2841                  * precision.
2842                  */
2843                 u32 iclk_virtual_root_freq = 172800 * 1000;
2844                 u32 iclk_pi_range = 64;
2845                 u32 desired_divisor, msb_divisor_value, pi_value;
2846
2847                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2848                 msb_divisor_value = desired_divisor / iclk_pi_range;
2849                 pi_value = desired_divisor % iclk_pi_range;
2850
2851                 auxdiv = 0;
2852                 divsel = msb_divisor_value - 2;
2853                 phaseinc = pi_value;
2854         }
2855
2856         /* This should not happen with any sane values */
2857         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2858                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2859         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2860                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2861
2862         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2863                         crtc->mode.clock,
2864                         auxdiv,
2865                         divsel,
2866                         phasedir,
2867                         phaseinc);
2868
2869         /* Program SSCDIVINTPHASE6 */
2870         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2871         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2872         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2873         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2874         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2875         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2876         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2877         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2878
2879         /* Program SSCAUXDIV */
2880         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2881         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2882         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2883         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2884
2885         /* Enable modulator and associated divider */
2886         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2887         temp &= ~SBI_SSCCTL_DISABLE;
2888         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2889
2890         /* Wait for initialization time */
2891         udelay(24);
2892
2893         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2894
2895         mutex_unlock(&dev_priv->dpio_lock);
2896 }
2897
2898 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2899                                                 enum pipe pch_transcoder)
2900 {
2901         struct drm_device *dev = crtc->base.dev;
2902         struct drm_i915_private *dev_priv = dev->dev_private;
2903         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2904
2905         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2906                    I915_READ(HTOTAL(cpu_transcoder)));
2907         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2908                    I915_READ(HBLANK(cpu_transcoder)));
2909         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2910                    I915_READ(HSYNC(cpu_transcoder)));
2911
2912         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2913                    I915_READ(VTOTAL(cpu_transcoder)));
2914         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2915                    I915_READ(VBLANK(cpu_transcoder)));
2916         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2917                    I915_READ(VSYNC(cpu_transcoder)));
2918         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2919                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2920 }
2921
2922 /*
2923  * Enable PCH resources required for PCH ports:
2924  *   - PCH PLLs
2925  *   - FDI training & RX/TX
2926  *   - update transcoder timings
2927  *   - DP transcoding bits
2928  *   - transcoder
2929  */
2930 static void ironlake_pch_enable(struct drm_crtc *crtc)
2931 {
2932         struct drm_device *dev = crtc->dev;
2933         struct drm_i915_private *dev_priv = dev->dev_private;
2934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935         int pipe = intel_crtc->pipe;
2936         u32 reg, temp;
2937
2938         assert_pch_transcoder_disabled(dev_priv, pipe);
2939
2940         /* Write the TU size bits before fdi link training, so that error
2941          * detection works. */
2942         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2943                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2944
2945         /* For PCH output, training FDI link */
2946         dev_priv->display.fdi_link_train(crtc);
2947
2948         /* XXX: pch pll's can be enabled any time before we enable the PCH
2949          * transcoder, and we actually should do this to not upset any PCH
2950          * transcoder that already use the clock when we share it.
2951          *
2952          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2953          * unconditionally resets the pll - we need that to have the right LVDS
2954          * enable sequence. */
2955         ironlake_enable_pch_pll(intel_crtc);
2956
2957         if (HAS_PCH_CPT(dev)) {
2958                 u32 sel;
2959
2960                 temp = I915_READ(PCH_DPLL_SEL);
2961                 switch (pipe) {
2962                 default:
2963                 case 0:
2964                         temp |= TRANSA_DPLL_ENABLE;
2965                         sel = TRANSA_DPLLB_SEL;
2966                         break;
2967                 case 1:
2968                         temp |= TRANSB_DPLL_ENABLE;
2969                         sel = TRANSB_DPLLB_SEL;
2970                         break;
2971                 case 2:
2972                         temp |= TRANSC_DPLL_ENABLE;
2973                         sel = TRANSC_DPLLB_SEL;
2974                         break;
2975                 }
2976                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2977                         temp |= sel;
2978                 else
2979                         temp &= ~sel;
2980                 I915_WRITE(PCH_DPLL_SEL, temp);
2981         }
2982
2983         /* set transcoder timing, panel must allow it */
2984         assert_panel_unlocked(dev_priv, pipe);
2985         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2986
2987         intel_fdi_normal_train(crtc);
2988
2989         /* For PCH DP, enable TRANS_DP_CTL */
2990         if (HAS_PCH_CPT(dev) &&
2991             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2992              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2993                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2994                 reg = TRANS_DP_CTL(pipe);
2995                 temp = I915_READ(reg);
2996                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2997                           TRANS_DP_SYNC_MASK |
2998                           TRANS_DP_BPC_MASK);
2999                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3000                          TRANS_DP_ENH_FRAMING);
3001                 temp |= bpc << 9; /* same format but at 11:9 */
3002
3003                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3004                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3005                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3006                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3007
3008                 switch (intel_trans_dp_port_sel(crtc)) {
3009                 case PCH_DP_B:
3010                         temp |= TRANS_DP_PORT_SEL_B;
3011                         break;
3012                 case PCH_DP_C:
3013                         temp |= TRANS_DP_PORT_SEL_C;
3014                         break;
3015                 case PCH_DP_D:
3016                         temp |= TRANS_DP_PORT_SEL_D;
3017                         break;
3018                 default:
3019                         BUG();
3020                 }
3021
3022                 I915_WRITE(reg, temp);
3023         }
3024
3025         ironlake_enable_pch_transcoder(dev_priv, pipe);
3026 }
3027
3028 static void lpt_pch_enable(struct drm_crtc *crtc)
3029 {
3030         struct drm_device *dev = crtc->dev;
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3033         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3034
3035         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3036
3037         lpt_program_iclkip(crtc);
3038
3039         /* Set transcoder timing. */
3040         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3041
3042         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3043 }
3044
3045 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3046 {
3047         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3048
3049         if (pll == NULL)
3050                 return;
3051
3052         if (pll->refcount == 0) {
3053                 WARN(1, "bad PCH PLL refcount\n");
3054                 return;
3055         }
3056
3057         --pll->refcount;
3058         intel_crtc->pch_pll = NULL;
3059 }
3060
3061 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3062 {
3063         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3064         struct intel_pch_pll *pll;
3065         int i;
3066
3067         pll = intel_crtc->pch_pll;
3068         if (pll) {
3069                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3070                               intel_crtc->base.base.id, pll->pll_reg);
3071                 goto prepare;
3072         }
3073
3074         if (HAS_PCH_IBX(dev_priv->dev)) {
3075                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3076                 i = intel_crtc->pipe;
3077                 pll = &dev_priv->pch_plls[i];
3078
3079                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3080                               intel_crtc->base.base.id, pll->pll_reg);
3081
3082                 goto found;
3083         }
3084
3085         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3086                 pll = &dev_priv->pch_plls[i];
3087
3088                 /* Only want to check enabled timings first */
3089                 if (pll->refcount == 0)
3090                         continue;
3091
3092                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3093                     fp == I915_READ(pll->fp0_reg)) {
3094                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3095                                       intel_crtc->base.base.id,
3096                                       pll->pll_reg, pll->refcount, pll->active);
3097
3098                         goto found;
3099                 }
3100         }
3101
3102         /* Ok no matching timings, maybe there's a free one? */
3103         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3104                 pll = &dev_priv->pch_plls[i];
3105                 if (pll->refcount == 0) {
3106                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3107                                       intel_crtc->base.base.id, pll->pll_reg);
3108                         goto found;
3109                 }
3110         }
3111
3112         return NULL;
3113
3114 found:
3115         intel_crtc->pch_pll = pll;
3116         pll->refcount++;
3117         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3118 prepare: /* separate function? */
3119         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3120
3121         /* Wait for the clocks to stabilize before rewriting the regs */
3122         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3123         POSTING_READ(pll->pll_reg);
3124         udelay(150);
3125
3126         I915_WRITE(pll->fp0_reg, fp);
3127         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3128         pll->on = false;
3129         return pll;
3130 }
3131
3132 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3133 {
3134         struct drm_i915_private *dev_priv = dev->dev_private;
3135         int dslreg = PIPEDSL(pipe);
3136         u32 temp;
3137
3138         temp = I915_READ(dslreg);
3139         udelay(500);
3140         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3141                 if (wait_for(I915_READ(dslreg) != temp, 5))
3142                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3143         }
3144 }
3145
3146 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3147 {
3148         struct drm_device *dev = crtc->base.dev;
3149         struct drm_i915_private *dev_priv = dev->dev_private;
3150         int pipe = crtc->pipe;
3151
3152         if (crtc->config.pch_pfit.size) {
3153                 /* Force use of hard-coded filter coefficients
3154                  * as some pre-programmed values are broken,
3155                  * e.g. x201.
3156                  */
3157                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3158                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3159                                                  PF_PIPE_SEL_IVB(pipe));
3160                 else
3161                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3162                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3163                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3164         }
3165 }
3166
3167 static void intel_enable_planes(struct drm_crtc *crtc)
3168 {
3169         struct drm_device *dev = crtc->dev;
3170         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3171         struct intel_plane *intel_plane;
3172
3173         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3174                 if (intel_plane->pipe == pipe)
3175                         intel_plane_restore(&intel_plane->base);
3176 }
3177
3178 static void intel_disable_planes(struct drm_crtc *crtc)
3179 {
3180         struct drm_device *dev = crtc->dev;
3181         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3182         struct intel_plane *intel_plane;
3183
3184         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3185                 if (intel_plane->pipe == pipe)
3186                         intel_plane_disable(&intel_plane->base);
3187 }
3188
3189 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3190 {
3191         struct drm_device *dev = crtc->dev;
3192         struct drm_i915_private *dev_priv = dev->dev_private;
3193         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3194         struct intel_encoder *encoder;
3195         int pipe = intel_crtc->pipe;
3196         int plane = intel_crtc->plane;
3197         u32 temp;
3198
3199         WARN_ON(!crtc->enabled);
3200
3201         if (intel_crtc->active)
3202                 return;
3203
3204         intel_crtc->active = true;
3205
3206         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3207         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3208
3209         intel_update_watermarks(dev);
3210
3211         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3212                 temp = I915_READ(PCH_LVDS);
3213                 if ((temp & LVDS_PORT_EN) == 0)
3214                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3215         }
3216
3217
3218         if (intel_crtc->config.has_pch_encoder) {
3219                 /* Note: FDI PLL enabling _must_ be done before we enable the
3220                  * cpu pipes, hence this is separate from all the other fdi/pch
3221                  * enabling. */
3222                 ironlake_fdi_pll_enable(intel_crtc);
3223         } else {
3224                 assert_fdi_tx_disabled(dev_priv, pipe);
3225                 assert_fdi_rx_disabled(dev_priv, pipe);
3226         }
3227
3228         for_each_encoder_on_crtc(dev, crtc, encoder)
3229                 if (encoder->pre_enable)
3230                         encoder->pre_enable(encoder);
3231
3232         /* Enable panel fitting for LVDS */
3233         ironlake_pfit_enable(intel_crtc);
3234
3235         /*
3236          * On ILK+ LUT must be loaded before the pipe is running but with
3237          * clocks enabled
3238          */
3239         intel_crtc_load_lut(crtc);
3240
3241         intel_enable_pipe(dev_priv, pipe,
3242                           intel_crtc->config.has_pch_encoder);
3243         intel_enable_plane(dev_priv, plane, pipe);
3244         intel_enable_planes(crtc);
3245         intel_crtc_update_cursor(crtc, true);
3246
3247         if (intel_crtc->config.has_pch_encoder)
3248                 ironlake_pch_enable(crtc);
3249
3250         mutex_lock(&dev->struct_mutex);
3251         intel_update_fbc(dev);
3252         mutex_unlock(&dev->struct_mutex);
3253
3254         for_each_encoder_on_crtc(dev, crtc, encoder)
3255                 encoder->enable(encoder);
3256
3257         if (HAS_PCH_CPT(dev))
3258                 cpt_verify_modeset(dev, intel_crtc->pipe);
3259
3260         /*
3261          * There seems to be a race in PCH platform hw (at least on some
3262          * outputs) where an enabled pipe still completes any pageflip right
3263          * away (as if the pipe is off) instead of waiting for vblank. As soon
3264          * as the first vblank happend, everything works as expected. Hence just
3265          * wait for one vblank before returning to avoid strange things
3266          * happening.
3267          */
3268         intel_wait_for_vblank(dev, intel_crtc->pipe);
3269 }
3270
3271 /* IPS only exists on ULT machines and is tied to pipe A. */
3272 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3273 {
3274         return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3275 }
3276
3277 static void hsw_enable_ips(struct intel_crtc *crtc)
3278 {
3279         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3280
3281         if (!crtc->config.ips_enabled)
3282                 return;
3283
3284         /* We can only enable IPS after we enable a plane and wait for a vblank.
3285          * We guarantee that the plane is enabled by calling intel_enable_ips
3286          * only after intel_enable_plane. And intel_enable_plane already waits
3287          * for a vblank, so all we need to do here is to enable the IPS bit. */
3288         assert_plane_enabled(dev_priv, crtc->plane);
3289         I915_WRITE(IPS_CTL, IPS_ENABLE);
3290 }
3291
3292 static void hsw_disable_ips(struct intel_crtc *crtc)
3293 {
3294         struct drm_device *dev = crtc->base.dev;
3295         struct drm_i915_private *dev_priv = dev->dev_private;
3296
3297         if (!crtc->config.ips_enabled)
3298                 return;
3299
3300         assert_plane_enabled(dev_priv, crtc->plane);
3301         I915_WRITE(IPS_CTL, 0);
3302
3303         /* We need to wait for a vblank before we can disable the plane. */
3304         intel_wait_for_vblank(dev, crtc->pipe);
3305 }
3306
3307 static void haswell_crtc_enable(struct drm_crtc *crtc)
3308 {
3309         struct drm_device *dev = crtc->dev;
3310         struct drm_i915_private *dev_priv = dev->dev_private;
3311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312         struct intel_encoder *encoder;
3313         int pipe = intel_crtc->pipe;
3314         int plane = intel_crtc->plane;
3315
3316         WARN_ON(!crtc->enabled);
3317
3318         if (intel_crtc->active)
3319                 return;
3320
3321         intel_crtc->active = true;
3322
3323         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3324         if (intel_crtc->config.has_pch_encoder)
3325                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3326
3327         intel_update_watermarks(dev);
3328
3329         if (intel_crtc->config.has_pch_encoder)
3330                 dev_priv->display.fdi_link_train(crtc);
3331
3332         for_each_encoder_on_crtc(dev, crtc, encoder)
3333                 if (encoder->pre_enable)
3334                         encoder->pre_enable(encoder);
3335
3336         intel_ddi_enable_pipe_clock(intel_crtc);
3337
3338         /* Enable panel fitting for eDP */
3339         ironlake_pfit_enable(intel_crtc);
3340
3341         /*
3342          * On ILK+ LUT must be loaded before the pipe is running but with
3343          * clocks enabled
3344          */
3345         intel_crtc_load_lut(crtc);
3346
3347         intel_ddi_set_pipe_settings(crtc);
3348         intel_ddi_enable_transcoder_func(crtc);
3349
3350         intel_enable_pipe(dev_priv, pipe,
3351                           intel_crtc->config.has_pch_encoder);
3352         intel_enable_plane(dev_priv, plane, pipe);
3353         intel_enable_planes(crtc);
3354         intel_crtc_update_cursor(crtc, true);
3355
3356         hsw_enable_ips(intel_crtc);
3357
3358         if (intel_crtc->config.has_pch_encoder)
3359                 lpt_pch_enable(crtc);
3360
3361         mutex_lock(&dev->struct_mutex);
3362         intel_update_fbc(dev);
3363         mutex_unlock(&dev->struct_mutex);
3364
3365         for_each_encoder_on_crtc(dev, crtc, encoder)
3366                 encoder->enable(encoder);
3367
3368         /*
3369          * There seems to be a race in PCH platform hw (at least on some
3370          * outputs) where an enabled pipe still completes any pageflip right
3371          * away (as if the pipe is off) instead of waiting for vblank. As soon
3372          * as the first vblank happend, everything works as expected. Hence just
3373          * wait for one vblank before returning to avoid strange things
3374          * happening.
3375          */
3376         intel_wait_for_vblank(dev, intel_crtc->pipe);
3377 }
3378
3379 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3380 {
3381         struct drm_device *dev = crtc->base.dev;
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383         int pipe = crtc->pipe;
3384
3385         /* To avoid upsetting the power well on haswell only disable the pfit if
3386          * it's in use. The hw state code will make sure we get this right. */
3387         if (crtc->config.pch_pfit.size) {
3388                 I915_WRITE(PF_CTL(pipe), 0);
3389                 I915_WRITE(PF_WIN_POS(pipe), 0);
3390                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3391         }
3392 }
3393
3394 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3395 {
3396         struct drm_device *dev = crtc->dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         struct intel_encoder *encoder;
3400         int pipe = intel_crtc->pipe;
3401         int plane = intel_crtc->plane;
3402         u32 reg, temp;
3403
3404
3405         if (!intel_crtc->active)
3406                 return;
3407
3408         for_each_encoder_on_crtc(dev, crtc, encoder)
3409                 encoder->disable(encoder);
3410
3411         intel_crtc_wait_for_pending_flips(crtc);
3412         drm_vblank_off(dev, pipe);
3413
3414         if (dev_priv->cfb_plane == plane)
3415                 intel_disable_fbc(dev);
3416
3417         intel_crtc_update_cursor(crtc, false);
3418         intel_disable_planes(crtc);
3419         intel_disable_plane(dev_priv, plane, pipe);
3420
3421         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3422         intel_disable_pipe(dev_priv, pipe);
3423
3424         ironlake_pfit_disable(intel_crtc);
3425
3426         for_each_encoder_on_crtc(dev, crtc, encoder)
3427                 if (encoder->post_disable)
3428                         encoder->post_disable(encoder);
3429
3430         ironlake_fdi_disable(crtc);
3431
3432         ironlake_disable_pch_transcoder(dev_priv, pipe);
3433         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3434
3435         if (HAS_PCH_CPT(dev)) {
3436                 /* disable TRANS_DP_CTL */
3437                 reg = TRANS_DP_CTL(pipe);
3438                 temp = I915_READ(reg);
3439                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3440                 temp |= TRANS_DP_PORT_SEL_NONE;
3441                 I915_WRITE(reg, temp);
3442
3443                 /* disable DPLL_SEL */
3444                 temp = I915_READ(PCH_DPLL_SEL);
3445                 switch (pipe) {
3446                 case 0:
3447                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3448                         break;
3449                 case 1:
3450                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3451                         break;
3452                 case 2:
3453                         /* C shares PLL A or B */
3454                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3455                         break;
3456                 default:
3457                         BUG(); /* wtf */
3458                 }
3459                 I915_WRITE(PCH_DPLL_SEL, temp);
3460         }
3461
3462         /* disable PCH DPLL */
3463         intel_disable_pch_pll(intel_crtc);
3464
3465         ironlake_fdi_pll_disable(intel_crtc);
3466
3467         intel_crtc->active = false;
3468         intel_update_watermarks(dev);
3469
3470         mutex_lock(&dev->struct_mutex);
3471         intel_update_fbc(dev);
3472         mutex_unlock(&dev->struct_mutex);
3473 }
3474
3475 static void haswell_crtc_disable(struct drm_crtc *crtc)
3476 {
3477         struct drm_device *dev = crtc->dev;
3478         struct drm_i915_private *dev_priv = dev->dev_private;
3479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480         struct intel_encoder *encoder;
3481         int pipe = intel_crtc->pipe;
3482         int plane = intel_crtc->plane;
3483         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3484
3485         if (!intel_crtc->active)
3486                 return;
3487
3488         for_each_encoder_on_crtc(dev, crtc, encoder)
3489                 encoder->disable(encoder);
3490
3491         intel_crtc_wait_for_pending_flips(crtc);
3492         drm_vblank_off(dev, pipe);
3493
3494         /* FBC must be disabled before disabling the plane on HSW. */
3495         if (dev_priv->cfb_plane == plane)
3496                 intel_disable_fbc(dev);
3497
3498         hsw_disable_ips(intel_crtc);
3499
3500         intel_crtc_update_cursor(crtc, false);
3501         intel_disable_planes(crtc);
3502         intel_disable_plane(dev_priv, plane, pipe);
3503
3504         if (intel_crtc->config.has_pch_encoder)
3505                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3506         intel_disable_pipe(dev_priv, pipe);
3507
3508         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3509
3510         ironlake_pfit_disable(intel_crtc);
3511
3512         intel_ddi_disable_pipe_clock(intel_crtc);
3513
3514         for_each_encoder_on_crtc(dev, crtc, encoder)
3515                 if (encoder->post_disable)
3516                         encoder->post_disable(encoder);
3517
3518         if (intel_crtc->config.has_pch_encoder) {
3519                 lpt_disable_pch_transcoder(dev_priv);
3520                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3521                 intel_ddi_fdi_disable(crtc);
3522         }
3523
3524         intel_crtc->active = false;
3525         intel_update_watermarks(dev);
3526
3527         mutex_lock(&dev->struct_mutex);
3528         intel_update_fbc(dev);
3529         mutex_unlock(&dev->struct_mutex);
3530 }
3531
3532 static void ironlake_crtc_off(struct drm_crtc *crtc)
3533 {
3534         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3535         intel_put_pch_pll(intel_crtc);
3536 }
3537
3538 static void haswell_crtc_off(struct drm_crtc *crtc)
3539 {
3540         intel_ddi_put_crtc_pll(crtc);
3541 }
3542
3543 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3544 {
3545         if (!enable && intel_crtc->overlay) {
3546                 struct drm_device *dev = intel_crtc->base.dev;
3547                 struct drm_i915_private *dev_priv = dev->dev_private;
3548
3549                 mutex_lock(&dev->struct_mutex);
3550                 dev_priv->mm.interruptible = false;
3551                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3552                 dev_priv->mm.interruptible = true;
3553                 mutex_unlock(&dev->struct_mutex);
3554         }
3555
3556         /* Let userspace switch the overlay on again. In most cases userspace
3557          * has to recompute where to put it anyway.
3558          */
3559 }
3560
3561 /**
3562  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3563  * cursor plane briefly if not already running after enabling the display
3564  * plane.
3565  * This workaround avoids occasional blank screens when self refresh is
3566  * enabled.
3567  */
3568 static void
3569 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3570 {
3571         u32 cntl = I915_READ(CURCNTR(pipe));
3572
3573         if ((cntl & CURSOR_MODE) == 0) {
3574                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3575
3576                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3577                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3578                 intel_wait_for_vblank(dev_priv->dev, pipe);
3579                 I915_WRITE(CURCNTR(pipe), cntl);
3580                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3581                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3582         }
3583 }
3584
3585 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3586 {
3587         struct drm_device *dev = crtc->base.dev;
3588         struct drm_i915_private *dev_priv = dev->dev_private;
3589         struct intel_crtc_config *pipe_config = &crtc->config;
3590
3591         if (!crtc->config.gmch_pfit.control)
3592                 return;
3593
3594         /*
3595          * The panel fitter should only be adjusted whilst the pipe is disabled,
3596          * according to register description and PRM.
3597          */
3598         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3599         assert_pipe_disabled(dev_priv, crtc->pipe);
3600
3601         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3602         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3603
3604         /* Border color in case we don't scale up to the full screen. Black by
3605          * default, change to something else for debugging. */
3606         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3607 }
3608
3609 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3610 {
3611         struct drm_device *dev = crtc->dev;
3612         struct drm_i915_private *dev_priv = dev->dev_private;
3613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614         struct intel_encoder *encoder;
3615         int pipe = intel_crtc->pipe;
3616         int plane = intel_crtc->plane;
3617
3618         WARN_ON(!crtc->enabled);
3619
3620         if (intel_crtc->active)
3621                 return;
3622
3623         intel_crtc->active = true;
3624         intel_update_watermarks(dev);
3625
3626         mutex_lock(&dev_priv->dpio_lock);
3627
3628         for_each_encoder_on_crtc(dev, crtc, encoder)
3629                 if (encoder->pre_pll_enable)
3630                         encoder->pre_pll_enable(encoder);
3631
3632         intel_enable_pll(dev_priv, pipe);
3633
3634         for_each_encoder_on_crtc(dev, crtc, encoder)
3635                 if (encoder->pre_enable)
3636                         encoder->pre_enable(encoder);
3637
3638         /* VLV wants encoder enabling _before_ the pipe is up. */
3639         for_each_encoder_on_crtc(dev, crtc, encoder)
3640                 encoder->enable(encoder);
3641
3642         /* Enable panel fitting for eDP */
3643         i9xx_pfit_enable(intel_crtc);
3644
3645         intel_crtc_load_lut(crtc);
3646
3647         intel_enable_pipe(dev_priv, pipe, false);
3648         intel_enable_plane(dev_priv, plane, pipe);
3649         intel_enable_planes(crtc);
3650         intel_crtc_update_cursor(crtc, true);
3651
3652         intel_update_fbc(dev);
3653
3654         mutex_unlock(&dev_priv->dpio_lock);
3655 }
3656
3657 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3658 {
3659         struct drm_device *dev = crtc->dev;
3660         struct drm_i915_private *dev_priv = dev->dev_private;
3661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3662         struct intel_encoder *encoder;
3663         int pipe = intel_crtc->pipe;
3664         int plane = intel_crtc->plane;
3665
3666         WARN_ON(!crtc->enabled);
3667
3668         if (intel_crtc->active)
3669                 return;
3670
3671         intel_crtc->active = true;
3672         intel_update_watermarks(dev);
3673
3674         intel_enable_pll(dev_priv, pipe);
3675
3676         for_each_encoder_on_crtc(dev, crtc, encoder)
3677                 if (encoder->pre_enable)
3678                         encoder->pre_enable(encoder);
3679
3680         /* Enable panel fitting for LVDS */
3681         i9xx_pfit_enable(intel_crtc);
3682
3683         intel_crtc_load_lut(crtc);
3684
3685         intel_enable_pipe(dev_priv, pipe, false);
3686         intel_enable_plane(dev_priv, plane, pipe);
3687         intel_enable_planes(crtc);
3688         intel_crtc_update_cursor(crtc, true);
3689         if (IS_G4X(dev))
3690                 g4x_fixup_plane(dev_priv, pipe);
3691
3692         /* Give the overlay scaler a chance to enable if it's on this pipe */
3693         intel_crtc_dpms_overlay(intel_crtc, true);
3694
3695         intel_update_fbc(dev);
3696
3697         for_each_encoder_on_crtc(dev, crtc, encoder)
3698                 encoder->enable(encoder);
3699 }
3700
3701 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3702 {
3703         struct drm_device *dev = crtc->base.dev;
3704         struct drm_i915_private *dev_priv = dev->dev_private;
3705
3706         if (!crtc->config.gmch_pfit.control)
3707                 return;
3708
3709         assert_pipe_disabled(dev_priv, crtc->pipe);
3710
3711         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3712                          I915_READ(PFIT_CONTROL));
3713         I915_WRITE(PFIT_CONTROL, 0);
3714 }
3715
3716 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->dev;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721         struct intel_encoder *encoder;
3722         int pipe = intel_crtc->pipe;
3723         int plane = intel_crtc->plane;
3724
3725         if (!intel_crtc->active)
3726                 return;
3727
3728         for_each_encoder_on_crtc(dev, crtc, encoder)
3729                 encoder->disable(encoder);
3730
3731         /* Give the overlay scaler a chance to disable if it's on this pipe */
3732         intel_crtc_wait_for_pending_flips(crtc);
3733         drm_vblank_off(dev, pipe);
3734
3735         if (dev_priv->cfb_plane == plane)
3736                 intel_disable_fbc(dev);
3737
3738         intel_crtc_dpms_overlay(intel_crtc, false);
3739         intel_crtc_update_cursor(crtc, false);
3740         intel_disable_planes(crtc);
3741         intel_disable_plane(dev_priv, plane, pipe);
3742
3743         intel_disable_pipe(dev_priv, pipe);
3744
3745         i9xx_pfit_disable(intel_crtc);
3746
3747         for_each_encoder_on_crtc(dev, crtc, encoder)
3748                 if (encoder->post_disable)
3749                         encoder->post_disable(encoder);
3750
3751         intel_disable_pll(dev_priv, pipe);
3752
3753         intel_crtc->active = false;
3754         intel_update_fbc(dev);
3755         intel_update_watermarks(dev);
3756 }
3757
3758 static void i9xx_crtc_off(struct drm_crtc *crtc)
3759 {
3760 }
3761
3762 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3763                                     bool enabled)
3764 {
3765         struct drm_device *dev = crtc->dev;
3766         struct drm_i915_master_private *master_priv;
3767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3768         int pipe = intel_crtc->pipe;
3769
3770         if (!dev->primary->master)
3771                 return;
3772
3773         master_priv = dev->primary->master->driver_priv;
3774         if (!master_priv->sarea_priv)
3775                 return;
3776
3777         switch (pipe) {
3778         case 0:
3779                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3780                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3781                 break;
3782         case 1:
3783                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3784                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3785                 break;
3786         default:
3787                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3788                 break;
3789         }
3790 }
3791
3792 /**
3793  * Sets the power management mode of the pipe and plane.
3794  */
3795 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3796 {
3797         struct drm_device *dev = crtc->dev;
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         struct intel_encoder *intel_encoder;
3800         bool enable = false;
3801
3802         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3803                 enable |= intel_encoder->connectors_active;
3804
3805         if (enable)
3806                 dev_priv->display.crtc_enable(crtc);
3807         else
3808                 dev_priv->display.crtc_disable(crtc);
3809
3810         intel_crtc_update_sarea(crtc, enable);
3811 }
3812
3813 static void intel_crtc_disable(struct drm_crtc *crtc)
3814 {
3815         struct drm_device *dev = crtc->dev;
3816         struct drm_connector *connector;
3817         struct drm_i915_private *dev_priv = dev->dev_private;
3818         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3819
3820         /* crtc should still be enabled when we disable it. */
3821         WARN_ON(!crtc->enabled);
3822
3823         dev_priv->display.crtc_disable(crtc);
3824         intel_crtc->eld_vld = false;
3825         intel_crtc_update_sarea(crtc, false);
3826         dev_priv->display.off(crtc);
3827
3828         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3829         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3830
3831         if (crtc->fb) {
3832                 mutex_lock(&dev->struct_mutex);
3833                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3834                 mutex_unlock(&dev->struct_mutex);
3835                 crtc->fb = NULL;
3836         }
3837
3838         /* Update computed state. */
3839         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3840                 if (!connector->encoder || !connector->encoder->crtc)
3841                         continue;
3842
3843                 if (connector->encoder->crtc != crtc)
3844                         continue;
3845
3846                 connector->dpms = DRM_MODE_DPMS_OFF;
3847                 to_intel_encoder(connector->encoder)->connectors_active = false;
3848         }
3849 }
3850
3851 void intel_modeset_disable(struct drm_device *dev)
3852 {
3853         struct drm_crtc *crtc;
3854
3855         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3856                 if (crtc->enabled)
3857                         intel_crtc_disable(crtc);
3858         }
3859 }
3860
3861 void intel_encoder_destroy(struct drm_encoder *encoder)
3862 {
3863         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3864
3865         drm_encoder_cleanup(encoder);
3866         kfree(intel_encoder);
3867 }
3868
3869 /* Simple dpms helper for encodres with just one connector, no cloning and only
3870  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3871  * state of the entire output pipe. */
3872 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3873 {
3874         if (mode == DRM_MODE_DPMS_ON) {
3875                 encoder->connectors_active = true;
3876
3877                 intel_crtc_update_dpms(encoder->base.crtc);
3878         } else {
3879                 encoder->connectors_active = false;
3880
3881                 intel_crtc_update_dpms(encoder->base.crtc);
3882         }
3883 }
3884
3885 /* Cross check the actual hw state with our own modeset state tracking (and it's
3886  * internal consistency). */
3887 static void intel_connector_check_state(struct intel_connector *connector)
3888 {
3889         if (connector->get_hw_state(connector)) {
3890                 struct intel_encoder *encoder = connector->encoder;
3891                 struct drm_crtc *crtc;
3892                 bool encoder_enabled;
3893                 enum pipe pipe;
3894
3895                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3896                               connector->base.base.id,
3897                               drm_get_connector_name(&connector->base));
3898
3899                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3900                      "wrong connector dpms state\n");
3901                 WARN(connector->base.encoder != &encoder->base,
3902                      "active connector not linked to encoder\n");
3903                 WARN(!encoder->connectors_active,
3904                      "encoder->connectors_active not set\n");
3905
3906                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3907                 WARN(!encoder_enabled, "encoder not enabled\n");
3908                 if (WARN_ON(!encoder->base.crtc))
3909                         return;
3910
3911                 crtc = encoder->base.crtc;
3912
3913                 WARN(!crtc->enabled, "crtc not enabled\n");
3914                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3915                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3916                      "encoder active on the wrong pipe\n");
3917         }
3918 }
3919
3920 /* Even simpler default implementation, if there's really no special case to
3921  * consider. */
3922 void intel_connector_dpms(struct drm_connector *connector, int mode)
3923 {
3924         struct intel_encoder *encoder = intel_attached_encoder(connector);
3925
3926         /* All the simple cases only support two dpms states. */
3927         if (mode != DRM_MODE_DPMS_ON)
3928                 mode = DRM_MODE_DPMS_OFF;
3929
3930         if (mode == connector->dpms)
3931                 return;
3932
3933         connector->dpms = mode;
3934
3935         /* Only need to change hw state when actually enabled */
3936         if (encoder->base.crtc)
3937                 intel_encoder_dpms(encoder, mode);
3938         else
3939                 WARN_ON(encoder->connectors_active != false);
3940
3941         intel_modeset_check_state(connector->dev);
3942 }
3943
3944 /* Simple connector->get_hw_state implementation for encoders that support only
3945  * one connector and no cloning and hence the encoder state determines the state
3946  * of the connector. */
3947 bool intel_connector_get_hw_state(struct intel_connector *connector)
3948 {
3949         enum pipe pipe = 0;
3950         struct intel_encoder *encoder = connector->encoder;
3951
3952         return encoder->get_hw_state(encoder, &pipe);
3953 }
3954
3955 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3956                                      struct intel_crtc_config *pipe_config)
3957 {
3958         struct drm_i915_private *dev_priv = dev->dev_private;
3959         struct intel_crtc *pipe_B_crtc =
3960                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3961
3962         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3963                       pipe_name(pipe), pipe_config->fdi_lanes);
3964         if (pipe_config->fdi_lanes > 4) {
3965                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3966                               pipe_name(pipe), pipe_config->fdi_lanes);
3967                 return false;
3968         }
3969
3970         if (IS_HASWELL(dev)) {
3971                 if (pipe_config->fdi_lanes > 2) {
3972                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3973                                       pipe_config->fdi_lanes);
3974                         return false;
3975                 } else {
3976                         return true;
3977                 }
3978         }
3979
3980         if (INTEL_INFO(dev)->num_pipes == 2)
3981                 return true;
3982
3983         /* Ivybridge 3 pipe is really complicated */
3984         switch (pipe) {
3985         case PIPE_A:
3986                 return true;
3987         case PIPE_B:
3988                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3989                     pipe_config->fdi_lanes > 2) {
3990                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3991                                       pipe_name(pipe), pipe_config->fdi_lanes);
3992                         return false;
3993                 }
3994                 return true;
3995         case PIPE_C:
3996                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3997                     pipe_B_crtc->config.fdi_lanes <= 2) {
3998                         if (pipe_config->fdi_lanes > 2) {
3999                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4000                                               pipe_name(pipe), pipe_config->fdi_lanes);
4001                                 return false;
4002                         }
4003                 } else {
4004                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4005                         return false;
4006                 }
4007                 return true;
4008         default:
4009                 BUG();
4010         }
4011 }
4012
4013 #define RETRY 1
4014 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4015                                        struct intel_crtc_config *pipe_config)
4016 {
4017         struct drm_device *dev = intel_crtc->base.dev;
4018         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4019         int lane, link_bw, fdi_dotclock;
4020         bool setup_ok, needs_recompute = false;
4021
4022 retry:
4023         /* FDI is a binary signal running at ~2.7GHz, encoding
4024          * each output octet as 10 bits. The actual frequency
4025          * is stored as a divider into a 100MHz clock, and the
4026          * mode pixel clock is stored in units of 1KHz.
4027          * Hence the bw of each lane in terms of the mode signal
4028          * is:
4029          */
4030         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4031
4032         fdi_dotclock = adjusted_mode->clock;
4033         fdi_dotclock /= pipe_config->pixel_multiplier;
4034
4035         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4036                                            pipe_config->pipe_bpp);
4037
4038         pipe_config->fdi_lanes = lane;
4039
4040         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4041                                link_bw, &pipe_config->fdi_m_n);
4042
4043         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4044                                             intel_crtc->pipe, pipe_config);
4045         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4046                 pipe_config->pipe_bpp -= 2*3;
4047                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4048                               pipe_config->pipe_bpp);
4049                 needs_recompute = true;
4050                 pipe_config->bw_constrained = true;
4051
4052                 goto retry;
4053         }
4054
4055         if (needs_recompute)
4056                 return RETRY;
4057
4058         return setup_ok ? 0 : -EINVAL;
4059 }
4060
4061 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4062                                    struct intel_crtc_config *pipe_config)
4063 {
4064         pipe_config->ips_enabled = i915_enable_ips &&
4065                                    hsw_crtc_supports_ips(crtc) &&
4066                                    pipe_config->pipe_bpp == 24;
4067 }
4068
4069 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4070                                      struct intel_crtc_config *pipe_config)
4071 {
4072         struct drm_device *dev = crtc->dev;
4073         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4075
4076         if (HAS_PCH_SPLIT(dev)) {
4077                 /* FDI link clock is fixed at 2.7G */
4078                 if (pipe_config->requested_mode.clock * 3
4079                     > IRONLAKE_FDI_FREQ * 4)
4080                         return -EINVAL;
4081         }
4082
4083         /* All interlaced capable intel hw wants timings in frames. Note though
4084          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4085          * timings, so we need to be careful not to clobber these.*/
4086         if (!pipe_config->timings_set)
4087                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4088
4089         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4090          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4091          */
4092         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4093                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4094                 return -EINVAL;
4095
4096         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4097                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4098         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4099                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4100                  * for lvds. */
4101                 pipe_config->pipe_bpp = 8*3;
4102         }
4103
4104         if (IS_HASWELL(dev))
4105                 hsw_compute_ips_config(intel_crtc, pipe_config);
4106
4107         if (pipe_config->has_pch_encoder)
4108                 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
4109
4110         return 0;
4111 }
4112
4113 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4114 {
4115         return 400000; /* FIXME */
4116 }
4117
4118 static int i945_get_display_clock_speed(struct drm_device *dev)
4119 {
4120         return 400000;
4121 }
4122
4123 static int i915_get_display_clock_speed(struct drm_device *dev)
4124 {
4125         return 333000;
4126 }
4127
4128 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4129 {
4130         return 200000;
4131 }
4132
4133 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4134 {
4135         u16 gcfgc = 0;
4136
4137         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4138
4139         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4140                 return 133000;
4141         else {
4142                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4143                 case GC_DISPLAY_CLOCK_333_MHZ:
4144                         return 333000;
4145                 default:
4146                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4147                         return 190000;
4148                 }
4149         }
4150 }
4151
4152 static int i865_get_display_clock_speed(struct drm_device *dev)
4153 {
4154         return 266000;
4155 }
4156
4157 static int i855_get_display_clock_speed(struct drm_device *dev)
4158 {
4159         u16 hpllcc = 0;
4160         /* Assume that the hardware is in the high speed state.  This
4161          * should be the default.
4162          */
4163         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4164         case GC_CLOCK_133_200:
4165         case GC_CLOCK_100_200:
4166                 return 200000;
4167         case GC_CLOCK_166_250:
4168                 return 250000;
4169         case GC_CLOCK_100_133:
4170                 return 133000;
4171         }
4172
4173         /* Shouldn't happen */
4174         return 0;
4175 }
4176
4177 static int i830_get_display_clock_speed(struct drm_device *dev)
4178 {
4179         return 133000;
4180 }
4181
4182 static void
4183 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4184 {
4185         while (*num > DATA_LINK_M_N_MASK ||
4186                *den > DATA_LINK_M_N_MASK) {
4187                 *num >>= 1;
4188                 *den >>= 1;
4189         }
4190 }
4191
4192 static void compute_m_n(unsigned int m, unsigned int n,
4193                         uint32_t *ret_m, uint32_t *ret_n)
4194 {
4195         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4196         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4197         intel_reduce_m_n_ratio(ret_m, ret_n);
4198 }
4199
4200 void
4201 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4202                        int pixel_clock, int link_clock,
4203                        struct intel_link_m_n *m_n)
4204 {
4205         m_n->tu = 64;
4206
4207         compute_m_n(bits_per_pixel * pixel_clock,
4208                     link_clock * nlanes * 8,
4209                     &m_n->gmch_m, &m_n->gmch_n);
4210
4211         compute_m_n(pixel_clock, link_clock,
4212                     &m_n->link_m, &m_n->link_n);
4213 }
4214
4215 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4216 {
4217         if (i915_panel_use_ssc >= 0)
4218                 return i915_panel_use_ssc != 0;
4219         return dev_priv->vbt.lvds_use_ssc
4220                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4221 }
4222
4223 static int vlv_get_refclk(struct drm_crtc *crtc)
4224 {
4225         struct drm_device *dev = crtc->dev;
4226         struct drm_i915_private *dev_priv = dev->dev_private;
4227         int refclk = 27000; /* for DP & HDMI */
4228
4229         return 100000; /* only one validated so far */
4230
4231         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4232                 refclk = 96000;
4233         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4234                 if (intel_panel_use_ssc(dev_priv))
4235                         refclk = 100000;
4236                 else
4237                         refclk = 96000;
4238         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4239                 refclk = 100000;
4240         }
4241
4242         return refclk;
4243 }
4244
4245 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4246 {
4247         struct drm_device *dev = crtc->dev;
4248         struct drm_i915_private *dev_priv = dev->dev_private;
4249         int refclk;
4250
4251         if (IS_VALLEYVIEW(dev)) {
4252                 refclk = vlv_get_refclk(crtc);
4253         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4254             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4255                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4256                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4257                               refclk / 1000);
4258         } else if (!IS_GEN2(dev)) {
4259                 refclk = 96000;
4260         } else {
4261                 refclk = 48000;
4262         }
4263
4264         return refclk;
4265 }
4266
4267 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4268 {
4269         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4270 }
4271
4272 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4273 {
4274         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4275 }
4276
4277 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4278                                      intel_clock_t *reduced_clock)
4279 {
4280         struct drm_device *dev = crtc->base.dev;
4281         struct drm_i915_private *dev_priv = dev->dev_private;
4282         int pipe = crtc->pipe;
4283         u32 fp, fp2 = 0;
4284
4285         if (IS_PINEVIEW(dev)) {
4286                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4287                 if (reduced_clock)
4288                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4289         } else {
4290                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4291                 if (reduced_clock)
4292                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4293         }
4294
4295         I915_WRITE(FP0(pipe), fp);
4296
4297         crtc->lowfreq_avail = false;
4298         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4299             reduced_clock && i915_powersave) {
4300                 I915_WRITE(FP1(pipe), fp2);
4301                 crtc->lowfreq_avail = true;
4302         } else {
4303                 I915_WRITE(FP1(pipe), fp);
4304         }
4305 }
4306
4307 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4308 {
4309         u32 reg_val;
4310
4311         /*
4312          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4313          * and set it to a reasonable value instead.
4314          */
4315         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4316         reg_val &= 0xffffff00;
4317         reg_val |= 0x00000030;
4318         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4319
4320         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4321         reg_val &= 0x8cffffff;
4322         reg_val = 0x8c000000;
4323         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4324
4325         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4326         reg_val &= 0xffffff00;
4327         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4328
4329         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4330         reg_val &= 0x00ffffff;
4331         reg_val |= 0xb0000000;
4332         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4333 }
4334
4335 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4336                                          struct intel_link_m_n *m_n)
4337 {
4338         struct drm_device *dev = crtc->base.dev;
4339         struct drm_i915_private *dev_priv = dev->dev_private;
4340         int pipe = crtc->pipe;
4341
4342         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4343         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4344         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4345         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4346 }
4347
4348 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4349                                          struct intel_link_m_n *m_n)
4350 {
4351         struct drm_device *dev = crtc->base.dev;
4352         struct drm_i915_private *dev_priv = dev->dev_private;
4353         int pipe = crtc->pipe;
4354         enum transcoder transcoder = crtc->config.cpu_transcoder;
4355
4356         if (INTEL_INFO(dev)->gen >= 5) {
4357                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4358                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4359                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4360                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4361         } else {
4362                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4363                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4364                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4365                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4366         }
4367 }
4368
4369 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4370 {
4371         if (crtc->config.has_pch_encoder)
4372                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4373         else
4374                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4375 }
4376
4377 static void vlv_update_pll(struct intel_crtc *crtc)
4378 {
4379         struct drm_device *dev = crtc->base.dev;
4380         struct drm_i915_private *dev_priv = dev->dev_private;
4381         struct intel_encoder *encoder;
4382         int pipe = crtc->pipe;
4383         u32 dpll, mdiv;
4384         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4385         bool is_hdmi;
4386         u32 coreclk, reg_val, dpll_md;
4387
4388         mutex_lock(&dev_priv->dpio_lock);
4389
4390         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4391
4392         bestn = crtc->config.dpll.n;
4393         bestm1 = crtc->config.dpll.m1;
4394         bestm2 = crtc->config.dpll.m2;
4395         bestp1 = crtc->config.dpll.p1;
4396         bestp2 = crtc->config.dpll.p2;
4397
4398         /* See eDP HDMI DPIO driver vbios notes doc */
4399
4400         /* PLL B needs special handling */
4401         if (pipe)
4402                 vlv_pllb_recal_opamp(dev_priv);
4403
4404         /* Set up Tx target for periodic Rcomp update */
4405         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4406
4407         /* Disable target IRef on PLL */
4408         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4409         reg_val &= 0x00ffffff;
4410         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4411
4412         /* Disable fast lock */
4413         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4414
4415         /* Set idtafcrecal before PLL is enabled */
4416         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4417         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4418         mdiv |= ((bestn << DPIO_N_SHIFT));
4419         mdiv |= (1 << DPIO_K_SHIFT);
4420
4421         /*
4422          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4423          * but we don't support that).
4424          * Note: don't use the DAC post divider as it seems unstable.
4425          */
4426         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4427         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4428
4429         mdiv |= DPIO_ENABLE_CALIBRATION;
4430         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4431
4432         /* Set HBR and RBR LPF coefficients */
4433         if (crtc->config.port_clock == 162000 ||
4434             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4435                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4436                                  0x005f0021);
4437         else
4438                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4439                                  0x00d0000f);
4440
4441         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4442             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4443                 /* Use SSC source */
4444                 if (!pipe)
4445                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4446                                          0x0df40000);
4447                 else
4448                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4449                                          0x0df70000);
4450         } else { /* HDMI or VGA */
4451                 /* Use bend source */
4452                 if (!pipe)
4453                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4454                                          0x0df70000);
4455                 else
4456                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4457                                          0x0df40000);
4458         }
4459
4460         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4461         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4462         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4463             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4464                 coreclk |= 0x01000000;
4465         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4466
4467         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4468
4469         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4470                 if (encoder->pre_pll_enable)
4471                         encoder->pre_pll_enable(encoder);
4472
4473         /* Enable DPIO clock input */
4474         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4475                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4476         if (pipe)
4477                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4478
4479         dpll |= DPLL_VCO_ENABLE;
4480         I915_WRITE(DPLL(pipe), dpll);
4481         POSTING_READ(DPLL(pipe));
4482         udelay(150);
4483
4484         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4485                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4486
4487         dpll_md = (crtc->config.pixel_multiplier - 1)
4488                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4489         I915_WRITE(DPLL_MD(pipe), dpll_md);
4490         POSTING_READ(DPLL_MD(pipe));
4491
4492         if (crtc->config.has_dp_encoder)
4493                 intel_dp_set_m_n(crtc);
4494
4495         mutex_unlock(&dev_priv->dpio_lock);
4496 }
4497
4498 static void i9xx_update_pll(struct intel_crtc *crtc,
4499                             intel_clock_t *reduced_clock,
4500                             int num_connectors)
4501 {
4502         struct drm_device *dev = crtc->base.dev;
4503         struct drm_i915_private *dev_priv = dev->dev_private;
4504         struct intel_encoder *encoder;
4505         int pipe = crtc->pipe;
4506         u32 dpll;
4507         bool is_sdvo;
4508         struct dpll *clock = &crtc->config.dpll;
4509
4510         i9xx_update_pll_dividers(crtc, reduced_clock);
4511
4512         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4513                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4514
4515         dpll = DPLL_VGA_MODE_DIS;
4516
4517         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4518                 dpll |= DPLLB_MODE_LVDS;
4519         else
4520                 dpll |= DPLLB_MODE_DAC_SERIAL;
4521
4522         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4523                 dpll |= (crtc->config.pixel_multiplier - 1)
4524                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4525         }
4526
4527         if (is_sdvo)
4528                 dpll |= DPLL_DVO_HIGH_SPEED;
4529
4530         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4531                 dpll |= DPLL_DVO_HIGH_SPEED;
4532
4533         /* compute bitmask from p1 value */
4534         if (IS_PINEVIEW(dev))
4535                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4536         else {
4537                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4538                 if (IS_G4X(dev) && reduced_clock)
4539                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4540         }
4541         switch (clock->p2) {
4542         case 5:
4543                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4544                 break;
4545         case 7:
4546                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4547                 break;
4548         case 10:
4549                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4550                 break;
4551         case 14:
4552                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4553                 break;
4554         }
4555         if (INTEL_INFO(dev)->gen >= 4)
4556                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4557
4558         if (crtc->config.sdvo_tv_clock)
4559                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4560         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4561                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4562                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4563         else
4564                 dpll |= PLL_REF_INPUT_DREFCLK;
4565
4566         dpll |= DPLL_VCO_ENABLE;
4567         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4568         POSTING_READ(DPLL(pipe));
4569         udelay(150);
4570
4571         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4572                 if (encoder->pre_pll_enable)
4573                         encoder->pre_pll_enable(encoder);
4574
4575         if (crtc->config.has_dp_encoder)
4576                 intel_dp_set_m_n(crtc);
4577
4578         I915_WRITE(DPLL(pipe), dpll);
4579
4580         /* Wait for the clocks to stabilize. */
4581         POSTING_READ(DPLL(pipe));
4582         udelay(150);
4583
4584         if (INTEL_INFO(dev)->gen >= 4) {
4585                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4586                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4587                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4588         } else {
4589                 /* The pixel multiplier can only be updated once the
4590                  * DPLL is enabled and the clocks are stable.
4591                  *
4592                  * So write it again.
4593                  */
4594                 I915_WRITE(DPLL(pipe), dpll);
4595         }
4596 }
4597
4598 static void i8xx_update_pll(struct intel_crtc *crtc,
4599                             intel_clock_t *reduced_clock,
4600                             int num_connectors)
4601 {
4602         struct drm_device *dev = crtc->base.dev;
4603         struct drm_i915_private *dev_priv = dev->dev_private;
4604         struct intel_encoder *encoder;
4605         int pipe = crtc->pipe;
4606         u32 dpll;
4607         struct dpll *clock = &crtc->config.dpll;
4608
4609         i9xx_update_pll_dividers(crtc, reduced_clock);
4610
4611         dpll = DPLL_VGA_MODE_DIS;
4612
4613         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4614                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4615         } else {
4616                 if (clock->p1 == 2)
4617                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4618                 else
4619                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4620                 if (clock->p2 == 4)
4621                         dpll |= PLL_P2_DIVIDE_BY_4;
4622         }
4623
4624         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4625                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4626                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4627         else
4628                 dpll |= PLL_REF_INPUT_DREFCLK;
4629
4630         dpll |= DPLL_VCO_ENABLE;
4631         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4632         POSTING_READ(DPLL(pipe));
4633         udelay(150);
4634
4635         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4636                 if (encoder->pre_pll_enable)
4637                         encoder->pre_pll_enable(encoder);
4638
4639         I915_WRITE(DPLL(pipe), dpll);
4640
4641         /* Wait for the clocks to stabilize. */
4642         POSTING_READ(DPLL(pipe));
4643         udelay(150);
4644
4645         /* The pixel multiplier can only be updated once the
4646          * DPLL is enabled and the clocks are stable.
4647          *
4648          * So write it again.
4649          */
4650         I915_WRITE(DPLL(pipe), dpll);
4651 }
4652
4653 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4654 {
4655         struct drm_device *dev = intel_crtc->base.dev;
4656         struct drm_i915_private *dev_priv = dev->dev_private;
4657         enum pipe pipe = intel_crtc->pipe;
4658         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4659         struct drm_display_mode *adjusted_mode =
4660                 &intel_crtc->config.adjusted_mode;
4661         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4662         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4663
4664         /* We need to be careful not to changed the adjusted mode, for otherwise
4665          * the hw state checker will get angry at the mismatch. */
4666         crtc_vtotal = adjusted_mode->crtc_vtotal;
4667         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4668
4669         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4670                 /* the chip adds 2 halflines automatically */
4671                 crtc_vtotal -= 1;
4672                 crtc_vblank_end -= 1;
4673                 vsyncshift = adjusted_mode->crtc_hsync_start
4674                              - adjusted_mode->crtc_htotal / 2;
4675         } else {
4676                 vsyncshift = 0;
4677         }
4678
4679         if (INTEL_INFO(dev)->gen > 3)
4680                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4681
4682         I915_WRITE(HTOTAL(cpu_transcoder),
4683                    (adjusted_mode->crtc_hdisplay - 1) |
4684                    ((adjusted_mode->crtc_htotal - 1) << 16));
4685         I915_WRITE(HBLANK(cpu_transcoder),
4686                    (adjusted_mode->crtc_hblank_start - 1) |
4687                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4688         I915_WRITE(HSYNC(cpu_transcoder),
4689                    (adjusted_mode->crtc_hsync_start - 1) |
4690                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4691
4692         I915_WRITE(VTOTAL(cpu_transcoder),
4693                    (adjusted_mode->crtc_vdisplay - 1) |
4694                    ((crtc_vtotal - 1) << 16));
4695         I915_WRITE(VBLANK(cpu_transcoder),
4696                    (adjusted_mode->crtc_vblank_start - 1) |
4697                    ((crtc_vblank_end - 1) << 16));
4698         I915_WRITE(VSYNC(cpu_transcoder),
4699                    (adjusted_mode->crtc_vsync_start - 1) |
4700                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4701
4702         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4703          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4704          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4705          * bits. */
4706         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4707             (pipe == PIPE_B || pipe == PIPE_C))
4708                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4709
4710         /* pipesrc controls the size that is scaled from, which should
4711          * always be the user's requested size.
4712          */
4713         I915_WRITE(PIPESRC(pipe),
4714                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4715 }
4716
4717 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4718                                    struct intel_crtc_config *pipe_config)
4719 {
4720         struct drm_device *dev = crtc->base.dev;
4721         struct drm_i915_private *dev_priv = dev->dev_private;
4722         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4723         uint32_t tmp;
4724
4725         tmp = I915_READ(HTOTAL(cpu_transcoder));
4726         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4727         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4728         tmp = I915_READ(HBLANK(cpu_transcoder));
4729         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4730         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4731         tmp = I915_READ(HSYNC(cpu_transcoder));
4732         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4733         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4734
4735         tmp = I915_READ(VTOTAL(cpu_transcoder));
4736         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4737         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4738         tmp = I915_READ(VBLANK(cpu_transcoder));
4739         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4740         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4741         tmp = I915_READ(VSYNC(cpu_transcoder));
4742         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4743         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4744
4745         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4746                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4747                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4748                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4749         }
4750
4751         tmp = I915_READ(PIPESRC(crtc->pipe));
4752         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4753         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4754 }
4755
4756 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4757 {
4758         struct drm_device *dev = intel_crtc->base.dev;
4759         struct drm_i915_private *dev_priv = dev->dev_private;
4760         uint32_t pipeconf;
4761
4762         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4763
4764         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4765                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4766                  * core speed.
4767                  *
4768                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4769                  * pipe == 0 check?
4770                  */
4771                 if (intel_crtc->config.requested_mode.clock >
4772                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4773                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4774                 else
4775                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4776         }
4777
4778         /* only g4x and later have fancy bpc/dither controls */
4779         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4780                 pipeconf &= ~(PIPECONF_BPC_MASK |
4781                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4782
4783                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4784                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4785                         pipeconf |= PIPECONF_DITHER_EN |
4786                                     PIPECONF_DITHER_TYPE_SP;
4787
4788                 switch (intel_crtc->config.pipe_bpp) {
4789                 case 18:
4790                         pipeconf |= PIPECONF_6BPC;
4791                         break;
4792                 case 24:
4793                         pipeconf |= PIPECONF_8BPC;
4794                         break;
4795                 case 30:
4796                         pipeconf |= PIPECONF_10BPC;
4797                         break;
4798                 default:
4799                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4800                         BUG();
4801                 }
4802         }
4803
4804         if (HAS_PIPE_CXSR(dev)) {
4805                 if (intel_crtc->lowfreq_avail) {
4806                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4807                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4808                 } else {
4809                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4810                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4811                 }
4812         }
4813
4814         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4815         if (!IS_GEN2(dev) &&
4816             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4817                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4818         else
4819                 pipeconf |= PIPECONF_PROGRESSIVE;
4820
4821         if (IS_VALLEYVIEW(dev)) {
4822                 if (intel_crtc->config.limited_color_range)
4823                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4824                 else
4825                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4826         }
4827
4828         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4829         POSTING_READ(PIPECONF(intel_crtc->pipe));
4830 }
4831
4832 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4833                               int x, int y,
4834                               struct drm_framebuffer *fb)
4835 {
4836         struct drm_device *dev = crtc->dev;
4837         struct drm_i915_private *dev_priv = dev->dev_private;
4838         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4839         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4840         int pipe = intel_crtc->pipe;
4841         int plane = intel_crtc->plane;
4842         int refclk, num_connectors = 0;
4843         intel_clock_t clock, reduced_clock;
4844         u32 dspcntr;
4845         bool ok, has_reduced_clock = false;
4846         bool is_lvds = false;
4847         struct intel_encoder *encoder;
4848         const intel_limit_t *limit;
4849         int ret;
4850
4851         for_each_encoder_on_crtc(dev, crtc, encoder) {
4852                 switch (encoder->type) {
4853                 case INTEL_OUTPUT_LVDS:
4854                         is_lvds = true;
4855                         break;
4856                 }
4857
4858                 num_connectors++;
4859         }
4860
4861         refclk = i9xx_get_refclk(crtc, num_connectors);
4862
4863         /*
4864          * Returns a set of divisors for the desired target clock with the given
4865          * refclk, or FALSE.  The returned values represent the clock equation:
4866          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4867          */
4868         limit = intel_limit(crtc, refclk);
4869         ok = dev_priv->display.find_dpll(limit, crtc,
4870                                          intel_crtc->config.port_clock,
4871                                          refclk, NULL, &clock);
4872         if (!ok && !intel_crtc->config.clock_set) {
4873                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4874                 return -EINVAL;
4875         }
4876
4877         /* Ensure that the cursor is valid for the new mode before changing... */
4878         intel_crtc_update_cursor(crtc, true);
4879
4880         if (is_lvds && dev_priv->lvds_downclock_avail) {
4881                 /*
4882                  * Ensure we match the reduced clock's P to the target clock.
4883                  * If the clocks don't match, we can't switch the display clock
4884                  * by using the FP0/FP1. In such case we will disable the LVDS
4885                  * downclock feature.
4886                 */
4887                 has_reduced_clock =
4888                         dev_priv->display.find_dpll(limit, crtc,
4889                                                     dev_priv->lvds_downclock,
4890                                                     refclk, &clock,
4891                                                     &reduced_clock);
4892         }
4893         /* Compat-code for transition, will disappear. */
4894         if (!intel_crtc->config.clock_set) {
4895                 intel_crtc->config.dpll.n = clock.n;
4896                 intel_crtc->config.dpll.m1 = clock.m1;
4897                 intel_crtc->config.dpll.m2 = clock.m2;
4898                 intel_crtc->config.dpll.p1 = clock.p1;
4899                 intel_crtc->config.dpll.p2 = clock.p2;
4900         }
4901
4902         if (IS_GEN2(dev))
4903                 i8xx_update_pll(intel_crtc,
4904                                 has_reduced_clock ? &reduced_clock : NULL,
4905                                 num_connectors);
4906         else if (IS_VALLEYVIEW(dev))
4907                 vlv_update_pll(intel_crtc);
4908         else
4909                 i9xx_update_pll(intel_crtc,
4910                                 has_reduced_clock ? &reduced_clock : NULL,
4911                                 num_connectors);
4912
4913         /* Set up the display plane register */
4914         dspcntr = DISPPLANE_GAMMA_ENABLE;
4915
4916         if (!IS_VALLEYVIEW(dev)) {
4917                 if (pipe == 0)
4918                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4919                 else
4920                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4921         }
4922
4923         intel_set_pipe_timings(intel_crtc);
4924
4925         /* pipesrc and dspsize control the size that is scaled from,
4926          * which should always be the user's requested size.
4927          */
4928         I915_WRITE(DSPSIZE(plane),
4929                    ((mode->vdisplay - 1) << 16) |
4930                    (mode->hdisplay - 1));
4931         I915_WRITE(DSPPOS(plane), 0);
4932
4933         i9xx_set_pipeconf(intel_crtc);
4934
4935         I915_WRITE(DSPCNTR(plane), dspcntr);
4936         POSTING_READ(DSPCNTR(plane));
4937
4938         ret = intel_pipe_set_base(crtc, x, y, fb);
4939
4940         intel_update_watermarks(dev);
4941
4942         return ret;
4943 }
4944
4945 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4946                                  struct intel_crtc_config *pipe_config)
4947 {
4948         struct drm_device *dev = crtc->base.dev;
4949         struct drm_i915_private *dev_priv = dev->dev_private;
4950         uint32_t tmp;
4951
4952         tmp = I915_READ(PFIT_CONTROL);
4953
4954         if (INTEL_INFO(dev)->gen < 4) {
4955                 if (crtc->pipe != PIPE_B)
4956                         return;
4957
4958                 /* gen2/3 store dither state in pfit control, needs to match */
4959                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4960         } else {
4961                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4962                         return;
4963         }
4964
4965         if (!(tmp & PFIT_ENABLE))
4966                 return;
4967
4968         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4969         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4970         if (INTEL_INFO(dev)->gen < 5)
4971                 pipe_config->gmch_pfit.lvds_border_bits =
4972                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4973 }
4974
4975 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4976                                  struct intel_crtc_config *pipe_config)
4977 {
4978         struct drm_device *dev = crtc->base.dev;
4979         struct drm_i915_private *dev_priv = dev->dev_private;
4980         uint32_t tmp;
4981
4982         pipe_config->cpu_transcoder = crtc->pipe;
4983
4984         tmp = I915_READ(PIPECONF(crtc->pipe));
4985         if (!(tmp & PIPECONF_ENABLE))
4986                 return false;
4987
4988         intel_get_pipe_timings(crtc, pipe_config);
4989
4990         i9xx_get_pfit_config(crtc, pipe_config);
4991
4992         return true;
4993 }
4994
4995 static void ironlake_init_pch_refclk(struct drm_device *dev)
4996 {
4997         struct drm_i915_private *dev_priv = dev->dev_private;
4998         struct drm_mode_config *mode_config = &dev->mode_config;
4999         struct intel_encoder *encoder;
5000         u32 val, final;
5001         bool has_lvds = false;
5002         bool has_cpu_edp = false;
5003         bool has_panel = false;
5004         bool has_ck505 = false;
5005         bool can_ssc = false;
5006
5007         /* We need to take the global config into account */
5008         list_for_each_entry(encoder, &mode_config->encoder_list,
5009                             base.head) {
5010                 switch (encoder->type) {
5011                 case INTEL_OUTPUT_LVDS:
5012                         has_panel = true;
5013                         has_lvds = true;
5014                         break;
5015                 case INTEL_OUTPUT_EDP:
5016                         has_panel = true;
5017                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5018                                 has_cpu_edp = true;
5019                         break;
5020                 }
5021         }
5022
5023         if (HAS_PCH_IBX(dev)) {
5024                 has_ck505 = dev_priv->vbt.display_clock_mode;
5025                 can_ssc = has_ck505;
5026         } else {
5027                 has_ck505 = false;
5028                 can_ssc = true;
5029         }
5030
5031         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5032                       has_panel, has_lvds, has_ck505);
5033
5034         /* Ironlake: try to setup display ref clock before DPLL
5035          * enabling. This is only under driver's control after
5036          * PCH B stepping, previous chipset stepping should be
5037          * ignoring this setting.
5038          */
5039         val = I915_READ(PCH_DREF_CONTROL);
5040
5041         /* As we must carefully and slowly disable/enable each source in turn,
5042          * compute the final state we want first and check if we need to
5043          * make any changes at all.
5044          */
5045         final = val;
5046         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5047         if (has_ck505)
5048                 final |= DREF_NONSPREAD_CK505_ENABLE;
5049         else
5050                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5051
5052         final &= ~DREF_SSC_SOURCE_MASK;
5053         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5054         final &= ~DREF_SSC1_ENABLE;
5055
5056         if (has_panel) {
5057                 final |= DREF_SSC_SOURCE_ENABLE;
5058
5059                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5060                         final |= DREF_SSC1_ENABLE;
5061
5062                 if (has_cpu_edp) {
5063                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5064                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5065                         else
5066                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5067                 } else
5068                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5069         } else {
5070                 final |= DREF_SSC_SOURCE_DISABLE;
5071                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5072         }
5073
5074         if (final == val)
5075                 return;
5076
5077         /* Always enable nonspread source */
5078         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5079
5080         if (has_ck505)
5081                 val |= DREF_NONSPREAD_CK505_ENABLE;
5082         else
5083                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5084
5085         if (has_panel) {
5086                 val &= ~DREF_SSC_SOURCE_MASK;
5087                 val |= DREF_SSC_SOURCE_ENABLE;
5088
5089                 /* SSC must be turned on before enabling the CPU output  */
5090                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5091                         DRM_DEBUG_KMS("Using SSC on panel\n");
5092                         val |= DREF_SSC1_ENABLE;
5093                 } else
5094                         val &= ~DREF_SSC1_ENABLE;
5095
5096                 /* Get SSC going before enabling the outputs */
5097                 I915_WRITE(PCH_DREF_CONTROL, val);
5098                 POSTING_READ(PCH_DREF_CONTROL);
5099                 udelay(200);
5100
5101                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5102
5103                 /* Enable CPU source on CPU attached eDP */
5104                 if (has_cpu_edp) {
5105                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5106                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5107                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5108                         }
5109                         else
5110                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5111                 } else
5112                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5113
5114                 I915_WRITE(PCH_DREF_CONTROL, val);
5115                 POSTING_READ(PCH_DREF_CONTROL);
5116                 udelay(200);
5117         } else {
5118                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5119
5120                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5121
5122                 /* Turn off CPU output */
5123                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5124
5125                 I915_WRITE(PCH_DREF_CONTROL, val);
5126                 POSTING_READ(PCH_DREF_CONTROL);
5127                 udelay(200);
5128
5129                 /* Turn off the SSC source */
5130                 val &= ~DREF_SSC_SOURCE_MASK;
5131                 val |= DREF_SSC_SOURCE_DISABLE;
5132
5133                 /* Turn off SSC1 */
5134                 val &= ~DREF_SSC1_ENABLE;
5135
5136                 I915_WRITE(PCH_DREF_CONTROL, val);
5137                 POSTING_READ(PCH_DREF_CONTROL);
5138                 udelay(200);
5139         }
5140
5141         BUG_ON(val != final);
5142 }
5143
5144 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5145 static void lpt_init_pch_refclk(struct drm_device *dev)
5146 {
5147         struct drm_i915_private *dev_priv = dev->dev_private;
5148         struct drm_mode_config *mode_config = &dev->mode_config;
5149         struct intel_encoder *encoder;
5150         bool has_vga = false;
5151         bool is_sdv = false;
5152         u32 tmp;
5153
5154         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5155                 switch (encoder->type) {
5156                 case INTEL_OUTPUT_ANALOG:
5157                         has_vga = true;
5158                         break;
5159                 }
5160         }
5161
5162         if (!has_vga)
5163                 return;
5164
5165         mutex_lock(&dev_priv->dpio_lock);
5166
5167         /* XXX: Rip out SDV support once Haswell ships for real. */
5168         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5169                 is_sdv = true;
5170
5171         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5172         tmp &= ~SBI_SSCCTL_DISABLE;
5173         tmp |= SBI_SSCCTL_PATHALT;
5174         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5175
5176         udelay(24);
5177
5178         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5179         tmp &= ~SBI_SSCCTL_PATHALT;
5180         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5181
5182         if (!is_sdv) {
5183                 tmp = I915_READ(SOUTH_CHICKEN2);
5184                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5185                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5186
5187                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5188                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5189                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5190
5191                 tmp = I915_READ(SOUTH_CHICKEN2);
5192                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5193                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5194
5195                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5196                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5197                                        100))
5198                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5199         }
5200
5201         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5202         tmp &= ~(0xFF << 24);
5203         tmp |= (0x12 << 24);
5204         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5205
5206         if (is_sdv) {
5207                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5208                 tmp |= 0x7FFF;
5209                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5210         }
5211
5212         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5213         tmp |= (1 << 11);
5214         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5215
5216         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5217         tmp |= (1 << 11);
5218         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5219
5220         if (is_sdv) {
5221                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5222                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5223                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5224
5225                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5226                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5227                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5228
5229                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5230                 tmp |= (0x3F << 8);
5231                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5232
5233                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5234                 tmp |= (0x3F << 8);
5235                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5236         }
5237
5238         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5239         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5240         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5241
5242         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5243         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5244         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5245
5246         if (!is_sdv) {
5247                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5248                 tmp &= ~(7 << 13);
5249                 tmp |= (5 << 13);
5250                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5251
5252                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5253                 tmp &= ~(7 << 13);
5254                 tmp |= (5 << 13);
5255                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5256         }
5257
5258         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5259         tmp &= ~0xFF;
5260         tmp |= 0x1C;
5261         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5262
5263         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5264         tmp &= ~0xFF;
5265         tmp |= 0x1C;
5266         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5267
5268         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5269         tmp &= ~(0xFF << 16);
5270         tmp |= (0x1C << 16);
5271         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5272
5273         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5274         tmp &= ~(0xFF << 16);
5275         tmp |= (0x1C << 16);
5276         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5277
5278         if (!is_sdv) {
5279                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5280                 tmp |= (1 << 27);
5281                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5282
5283                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5284                 tmp |= (1 << 27);
5285                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5286
5287                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5288                 tmp &= ~(0xF << 28);
5289                 tmp |= (4 << 28);
5290                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5291
5292                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5293                 tmp &= ~(0xF << 28);
5294                 tmp |= (4 << 28);
5295                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5296         }
5297
5298         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5299         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5300         tmp |= SBI_DBUFF0_ENABLE;
5301         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5302
5303         mutex_unlock(&dev_priv->dpio_lock);
5304 }
5305
5306 /*
5307  * Initialize reference clocks when the driver loads
5308  */
5309 void intel_init_pch_refclk(struct drm_device *dev)
5310 {
5311         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5312                 ironlake_init_pch_refclk(dev);
5313         else if (HAS_PCH_LPT(dev))
5314                 lpt_init_pch_refclk(dev);
5315 }
5316
5317 static int ironlake_get_refclk(struct drm_crtc *crtc)
5318 {
5319         struct drm_device *dev = crtc->dev;
5320         struct drm_i915_private *dev_priv = dev->dev_private;
5321         struct intel_encoder *encoder;
5322         int num_connectors = 0;
5323         bool is_lvds = false;
5324
5325         for_each_encoder_on_crtc(dev, crtc, encoder) {
5326                 switch (encoder->type) {
5327                 case INTEL_OUTPUT_LVDS:
5328                         is_lvds = true;
5329                         break;
5330                 }
5331                 num_connectors++;
5332         }
5333
5334         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5335                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5336                               dev_priv->vbt.lvds_ssc_freq);
5337                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5338         }
5339
5340         return 120000;
5341 }
5342
5343 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5344 {
5345         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5346         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5347         int pipe = intel_crtc->pipe;
5348         uint32_t val;
5349
5350         val = I915_READ(PIPECONF(pipe));
5351
5352         val &= ~PIPECONF_BPC_MASK;
5353         switch (intel_crtc->config.pipe_bpp) {
5354         case 18:
5355                 val |= PIPECONF_6BPC;
5356                 break;
5357         case 24:
5358                 val |= PIPECONF_8BPC;
5359                 break;
5360         case 30:
5361                 val |= PIPECONF_10BPC;
5362                 break;
5363         case 36:
5364                 val |= PIPECONF_12BPC;
5365                 break;
5366         default:
5367                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5368                 BUG();
5369         }
5370
5371         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5372         if (intel_crtc->config.dither)
5373                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5374
5375         val &= ~PIPECONF_INTERLACE_MASK;
5376         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5377                 val |= PIPECONF_INTERLACED_ILK;
5378         else
5379                 val |= PIPECONF_PROGRESSIVE;
5380
5381         if (intel_crtc->config.limited_color_range)
5382                 val |= PIPECONF_COLOR_RANGE_SELECT;
5383         else
5384                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5385
5386         I915_WRITE(PIPECONF(pipe), val);
5387         POSTING_READ(PIPECONF(pipe));
5388 }
5389
5390 /*
5391  * Set up the pipe CSC unit.
5392  *
5393  * Currently only full range RGB to limited range RGB conversion
5394  * is supported, but eventually this should handle various
5395  * RGB<->YCbCr scenarios as well.
5396  */
5397 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5398 {
5399         struct drm_device *dev = crtc->dev;
5400         struct drm_i915_private *dev_priv = dev->dev_private;
5401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5402         int pipe = intel_crtc->pipe;
5403         uint16_t coeff = 0x7800; /* 1.0 */
5404
5405         /*
5406          * TODO: Check what kind of values actually come out of the pipe
5407          * with these coeff/postoff values and adjust to get the best
5408          * accuracy. Perhaps we even need to take the bpc value into
5409          * consideration.
5410          */
5411
5412         if (intel_crtc->config.limited_color_range)
5413                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5414
5415         /*
5416          * GY/GU and RY/RU should be the other way around according
5417          * to BSpec, but reality doesn't agree. Just set them up in
5418          * a way that results in the correct picture.
5419          */
5420         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5421         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5422
5423         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5424         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5425
5426         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5427         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5428
5429         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5430         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5431         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5432
5433         if (INTEL_INFO(dev)->gen > 6) {
5434                 uint16_t postoff = 0;
5435
5436                 if (intel_crtc->config.limited_color_range)
5437                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5438
5439                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5440                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5441                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5442
5443                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5444         } else {
5445                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5446
5447                 if (intel_crtc->config.limited_color_range)
5448                         mode |= CSC_BLACK_SCREEN_OFFSET;
5449
5450                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5451         }
5452 }
5453
5454 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5455 {
5456         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5458         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5459         uint32_t val;
5460
5461         val = I915_READ(PIPECONF(cpu_transcoder));
5462
5463         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5464         if (intel_crtc->config.dither)
5465                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5466
5467         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5468         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5469                 val |= PIPECONF_INTERLACED_ILK;
5470         else
5471                 val |= PIPECONF_PROGRESSIVE;
5472
5473         I915_WRITE(PIPECONF(cpu_transcoder), val);
5474         POSTING_READ(PIPECONF(cpu_transcoder));
5475 }
5476
5477 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5478                                     intel_clock_t *clock,
5479                                     bool *has_reduced_clock,
5480                                     intel_clock_t *reduced_clock)
5481 {
5482         struct drm_device *dev = crtc->dev;
5483         struct drm_i915_private *dev_priv = dev->dev_private;
5484         struct intel_encoder *intel_encoder;
5485         int refclk;
5486         const intel_limit_t *limit;
5487         bool ret, is_lvds = false;
5488
5489         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5490                 switch (intel_encoder->type) {
5491                 case INTEL_OUTPUT_LVDS:
5492                         is_lvds = true;
5493                         break;
5494                 }
5495         }
5496
5497         refclk = ironlake_get_refclk(crtc);
5498
5499         /*
5500          * Returns a set of divisors for the desired target clock with the given
5501          * refclk, or FALSE.  The returned values represent the clock equation:
5502          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5503          */
5504         limit = intel_limit(crtc, refclk);
5505         ret = dev_priv->display.find_dpll(limit, crtc,
5506                                           to_intel_crtc(crtc)->config.port_clock,
5507                                           refclk, NULL, clock);
5508         if (!ret)
5509                 return false;
5510
5511         if (is_lvds && dev_priv->lvds_downclock_avail) {
5512                 /*
5513                  * Ensure we match the reduced clock's P to the target clock.
5514                  * If the clocks don't match, we can't switch the display clock
5515                  * by using the FP0/FP1. In such case we will disable the LVDS
5516                  * downclock feature.
5517                 */
5518                 *has_reduced_clock =
5519                         dev_priv->display.find_dpll(limit, crtc,
5520                                                     dev_priv->lvds_downclock,
5521                                                     refclk, clock,
5522                                                     reduced_clock);
5523         }
5524
5525         return true;
5526 }
5527
5528 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5529 {
5530         struct drm_i915_private *dev_priv = dev->dev_private;
5531         uint32_t temp;
5532
5533         temp = I915_READ(SOUTH_CHICKEN1);
5534         if (temp & FDI_BC_BIFURCATION_SELECT)
5535                 return;
5536
5537         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5538         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5539
5540         temp |= FDI_BC_BIFURCATION_SELECT;
5541         DRM_DEBUG_KMS("enabling fdi C rx\n");
5542         I915_WRITE(SOUTH_CHICKEN1, temp);
5543         POSTING_READ(SOUTH_CHICKEN1);
5544 }
5545
5546 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5547 {
5548         struct drm_device *dev = intel_crtc->base.dev;
5549         struct drm_i915_private *dev_priv = dev->dev_private;
5550
5551         switch (intel_crtc->pipe) {
5552         case PIPE_A:
5553                 break;
5554         case PIPE_B:
5555                 if (intel_crtc->config.fdi_lanes > 2)
5556                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5557                 else
5558                         cpt_enable_fdi_bc_bifurcation(dev);
5559
5560                 break;
5561         case PIPE_C:
5562                 cpt_enable_fdi_bc_bifurcation(dev);
5563
5564                 break;
5565         default:
5566                 BUG();
5567         }
5568 }
5569
5570 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5571 {
5572         /*
5573          * Account for spread spectrum to avoid
5574          * oversubscribing the link. Max center spread
5575          * is 2.5%; use 5% for safety's sake.
5576          */
5577         u32 bps = target_clock * bpp * 21 / 20;
5578         return bps / (link_bw * 8) + 1;
5579 }
5580
5581 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5582 {
5583         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5584 }
5585
5586 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5587                                       u32 *fp,
5588                                       intel_clock_t *reduced_clock, u32 *fp2)
5589 {
5590         struct drm_crtc *crtc = &intel_crtc->base;
5591         struct drm_device *dev = crtc->dev;
5592         struct drm_i915_private *dev_priv = dev->dev_private;
5593         struct intel_encoder *intel_encoder;
5594         uint32_t dpll;
5595         int factor, num_connectors = 0;
5596         bool is_lvds = false, is_sdvo = false;
5597
5598         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5599                 switch (intel_encoder->type) {
5600                 case INTEL_OUTPUT_LVDS:
5601                         is_lvds = true;
5602                         break;
5603                 case INTEL_OUTPUT_SDVO:
5604                 case INTEL_OUTPUT_HDMI:
5605                         is_sdvo = true;
5606                         break;
5607                 }
5608
5609                 num_connectors++;
5610         }
5611
5612         /* Enable autotuning of the PLL clock (if permissible) */
5613         factor = 21;
5614         if (is_lvds) {
5615                 if ((intel_panel_use_ssc(dev_priv) &&
5616                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5617                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5618                         factor = 25;
5619         } else if (intel_crtc->config.sdvo_tv_clock)
5620                 factor = 20;
5621
5622         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5623                 *fp |= FP_CB_TUNE;
5624
5625         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5626                 *fp2 |= FP_CB_TUNE;
5627
5628         dpll = 0;
5629
5630         if (is_lvds)
5631                 dpll |= DPLLB_MODE_LVDS;
5632         else
5633                 dpll |= DPLLB_MODE_DAC_SERIAL;
5634
5635         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5636                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5637
5638         if (is_sdvo)
5639                 dpll |= DPLL_DVO_HIGH_SPEED;
5640         if (intel_crtc->config.has_dp_encoder)
5641                 dpll |= DPLL_DVO_HIGH_SPEED;
5642
5643         /* compute bitmask from p1 value */
5644         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5645         /* also FPA1 */
5646         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5647
5648         switch (intel_crtc->config.dpll.p2) {
5649         case 5:
5650                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5651                 break;
5652         case 7:
5653                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5654                 break;
5655         case 10:
5656                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5657                 break;
5658         case 14:
5659                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5660                 break;
5661         }
5662
5663         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5664                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5665         else
5666                 dpll |= PLL_REF_INPUT_DREFCLK;
5667
5668         return dpll;
5669 }
5670
5671 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5672                                   int x, int y,
5673                                   struct drm_framebuffer *fb)
5674 {
5675         struct drm_device *dev = crtc->dev;
5676         struct drm_i915_private *dev_priv = dev->dev_private;
5677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5678         int pipe = intel_crtc->pipe;
5679         int plane = intel_crtc->plane;
5680         int num_connectors = 0;
5681         intel_clock_t clock, reduced_clock;
5682         u32 dpll = 0, fp = 0, fp2 = 0;
5683         bool ok, has_reduced_clock = false;
5684         bool is_lvds = false;
5685         struct intel_encoder *encoder;
5686         int ret;
5687
5688         for_each_encoder_on_crtc(dev, crtc, encoder) {
5689                 switch (encoder->type) {
5690                 case INTEL_OUTPUT_LVDS:
5691                         is_lvds = true;
5692                         break;
5693                 }
5694
5695                 num_connectors++;
5696         }
5697
5698         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5699              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5700
5701         ok = ironlake_compute_clocks(crtc, &clock,
5702                                      &has_reduced_clock, &reduced_clock);
5703         if (!ok && !intel_crtc->config.clock_set) {
5704                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5705                 return -EINVAL;
5706         }
5707         /* Compat-code for transition, will disappear. */
5708         if (!intel_crtc->config.clock_set) {
5709                 intel_crtc->config.dpll.n = clock.n;
5710                 intel_crtc->config.dpll.m1 = clock.m1;
5711                 intel_crtc->config.dpll.m2 = clock.m2;
5712                 intel_crtc->config.dpll.p1 = clock.p1;
5713                 intel_crtc->config.dpll.p2 = clock.p2;
5714         }
5715
5716         /* Ensure that the cursor is valid for the new mode before changing... */
5717         intel_crtc_update_cursor(crtc, true);
5718
5719         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5720         if (intel_crtc->config.has_pch_encoder) {
5721                 struct intel_pch_pll *pll;
5722
5723                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5724                 if (has_reduced_clock)
5725                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5726
5727                 dpll = ironlake_compute_dpll(intel_crtc,
5728                                              &fp, &reduced_clock,
5729                                              has_reduced_clock ? &fp2 : NULL);
5730
5731                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5732                 if (pll == NULL) {
5733                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5734                                          pipe_name(pipe));
5735                         return -EINVAL;
5736                 }
5737         } else
5738                 intel_put_pch_pll(intel_crtc);
5739
5740         if (intel_crtc->config.has_dp_encoder)
5741                 intel_dp_set_m_n(intel_crtc);
5742
5743         for_each_encoder_on_crtc(dev, crtc, encoder)
5744                 if (encoder->pre_pll_enable)
5745                         encoder->pre_pll_enable(encoder);
5746
5747         if (intel_crtc->pch_pll) {
5748                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5749
5750                 /* Wait for the clocks to stabilize. */
5751                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5752                 udelay(150);
5753
5754                 /* The pixel multiplier can only be updated once the
5755                  * DPLL is enabled and the clocks are stable.
5756                  *
5757                  * So write it again.
5758                  */
5759                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5760         }
5761
5762         intel_crtc->lowfreq_avail = false;
5763         if (intel_crtc->pch_pll) {
5764                 if (is_lvds && has_reduced_clock && i915_powersave) {
5765                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5766                         intel_crtc->lowfreq_avail = true;
5767                 } else {
5768                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5769                 }
5770         }
5771
5772         intel_set_pipe_timings(intel_crtc);
5773
5774         if (intel_crtc->config.has_pch_encoder) {
5775                 intel_cpu_transcoder_set_m_n(intel_crtc,
5776                                              &intel_crtc->config.fdi_m_n);
5777         }
5778
5779         if (IS_IVYBRIDGE(dev))
5780                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5781
5782         ironlake_set_pipeconf(crtc);
5783
5784         /* Set up the display plane register */
5785         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5786         POSTING_READ(DSPCNTR(plane));
5787
5788         ret = intel_pipe_set_base(crtc, x, y, fb);
5789
5790         intel_update_watermarks(dev);
5791
5792         return ret;
5793 }
5794
5795 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5796                                         struct intel_crtc_config *pipe_config)
5797 {
5798         struct drm_device *dev = crtc->base.dev;
5799         struct drm_i915_private *dev_priv = dev->dev_private;
5800         enum transcoder transcoder = pipe_config->cpu_transcoder;
5801
5802         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5803         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5804         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5805                                         & ~TU_SIZE_MASK;
5806         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5807         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5808                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5809 }
5810
5811 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5812                                      struct intel_crtc_config *pipe_config)
5813 {
5814         struct drm_device *dev = crtc->base.dev;
5815         struct drm_i915_private *dev_priv = dev->dev_private;
5816         uint32_t tmp;
5817
5818         tmp = I915_READ(PF_CTL(crtc->pipe));
5819
5820         if (tmp & PF_ENABLE) {
5821                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5822                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5823
5824                 /* We currently do not free assignements of panel fitters on
5825                  * ivb/hsw (since we don't use the higher upscaling modes which
5826                  * differentiates them) so just WARN about this case for now. */
5827                 if (IS_GEN7(dev)) {
5828                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5829                                 PF_PIPE_SEL_IVB(crtc->pipe));
5830                 }
5831         }
5832 }
5833
5834 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5835                                      struct intel_crtc_config *pipe_config)
5836 {
5837         struct drm_device *dev = crtc->base.dev;
5838         struct drm_i915_private *dev_priv = dev->dev_private;
5839         uint32_t tmp;
5840
5841         pipe_config->cpu_transcoder = crtc->pipe;
5842
5843         tmp = I915_READ(PIPECONF(crtc->pipe));
5844         if (!(tmp & PIPECONF_ENABLE))
5845                 return false;
5846
5847         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5848                 pipe_config->has_pch_encoder = true;
5849
5850                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5851                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5852                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5853
5854                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5855         }
5856
5857         intel_get_pipe_timings(crtc, pipe_config);
5858
5859         ironlake_get_pfit_config(crtc, pipe_config);
5860
5861         return true;
5862 }
5863
5864 static void haswell_modeset_global_resources(struct drm_device *dev)
5865 {
5866         bool enable = false;
5867         struct intel_crtc *crtc;
5868
5869         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5870                 if (!crtc->base.enabled)
5871                         continue;
5872
5873                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5874                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5875                         enable = true;
5876         }
5877
5878         intel_set_power_well(dev, enable);
5879 }
5880
5881 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5882                                  int x, int y,
5883                                  struct drm_framebuffer *fb)
5884 {
5885         struct drm_device *dev = crtc->dev;
5886         struct drm_i915_private *dev_priv = dev->dev_private;
5887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5888         int plane = intel_crtc->plane;
5889         int ret;
5890
5891         if (!intel_ddi_pll_mode_set(crtc))
5892                 return -EINVAL;
5893
5894         /* Ensure that the cursor is valid for the new mode before changing... */
5895         intel_crtc_update_cursor(crtc, true);
5896
5897         if (intel_crtc->config.has_dp_encoder)
5898                 intel_dp_set_m_n(intel_crtc);
5899
5900         intel_crtc->lowfreq_avail = false;
5901
5902         intel_set_pipe_timings(intel_crtc);
5903
5904         if (intel_crtc->config.has_pch_encoder) {
5905                 intel_cpu_transcoder_set_m_n(intel_crtc,
5906                                              &intel_crtc->config.fdi_m_n);
5907         }
5908
5909         haswell_set_pipeconf(crtc);
5910
5911         intel_set_pipe_csc(crtc);
5912
5913         /* Set up the display plane register */
5914         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5915         POSTING_READ(DSPCNTR(plane));
5916
5917         ret = intel_pipe_set_base(crtc, x, y, fb);
5918
5919         intel_update_watermarks(dev);
5920
5921         return ret;
5922 }
5923
5924 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5925                                     struct intel_crtc_config *pipe_config)
5926 {
5927         struct drm_device *dev = crtc->base.dev;
5928         struct drm_i915_private *dev_priv = dev->dev_private;
5929         enum intel_display_power_domain pfit_domain;
5930         uint32_t tmp;
5931
5932         pipe_config->cpu_transcoder = crtc->pipe;
5933         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5934         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5935                 enum pipe trans_edp_pipe;
5936                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5937                 default:
5938                         WARN(1, "unknown pipe linked to edp transcoder\n");
5939                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5940                 case TRANS_DDI_EDP_INPUT_A_ON:
5941                         trans_edp_pipe = PIPE_A;
5942                         break;
5943                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5944                         trans_edp_pipe = PIPE_B;
5945                         break;
5946                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5947                         trans_edp_pipe = PIPE_C;
5948                         break;
5949                 }
5950
5951                 if (trans_edp_pipe == crtc->pipe)
5952                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5953         }
5954
5955         if (!intel_display_power_enabled(dev,
5956                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5957                 return false;
5958
5959         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5960         if (!(tmp & PIPECONF_ENABLE))
5961                 return false;
5962
5963         /*
5964          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5965          * DDI E. So just check whether this pipe is wired to DDI E and whether
5966          * the PCH transcoder is on.
5967          */
5968         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5969         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5970             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5971                 pipe_config->has_pch_encoder = true;
5972
5973                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5974                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5975                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5976
5977                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5978         }
5979
5980         intel_get_pipe_timings(crtc, pipe_config);
5981
5982         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5983         if (intel_display_power_enabled(dev, pfit_domain))
5984                 ironlake_get_pfit_config(crtc, pipe_config);
5985
5986         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5987                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
5988
5989         return true;
5990 }
5991
5992 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5993                                int x, int y,
5994                                struct drm_framebuffer *fb)
5995 {
5996         struct drm_device *dev = crtc->dev;
5997         struct drm_i915_private *dev_priv = dev->dev_private;
5998         struct drm_encoder_helper_funcs *encoder_funcs;
5999         struct intel_encoder *encoder;
6000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6001         struct drm_display_mode *adjusted_mode =
6002                 &intel_crtc->config.adjusted_mode;
6003         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6004         int pipe = intel_crtc->pipe;
6005         int ret;
6006
6007         drm_vblank_pre_modeset(dev, pipe);
6008
6009         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6010
6011         drm_vblank_post_modeset(dev, pipe);
6012
6013         if (ret != 0)
6014                 return ret;
6015
6016         for_each_encoder_on_crtc(dev, crtc, encoder) {
6017                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6018                         encoder->base.base.id,
6019                         drm_get_encoder_name(&encoder->base),
6020                         mode->base.id, mode->name);
6021                 if (encoder->mode_set) {
6022                         encoder->mode_set(encoder);
6023                 } else {
6024                         encoder_funcs = encoder->base.helper_private;
6025                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6026                 }
6027         }
6028
6029         return 0;
6030 }
6031
6032 static bool intel_eld_uptodate(struct drm_connector *connector,
6033                                int reg_eldv, uint32_t bits_eldv,
6034                                int reg_elda, uint32_t bits_elda,
6035                                int reg_edid)
6036 {
6037         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6038         uint8_t *eld = connector->eld;
6039         uint32_t i;
6040
6041         i = I915_READ(reg_eldv);
6042         i &= bits_eldv;
6043
6044         if (!eld[0])
6045                 return !i;
6046
6047         if (!i)
6048                 return false;
6049
6050         i = I915_READ(reg_elda);
6051         i &= ~bits_elda;
6052         I915_WRITE(reg_elda, i);
6053
6054         for (i = 0; i < eld[2]; i++)
6055                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6056                         return false;
6057
6058         return true;
6059 }
6060
6061 static void g4x_write_eld(struct drm_connector *connector,
6062                           struct drm_crtc *crtc)
6063 {
6064         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6065         uint8_t *eld = connector->eld;
6066         uint32_t eldv;
6067         uint32_t len;
6068         uint32_t i;
6069
6070         i = I915_READ(G4X_AUD_VID_DID);
6071
6072         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6073                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6074         else
6075                 eldv = G4X_ELDV_DEVCTG;
6076
6077         if (intel_eld_uptodate(connector,
6078                                G4X_AUD_CNTL_ST, eldv,
6079                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6080                                G4X_HDMIW_HDMIEDID))
6081                 return;
6082
6083         i = I915_READ(G4X_AUD_CNTL_ST);
6084         i &= ~(eldv | G4X_ELD_ADDR);
6085         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6086         I915_WRITE(G4X_AUD_CNTL_ST, i);
6087
6088         if (!eld[0])
6089                 return;
6090
6091         len = min_t(uint8_t, eld[2], len);
6092         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6093         for (i = 0; i < len; i++)
6094                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6095
6096         i = I915_READ(G4X_AUD_CNTL_ST);
6097         i |= eldv;
6098         I915_WRITE(G4X_AUD_CNTL_ST, i);
6099 }
6100
6101 static void haswell_write_eld(struct drm_connector *connector,
6102                                      struct drm_crtc *crtc)
6103 {
6104         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6105         uint8_t *eld = connector->eld;
6106         struct drm_device *dev = crtc->dev;
6107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6108         uint32_t eldv;
6109         uint32_t i;
6110         int len;
6111         int pipe = to_intel_crtc(crtc)->pipe;
6112         int tmp;
6113
6114         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6115         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6116         int aud_config = HSW_AUD_CFG(pipe);
6117         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6118
6119
6120         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6121
6122         /* Audio output enable */
6123         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6124         tmp = I915_READ(aud_cntrl_st2);
6125         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6126         I915_WRITE(aud_cntrl_st2, tmp);
6127
6128         /* Wait for 1 vertical blank */
6129         intel_wait_for_vblank(dev, pipe);
6130
6131         /* Set ELD valid state */
6132         tmp = I915_READ(aud_cntrl_st2);
6133         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6134         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6135         I915_WRITE(aud_cntrl_st2, tmp);
6136         tmp = I915_READ(aud_cntrl_st2);
6137         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6138
6139         /* Enable HDMI mode */
6140         tmp = I915_READ(aud_config);
6141         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6142         /* clear N_programing_enable and N_value_index */
6143         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6144         I915_WRITE(aud_config, tmp);
6145
6146         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6147
6148         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6149         intel_crtc->eld_vld = true;
6150
6151         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6152                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6153                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6154                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6155         } else
6156                 I915_WRITE(aud_config, 0);
6157
6158         if (intel_eld_uptodate(connector,
6159                                aud_cntrl_st2, eldv,
6160                                aud_cntl_st, IBX_ELD_ADDRESS,
6161                                hdmiw_hdmiedid))
6162                 return;
6163
6164         i = I915_READ(aud_cntrl_st2);
6165         i &= ~eldv;
6166         I915_WRITE(aud_cntrl_st2, i);
6167
6168         if (!eld[0])
6169                 return;
6170
6171         i = I915_READ(aud_cntl_st);
6172         i &= ~IBX_ELD_ADDRESS;
6173         I915_WRITE(aud_cntl_st, i);
6174         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6175         DRM_DEBUG_DRIVER("port num:%d\n", i);
6176
6177         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6178         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6179         for (i = 0; i < len; i++)
6180                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6181
6182         i = I915_READ(aud_cntrl_st2);
6183         i |= eldv;
6184         I915_WRITE(aud_cntrl_st2, i);
6185
6186 }
6187
6188 static void ironlake_write_eld(struct drm_connector *connector,
6189                                      struct drm_crtc *crtc)
6190 {
6191         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6192         uint8_t *eld = connector->eld;
6193         uint32_t eldv;
6194         uint32_t i;
6195         int len;
6196         int hdmiw_hdmiedid;
6197         int aud_config;
6198         int aud_cntl_st;
6199         int aud_cntrl_st2;
6200         int pipe = to_intel_crtc(crtc)->pipe;
6201
6202         if (HAS_PCH_IBX(connector->dev)) {
6203                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6204                 aud_config = IBX_AUD_CFG(pipe);
6205                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6206                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6207         } else {
6208                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6209                 aud_config = CPT_AUD_CFG(pipe);
6210                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6211                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6212         }
6213
6214         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6215
6216         i = I915_READ(aud_cntl_st);
6217         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6218         if (!i) {
6219                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6220                 /* operate blindly on all ports */
6221                 eldv = IBX_ELD_VALIDB;
6222                 eldv |= IBX_ELD_VALIDB << 4;
6223                 eldv |= IBX_ELD_VALIDB << 8;
6224         } else {
6225                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6226                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6227         }
6228
6229         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6230                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6231                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6232                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6233         } else
6234                 I915_WRITE(aud_config, 0);
6235
6236         if (intel_eld_uptodate(connector,
6237                                aud_cntrl_st2, eldv,
6238                                aud_cntl_st, IBX_ELD_ADDRESS,
6239                                hdmiw_hdmiedid))
6240                 return;
6241
6242         i = I915_READ(aud_cntrl_st2);
6243         i &= ~eldv;
6244         I915_WRITE(aud_cntrl_st2, i);
6245
6246         if (!eld[0])
6247                 return;
6248
6249         i = I915_READ(aud_cntl_st);
6250         i &= ~IBX_ELD_ADDRESS;
6251         I915_WRITE(aud_cntl_st, i);
6252
6253         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6254         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6255         for (i = 0; i < len; i++)
6256                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6257
6258         i = I915_READ(aud_cntrl_st2);
6259         i |= eldv;
6260         I915_WRITE(aud_cntrl_st2, i);
6261 }
6262
6263 void intel_write_eld(struct drm_encoder *encoder,
6264                      struct drm_display_mode *mode)
6265 {
6266         struct drm_crtc *crtc = encoder->crtc;
6267         struct drm_connector *connector;
6268         struct drm_device *dev = encoder->dev;
6269         struct drm_i915_private *dev_priv = dev->dev_private;
6270
6271         connector = drm_select_eld(encoder, mode);
6272         if (!connector)
6273                 return;
6274
6275         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6276                          connector->base.id,
6277                          drm_get_connector_name(connector),
6278                          connector->encoder->base.id,
6279                          drm_get_encoder_name(connector->encoder));
6280
6281         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6282
6283         if (dev_priv->display.write_eld)
6284                 dev_priv->display.write_eld(connector, crtc);
6285 }
6286
6287 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6288 void intel_crtc_load_lut(struct drm_crtc *crtc)
6289 {
6290         struct drm_device *dev = crtc->dev;
6291         struct drm_i915_private *dev_priv = dev->dev_private;
6292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6293         enum pipe pipe = intel_crtc->pipe;
6294         int palreg = PALETTE(pipe);
6295         int i;
6296         bool reenable_ips = false;
6297
6298         /* The clocks have to be on to load the palette. */
6299         if (!crtc->enabled || !intel_crtc->active)
6300                 return;
6301
6302         /* use legacy palette for Ironlake */
6303         if (HAS_PCH_SPLIT(dev))
6304                 palreg = LGC_PALETTE(pipe);
6305
6306         /* Workaround : Do not read or write the pipe palette/gamma data while
6307          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6308          */
6309         if (intel_crtc->config.ips_enabled &&
6310             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6311              GAMMA_MODE_MODE_SPLIT)) {
6312                 hsw_disable_ips(intel_crtc);
6313                 reenable_ips = true;
6314         }
6315
6316         for (i = 0; i < 256; i++) {
6317                 I915_WRITE(palreg + 4 * i,
6318                            (intel_crtc->lut_r[i] << 16) |
6319                            (intel_crtc->lut_g[i] << 8) |
6320                            intel_crtc->lut_b[i]);
6321         }
6322
6323         if (reenable_ips)
6324                 hsw_enable_ips(intel_crtc);
6325 }
6326
6327 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6328 {
6329         struct drm_device *dev = crtc->dev;
6330         struct drm_i915_private *dev_priv = dev->dev_private;
6331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6332         bool visible = base != 0;
6333         u32 cntl;
6334
6335         if (intel_crtc->cursor_visible == visible)
6336                 return;
6337
6338         cntl = I915_READ(_CURACNTR);
6339         if (visible) {
6340                 /* On these chipsets we can only modify the base whilst
6341                  * the cursor is disabled.
6342                  */
6343                 I915_WRITE(_CURABASE, base);
6344
6345                 cntl &= ~(CURSOR_FORMAT_MASK);
6346                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6347                 cntl |= CURSOR_ENABLE |
6348                         CURSOR_GAMMA_ENABLE |
6349                         CURSOR_FORMAT_ARGB;
6350         } else
6351                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6352         I915_WRITE(_CURACNTR, cntl);
6353
6354         intel_crtc->cursor_visible = visible;
6355 }
6356
6357 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6358 {
6359         struct drm_device *dev = crtc->dev;
6360         struct drm_i915_private *dev_priv = dev->dev_private;
6361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362         int pipe = intel_crtc->pipe;
6363         bool visible = base != 0;
6364
6365         if (intel_crtc->cursor_visible != visible) {
6366                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6367                 if (base) {
6368                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6369                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6370                         cntl |= pipe << 28; /* Connect to correct pipe */
6371                 } else {
6372                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6373                         cntl |= CURSOR_MODE_DISABLE;
6374                 }
6375                 I915_WRITE(CURCNTR(pipe), cntl);
6376
6377                 intel_crtc->cursor_visible = visible;
6378         }
6379         /* and commit changes on next vblank */
6380         I915_WRITE(CURBASE(pipe), base);
6381 }
6382
6383 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6384 {
6385         struct drm_device *dev = crtc->dev;
6386         struct drm_i915_private *dev_priv = dev->dev_private;
6387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6388         int pipe = intel_crtc->pipe;
6389         bool visible = base != 0;
6390
6391         if (intel_crtc->cursor_visible != visible) {
6392                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6393                 if (base) {
6394                         cntl &= ~CURSOR_MODE;
6395                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6396                 } else {
6397                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6398                         cntl |= CURSOR_MODE_DISABLE;
6399                 }
6400                 if (IS_HASWELL(dev))
6401                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6402                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6403
6404                 intel_crtc->cursor_visible = visible;
6405         }
6406         /* and commit changes on next vblank */
6407         I915_WRITE(CURBASE_IVB(pipe), base);
6408 }
6409
6410 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6411 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6412                                      bool on)
6413 {
6414         struct drm_device *dev = crtc->dev;
6415         struct drm_i915_private *dev_priv = dev->dev_private;
6416         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6417         int pipe = intel_crtc->pipe;
6418         int x = intel_crtc->cursor_x;
6419         int y = intel_crtc->cursor_y;
6420         u32 base, pos;
6421         bool visible;
6422
6423         pos = 0;
6424
6425         if (on && crtc->enabled && crtc->fb) {
6426                 base = intel_crtc->cursor_addr;
6427                 if (x > (int) crtc->fb->width)
6428                         base = 0;
6429
6430                 if (y > (int) crtc->fb->height)
6431                         base = 0;
6432         } else
6433                 base = 0;
6434
6435         if (x < 0) {
6436                 if (x + intel_crtc->cursor_width < 0)
6437                         base = 0;
6438
6439                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6440                 x = -x;
6441         }
6442         pos |= x << CURSOR_X_SHIFT;
6443
6444         if (y < 0) {
6445                 if (y + intel_crtc->cursor_height < 0)
6446                         base = 0;
6447
6448                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6449                 y = -y;
6450         }
6451         pos |= y << CURSOR_Y_SHIFT;
6452
6453         visible = base != 0;
6454         if (!visible && !intel_crtc->cursor_visible)
6455                 return;
6456
6457         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6458                 I915_WRITE(CURPOS_IVB(pipe), pos);
6459                 ivb_update_cursor(crtc, base);
6460         } else {
6461                 I915_WRITE(CURPOS(pipe), pos);
6462                 if (IS_845G(dev) || IS_I865G(dev))
6463                         i845_update_cursor(crtc, base);
6464                 else
6465                         i9xx_update_cursor(crtc, base);
6466         }
6467 }
6468
6469 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6470                                  struct drm_file *file,
6471                                  uint32_t handle,
6472                                  uint32_t width, uint32_t height)
6473 {
6474         struct drm_device *dev = crtc->dev;
6475         struct drm_i915_private *dev_priv = dev->dev_private;
6476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6477         struct drm_i915_gem_object *obj;
6478         uint32_t addr;
6479         int ret;
6480
6481         /* if we want to turn off the cursor ignore width and height */
6482         if (!handle) {
6483                 DRM_DEBUG_KMS("cursor off\n");
6484                 addr = 0;
6485                 obj = NULL;
6486                 mutex_lock(&dev->struct_mutex);
6487                 goto finish;
6488         }
6489
6490         /* Currently we only support 64x64 cursors */
6491         if (width != 64 || height != 64) {
6492                 DRM_ERROR("we currently only support 64x64 cursors\n");
6493                 return -EINVAL;
6494         }
6495
6496         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6497         if (&obj->base == NULL)
6498                 return -ENOENT;
6499
6500         if (obj->base.size < width * height * 4) {
6501                 DRM_ERROR("buffer is to small\n");
6502                 ret = -ENOMEM;
6503                 goto fail;
6504         }
6505
6506         /* we only need to pin inside GTT if cursor is non-phy */
6507         mutex_lock(&dev->struct_mutex);
6508         if (!dev_priv->info->cursor_needs_physical) {
6509                 unsigned alignment;
6510
6511                 if (obj->tiling_mode) {
6512                         DRM_ERROR("cursor cannot be tiled\n");
6513                         ret = -EINVAL;
6514                         goto fail_locked;
6515                 }
6516
6517                 /* Note that the w/a also requires 2 PTE of padding following
6518                  * the bo. We currently fill all unused PTE with the shadow
6519                  * page and so we should always have valid PTE following the
6520                  * cursor preventing the VT-d warning.
6521                  */
6522                 alignment = 0;
6523                 if (need_vtd_wa(dev))
6524                         alignment = 64*1024;
6525
6526                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6527                 if (ret) {
6528                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6529                         goto fail_locked;
6530                 }
6531
6532                 ret = i915_gem_object_put_fence(obj);
6533                 if (ret) {
6534                         DRM_ERROR("failed to release fence for cursor");
6535                         goto fail_unpin;
6536                 }
6537
6538                 addr = obj->gtt_offset;
6539         } else {
6540                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6541                 ret = i915_gem_attach_phys_object(dev, obj,
6542                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6543                                                   align);
6544                 if (ret) {
6545                         DRM_ERROR("failed to attach phys object\n");
6546                         goto fail_locked;
6547                 }
6548                 addr = obj->phys_obj->handle->busaddr;
6549         }
6550
6551         if (IS_GEN2(dev))
6552                 I915_WRITE(CURSIZE, (height << 12) | width);
6553
6554  finish:
6555         if (intel_crtc->cursor_bo) {
6556                 if (dev_priv->info->cursor_needs_physical) {
6557                         if (intel_crtc->cursor_bo != obj)
6558                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6559                 } else
6560                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6561                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6562         }
6563
6564         mutex_unlock(&dev->struct_mutex);
6565
6566         intel_crtc->cursor_addr = addr;
6567         intel_crtc->cursor_bo = obj;
6568         intel_crtc->cursor_width = width;
6569         intel_crtc->cursor_height = height;
6570
6571         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6572
6573         return 0;
6574 fail_unpin:
6575         i915_gem_object_unpin(obj);
6576 fail_locked:
6577         mutex_unlock(&dev->struct_mutex);
6578 fail:
6579         drm_gem_object_unreference_unlocked(&obj->base);
6580         return ret;
6581 }
6582
6583 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6584 {
6585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6586
6587         intel_crtc->cursor_x = x;
6588         intel_crtc->cursor_y = y;
6589
6590         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6591
6592         return 0;
6593 }
6594
6595 /** Sets the color ramps on behalf of RandR */
6596 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6597                                  u16 blue, int regno)
6598 {
6599         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6600
6601         intel_crtc->lut_r[regno] = red >> 8;
6602         intel_crtc->lut_g[regno] = green >> 8;
6603         intel_crtc->lut_b[regno] = blue >> 8;
6604 }
6605
6606 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6607                              u16 *blue, int regno)
6608 {
6609         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6610
6611         *red = intel_crtc->lut_r[regno] << 8;
6612         *green = intel_crtc->lut_g[regno] << 8;
6613         *blue = intel_crtc->lut_b[regno] << 8;
6614 }
6615
6616 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6617                                  u16 *blue, uint32_t start, uint32_t size)
6618 {
6619         int end = (start + size > 256) ? 256 : start + size, i;
6620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6621
6622         for (i = start; i < end; i++) {
6623                 intel_crtc->lut_r[i] = red[i] >> 8;
6624                 intel_crtc->lut_g[i] = green[i] >> 8;
6625                 intel_crtc->lut_b[i] = blue[i] >> 8;
6626         }
6627
6628         intel_crtc_load_lut(crtc);
6629 }
6630
6631 /* VESA 640x480x72Hz mode to set on the pipe */
6632 static struct drm_display_mode load_detect_mode = {
6633         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6634                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6635 };
6636
6637 static struct drm_framebuffer *
6638 intel_framebuffer_create(struct drm_device *dev,
6639                          struct drm_mode_fb_cmd2 *mode_cmd,
6640                          struct drm_i915_gem_object *obj)
6641 {
6642         struct intel_framebuffer *intel_fb;
6643         int ret;
6644
6645         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6646         if (!intel_fb) {
6647                 drm_gem_object_unreference_unlocked(&obj->base);
6648                 return ERR_PTR(-ENOMEM);
6649         }
6650
6651         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6652         if (ret) {
6653                 drm_gem_object_unreference_unlocked(&obj->base);
6654                 kfree(intel_fb);
6655                 return ERR_PTR(ret);
6656         }
6657
6658         return &intel_fb->base;
6659 }
6660
6661 static u32
6662 intel_framebuffer_pitch_for_width(int width, int bpp)
6663 {
6664         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6665         return ALIGN(pitch, 64);
6666 }
6667
6668 static u32
6669 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6670 {
6671         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6672         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6673 }
6674
6675 static struct drm_framebuffer *
6676 intel_framebuffer_create_for_mode(struct drm_device *dev,
6677                                   struct drm_display_mode *mode,
6678                                   int depth, int bpp)
6679 {
6680         struct drm_i915_gem_object *obj;
6681         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6682
6683         obj = i915_gem_alloc_object(dev,
6684                                     intel_framebuffer_size_for_mode(mode, bpp));
6685         if (obj == NULL)
6686                 return ERR_PTR(-ENOMEM);
6687
6688         mode_cmd.width = mode->hdisplay;
6689         mode_cmd.height = mode->vdisplay;
6690         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6691                                                                 bpp);
6692         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6693
6694         return intel_framebuffer_create(dev, &mode_cmd, obj);
6695 }
6696
6697 static struct drm_framebuffer *
6698 mode_fits_in_fbdev(struct drm_device *dev,
6699                    struct drm_display_mode *mode)
6700 {
6701         struct drm_i915_private *dev_priv = dev->dev_private;
6702         struct drm_i915_gem_object *obj;
6703         struct drm_framebuffer *fb;
6704
6705         if (dev_priv->fbdev == NULL)
6706                 return NULL;
6707
6708         obj = dev_priv->fbdev->ifb.obj;
6709         if (obj == NULL)
6710                 return NULL;
6711
6712         fb = &dev_priv->fbdev->ifb.base;
6713         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6714                                                                fb->bits_per_pixel))
6715                 return NULL;
6716
6717         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6718                 return NULL;
6719
6720         return fb;
6721 }
6722
6723 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6724                                 struct drm_display_mode *mode,
6725                                 struct intel_load_detect_pipe *old)
6726 {
6727         struct intel_crtc *intel_crtc;
6728         struct intel_encoder *intel_encoder =
6729                 intel_attached_encoder(connector);
6730         struct drm_crtc *possible_crtc;
6731         struct drm_encoder *encoder = &intel_encoder->base;
6732         struct drm_crtc *crtc = NULL;
6733         struct drm_device *dev = encoder->dev;
6734         struct drm_framebuffer *fb;
6735         int i = -1;
6736
6737         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6738                       connector->base.id, drm_get_connector_name(connector),
6739                       encoder->base.id, drm_get_encoder_name(encoder));
6740
6741         /*
6742          * Algorithm gets a little messy:
6743          *
6744          *   - if the connector already has an assigned crtc, use it (but make
6745          *     sure it's on first)
6746          *
6747          *   - try to find the first unused crtc that can drive this connector,
6748          *     and use that if we find one
6749          */
6750
6751         /* See if we already have a CRTC for this connector */
6752         if (encoder->crtc) {
6753                 crtc = encoder->crtc;
6754
6755                 mutex_lock(&crtc->mutex);
6756
6757                 old->dpms_mode = connector->dpms;
6758                 old->load_detect_temp = false;
6759
6760                 /* Make sure the crtc and connector are running */
6761                 if (connector->dpms != DRM_MODE_DPMS_ON)
6762                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6763
6764                 return true;
6765         }
6766
6767         /* Find an unused one (if possible) */
6768         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6769                 i++;
6770                 if (!(encoder->possible_crtcs & (1 << i)))
6771                         continue;
6772                 if (!possible_crtc->enabled) {
6773                         crtc = possible_crtc;
6774                         break;
6775                 }
6776         }
6777
6778         /*
6779          * If we didn't find an unused CRTC, don't use any.
6780          */
6781         if (!crtc) {
6782                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6783                 return false;
6784         }
6785
6786         mutex_lock(&crtc->mutex);
6787         intel_encoder->new_crtc = to_intel_crtc(crtc);
6788         to_intel_connector(connector)->new_encoder = intel_encoder;
6789
6790         intel_crtc = to_intel_crtc(crtc);
6791         old->dpms_mode = connector->dpms;
6792         old->load_detect_temp = true;
6793         old->release_fb = NULL;
6794
6795         if (!mode)
6796                 mode = &load_detect_mode;
6797
6798         /* We need a framebuffer large enough to accommodate all accesses
6799          * that the plane may generate whilst we perform load detection.
6800          * We can not rely on the fbcon either being present (we get called
6801          * during its initialisation to detect all boot displays, or it may
6802          * not even exist) or that it is large enough to satisfy the
6803          * requested mode.
6804          */
6805         fb = mode_fits_in_fbdev(dev, mode);
6806         if (fb == NULL) {
6807                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6808                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6809                 old->release_fb = fb;
6810         } else
6811                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6812         if (IS_ERR(fb)) {
6813                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6814                 mutex_unlock(&crtc->mutex);
6815                 return false;
6816         }
6817
6818         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6819                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6820                 if (old->release_fb)
6821                         old->release_fb->funcs->destroy(old->release_fb);
6822                 mutex_unlock(&crtc->mutex);
6823                 return false;
6824         }
6825
6826         /* let the connector get through one full cycle before testing */
6827         intel_wait_for_vblank(dev, intel_crtc->pipe);
6828         return true;
6829 }
6830
6831 void intel_release_load_detect_pipe(struct drm_connector *connector,
6832                                     struct intel_load_detect_pipe *old)
6833 {
6834         struct intel_encoder *intel_encoder =
6835                 intel_attached_encoder(connector);
6836         struct drm_encoder *encoder = &intel_encoder->base;
6837         struct drm_crtc *crtc = encoder->crtc;
6838
6839         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6840                       connector->base.id, drm_get_connector_name(connector),
6841                       encoder->base.id, drm_get_encoder_name(encoder));
6842
6843         if (old->load_detect_temp) {
6844                 to_intel_connector(connector)->new_encoder = NULL;
6845                 intel_encoder->new_crtc = NULL;
6846                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6847
6848                 if (old->release_fb) {
6849                         drm_framebuffer_unregister_private(old->release_fb);
6850                         drm_framebuffer_unreference(old->release_fb);
6851                 }
6852
6853                 mutex_unlock(&crtc->mutex);
6854                 return;
6855         }
6856
6857         /* Switch crtc and encoder back off if necessary */
6858         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6859                 connector->funcs->dpms(connector, old->dpms_mode);
6860
6861         mutex_unlock(&crtc->mutex);
6862 }
6863
6864 /* Returns the clock of the currently programmed mode of the given pipe. */
6865 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6866 {
6867         struct drm_i915_private *dev_priv = dev->dev_private;
6868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6869         int pipe = intel_crtc->pipe;
6870         u32 dpll = I915_READ(DPLL(pipe));
6871         u32 fp;
6872         intel_clock_t clock;
6873
6874         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6875                 fp = I915_READ(FP0(pipe));
6876         else
6877                 fp = I915_READ(FP1(pipe));
6878
6879         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6880         if (IS_PINEVIEW(dev)) {
6881                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6882                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6883         } else {
6884                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6885                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6886         }
6887
6888         if (!IS_GEN2(dev)) {
6889                 if (IS_PINEVIEW(dev))
6890                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6891                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6892                 else
6893                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6894                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6895
6896                 switch (dpll & DPLL_MODE_MASK) {
6897                 case DPLLB_MODE_DAC_SERIAL:
6898                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6899                                 5 : 10;
6900                         break;
6901                 case DPLLB_MODE_LVDS:
6902                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6903                                 7 : 14;
6904                         break;
6905                 default:
6906                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6907                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6908                         return 0;
6909                 }
6910
6911                 if (IS_PINEVIEW(dev))
6912                         pineview_clock(96000, &clock);
6913                 else
6914                         i9xx_clock(96000, &clock);
6915         } else {
6916                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6917
6918                 if (is_lvds) {
6919                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6920                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6921                         clock.p2 = 14;
6922
6923                         if ((dpll & PLL_REF_INPUT_MASK) ==
6924                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6925                                 /* XXX: might not be 66MHz */
6926                                 i9xx_clock(66000, &clock);
6927                         } else
6928                                 i9xx_clock(48000, &clock);
6929                 } else {
6930                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6931                                 clock.p1 = 2;
6932                         else {
6933                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6934                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6935                         }
6936                         if (dpll & PLL_P2_DIVIDE_BY_4)
6937                                 clock.p2 = 4;
6938                         else
6939                                 clock.p2 = 2;
6940
6941                         i9xx_clock(48000, &clock);
6942                 }
6943         }
6944
6945         /* XXX: It would be nice to validate the clocks, but we can't reuse
6946          * i830PllIsValid() because it relies on the xf86_config connector
6947          * configuration being accurate, which it isn't necessarily.
6948          */
6949
6950         return clock.dot;
6951 }
6952
6953 /** Returns the currently programmed mode of the given pipe. */
6954 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6955                                              struct drm_crtc *crtc)
6956 {
6957         struct drm_i915_private *dev_priv = dev->dev_private;
6958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6959         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6960         struct drm_display_mode *mode;
6961         int htot = I915_READ(HTOTAL(cpu_transcoder));
6962         int hsync = I915_READ(HSYNC(cpu_transcoder));
6963         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6964         int vsync = I915_READ(VSYNC(cpu_transcoder));
6965
6966         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6967         if (!mode)
6968                 return NULL;
6969
6970         mode->clock = intel_crtc_clock_get(dev, crtc);
6971         mode->hdisplay = (htot & 0xffff) + 1;
6972         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6973         mode->hsync_start = (hsync & 0xffff) + 1;
6974         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6975         mode->vdisplay = (vtot & 0xffff) + 1;
6976         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6977         mode->vsync_start = (vsync & 0xffff) + 1;
6978         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6979
6980         drm_mode_set_name(mode);
6981
6982         return mode;
6983 }
6984
6985 static void intel_increase_pllclock(struct drm_crtc *crtc)
6986 {
6987         struct drm_device *dev = crtc->dev;
6988         drm_i915_private_t *dev_priv = dev->dev_private;
6989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6990         int pipe = intel_crtc->pipe;
6991         int dpll_reg = DPLL(pipe);
6992         int dpll;
6993
6994         if (HAS_PCH_SPLIT(dev))
6995                 return;
6996
6997         if (!dev_priv->lvds_downclock_avail)
6998                 return;
6999
7000         dpll = I915_READ(dpll_reg);
7001         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7002                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7003
7004                 assert_panel_unlocked(dev_priv, pipe);
7005
7006                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7007                 I915_WRITE(dpll_reg, dpll);
7008                 intel_wait_for_vblank(dev, pipe);
7009
7010                 dpll = I915_READ(dpll_reg);
7011                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7012                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7013         }
7014 }
7015
7016 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7017 {
7018         struct drm_device *dev = crtc->dev;
7019         drm_i915_private_t *dev_priv = dev->dev_private;
7020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7021
7022         if (HAS_PCH_SPLIT(dev))
7023                 return;
7024
7025         if (!dev_priv->lvds_downclock_avail)
7026                 return;
7027
7028         /*
7029          * Since this is called by a timer, we should never get here in
7030          * the manual case.
7031          */
7032         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7033                 int pipe = intel_crtc->pipe;
7034                 int dpll_reg = DPLL(pipe);
7035                 int dpll;
7036
7037                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7038
7039                 assert_panel_unlocked(dev_priv, pipe);
7040
7041                 dpll = I915_READ(dpll_reg);
7042                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7043                 I915_WRITE(dpll_reg, dpll);
7044                 intel_wait_for_vblank(dev, pipe);
7045                 dpll = I915_READ(dpll_reg);
7046                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7047                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7048         }
7049
7050 }
7051
7052 void intel_mark_busy(struct drm_device *dev)
7053 {
7054         i915_update_gfx_val(dev->dev_private);
7055 }
7056
7057 void intel_mark_idle(struct drm_device *dev)
7058 {
7059         struct drm_crtc *crtc;
7060
7061         if (!i915_powersave)
7062                 return;
7063
7064         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7065                 if (!crtc->fb)
7066                         continue;
7067
7068                 intel_decrease_pllclock(crtc);
7069         }
7070 }
7071
7072 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7073 {
7074         struct drm_device *dev = obj->base.dev;
7075         struct drm_crtc *crtc;
7076
7077         if (!i915_powersave)
7078                 return;
7079
7080         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7081                 if (!crtc->fb)
7082                         continue;
7083
7084                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7085                         intel_increase_pllclock(crtc);
7086         }
7087 }
7088
7089 static void intel_crtc_destroy(struct drm_crtc *crtc)
7090 {
7091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7092         struct drm_device *dev = crtc->dev;
7093         struct intel_unpin_work *work;
7094         unsigned long flags;
7095
7096         spin_lock_irqsave(&dev->event_lock, flags);
7097         work = intel_crtc->unpin_work;
7098         intel_crtc->unpin_work = NULL;
7099         spin_unlock_irqrestore(&dev->event_lock, flags);
7100
7101         if (work) {
7102                 cancel_work_sync(&work->work);
7103                 kfree(work);
7104         }
7105
7106         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7107
7108         drm_crtc_cleanup(crtc);
7109
7110         kfree(intel_crtc);
7111 }
7112
7113 static void intel_unpin_work_fn(struct work_struct *__work)
7114 {
7115         struct intel_unpin_work *work =
7116                 container_of(__work, struct intel_unpin_work, work);
7117         struct drm_device *dev = work->crtc->dev;
7118
7119         mutex_lock(&dev->struct_mutex);
7120         intel_unpin_fb_obj(work->old_fb_obj);
7121         drm_gem_object_unreference(&work->pending_flip_obj->base);
7122         drm_gem_object_unreference(&work->old_fb_obj->base);
7123
7124         intel_update_fbc(dev);
7125         mutex_unlock(&dev->struct_mutex);
7126
7127         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7128         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7129
7130         kfree(work);
7131 }
7132
7133 static void do_intel_finish_page_flip(struct drm_device *dev,
7134                                       struct drm_crtc *crtc)
7135 {
7136         drm_i915_private_t *dev_priv = dev->dev_private;
7137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138         struct intel_unpin_work *work;
7139         unsigned long flags;
7140
7141         /* Ignore early vblank irqs */
7142         if (intel_crtc == NULL)
7143                 return;
7144
7145         spin_lock_irqsave(&dev->event_lock, flags);
7146         work = intel_crtc->unpin_work;
7147
7148         /* Ensure we don't miss a work->pending update ... */
7149         smp_rmb();
7150
7151         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7152                 spin_unlock_irqrestore(&dev->event_lock, flags);
7153                 return;
7154         }
7155
7156         /* and that the unpin work is consistent wrt ->pending. */
7157         smp_rmb();
7158
7159         intel_crtc->unpin_work = NULL;
7160
7161         if (work->event)
7162                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7163
7164         drm_vblank_put(dev, intel_crtc->pipe);
7165
7166         spin_unlock_irqrestore(&dev->event_lock, flags);
7167
7168         wake_up_all(&dev_priv->pending_flip_queue);
7169
7170         queue_work(dev_priv->wq, &work->work);
7171
7172         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7173 }
7174
7175 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7176 {
7177         drm_i915_private_t *dev_priv = dev->dev_private;
7178         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7179
7180         do_intel_finish_page_flip(dev, crtc);
7181 }
7182
7183 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7184 {
7185         drm_i915_private_t *dev_priv = dev->dev_private;
7186         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7187
7188         do_intel_finish_page_flip(dev, crtc);
7189 }
7190
7191 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7192 {
7193         drm_i915_private_t *dev_priv = dev->dev_private;
7194         struct intel_crtc *intel_crtc =
7195                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7196         unsigned long flags;
7197
7198         /* NB: An MMIO update of the plane base pointer will also
7199          * generate a page-flip completion irq, i.e. every modeset
7200          * is also accompanied by a spurious intel_prepare_page_flip().
7201          */
7202         spin_lock_irqsave(&dev->event_lock, flags);
7203         if (intel_crtc->unpin_work)
7204                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7205         spin_unlock_irqrestore(&dev->event_lock, flags);
7206 }
7207
7208 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7209 {
7210         /* Ensure that the work item is consistent when activating it ... */
7211         smp_wmb();
7212         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7213         /* and that it is marked active as soon as the irq could fire. */
7214         smp_wmb();
7215 }
7216
7217 static int intel_gen2_queue_flip(struct drm_device *dev,
7218                                  struct drm_crtc *crtc,
7219                                  struct drm_framebuffer *fb,
7220                                  struct drm_i915_gem_object *obj)
7221 {
7222         struct drm_i915_private *dev_priv = dev->dev_private;
7223         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7224         u32 flip_mask;
7225         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7226         int ret;
7227
7228         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7229         if (ret)
7230                 goto err;
7231
7232         ret = intel_ring_begin(ring, 6);
7233         if (ret)
7234                 goto err_unpin;
7235
7236         /* Can't queue multiple flips, so wait for the previous
7237          * one to finish before executing the next.
7238          */
7239         if (intel_crtc->plane)
7240                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7241         else
7242                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7243         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7244         intel_ring_emit(ring, MI_NOOP);
7245         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7246                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7247         intel_ring_emit(ring, fb->pitches[0]);
7248         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7249         intel_ring_emit(ring, 0); /* aux display base address, unused */
7250
7251         intel_mark_page_flip_active(intel_crtc);
7252         intel_ring_advance(ring);
7253         return 0;
7254
7255 err_unpin:
7256         intel_unpin_fb_obj(obj);
7257 err:
7258         return ret;
7259 }
7260
7261 static int intel_gen3_queue_flip(struct drm_device *dev,
7262                                  struct drm_crtc *crtc,
7263                                  struct drm_framebuffer *fb,
7264                                  struct drm_i915_gem_object *obj)
7265 {
7266         struct drm_i915_private *dev_priv = dev->dev_private;
7267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7268         u32 flip_mask;
7269         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7270         int ret;
7271
7272         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7273         if (ret)
7274                 goto err;
7275
7276         ret = intel_ring_begin(ring, 6);
7277         if (ret)
7278                 goto err_unpin;
7279
7280         if (intel_crtc->plane)
7281                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7282         else
7283                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7284         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7285         intel_ring_emit(ring, MI_NOOP);
7286         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7287                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7288         intel_ring_emit(ring, fb->pitches[0]);
7289         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7290         intel_ring_emit(ring, MI_NOOP);
7291
7292         intel_mark_page_flip_active(intel_crtc);
7293         intel_ring_advance(ring);
7294         return 0;
7295
7296 err_unpin:
7297         intel_unpin_fb_obj(obj);
7298 err:
7299         return ret;
7300 }
7301
7302 static int intel_gen4_queue_flip(struct drm_device *dev,
7303                                  struct drm_crtc *crtc,
7304                                  struct drm_framebuffer *fb,
7305                                  struct drm_i915_gem_object *obj)
7306 {
7307         struct drm_i915_private *dev_priv = dev->dev_private;
7308         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7309         uint32_t pf, pipesrc;
7310         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7311         int ret;
7312
7313         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7314         if (ret)
7315                 goto err;
7316
7317         ret = intel_ring_begin(ring, 4);
7318         if (ret)
7319                 goto err_unpin;
7320
7321         /* i965+ uses the linear or tiled offsets from the
7322          * Display Registers (which do not change across a page-flip)
7323          * so we need only reprogram the base address.
7324          */
7325         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7326                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7327         intel_ring_emit(ring, fb->pitches[0]);
7328         intel_ring_emit(ring,
7329                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7330                         obj->tiling_mode);
7331
7332         /* XXX Enabling the panel-fitter across page-flip is so far
7333          * untested on non-native modes, so ignore it for now.
7334          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7335          */
7336         pf = 0;
7337         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7338         intel_ring_emit(ring, pf | pipesrc);
7339
7340         intel_mark_page_flip_active(intel_crtc);
7341         intel_ring_advance(ring);
7342         return 0;
7343
7344 err_unpin:
7345         intel_unpin_fb_obj(obj);
7346 err:
7347         return ret;
7348 }
7349
7350 static int intel_gen6_queue_flip(struct drm_device *dev,
7351                                  struct drm_crtc *crtc,
7352                                  struct drm_framebuffer *fb,
7353                                  struct drm_i915_gem_object *obj)
7354 {
7355         struct drm_i915_private *dev_priv = dev->dev_private;
7356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7357         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7358         uint32_t pf, pipesrc;
7359         int ret;
7360
7361         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7362         if (ret)
7363                 goto err;
7364
7365         ret = intel_ring_begin(ring, 4);
7366         if (ret)
7367                 goto err_unpin;
7368
7369         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7370                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7371         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7372         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7373
7374         /* Contrary to the suggestions in the documentation,
7375          * "Enable Panel Fitter" does not seem to be required when page
7376          * flipping with a non-native mode, and worse causes a normal
7377          * modeset to fail.
7378          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7379          */
7380         pf = 0;
7381         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7382         intel_ring_emit(ring, pf | pipesrc);
7383
7384         intel_mark_page_flip_active(intel_crtc);
7385         intel_ring_advance(ring);
7386         return 0;
7387
7388 err_unpin:
7389         intel_unpin_fb_obj(obj);
7390 err:
7391         return ret;
7392 }
7393
7394 /*
7395  * On gen7 we currently use the blit ring because (in early silicon at least)
7396  * the render ring doesn't give us interrpts for page flip completion, which
7397  * means clients will hang after the first flip is queued.  Fortunately the
7398  * blit ring generates interrupts properly, so use it instead.
7399  */
7400 static int intel_gen7_queue_flip(struct drm_device *dev,
7401                                  struct drm_crtc *crtc,
7402                                  struct drm_framebuffer *fb,
7403                                  struct drm_i915_gem_object *obj)
7404 {
7405         struct drm_i915_private *dev_priv = dev->dev_private;
7406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7407         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7408         uint32_t plane_bit = 0;
7409         int ret;
7410
7411         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7412         if (ret)
7413                 goto err;
7414
7415         switch(intel_crtc->plane) {
7416         case PLANE_A:
7417                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7418                 break;
7419         case PLANE_B:
7420                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7421                 break;
7422         case PLANE_C:
7423                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7424                 break;
7425         default:
7426                 WARN_ONCE(1, "unknown plane in flip command\n");
7427                 ret = -ENODEV;
7428                 goto err_unpin;
7429         }
7430
7431         ret = intel_ring_begin(ring, 4);
7432         if (ret)
7433                 goto err_unpin;
7434
7435         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7436         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7437         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7438         intel_ring_emit(ring, (MI_NOOP));
7439
7440         intel_mark_page_flip_active(intel_crtc);
7441         intel_ring_advance(ring);
7442         return 0;
7443
7444 err_unpin:
7445         intel_unpin_fb_obj(obj);
7446 err:
7447         return ret;
7448 }
7449
7450 static int intel_default_queue_flip(struct drm_device *dev,
7451                                     struct drm_crtc *crtc,
7452                                     struct drm_framebuffer *fb,
7453                                     struct drm_i915_gem_object *obj)
7454 {
7455         return -ENODEV;
7456 }
7457
7458 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7459                                 struct drm_framebuffer *fb,
7460                                 struct drm_pending_vblank_event *event)
7461 {
7462         struct drm_device *dev = crtc->dev;
7463         struct drm_i915_private *dev_priv = dev->dev_private;
7464         struct drm_framebuffer *old_fb = crtc->fb;
7465         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7467         struct intel_unpin_work *work;
7468         unsigned long flags;
7469         int ret;
7470
7471         /* Can't change pixel format via MI display flips. */
7472         if (fb->pixel_format != crtc->fb->pixel_format)
7473                 return -EINVAL;
7474
7475         /*
7476          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7477          * Note that pitch changes could also affect these register.
7478          */
7479         if (INTEL_INFO(dev)->gen > 3 &&
7480             (fb->offsets[0] != crtc->fb->offsets[0] ||
7481              fb->pitches[0] != crtc->fb->pitches[0]))
7482                 return -EINVAL;
7483
7484         work = kzalloc(sizeof *work, GFP_KERNEL);
7485         if (work == NULL)
7486                 return -ENOMEM;
7487
7488         work->event = event;
7489         work->crtc = crtc;
7490         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7491         INIT_WORK(&work->work, intel_unpin_work_fn);
7492
7493         ret = drm_vblank_get(dev, intel_crtc->pipe);
7494         if (ret)
7495                 goto free_work;
7496
7497         /* We borrow the event spin lock for protecting unpin_work */
7498         spin_lock_irqsave(&dev->event_lock, flags);
7499         if (intel_crtc->unpin_work) {
7500                 spin_unlock_irqrestore(&dev->event_lock, flags);
7501                 kfree(work);
7502                 drm_vblank_put(dev, intel_crtc->pipe);
7503
7504                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7505                 return -EBUSY;
7506         }
7507         intel_crtc->unpin_work = work;
7508         spin_unlock_irqrestore(&dev->event_lock, flags);
7509
7510         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7511                 flush_workqueue(dev_priv->wq);
7512
7513         ret = i915_mutex_lock_interruptible(dev);
7514         if (ret)
7515                 goto cleanup;
7516
7517         /* Reference the objects for the scheduled work. */
7518         drm_gem_object_reference(&work->old_fb_obj->base);
7519         drm_gem_object_reference(&obj->base);
7520
7521         crtc->fb = fb;
7522
7523         work->pending_flip_obj = obj;
7524
7525         work->enable_stall_check = true;
7526
7527         atomic_inc(&intel_crtc->unpin_work_count);
7528         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7529
7530         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7531         if (ret)
7532                 goto cleanup_pending;
7533
7534         intel_disable_fbc(dev);
7535         intel_mark_fb_busy(obj);
7536         mutex_unlock(&dev->struct_mutex);
7537
7538         trace_i915_flip_request(intel_crtc->plane, obj);
7539
7540         return 0;
7541
7542 cleanup_pending:
7543         atomic_dec(&intel_crtc->unpin_work_count);
7544         crtc->fb = old_fb;
7545         drm_gem_object_unreference(&work->old_fb_obj->base);
7546         drm_gem_object_unreference(&obj->base);
7547         mutex_unlock(&dev->struct_mutex);
7548
7549 cleanup:
7550         spin_lock_irqsave(&dev->event_lock, flags);
7551         intel_crtc->unpin_work = NULL;
7552         spin_unlock_irqrestore(&dev->event_lock, flags);
7553
7554         drm_vblank_put(dev, intel_crtc->pipe);
7555 free_work:
7556         kfree(work);
7557
7558         return ret;
7559 }
7560
7561 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7562         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7563         .load_lut = intel_crtc_load_lut,
7564 };
7565
7566 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7567                                   struct drm_crtc *crtc)
7568 {
7569         struct drm_device *dev;
7570         struct drm_crtc *tmp;
7571         int crtc_mask = 1;
7572
7573         WARN(!crtc, "checking null crtc?\n");
7574
7575         dev = crtc->dev;
7576
7577         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7578                 if (tmp == crtc)
7579                         break;
7580                 crtc_mask <<= 1;
7581         }
7582
7583         if (encoder->possible_crtcs & crtc_mask)
7584                 return true;
7585         return false;
7586 }
7587
7588 /**
7589  * intel_modeset_update_staged_output_state
7590  *
7591  * Updates the staged output configuration state, e.g. after we've read out the
7592  * current hw state.
7593  */
7594 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7595 {
7596         struct intel_encoder *encoder;
7597         struct intel_connector *connector;
7598
7599         list_for_each_entry(connector, &dev->mode_config.connector_list,
7600                             base.head) {
7601                 connector->new_encoder =
7602                         to_intel_encoder(connector->base.encoder);
7603         }
7604
7605         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7606                             base.head) {
7607                 encoder->new_crtc =
7608                         to_intel_crtc(encoder->base.crtc);
7609         }
7610 }
7611
7612 /**
7613  * intel_modeset_commit_output_state
7614  *
7615  * This function copies the stage display pipe configuration to the real one.
7616  */
7617 static void intel_modeset_commit_output_state(struct drm_device *dev)
7618 {
7619         struct intel_encoder *encoder;
7620         struct intel_connector *connector;
7621
7622         list_for_each_entry(connector, &dev->mode_config.connector_list,
7623                             base.head) {
7624                 connector->base.encoder = &connector->new_encoder->base;
7625         }
7626
7627         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7628                             base.head) {
7629                 encoder->base.crtc = &encoder->new_crtc->base;
7630         }
7631 }
7632
7633 static void
7634 connected_sink_compute_bpp(struct intel_connector * connector,
7635                            struct intel_crtc_config *pipe_config)
7636 {
7637         int bpp = pipe_config->pipe_bpp;
7638
7639         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7640                 connector->base.base.id,
7641                 drm_get_connector_name(&connector->base));
7642
7643         /* Don't use an invalid EDID bpc value */
7644         if (connector->base.display_info.bpc &&
7645             connector->base.display_info.bpc * 3 < bpp) {
7646                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7647                               bpp, connector->base.display_info.bpc*3);
7648                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7649         }
7650
7651         /* Clamp bpp to 8 on screens without EDID 1.4 */
7652         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7653                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7654                               bpp);
7655                 pipe_config->pipe_bpp = 24;
7656         }
7657 }
7658
7659 static int
7660 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7661                           struct drm_framebuffer *fb,
7662                           struct intel_crtc_config *pipe_config)
7663 {
7664         struct drm_device *dev = crtc->base.dev;
7665         struct intel_connector *connector;
7666         int bpp;
7667
7668         switch (fb->pixel_format) {
7669         case DRM_FORMAT_C8:
7670                 bpp = 8*3; /* since we go through a colormap */
7671                 break;
7672         case DRM_FORMAT_XRGB1555:
7673         case DRM_FORMAT_ARGB1555:
7674                 /* checked in intel_framebuffer_init already */
7675                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7676                         return -EINVAL;
7677         case DRM_FORMAT_RGB565:
7678                 bpp = 6*3; /* min is 18bpp */
7679                 break;
7680         case DRM_FORMAT_XBGR8888:
7681         case DRM_FORMAT_ABGR8888:
7682                 /* checked in intel_framebuffer_init already */
7683                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7684                         return -EINVAL;
7685         case DRM_FORMAT_XRGB8888:
7686         case DRM_FORMAT_ARGB8888:
7687                 bpp = 8*3;
7688                 break;
7689         case DRM_FORMAT_XRGB2101010:
7690         case DRM_FORMAT_ARGB2101010:
7691         case DRM_FORMAT_XBGR2101010:
7692         case DRM_FORMAT_ABGR2101010:
7693                 /* checked in intel_framebuffer_init already */
7694                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7695                         return -EINVAL;
7696                 bpp = 10*3;
7697                 break;
7698         /* TODO: gen4+ supports 16 bpc floating point, too. */
7699         default:
7700                 DRM_DEBUG_KMS("unsupported depth\n");
7701                 return -EINVAL;
7702         }
7703
7704         pipe_config->pipe_bpp = bpp;
7705
7706         /* Clamp display bpp to EDID value */
7707         list_for_each_entry(connector, &dev->mode_config.connector_list,
7708                             base.head) {
7709                 if (!connector->new_encoder ||
7710                     connector->new_encoder->new_crtc != crtc)
7711                         continue;
7712
7713                 connected_sink_compute_bpp(connector, pipe_config);
7714         }
7715
7716         return bpp;
7717 }
7718
7719 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7720                                    struct intel_crtc_config *pipe_config,
7721                                    const char *context)
7722 {
7723         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7724                       context, pipe_name(crtc->pipe));
7725
7726         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7727         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7728                       pipe_config->pipe_bpp, pipe_config->dither);
7729         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7730                       pipe_config->has_pch_encoder,
7731                       pipe_config->fdi_lanes,
7732                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7733                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7734                       pipe_config->fdi_m_n.tu);
7735         DRM_DEBUG_KMS("requested mode:\n");
7736         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7737         DRM_DEBUG_KMS("adjusted mode:\n");
7738         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7739         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7740                       pipe_config->gmch_pfit.control,
7741                       pipe_config->gmch_pfit.pgm_ratios,
7742                       pipe_config->gmch_pfit.lvds_border_bits);
7743         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7744                       pipe_config->pch_pfit.pos,
7745                       pipe_config->pch_pfit.size);
7746         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7747 }
7748
7749 static bool check_encoder_cloning(struct drm_crtc *crtc)
7750 {
7751         int num_encoders = 0;
7752         bool uncloneable_encoders = false;
7753         struct intel_encoder *encoder;
7754
7755         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7756                             base.head) {
7757                 if (&encoder->new_crtc->base != crtc)
7758                         continue;
7759
7760                 num_encoders++;
7761                 if (!encoder->cloneable)
7762                         uncloneable_encoders = true;
7763         }
7764
7765         return !(num_encoders > 1 && uncloneable_encoders);
7766 }
7767
7768 static struct intel_crtc_config *
7769 intel_modeset_pipe_config(struct drm_crtc *crtc,
7770                           struct drm_framebuffer *fb,
7771                           struct drm_display_mode *mode)
7772 {
7773         struct drm_device *dev = crtc->dev;
7774         struct drm_encoder_helper_funcs *encoder_funcs;
7775         struct intel_encoder *encoder;
7776         struct intel_crtc_config *pipe_config;
7777         int plane_bpp, ret = -EINVAL;
7778         bool retry = true;
7779
7780         if (!check_encoder_cloning(crtc)) {
7781                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7782                 return ERR_PTR(-EINVAL);
7783         }
7784
7785         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7786         if (!pipe_config)
7787                 return ERR_PTR(-ENOMEM);
7788
7789         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7790         drm_mode_copy(&pipe_config->requested_mode, mode);
7791         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7792
7793         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7794          * plane pixel format and any sink constraints into account. Returns the
7795          * source plane bpp so that dithering can be selected on mismatches
7796          * after encoders and crtc also have had their say. */
7797         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7798                                               fb, pipe_config);
7799         if (plane_bpp < 0)
7800                 goto fail;
7801
7802 encoder_retry:
7803         /* Ensure the port clock defaults are reset when retrying. */
7804         pipe_config->port_clock = 0;
7805         pipe_config->pixel_multiplier = 1;
7806
7807         /* Pass our mode to the connectors and the CRTC to give them a chance to
7808          * adjust it according to limitations or connector properties, and also
7809          * a chance to reject the mode entirely.
7810          */
7811         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7812                             base.head) {
7813
7814                 if (&encoder->new_crtc->base != crtc)
7815                         continue;
7816
7817                 if (encoder->compute_config) {
7818                         if (!(encoder->compute_config(encoder, pipe_config))) {
7819                                 DRM_DEBUG_KMS("Encoder config failure\n");
7820                                 goto fail;
7821                         }
7822
7823                         continue;
7824                 }
7825
7826                 encoder_funcs = encoder->base.helper_private;
7827                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7828                                                 &pipe_config->requested_mode,
7829                                                 &pipe_config->adjusted_mode))) {
7830                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7831                         goto fail;
7832                 }
7833         }
7834
7835         /* Set default port clock if not overwritten by the encoder. Needs to be
7836          * done afterwards in case the encoder adjusts the mode. */
7837         if (!pipe_config->port_clock)
7838                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7839
7840         ret = intel_crtc_compute_config(crtc, pipe_config);
7841         if (ret < 0) {
7842                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7843                 goto fail;
7844         }
7845
7846         if (ret == RETRY) {
7847                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7848                         ret = -EINVAL;
7849                         goto fail;
7850                 }
7851
7852                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7853                 retry = false;
7854                 goto encoder_retry;
7855         }
7856
7857         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7858         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7859                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7860
7861         return pipe_config;
7862 fail:
7863         kfree(pipe_config);
7864         return ERR_PTR(ret);
7865 }
7866
7867 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7868  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7869 static void
7870 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7871                              unsigned *prepare_pipes, unsigned *disable_pipes)
7872 {
7873         struct intel_crtc *intel_crtc;
7874         struct drm_device *dev = crtc->dev;
7875         struct intel_encoder *encoder;
7876         struct intel_connector *connector;
7877         struct drm_crtc *tmp_crtc;
7878
7879         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7880
7881         /* Check which crtcs have changed outputs connected to them, these need
7882          * to be part of the prepare_pipes mask. We don't (yet) support global
7883          * modeset across multiple crtcs, so modeset_pipes will only have one
7884          * bit set at most. */
7885         list_for_each_entry(connector, &dev->mode_config.connector_list,
7886                             base.head) {
7887                 if (connector->base.encoder == &connector->new_encoder->base)
7888                         continue;
7889
7890                 if (connector->base.encoder) {
7891                         tmp_crtc = connector->base.encoder->crtc;
7892
7893                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7894                 }
7895
7896                 if (connector->new_encoder)
7897                         *prepare_pipes |=
7898                                 1 << connector->new_encoder->new_crtc->pipe;
7899         }
7900
7901         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7902                             base.head) {
7903                 if (encoder->base.crtc == &encoder->new_crtc->base)
7904                         continue;
7905
7906                 if (encoder->base.crtc) {
7907                         tmp_crtc = encoder->base.crtc;
7908
7909                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7910                 }
7911
7912                 if (encoder->new_crtc)
7913                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7914         }
7915
7916         /* Check for any pipes that will be fully disabled ... */
7917         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7918                             base.head) {
7919                 bool used = false;
7920
7921                 /* Don't try to disable disabled crtcs. */
7922                 if (!intel_crtc->base.enabled)
7923                         continue;
7924
7925                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7926                                     base.head) {
7927                         if (encoder->new_crtc == intel_crtc)
7928                                 used = true;
7929                 }
7930
7931                 if (!used)
7932                         *disable_pipes |= 1 << intel_crtc->pipe;
7933         }
7934
7935
7936         /* set_mode is also used to update properties on life display pipes. */
7937         intel_crtc = to_intel_crtc(crtc);
7938         if (crtc->enabled)
7939                 *prepare_pipes |= 1 << intel_crtc->pipe;
7940
7941         /*
7942          * For simplicity do a full modeset on any pipe where the output routing
7943          * changed. We could be more clever, but that would require us to be
7944          * more careful with calling the relevant encoder->mode_set functions.
7945          */
7946         if (*prepare_pipes)
7947                 *modeset_pipes = *prepare_pipes;
7948
7949         /* ... and mask these out. */
7950         *modeset_pipes &= ~(*disable_pipes);
7951         *prepare_pipes &= ~(*disable_pipes);
7952
7953         /*
7954          * HACK: We don't (yet) fully support global modesets. intel_set_config
7955          * obies this rule, but the modeset restore mode of
7956          * intel_modeset_setup_hw_state does not.
7957          */
7958         *modeset_pipes &= 1 << intel_crtc->pipe;
7959         *prepare_pipes &= 1 << intel_crtc->pipe;
7960
7961         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7962                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7963 }
7964
7965 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7966 {
7967         struct drm_encoder *encoder;
7968         struct drm_device *dev = crtc->dev;
7969
7970         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7971                 if (encoder->crtc == crtc)
7972                         return true;
7973
7974         return false;
7975 }
7976
7977 static void
7978 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7979 {
7980         struct intel_encoder *intel_encoder;
7981         struct intel_crtc *intel_crtc;
7982         struct drm_connector *connector;
7983
7984         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7985                             base.head) {
7986                 if (!intel_encoder->base.crtc)
7987                         continue;
7988
7989                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7990
7991                 if (prepare_pipes & (1 << intel_crtc->pipe))
7992                         intel_encoder->connectors_active = false;
7993         }
7994
7995         intel_modeset_commit_output_state(dev);
7996
7997         /* Update computed state. */
7998         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7999                             base.head) {
8000                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8001         }
8002
8003         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8004                 if (!connector->encoder || !connector->encoder->crtc)
8005                         continue;
8006
8007                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8008
8009                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8010                         struct drm_property *dpms_property =
8011                                 dev->mode_config.dpms_property;
8012
8013                         connector->dpms = DRM_MODE_DPMS_ON;
8014                         drm_object_property_set_value(&connector->base,
8015                                                          dpms_property,
8016                                                          DRM_MODE_DPMS_ON);
8017
8018                         intel_encoder = to_intel_encoder(connector->encoder);
8019                         intel_encoder->connectors_active = true;
8020                 }
8021         }
8022
8023 }
8024
8025 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8026         list_for_each_entry((intel_crtc), \
8027                             &(dev)->mode_config.crtc_list, \
8028                             base.head) \
8029                 if (mask & (1 <<(intel_crtc)->pipe))
8030
8031 static bool
8032 intel_pipe_config_compare(struct drm_device *dev,
8033                           struct intel_crtc_config *current_config,
8034                           struct intel_crtc_config *pipe_config)
8035 {
8036 #define PIPE_CONF_CHECK_I(name) \
8037         if (current_config->name != pipe_config->name) { \
8038                 DRM_ERROR("mismatch in " #name " " \
8039                           "(expected %i, found %i)\n", \
8040                           current_config->name, \
8041                           pipe_config->name); \
8042                 return false; \
8043         }
8044
8045 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8046         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8047                 DRM_ERROR("mismatch in " #name " " \
8048                           "(expected %i, found %i)\n", \
8049                           current_config->name & (mask), \
8050                           pipe_config->name & (mask)); \
8051                 return false; \
8052         }
8053
8054         PIPE_CONF_CHECK_I(cpu_transcoder);
8055
8056         PIPE_CONF_CHECK_I(has_pch_encoder);
8057         PIPE_CONF_CHECK_I(fdi_lanes);
8058         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8059         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8060         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8061         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8062         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8063
8064         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8065         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8066         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8067         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8068         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8069         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8070
8071         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8072         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8073         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8074         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8075         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8076         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8077
8078         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8079                               DRM_MODE_FLAG_INTERLACE);
8080
8081         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8082                               DRM_MODE_FLAG_PHSYNC);
8083         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8084                               DRM_MODE_FLAG_NHSYNC);
8085         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8086                               DRM_MODE_FLAG_PVSYNC);
8087         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8088                               DRM_MODE_FLAG_NVSYNC);
8089
8090         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8091         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8092
8093         PIPE_CONF_CHECK_I(gmch_pfit.control);
8094         /* pfit ratios are autocomputed by the hw on gen4+ */
8095         if (INTEL_INFO(dev)->gen < 4)
8096                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8097         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8098         PIPE_CONF_CHECK_I(pch_pfit.pos);
8099         PIPE_CONF_CHECK_I(pch_pfit.size);
8100
8101         PIPE_CONF_CHECK_I(ips_enabled);
8102
8103 #undef PIPE_CONF_CHECK_I
8104 #undef PIPE_CONF_CHECK_FLAGS
8105
8106         return true;
8107 }
8108
8109 void
8110 intel_modeset_check_state(struct drm_device *dev)
8111 {
8112         drm_i915_private_t *dev_priv = dev->dev_private;
8113         struct intel_crtc *crtc;
8114         struct intel_encoder *encoder;
8115         struct intel_connector *connector;
8116         struct intel_crtc_config pipe_config;
8117
8118         list_for_each_entry(connector, &dev->mode_config.connector_list,
8119                             base.head) {
8120                 /* This also checks the encoder/connector hw state with the
8121                  * ->get_hw_state callbacks. */
8122                 intel_connector_check_state(connector);
8123
8124                 WARN(&connector->new_encoder->base != connector->base.encoder,
8125                      "connector's staged encoder doesn't match current encoder\n");
8126         }
8127
8128         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8129                             base.head) {
8130                 bool enabled = false;
8131                 bool active = false;
8132                 enum pipe pipe, tracked_pipe;
8133
8134                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8135                               encoder->base.base.id,
8136                               drm_get_encoder_name(&encoder->base));
8137
8138                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8139                      "encoder's stage crtc doesn't match current crtc\n");
8140                 WARN(encoder->connectors_active && !encoder->base.crtc,
8141                      "encoder's active_connectors set, but no crtc\n");
8142
8143                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8144                                     base.head) {
8145                         if (connector->base.encoder != &encoder->base)
8146                                 continue;
8147                         enabled = true;
8148                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8149                                 active = true;
8150                 }
8151                 WARN(!!encoder->base.crtc != enabled,
8152                      "encoder's enabled state mismatch "
8153                      "(expected %i, found %i)\n",
8154                      !!encoder->base.crtc, enabled);
8155                 WARN(active && !encoder->base.crtc,
8156                      "active encoder with no crtc\n");
8157
8158                 WARN(encoder->connectors_active != active,
8159                      "encoder's computed active state doesn't match tracked active state "
8160                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8161
8162                 active = encoder->get_hw_state(encoder, &pipe);
8163                 WARN(active != encoder->connectors_active,
8164                      "encoder's hw state doesn't match sw tracking "
8165                      "(expected %i, found %i)\n",
8166                      encoder->connectors_active, active);
8167
8168                 if (!encoder->base.crtc)
8169                         continue;
8170
8171                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8172                 WARN(active && pipe != tracked_pipe,
8173                      "active encoder's pipe doesn't match"
8174                      "(expected %i, found %i)\n",
8175                      tracked_pipe, pipe);
8176
8177         }
8178
8179         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8180                             base.head) {
8181                 bool enabled = false;
8182                 bool active = false;
8183
8184                 memset(&pipe_config, 0, sizeof(pipe_config));
8185
8186                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8187                               crtc->base.base.id);
8188
8189                 WARN(crtc->active && !crtc->base.enabled,
8190                      "active crtc, but not enabled in sw tracking\n");
8191
8192                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8193                                     base.head) {
8194                         if (encoder->base.crtc != &crtc->base)
8195                                 continue;
8196                         enabled = true;
8197                         if (encoder->connectors_active)
8198                                 active = true;
8199                         if (encoder->get_config)
8200                                 encoder->get_config(encoder, &pipe_config);
8201                 }
8202                 WARN(active != crtc->active,
8203                      "crtc's computed active state doesn't match tracked active state "
8204                      "(expected %i, found %i)\n", active, crtc->active);
8205                 WARN(enabled != crtc->base.enabled,
8206                      "crtc's computed enabled state doesn't match tracked enabled state "
8207                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8208
8209                 active = dev_priv->display.get_pipe_config(crtc,
8210                                                            &pipe_config);
8211                 WARN(crtc->active != active,
8212                      "crtc active state doesn't match with hw state "
8213                      "(expected %i, found %i)\n", crtc->active, active);
8214
8215                 if (active &&
8216                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8217                         WARN(1, "pipe state doesn't match!\n");
8218                         intel_dump_pipe_config(crtc, &pipe_config,
8219                                                "[hw state]");
8220                         intel_dump_pipe_config(crtc, &crtc->config,
8221                                                "[sw state]");
8222                 }
8223         }
8224 }
8225
8226 static int __intel_set_mode(struct drm_crtc *crtc,
8227                             struct drm_display_mode *mode,
8228                             int x, int y, struct drm_framebuffer *fb)
8229 {
8230         struct drm_device *dev = crtc->dev;
8231         drm_i915_private_t *dev_priv = dev->dev_private;
8232         struct drm_display_mode *saved_mode, *saved_hwmode;
8233         struct intel_crtc_config *pipe_config = NULL;
8234         struct intel_crtc *intel_crtc;
8235         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8236         int ret = 0;
8237
8238         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8239         if (!saved_mode)
8240                 return -ENOMEM;
8241         saved_hwmode = saved_mode + 1;
8242
8243         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8244                                      &prepare_pipes, &disable_pipes);
8245
8246         *saved_hwmode = crtc->hwmode;
8247         *saved_mode = crtc->mode;
8248
8249         /* Hack: Because we don't (yet) support global modeset on multiple
8250          * crtcs, we don't keep track of the new mode for more than one crtc.
8251          * Hence simply check whether any bit is set in modeset_pipes in all the
8252          * pieces of code that are not yet converted to deal with mutliple crtcs
8253          * changing their mode at the same time. */
8254         if (modeset_pipes) {
8255                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8256                 if (IS_ERR(pipe_config)) {
8257                         ret = PTR_ERR(pipe_config);
8258                         pipe_config = NULL;
8259
8260                         goto out;
8261                 }
8262                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8263                                        "[modeset]");
8264         }
8265
8266         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8267                 intel_crtc_disable(&intel_crtc->base);
8268
8269         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8270                 if (intel_crtc->base.enabled)
8271                         dev_priv->display.crtc_disable(&intel_crtc->base);
8272         }
8273
8274         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8275          * to set it here already despite that we pass it down the callchain.
8276          */
8277         if (modeset_pipes) {
8278                 crtc->mode = *mode;
8279                 /* mode_set/enable/disable functions rely on a correct pipe
8280                  * config. */
8281                 to_intel_crtc(crtc)->config = *pipe_config;
8282         }
8283
8284         /* Only after disabling all output pipelines that will be changed can we
8285          * update the the output configuration. */
8286         intel_modeset_update_state(dev, prepare_pipes);
8287
8288         if (dev_priv->display.modeset_global_resources)
8289                 dev_priv->display.modeset_global_resources(dev);
8290
8291         /* Set up the DPLL and any encoders state that needs to adjust or depend
8292          * on the DPLL.
8293          */
8294         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8295                 ret = intel_crtc_mode_set(&intel_crtc->base,
8296                                           x, y, fb);
8297                 if (ret)
8298                         goto done;
8299         }
8300
8301         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8302         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8303                 dev_priv->display.crtc_enable(&intel_crtc->base);
8304
8305         if (modeset_pipes) {
8306                 /* Store real post-adjustment hardware mode. */
8307                 crtc->hwmode = pipe_config->adjusted_mode;
8308
8309                 /* Calculate and store various constants which
8310                  * are later needed by vblank and swap-completion
8311                  * timestamping. They are derived from true hwmode.
8312                  */
8313                 drm_calc_timestamping_constants(crtc);
8314         }
8315
8316         /* FIXME: add subpixel order */
8317 done:
8318         if (ret && crtc->enabled) {
8319                 crtc->hwmode = *saved_hwmode;
8320                 crtc->mode = *saved_mode;
8321         }
8322
8323 out:
8324         kfree(pipe_config);
8325         kfree(saved_mode);
8326         return ret;
8327 }
8328
8329 int intel_set_mode(struct drm_crtc *crtc,
8330                      struct drm_display_mode *mode,
8331                      int x, int y, struct drm_framebuffer *fb)
8332 {
8333         int ret;
8334
8335         ret = __intel_set_mode(crtc, mode, x, y, fb);
8336
8337         if (ret == 0)
8338                 intel_modeset_check_state(crtc->dev);
8339
8340         return ret;
8341 }
8342
8343 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8344 {
8345         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8346 }
8347
8348 #undef for_each_intel_crtc_masked
8349
8350 static void intel_set_config_free(struct intel_set_config *config)
8351 {
8352         if (!config)
8353                 return;
8354
8355         kfree(config->save_connector_encoders);
8356         kfree(config->save_encoder_crtcs);
8357         kfree(config);
8358 }
8359
8360 static int intel_set_config_save_state(struct drm_device *dev,
8361                                        struct intel_set_config *config)
8362 {
8363         struct drm_encoder *encoder;
8364         struct drm_connector *connector;
8365         int count;
8366
8367         config->save_encoder_crtcs =
8368                 kcalloc(dev->mode_config.num_encoder,
8369                         sizeof(struct drm_crtc *), GFP_KERNEL);
8370         if (!config->save_encoder_crtcs)
8371                 return -ENOMEM;
8372
8373         config->save_connector_encoders =
8374                 kcalloc(dev->mode_config.num_connector,
8375                         sizeof(struct drm_encoder *), GFP_KERNEL);
8376         if (!config->save_connector_encoders)
8377                 return -ENOMEM;
8378
8379         /* Copy data. Note that driver private data is not affected.
8380          * Should anything bad happen only the expected state is
8381          * restored, not the drivers personal bookkeeping.
8382          */
8383         count = 0;
8384         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8385                 config->save_encoder_crtcs[count++] = encoder->crtc;
8386         }
8387
8388         count = 0;
8389         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8390                 config->save_connector_encoders[count++] = connector->encoder;
8391         }
8392
8393         return 0;
8394 }
8395
8396 static void intel_set_config_restore_state(struct drm_device *dev,
8397                                            struct intel_set_config *config)
8398 {
8399         struct intel_encoder *encoder;
8400         struct intel_connector *connector;
8401         int count;
8402
8403         count = 0;
8404         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8405                 encoder->new_crtc =
8406                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8407         }
8408
8409         count = 0;
8410         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8411                 connector->new_encoder =
8412                         to_intel_encoder(config->save_connector_encoders[count++]);
8413         }
8414 }
8415
8416 static void
8417 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8418                                       struct intel_set_config *config)
8419 {
8420
8421         /* We should be able to check here if the fb has the same properties
8422          * and then just flip_or_move it */
8423         if (set->crtc->fb != set->fb) {
8424                 /* If we have no fb then treat it as a full mode set */
8425                 if (set->crtc->fb == NULL) {
8426                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8427                         config->mode_changed = true;
8428                 } else if (set->fb == NULL) {
8429                         config->mode_changed = true;
8430                 } else if (set->fb->pixel_format !=
8431                            set->crtc->fb->pixel_format) {
8432                         config->mode_changed = true;
8433                 } else
8434                         config->fb_changed = true;
8435         }
8436
8437         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8438                 config->fb_changed = true;
8439
8440         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8441                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8442                 drm_mode_debug_printmodeline(&set->crtc->mode);
8443                 drm_mode_debug_printmodeline(set->mode);
8444                 config->mode_changed = true;
8445         }
8446 }
8447
8448 static int
8449 intel_modeset_stage_output_state(struct drm_device *dev,
8450                                  struct drm_mode_set *set,
8451                                  struct intel_set_config *config)
8452 {
8453         struct drm_crtc *new_crtc;
8454         struct intel_connector *connector;
8455         struct intel_encoder *encoder;
8456         int count, ro;
8457
8458         /* The upper layers ensure that we either disable a crtc or have a list
8459          * of connectors. For paranoia, double-check this. */
8460         WARN_ON(!set->fb && (set->num_connectors != 0));
8461         WARN_ON(set->fb && (set->num_connectors == 0));
8462
8463         count = 0;
8464         list_for_each_entry(connector, &dev->mode_config.connector_list,
8465                             base.head) {
8466                 /* Otherwise traverse passed in connector list and get encoders
8467                  * for them. */
8468                 for (ro = 0; ro < set->num_connectors; ro++) {
8469                         if (set->connectors[ro] == &connector->base) {
8470                                 connector->new_encoder = connector->encoder;
8471                                 break;
8472                         }
8473                 }
8474
8475                 /* If we disable the crtc, disable all its connectors. Also, if
8476                  * the connector is on the changing crtc but not on the new
8477                  * connector list, disable it. */
8478                 if ((!set->fb || ro == set->num_connectors) &&
8479                     connector->base.encoder &&
8480                     connector->base.encoder->crtc == set->crtc) {
8481                         connector->new_encoder = NULL;
8482
8483                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8484                                 connector->base.base.id,
8485                                 drm_get_connector_name(&connector->base));
8486                 }
8487
8488
8489                 if (&connector->new_encoder->base != connector->base.encoder) {
8490                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8491                         config->mode_changed = true;
8492                 }
8493         }
8494         /* connector->new_encoder is now updated for all connectors. */
8495
8496         /* Update crtc of enabled connectors. */
8497         count = 0;
8498         list_for_each_entry(connector, &dev->mode_config.connector_list,
8499                             base.head) {
8500                 if (!connector->new_encoder)
8501                         continue;
8502
8503                 new_crtc = connector->new_encoder->base.crtc;
8504
8505                 for (ro = 0; ro < set->num_connectors; ro++) {
8506                         if (set->connectors[ro] == &connector->base)
8507                                 new_crtc = set->crtc;
8508                 }
8509
8510                 /* Make sure the new CRTC will work with the encoder */
8511                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8512                                            new_crtc)) {
8513                         return -EINVAL;
8514                 }
8515                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8516
8517                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8518                         connector->base.base.id,
8519                         drm_get_connector_name(&connector->base),
8520                         new_crtc->base.id);
8521         }
8522
8523         /* Check for any encoders that needs to be disabled. */
8524         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8525                             base.head) {
8526                 list_for_each_entry(connector,
8527                                     &dev->mode_config.connector_list,
8528                                     base.head) {
8529                         if (connector->new_encoder == encoder) {
8530                                 WARN_ON(!connector->new_encoder->new_crtc);
8531
8532                                 goto next_encoder;
8533                         }
8534                 }
8535                 encoder->new_crtc = NULL;
8536 next_encoder:
8537                 /* Only now check for crtc changes so we don't miss encoders
8538                  * that will be disabled. */
8539                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8540                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8541                         config->mode_changed = true;
8542                 }
8543         }
8544         /* Now we've also updated encoder->new_crtc for all encoders. */
8545
8546         return 0;
8547 }
8548
8549 static int intel_crtc_set_config(struct drm_mode_set *set)
8550 {
8551         struct drm_device *dev;
8552         struct drm_mode_set save_set;
8553         struct intel_set_config *config;
8554         int ret;
8555
8556         BUG_ON(!set);
8557         BUG_ON(!set->crtc);
8558         BUG_ON(!set->crtc->helper_private);
8559
8560         /* Enforce sane interface api - has been abused by the fb helper. */
8561         BUG_ON(!set->mode && set->fb);
8562         BUG_ON(set->fb && set->num_connectors == 0);
8563
8564         if (set->fb) {
8565                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8566                                 set->crtc->base.id, set->fb->base.id,
8567                                 (int)set->num_connectors, set->x, set->y);
8568         } else {
8569                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8570         }
8571
8572         dev = set->crtc->dev;
8573
8574         ret = -ENOMEM;
8575         config = kzalloc(sizeof(*config), GFP_KERNEL);
8576         if (!config)
8577                 goto out_config;
8578
8579         ret = intel_set_config_save_state(dev, config);
8580         if (ret)
8581                 goto out_config;
8582
8583         save_set.crtc = set->crtc;
8584         save_set.mode = &set->crtc->mode;
8585         save_set.x = set->crtc->x;
8586         save_set.y = set->crtc->y;
8587         save_set.fb = set->crtc->fb;
8588
8589         /* Compute whether we need a full modeset, only an fb base update or no
8590          * change at all. In the future we might also check whether only the
8591          * mode changed, e.g. for LVDS where we only change the panel fitter in
8592          * such cases. */
8593         intel_set_config_compute_mode_changes(set, config);
8594
8595         ret = intel_modeset_stage_output_state(dev, set, config);
8596         if (ret)
8597                 goto fail;
8598
8599         if (config->mode_changed) {
8600                 ret = intel_set_mode(set->crtc, set->mode,
8601                                      set->x, set->y, set->fb);
8602                 if (ret) {
8603                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8604                                   set->crtc->base.id, ret);
8605                         goto fail;
8606                 }
8607         } else if (config->fb_changed) {
8608                 intel_crtc_wait_for_pending_flips(set->crtc);
8609
8610                 ret = intel_pipe_set_base(set->crtc,
8611                                           set->x, set->y, set->fb);
8612         }
8613
8614         intel_set_config_free(config);
8615
8616         return 0;
8617
8618 fail:
8619         intel_set_config_restore_state(dev, config);
8620
8621         /* Try to restore the config */
8622         if (config->mode_changed &&
8623             intel_set_mode(save_set.crtc, save_set.mode,
8624                            save_set.x, save_set.y, save_set.fb))
8625                 DRM_ERROR("failed to restore config after modeset failure\n");
8626
8627 out_config:
8628         intel_set_config_free(config);
8629         return ret;
8630 }
8631
8632 static const struct drm_crtc_funcs intel_crtc_funcs = {
8633         .cursor_set = intel_crtc_cursor_set,
8634         .cursor_move = intel_crtc_cursor_move,
8635         .gamma_set = intel_crtc_gamma_set,
8636         .set_config = intel_crtc_set_config,
8637         .destroy = intel_crtc_destroy,
8638         .page_flip = intel_crtc_page_flip,
8639 };
8640
8641 static void intel_cpu_pll_init(struct drm_device *dev)
8642 {
8643         if (HAS_DDI(dev))
8644                 intel_ddi_pll_init(dev);
8645 }
8646
8647 static void intel_pch_pll_init(struct drm_device *dev)
8648 {
8649         drm_i915_private_t *dev_priv = dev->dev_private;
8650         int i;
8651
8652         if (dev_priv->num_pch_pll == 0) {
8653                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8654                 return;
8655         }
8656
8657         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8658                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8659                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8660                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8661         }
8662 }
8663
8664 static void intel_crtc_init(struct drm_device *dev, int pipe)
8665 {
8666         drm_i915_private_t *dev_priv = dev->dev_private;
8667         struct intel_crtc *intel_crtc;
8668         int i;
8669
8670         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8671         if (intel_crtc == NULL)
8672                 return;
8673
8674         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8675
8676         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8677         for (i = 0; i < 256; i++) {
8678                 intel_crtc->lut_r[i] = i;
8679                 intel_crtc->lut_g[i] = i;
8680                 intel_crtc->lut_b[i] = i;
8681         }
8682
8683         /* Swap pipes & planes for FBC on pre-965 */
8684         intel_crtc->pipe = pipe;
8685         intel_crtc->plane = pipe;
8686         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8687                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8688                 intel_crtc->plane = !pipe;
8689         }
8690
8691         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8692                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8693         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8694         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8695
8696         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8697 }
8698
8699 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8700                                 struct drm_file *file)
8701 {
8702         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8703         struct drm_mode_object *drmmode_obj;
8704         struct intel_crtc *crtc;
8705
8706         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8707                 return -ENODEV;
8708
8709         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8710                         DRM_MODE_OBJECT_CRTC);
8711
8712         if (!drmmode_obj) {
8713                 DRM_ERROR("no such CRTC id\n");
8714                 return -EINVAL;
8715         }
8716
8717         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8718         pipe_from_crtc_id->pipe = crtc->pipe;
8719
8720         return 0;
8721 }
8722
8723 static int intel_encoder_clones(struct intel_encoder *encoder)
8724 {
8725         struct drm_device *dev = encoder->base.dev;
8726         struct intel_encoder *source_encoder;
8727         int index_mask = 0;
8728         int entry = 0;
8729
8730         list_for_each_entry(source_encoder,
8731                             &dev->mode_config.encoder_list, base.head) {
8732
8733                 if (encoder == source_encoder)
8734                         index_mask |= (1 << entry);
8735
8736                 /* Intel hw has only one MUX where enocoders could be cloned. */
8737                 if (encoder->cloneable && source_encoder->cloneable)
8738                         index_mask |= (1 << entry);
8739
8740                 entry++;
8741         }
8742
8743         return index_mask;
8744 }
8745
8746 static bool has_edp_a(struct drm_device *dev)
8747 {
8748         struct drm_i915_private *dev_priv = dev->dev_private;
8749
8750         if (!IS_MOBILE(dev))
8751                 return false;
8752
8753         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8754                 return false;
8755
8756         if (IS_GEN5(dev) &&
8757             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8758                 return false;
8759
8760         return true;
8761 }
8762
8763 static void intel_setup_outputs(struct drm_device *dev)
8764 {
8765         struct drm_i915_private *dev_priv = dev->dev_private;
8766         struct intel_encoder *encoder;
8767         bool dpd_is_edp = false;
8768         bool has_lvds;
8769
8770         has_lvds = intel_lvds_init(dev);
8771         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8772                 /* disable the panel fitter on everything but LVDS */
8773                 I915_WRITE(PFIT_CONTROL, 0);
8774         }
8775
8776         if (!IS_ULT(dev))
8777                 intel_crt_init(dev);
8778
8779         if (HAS_DDI(dev)) {
8780                 int found;
8781
8782                 /* Haswell uses DDI functions to detect digital outputs */
8783                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8784                 /* DDI A only supports eDP */
8785                 if (found)
8786                         intel_ddi_init(dev, PORT_A);
8787
8788                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8789                  * register */
8790                 found = I915_READ(SFUSE_STRAP);
8791
8792                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8793                         intel_ddi_init(dev, PORT_B);
8794                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8795                         intel_ddi_init(dev, PORT_C);
8796                 if (found & SFUSE_STRAP_DDID_DETECTED)
8797                         intel_ddi_init(dev, PORT_D);
8798         } else if (HAS_PCH_SPLIT(dev)) {
8799                 int found;
8800                 dpd_is_edp = intel_dpd_is_edp(dev);
8801
8802                 if (has_edp_a(dev))
8803                         intel_dp_init(dev, DP_A, PORT_A);
8804
8805                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8806                         /* PCH SDVOB multiplex with HDMIB */
8807                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8808                         if (!found)
8809                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8810                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8811                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8812                 }
8813
8814                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8815                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8816
8817                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8818                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8819
8820                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8821                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8822
8823                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8824                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8825         } else if (IS_VALLEYVIEW(dev)) {
8826                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8827                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8828                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8829
8830                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8831                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8832                                         PORT_B);
8833                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8834                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8835                 }
8836         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8837                 bool found = false;
8838
8839                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8840                         DRM_DEBUG_KMS("probing SDVOB\n");
8841                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8842                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8843                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8844                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8845                         }
8846
8847                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
8848                                 intel_dp_init(dev, DP_B, PORT_B);
8849                 }
8850
8851                 /* Before G4X SDVOC doesn't have its own detect register */
8852
8853                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8854                         DRM_DEBUG_KMS("probing SDVOC\n");
8855                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8856                 }
8857
8858                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8859
8860                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8861                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8862                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8863                         }
8864                         if (SUPPORTS_INTEGRATED_DP(dev))
8865                                 intel_dp_init(dev, DP_C, PORT_C);
8866                 }
8867
8868                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8869                     (I915_READ(DP_D) & DP_DETECTED))
8870                         intel_dp_init(dev, DP_D, PORT_D);
8871         } else if (IS_GEN2(dev))
8872                 intel_dvo_init(dev);
8873
8874         if (SUPPORTS_TV(dev))
8875                 intel_tv_init(dev);
8876
8877         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8878                 encoder->base.possible_crtcs = encoder->crtc_mask;
8879                 encoder->base.possible_clones =
8880                         intel_encoder_clones(encoder);
8881         }
8882
8883         intel_init_pch_refclk(dev);
8884
8885         drm_helper_move_panel_connectors_to_head(dev);
8886 }
8887
8888 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8889 {
8890         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8891
8892         drm_framebuffer_cleanup(fb);
8893         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8894
8895         kfree(intel_fb);
8896 }
8897
8898 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8899                                                 struct drm_file *file,
8900                                                 unsigned int *handle)
8901 {
8902         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8903         struct drm_i915_gem_object *obj = intel_fb->obj;
8904
8905         return drm_gem_handle_create(file, &obj->base, handle);
8906 }
8907
8908 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8909         .destroy = intel_user_framebuffer_destroy,
8910         .create_handle = intel_user_framebuffer_create_handle,
8911 };
8912
8913 int intel_framebuffer_init(struct drm_device *dev,
8914                            struct intel_framebuffer *intel_fb,
8915                            struct drm_mode_fb_cmd2 *mode_cmd,
8916                            struct drm_i915_gem_object *obj)
8917 {
8918         int ret;
8919
8920         if (obj->tiling_mode == I915_TILING_Y) {
8921                 DRM_DEBUG("hardware does not support tiling Y\n");
8922                 return -EINVAL;
8923         }
8924
8925         if (mode_cmd->pitches[0] & 63) {
8926                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8927                           mode_cmd->pitches[0]);
8928                 return -EINVAL;
8929         }
8930
8931         /* FIXME <= Gen4 stride limits are bit unclear */
8932         if (mode_cmd->pitches[0] > 32768) {
8933                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8934                           mode_cmd->pitches[0]);
8935                 return -EINVAL;
8936         }
8937
8938         if (obj->tiling_mode != I915_TILING_NONE &&
8939             mode_cmd->pitches[0] != obj->stride) {
8940                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8941                           mode_cmd->pitches[0], obj->stride);
8942                 return -EINVAL;
8943         }
8944
8945         /* Reject formats not supported by any plane early. */
8946         switch (mode_cmd->pixel_format) {
8947         case DRM_FORMAT_C8:
8948         case DRM_FORMAT_RGB565:
8949         case DRM_FORMAT_XRGB8888:
8950         case DRM_FORMAT_ARGB8888:
8951                 break;
8952         case DRM_FORMAT_XRGB1555:
8953         case DRM_FORMAT_ARGB1555:
8954                 if (INTEL_INFO(dev)->gen > 3) {
8955                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8956                         return -EINVAL;
8957                 }
8958                 break;
8959         case DRM_FORMAT_XBGR8888:
8960         case DRM_FORMAT_ABGR8888:
8961         case DRM_FORMAT_XRGB2101010:
8962         case DRM_FORMAT_ARGB2101010:
8963         case DRM_FORMAT_XBGR2101010:
8964         case DRM_FORMAT_ABGR2101010:
8965                 if (INTEL_INFO(dev)->gen < 4) {
8966                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8967                         return -EINVAL;
8968                 }
8969                 break;
8970         case DRM_FORMAT_YUYV:
8971         case DRM_FORMAT_UYVY:
8972         case DRM_FORMAT_YVYU:
8973         case DRM_FORMAT_VYUY:
8974                 if (INTEL_INFO(dev)->gen < 5) {
8975                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8976                         return -EINVAL;
8977                 }
8978                 break;
8979         default:
8980                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8981                 return -EINVAL;
8982         }
8983
8984         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8985         if (mode_cmd->offsets[0] != 0)
8986                 return -EINVAL;
8987
8988         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8989         intel_fb->obj = obj;
8990
8991         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8992         if (ret) {
8993                 DRM_ERROR("framebuffer init failed %d\n", ret);
8994                 return ret;
8995         }
8996
8997         return 0;
8998 }
8999
9000 static struct drm_framebuffer *
9001 intel_user_framebuffer_create(struct drm_device *dev,
9002                               struct drm_file *filp,
9003                               struct drm_mode_fb_cmd2 *mode_cmd)
9004 {
9005         struct drm_i915_gem_object *obj;
9006
9007         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9008                                                 mode_cmd->handles[0]));
9009         if (&obj->base == NULL)
9010                 return ERR_PTR(-ENOENT);
9011
9012         return intel_framebuffer_create(dev, mode_cmd, obj);
9013 }
9014
9015 static const struct drm_mode_config_funcs intel_mode_funcs = {
9016         .fb_create = intel_user_framebuffer_create,
9017         .output_poll_changed = intel_fb_output_poll_changed,
9018 };
9019
9020 /* Set up chip specific display functions */
9021 static void intel_init_display(struct drm_device *dev)
9022 {
9023         struct drm_i915_private *dev_priv = dev->dev_private;
9024
9025         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9026                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9027         else if (IS_VALLEYVIEW(dev))
9028                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9029         else if (IS_PINEVIEW(dev))
9030                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9031         else
9032                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9033
9034         if (HAS_DDI(dev)) {
9035                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9036                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9037                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9038                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9039                 dev_priv->display.off = haswell_crtc_off;
9040                 dev_priv->display.update_plane = ironlake_update_plane;
9041         } else if (HAS_PCH_SPLIT(dev)) {
9042                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9043                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9044                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9045                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9046                 dev_priv->display.off = ironlake_crtc_off;
9047                 dev_priv->display.update_plane = ironlake_update_plane;
9048         } else if (IS_VALLEYVIEW(dev)) {
9049                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9050                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9051                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9052                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9053                 dev_priv->display.off = i9xx_crtc_off;
9054                 dev_priv->display.update_plane = i9xx_update_plane;
9055         } else {
9056                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9057                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9058                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9059                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9060                 dev_priv->display.off = i9xx_crtc_off;
9061                 dev_priv->display.update_plane = i9xx_update_plane;
9062         }
9063
9064         /* Returns the core display clock speed */
9065         if (IS_VALLEYVIEW(dev))
9066                 dev_priv->display.get_display_clock_speed =
9067                         valleyview_get_display_clock_speed;
9068         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9069                 dev_priv->display.get_display_clock_speed =
9070                         i945_get_display_clock_speed;
9071         else if (IS_I915G(dev))
9072                 dev_priv->display.get_display_clock_speed =
9073                         i915_get_display_clock_speed;
9074         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9075                 dev_priv->display.get_display_clock_speed =
9076                         i9xx_misc_get_display_clock_speed;
9077         else if (IS_I915GM(dev))
9078                 dev_priv->display.get_display_clock_speed =
9079                         i915gm_get_display_clock_speed;
9080         else if (IS_I865G(dev))
9081                 dev_priv->display.get_display_clock_speed =
9082                         i865_get_display_clock_speed;
9083         else if (IS_I85X(dev))
9084                 dev_priv->display.get_display_clock_speed =
9085                         i855_get_display_clock_speed;
9086         else /* 852, 830 */
9087                 dev_priv->display.get_display_clock_speed =
9088                         i830_get_display_clock_speed;
9089
9090         if (HAS_PCH_SPLIT(dev)) {
9091                 if (IS_GEN5(dev)) {
9092                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9093                         dev_priv->display.write_eld = ironlake_write_eld;
9094                 } else if (IS_GEN6(dev)) {
9095                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9096                         dev_priv->display.write_eld = ironlake_write_eld;
9097                 } else if (IS_IVYBRIDGE(dev)) {
9098                         /* FIXME: detect B0+ stepping and use auto training */
9099                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9100                         dev_priv->display.write_eld = ironlake_write_eld;
9101                         dev_priv->display.modeset_global_resources =
9102                                 ivb_modeset_global_resources;
9103                 } else if (IS_HASWELL(dev)) {
9104                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9105                         dev_priv->display.write_eld = haswell_write_eld;
9106                         dev_priv->display.modeset_global_resources =
9107                                 haswell_modeset_global_resources;
9108                 }
9109         } else if (IS_G4X(dev)) {
9110                 dev_priv->display.write_eld = g4x_write_eld;
9111         }
9112
9113         /* Default just returns -ENODEV to indicate unsupported */
9114         dev_priv->display.queue_flip = intel_default_queue_flip;
9115
9116         switch (INTEL_INFO(dev)->gen) {
9117         case 2:
9118                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9119                 break;
9120
9121         case 3:
9122                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9123                 break;
9124
9125         case 4:
9126         case 5:
9127                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9128                 break;
9129
9130         case 6:
9131                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9132                 break;
9133         case 7:
9134                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9135                 break;
9136         }
9137 }
9138
9139 /*
9140  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9141  * resume, or other times.  This quirk makes sure that's the case for
9142  * affected systems.
9143  */
9144 static void quirk_pipea_force(struct drm_device *dev)
9145 {
9146         struct drm_i915_private *dev_priv = dev->dev_private;
9147
9148         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9149         DRM_INFO("applying pipe a force quirk\n");
9150 }
9151
9152 /*
9153  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9154  */
9155 static void quirk_ssc_force_disable(struct drm_device *dev)
9156 {
9157         struct drm_i915_private *dev_priv = dev->dev_private;
9158         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9159         DRM_INFO("applying lvds SSC disable quirk\n");
9160 }
9161
9162 /*
9163  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9164  * brightness value
9165  */
9166 static void quirk_invert_brightness(struct drm_device *dev)
9167 {
9168         struct drm_i915_private *dev_priv = dev->dev_private;
9169         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9170         DRM_INFO("applying inverted panel brightness quirk\n");
9171 }
9172
9173 struct intel_quirk {
9174         int device;
9175         int subsystem_vendor;
9176         int subsystem_device;
9177         void (*hook)(struct drm_device *dev);
9178 };
9179
9180 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9181 struct intel_dmi_quirk {
9182         void (*hook)(struct drm_device *dev);
9183         const struct dmi_system_id (*dmi_id_list)[];
9184 };
9185
9186 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9187 {
9188         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9189         return 1;
9190 }
9191
9192 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9193         {
9194                 .dmi_id_list = &(const struct dmi_system_id[]) {
9195                         {
9196                                 .callback = intel_dmi_reverse_brightness,
9197                                 .ident = "NCR Corporation",
9198                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9199                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9200                                 },
9201                         },
9202                         { }  /* terminating entry */
9203                 },
9204                 .hook = quirk_invert_brightness,
9205         },
9206 };
9207
9208 static struct intel_quirk intel_quirks[] = {
9209         /* HP Mini needs pipe A force quirk (LP: #322104) */
9210         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9211
9212         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9213         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9214
9215         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9216         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9217
9218         /* 830/845 need to leave pipe A & dpll A up */
9219         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9220         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9221
9222         /* Lenovo U160 cannot use SSC on LVDS */
9223         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9224
9225         /* Sony Vaio Y cannot use SSC on LVDS */
9226         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9227
9228         /* Acer Aspire 5734Z must invert backlight brightness */
9229         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9230
9231         /* Acer/eMachines G725 */
9232         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9233
9234         /* Acer/eMachines e725 */
9235         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9236
9237         /* Acer/Packard Bell NCL20 */
9238         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9239
9240         /* Acer Aspire 4736Z */
9241         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9242 };
9243
9244 static void intel_init_quirks(struct drm_device *dev)
9245 {
9246         struct pci_dev *d = dev->pdev;
9247         int i;
9248
9249         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9250                 struct intel_quirk *q = &intel_quirks[i];
9251
9252                 if (d->device == q->device &&
9253                     (d->subsystem_vendor == q->subsystem_vendor ||
9254                      q->subsystem_vendor == PCI_ANY_ID) &&
9255                     (d->subsystem_device == q->subsystem_device ||
9256                      q->subsystem_device == PCI_ANY_ID))
9257                         q->hook(dev);
9258         }
9259         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9260                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9261                         intel_dmi_quirks[i].hook(dev);
9262         }
9263 }
9264
9265 /* Disable the VGA plane that we never use */
9266 static void i915_disable_vga(struct drm_device *dev)
9267 {
9268         struct drm_i915_private *dev_priv = dev->dev_private;
9269         u8 sr1;
9270         u32 vga_reg = i915_vgacntrl_reg(dev);
9271
9272         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9273         outb(SR01, VGA_SR_INDEX);
9274         sr1 = inb(VGA_SR_DATA);
9275         outb(sr1 | 1<<5, VGA_SR_DATA);
9276         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9277         udelay(300);
9278
9279         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9280         POSTING_READ(vga_reg);
9281 }
9282
9283 void intel_modeset_init_hw(struct drm_device *dev)
9284 {
9285         intel_init_power_well(dev);
9286
9287         intel_prepare_ddi(dev);
9288
9289         intel_init_clock_gating(dev);
9290
9291         mutex_lock(&dev->struct_mutex);
9292         intel_enable_gt_powersave(dev);
9293         mutex_unlock(&dev->struct_mutex);
9294 }
9295
9296 void intel_modeset_suspend_hw(struct drm_device *dev)
9297 {
9298         intel_suspend_hw(dev);
9299 }
9300
9301 void intel_modeset_init(struct drm_device *dev)
9302 {
9303         struct drm_i915_private *dev_priv = dev->dev_private;
9304         int i, j, ret;
9305
9306         drm_mode_config_init(dev);
9307
9308         dev->mode_config.min_width = 0;
9309         dev->mode_config.min_height = 0;
9310
9311         dev->mode_config.preferred_depth = 24;
9312         dev->mode_config.prefer_shadow = 1;
9313
9314         dev->mode_config.funcs = &intel_mode_funcs;
9315
9316         intel_init_quirks(dev);
9317
9318         intel_init_pm(dev);
9319
9320         if (INTEL_INFO(dev)->num_pipes == 0)
9321                 return;
9322
9323         intel_init_display(dev);
9324
9325         if (IS_GEN2(dev)) {
9326                 dev->mode_config.max_width = 2048;
9327                 dev->mode_config.max_height = 2048;
9328         } else if (IS_GEN3(dev)) {
9329                 dev->mode_config.max_width = 4096;
9330                 dev->mode_config.max_height = 4096;
9331         } else {
9332                 dev->mode_config.max_width = 8192;
9333                 dev->mode_config.max_height = 8192;
9334         }
9335         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9336
9337         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9338                       INTEL_INFO(dev)->num_pipes,
9339                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9340
9341         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9342                 intel_crtc_init(dev, i);
9343                 for (j = 0; j < dev_priv->num_plane; j++) {
9344                         ret = intel_plane_init(dev, i, j);
9345                         if (ret)
9346                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9347                                               pipe_name(i), sprite_name(i, j), ret);
9348                 }
9349         }
9350
9351         intel_cpu_pll_init(dev);
9352         intel_pch_pll_init(dev);
9353
9354         /* Just disable it once at startup */
9355         i915_disable_vga(dev);
9356         intel_setup_outputs(dev);
9357
9358         /* Just in case the BIOS is doing something questionable. */
9359         intel_disable_fbc(dev);
9360 }
9361
9362 static void
9363 intel_connector_break_all_links(struct intel_connector *connector)
9364 {
9365         connector->base.dpms = DRM_MODE_DPMS_OFF;
9366         connector->base.encoder = NULL;
9367         connector->encoder->connectors_active = false;
9368         connector->encoder->base.crtc = NULL;
9369 }
9370
9371 static void intel_enable_pipe_a(struct drm_device *dev)
9372 {
9373         struct intel_connector *connector;
9374         struct drm_connector *crt = NULL;
9375         struct intel_load_detect_pipe load_detect_temp;
9376
9377         /* We can't just switch on the pipe A, we need to set things up with a
9378          * proper mode and output configuration. As a gross hack, enable pipe A
9379          * by enabling the load detect pipe once. */
9380         list_for_each_entry(connector,
9381                             &dev->mode_config.connector_list,
9382                             base.head) {
9383                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9384                         crt = &connector->base;
9385                         break;
9386                 }
9387         }
9388
9389         if (!crt)
9390                 return;
9391
9392         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9393                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9394
9395
9396 }
9397
9398 static bool
9399 intel_check_plane_mapping(struct intel_crtc *crtc)
9400 {
9401         struct drm_device *dev = crtc->base.dev;
9402         struct drm_i915_private *dev_priv = dev->dev_private;
9403         u32 reg, val;
9404
9405         if (INTEL_INFO(dev)->num_pipes == 1)
9406                 return true;
9407
9408         reg = DSPCNTR(!crtc->plane);
9409         val = I915_READ(reg);
9410
9411         if ((val & DISPLAY_PLANE_ENABLE) &&
9412             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9413                 return false;
9414
9415         return true;
9416 }
9417
9418 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9419 {
9420         struct drm_device *dev = crtc->base.dev;
9421         struct drm_i915_private *dev_priv = dev->dev_private;
9422         u32 reg;
9423
9424         /* Clear any frame start delays used for debugging left by the BIOS */
9425         reg = PIPECONF(crtc->config.cpu_transcoder);
9426         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9427
9428         /* We need to sanitize the plane -> pipe mapping first because this will
9429          * disable the crtc (and hence change the state) if it is wrong. Note
9430          * that gen4+ has a fixed plane -> pipe mapping.  */
9431         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9432                 struct intel_connector *connector;
9433                 bool plane;
9434
9435                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9436                               crtc->base.base.id);
9437
9438                 /* Pipe has the wrong plane attached and the plane is active.
9439                  * Temporarily change the plane mapping and disable everything
9440                  * ...  */
9441                 plane = crtc->plane;
9442                 crtc->plane = !plane;
9443                 dev_priv->display.crtc_disable(&crtc->base);
9444                 crtc->plane = plane;
9445
9446                 /* ... and break all links. */
9447                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9448                                     base.head) {
9449                         if (connector->encoder->base.crtc != &crtc->base)
9450                                 continue;
9451
9452                         intel_connector_break_all_links(connector);
9453                 }
9454
9455                 WARN_ON(crtc->active);
9456                 crtc->base.enabled = false;
9457         }
9458
9459         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9460             crtc->pipe == PIPE_A && !crtc->active) {
9461                 /* BIOS forgot to enable pipe A, this mostly happens after
9462                  * resume. Force-enable the pipe to fix this, the update_dpms
9463                  * call below we restore the pipe to the right state, but leave
9464                  * the required bits on. */
9465                 intel_enable_pipe_a(dev);
9466         }
9467
9468         /* Adjust the state of the output pipe according to whether we
9469          * have active connectors/encoders. */
9470         intel_crtc_update_dpms(&crtc->base);
9471
9472         if (crtc->active != crtc->base.enabled) {
9473                 struct intel_encoder *encoder;
9474
9475                 /* This can happen either due to bugs in the get_hw_state
9476                  * functions or because the pipe is force-enabled due to the
9477                  * pipe A quirk. */
9478                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9479                               crtc->base.base.id,
9480                               crtc->base.enabled ? "enabled" : "disabled",
9481                               crtc->active ? "enabled" : "disabled");
9482
9483                 crtc->base.enabled = crtc->active;
9484
9485                 /* Because we only establish the connector -> encoder ->
9486                  * crtc links if something is active, this means the
9487                  * crtc is now deactivated. Break the links. connector
9488                  * -> encoder links are only establish when things are
9489                  *  actually up, hence no need to break them. */
9490                 WARN_ON(crtc->active);
9491
9492                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9493                         WARN_ON(encoder->connectors_active);
9494                         encoder->base.crtc = NULL;
9495                 }
9496         }
9497 }
9498
9499 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9500 {
9501         struct intel_connector *connector;
9502         struct drm_device *dev = encoder->base.dev;
9503
9504         /* We need to check both for a crtc link (meaning that the
9505          * encoder is active and trying to read from a pipe) and the
9506          * pipe itself being active. */
9507         bool has_active_crtc = encoder->base.crtc &&
9508                 to_intel_crtc(encoder->base.crtc)->active;
9509
9510         if (encoder->connectors_active && !has_active_crtc) {
9511                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9512                               encoder->base.base.id,
9513                               drm_get_encoder_name(&encoder->base));
9514
9515                 /* Connector is active, but has no active pipe. This is
9516                  * fallout from our resume register restoring. Disable
9517                  * the encoder manually again. */
9518                 if (encoder->base.crtc) {
9519                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9520                                       encoder->base.base.id,
9521                                       drm_get_encoder_name(&encoder->base));
9522                         encoder->disable(encoder);
9523                 }
9524
9525                 /* Inconsistent output/port/pipe state happens presumably due to
9526                  * a bug in one of the get_hw_state functions. Or someplace else
9527                  * in our code, like the register restore mess on resume. Clamp
9528                  * things to off as a safer default. */
9529                 list_for_each_entry(connector,
9530                                     &dev->mode_config.connector_list,
9531                                     base.head) {
9532                         if (connector->encoder != encoder)
9533                                 continue;
9534
9535                         intel_connector_break_all_links(connector);
9536                 }
9537         }
9538         /* Enabled encoders without active connectors will be fixed in
9539          * the crtc fixup. */
9540 }
9541
9542 void i915_redisable_vga(struct drm_device *dev)
9543 {
9544         struct drm_i915_private *dev_priv = dev->dev_private;
9545         u32 vga_reg = i915_vgacntrl_reg(dev);
9546
9547         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9548                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9549                 i915_disable_vga(dev);
9550         }
9551 }
9552
9553 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9554  * and i915 state tracking structures. */
9555 void intel_modeset_setup_hw_state(struct drm_device *dev,
9556                                   bool force_restore)
9557 {
9558         struct drm_i915_private *dev_priv = dev->dev_private;
9559         enum pipe pipe;
9560         struct drm_plane *plane;
9561         struct intel_crtc *crtc;
9562         struct intel_encoder *encoder;
9563         struct intel_connector *connector;
9564
9565         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9566                             base.head) {
9567                 memset(&crtc->config, 0, sizeof(crtc->config));
9568
9569                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9570                                                                  &crtc->config);
9571
9572                 crtc->base.enabled = crtc->active;
9573
9574                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9575                               crtc->base.base.id,
9576                               crtc->active ? "enabled" : "disabled");
9577         }
9578
9579         if (HAS_DDI(dev))
9580                 intel_ddi_setup_hw_pll_state(dev);
9581
9582         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9583                             base.head) {
9584                 pipe = 0;
9585
9586                 if (encoder->get_hw_state(encoder, &pipe)) {
9587                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9588                         encoder->base.crtc = &crtc->base;
9589                         if (encoder->get_config)
9590                                 encoder->get_config(encoder, &crtc->config);
9591                 } else {
9592                         encoder->base.crtc = NULL;
9593                 }
9594
9595                 encoder->connectors_active = false;
9596                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9597                               encoder->base.base.id,
9598                               drm_get_encoder_name(&encoder->base),
9599                               encoder->base.crtc ? "enabled" : "disabled",
9600                               pipe);
9601         }
9602
9603         list_for_each_entry(connector, &dev->mode_config.connector_list,
9604                             base.head) {
9605                 if (connector->get_hw_state(connector)) {
9606                         connector->base.dpms = DRM_MODE_DPMS_ON;
9607                         connector->encoder->connectors_active = true;
9608                         connector->base.encoder = &connector->encoder->base;
9609                 } else {
9610                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9611                         connector->base.encoder = NULL;
9612                 }
9613                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9614                               connector->base.base.id,
9615                               drm_get_connector_name(&connector->base),
9616                               connector->base.encoder ? "enabled" : "disabled");
9617         }
9618
9619         /* HW state is read out, now we need to sanitize this mess. */
9620         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9621                             base.head) {
9622                 intel_sanitize_encoder(encoder);
9623         }
9624
9625         for_each_pipe(pipe) {
9626                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9627                 intel_sanitize_crtc(crtc);
9628                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9629         }
9630
9631         if (force_restore) {
9632                 /*
9633                  * We need to use raw interfaces for restoring state to avoid
9634                  * checking (bogus) intermediate states.
9635                  */
9636                 for_each_pipe(pipe) {
9637                         struct drm_crtc *crtc =
9638                                 dev_priv->pipe_to_crtc_mapping[pipe];
9639
9640                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9641                                          crtc->fb);
9642                 }
9643                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9644                         intel_plane_restore(plane);
9645
9646                 i915_redisable_vga(dev);
9647         } else {
9648                 intel_modeset_update_staged_output_state(dev);
9649         }
9650
9651         intel_modeset_check_state(dev);
9652
9653         drm_mode_config_reset(dev);
9654 }
9655
9656 void intel_modeset_gem_init(struct drm_device *dev)
9657 {
9658         intel_modeset_init_hw(dev);
9659
9660         intel_setup_overlay(dev);
9661
9662         intel_modeset_setup_hw_state(dev, false);
9663 }
9664
9665 void intel_modeset_cleanup(struct drm_device *dev)
9666 {
9667         struct drm_i915_private *dev_priv = dev->dev_private;
9668         struct drm_crtc *crtc;
9669         struct intel_crtc *intel_crtc;
9670
9671         /*
9672          * Interrupts and polling as the first thing to avoid creating havoc.
9673          * Too much stuff here (turning of rps, connectors, ...) would
9674          * experience fancy races otherwise.
9675          */
9676         drm_irq_uninstall(dev);
9677         cancel_work_sync(&dev_priv->hotplug_work);
9678         /*
9679          * Due to the hpd irq storm handling the hotplug work can re-arm the
9680          * poll handlers. Hence disable polling after hpd handling is shut down.
9681          */
9682         drm_kms_helper_poll_fini(dev);
9683
9684         mutex_lock(&dev->struct_mutex);
9685
9686         intel_unregister_dsm_handler();
9687
9688         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9689                 /* Skip inactive CRTCs */
9690                 if (!crtc->fb)
9691                         continue;
9692
9693                 intel_crtc = to_intel_crtc(crtc);
9694                 intel_increase_pllclock(crtc);
9695         }
9696
9697         intel_disable_fbc(dev);
9698
9699         intel_disable_gt_powersave(dev);
9700
9701         ironlake_teardown_rc6(dev);
9702
9703         mutex_unlock(&dev->struct_mutex);
9704
9705         /* flush any delayed tasks or pending work */
9706         flush_scheduled_work();
9707
9708         /* destroy backlight, if any, before the connectors */
9709         intel_panel_destroy_backlight(dev);
9710
9711         drm_mode_config_cleanup(dev);
9712
9713         intel_cleanup_overlay(dev);
9714 }
9715
9716 /*
9717  * Return which encoder is currently attached for connector.
9718  */
9719 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9720 {
9721         return &intel_attached_encoder(connector)->base;
9722 }
9723
9724 void intel_connector_attach_encoder(struct intel_connector *connector,
9725                                     struct intel_encoder *encoder)
9726 {
9727         connector->encoder = encoder;
9728         drm_mode_connector_attach_encoder(&connector->base,
9729                                           &encoder->base);
9730 }
9731
9732 /*
9733  * set vga decode state - true == enable VGA decode
9734  */
9735 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9736 {
9737         struct drm_i915_private *dev_priv = dev->dev_private;
9738         u16 gmch_ctrl;
9739
9740         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9741         if (state)
9742                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9743         else
9744                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9745         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9746         return 0;
9747 }
9748
9749 #ifdef CONFIG_DEBUG_FS
9750 #include <linux/seq_file.h>
9751
9752 struct intel_display_error_state {
9753
9754         u32 power_well_driver;
9755
9756         struct intel_cursor_error_state {
9757                 u32 control;
9758                 u32 position;
9759                 u32 base;
9760                 u32 size;
9761         } cursor[I915_MAX_PIPES];
9762
9763         struct intel_pipe_error_state {
9764                 enum transcoder cpu_transcoder;
9765                 u32 conf;
9766                 u32 source;
9767
9768                 u32 htotal;
9769                 u32 hblank;
9770                 u32 hsync;
9771                 u32 vtotal;
9772                 u32 vblank;
9773                 u32 vsync;
9774         } pipe[I915_MAX_PIPES];
9775
9776         struct intel_plane_error_state {
9777                 u32 control;
9778                 u32 stride;
9779                 u32 size;
9780                 u32 pos;
9781                 u32 addr;
9782                 u32 surface;
9783                 u32 tile_offset;
9784         } plane[I915_MAX_PIPES];
9785 };
9786
9787 struct intel_display_error_state *
9788 intel_display_capture_error_state(struct drm_device *dev)
9789 {
9790         drm_i915_private_t *dev_priv = dev->dev_private;
9791         struct intel_display_error_state *error;
9792         enum transcoder cpu_transcoder;
9793         int i;
9794
9795         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9796         if (error == NULL)
9797                 return NULL;
9798
9799         if (HAS_POWER_WELL(dev))
9800                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9801
9802         for_each_pipe(i) {
9803                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9804                 error->pipe[i].cpu_transcoder = cpu_transcoder;
9805
9806                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9807                         error->cursor[i].control = I915_READ(CURCNTR(i));
9808                         error->cursor[i].position = I915_READ(CURPOS(i));
9809                         error->cursor[i].base = I915_READ(CURBASE(i));
9810                 } else {
9811                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9812                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9813                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9814                 }
9815
9816                 error->plane[i].control = I915_READ(DSPCNTR(i));
9817                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9818                 if (INTEL_INFO(dev)->gen <= 3) {
9819                         error->plane[i].size = I915_READ(DSPSIZE(i));
9820                         error->plane[i].pos = I915_READ(DSPPOS(i));
9821                 }
9822                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9823                         error->plane[i].addr = I915_READ(DSPADDR(i));
9824                 if (INTEL_INFO(dev)->gen >= 4) {
9825                         error->plane[i].surface = I915_READ(DSPSURF(i));
9826                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9827                 }
9828
9829                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9830                 error->pipe[i].source = I915_READ(PIPESRC(i));
9831                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9832                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9833                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9834                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9835                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9836                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9837         }
9838
9839         /* In the code above we read the registers without checking if the power
9840          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9841          * prevent the next I915_WRITE from detecting it and printing an error
9842          * message. */
9843         if (HAS_POWER_WELL(dev))
9844                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9845
9846         return error;
9847 }
9848
9849 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9850
9851 void
9852 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9853                                 struct drm_device *dev,
9854                                 struct intel_display_error_state *error)
9855 {
9856         int i;
9857
9858         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9859         if (HAS_POWER_WELL(dev))
9860                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9861                            error->power_well_driver);
9862         for_each_pipe(i) {
9863                 err_printf(m, "Pipe [%d]:\n", i);
9864                 err_printf(m, "  CPU transcoder: %c\n",
9865                            transcoder_name(error->pipe[i].cpu_transcoder));
9866                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9867                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9868                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9869                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9870                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9871                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9872                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9873                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9874
9875                 err_printf(m, "Plane [%d]:\n", i);
9876                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9877                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9878                 if (INTEL_INFO(dev)->gen <= 3) {
9879                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9880                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
9881                 }
9882                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9883                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9884                 if (INTEL_INFO(dev)->gen >= 4) {
9885                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9886                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9887                 }
9888
9889                 err_printf(m, "Cursor [%d]:\n", i);
9890                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9891                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
9892                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9893         }
9894 }
9895 #endif