2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include <linux/module.h>
34 #include <drm/radeon_drm.h>
36 #include "radeon_asic.h"
37 #include "radeon_mode.h"
42 #define PFP_UCODE_SIZE 576
43 #define PM4_UCODE_SIZE 1792
44 #define RLC_UCODE_SIZE 768
45 #define R700_PFP_UCODE_SIZE 848
46 #define R700_PM4_UCODE_SIZE 1360
47 #define R700_RLC_UCODE_SIZE 1024
48 #define EVERGREEN_PFP_UCODE_SIZE 1120
49 #define EVERGREEN_PM4_UCODE_SIZE 1376
50 #define EVERGREEN_RLC_UCODE_SIZE 768
51 #define CAYMAN_RLC_UCODE_SIZE 1024
52 #define ARUBA_RLC_UCODE_SIZE 1536
55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
56 MODULE_FIRMWARE("radeon/R600_me.bin");
57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV610_me.bin");
59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV630_me.bin");
61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV620_me.bin");
63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV635_me.bin");
65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
66 MODULE_FIRMWARE("radeon/RV670_me.bin");
67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
68 MODULE_FIRMWARE("radeon/RS780_me.bin");
69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV770_me.bin");
71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV730_me.bin");
73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
74 MODULE_FIRMWARE("radeon/RV710_me.bin");
75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
90 MODULE_FIRMWARE("radeon/PALM_me.bin");
91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
97 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
99 /* r600,rv610,rv630,rv620,rv635,rv670 */
100 int r600_mc_wait_for_idle(struct radeon_device *rdev);
101 static void r600_gpu_init(struct radeon_device *rdev);
102 void r600_fini(struct radeon_device *rdev);
103 void r600_irq_disable(struct radeon_device *rdev);
104 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
106 /* get temperature in millidegrees */
107 int rv6xx_get_temp(struct radeon_device *rdev)
109 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
111 int actual_temp = temp & 0xff;
116 return actual_temp * 1000;
119 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
123 rdev->pm.dynpm_can_upclock = true;
124 rdev->pm.dynpm_can_downclock = true;
126 /* power state array is low to high, default is first */
127 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
128 int min_power_state_index = 0;
130 if (rdev->pm.num_power_states > 2)
131 min_power_state_index = 1;
133 switch (rdev->pm.dynpm_planned_action) {
134 case DYNPM_ACTION_MINIMUM:
135 rdev->pm.requested_power_state_index = min_power_state_index;
136 rdev->pm.requested_clock_mode_index = 0;
137 rdev->pm.dynpm_can_downclock = false;
139 case DYNPM_ACTION_DOWNCLOCK:
140 if (rdev->pm.current_power_state_index == min_power_state_index) {
141 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
142 rdev->pm.dynpm_can_downclock = false;
144 if (rdev->pm.active_crtc_count > 1) {
145 for (i = 0; i < rdev->pm.num_power_states; i++) {
146 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
148 else if (i >= rdev->pm.current_power_state_index) {
149 rdev->pm.requested_power_state_index =
150 rdev->pm.current_power_state_index;
153 rdev->pm.requested_power_state_index = i;
158 if (rdev->pm.current_power_state_index == 0)
159 rdev->pm.requested_power_state_index =
160 rdev->pm.num_power_states - 1;
162 rdev->pm.requested_power_state_index =
163 rdev->pm.current_power_state_index - 1;
166 rdev->pm.requested_clock_mode_index = 0;
167 /* don't use the power state if crtcs are active and no display flag is set */
168 if ((rdev->pm.active_crtc_count > 0) &&
169 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
170 clock_info[rdev->pm.requested_clock_mode_index].flags &
171 RADEON_PM_MODE_NO_DISPLAY)) {
172 rdev->pm.requested_power_state_index++;
175 case DYNPM_ACTION_UPCLOCK:
176 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
177 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
178 rdev->pm.dynpm_can_upclock = false;
180 if (rdev->pm.active_crtc_count > 1) {
181 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
182 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
184 else if (i <= rdev->pm.current_power_state_index) {
185 rdev->pm.requested_power_state_index =
186 rdev->pm.current_power_state_index;
189 rdev->pm.requested_power_state_index = i;
194 rdev->pm.requested_power_state_index =
195 rdev->pm.current_power_state_index + 1;
197 rdev->pm.requested_clock_mode_index = 0;
199 case DYNPM_ACTION_DEFAULT:
200 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
201 rdev->pm.requested_clock_mode_index = 0;
202 rdev->pm.dynpm_can_upclock = false;
204 case DYNPM_ACTION_NONE:
206 DRM_ERROR("Requested mode for not defined action\n");
210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
211 /* for now just select the first power state and switch between clock modes */
212 /* power state array is low to high, default is first (0) */
213 if (rdev->pm.active_crtc_count > 1) {
214 rdev->pm.requested_power_state_index = -1;
215 /* start at 1 as we don't want the default mode */
216 for (i = 1; i < rdev->pm.num_power_states; i++) {
217 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
219 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
220 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
221 rdev->pm.requested_power_state_index = i;
225 /* if nothing selected, grab the default state. */
226 if (rdev->pm.requested_power_state_index == -1)
227 rdev->pm.requested_power_state_index = 0;
229 rdev->pm.requested_power_state_index = 1;
231 switch (rdev->pm.dynpm_planned_action) {
232 case DYNPM_ACTION_MINIMUM:
233 rdev->pm.requested_clock_mode_index = 0;
234 rdev->pm.dynpm_can_downclock = false;
236 case DYNPM_ACTION_DOWNCLOCK:
237 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
238 if (rdev->pm.current_clock_mode_index == 0) {
239 rdev->pm.requested_clock_mode_index = 0;
240 rdev->pm.dynpm_can_downclock = false;
242 rdev->pm.requested_clock_mode_index =
243 rdev->pm.current_clock_mode_index - 1;
245 rdev->pm.requested_clock_mode_index = 0;
246 rdev->pm.dynpm_can_downclock = false;
248 /* don't use the power state if crtcs are active and no display flag is set */
249 if ((rdev->pm.active_crtc_count > 0) &&
250 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
251 clock_info[rdev->pm.requested_clock_mode_index].flags &
252 RADEON_PM_MODE_NO_DISPLAY)) {
253 rdev->pm.requested_clock_mode_index++;
256 case DYNPM_ACTION_UPCLOCK:
257 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
258 if (rdev->pm.current_clock_mode_index ==
259 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
260 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
261 rdev->pm.dynpm_can_upclock = false;
263 rdev->pm.requested_clock_mode_index =
264 rdev->pm.current_clock_mode_index + 1;
266 rdev->pm.requested_clock_mode_index =
267 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
268 rdev->pm.dynpm_can_upclock = false;
271 case DYNPM_ACTION_DEFAULT:
272 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
273 rdev->pm.requested_clock_mode_index = 0;
274 rdev->pm.dynpm_can_upclock = false;
276 case DYNPM_ACTION_NONE:
278 DRM_ERROR("Requested mode for not defined action\n");
283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].sclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 clock_info[rdev->pm.requested_clock_mode_index].mclk,
288 rdev->pm.power_state[rdev->pm.requested_power_state_index].
292 void rs780_pm_init_profile(struct radeon_device *rdev)
294 if (rdev->pm.num_power_states == 2) {
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
330 } else if (rdev->pm.num_power_states == 3) {
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
405 void r600_pm_init_profile(struct radeon_device *rdev)
409 if (rdev->family == CHIP_R600) {
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
447 if (rdev->pm.num_power_states < 4) {
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
490 if (rdev->flags & RADEON_IS_MOBILITY)
491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
493 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
504 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
508 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
510 if (rdev->flags & RADEON_IS_MOBILITY)
511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
513 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
533 void r600_pm_misc(struct radeon_device *rdev)
535 int req_ps_idx = rdev->pm.requested_power_state_index;
536 int req_cm_idx = rdev->pm.requested_clock_mode_index;
537 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
538 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
540 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
541 /* 0xff01 is a flag rather then an actual voltage */
542 if (voltage->voltage == 0xff01)
544 if (voltage->voltage != rdev->pm.current_vddc) {
545 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
546 rdev->pm.current_vddc = voltage->voltage;
547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
552 bool r600_gui_idle(struct radeon_device *rdev)
554 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
560 /* hpd for digital panel detect/disconnect */
561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
563 bool connected = false;
565 if (ASIC_IS_DCE3(rdev)) {
568 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
572 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
576 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
580 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
585 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
589 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
616 void r600_hpd_set_polarity(struct radeon_device *rdev,
617 enum radeon_hpd_id hpd)
620 bool connected = r600_hpd_sense(rdev, hpd);
622 if (ASIC_IS_DCE3(rdev)) {
625 tmp = RREG32(DC_HPD1_INT_CONTROL);
627 tmp &= ~DC_HPDx_INT_POLARITY;
629 tmp |= DC_HPDx_INT_POLARITY;
630 WREG32(DC_HPD1_INT_CONTROL, tmp);
633 tmp = RREG32(DC_HPD2_INT_CONTROL);
635 tmp &= ~DC_HPDx_INT_POLARITY;
637 tmp |= DC_HPDx_INT_POLARITY;
638 WREG32(DC_HPD2_INT_CONTROL, tmp);
641 tmp = RREG32(DC_HPD3_INT_CONTROL);
643 tmp &= ~DC_HPDx_INT_POLARITY;
645 tmp |= DC_HPDx_INT_POLARITY;
646 WREG32(DC_HPD3_INT_CONTROL, tmp);
649 tmp = RREG32(DC_HPD4_INT_CONTROL);
651 tmp &= ~DC_HPDx_INT_POLARITY;
653 tmp |= DC_HPDx_INT_POLARITY;
654 WREG32(DC_HPD4_INT_CONTROL, tmp);
657 tmp = RREG32(DC_HPD5_INT_CONTROL);
659 tmp &= ~DC_HPDx_INT_POLARITY;
661 tmp |= DC_HPDx_INT_POLARITY;
662 WREG32(DC_HPD5_INT_CONTROL, tmp);
666 tmp = RREG32(DC_HPD6_INT_CONTROL);
668 tmp &= ~DC_HPDx_INT_POLARITY;
670 tmp |= DC_HPDx_INT_POLARITY;
671 WREG32(DC_HPD6_INT_CONTROL, tmp);
679 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
681 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
683 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
687 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
695 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
708 void r600_hpd_init(struct radeon_device *rdev)
710 struct drm_device *dev = rdev->ddev;
711 struct drm_connector *connector;
714 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
715 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
717 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
718 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
719 /* don't try to enable hpd on eDP or LVDS avoid breaking the
720 * aux dp channel on imac and help (but not completely fix)
721 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
725 if (ASIC_IS_DCE3(rdev)) {
726 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
727 if (ASIC_IS_DCE32(rdev))
730 switch (radeon_connector->hpd.hpd) {
732 WREG32(DC_HPD1_CONTROL, tmp);
735 WREG32(DC_HPD2_CONTROL, tmp);
738 WREG32(DC_HPD3_CONTROL, tmp);
741 WREG32(DC_HPD4_CONTROL, tmp);
745 WREG32(DC_HPD5_CONTROL, tmp);
748 WREG32(DC_HPD6_CONTROL, tmp);
754 switch (radeon_connector->hpd.hpd) {
756 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
759 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
762 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
768 enable |= 1 << radeon_connector->hpd.hpd;
769 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
771 radeon_irq_kms_enable_hpd(rdev, enable);
774 void r600_hpd_fini(struct radeon_device *rdev)
776 struct drm_device *dev = rdev->ddev;
777 struct drm_connector *connector;
778 unsigned disable = 0;
780 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
781 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
782 if (ASIC_IS_DCE3(rdev)) {
783 switch (radeon_connector->hpd.hpd) {
785 WREG32(DC_HPD1_CONTROL, 0);
788 WREG32(DC_HPD2_CONTROL, 0);
791 WREG32(DC_HPD3_CONTROL, 0);
794 WREG32(DC_HPD4_CONTROL, 0);
798 WREG32(DC_HPD5_CONTROL, 0);
801 WREG32(DC_HPD6_CONTROL, 0);
807 switch (radeon_connector->hpd.hpd) {
809 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
812 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
815 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
821 disable |= 1 << radeon_connector->hpd.hpd;
823 radeon_irq_kms_disable_hpd(rdev, disable);
829 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
834 /* flush hdp cache so updates hit vram */
835 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
836 !(rdev->flags & RADEON_IS_AGP)) {
837 void __iomem *ptr = (void *)rdev->gart.ptr;
840 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
841 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
842 * This seems to cause problems on some AGP cards. Just use the old
845 WREG32(HDP_DEBUG1, 0);
846 tmp = readl((void __iomem *)ptr);
848 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
850 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
851 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
852 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
853 for (i = 0; i < rdev->usec_timeout; i++) {
855 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
856 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
858 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
868 int r600_pcie_gart_init(struct radeon_device *rdev)
872 if (rdev->gart.robj) {
873 WARN(1, "R600 PCIE GART already initialized\n");
876 /* Initialize common gart structure */
877 r = radeon_gart_init(rdev);
880 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
881 return radeon_gart_table_vram_alloc(rdev);
884 static int r600_pcie_gart_enable(struct radeon_device *rdev)
889 if (rdev->gart.robj == NULL) {
890 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
893 r = radeon_gart_table_vram_pin(rdev);
896 radeon_gart_restore(rdev);
899 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
900 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
901 EFFECTIVE_L2_QUEUE_SIZE(7));
902 WREG32(VM_L2_CNTL2, 0);
903 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
904 /* Setup TLB control */
905 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
906 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
907 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
908 ENABLE_WAIT_L2_QUERY;
909 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
910 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
911 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
912 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
913 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
914 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
915 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
916 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
917 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
918 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
920 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
921 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
922 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
923 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
924 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
925 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
926 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
927 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
928 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
929 (u32)(rdev->dummy_page.addr >> 12));
930 for (i = 1; i < 7; i++)
931 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
933 r600_pcie_gart_tlb_flush(rdev);
934 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
935 (unsigned)(rdev->mc.gtt_size >> 20),
936 (unsigned long long)rdev->gart.table_addr);
937 rdev->gart.ready = true;
941 static void r600_pcie_gart_disable(struct radeon_device *rdev)
946 /* Disable all tables */
947 for (i = 0; i < 7; i++)
948 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
950 /* Disable L2 cache */
951 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
952 EFFECTIVE_L2_QUEUE_SIZE(7));
953 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
954 /* Setup L1 TLB control */
955 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
956 ENABLE_WAIT_L2_QUERY;
957 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
958 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
959 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
960 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
961 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
962 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
963 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
964 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
965 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
971 radeon_gart_table_vram_unpin(rdev);
974 static void r600_pcie_gart_fini(struct radeon_device *rdev)
976 radeon_gart_fini(rdev);
977 r600_pcie_gart_disable(rdev);
978 radeon_gart_table_vram_free(rdev);
981 static void r600_agp_enable(struct radeon_device *rdev)
987 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
988 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
989 EFFECTIVE_L2_QUEUE_SIZE(7));
990 WREG32(VM_L2_CNTL2, 0);
991 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
992 /* Setup TLB control */
993 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
994 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
995 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
996 ENABLE_WAIT_L2_QUERY;
997 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
998 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
999 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1000 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1001 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1002 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1003 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1004 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1005 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1008 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1010 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1011 for (i = 0; i < 7; i++)
1012 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1015 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1020 for (i = 0; i < rdev->usec_timeout; i++) {
1021 /* read MC_STATUS */
1022 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1030 static void r600_mc_program(struct radeon_device *rdev)
1032 struct rv515_mc_save save;
1036 /* Initialize HDP */
1037 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1038 WREG32((0x2c14 + j), 0x00000000);
1039 WREG32((0x2c18 + j), 0x00000000);
1040 WREG32((0x2c1c + j), 0x00000000);
1041 WREG32((0x2c20 + j), 0x00000000);
1042 WREG32((0x2c24 + j), 0x00000000);
1044 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1046 rv515_mc_stop(rdev, &save);
1047 if (r600_mc_wait_for_idle(rdev)) {
1048 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1050 /* Lockout access through VGA aperture (doesn't exist before R600) */
1051 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1052 /* Update configuration */
1053 if (rdev->flags & RADEON_IS_AGP) {
1054 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1055 /* VRAM before AGP */
1056 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1057 rdev->mc.vram_start >> 12);
1058 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1059 rdev->mc.gtt_end >> 12);
1061 /* VRAM after AGP */
1062 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1063 rdev->mc.gtt_start >> 12);
1064 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1065 rdev->mc.vram_end >> 12);
1068 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1069 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1071 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1072 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1073 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1074 WREG32(MC_VM_FB_LOCATION, tmp);
1075 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1076 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1077 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1078 if (rdev->flags & RADEON_IS_AGP) {
1079 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1080 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1081 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1083 WREG32(MC_VM_AGP_BASE, 0);
1084 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1085 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1087 if (r600_mc_wait_for_idle(rdev)) {
1088 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1090 rv515_mc_resume(rdev, &save);
1091 /* we need to own VRAM, so turn off the VGA renderer here
1092 * to stop it overwriting our objects */
1093 rv515_vga_render_disable(rdev);
1097 * r600_vram_gtt_location - try to find VRAM & GTT location
1098 * @rdev: radeon device structure holding all necessary informations
1099 * @mc: memory controller structure holding memory informations
1101 * Function will place try to place VRAM at same place as in CPU (PCI)
1102 * address space as some GPU seems to have issue when we reprogram at
1103 * different address space.
1105 * If there is not enough space to fit the unvisible VRAM after the
1106 * aperture then we limit the VRAM size to the aperture.
1108 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1109 * them to be in one from GPU point of view so that we can program GPU to
1110 * catch access outside them (weird GPU policy see ??).
1112 * This function will never fails, worst case are limiting VRAM or GTT.
1114 * Note: GTT start, end, size should be initialized before calling this
1115 * function on AGP platform.
1117 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1119 u64 size_bf, size_af;
1121 if (mc->mc_vram_size > 0xE0000000) {
1122 /* leave room for at least 512M GTT */
1123 dev_warn(rdev->dev, "limiting VRAM\n");
1124 mc->real_vram_size = 0xE0000000;
1125 mc->mc_vram_size = 0xE0000000;
1127 if (rdev->flags & RADEON_IS_AGP) {
1128 size_bf = mc->gtt_start;
1129 size_af = 0xFFFFFFFF - mc->gtt_end;
1130 if (size_bf > size_af) {
1131 if (mc->mc_vram_size > size_bf) {
1132 dev_warn(rdev->dev, "limiting VRAM\n");
1133 mc->real_vram_size = size_bf;
1134 mc->mc_vram_size = size_bf;
1136 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1138 if (mc->mc_vram_size > size_af) {
1139 dev_warn(rdev->dev, "limiting VRAM\n");
1140 mc->real_vram_size = size_af;
1141 mc->mc_vram_size = size_af;
1143 mc->vram_start = mc->gtt_end + 1;
1145 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1146 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1147 mc->mc_vram_size >> 20, mc->vram_start,
1148 mc->vram_end, mc->real_vram_size >> 20);
1151 if (rdev->flags & RADEON_IS_IGP) {
1152 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1155 radeon_vram_location(rdev, &rdev->mc, base);
1156 rdev->mc.gtt_base_align = 0;
1157 radeon_gtt_location(rdev, mc);
1161 static int r600_mc_init(struct radeon_device *rdev)
1164 int chansize, numchan;
1166 /* Get VRAM informations */
1167 rdev->mc.vram_is_ddr = true;
1168 tmp = RREG32(RAMCFG);
1169 if (tmp & CHANSIZE_OVERRIDE) {
1171 } else if (tmp & CHANSIZE_MASK) {
1176 tmp = RREG32(CHMAP);
1177 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1192 rdev->mc.vram_width = numchan * chansize;
1193 /* Could aper size report 0 ? */
1194 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1195 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1196 /* Setup GPU memory space */
1197 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1198 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1199 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1200 r600_vram_gtt_location(rdev, &rdev->mc);
1202 if (rdev->flags & RADEON_IS_IGP) {
1203 rs690_pm_info(rdev);
1204 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1206 radeon_update_bandwidth_info(rdev);
1210 int r600_vram_scratch_init(struct radeon_device *rdev)
1214 if (rdev->vram_scratch.robj == NULL) {
1215 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1216 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1217 NULL, &rdev->vram_scratch.robj);
1223 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1224 if (unlikely(r != 0))
1226 r = radeon_bo_pin(rdev->vram_scratch.robj,
1227 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1229 radeon_bo_unreserve(rdev->vram_scratch.robj);
1232 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1233 (void **)&rdev->vram_scratch.ptr);
1235 radeon_bo_unpin(rdev->vram_scratch.robj);
1236 radeon_bo_unreserve(rdev->vram_scratch.robj);
1241 void r600_vram_scratch_fini(struct radeon_device *rdev)
1245 if (rdev->vram_scratch.robj == NULL) {
1248 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1249 if (likely(r == 0)) {
1250 radeon_bo_kunmap(rdev->vram_scratch.robj);
1251 radeon_bo_unpin(rdev->vram_scratch.robj);
1252 radeon_bo_unreserve(rdev->vram_scratch.robj);
1254 radeon_bo_unref(&rdev->vram_scratch.robj);
1257 /* We doesn't check that the GPU really needs a reset we simply do the
1258 * reset, it's up to the caller to determine if the GPU needs one. We
1259 * might add an helper function to check that.
1261 static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)
1263 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1264 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1265 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1266 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1267 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1268 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1269 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1270 S_008010_GUI_ACTIVE(1);
1271 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1272 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1273 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1274 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1275 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1276 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1277 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1278 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1281 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1284 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1285 RREG32(R_008010_GRBM_STATUS));
1286 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1287 RREG32(R_008014_GRBM_STATUS2));
1288 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1289 RREG32(R_000E50_SRBM_STATUS));
1290 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1291 RREG32(CP_STALLED_STAT1));
1292 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1293 RREG32(CP_STALLED_STAT2));
1294 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1295 RREG32(CP_BUSY_STAT));
1296 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1299 /* Disable CP parsing/prefetching */
1300 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1302 /* Check if any of the rendering block is busy and reset it */
1303 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1304 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1305 tmp = S_008020_SOFT_RESET_CR(1) |
1306 S_008020_SOFT_RESET_DB(1) |
1307 S_008020_SOFT_RESET_CB(1) |
1308 S_008020_SOFT_RESET_PA(1) |
1309 S_008020_SOFT_RESET_SC(1) |
1310 S_008020_SOFT_RESET_SMX(1) |
1311 S_008020_SOFT_RESET_SPI(1) |
1312 S_008020_SOFT_RESET_SX(1) |
1313 S_008020_SOFT_RESET_SH(1) |
1314 S_008020_SOFT_RESET_TC(1) |
1315 S_008020_SOFT_RESET_TA(1) |
1316 S_008020_SOFT_RESET_VC(1) |
1317 S_008020_SOFT_RESET_VGT(1);
1318 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1319 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1320 RREG32(R_008020_GRBM_SOFT_RESET);
1322 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1324 /* Reset CP (we always reset CP) */
1325 tmp = S_008020_SOFT_RESET_CP(1);
1326 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1327 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1328 RREG32(R_008020_GRBM_SOFT_RESET);
1330 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1332 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1333 RREG32(R_008010_GRBM_STATUS));
1334 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1335 RREG32(R_008014_GRBM_STATUS2));
1336 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1337 RREG32(R_000E50_SRBM_STATUS));
1338 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1339 RREG32(CP_STALLED_STAT1));
1340 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1341 RREG32(CP_STALLED_STAT2));
1342 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1343 RREG32(CP_BUSY_STAT));
1344 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1349 static void r600_gpu_soft_reset_dma(struct radeon_device *rdev)
1353 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1356 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1357 RREG32(DMA_STATUS_REG));
1360 tmp = RREG32(DMA_RB_CNTL);
1361 tmp &= ~DMA_RB_ENABLE;
1362 WREG32(DMA_RB_CNTL, tmp);
1365 if (rdev->family >= CHIP_RV770)
1366 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
1368 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
1369 RREG32(SRBM_SOFT_RESET);
1371 WREG32(SRBM_SOFT_RESET, 0);
1373 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1374 RREG32(DMA_STATUS_REG));
1377 static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1379 struct rv515_mc_save save;
1381 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1382 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
1384 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1385 reset_mask &= ~RADEON_RESET_DMA;
1387 if (reset_mask == 0)
1390 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1392 rv515_mc_stop(rdev, &save);
1393 if (r600_mc_wait_for_idle(rdev)) {
1394 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1397 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
1398 r600_gpu_soft_reset_gfx(rdev);
1400 if (reset_mask & RADEON_RESET_DMA)
1401 r600_gpu_soft_reset_dma(rdev);
1403 /* Wait a little for things to settle down */
1406 rv515_mc_resume(rdev, &save);
1410 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1416 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1417 grbm_status = RREG32(R_008010_GRBM_STATUS);
1418 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1419 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1420 radeon_ring_lockup_update(ring);
1423 /* force CP activities */
1424 radeon_ring_force_activity(rdev, ring);
1425 return radeon_ring_test_lockup(rdev, ring);
1429 * r600_dma_is_lockup - Check if the DMA engine is locked up
1431 * @rdev: radeon_device pointer
1432 * @ring: radeon_ring structure holding ring information
1434 * Check if the async DMA engine is locked up (r6xx-evergreen).
1435 * Returns true if the engine appears to be locked up, false if not.
1437 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1441 dma_status_reg = RREG32(DMA_STATUS_REG);
1442 if (dma_status_reg & DMA_IDLE) {
1443 radeon_ring_lockup_update(ring);
1446 /* force ring activities */
1447 radeon_ring_force_activity(rdev, ring);
1448 return radeon_ring_test_lockup(rdev, ring);
1451 int r600_asic_reset(struct radeon_device *rdev)
1453 return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
1454 RADEON_RESET_COMPUTE |
1458 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1459 u32 tiling_pipe_num,
1461 u32 total_max_rb_num,
1462 u32 disabled_rb_mask)
1464 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1465 u32 pipe_rb_ratio, pipe_rb_remain;
1466 u32 data = 0, mask = 1 << (max_rb_num - 1);
1469 /* mask out the RBs that don't exist on that asic */
1470 disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
1472 rendering_pipe_num = 1 << tiling_pipe_num;
1473 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1474 BUG_ON(rendering_pipe_num < req_rb_num);
1476 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1477 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1479 if (rdev->family <= CHIP_RV740) {
1487 for (i = 0; i < max_rb_num; i++) {
1488 if (!(mask & disabled_rb_mask)) {
1489 for (j = 0; j < pipe_rb_ratio; j++) {
1490 data <<= rb_num_width;
1491 data |= max_rb_num - i - 1;
1493 if (pipe_rb_remain) {
1494 data <<= rb_num_width;
1495 data |= max_rb_num - i - 1;
1505 int r600_count_pipe_bits(uint32_t val)
1507 return hweight32(val);
1510 static void r600_gpu_init(struct radeon_device *rdev)
1514 u32 cc_rb_backend_disable;
1515 u32 cc_gc_shader_pipe_config;
1519 u32 sq_gpr_resource_mgmt_1 = 0;
1520 u32 sq_gpr_resource_mgmt_2 = 0;
1521 u32 sq_thread_resource_mgmt = 0;
1522 u32 sq_stack_resource_mgmt_1 = 0;
1523 u32 sq_stack_resource_mgmt_2 = 0;
1524 u32 disabled_rb_mask;
1526 rdev->config.r600.tiling_group_size = 256;
1527 switch (rdev->family) {
1529 rdev->config.r600.max_pipes = 4;
1530 rdev->config.r600.max_tile_pipes = 8;
1531 rdev->config.r600.max_simds = 4;
1532 rdev->config.r600.max_backends = 4;
1533 rdev->config.r600.max_gprs = 256;
1534 rdev->config.r600.max_threads = 192;
1535 rdev->config.r600.max_stack_entries = 256;
1536 rdev->config.r600.max_hw_contexts = 8;
1537 rdev->config.r600.max_gs_threads = 16;
1538 rdev->config.r600.sx_max_export_size = 128;
1539 rdev->config.r600.sx_max_export_pos_size = 16;
1540 rdev->config.r600.sx_max_export_smx_size = 128;
1541 rdev->config.r600.sq_num_cf_insts = 2;
1545 rdev->config.r600.max_pipes = 2;
1546 rdev->config.r600.max_tile_pipes = 2;
1547 rdev->config.r600.max_simds = 3;
1548 rdev->config.r600.max_backends = 1;
1549 rdev->config.r600.max_gprs = 128;
1550 rdev->config.r600.max_threads = 192;
1551 rdev->config.r600.max_stack_entries = 128;
1552 rdev->config.r600.max_hw_contexts = 8;
1553 rdev->config.r600.max_gs_threads = 4;
1554 rdev->config.r600.sx_max_export_size = 128;
1555 rdev->config.r600.sx_max_export_pos_size = 16;
1556 rdev->config.r600.sx_max_export_smx_size = 128;
1557 rdev->config.r600.sq_num_cf_insts = 2;
1563 rdev->config.r600.max_pipes = 1;
1564 rdev->config.r600.max_tile_pipes = 1;
1565 rdev->config.r600.max_simds = 2;
1566 rdev->config.r600.max_backends = 1;
1567 rdev->config.r600.max_gprs = 128;
1568 rdev->config.r600.max_threads = 192;
1569 rdev->config.r600.max_stack_entries = 128;
1570 rdev->config.r600.max_hw_contexts = 4;
1571 rdev->config.r600.max_gs_threads = 4;
1572 rdev->config.r600.sx_max_export_size = 128;
1573 rdev->config.r600.sx_max_export_pos_size = 16;
1574 rdev->config.r600.sx_max_export_smx_size = 128;
1575 rdev->config.r600.sq_num_cf_insts = 1;
1578 rdev->config.r600.max_pipes = 4;
1579 rdev->config.r600.max_tile_pipes = 4;
1580 rdev->config.r600.max_simds = 4;
1581 rdev->config.r600.max_backends = 4;
1582 rdev->config.r600.max_gprs = 192;
1583 rdev->config.r600.max_threads = 192;
1584 rdev->config.r600.max_stack_entries = 256;
1585 rdev->config.r600.max_hw_contexts = 8;
1586 rdev->config.r600.max_gs_threads = 16;
1587 rdev->config.r600.sx_max_export_size = 128;
1588 rdev->config.r600.sx_max_export_pos_size = 16;
1589 rdev->config.r600.sx_max_export_smx_size = 128;
1590 rdev->config.r600.sq_num_cf_insts = 2;
1596 /* Initialize HDP */
1597 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1598 WREG32((0x2c14 + j), 0x00000000);
1599 WREG32((0x2c18 + j), 0x00000000);
1600 WREG32((0x2c1c + j), 0x00000000);
1601 WREG32((0x2c20 + j), 0x00000000);
1602 WREG32((0x2c24 + j), 0x00000000);
1605 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1609 ramcfg = RREG32(RAMCFG);
1610 switch (rdev->config.r600.max_tile_pipes) {
1612 tiling_config |= PIPE_TILING(0);
1615 tiling_config |= PIPE_TILING(1);
1618 tiling_config |= PIPE_TILING(2);
1621 tiling_config |= PIPE_TILING(3);
1626 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1627 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1628 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1629 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1631 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1633 tiling_config |= ROW_TILING(3);
1634 tiling_config |= SAMPLE_SPLIT(3);
1636 tiling_config |= ROW_TILING(tmp);
1637 tiling_config |= SAMPLE_SPLIT(tmp);
1639 tiling_config |= BANK_SWAPS(1);
1641 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1642 tmp = R6XX_MAX_BACKENDS -
1643 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1644 if (tmp < rdev->config.r600.max_backends) {
1645 rdev->config.r600.max_backends = tmp;
1648 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1649 tmp = R6XX_MAX_PIPES -
1650 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1651 if (tmp < rdev->config.r600.max_pipes) {
1652 rdev->config.r600.max_pipes = tmp;
1654 tmp = R6XX_MAX_SIMDS -
1655 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1656 if (tmp < rdev->config.r600.max_simds) {
1657 rdev->config.r600.max_simds = tmp;
1660 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1661 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1662 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1663 R6XX_MAX_BACKENDS, disabled_rb_mask);
1664 tiling_config |= tmp << 16;
1665 rdev->config.r600.backend_map = tmp;
1667 rdev->config.r600.tile_config = tiling_config;
1668 WREG32(GB_TILING_CONFIG, tiling_config);
1669 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1670 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1671 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1673 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1674 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1675 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1677 /* Setup some CP states */
1678 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1679 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1681 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1682 SYNC_WALKER | SYNC_ALIGNER));
1683 /* Setup various GPU states */
1684 if (rdev->family == CHIP_RV670)
1685 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1687 tmp = RREG32(SX_DEBUG_1);
1688 tmp |= SMX_EVENT_RELEASE;
1689 if ((rdev->family > CHIP_R600))
1690 tmp |= ENABLE_NEW_SMX_ADDRESS;
1691 WREG32(SX_DEBUG_1, tmp);
1693 if (((rdev->family) == CHIP_R600) ||
1694 ((rdev->family) == CHIP_RV630) ||
1695 ((rdev->family) == CHIP_RV610) ||
1696 ((rdev->family) == CHIP_RV620) ||
1697 ((rdev->family) == CHIP_RS780) ||
1698 ((rdev->family) == CHIP_RS880)) {
1699 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1701 WREG32(DB_DEBUG, 0);
1703 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1704 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1706 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1707 WREG32(VGT_NUM_INSTANCES, 0);
1709 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1710 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1712 tmp = RREG32(SQ_MS_FIFO_SIZES);
1713 if (((rdev->family) == CHIP_RV610) ||
1714 ((rdev->family) == CHIP_RV620) ||
1715 ((rdev->family) == CHIP_RS780) ||
1716 ((rdev->family) == CHIP_RS880)) {
1717 tmp = (CACHE_FIFO_SIZE(0xa) |
1718 FETCH_FIFO_HIWATER(0xa) |
1719 DONE_FIFO_HIWATER(0xe0) |
1720 ALU_UPDATE_FIFO_HIWATER(0x8));
1721 } else if (((rdev->family) == CHIP_R600) ||
1722 ((rdev->family) == CHIP_RV630)) {
1723 tmp &= ~DONE_FIFO_HIWATER(0xff);
1724 tmp |= DONE_FIFO_HIWATER(0x4);
1726 WREG32(SQ_MS_FIFO_SIZES, tmp);
1728 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1729 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1731 sq_config = RREG32(SQ_CONFIG);
1732 sq_config &= ~(PS_PRIO(3) |
1736 sq_config |= (DX9_CONSTS |
1743 if ((rdev->family) == CHIP_R600) {
1744 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1746 NUM_CLAUSE_TEMP_GPRS(4));
1747 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1749 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1750 NUM_VS_THREADS(48) |
1753 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1754 NUM_VS_STACK_ENTRIES(128));
1755 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1756 NUM_ES_STACK_ENTRIES(0));
1757 } else if (((rdev->family) == CHIP_RV610) ||
1758 ((rdev->family) == CHIP_RV620) ||
1759 ((rdev->family) == CHIP_RS780) ||
1760 ((rdev->family) == CHIP_RS880)) {
1761 /* no vertex cache */
1762 sq_config &= ~VC_ENABLE;
1764 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1766 NUM_CLAUSE_TEMP_GPRS(2));
1767 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1769 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1770 NUM_VS_THREADS(78) |
1772 NUM_ES_THREADS(31));
1773 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1774 NUM_VS_STACK_ENTRIES(40));
1775 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1776 NUM_ES_STACK_ENTRIES(16));
1777 } else if (((rdev->family) == CHIP_RV630) ||
1778 ((rdev->family) == CHIP_RV635)) {
1779 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1781 NUM_CLAUSE_TEMP_GPRS(2));
1782 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1784 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1785 NUM_VS_THREADS(78) |
1787 NUM_ES_THREADS(31));
1788 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1789 NUM_VS_STACK_ENTRIES(40));
1790 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1791 NUM_ES_STACK_ENTRIES(16));
1792 } else if ((rdev->family) == CHIP_RV670) {
1793 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1795 NUM_CLAUSE_TEMP_GPRS(2));
1796 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1798 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1799 NUM_VS_THREADS(78) |
1801 NUM_ES_THREADS(31));
1802 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1803 NUM_VS_STACK_ENTRIES(64));
1804 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1805 NUM_ES_STACK_ENTRIES(64));
1808 WREG32(SQ_CONFIG, sq_config);
1809 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1810 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1811 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1812 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1813 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1815 if (((rdev->family) == CHIP_RV610) ||
1816 ((rdev->family) == CHIP_RV620) ||
1817 ((rdev->family) == CHIP_RS780) ||
1818 ((rdev->family) == CHIP_RS880)) {
1819 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1821 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1824 /* More default values. 2D/3D driver should adjust as needed */
1825 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1826 S1_X(0x4) | S1_Y(0xc)));
1827 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1828 S1_X(0x2) | S1_Y(0x2) |
1829 S2_X(0xa) | S2_Y(0x6) |
1830 S3_X(0x6) | S3_Y(0xa)));
1831 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1832 S1_X(0x4) | S1_Y(0xc) |
1833 S2_X(0x1) | S2_Y(0x6) |
1834 S3_X(0xa) | S3_Y(0xe)));
1835 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1836 S5_X(0x0) | S5_Y(0x0) |
1837 S6_X(0xb) | S6_Y(0x4) |
1838 S7_X(0x7) | S7_Y(0x8)));
1840 WREG32(VGT_STRMOUT_EN, 0);
1841 tmp = rdev->config.r600.max_pipes * 16;
1842 switch (rdev->family) {
1858 WREG32(VGT_ES_PER_GS, 128);
1859 WREG32(VGT_GS_PER_ES, tmp);
1860 WREG32(VGT_GS_PER_VS, 2);
1861 WREG32(VGT_GS_VERTEX_REUSE, 16);
1863 /* more default values. 2D/3D driver should adjust as needed */
1864 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1865 WREG32(VGT_STRMOUT_EN, 0);
1867 WREG32(PA_SC_MODE_CNTL, 0);
1868 WREG32(PA_SC_AA_CONFIG, 0);
1869 WREG32(PA_SC_LINE_STIPPLE, 0);
1870 WREG32(SPI_INPUT_Z, 0);
1871 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1872 WREG32(CB_COLOR7_FRAG, 0);
1874 /* Clear render buffer base addresses */
1875 WREG32(CB_COLOR0_BASE, 0);
1876 WREG32(CB_COLOR1_BASE, 0);
1877 WREG32(CB_COLOR2_BASE, 0);
1878 WREG32(CB_COLOR3_BASE, 0);
1879 WREG32(CB_COLOR4_BASE, 0);
1880 WREG32(CB_COLOR5_BASE, 0);
1881 WREG32(CB_COLOR6_BASE, 0);
1882 WREG32(CB_COLOR7_BASE, 0);
1883 WREG32(CB_COLOR7_FRAG, 0);
1885 switch (rdev->family) {
1890 tmp = TC_L2_SIZE(8);
1894 tmp = TC_L2_SIZE(4);
1897 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1900 tmp = TC_L2_SIZE(0);
1903 WREG32(TC_CNTL, tmp);
1905 tmp = RREG32(HDP_HOST_PATH_CNTL);
1906 WREG32(HDP_HOST_PATH_CNTL, tmp);
1908 tmp = RREG32(ARB_POP);
1909 tmp |= ENABLE_TC128;
1910 WREG32(ARB_POP, tmp);
1912 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1913 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1915 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1916 WREG32(VC_ENHANCE, 0);
1921 * Indirect registers accessor
1923 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1927 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1928 (void)RREG32(PCIE_PORT_INDEX);
1929 r = RREG32(PCIE_PORT_DATA);
1933 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1935 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1936 (void)RREG32(PCIE_PORT_INDEX);
1937 WREG32(PCIE_PORT_DATA, (v));
1938 (void)RREG32(PCIE_PORT_DATA);
1944 void r600_cp_stop(struct radeon_device *rdev)
1946 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1947 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1948 WREG32(SCRATCH_UMSK, 0);
1949 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1952 int r600_init_microcode(struct radeon_device *rdev)
1954 struct platform_device *pdev;
1955 const char *chip_name;
1956 const char *rlc_chip_name;
1957 size_t pfp_req_size, me_req_size, rlc_req_size;
1963 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1966 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1970 switch (rdev->family) {
1973 rlc_chip_name = "R600";
1976 chip_name = "RV610";
1977 rlc_chip_name = "R600";
1980 chip_name = "RV630";
1981 rlc_chip_name = "R600";
1984 chip_name = "RV620";
1985 rlc_chip_name = "R600";
1988 chip_name = "RV635";
1989 rlc_chip_name = "R600";
1992 chip_name = "RV670";
1993 rlc_chip_name = "R600";
1997 chip_name = "RS780";
1998 rlc_chip_name = "R600";
2001 chip_name = "RV770";
2002 rlc_chip_name = "R700";
2006 chip_name = "RV730";
2007 rlc_chip_name = "R700";
2010 chip_name = "RV710";
2011 rlc_chip_name = "R700";
2014 chip_name = "CEDAR";
2015 rlc_chip_name = "CEDAR";
2018 chip_name = "REDWOOD";
2019 rlc_chip_name = "REDWOOD";
2022 chip_name = "JUNIPER";
2023 rlc_chip_name = "JUNIPER";
2027 chip_name = "CYPRESS";
2028 rlc_chip_name = "CYPRESS";
2032 rlc_chip_name = "SUMO";
2036 rlc_chip_name = "SUMO";
2039 chip_name = "SUMO2";
2040 rlc_chip_name = "SUMO";
2045 if (rdev->family >= CHIP_CEDAR) {
2046 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2047 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2048 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2049 } else if (rdev->family >= CHIP_RV770) {
2050 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2051 me_req_size = R700_PM4_UCODE_SIZE * 4;
2052 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2054 pfp_req_size = PFP_UCODE_SIZE * 4;
2055 me_req_size = PM4_UCODE_SIZE * 12;
2056 rlc_req_size = RLC_UCODE_SIZE * 4;
2059 DRM_INFO("Loading %s Microcode\n", chip_name);
2061 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2062 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2065 if (rdev->pfp_fw->size != pfp_req_size) {
2067 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2068 rdev->pfp_fw->size, fw_name);
2073 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2074 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2077 if (rdev->me_fw->size != me_req_size) {
2079 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2080 rdev->me_fw->size, fw_name);
2084 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2085 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2088 if (rdev->rlc_fw->size != rlc_req_size) {
2090 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2091 rdev->rlc_fw->size, fw_name);
2096 platform_device_unregister(pdev);
2101 "r600_cp: Failed to load firmware \"%s\"\n",
2103 release_firmware(rdev->pfp_fw);
2104 rdev->pfp_fw = NULL;
2105 release_firmware(rdev->me_fw);
2107 release_firmware(rdev->rlc_fw);
2108 rdev->rlc_fw = NULL;
2113 static int r600_cp_load_microcode(struct radeon_device *rdev)
2115 const __be32 *fw_data;
2118 if (!rdev->me_fw || !rdev->pfp_fw)
2127 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2130 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2131 RREG32(GRBM_SOFT_RESET);
2133 WREG32(GRBM_SOFT_RESET, 0);
2135 WREG32(CP_ME_RAM_WADDR, 0);
2137 fw_data = (const __be32 *)rdev->me_fw->data;
2138 WREG32(CP_ME_RAM_WADDR, 0);
2139 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2140 WREG32(CP_ME_RAM_DATA,
2141 be32_to_cpup(fw_data++));
2143 fw_data = (const __be32 *)rdev->pfp_fw->data;
2144 WREG32(CP_PFP_UCODE_ADDR, 0);
2145 for (i = 0; i < PFP_UCODE_SIZE; i++)
2146 WREG32(CP_PFP_UCODE_DATA,
2147 be32_to_cpup(fw_data++));
2149 WREG32(CP_PFP_UCODE_ADDR, 0);
2150 WREG32(CP_ME_RAM_WADDR, 0);
2151 WREG32(CP_ME_RAM_RADDR, 0);
2155 int r600_cp_start(struct radeon_device *rdev)
2157 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2161 r = radeon_ring_lock(rdev, ring, 7);
2163 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2166 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2167 radeon_ring_write(ring, 0x1);
2168 if (rdev->family >= CHIP_RV770) {
2169 radeon_ring_write(ring, 0x0);
2170 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2172 radeon_ring_write(ring, 0x3);
2173 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2175 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2176 radeon_ring_write(ring, 0);
2177 radeon_ring_write(ring, 0);
2178 radeon_ring_unlock_commit(rdev, ring);
2181 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2185 int r600_cp_resume(struct radeon_device *rdev)
2187 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2193 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2194 RREG32(GRBM_SOFT_RESET);
2196 WREG32(GRBM_SOFT_RESET, 0);
2198 /* Set ring buffer size */
2199 rb_bufsz = drm_order(ring->ring_size / 8);
2200 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2202 tmp |= BUF_SWAP_32BIT;
2204 WREG32(CP_RB_CNTL, tmp);
2205 WREG32(CP_SEM_WAIT_TIMER, 0x0);
2207 /* Set the write pointer delay */
2208 WREG32(CP_RB_WPTR_DELAY, 0);
2210 /* Initialize the ring buffer's read and write pointers */
2211 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2212 WREG32(CP_RB_RPTR_WR, 0);
2214 WREG32(CP_RB_WPTR, ring->wptr);
2216 /* set the wb address whether it's enabled or not */
2217 WREG32(CP_RB_RPTR_ADDR,
2218 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2219 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2220 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2222 if (rdev->wb.enabled)
2223 WREG32(SCRATCH_UMSK, 0xff);
2225 tmp |= RB_NO_UPDATE;
2226 WREG32(SCRATCH_UMSK, 0);
2230 WREG32(CP_RB_CNTL, tmp);
2232 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2233 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2235 ring->rptr = RREG32(CP_RB_RPTR);
2237 r600_cp_start(rdev);
2239 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2241 ring->ready = false;
2247 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2252 /* Align ring size */
2253 rb_bufsz = drm_order(ring_size / 8);
2254 ring_size = (1 << (rb_bufsz + 1)) * 4;
2255 ring->ring_size = ring_size;
2256 ring->align_mask = 16 - 1;
2258 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2259 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2261 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2262 ring->rptr_save_reg = 0;
2267 void r600_cp_fini(struct radeon_device *rdev)
2269 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2271 radeon_ring_fini(rdev, ring);
2272 radeon_scratch_free(rdev, ring->rptr_save_reg);
2277 * Starting with R600, the GPU has an asynchronous
2278 * DMA engine. The programming model is very similar
2279 * to the 3D engine (ring buffer, IBs, etc.), but the
2280 * DMA controller has it's own packet format that is
2281 * different form the PM4 format used by the 3D engine.
2282 * It supports copying data, writing embedded data,
2283 * solid fills, and a number of other things. It also
2284 * has support for tiling/detiling of buffers.
2287 * r600_dma_stop - stop the async dma engine
2289 * @rdev: radeon_device pointer
2291 * Stop the async dma engine (r6xx-evergreen).
2293 void r600_dma_stop(struct radeon_device *rdev)
2295 u32 rb_cntl = RREG32(DMA_RB_CNTL);
2297 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2299 rb_cntl &= ~DMA_RB_ENABLE;
2300 WREG32(DMA_RB_CNTL, rb_cntl);
2302 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2306 * r600_dma_resume - setup and start the async dma engine
2308 * @rdev: radeon_device pointer
2310 * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2311 * Returns 0 for success, error for failure.
2313 int r600_dma_resume(struct radeon_device *rdev)
2315 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2316 u32 rb_cntl, dma_cntl, ib_cntl;
2321 if (rdev->family >= CHIP_RV770)
2322 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2324 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2325 RREG32(SRBM_SOFT_RESET);
2327 WREG32(SRBM_SOFT_RESET, 0);
2329 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2330 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2332 /* Set ring buffer size in dwords */
2333 rb_bufsz = drm_order(ring->ring_size / 4);
2334 rb_cntl = rb_bufsz << 1;
2336 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2338 WREG32(DMA_RB_CNTL, rb_cntl);
2340 /* Initialize the ring buffer's read and write pointers */
2341 WREG32(DMA_RB_RPTR, 0);
2342 WREG32(DMA_RB_WPTR, 0);
2344 /* set the wb address whether it's enabled or not */
2345 WREG32(DMA_RB_RPTR_ADDR_HI,
2346 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2347 WREG32(DMA_RB_RPTR_ADDR_LO,
2348 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2350 if (rdev->wb.enabled)
2351 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2353 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2355 /* enable DMA IBs */
2356 ib_cntl = DMA_IB_ENABLE;
2358 ib_cntl |= DMA_IB_SWAP_ENABLE;
2360 WREG32(DMA_IB_CNTL, ib_cntl);
2362 dma_cntl = RREG32(DMA_CNTL);
2363 dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2364 WREG32(DMA_CNTL, dma_cntl);
2366 if (rdev->family >= CHIP_RV770)
2367 WREG32(DMA_MODE, 1);
2370 WREG32(DMA_RB_WPTR, ring->wptr << 2);
2372 ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2374 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2378 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2380 ring->ready = false;
2384 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2390 * r600_dma_fini - tear down the async dma engine
2392 * @rdev: radeon_device pointer
2394 * Stop the async dma engine and free the ring (r6xx-evergreen).
2396 void r600_dma_fini(struct radeon_device *rdev)
2398 r600_dma_stop(rdev);
2399 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2403 * GPU scratch registers helpers function.
2405 void r600_scratch_init(struct radeon_device *rdev)
2409 rdev->scratch.num_reg = 7;
2410 rdev->scratch.reg_base = SCRATCH_REG0;
2411 for (i = 0; i < rdev->scratch.num_reg; i++) {
2412 rdev->scratch.free[i] = true;
2413 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2417 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2424 r = radeon_scratch_get(rdev, &scratch);
2426 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2429 WREG32(scratch, 0xCAFEDEAD);
2430 r = radeon_ring_lock(rdev, ring, 3);
2432 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2433 radeon_scratch_free(rdev, scratch);
2436 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2437 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2438 radeon_ring_write(ring, 0xDEADBEEF);
2439 radeon_ring_unlock_commit(rdev, ring);
2440 for (i = 0; i < rdev->usec_timeout; i++) {
2441 tmp = RREG32(scratch);
2442 if (tmp == 0xDEADBEEF)
2446 if (i < rdev->usec_timeout) {
2447 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2449 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2450 ring->idx, scratch, tmp);
2453 radeon_scratch_free(rdev, scratch);
2458 * r600_dma_ring_test - simple async dma engine test
2460 * @rdev: radeon_device pointer
2461 * @ring: radeon_ring structure holding ring information
2463 * Test the DMA engine by writing using it to write an
2464 * value to memory. (r6xx-SI).
2465 * Returns 0 for success, error for failure.
2467 int r600_dma_ring_test(struct radeon_device *rdev,
2468 struct radeon_ring *ring)
2472 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2476 DRM_ERROR("invalid vram scratch pointer\n");
2483 r = radeon_ring_lock(rdev, ring, 4);
2485 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2488 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2489 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2490 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2491 radeon_ring_write(ring, 0xDEADBEEF);
2492 radeon_ring_unlock_commit(rdev, ring);
2494 for (i = 0; i < rdev->usec_timeout; i++) {
2496 if (tmp == 0xDEADBEEF)
2501 if (i < rdev->usec_timeout) {
2502 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2504 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2512 * CP fences/semaphores
2515 void r600_fence_ring_emit(struct radeon_device *rdev,
2516 struct radeon_fence *fence)
2518 struct radeon_ring *ring = &rdev->ring[fence->ring];
2520 if (rdev->wb.use_event) {
2521 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2522 /* flush read cache over gart */
2523 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2524 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2525 PACKET3_VC_ACTION_ENA |
2526 PACKET3_SH_ACTION_ENA);
2527 radeon_ring_write(ring, 0xFFFFFFFF);
2528 radeon_ring_write(ring, 0);
2529 radeon_ring_write(ring, 10); /* poll interval */
2530 /* EVENT_WRITE_EOP - flush caches, send int */
2531 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2532 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2533 radeon_ring_write(ring, addr & 0xffffffff);
2534 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2535 radeon_ring_write(ring, fence->seq);
2536 radeon_ring_write(ring, 0);
2538 /* flush read cache over gart */
2539 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2540 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2541 PACKET3_VC_ACTION_ENA |
2542 PACKET3_SH_ACTION_ENA);
2543 radeon_ring_write(ring, 0xFFFFFFFF);
2544 radeon_ring_write(ring, 0);
2545 radeon_ring_write(ring, 10); /* poll interval */
2546 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2547 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2548 /* wait for 3D idle clean */
2549 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2550 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2551 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2552 /* Emit fence sequence & fire IRQ */
2553 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2554 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2555 radeon_ring_write(ring, fence->seq);
2556 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2557 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2558 radeon_ring_write(ring, RB_INT_STAT);
2562 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2563 struct radeon_ring *ring,
2564 struct radeon_semaphore *semaphore,
2567 uint64_t addr = semaphore->gpu_addr;
2568 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2570 if (rdev->family < CHIP_CAYMAN)
2571 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2573 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2574 radeon_ring_write(ring, addr & 0xffffffff);
2575 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2579 * DMA fences/semaphores
2583 * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2585 * @rdev: radeon_device pointer
2586 * @fence: radeon fence object
2588 * Add a DMA fence packet to the ring to write
2589 * the fence seq number and DMA trap packet to generate
2590 * an interrupt if needed (r6xx-r7xx).
2592 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
2593 struct radeon_fence *fence)
2595 struct radeon_ring *ring = &rdev->ring[fence->ring];
2596 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2598 /* write the fence */
2599 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2600 radeon_ring_write(ring, addr & 0xfffffffc);
2601 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
2602 radeon_ring_write(ring, lower_32_bits(fence->seq));
2603 /* generate an interrupt */
2604 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2608 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2610 * @rdev: radeon_device pointer
2611 * @ring: radeon_ring structure holding ring information
2612 * @semaphore: radeon semaphore object
2613 * @emit_wait: wait or signal semaphore
2615 * Add a DMA semaphore packet to the ring wait on or signal
2616 * other rings (r6xx-SI).
2618 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2619 struct radeon_ring *ring,
2620 struct radeon_semaphore *semaphore,
2623 u64 addr = semaphore->gpu_addr;
2624 u32 s = emit_wait ? 0 : 1;
2626 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2627 radeon_ring_write(ring, addr & 0xfffffffc);
2628 radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2631 int r600_copy_blit(struct radeon_device *rdev,
2632 uint64_t src_offset,
2633 uint64_t dst_offset,
2634 unsigned num_gpu_pages,
2635 struct radeon_fence **fence)
2637 struct radeon_semaphore *sem = NULL;
2638 struct radeon_sa_bo *vb = NULL;
2641 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
2645 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2646 r600_blit_done_copy(rdev, fence, vb, sem);
2651 * r600_copy_dma - copy pages using the DMA engine
2653 * @rdev: radeon_device pointer
2654 * @src_offset: src GPU address
2655 * @dst_offset: dst GPU address
2656 * @num_gpu_pages: number of GPU pages to xfer
2657 * @fence: radeon fence object
2659 * Copy GPU paging using the DMA engine (r6xx).
2660 * Used by the radeon ttm implementation to move pages if
2661 * registered as the asic copy callback.
2663 int r600_copy_dma(struct radeon_device *rdev,
2664 uint64_t src_offset, uint64_t dst_offset,
2665 unsigned num_gpu_pages,
2666 struct radeon_fence **fence)
2668 struct radeon_semaphore *sem = NULL;
2669 int ring_index = rdev->asic->copy.dma_ring_index;
2670 struct radeon_ring *ring = &rdev->ring[ring_index];
2671 u32 size_in_dw, cur_size_in_dw;
2675 r = radeon_semaphore_create(rdev, &sem);
2677 DRM_ERROR("radeon: moving bo (%d).\n", r);
2681 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
2682 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
2683 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
2685 DRM_ERROR("radeon: moving bo (%d).\n", r);
2686 radeon_semaphore_free(rdev, &sem, NULL);
2690 if (radeon_fence_need_sync(*fence, ring->idx)) {
2691 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2693 radeon_fence_note_sync(*fence, ring->idx);
2695 radeon_semaphore_free(rdev, &sem, NULL);
2698 for (i = 0; i < num_loops; i++) {
2699 cur_size_in_dw = size_in_dw;
2700 if (cur_size_in_dw > 0xFFFE)
2701 cur_size_in_dw = 0xFFFE;
2702 size_in_dw -= cur_size_in_dw;
2703 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2704 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2705 radeon_ring_write(ring, src_offset & 0xfffffffc);
2706 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
2707 (upper_32_bits(src_offset) & 0xff)));
2708 src_offset += cur_size_in_dw * 4;
2709 dst_offset += cur_size_in_dw * 4;
2712 r = radeon_fence_emit(rdev, fence, ring->idx);
2714 radeon_ring_unlock_undo(rdev, ring);
2718 radeon_ring_unlock_commit(rdev, ring);
2719 radeon_semaphore_free(rdev, &sem, *fence);
2724 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2725 uint32_t tiling_flags, uint32_t pitch,
2726 uint32_t offset, uint32_t obj_size)
2728 /* FIXME: implement */
2732 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2734 /* FIXME: implement */
2737 static int r600_startup(struct radeon_device *rdev)
2739 struct radeon_ring *ring;
2742 /* enable pcie gen2 link */
2743 r600_pcie_gen2_enable(rdev);
2745 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2746 r = r600_init_microcode(rdev);
2748 DRM_ERROR("Failed to load firmware!\n");
2753 r = r600_vram_scratch_init(rdev);
2757 r600_mc_program(rdev);
2758 if (rdev->flags & RADEON_IS_AGP) {
2759 r600_agp_enable(rdev);
2761 r = r600_pcie_gart_enable(rdev);
2765 r600_gpu_init(rdev);
2766 r = r600_blit_init(rdev);
2768 r600_blit_fini(rdev);
2769 rdev->asic->copy.copy = NULL;
2770 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2773 /* allocate wb buffer */
2774 r = radeon_wb_init(rdev);
2778 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2780 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2784 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2786 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2791 r = r600_irq_init(rdev);
2793 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2794 radeon_irq_kms_fini(rdev);
2799 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2800 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2801 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2802 0, 0xfffff, RADEON_CP_PACKET2);
2806 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2807 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2808 DMA_RB_RPTR, DMA_RB_WPTR,
2809 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2813 r = r600_cp_load_microcode(rdev);
2816 r = r600_cp_resume(rdev);
2820 r = r600_dma_resume(rdev);
2824 r = radeon_ib_pool_init(rdev);
2826 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2830 r = r600_audio_init(rdev);
2832 DRM_ERROR("radeon: audio init failed\n");
2839 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2843 temp = RREG32(CONFIG_CNTL);
2844 if (state == false) {
2850 WREG32(CONFIG_CNTL, temp);
2853 int r600_resume(struct radeon_device *rdev)
2857 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2858 * posting will perform necessary task to bring back GPU into good
2862 atom_asic_init(rdev->mode_info.atom_context);
2864 rdev->accel_working = true;
2865 r = r600_startup(rdev);
2867 DRM_ERROR("r600 startup failed on resume\n");
2868 rdev->accel_working = false;
2875 int r600_suspend(struct radeon_device *rdev)
2877 r600_audio_fini(rdev);
2879 r600_dma_stop(rdev);
2880 r600_irq_suspend(rdev);
2881 radeon_wb_disable(rdev);
2882 r600_pcie_gart_disable(rdev);
2887 /* Plan is to move initialization in that function and use
2888 * helper function so that radeon_device_init pretty much
2889 * do nothing more than calling asic specific function. This
2890 * should also allow to remove a bunch of callback function
2893 int r600_init(struct radeon_device *rdev)
2897 if (r600_debugfs_mc_info_init(rdev)) {
2898 DRM_ERROR("Failed to register debugfs file for mc !\n");
2901 if (!radeon_get_bios(rdev)) {
2902 if (ASIC_IS_AVIVO(rdev))
2905 /* Must be an ATOMBIOS */
2906 if (!rdev->is_atom_bios) {
2907 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2910 r = radeon_atombios_init(rdev);
2913 /* Post card if necessary */
2914 if (!radeon_card_posted(rdev)) {
2916 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2919 DRM_INFO("GPU not posted. posting now...\n");
2920 atom_asic_init(rdev->mode_info.atom_context);
2922 /* Initialize scratch registers */
2923 r600_scratch_init(rdev);
2924 /* Initialize surface registers */
2925 radeon_surface_init(rdev);
2926 /* Initialize clocks */
2927 radeon_get_clock_info(rdev->ddev);
2929 r = radeon_fence_driver_init(rdev);
2932 if (rdev->flags & RADEON_IS_AGP) {
2933 r = radeon_agp_init(rdev);
2935 radeon_agp_disable(rdev);
2937 r = r600_mc_init(rdev);
2940 /* Memory manager */
2941 r = radeon_bo_init(rdev);
2945 r = radeon_irq_kms_init(rdev);
2949 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2950 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2952 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2953 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2955 rdev->ih.ring_obj = NULL;
2956 r600_ih_ring_init(rdev, 64 * 1024);
2958 r = r600_pcie_gart_init(rdev);
2962 rdev->accel_working = true;
2963 r = r600_startup(rdev);
2965 dev_err(rdev->dev, "disabling GPU acceleration\n");
2967 r600_dma_fini(rdev);
2968 r600_irq_fini(rdev);
2969 radeon_wb_fini(rdev);
2970 radeon_ib_pool_fini(rdev);
2971 radeon_irq_kms_fini(rdev);
2972 r600_pcie_gart_fini(rdev);
2973 rdev->accel_working = false;
2979 void r600_fini(struct radeon_device *rdev)
2981 r600_audio_fini(rdev);
2982 r600_blit_fini(rdev);
2984 r600_dma_fini(rdev);
2985 r600_irq_fini(rdev);
2986 radeon_wb_fini(rdev);
2987 radeon_ib_pool_fini(rdev);
2988 radeon_irq_kms_fini(rdev);
2989 r600_pcie_gart_fini(rdev);
2990 r600_vram_scratch_fini(rdev);
2991 radeon_agp_fini(rdev);
2992 radeon_gem_fini(rdev);
2993 radeon_fence_driver_fini(rdev);
2994 radeon_bo_fini(rdev);
2995 radeon_atombios_fini(rdev);
3004 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3006 struct radeon_ring *ring = &rdev->ring[ib->ring];
3009 if (ring->rptr_save_reg) {
3010 next_rptr = ring->wptr + 3 + 4;
3011 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3012 radeon_ring_write(ring, ((ring->rptr_save_reg -
3013 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3014 radeon_ring_write(ring, next_rptr);
3015 } else if (rdev->wb.enabled) {
3016 next_rptr = ring->wptr + 5 + 4;
3017 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3018 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3019 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3020 radeon_ring_write(ring, next_rptr);
3021 radeon_ring_write(ring, 0);
3024 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3025 radeon_ring_write(ring,
3029 (ib->gpu_addr & 0xFFFFFFFC));
3030 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3031 radeon_ring_write(ring, ib->length_dw);
3034 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3036 struct radeon_ib ib;
3042 r = radeon_scratch_get(rdev, &scratch);
3044 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3047 WREG32(scratch, 0xCAFEDEAD);
3048 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3050 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3053 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3054 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3055 ib.ptr[2] = 0xDEADBEEF;
3057 r = radeon_ib_schedule(rdev, &ib, NULL);
3059 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3062 r = radeon_fence_wait(ib.fence, false);
3064 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3067 for (i = 0; i < rdev->usec_timeout; i++) {
3068 tmp = RREG32(scratch);
3069 if (tmp == 0xDEADBEEF)
3073 if (i < rdev->usec_timeout) {
3074 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3076 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3081 radeon_ib_free(rdev, &ib);
3083 radeon_scratch_free(rdev, scratch);
3088 * r600_dma_ib_test - test an IB on the DMA engine
3090 * @rdev: radeon_device pointer
3091 * @ring: radeon_ring structure holding ring information
3093 * Test a simple IB in the DMA ring (r6xx-SI).
3094 * Returns 0 on success, error on failure.
3096 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3098 struct radeon_ib ib;
3101 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3105 DRM_ERROR("invalid vram scratch pointer\n");
3112 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3114 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3118 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3119 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3120 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3121 ib.ptr[3] = 0xDEADBEEF;
3124 r = radeon_ib_schedule(rdev, &ib, NULL);
3126 radeon_ib_free(rdev, &ib);
3127 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3130 r = radeon_fence_wait(ib.fence, false);
3132 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3135 for (i = 0; i < rdev->usec_timeout; i++) {
3137 if (tmp == 0xDEADBEEF)
3141 if (i < rdev->usec_timeout) {
3142 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3144 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3147 radeon_ib_free(rdev, &ib);
3152 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3154 * @rdev: radeon_device pointer
3155 * @ib: IB object to schedule
3157 * Schedule an IB in the DMA ring (r6xx-r7xx).
3159 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3161 struct radeon_ring *ring = &rdev->ring[ib->ring];
3163 if (rdev->wb.enabled) {
3164 u32 next_rptr = ring->wptr + 4;
3165 while ((next_rptr & 7) != 5)
3168 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3169 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3170 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3171 radeon_ring_write(ring, next_rptr);
3174 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3175 * Pad as necessary with NOPs.
3177 while ((ring->wptr & 7) != 5)
3178 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3179 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3180 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3181 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3188 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3189 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3190 * writing to the ring and the GPU consuming, the GPU writes to the ring
3191 * and host consumes. As the host irq handler processes interrupts, it
3192 * increments the rptr. When the rptr catches up with the wptr, all the
3193 * current interrupts have been processed.
3196 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3200 /* Align ring size */
3201 rb_bufsz = drm_order(ring_size / 4);
3202 ring_size = (1 << rb_bufsz) * 4;
3203 rdev->ih.ring_size = ring_size;
3204 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3208 int r600_ih_ring_alloc(struct radeon_device *rdev)
3212 /* Allocate ring buffer */
3213 if (rdev->ih.ring_obj == NULL) {
3214 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3216 RADEON_GEM_DOMAIN_GTT,
3217 NULL, &rdev->ih.ring_obj);
3219 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3222 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3223 if (unlikely(r != 0))
3225 r = radeon_bo_pin(rdev->ih.ring_obj,
3226 RADEON_GEM_DOMAIN_GTT,
3227 &rdev->ih.gpu_addr);
3229 radeon_bo_unreserve(rdev->ih.ring_obj);
3230 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3233 r = radeon_bo_kmap(rdev->ih.ring_obj,
3234 (void **)&rdev->ih.ring);
3235 radeon_bo_unreserve(rdev->ih.ring_obj);
3237 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3244 void r600_ih_ring_fini(struct radeon_device *rdev)
3247 if (rdev->ih.ring_obj) {
3248 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3249 if (likely(r == 0)) {
3250 radeon_bo_kunmap(rdev->ih.ring_obj);
3251 radeon_bo_unpin(rdev->ih.ring_obj);
3252 radeon_bo_unreserve(rdev->ih.ring_obj);
3254 radeon_bo_unref(&rdev->ih.ring_obj);
3255 rdev->ih.ring = NULL;
3256 rdev->ih.ring_obj = NULL;
3260 void r600_rlc_stop(struct radeon_device *rdev)
3263 if ((rdev->family >= CHIP_RV770) &&
3264 (rdev->family <= CHIP_RV740)) {
3265 /* r7xx asics need to soft reset RLC before halting */
3266 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3267 RREG32(SRBM_SOFT_RESET);
3269 WREG32(SRBM_SOFT_RESET, 0);
3270 RREG32(SRBM_SOFT_RESET);
3273 WREG32(RLC_CNTL, 0);
3276 static void r600_rlc_start(struct radeon_device *rdev)
3278 WREG32(RLC_CNTL, RLC_ENABLE);
3281 static int r600_rlc_init(struct radeon_device *rdev)
3284 const __be32 *fw_data;
3289 r600_rlc_stop(rdev);
3291 WREG32(RLC_HB_CNTL, 0);
3293 if (rdev->family == CHIP_ARUBA) {
3294 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3295 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3297 if (rdev->family <= CHIP_CAYMAN) {
3298 WREG32(RLC_HB_BASE, 0);
3299 WREG32(RLC_HB_RPTR, 0);
3300 WREG32(RLC_HB_WPTR, 0);
3302 if (rdev->family <= CHIP_CAICOS) {
3303 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3304 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3306 WREG32(RLC_MC_CNTL, 0);
3307 WREG32(RLC_UCODE_CNTL, 0);
3309 fw_data = (const __be32 *)rdev->rlc_fw->data;
3310 if (rdev->family >= CHIP_ARUBA) {
3311 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3312 WREG32(RLC_UCODE_ADDR, i);
3313 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3315 } else if (rdev->family >= CHIP_CAYMAN) {
3316 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3317 WREG32(RLC_UCODE_ADDR, i);
3318 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3320 } else if (rdev->family >= CHIP_CEDAR) {
3321 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3322 WREG32(RLC_UCODE_ADDR, i);
3323 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3325 } else if (rdev->family >= CHIP_RV770) {
3326 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3327 WREG32(RLC_UCODE_ADDR, i);
3328 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3331 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3332 WREG32(RLC_UCODE_ADDR, i);
3333 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3336 WREG32(RLC_UCODE_ADDR, 0);
3338 r600_rlc_start(rdev);
3343 static void r600_enable_interrupts(struct radeon_device *rdev)
3345 u32 ih_cntl = RREG32(IH_CNTL);
3346 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3348 ih_cntl |= ENABLE_INTR;
3349 ih_rb_cntl |= IH_RB_ENABLE;
3350 WREG32(IH_CNTL, ih_cntl);
3351 WREG32(IH_RB_CNTL, ih_rb_cntl);
3352 rdev->ih.enabled = true;
3355 void r600_disable_interrupts(struct radeon_device *rdev)
3357 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3358 u32 ih_cntl = RREG32(IH_CNTL);
3360 ih_rb_cntl &= ~IH_RB_ENABLE;
3361 ih_cntl &= ~ENABLE_INTR;
3362 WREG32(IH_RB_CNTL, ih_rb_cntl);
3363 WREG32(IH_CNTL, ih_cntl);
3364 /* set rptr, wptr to 0 */
3365 WREG32(IH_RB_RPTR, 0);
3366 WREG32(IH_RB_WPTR, 0);
3367 rdev->ih.enabled = false;
3371 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3375 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3376 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3377 WREG32(DMA_CNTL, tmp);
3378 WREG32(GRBM_INT_CNTL, 0);
3379 WREG32(DxMODE_INT_MASK, 0);
3380 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3381 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3382 if (ASIC_IS_DCE3(rdev)) {
3383 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3384 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3385 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3386 WREG32(DC_HPD1_INT_CONTROL, tmp);
3387 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3388 WREG32(DC_HPD2_INT_CONTROL, tmp);
3389 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3390 WREG32(DC_HPD3_INT_CONTROL, tmp);
3391 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3392 WREG32(DC_HPD4_INT_CONTROL, tmp);
3393 if (ASIC_IS_DCE32(rdev)) {
3394 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3395 WREG32(DC_HPD5_INT_CONTROL, tmp);
3396 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3397 WREG32(DC_HPD6_INT_CONTROL, tmp);
3398 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3399 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3400 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3401 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3403 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3404 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3405 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3406 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3409 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3410 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3411 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3412 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3413 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3414 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3415 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3416 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3417 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3418 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3419 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3420 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3424 int r600_irq_init(struct radeon_device *rdev)
3428 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3431 ret = r600_ih_ring_alloc(rdev);
3436 r600_disable_interrupts(rdev);
3439 ret = r600_rlc_init(rdev);
3441 r600_ih_ring_fini(rdev);
3445 /* setup interrupt control */
3446 /* set dummy read address to ring address */
3447 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3448 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3449 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3450 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3452 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3453 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3454 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3455 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3457 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3458 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3460 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3461 IH_WPTR_OVERFLOW_CLEAR |
3464 if (rdev->wb.enabled)
3465 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3467 /* set the writeback address whether it's enabled or not */
3468 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3469 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3471 WREG32(IH_RB_CNTL, ih_rb_cntl);
3473 /* set rptr, wptr to 0 */
3474 WREG32(IH_RB_RPTR, 0);
3475 WREG32(IH_RB_WPTR, 0);
3477 /* Default settings for IH_CNTL (disabled at first) */
3478 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3479 /* RPTR_REARM only works if msi's are enabled */
3480 if (rdev->msi_enabled)
3481 ih_cntl |= RPTR_REARM;
3482 WREG32(IH_CNTL, ih_cntl);
3484 /* force the active interrupt state to all disabled */
3485 if (rdev->family >= CHIP_CEDAR)
3486 evergreen_disable_interrupt_state(rdev);
3488 r600_disable_interrupt_state(rdev);
3490 /* at this point everything should be setup correctly to enable master */
3491 pci_set_master(rdev->pdev);
3494 r600_enable_interrupts(rdev);
3499 void r600_irq_suspend(struct radeon_device *rdev)
3501 r600_irq_disable(rdev);
3502 r600_rlc_stop(rdev);
3505 void r600_irq_fini(struct radeon_device *rdev)
3507 r600_irq_suspend(rdev);
3508 r600_ih_ring_fini(rdev);
3511 int r600_irq_set(struct radeon_device *rdev)
3513 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3515 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3516 u32 grbm_int_cntl = 0;
3518 u32 d1grph = 0, d2grph = 0;
3521 if (!rdev->irq.installed) {
3522 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3525 /* don't enable anything if the ih is disabled */
3526 if (!rdev->ih.enabled) {
3527 r600_disable_interrupts(rdev);
3528 /* force the active interrupt state to all disabled */
3529 r600_disable_interrupt_state(rdev);
3533 if (ASIC_IS_DCE3(rdev)) {
3534 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3535 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3536 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3537 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3538 if (ASIC_IS_DCE32(rdev)) {
3539 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3540 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3541 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3542 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3544 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3545 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3548 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3549 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3550 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3551 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3552 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3554 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3556 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3557 DRM_DEBUG("r600_irq_set: sw int\n");
3558 cp_int_cntl |= RB_INT_ENABLE;
3559 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3562 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3563 DRM_DEBUG("r600_irq_set: sw int dma\n");
3564 dma_cntl |= TRAP_ENABLE;
3567 if (rdev->irq.crtc_vblank_int[0] ||
3568 atomic_read(&rdev->irq.pflip[0])) {
3569 DRM_DEBUG("r600_irq_set: vblank 0\n");
3570 mode_int |= D1MODE_VBLANK_INT_MASK;
3572 if (rdev->irq.crtc_vblank_int[1] ||
3573 atomic_read(&rdev->irq.pflip[1])) {
3574 DRM_DEBUG("r600_irq_set: vblank 1\n");
3575 mode_int |= D2MODE_VBLANK_INT_MASK;
3577 if (rdev->irq.hpd[0]) {
3578 DRM_DEBUG("r600_irq_set: hpd 1\n");
3579 hpd1 |= DC_HPDx_INT_EN;
3581 if (rdev->irq.hpd[1]) {
3582 DRM_DEBUG("r600_irq_set: hpd 2\n");
3583 hpd2 |= DC_HPDx_INT_EN;
3585 if (rdev->irq.hpd[2]) {
3586 DRM_DEBUG("r600_irq_set: hpd 3\n");
3587 hpd3 |= DC_HPDx_INT_EN;
3589 if (rdev->irq.hpd[3]) {
3590 DRM_DEBUG("r600_irq_set: hpd 4\n");
3591 hpd4 |= DC_HPDx_INT_EN;
3593 if (rdev->irq.hpd[4]) {
3594 DRM_DEBUG("r600_irq_set: hpd 5\n");
3595 hpd5 |= DC_HPDx_INT_EN;
3597 if (rdev->irq.hpd[5]) {
3598 DRM_DEBUG("r600_irq_set: hpd 6\n");
3599 hpd6 |= DC_HPDx_INT_EN;
3601 if (rdev->irq.afmt[0]) {
3602 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3603 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3605 if (rdev->irq.afmt[1]) {
3606 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3607 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3610 WREG32(CP_INT_CNTL, cp_int_cntl);
3611 WREG32(DMA_CNTL, dma_cntl);
3612 WREG32(DxMODE_INT_MASK, mode_int);
3613 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3614 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3615 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3616 if (ASIC_IS_DCE3(rdev)) {
3617 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3618 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3619 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3620 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3621 if (ASIC_IS_DCE32(rdev)) {
3622 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3623 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3624 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3625 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3627 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3628 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3631 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3632 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3633 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3634 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3635 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3641 static void r600_irq_ack(struct radeon_device *rdev)
3645 if (ASIC_IS_DCE3(rdev)) {
3646 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3647 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3648 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3649 if (ASIC_IS_DCE32(rdev)) {
3650 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3651 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3653 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3654 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3657 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3658 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3659 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3660 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3661 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3663 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3664 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3666 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3667 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3668 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3669 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3670 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3671 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3672 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3673 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3674 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3675 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3676 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3677 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3678 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3679 if (ASIC_IS_DCE3(rdev)) {
3680 tmp = RREG32(DC_HPD1_INT_CONTROL);
3681 tmp |= DC_HPDx_INT_ACK;
3682 WREG32(DC_HPD1_INT_CONTROL, tmp);
3684 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3685 tmp |= DC_HPDx_INT_ACK;
3686 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3689 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3690 if (ASIC_IS_DCE3(rdev)) {
3691 tmp = RREG32(DC_HPD2_INT_CONTROL);
3692 tmp |= DC_HPDx_INT_ACK;
3693 WREG32(DC_HPD2_INT_CONTROL, tmp);
3695 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3696 tmp |= DC_HPDx_INT_ACK;
3697 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3700 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3701 if (ASIC_IS_DCE3(rdev)) {
3702 tmp = RREG32(DC_HPD3_INT_CONTROL);
3703 tmp |= DC_HPDx_INT_ACK;
3704 WREG32(DC_HPD3_INT_CONTROL, tmp);
3706 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3707 tmp |= DC_HPDx_INT_ACK;
3708 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3711 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3712 tmp = RREG32(DC_HPD4_INT_CONTROL);
3713 tmp |= DC_HPDx_INT_ACK;
3714 WREG32(DC_HPD4_INT_CONTROL, tmp);
3716 if (ASIC_IS_DCE32(rdev)) {
3717 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3718 tmp = RREG32(DC_HPD5_INT_CONTROL);
3719 tmp |= DC_HPDx_INT_ACK;
3720 WREG32(DC_HPD5_INT_CONTROL, tmp);
3722 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3723 tmp = RREG32(DC_HPD5_INT_CONTROL);
3724 tmp |= DC_HPDx_INT_ACK;
3725 WREG32(DC_HPD6_INT_CONTROL, tmp);
3727 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3728 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3729 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3730 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3732 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3733 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3734 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3735 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3738 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3739 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3740 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3741 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3743 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3744 if (ASIC_IS_DCE3(rdev)) {
3745 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3746 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3747 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3749 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3750 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3751 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3757 void r600_irq_disable(struct radeon_device *rdev)
3759 r600_disable_interrupts(rdev);
3760 /* Wait and acknowledge irq */
3763 r600_disable_interrupt_state(rdev);
3766 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3770 if (rdev->wb.enabled)
3771 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3773 wptr = RREG32(IH_RB_WPTR);
3775 if (wptr & RB_OVERFLOW) {
3776 /* When a ring buffer overflow happen start parsing interrupt
3777 * from the last not overwritten vector (wptr + 16). Hopefully
3778 * this should allow us to catchup.
3780 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3781 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3782 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3783 tmp = RREG32(IH_RB_CNTL);
3784 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3785 WREG32(IH_RB_CNTL, tmp);
3787 return (wptr & rdev->ih.ptr_mask);
3791 * Each IV ring entry is 128 bits:
3792 * [7:0] - interrupt source id
3794 * [59:32] - interrupt source data
3795 * [127:60] - reserved
3797 * The basic interrupt vector entries
3798 * are decoded as follows:
3799 * src_id src_data description
3804 * 19 0 FP Hot plug detection A
3805 * 19 1 FP Hot plug detection B
3806 * 19 2 DAC A auto-detection
3807 * 19 3 DAC B auto-detection
3813 * 181 - EOP Interrupt
3816 * Note, these are based on r600 and may need to be
3817 * adjusted or added to on newer asics
3820 int r600_irq_process(struct radeon_device *rdev)
3824 u32 src_id, src_data;
3826 bool queue_hotplug = false;
3827 bool queue_hdmi = false;
3829 if (!rdev->ih.enabled || rdev->shutdown)
3832 /* No MSIs, need a dummy read to flush PCI DMAs */
3833 if (!rdev->msi_enabled)
3836 wptr = r600_get_ih_wptr(rdev);
3839 /* is somebody else already processing irqs? */
3840 if (atomic_xchg(&rdev->ih.lock, 1))
3843 rptr = rdev->ih.rptr;
3844 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3846 /* Order reading of wptr vs. reading of IH ring data */
3849 /* display interrupts */
3852 while (rptr != wptr) {
3853 /* wptr/rptr are in bytes! */
3854 ring_index = rptr / 4;
3855 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3856 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3859 case 1: /* D1 vblank/vline */
3861 case 0: /* D1 vblank */
3862 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3863 if (rdev->irq.crtc_vblank_int[0]) {
3864 drm_handle_vblank(rdev->ddev, 0);
3865 rdev->pm.vblank_sync = true;
3866 wake_up(&rdev->irq.vblank_queue);
3868 if (atomic_read(&rdev->irq.pflip[0]))
3869 radeon_crtc_handle_flip(rdev, 0);
3870 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3871 DRM_DEBUG("IH: D1 vblank\n");
3874 case 1: /* D1 vline */
3875 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3876 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3877 DRM_DEBUG("IH: D1 vline\n");
3881 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3885 case 5: /* D2 vblank/vline */
3887 case 0: /* D2 vblank */
3888 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3889 if (rdev->irq.crtc_vblank_int[1]) {
3890 drm_handle_vblank(rdev->ddev, 1);
3891 rdev->pm.vblank_sync = true;
3892 wake_up(&rdev->irq.vblank_queue);
3894 if (atomic_read(&rdev->irq.pflip[1]))
3895 radeon_crtc_handle_flip(rdev, 1);
3896 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3897 DRM_DEBUG("IH: D2 vblank\n");
3900 case 1: /* D1 vline */
3901 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3902 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3903 DRM_DEBUG("IH: D2 vline\n");
3907 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3911 case 19: /* HPD/DAC hotplug */
3914 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3915 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3916 queue_hotplug = true;
3917 DRM_DEBUG("IH: HPD1\n");
3921 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3922 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3923 queue_hotplug = true;
3924 DRM_DEBUG("IH: HPD2\n");
3928 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3929 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3930 queue_hotplug = true;
3931 DRM_DEBUG("IH: HPD3\n");
3935 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3936 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3937 queue_hotplug = true;
3938 DRM_DEBUG("IH: HPD4\n");
3942 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3943 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3944 queue_hotplug = true;
3945 DRM_DEBUG("IH: HPD5\n");
3949 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3950 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3951 queue_hotplug = true;
3952 DRM_DEBUG("IH: HPD6\n");
3956 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3963 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3964 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3966 DRM_DEBUG("IH: HDMI0\n");
3970 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3971 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3973 DRM_DEBUG("IH: HDMI1\n");
3977 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3981 case 176: /* CP_INT in ring buffer */
3982 case 177: /* CP_INT in IB1 */
3983 case 178: /* CP_INT in IB2 */
3984 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3985 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3987 case 181: /* CP EOP event */
3988 DRM_DEBUG("IH: CP EOP\n");
3989 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3991 case 224: /* DMA trap event */
3992 DRM_DEBUG("IH: DMA trap\n");
3993 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3995 case 233: /* GUI IDLE */
3996 DRM_DEBUG("IH: GUI idle\n");
3999 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4003 /* wptr/rptr are in bytes! */
4005 rptr &= rdev->ih.ptr_mask;
4008 schedule_work(&rdev->hotplug_work);
4010 schedule_work(&rdev->audio_work);
4011 rdev->ih.rptr = rptr;
4012 WREG32(IH_RB_RPTR, rdev->ih.rptr);
4013 atomic_set(&rdev->ih.lock, 0);
4015 /* make sure wptr hasn't changed while processing */
4016 wptr = r600_get_ih_wptr(rdev);
4026 #if defined(CONFIG_DEBUG_FS)
4028 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4030 struct drm_info_node *node = (struct drm_info_node *) m->private;
4031 struct drm_device *dev = node->minor->dev;
4032 struct radeon_device *rdev = dev->dev_private;
4034 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4035 DREG32_SYS(m, rdev, VM_L2_STATUS);
4039 static struct drm_info_list r600_mc_info_list[] = {
4040 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4044 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4046 #if defined(CONFIG_DEBUG_FS)
4047 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4054 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4055 * rdev: radeon device structure
4056 * bo: buffer object struct which userspace is waiting for idle
4058 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4059 * through ring buffer, this leads to corruption in rendering, see
4060 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4061 * directly perform HDP flush by writing register through MMIO.
4063 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4065 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
4066 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4067 * This seems to cause problems on some AGP cards. Just use the old
4070 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4071 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4072 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4075 WREG32(HDP_DEBUG1, 0);
4076 tmp = readl((void __iomem *)ptr);
4078 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4081 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4083 u32 link_width_cntl, mask, target_reg;
4085 if (rdev->flags & RADEON_IS_IGP)
4088 if (!(rdev->flags & RADEON_IS_PCIE))
4091 /* x2 cards have a special sequence */
4092 if (ASIC_IS_X2(rdev))
4095 /* FIXME wait for idle */
4099 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4102 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4105 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4108 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4111 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4114 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4118 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4122 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4124 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4125 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4128 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4131 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4132 RADEON_PCIE_LC_RECONFIG_NOW |
4133 R600_PCIE_LC_RENEGOTIATE_EN |
4134 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4135 link_width_cntl |= mask;
4137 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4139 /* some northbridges can renegotiate the link rather than requiring
4140 * a complete re-config.
4141 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4143 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4144 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4146 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4148 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4149 RADEON_PCIE_LC_RECONFIG_NOW));
4151 if (rdev->family >= CHIP_RV770)
4152 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4154 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4156 /* wait for lane set to complete */
4157 link_width_cntl = RREG32(target_reg);
4158 while (link_width_cntl == 0xffffffff)
4159 link_width_cntl = RREG32(target_reg);
4163 int r600_get_pcie_lanes(struct radeon_device *rdev)
4165 u32 link_width_cntl;
4167 if (rdev->flags & RADEON_IS_IGP)
4170 if (!(rdev->flags & RADEON_IS_PCIE))
4173 /* x2 cards have a special sequence */
4174 if (ASIC_IS_X2(rdev))
4177 /* FIXME wait for idle */
4179 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4181 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4182 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4184 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4186 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4188 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4190 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4192 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4198 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4200 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4205 if (radeon_pcie_gen2 == 0)
4208 if (rdev->flags & RADEON_IS_IGP)
4211 if (!(rdev->flags & RADEON_IS_PCIE))
4214 /* x2 cards have a special sequence */
4215 if (ASIC_IS_X2(rdev))
4218 /* only RV6xx+ chips are supported */
4219 if (rdev->family <= CHIP_R600)
4222 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4226 if (!(mask & DRM_PCIE_SPEED_50))
4229 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4230 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4231 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4235 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4237 /* 55 nm r6xx asics */
4238 if ((rdev->family == CHIP_RV670) ||
4239 (rdev->family == CHIP_RV620) ||
4240 (rdev->family == CHIP_RV635)) {
4241 /* advertise upconfig capability */
4242 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4243 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4244 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4245 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4246 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4247 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4248 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4249 LC_RECONFIG_ARC_MISSING_ESCAPE);
4250 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4251 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4253 link_width_cntl |= LC_UPCONFIGURE_DIS;
4254 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4258 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4259 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4260 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4262 /* 55 nm r6xx asics */
4263 if ((rdev->family == CHIP_RV670) ||
4264 (rdev->family == CHIP_RV620) ||
4265 (rdev->family == CHIP_RV635)) {
4266 WREG32(MM_CFGREGS_CNTL, 0x8);
4267 link_cntl2 = RREG32(0x4088);
4268 WREG32(MM_CFGREGS_CNTL, 0);
4269 /* not supported yet */
4270 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4274 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4275 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4276 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4277 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4278 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4279 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4281 tmp = RREG32(0x541c);
4282 WREG32(0x541c, tmp | 0x8);
4283 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4284 link_cntl2 = RREG16(0x4088);
4285 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4287 WREG16(0x4088, link_cntl2);
4288 WREG32(MM_CFGREGS_CNTL, 0);
4290 if ((rdev->family == CHIP_RV670) ||
4291 (rdev->family == CHIP_RV620) ||
4292 (rdev->family == CHIP_RV635)) {
4293 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
4294 training_cntl &= ~LC_POINT_7_PLUS_EN;
4295 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
4297 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4298 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4299 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4302 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4303 speed_cntl |= LC_GEN2_EN_STRAP;
4304 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4307 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4308 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4310 link_width_cntl |= LC_UPCONFIGURE_DIS;
4312 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4313 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4318 * r600_get_gpu_clock - return GPU clock counter snapshot
4320 * @rdev: radeon_device pointer
4322 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4323 * Returns the 64 bit clock counter snapshot.
4325 uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
4329 mutex_lock(&rdev->gpu_clock_mutex);
4330 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4331 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4332 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4333 mutex_unlock(&rdev->gpu_clock_mutex);