drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  40 {
  41         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  42 }
  43
  44 static void
  45 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  46 {
  47         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49         uint32_t enabled_bits;
  50
  51         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  52
  53         WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
  54              "HDMI port enabled, expecting disabled\n");
  55 }
  56
  57 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  58 {
  59         struct intel_digital_port *intel_dig_port =
  60                 container_of(encoder, struct intel_digital_port, base.base);
  61         return &intel_dig_port->hdmi;
  62 }
  63
  64 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  65 {
  66         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  67 }
  68
  69 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  70 {
  71         uint8_t *data = (uint8_t *)frame;
  72         uint8_t sum = 0;
  73         unsigned i;
  74
  75         frame->checksum = 0;
  76         frame->ecc = 0;
  77
  78         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  79                 sum += data[i];
  80
  81         frame->checksum = 0x100 - sum;
  82 }
  83
  84 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  85 {
  86         switch (frame->type) {
  87         case DIP_TYPE_AVI:
  88                 return VIDEO_DIP_SELECT_AVI;
  89         case DIP_TYPE_SPD:
  90                 return VIDEO_DIP_SELECT_SPD;
  91         default:
  92                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  93                 return 0;
  94         }
  95 }
  96
  97 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  98 {
  99         switch (frame->type) {
 100         case DIP_TYPE_AVI:
 101                 return VIDEO_DIP_ENABLE_AVI;
 102         case DIP_TYPE_SPD:
 103                 return VIDEO_DIP_ENABLE_SPD;
 104         default:
 105                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 106                 return 0;
 107         }
 108 }
 109
 110 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
 111 {
 112         switch (frame->type) {
 113         case DIP_TYPE_AVI:
 114                 return VIDEO_DIP_ENABLE_AVI_HSW;
 115         case DIP_TYPE_SPD:
 116                 return VIDEO_DIP_ENABLE_SPD_HSW;
 117         default:
 118                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 119                 return 0;
 120         }
 121 }
 122
 123 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
 124 {
 125         switch (frame->type) {
 126         case DIP_TYPE_AVI:
 127                 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
 128         case DIP_TYPE_SPD:
 129                 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
 130         default:
 131                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 132                 return 0;
 133         }
 134 }
 135
 136 static void g4x_write_infoframe(struct drm_encoder *encoder,
 137                                 struct dip_infoframe *frame)
 138 {
 139         uint32_t *data = (uint32_t *)frame;
 140         struct drm_device *dev = encoder->dev;
 141         struct drm_i915_private *dev_priv = dev->dev_private;
 142         u32 val = I915_READ(VIDEO_DIP_CTL);
 143         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 144
 145         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 146
 147         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 148         val |= g4x_infoframe_index(frame);
 149
 150         val &= ~g4x_infoframe_enable(frame);
 151
 152         I915_WRITE(VIDEO_DIP_CTL, val);
 153
 154         mmiowb();
 155         for (i = 0; i < len; i += 4) {
 156                 I915_WRITE(VIDEO_DIP_DATA, *data);
 157                 data++;
 158         }
 159         /* Write every possible data byte to force correct ECC calculation. */
 160         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 161                 I915_WRITE(VIDEO_DIP_DATA, 0);
 162         mmiowb();
 163
 164         val |= g4x_infoframe_enable(frame);
 165         val &= ~VIDEO_DIP_FREQ_MASK;
 166         val |= VIDEO_DIP_FREQ_VSYNC;
 167
 168         I915_WRITE(VIDEO_DIP_CTL, val);
 169         POSTING_READ(VIDEO_DIP_CTL);
 170 }
 171
 172 static void ibx_write_infoframe(struct drm_encoder *encoder,
 173                                 struct dip_infoframe *frame)
 174 {
 175         uint32_t *data = (uint32_t *)frame;
 176         struct drm_device *dev = encoder->dev;
 177         struct drm_i915_private *dev_priv = dev->dev_private;
 178         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 179         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 180         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 181         u32 val = I915_READ(reg);
 182
 183         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 184
 185         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 186         val |= g4x_infoframe_index(frame);
 187
 188         val &= ~g4x_infoframe_enable(frame);
 189
 190         I915_WRITE(reg, val);
 191
 192         mmiowb();
 193         for (i = 0; i < len; i += 4) {
 194                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 195                 data++;
 196         }
 197         /* Write every possible data byte to force correct ECC calculation. */
 198         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 199                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 200         mmiowb();
 201
 202         val |= g4x_infoframe_enable(frame);
 203         val &= ~VIDEO_DIP_FREQ_MASK;
 204         val |= VIDEO_DIP_FREQ_VSYNC;
 205
 206         I915_WRITE(reg, val);
 207         POSTING_READ(reg);
 208 }
 209
 210 static void cpt_write_infoframe(struct drm_encoder *encoder,
 211                                 struct dip_infoframe *frame)
 212 {
 213         uint32_t *data = (uint32_t *)frame;
 214         struct drm_device *dev = encoder->dev;
 215         struct drm_i915_private *dev_priv = dev->dev_private;
 216         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 217         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 218         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 219         u32 val = I915_READ(reg);
 220
 221         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 222
 223         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 224         val |= g4x_infoframe_index(frame);
 225
 226         /* The DIP control register spec says that we need to update the AVI
 227          * infoframe without clearing its enable bit */
 228         if (frame->type != DIP_TYPE_AVI)
 229                 val &= ~g4x_infoframe_enable(frame);
 230
 231         I915_WRITE(reg, val);
 232
 233         mmiowb();
 234         for (i = 0; i < len; i += 4) {
 235                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 236                 data++;
 237         }
 238         /* Write every possible data byte to force correct ECC calculation. */
 239         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 240                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 241         mmiowb();
 242
 243         val |= g4x_infoframe_enable(frame);
 244         val &= ~VIDEO_DIP_FREQ_MASK;
 245         val |= VIDEO_DIP_FREQ_VSYNC;
 246
 247         I915_WRITE(reg, val);
 248         POSTING_READ(reg);
 249 }
 250
 251 static void vlv_write_infoframe(struct drm_encoder *encoder,
 252                                      struct dip_infoframe *frame)
 253 {
 254         uint32_t *data = (uint32_t *)frame;
 255         struct drm_device *dev = encoder->dev;
 256         struct drm_i915_private *dev_priv = dev->dev_private;
 257         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 258         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 259         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 260         u32 val = I915_READ(reg);
 261
 262         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 263
 264         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 265         val |= g4x_infoframe_index(frame);
 266
 267         val &= ~g4x_infoframe_enable(frame);
 268
 269         I915_WRITE(reg, val);
 270
 271         mmiowb();
 272         for (i = 0; i < len; i += 4) {
 273                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 274                 data++;
 275         }
 276         /* Write every possible data byte to force correct ECC calculation. */
 277         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 278                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 279         mmiowb();
 280
 281         val |= g4x_infoframe_enable(frame);
 282         val &= ~VIDEO_DIP_FREQ_MASK;
 283         val |= VIDEO_DIP_FREQ_VSYNC;
 284
 285         I915_WRITE(reg, val);
 286         POSTING_READ(reg);
 287 }
 288
 289 static void hsw_write_infoframe(struct drm_encoder *encoder,
 290                                 struct dip_infoframe *frame)
 291 {
 292         uint32_t *data = (uint32_t *)frame;
 293         struct drm_device *dev = encoder->dev;
 294         struct drm_i915_private *dev_priv = dev->dev_private;
 295         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 296         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 297         u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
 298         unsigned int i, len = DIP_HEADER_SIZE + frame->len;
 299         u32 val = I915_READ(ctl_reg);
 300
 301         if (data_reg == 0)
 302                 return;
 303
 304         val &= ~hsw_infoframe_enable(frame);
 305         I915_WRITE(ctl_reg, val);
 306
 307         mmiowb();
 308         for (i = 0; i < len; i += 4) {
 309                 I915_WRITE(data_reg + i, *data);
 310                 data++;
 311         }
 312         /* Write every possible data byte to force correct ECC calculation. */
 313         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 314                 I915_WRITE(data_reg + i, 0);
 315         mmiowb();
 316
 317         val |= hsw_infoframe_enable(frame);
 318         I915_WRITE(ctl_reg, val);
 319         POSTING_READ(ctl_reg);
 320 }
 321
 322 static void intel_set_infoframe(struct drm_encoder *encoder,
 323                                 struct dip_infoframe *frame)
 324 {
 325         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 326
 327         intel_dip_infoframe_csum(frame);
 328         intel_hdmi->write_infoframe(encoder, frame);
 329 }
 330
 331 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 332                                          struct drm_display_mode *adjusted_mode)
 333 {
 334         struct dip_infoframe avi_if = {
 335                 .type = DIP_TYPE_AVI,
 336                 .ver = DIP_VERSION_AVI,
 337                 .len = DIP_LEN_AVI,
 338         };
 339
 340         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 341                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 342
 343         avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode);
 344
 345         intel_set_infoframe(encoder, &avi_if);
 346 }
 347
 348 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 349 {
 350         struct dip_infoframe spd_if;
 351
 352         memset(&spd_if, 0, sizeof(spd_if));
 353         spd_if.type = DIP_TYPE_SPD;
 354         spd_if.ver = DIP_VERSION_SPD;
 355         spd_if.len = DIP_LEN_SPD;
 356         strcpy(spd_if.body.spd.vn, "Intel");
 357         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 358         spd_if.body.spd.sdi = DIP_SPD_PC;
 359
 360         intel_set_infoframe(encoder, &spd_if);
 361 }
 362
 363 static void g4x_set_infoframes(struct drm_encoder *encoder,
 364                                struct drm_display_mode *adjusted_mode)
 365 {
 366         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 367         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 368         u32 reg = VIDEO_DIP_CTL;
 369         u32 val = I915_READ(reg);
 370         u32 port;
 371
 372         assert_hdmi_port_disabled(intel_hdmi);
 373
 374         /* If the registers were not initialized yet, they might be zeroes,
 375          * which means we're selecting the AVI DIP and we're setting its
 376          * frequency to once. This seems to really confuse the HW and make
 377          * things stop working (the register spec says the AVI always needs to
 378          * be sent every VSync). So here we avoid writing to the register more
 379          * than we need and also explicitly select the AVI DIP and explicitly
 380          * set its frequency to every VSync. Avoiding to write it twice seems to
 381          * be enough to solve the problem, but being defensive shouldn't hurt us
 382          * either. */
 383         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 384
 385         if (!intel_hdmi->has_hdmi_sink) {
 386                 if (!(val & VIDEO_DIP_ENABLE))
 387                         return;
 388                 val &= ~VIDEO_DIP_ENABLE;
 389                 I915_WRITE(reg, val);
 390                 POSTING_READ(reg);
 391                 return;
 392         }
 393
 394         switch (intel_hdmi->sdvox_reg) {
 395         case SDVOB:
 396                 port = VIDEO_DIP_PORT_B;
 397                 break;
 398         case SDVOC:
 399                 port = VIDEO_DIP_PORT_C;
 400                 break;
 401         default:
 402                 BUG();
 403                 return;
 404         }
 405
 406         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 407                 if (val & VIDEO_DIP_ENABLE) {
 408                         val &= ~VIDEO_DIP_ENABLE;
 409                         I915_WRITE(reg, val);
 410                         POSTING_READ(reg);
 411                 }
 412                 val &= ~VIDEO_DIP_PORT_MASK;
 413                 val |= port;
 414         }
 415
 416         val |= VIDEO_DIP_ENABLE;
 417         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 418
 419         I915_WRITE(reg, val);
 420         POSTING_READ(reg);
 421
 422         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 423         intel_hdmi_set_spd_infoframe(encoder);
 424 }
 425
 426 static void ibx_set_infoframes(struct drm_encoder *encoder,
 427                                struct drm_display_mode *adjusted_mode)
 428 {
 429         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 430         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 431         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 432         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 433         u32 val = I915_READ(reg);
 434         u32 port;
 435
 436         assert_hdmi_port_disabled(intel_hdmi);
 437
 438         /* See the big comment in g4x_set_infoframes() */
 439         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 440
 441         if (!intel_hdmi->has_hdmi_sink) {
 442                 if (!(val & VIDEO_DIP_ENABLE))
 443                         return;
 444                 val &= ~VIDEO_DIP_ENABLE;
 445                 I915_WRITE(reg, val);
 446                 POSTING_READ(reg);
 447                 return;
 448         }
 449
 450         switch (intel_hdmi->sdvox_reg) {
 451         case HDMIB:
 452                 port = VIDEO_DIP_PORT_B;
 453                 break;
 454         case HDMIC:
 455                 port = VIDEO_DIP_PORT_C;
 456                 break;
 457         case HDMID:
 458                 port = VIDEO_DIP_PORT_D;
 459                 break;
 460         default:
 461                 BUG();
 462                 return;
 463         }
 464
 465         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 466                 if (val & VIDEO_DIP_ENABLE) {
 467                         val &= ~VIDEO_DIP_ENABLE;
 468                         I915_WRITE(reg, val);
 469                         POSTING_READ(reg);
 470                 }
 471                 val &= ~VIDEO_DIP_PORT_MASK;
 472                 val |= port;
 473         }
 474
 475         val |= VIDEO_DIP_ENABLE;
 476         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 477                  VIDEO_DIP_ENABLE_GCP);
 478
 479         I915_WRITE(reg, val);
 480         POSTING_READ(reg);
 481
 482         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 483         intel_hdmi_set_spd_infoframe(encoder);
 484 }
 485
 486 static void cpt_set_infoframes(struct drm_encoder *encoder,
 487                                struct drm_display_mode *adjusted_mode)
 488 {
 489         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 490         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 491         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 492         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 493         u32 val = I915_READ(reg);
 494
 495         assert_hdmi_port_disabled(intel_hdmi);
 496
 497         /* See the big comment in g4x_set_infoframes() */
 498         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 499
 500         if (!intel_hdmi->has_hdmi_sink) {
 501                 if (!(val & VIDEO_DIP_ENABLE))
 502                         return;
 503                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 504                 I915_WRITE(reg, val);
 505                 POSTING_READ(reg);
 506                 return;
 507         }
 508
 509         /* Set both together, unset both together: see the spec. */
 510         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 511         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 512                  VIDEO_DIP_ENABLE_GCP);
 513
 514         I915_WRITE(reg, val);
 515         POSTING_READ(reg);
 516
 517         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 518         intel_hdmi_set_spd_infoframe(encoder);
 519 }
 520
 521 static void vlv_set_infoframes(struct drm_encoder *encoder,
 522                                struct drm_display_mode *adjusted_mode)
 523 {
 524         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 525         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 526         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 527         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 528         u32 val = I915_READ(reg);
 529
 530         assert_hdmi_port_disabled(intel_hdmi);
 531
 532         /* See the big comment in g4x_set_infoframes() */
 533         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 534
 535         if (!intel_hdmi->has_hdmi_sink) {
 536                 if (!(val & VIDEO_DIP_ENABLE))
 537                         return;
 538                 val &= ~VIDEO_DIP_ENABLE;
 539                 I915_WRITE(reg, val);
 540                 POSTING_READ(reg);
 541                 return;
 542         }
 543
 544         val |= VIDEO_DIP_ENABLE;
 545         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 546                  VIDEO_DIP_ENABLE_GCP);
 547
 548         I915_WRITE(reg, val);
 549         POSTING_READ(reg);
 550
 551         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 552         intel_hdmi_set_spd_infoframe(encoder);
 553 }
 554
 555 static void hsw_set_infoframes(struct drm_encoder *encoder,
 556                                struct drm_display_mode *adjusted_mode)
 557 {
 558         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 559         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 560         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 561         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
 562         u32 val = I915_READ(reg);
 563
 564         assert_hdmi_port_disabled(intel_hdmi);
 565
 566         if (!intel_hdmi->has_hdmi_sink) {
 567                 I915_WRITE(reg, 0);
 568                 POSTING_READ(reg);
 569                 return;
 570         }
 571
 572         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 573                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 574
 575         I915_WRITE(reg, val);
 576         POSTING_READ(reg);
 577
 578         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 579         intel_hdmi_set_spd_infoframe(encoder);
 580 }
 581
 582 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 583                                 struct drm_display_mode *mode,
 584                                 struct drm_display_mode *adjusted_mode)
 585 {
 586         struct drm_device *dev = encoder->dev;
 587         struct drm_i915_private *dev_priv = dev->dev_private;
 588         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 589         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 590         u32 sdvox;
 591
 592         sdvox = SDVO_ENCODING_HDMI;
 593         if (!HAS_PCH_SPLIT(dev))
 594                 sdvox |= intel_hdmi->color_range;
 595         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 596                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
 597         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 598                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
 599
 600         if (intel_crtc->bpp > 24)
 601                 sdvox |= COLOR_FORMAT_12bpc;
 602         else
 603                 sdvox |= COLOR_FORMAT_8bpc;
 604
 605         /* Required on CPT */
 606         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 607                 sdvox |= HDMI_MODE_SELECT;
 608
 609         if (intel_hdmi->has_audio) {
 610                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 611                                  pipe_name(intel_crtc->pipe));
 612                 sdvox |= SDVO_AUDIO_ENABLE;
 613                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
 614                 intel_write_eld(encoder, adjusted_mode);
 615         }
 616
 617         if (HAS_PCH_CPT(dev))
 618                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
 619         else if (intel_crtc->pipe == PIPE_B)
 620                 sdvox |= SDVO_PIPE_B_SELECT;
 621
 622         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
 623         POSTING_READ(intel_hdmi->sdvox_reg);
 624
 625         intel_hdmi->set_infoframes(encoder, adjusted_mode);
 626 }
 627
 628 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 629                                     enum pipe *pipe)
 630 {
 631         struct drm_device *dev = encoder->base.dev;
 632         struct drm_i915_private *dev_priv = dev->dev_private;
 633         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 634         u32 tmp;
 635
 636         tmp = I915_READ(intel_hdmi->sdvox_reg);
 637
 638         if (!(tmp & SDVO_ENABLE))
 639                 return false;
 640
 641         if (HAS_PCH_CPT(dev))
 642                 *pipe = PORT_TO_PIPE_CPT(tmp);
 643         else
 644                 *pipe = PORT_TO_PIPE(tmp);
 645
 646         return true;
 647 }
 648
 649 static void intel_enable_hdmi(struct intel_encoder *encoder)
 650 {
 651         struct drm_device *dev = encoder->base.dev;
 652         struct drm_i915_private *dev_priv = dev->dev_private;
 653         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 654         u32 temp;
 655         u32 enable_bits = SDVO_ENABLE;
 656
 657         if (intel_hdmi->has_audio)
 658                 enable_bits |= SDVO_AUDIO_ENABLE;
 659
 660         temp = I915_READ(intel_hdmi->sdvox_reg);
 661
 662         /* HW workaround for IBX, we need to move the port to transcoder A
 663          * before disabling it. */
 664         if (HAS_PCH_IBX(dev)) {
 665                 struct drm_crtc *crtc = encoder->base.crtc;
 666                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 667
 668                 /* Restore the transcoder select bit. */
 669                 if (pipe == PIPE_B)
 670                         enable_bits |= SDVO_PIPE_B_SELECT;
 671         }
 672
 673         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 674          * we do this anyway which shows more stable in testing.
 675          */
 676         if (HAS_PCH_SPLIT(dev)) {
 677                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 678                 POSTING_READ(intel_hdmi->sdvox_reg);
 679         }
 680
 681         temp |= enable_bits;
 682
 683         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 684         POSTING_READ(intel_hdmi->sdvox_reg);
 685
 686         /* HW workaround, need to write this twice for issue that may result
 687          * in first write getting masked.
 688          */
 689         if (HAS_PCH_SPLIT(dev)) {
 690                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 691                 POSTING_READ(intel_hdmi->sdvox_reg);
 692         }
 693 }
 694
 695 static void intel_disable_hdmi(struct intel_encoder *encoder)
 696 {
 697         struct drm_device *dev = encoder->base.dev;
 698         struct drm_i915_private *dev_priv = dev->dev_private;
 699         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 700         u32 temp;
 701         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 702
 703         temp = I915_READ(intel_hdmi->sdvox_reg);
 704
 705         /* HW workaround for IBX, we need to move the port to transcoder A
 706          * before disabling it. */
 707         if (HAS_PCH_IBX(dev)) {
 708                 struct drm_crtc *crtc = encoder->base.crtc;
 709                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 710
 711                 if (temp & SDVO_PIPE_B_SELECT) {
 712                         temp &= ~SDVO_PIPE_B_SELECT;
 713                         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 714                         POSTING_READ(intel_hdmi->sdvox_reg);
 715
 716                         /* Again we need to write this twice. */
 717                         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 718                         POSTING_READ(intel_hdmi->sdvox_reg);
 719
 720                         /* Transcoder selection bits only update
 721                          * effectively on vblank. */
 722                         if (crtc)
 723                                 intel_wait_for_vblank(dev, pipe);
 724                         else
 725                                 msleep(50);
 726                 }
 727         }
 728
 729         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 730          * we do this anyway which shows more stable in testing.
 731          */
 732         if (HAS_PCH_SPLIT(dev)) {
 733                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
 734                 POSTING_READ(intel_hdmi->sdvox_reg);
 735         }
 736
 737         temp &= ~enable_bits;
 738
 739         I915_WRITE(intel_hdmi->sdvox_reg, temp);
 740         POSTING_READ(intel_hdmi->sdvox_reg);
 741
 742         /* HW workaround, need to write this twice for issue that may result
 743          * in first write getting masked.
 744          */
 745         if (HAS_PCH_SPLIT(dev)) {
 746                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
 747                 POSTING_READ(intel_hdmi->sdvox_reg);
 748         }
 749 }
 750
 751 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 752                                  struct drm_display_mode *mode)
 753 {
 754         if (mode->clock > 165000)
 755                 return MODE_CLOCK_HIGH;
 756         if (mode->clock < 20000)
 757                 return MODE_CLOCK_LOW;
 758
 759         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 760                 return MODE_NO_DBLESCAN;
 761
 762         return MODE_OK;
 763 }
 764
 765 bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 766                            const struct drm_display_mode *mode,
 767                            struct drm_display_mode *adjusted_mode)
 768 {
 769         return true;
 770 }
 771
 772 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
 773 {
 774         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
 775         struct drm_i915_private *dev_priv = dev->dev_private;
 776         uint32_t bit;
 777
 778         switch (intel_hdmi->sdvox_reg) {
 779         case SDVOB:
 780                 bit = HDMIB_HOTPLUG_LIVE_STATUS;
 781                 break;
 782         case SDVOC:
 783                 bit = HDMIC_HOTPLUG_LIVE_STATUS;
 784                 break;
 785         default:
 786                 bit = 0;
 787                 break;
 788         }
 789
 790         return I915_READ(PORT_HOTPLUG_STAT) & bit;
 791 }
 792
 793 static enum drm_connector_status
 794 intel_hdmi_detect(struct drm_connector *connector, bool force)
 795 {
 796         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 797         struct intel_digital_port *intel_dig_port =
 798                 hdmi_to_dig_port(intel_hdmi);
 799         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 800         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 801         struct edid *edid;
 802         enum drm_connector_status status = connector_status_disconnected;
 803
 804         if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
 805                 return status;
 806
 807         intel_hdmi->has_hdmi_sink = false;
 808         intel_hdmi->has_audio = false;
 809         edid = drm_get_edid(connector,
 810                             intel_gmbus_get_adapter(dev_priv,
 811                                                     intel_hdmi->ddc_bus));
 812
 813         if (edid) {
 814                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 815                         status = connector_status_connected;
 816                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 817                                 intel_hdmi->has_hdmi_sink =
 818                                                 drm_detect_hdmi_monitor(edid);
 819                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 820                 }
 821                 kfree(edid);
 822         }
 823
 824         if (status == connector_status_connected) {
 825                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 826                         intel_hdmi->has_audio =
 827                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 828                 intel_encoder->type = INTEL_OUTPUT_HDMI;
 829         }
 830
 831         return status;
 832 }
 833
 834 static int intel_hdmi_get_modes(struct drm_connector *connector)
 835 {
 836         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 837         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 838
 839         /* We should parse the EDID data and find out if it's an HDMI sink so
 840          * we can send audio to it.
 841          */
 842
 843         return intel_ddc_get_modes(connector,
 844                                    intel_gmbus_get_adapter(dev_priv,
 845                                                            intel_hdmi->ddc_bus));
 846 }
 847
 848 static bool
 849 intel_hdmi_detect_audio(struct drm_connector *connector)
 850 {
 851         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 852         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 853         struct edid *edid;
 854         bool has_audio = false;
 855
 856         edid = drm_get_edid(connector,
 857                             intel_gmbus_get_adapter(dev_priv,
 858                                                     intel_hdmi->ddc_bus));
 859         if (edid) {
 860                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 861                         has_audio = drm_detect_monitor_audio(edid);
 862                 kfree(edid);
 863         }
 864
 865         return has_audio;
 866 }
 867
 868 static int
 869 intel_hdmi_set_property(struct drm_connector *connector,
 870                         struct drm_property *property,
 871                         uint64_t val)
 872 {
 873         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 874         struct intel_digital_port *intel_dig_port =
 875                 hdmi_to_dig_port(intel_hdmi);
 876         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 877         int ret;
 878
 879         ret = drm_object_property_set_value(&connector->base, property, val);
 880         if (ret)
 881                 return ret;
 882
 883         if (property == dev_priv->force_audio_property) {
 884                 enum hdmi_force_audio i = val;
 885                 bool has_audio;
 886
 887                 if (i == intel_hdmi->force_audio)
 888                         return 0;
 889
 890                 intel_hdmi->force_audio = i;
 891
 892                 if (i == HDMI_AUDIO_AUTO)
 893                         has_audio = intel_hdmi_detect_audio(connector);
 894                 else
 895                         has_audio = (i == HDMI_AUDIO_ON);
 896
 897                 if (i == HDMI_AUDIO_OFF_DVI)
 898                         intel_hdmi->has_hdmi_sink = 0;
 899
 900                 intel_hdmi->has_audio = has_audio;
 901                 goto done;
 902         }
 903
 904         if (property == dev_priv->broadcast_rgb_property) {
 905                 if (val == !!intel_hdmi->color_range)
 906                         return 0;
 907
 908                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
 909                 goto done;
 910         }
 911
 912         return -EINVAL;
 913
 914 done:
 915         if (intel_dig_port->base.base.crtc) {
 916                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 917                 intel_set_mode(crtc, &crtc->mode,
 918                                crtc->x, crtc->y, crtc->fb);
 919         }
 920
 921         return 0;
 922 }
 923
 924 static void intel_hdmi_destroy(struct drm_connector *connector)
 925 {
 926         drm_sysfs_connector_remove(connector);
 927         drm_connector_cleanup(connector);
 928         kfree(connector);
 929 }
 930
 931 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
 932         .mode_fixup = intel_hdmi_mode_fixup,
 933         .mode_set = intel_hdmi_mode_set,
 934         .disable = intel_encoder_noop,
 935 };
 936
 937 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
 938         .dpms = intel_connector_dpms,
 939         .detect = intel_hdmi_detect,
 940         .fill_modes = drm_helper_probe_single_connector_modes,
 941         .set_property = intel_hdmi_set_property,
 942         .destroy = intel_hdmi_destroy,
 943 };
 944
 945 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
 946         .get_modes = intel_hdmi_get_modes,
 947         .mode_valid = intel_hdmi_mode_valid,
 948         .best_encoder = intel_best_encoder,
 949 };
 950
 951 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
 952         .destroy = intel_encoder_destroy,
 953 };
 954
 955 static void
 956 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
 957 {
 958         intel_attach_force_audio_property(connector);
 959         intel_attach_broadcast_rgb_property(connector);
 960 }
 961
 962 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 963                                struct intel_connector *intel_connector)
 964 {
 965         struct drm_connector *connector = &intel_connector->base;
 966         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 967         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 968         struct drm_device *dev = intel_encoder->base.dev;
 969         struct drm_i915_private *dev_priv = dev->dev_private;
 970         enum port port = intel_dig_port->port;
 971
 972         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
 973                            DRM_MODE_CONNECTOR_HDMIA);
 974         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
 975
 976         connector->polled = DRM_CONNECTOR_POLL_HPD;
 977         connector->interlace_allowed = 1;
 978         connector->doublescan_allowed = 0;
 979
 980         switch (port) {
 981         case PORT_B:
 982                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
 983                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
 984                 break;
 985         case PORT_C:
 986                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
 987                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
 988                 break;
 989         case PORT_D:
 990                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
 991                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
 992                 break;
 993         case PORT_A:
 994                 /* Internal port only for eDP. */
 995         default:
 996                 BUG();
 997         }
 998
 999         if (!HAS_PCH_SPLIT(dev)) {
1000                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1001                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1002         } else if (IS_VALLEYVIEW(dev)) {
1003                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1004                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1005         } else if (IS_HASWELL(dev)) {
1006                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1007                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1008         } else if (HAS_PCH_IBX(dev)) {
1009                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1010                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1011         } else {
1012                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1013                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1014         }
1015
1016         if (HAS_DDI(dev))
1017                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1018         else
1019                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1020
1021         intel_hdmi_add_properties(intel_hdmi, connector);
1022
1023         intel_connector_attach_encoder(intel_connector, intel_encoder);
1024         drm_sysfs_connector_add(connector);
1025
1026         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1027          * 0xd.  Failure to do so will result in spurious interrupts being
1028          * generated on the port when a cable is not attached.
1029          */
1030         if (IS_G4X(dev) && !IS_GM45(dev)) {
1031                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1032                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1033         }
1034 }
1035
1036 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
1037 {
1038         struct intel_digital_port *intel_dig_port;
1039         struct intel_encoder *intel_encoder;
1040         struct drm_encoder *encoder;
1041         struct intel_connector *intel_connector;
1042
1043         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1044         if (!intel_dig_port)
1045                 return;
1046
1047         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1048         if (!intel_connector) {
1049                 kfree(intel_dig_port);
1050                 return;
1051         }
1052
1053         intel_encoder = &intel_dig_port->base;
1054         encoder = &intel_encoder->base;
1055
1056         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1057                          DRM_MODE_ENCODER_TMDS);
1058         drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
1059
1060         intel_encoder->enable = intel_enable_hdmi;
1061         intel_encoder->disable = intel_disable_hdmi;
1062         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1063
1064         intel_encoder->type = INTEL_OUTPUT_HDMI;
1065         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1066         intel_encoder->cloneable = false;
1067
1068         intel_dig_port->port = port;
1069         intel_dig_port->hdmi.sdvox_reg = sdvox_reg;
1070         intel_dig_port->dp.output_reg = 0;
1071
1072         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1073 }