drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include "intel_drv.h"
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include <linux/pci.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/acpi.h>
  41 #include <linux/pnp.h>
  42 #include <linux/vga_switcheroo.h>
  43 #include <linux/slab.h>
  44 #include <acpi/video.h>
  45 #include <asm/pat.h>
  46
  47 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  48
  49 #define BEGIN_LP_RING(n) \
  50         intel_ring_begin(LP_RING(dev_priv), (n))
  51
  52 #define OUT_RING(x) \
  53         intel_ring_emit(LP_RING(dev_priv), x)
  54
  55 #define ADVANCE_LP_RING() \
  56         intel_ring_advance(LP_RING(dev_priv))
  57
  58 /**
  59  * Lock test for when it's just for synchronization of ring access.
  60  *
  61  * In that case, we don't need to do it when GEM is initialized as nobody else
  62  * has access to the ring.
  63  */
  64 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  65         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  66                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  67 } while (0)
  68
  69 static inline u32
  70 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  71 {
  72         if (I915_NEED_GFX_HWS(dev_priv->dev))
  73                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  74         else
  75                 return intel_read_status_page(LP_RING(dev_priv), reg);
  76 }
  77
  78 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  79 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  80 #define I915_BREADCRUMB_INDEX           0x21
  81
  82 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  83 {
  84         drm_i915_private_t *dev_priv = dev->dev_private;
  85         struct drm_i915_master_private *master_priv;
  86
  87         if (dev->primary->master) {
  88                 master_priv = dev->primary->master->driver_priv;
  89                 if (master_priv->sarea_priv)
  90                         master_priv->sarea_priv->last_dispatch =
  91                                 READ_BREADCRUMB(dev_priv);
  92         }
  93 }
  94
  95 static void i915_write_hws_pga(struct drm_device *dev)
  96 {
  97         drm_i915_private_t *dev_priv = dev->dev_private;
  98         u32 addr;
  99
 100         addr = dev_priv->status_page_dmah->busaddr;
 101         if (INTEL_INFO(dev)->gen >= 4)
 102                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 103         I915_WRITE(HWS_PGA, addr);
 104 }
 105
 106 /**
 107  * Frees the hardware status page, whether it's a physical address or a virtual
 108  * address set up by the X Server.
 109  */
 110 static void i915_free_hws(struct drm_device *dev)
 111 {
 112         drm_i915_private_t *dev_priv = dev->dev_private;
 113         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 114
 115         if (dev_priv->status_page_dmah) {
 116                 drm_pci_free(dev, dev_priv->status_page_dmah);
 117                 dev_priv->status_page_dmah = NULL;
 118         }
 119
 120         if (ring->status_page.gfx_addr) {
 121                 ring->status_page.gfx_addr = 0;
 122                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 123         }
 124
 125         /* Need to rewrite hardware status page */
 126         I915_WRITE(HWS_PGA, 0x1ffff000);
 127 }
 128
 129 void i915_kernel_lost_context(struct drm_device * dev)
 130 {
 131         drm_i915_private_t *dev_priv = dev->dev_private;
 132         struct drm_i915_master_private *master_priv;
 133         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 134
 135         /*
 136          * We should never lose context on the ring with modesetting
 137          * as we don't expose it to userspace
 138          */
 139         if (drm_core_check_feature(dev, DRIVER_MODESET))
 140                 return;
 141
 142         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 143         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 144         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 145         if (ring->space < 0)
 146                 ring->space += ring->size;
 147
 148         if (!dev->primary->master)
 149                 return;
 150
 151         master_priv = dev->primary->master->driver_priv;
 152         if (ring->head == ring->tail && master_priv->sarea_priv)
 153                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 154 }
 155
 156 static int i915_dma_cleanup(struct drm_device * dev)
 157 {
 158         drm_i915_private_t *dev_priv = dev->dev_private;
 159         int i;
 160
 161         /* Make sure interrupts are disabled here because the uninstall ioctl
 162          * may not have been called from userspace and after dev_private
 163          * is freed, it's too late.
 164          */
 165         if (dev->irq_enabled)
 166                 drm_irq_uninstall(dev);
 167
 168         mutex_lock(&dev->struct_mutex);
 169         for (i = 0; i < I915_NUM_RINGS; i++)
 170                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 171         mutex_unlock(&dev->struct_mutex);
 172
 173         /* Clear the HWS virtual address at teardown */
 174         if (I915_NEED_GFX_HWS(dev))
 175                 i915_free_hws(dev);
 176
 177         return 0;
 178 }
 179
 180 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 181 {
 182         drm_i915_private_t *dev_priv = dev->dev_private;
 183         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 184         int ret;
 185
 186         master_priv->sarea = drm_getsarea(dev);
 187         if (master_priv->sarea) {
 188                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 189                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 190         } else {
 191                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 192         }
 193
 194         if (init->ring_size != 0) {
 195                 if (LP_RING(dev_priv)->obj != NULL) {
 196                         i915_dma_cleanup(dev);
 197                         DRM_ERROR("Client tried to initialize ringbuffer in "
 198                                   "GEM mode\n");
 199                         return -EINVAL;
 200                 }
 201
 202                 ret = intel_render_ring_init_dri(dev,
 203                                                  init->ring_start,
 204                                                  init->ring_size);
 205                 if (ret) {
 206                         i915_dma_cleanup(dev);
 207                         return ret;
 208                 }
 209         }
 210
 211         dev_priv->dri1.cpp = init->cpp;
 212         dev_priv->dri1.back_offset = init->back_offset;
 213         dev_priv->dri1.front_offset = init->front_offset;
 214         dev_priv->dri1.current_page = 0;
 215         if (master_priv->sarea_priv)
 216                 master_priv->sarea_priv->pf_current_page = 0;
 217
 218         /* Allow hardware batchbuffers unless told otherwise.
 219          */
 220         dev_priv->dri1.allow_batchbuffer = 1;
 221
 222         return 0;
 223 }
 224
 225 static int i915_dma_resume(struct drm_device * dev)
 226 {
 227         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 228         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 229
 230         DRM_DEBUG_DRIVER("%s\n", __func__);
 231
 232         if (ring->virtual_start == NULL) {
 233                 DRM_ERROR("can not ioremap virtual address for"
 234                           " ring buffer\n");
 235                 return -ENOMEM;
 236         }
 237
 238         /* Program Hardware Status Page */
 239         if (!ring->status_page.page_addr) {
 240                 DRM_ERROR("Can not find hardware status page\n");
 241                 return -EINVAL;
 242         }
 243         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 244                                 ring->status_page.page_addr);
 245         if (ring->status_page.gfx_addr != 0)
 246                 intel_ring_setup_status_page(ring);
 247         else
 248                 i915_write_hws_pga(dev);
 249
 250         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 251
 252         return 0;
 253 }
 254
 255 static int i915_dma_init(struct drm_device *dev, void *data,
 256                          struct drm_file *file_priv)
 257 {
 258         drm_i915_init_t *init = data;
 259         int retcode = 0;
 260
 261         if (drm_core_check_feature(dev, DRIVER_MODESET))
 262                 return -ENODEV;
 263
 264         switch (init->func) {
 265         case I915_INIT_DMA:
 266                 retcode = i915_initialize(dev, init);
 267                 break;
 268         case I915_CLEANUP_DMA:
 269                 retcode = i915_dma_cleanup(dev);
 270                 break;
 271         case I915_RESUME_DMA:
 272                 retcode = i915_dma_resume(dev);
 273                 break;
 274         default:
 275                 retcode = -EINVAL;
 276                 break;
 277         }
 278
 279         return retcode;
 280 }
 281
 282 /* Implement basically the same security restrictions as hardware does
 283  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 284  *
 285  * Most of the calculations below involve calculating the size of a
 286  * particular instruction.  It's important to get the size right as
 287  * that tells us where the next instruction to check is.  Any illegal
 288  * instruction detected will be given a size of zero, which is a
 289  * signal to abort the rest of the buffer.
 290  */
 291 static int validate_cmd(int cmd)
 292 {
 293         switch (((cmd >> 29) & 0x7)) {
 294         case 0x0:
 295                 switch ((cmd >> 23) & 0x3f) {
 296                 case 0x0:
 297                         return 1;       /* MI_NOOP */
 298                 case 0x4:
 299                         return 1;       /* MI_FLUSH */
 300                 default:
 301                         return 0;       /* disallow everything else */
 302                 }
 303                 break;
 304         case 0x1:
 305                 return 0;       /* reserved */
 306         case 0x2:
 307                 return (cmd & 0xff) + 2;        /* 2d commands */
 308         case 0x3:
 309                 if (((cmd >> 24) & 0x1f) <= 0x18)
 310                         return 1;
 311
 312                 switch ((cmd >> 24) & 0x1f) {
 313                 case 0x1c:
 314                         return 1;
 315                 case 0x1d:
 316                         switch ((cmd >> 16) & 0xff) {
 317                         case 0x3:
 318                                 return (cmd & 0x1f) + 2;
 319                         case 0x4:
 320                                 return (cmd & 0xf) + 2;
 321                         default:
 322                                 return (cmd & 0xffff) + 2;
 323                         }
 324                 case 0x1e:
 325                         if (cmd & (1 << 23))
 326                                 return (cmd & 0xffff) + 1;
 327                         else
 328                                 return 1;
 329                 case 0x1f:
 330                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 331                                 return (cmd & 0x1ffff) + 2;
 332                         else if (cmd & (1 << 17))       /* indirect random */
 333                                 if ((cmd & 0xffff) == 0)
 334                                         return 0;       /* unknown length, too hard */
 335                                 else
 336                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 337                         else
 338                                 return 2;       /* indirect sequential */
 339                 default:
 340                         return 0;
 341                 }
 342         default:
 343                 return 0;
 344         }
 345
 346         return 0;
 347 }
 348
 349 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 350 {
 351         drm_i915_private_t *dev_priv = dev->dev_private;
 352         int i, ret;
 353
 354         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 355                 return -EINVAL;
 356
 357         for (i = 0; i < dwords;) {
 358                 int sz = validate_cmd(buffer[i]);
 359                 if (sz == 0 || i + sz > dwords)
 360                         return -EINVAL;
 361                 i += sz;
 362         }
 363
 364         ret = BEGIN_LP_RING((dwords+1)&~1);
 365         if (ret)
 366                 return ret;
 367
 368         for (i = 0; i < dwords; i++)
 369                 OUT_RING(buffer[i]);
 370         if (dwords & 1)
 371                 OUT_RING(0);
 372
 373         ADVANCE_LP_RING();
 374
 375         return 0;
 376 }
 377
 378 int
 379 i915_emit_box(struct drm_device *dev,
 380               struct drm_clip_rect *box,
 381               int DR1, int DR4)
 382 {
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384         int ret;
 385
 386         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 387             box->y2 <= 0 || box->x2 <= 0) {
 388                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 389                           box->x1, box->y1, box->x2, box->y2);
 390                 return -EINVAL;
 391         }
 392
 393         if (INTEL_INFO(dev)->gen >= 4) {
 394                 ret = BEGIN_LP_RING(4);
 395                 if (ret)
 396                         return ret;
 397
 398                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 399                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 400                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 401                 OUT_RING(DR4);
 402         } else {
 403                 ret = BEGIN_LP_RING(6);
 404                 if (ret)
 405                         return ret;
 406
 407                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 408                 OUT_RING(DR1);
 409                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 410                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 411                 OUT_RING(DR4);
 412                 OUT_RING(0);
 413         }
 414         ADVANCE_LP_RING();
 415
 416         return 0;
 417 }
 418
 419 /* XXX: Emitting the counter should really be moved to part of the IRQ
 420  * emit. For now, do it in both places:
 421  */
 422
 423 static void i915_emit_breadcrumb(struct drm_device *dev)
 424 {
 425         drm_i915_private_t *dev_priv = dev->dev_private;
 426         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 427
 428         dev_priv->dri1.counter++;
 429         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 430                 dev_priv->dri1.counter = 0;
 431         if (master_priv->sarea_priv)
 432                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 433
 434         if (BEGIN_LP_RING(4) == 0) {
 435                 OUT_RING(MI_STORE_DWORD_INDEX);
 436                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 437                 OUT_RING(dev_priv->dri1.counter);
 438                 OUT_RING(0);
 439                 ADVANCE_LP_RING();
 440         }
 441 }
 442
 443 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 444                                    drm_i915_cmdbuffer_t *cmd,
 445                                    struct drm_clip_rect *cliprects,
 446                                    void *cmdbuf)
 447 {
 448         int nbox = cmd->num_cliprects;
 449         int i = 0, count, ret;
 450
 451         if (cmd->sz & 0x3) {
 452                 DRM_ERROR("alignment");
 453                 return -EINVAL;
 454         }
 455
 456         i915_kernel_lost_context(dev);
 457
 458         count = nbox ? nbox : 1;
 459
 460         for (i = 0; i < count; i++) {
 461                 if (i < nbox) {
 462                         ret = i915_emit_box(dev, &cliprects[i],
 463                                             cmd->DR1, cmd->DR4);
 464                         if (ret)
 465                                 return ret;
 466                 }
 467
 468                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 469                 if (ret)
 470                         return ret;
 471         }
 472
 473         i915_emit_breadcrumb(dev);
 474         return 0;
 475 }
 476
 477 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 478                                      drm_i915_batchbuffer_t * batch,
 479                                      struct drm_clip_rect *cliprects)
 480 {
 481         struct drm_i915_private *dev_priv = dev->dev_private;
 482         int nbox = batch->num_cliprects;
 483         int i, count, ret;
 484
 485         if ((batch->start | batch->used) & 0x7) {
 486                 DRM_ERROR("alignment");
 487                 return -EINVAL;
 488         }
 489
 490         i915_kernel_lost_context(dev);
 491
 492         count = nbox ? nbox : 1;
 493         for (i = 0; i < count; i++) {
 494                 if (i < nbox) {
 495                         ret = i915_emit_box(dev, &cliprects[i],
 496                                             batch->DR1, batch->DR4);
 497                         if (ret)
 498                                 return ret;
 499                 }
 500
 501                 if (!IS_I830(dev) && !IS_845G(dev)) {
 502                         ret = BEGIN_LP_RING(2);
 503                         if (ret)
 504                                 return ret;
 505
 506                         if (INTEL_INFO(dev)->gen >= 4) {
 507                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 508                                 OUT_RING(batch->start);
 509                         } else {
 510                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 511                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 512                         }
 513                 } else {
 514                         ret = BEGIN_LP_RING(4);
 515                         if (ret)
 516                                 return ret;
 517
 518                         OUT_RING(MI_BATCH_BUFFER);
 519                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 520                         OUT_RING(batch->start + batch->used - 4);
 521                         OUT_RING(0);
 522                 }
 523                 ADVANCE_LP_RING();
 524         }
 525
 526
 527         if (IS_G4X(dev) || IS_GEN5(dev)) {
 528                 if (BEGIN_LP_RING(2) == 0) {
 529                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 530                         OUT_RING(MI_NOOP);
 531                         ADVANCE_LP_RING();
 532                 }
 533         }
 534
 535         i915_emit_breadcrumb(dev);
 536         return 0;
 537 }
 538
 539 static int i915_dispatch_flip(struct drm_device * dev)
 540 {
 541         drm_i915_private_t *dev_priv = dev->dev_private;
 542         struct drm_i915_master_private *master_priv =
 543                 dev->primary->master->driver_priv;
 544         int ret;
 545
 546         if (!master_priv->sarea_priv)
 547                 return -EINVAL;
 548
 549         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 550                           __func__,
 551                          dev_priv->dri1.current_page,
 552                          master_priv->sarea_priv->pf_current_page);
 553
 554         i915_kernel_lost_context(dev);
 555
 556         ret = BEGIN_LP_RING(10);
 557         if (ret)
 558                 return ret;
 559
 560         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 561         OUT_RING(0);
 562
 563         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 564         OUT_RING(0);
 565         if (dev_priv->dri1.current_page == 0) {
 566                 OUT_RING(dev_priv->dri1.back_offset);
 567                 dev_priv->dri1.current_page = 1;
 568         } else {
 569                 OUT_RING(dev_priv->dri1.front_offset);
 570                 dev_priv->dri1.current_page = 0;
 571         }
 572         OUT_RING(0);
 573
 574         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 575         OUT_RING(0);
 576
 577         ADVANCE_LP_RING();
 578
 579         master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 580
 581         if (BEGIN_LP_RING(4) == 0) {
 582                 OUT_RING(MI_STORE_DWORD_INDEX);
 583                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 584                 OUT_RING(dev_priv->dri1.counter);
 585                 OUT_RING(0);
 586                 ADVANCE_LP_RING();
 587         }
 588
 589         master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 590         return 0;
 591 }
 592
 593 static int i915_quiescent(struct drm_device *dev)
 594 {
 595         i915_kernel_lost_context(dev);
 596         return intel_ring_idle(LP_RING(dev->dev_private));
 597 }
 598
 599 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 600                             struct drm_file *file_priv)
 601 {
 602         int ret;
 603
 604         if (drm_core_check_feature(dev, DRIVER_MODESET))
 605                 return -ENODEV;
 606
 607         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 608
 609         mutex_lock(&dev->struct_mutex);
 610         ret = i915_quiescent(dev);
 611         mutex_unlock(&dev->struct_mutex);
 612
 613         return ret;
 614 }
 615
 616 static int i915_batchbuffer(struct drm_device *dev, void *data,
 617                             struct drm_file *file_priv)
 618 {
 619         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 620         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 621         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 622             master_priv->sarea_priv;
 623         drm_i915_batchbuffer_t *batch = data;
 624         int ret;
 625         struct drm_clip_rect *cliprects = NULL;
 626
 627         if (drm_core_check_feature(dev, DRIVER_MODESET))
 628                 return -ENODEV;
 629
 630         if (!dev_priv->dri1.allow_batchbuffer) {
 631                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 632                 return -EINVAL;
 633         }
 634
 635         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 636                         batch->start, batch->used, batch->num_cliprects);
 637
 638         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 639
 640         if (batch->num_cliprects < 0)
 641                 return -EINVAL;
 642
 643         if (batch->num_cliprects) {
 644                 cliprects = kcalloc(batch->num_cliprects,
 645                                     sizeof(struct drm_clip_rect),
 646                                     GFP_KERNEL);
 647                 if (cliprects == NULL)
 648                         return -ENOMEM;
 649
 650                 ret = copy_from_user(cliprects, batch->cliprects,
 651                                      batch->num_cliprects *
 652                                      sizeof(struct drm_clip_rect));
 653                 if (ret != 0) {
 654                         ret = -EFAULT;
 655                         goto fail_free;
 656                 }
 657         }
 658
 659         mutex_lock(&dev->struct_mutex);
 660         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 661         mutex_unlock(&dev->struct_mutex);
 662
 663         if (sarea_priv)
 664                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 665
 666 fail_free:
 667         kfree(cliprects);
 668
 669         return ret;
 670 }
 671
 672 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 673                           struct drm_file *file_priv)
 674 {
 675         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 676         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 677         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 678             master_priv->sarea_priv;
 679         drm_i915_cmdbuffer_t *cmdbuf = data;
 680         struct drm_clip_rect *cliprects = NULL;
 681         void *batch_data;
 682         int ret;
 683
 684         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 685                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 686
 687         if (drm_core_check_feature(dev, DRIVER_MODESET))
 688                 return -ENODEV;
 689
 690         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 691
 692         if (cmdbuf->num_cliprects < 0)
 693                 return -EINVAL;
 694
 695         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 696         if (batch_data == NULL)
 697                 return -ENOMEM;
 698
 699         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 700         if (ret != 0) {
 701                 ret = -EFAULT;
 702                 goto fail_batch_free;
 703         }
 704
 705         if (cmdbuf->num_cliprects) {
 706                 cliprects = kcalloc(cmdbuf->num_cliprects,
 707                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 708                 if (cliprects == NULL) {
 709                         ret = -ENOMEM;
 710                         goto fail_batch_free;
 711                 }
 712
 713                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 714                                      cmdbuf->num_cliprects *
 715                                      sizeof(struct drm_clip_rect));
 716                 if (ret != 0) {
 717                         ret = -EFAULT;
 718                         goto fail_clip_free;
 719                 }
 720         }
 721
 722         mutex_lock(&dev->struct_mutex);
 723         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 724         mutex_unlock(&dev->struct_mutex);
 725         if (ret) {
 726                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 727                 goto fail_clip_free;
 728         }
 729
 730         if (sarea_priv)
 731                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 732
 733 fail_clip_free:
 734         kfree(cliprects);
 735 fail_batch_free:
 736         kfree(batch_data);
 737
 738         return ret;
 739 }
 740
 741 static int i915_emit_irq(struct drm_device * dev)
 742 {
 743         drm_i915_private_t *dev_priv = dev->dev_private;
 744         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 745
 746         i915_kernel_lost_context(dev);
 747
 748         DRM_DEBUG_DRIVER("\n");
 749
 750         dev_priv->dri1.counter++;
 751         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 752                 dev_priv->dri1.counter = 1;
 753         if (master_priv->sarea_priv)
 754                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 755
 756         if (BEGIN_LP_RING(4) == 0) {
 757                 OUT_RING(MI_STORE_DWORD_INDEX);
 758                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 759                 OUT_RING(dev_priv->dri1.counter);
 760                 OUT_RING(MI_USER_INTERRUPT);
 761                 ADVANCE_LP_RING();
 762         }
 763
 764         return dev_priv->dri1.counter;
 765 }
 766
 767 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 768 {
 769         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 770         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 771         int ret = 0;
 772         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 773
 774         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 775                   READ_BREADCRUMB(dev_priv));
 776
 777         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 778                 if (master_priv->sarea_priv)
 779                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 780                 return 0;
 781         }
 782
 783         if (master_priv->sarea_priv)
 784                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 785
 786         if (ring->irq_get(ring)) {
 787                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 788                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 789                 ring->irq_put(ring);
 790         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 791                 ret = -EBUSY;
 792
 793         if (ret == -EBUSY) {
 794                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 795                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 796         }
 797
 798         return ret;
 799 }
 800
 801 /* Needs the lock as it touches the ring.
 802  */
 803 static int i915_irq_emit(struct drm_device *dev, void *data,
 804                          struct drm_file *file_priv)
 805 {
 806         drm_i915_private_t *dev_priv = dev->dev_private;
 807         drm_i915_irq_emit_t *emit = data;
 808         int result;
 809
 810         if (drm_core_check_feature(dev, DRIVER_MODESET))
 811                 return -ENODEV;
 812
 813         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 814                 DRM_ERROR("called with no initialization\n");
 815                 return -EINVAL;
 816         }
 817
 818         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 819
 820         mutex_lock(&dev->struct_mutex);
 821         result = i915_emit_irq(dev);
 822         mutex_unlock(&dev->struct_mutex);
 823
 824         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 825                 DRM_ERROR("copy_to_user\n");
 826                 return -EFAULT;
 827         }
 828
 829         return 0;
 830 }
 831
 832 /* Doesn't need the hardware lock.
 833  */
 834 static int i915_irq_wait(struct drm_device *dev, void *data,
 835                          struct drm_file *file_priv)
 836 {
 837         drm_i915_private_t *dev_priv = dev->dev_private;
 838         drm_i915_irq_wait_t *irqwait = data;
 839
 840         if (drm_core_check_feature(dev, DRIVER_MODESET))
 841                 return -ENODEV;
 842
 843         if (!dev_priv) {
 844                 DRM_ERROR("called with no initialization\n");
 845                 return -EINVAL;
 846         }
 847
 848         return i915_wait_irq(dev, irqwait->irq_seq);
 849 }
 850
 851 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 852                          struct drm_file *file_priv)
 853 {
 854         drm_i915_private_t *dev_priv = dev->dev_private;
 855         drm_i915_vblank_pipe_t *pipe = data;
 856
 857         if (drm_core_check_feature(dev, DRIVER_MODESET))
 858                 return -ENODEV;
 859
 860         if (!dev_priv) {
 861                 DRM_ERROR("called with no initialization\n");
 862                 return -EINVAL;
 863         }
 864
 865         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 866
 867         return 0;
 868 }
 869
 870 /**
 871  * Schedule buffer swap at given vertical blank.
 872  */
 873 static int i915_vblank_swap(struct drm_device *dev, void *data,
 874                      struct drm_file *file_priv)
 875 {
 876         /* The delayed swap mechanism was fundamentally racy, and has been
 877          * removed.  The model was that the client requested a delayed flip/swap
 878          * from the kernel, then waited for vblank before continuing to perform
 879          * rendering.  The problem was that the kernel might wake the client
 880          * up before it dispatched the vblank swap (since the lock has to be
 881          * held while touching the ringbuffer), in which case the client would
 882          * clear and start the next frame before the swap occurred, and
 883          * flicker would occur in addition to likely missing the vblank.
 884          *
 885          * In the absence of this ioctl, userland falls back to a correct path
 886          * of waiting for a vblank, then dispatching the swap on its own.
 887          * Context switching to userland and back is plenty fast enough for
 888          * meeting the requirements of vblank swapping.
 889          */
 890         return -EINVAL;
 891 }
 892
 893 static int i915_flip_bufs(struct drm_device *dev, void *data,
 894                           struct drm_file *file_priv)
 895 {
 896         int ret;
 897
 898         if (drm_core_check_feature(dev, DRIVER_MODESET))
 899                 return -ENODEV;
 900
 901         DRM_DEBUG_DRIVER("%s\n", __func__);
 902
 903         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 904
 905         mutex_lock(&dev->struct_mutex);
 906         ret = i915_dispatch_flip(dev);
 907         mutex_unlock(&dev->struct_mutex);
 908
 909         return ret;
 910 }
 911
 912 static int i915_getparam(struct drm_device *dev, void *data,
 913                          struct drm_file *file_priv)
 914 {
 915         drm_i915_private_t *dev_priv = dev->dev_private;
 916         drm_i915_getparam_t *param = data;
 917         int value;
 918
 919         if (!dev_priv) {
 920                 DRM_ERROR("called with no initialization\n");
 921                 return -EINVAL;
 922         }
 923
 924         switch (param->param) {
 925         case I915_PARAM_IRQ_ACTIVE:
 926                 value = dev->pdev->irq ? 1 : 0;
 927                 break;
 928         case I915_PARAM_ALLOW_BATCHBUFFER:
 929                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 930                 break;
 931         case I915_PARAM_LAST_DISPATCH:
 932                 value = READ_BREADCRUMB(dev_priv);
 933                 break;
 934         case I915_PARAM_CHIPSET_ID:
 935                 value = dev->pci_device;
 936                 break;
 937         case I915_PARAM_HAS_GEM:
 938                 value = 1;
 939                 break;
 940         case I915_PARAM_NUM_FENCES_AVAIL:
 941                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 942                 break;
 943         case I915_PARAM_HAS_OVERLAY:
 944                 value = dev_priv->overlay ? 1 : 0;
 945                 break;
 946         case I915_PARAM_HAS_PAGEFLIPPING:
 947                 value = 1;
 948                 break;
 949         case I915_PARAM_HAS_EXECBUF2:
 950                 /* depends on GEM */
 951                 value = 1;
 952                 break;
 953         case I915_PARAM_HAS_BSD:
 954                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 955                 break;
 956         case I915_PARAM_HAS_BLT:
 957                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 958                 break;
 959         case I915_PARAM_HAS_RELAXED_FENCING:
 960                 value = 1;
 961                 break;
 962         case I915_PARAM_HAS_COHERENT_RINGS:
 963                 value = 1;
 964                 break;
 965         case I915_PARAM_HAS_EXEC_CONSTANTS:
 966                 value = INTEL_INFO(dev)->gen >= 4;
 967                 break;
 968         case I915_PARAM_HAS_RELAXED_DELTA:
 969                 value = 1;
 970                 break;
 971         case I915_PARAM_HAS_GEN7_SOL_RESET:
 972                 value = 1;
 973                 break;
 974         case I915_PARAM_HAS_LLC:
 975                 value = HAS_LLC(dev);
 976                 break;
 977         case I915_PARAM_HAS_ALIASING_PPGTT:
 978                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 979                 break;
 980         case I915_PARAM_HAS_WAIT_TIMEOUT:
 981                 value = 1;
 982                 break;
 983         case I915_PARAM_HAS_SEMAPHORES:
 984                 value = i915_semaphore_is_enabled(dev);
 985                 break;
 986         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 987                 value = 1;
 988                 break;
 989         case I915_PARAM_HAS_SECURE_BATCHES:
 990                 value = capable(CAP_SYS_ADMIN);
 991                 break;
 992         default:
 993                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 994                                  param->param);
 995                 return -EINVAL;
 996         }
 997
 998         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 999                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1000                 return -EFAULT;
1001         }
1002
1003         return 0;
1004 }
1005
1006 static int i915_setparam(struct drm_device *dev, void *data,
1007                          struct drm_file *file_priv)
1008 {
1009         drm_i915_private_t *dev_priv = dev->dev_private;
1010         drm_i915_setparam_t *param = data;
1011
1012         if (!dev_priv) {
1013                 DRM_ERROR("called with no initialization\n");
1014                 return -EINVAL;
1015         }
1016
1017         switch (param->param) {
1018         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1019                 break;
1020         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1021                 break;
1022         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1023                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1024                 break;
1025         case I915_SETPARAM_NUM_USED_FENCES:
1026                 if (param->value > dev_priv->num_fence_regs ||
1027                     param->value < 0)
1028                         return -EINVAL;
1029                 /* Userspace can use first N regs */
1030                 dev_priv->fence_reg_start = param->value;
1031                 break;
1032         default:
1033                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1034                                         param->param);
1035                 return -EINVAL;
1036         }
1037
1038         return 0;
1039 }
1040
1041 static int i915_set_status_page(struct drm_device *dev, void *data,
1042                                 struct drm_file *file_priv)
1043 {
1044         drm_i915_private_t *dev_priv = dev->dev_private;
1045         drm_i915_hws_addr_t *hws = data;
1046         struct intel_ring_buffer *ring;
1047
1048         if (drm_core_check_feature(dev, DRIVER_MODESET))
1049                 return -ENODEV;
1050
1051         if (!I915_NEED_GFX_HWS(dev))
1052                 return -EINVAL;
1053
1054         if (!dev_priv) {
1055                 DRM_ERROR("called with no initialization\n");
1056                 return -EINVAL;
1057         }
1058
1059         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1060                 WARN(1, "tried to set status page when mode setting active\n");
1061                 return 0;
1062         }
1063
1064         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1065
1066         ring = LP_RING(dev_priv);
1067         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1068
1069         dev_priv->dri1.gfx_hws_cpu_addr =
1070                 ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
1071         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1072                 i915_dma_cleanup(dev);
1073                 ring->status_page.gfx_addr = 0;
1074                 DRM_ERROR("can not ioremap virtual address for"
1075                                 " G33 hw status page\n");
1076                 return -ENOMEM;
1077         }
1078
1079         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1080         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1081
1082         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1083                          ring->status_page.gfx_addr);
1084         DRM_DEBUG_DRIVER("load hws at %p\n",
1085                          ring->status_page.page_addr);
1086         return 0;
1087 }
1088
1089 static int i915_get_bridge_dev(struct drm_device *dev)
1090 {
1091         struct drm_i915_private *dev_priv = dev->dev_private;
1092
1093         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1094         if (!dev_priv->bridge_dev) {
1095                 DRM_ERROR("bridge device not found\n");
1096                 return -1;
1097         }
1098         return 0;
1099 }
1100
1101 #define MCHBAR_I915 0x44
1102 #define MCHBAR_I965 0x48
1103 #define MCHBAR_SIZE (4*4096)
1104
1105 #define DEVEN_REG 0x54
1106 #define   DEVEN_MCHBAR_EN (1 << 28)
1107
1108 /* Allocate space for the MCH regs if needed, return nonzero on error */
1109 static int
1110 intel_alloc_mchbar_resource(struct drm_device *dev)
1111 {
1112         drm_i915_private_t *dev_priv = dev->dev_private;
1113         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1114         u32 temp_lo, temp_hi = 0;
1115         u64 mchbar_addr;
1116         int ret;
1117
1118         if (INTEL_INFO(dev)->gen >= 4)
1119                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1120         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1121         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1122
1123         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1124 #ifdef CONFIG_PNP
1125         if (mchbar_addr &&
1126             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1127                 return 0;
1128 #endif
1129
1130         /* Get some space for it */
1131         dev_priv->mch_res.name = "i915 MCHBAR";
1132         dev_priv->mch_res.flags = IORESOURCE_MEM;
1133         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1134                                      &dev_priv->mch_res,
1135                                      MCHBAR_SIZE, MCHBAR_SIZE,
1136                                      PCIBIOS_MIN_MEM,
1137                                      0, pcibios_align_resource,
1138                                      dev_priv->bridge_dev);
1139         if (ret) {
1140                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1141                 dev_priv->mch_res.start = 0;
1142                 return ret;
1143         }
1144
1145         if (INTEL_INFO(dev)->gen >= 4)
1146                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1147                                        upper_32_bits(dev_priv->mch_res.start));
1148
1149         pci_write_config_dword(dev_priv->bridge_dev, reg,
1150                                lower_32_bits(dev_priv->mch_res.start));
1151         return 0;
1152 }
1153
1154 /* Setup MCHBAR if possible, return true if we should disable it again */
1155 static void
1156 intel_setup_mchbar(struct drm_device *dev)
1157 {
1158         drm_i915_private_t *dev_priv = dev->dev_private;
1159         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1160         u32 temp;
1161         bool enabled;
1162
1163         dev_priv->mchbar_need_disable = false;
1164
1165         if (IS_I915G(dev) || IS_I915GM(dev)) {
1166                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1167                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1168         } else {
1169                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1170                 enabled = temp & 1;
1171         }
1172
1173         /* If it's already enabled, don't have to do anything */
1174         if (enabled)
1175                 return;
1176
1177         if (intel_alloc_mchbar_resource(dev))
1178                 return;
1179
1180         dev_priv->mchbar_need_disable = true;
1181
1182         /* Space is allocated or reserved, so enable it. */
1183         if (IS_I915G(dev) || IS_I915GM(dev)) {
1184                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1185                                        temp | DEVEN_MCHBAR_EN);
1186         } else {
1187                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1188                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1189         }
1190 }
1191
1192 static void
1193 intel_teardown_mchbar(struct drm_device *dev)
1194 {
1195         drm_i915_private_t *dev_priv = dev->dev_private;
1196         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1197         u32 temp;
1198
1199         if (dev_priv->mchbar_need_disable) {
1200                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1201                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1202                         temp &= ~DEVEN_MCHBAR_EN;
1203                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1204                 } else {
1205                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1206                         temp &= ~1;
1207                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1208                 }
1209         }
1210
1211         if (dev_priv->mch_res.start)
1212                 release_resource(&dev_priv->mch_res);
1213 }
1214
1215 /* true = enable decode, false = disable decoder */
1216 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1217 {
1218         struct drm_device *dev = cookie;
1219
1220         intel_modeset_vga_set_state(dev, state);
1221         if (state)
1222                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1223                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1224         else
1225                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1226 }
1227
1228 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1229 {
1230         struct drm_device *dev = pci_get_drvdata(pdev);
1231         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1232         if (state == VGA_SWITCHEROO_ON) {
1233                 pr_info("switched on\n");
1234                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1235                 /* i915 resume handler doesn't set to D0 */
1236                 pci_set_power_state(dev->pdev, PCI_D0);
1237                 i915_resume(dev);
1238                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1239         } else {
1240                 pr_err("switched off\n");
1241                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1242                 i915_suspend(dev, pmm);
1243                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1244         }
1245 }
1246
1247 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1248 {
1249         struct drm_device *dev = pci_get_drvdata(pdev);
1250         bool can_switch;
1251
1252         spin_lock(&dev->count_lock);
1253         can_switch = (dev->open_count == 0);
1254         spin_unlock(&dev->count_lock);
1255         return can_switch;
1256 }
1257
1258 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1259         .set_gpu_state = i915_switcheroo_set_state,
1260         .reprobe = NULL,
1261         .can_switch = i915_switcheroo_can_switch,
1262 };
1263
1264 static int i915_load_modeset_init(struct drm_device *dev)
1265 {
1266         struct drm_i915_private *dev_priv = dev->dev_private;
1267         int ret;
1268
1269         ret = intel_parse_bios(dev);
1270         if (ret)
1271                 DRM_INFO("failed to find VBIOS tables\n");
1272
1273         /* If we have > 1 VGA cards, then we need to arbitrate access
1274          * to the common VGA resources.
1275          *
1276          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1277          * then we do not take part in VGA arbitration and the
1278          * vga_client_register() fails with -ENODEV.
1279          */
1280         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1281         if (ret && ret != -ENODEV)
1282                 goto out;
1283
1284         intel_register_dsm_handler();
1285
1286         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1287         if (ret)
1288                 goto cleanup_vga_client;
1289
1290         /* Initialise stolen first so that we may reserve preallocated
1291          * objects for the BIOS to KMS transition.
1292          */
1293         ret = i915_gem_init_stolen(dev);
1294         if (ret)
1295                 goto cleanup_vga_switcheroo;
1296
1297         intel_modeset_init(dev);
1298
1299         ret = i915_gem_init(dev);
1300         if (ret)
1301                 goto cleanup_gem_stolen;
1302
1303         intel_modeset_gem_init(dev);
1304
1305         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1306
1307         ret = drm_irq_install(dev);
1308         if (ret)
1309                 goto cleanup_gem;
1310
1311         /* Always safe in the mode setting case. */
1312         /* FIXME: do pre/post-mode set stuff in core KMS code */
1313         dev->vblank_disable_allowed = 1;
1314
1315         ret = intel_fbdev_init(dev);
1316         if (ret)
1317                 goto cleanup_irq;
1318
1319         drm_kms_helper_poll_init(dev);
1320
1321         /* We're off and running w/KMS */
1322         dev_priv->mm.suspended = 0;
1323
1324         return 0;
1325
1326 cleanup_irq:
1327         drm_irq_uninstall(dev);
1328 cleanup_gem:
1329         mutex_lock(&dev->struct_mutex);
1330         i915_gem_cleanup_ringbuffer(dev);
1331         mutex_unlock(&dev->struct_mutex);
1332         i915_gem_cleanup_aliasing_ppgtt(dev);
1333 cleanup_gem_stolen:
1334         i915_gem_cleanup_stolen(dev);
1335 cleanup_vga_switcheroo:
1336         vga_switcheroo_unregister_client(dev->pdev);
1337 cleanup_vga_client:
1338         vga_client_register(dev->pdev, NULL, NULL, NULL);
1339 out:
1340         return ret;
1341 }
1342
1343 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1344 {
1345         struct drm_i915_master_private *master_priv;
1346
1347         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1348         if (!master_priv)
1349                 return -ENOMEM;
1350
1351         master->driver_priv = master_priv;
1352         return 0;
1353 }
1354
1355 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1356 {
1357         struct drm_i915_master_private *master_priv = master->driver_priv;
1358
1359         if (!master_priv)
1360                 return;
1361
1362         kfree(master_priv);
1363
1364         master->driver_priv = NULL;
1365 }
1366
1367 static void
1368 i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1369                 unsigned long size)
1370 {
1371         dev_priv->mm.gtt_mtrr = -1;
1372
1373 #if defined(CONFIG_X86_PAT)
1374         if (cpu_has_pat)
1375                 return;
1376 #endif
1377
1378         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1379          * one would think, because the kernel disables PAT on first
1380          * generation Core chips because WC PAT gets overridden by a UC
1381          * MTRR if present.  Even if a UC MTRR isn't present.
1382          */
1383         dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
1384         if (dev_priv->mm.gtt_mtrr < 0) {
1385                 DRM_INFO("MTRR allocation failed.  Graphics "
1386                          "performance may suffer.\n");
1387         }
1388 }
1389
1390 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1391 {
1392         struct apertures_struct *ap;
1393         struct pci_dev *pdev = dev_priv->dev->pdev;
1394         bool primary;
1395
1396         ap = alloc_apertures(1);
1397         if (!ap)
1398                 return;
1399
1400         ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
1401         ap->ranges[0].size =
1402                 dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1403         primary =
1404                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1405
1406         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1407
1408         kfree(ap);
1409 }
1410
1411 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1412 {
1413         const struct intel_device_info *info = dev_priv->info;
1414
1415 #define DEV_INFO_FLAG(name) info->name ? #name "," : ""
1416 #define DEV_INFO_SEP ,
1417         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
1418                          "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
1419                          info->gen,
1420                          dev_priv->dev->pdev->device,
1421                          DEV_INFO_FLAGS);
1422 #undef DEV_INFO_FLAG
1423 #undef DEV_INFO_SEP
1424 }
1425
1426 /**
1427  * i915_driver_load - setup chip and create an initial config
1428  * @dev: DRM device
1429  * @flags: startup flags
1430  *
1431  * The driver load routine has to do several things:
1432  *   - drive output discovery via intel_modeset_init()
1433  *   - initialize the memory manager
1434  *   - allocate initial config memory
1435  *   - setup the DRM framebuffer with the allocated memory
1436  */
1437 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1438 {
1439         struct drm_i915_private *dev_priv;
1440         struct intel_device_info *info;
1441         int ret = 0, mmio_bar, mmio_size;
1442         uint32_t aperture_size;
1443
1444         info = (struct intel_device_info *) flags;
1445
1446         /* Refuse to load on gen6+ without kms enabled. */
1447         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1448                 return -ENODEV;
1449
1450         /* i915 has 4 more counters */
1451         dev->counters += 4;
1452         dev->types[6] = _DRM_STAT_IRQ;
1453         dev->types[7] = _DRM_STAT_PRIMARY;
1454         dev->types[8] = _DRM_STAT_SECONDARY;
1455         dev->types[9] = _DRM_STAT_DMA;
1456
1457         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1458         if (dev_priv == NULL)
1459                 return -ENOMEM;
1460
1461         dev->dev_private = (void *)dev_priv;
1462         dev_priv->dev = dev;
1463         dev_priv->info = info;
1464
1465         i915_dump_device_info(dev_priv);
1466
1467         if (i915_get_bridge_dev(dev)) {
1468                 ret = -EIO;
1469                 goto free_priv;
1470         }
1471
1472         ret = i915_gem_gtt_init(dev);
1473         if (ret)
1474                 goto put_bridge;
1475
1476         if (drm_core_check_feature(dev, DRIVER_MODESET))
1477                 i915_kick_out_firmware_fb(dev_priv);
1478
1479         pci_set_master(dev->pdev);
1480
1481         /* overlay on gen2 is broken and can't address above 1G */
1482         if (IS_GEN2(dev))
1483                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1484
1485         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1486          * using 32bit addressing, overwriting memory if HWS is located
1487          * above 4GB.
1488          *
1489          * The documentation also mentions an issue with undefined
1490          * behaviour if any general state is accessed within a page above 4GB,
1491          * which also needs to be handled carefully.
1492          */
1493         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1494                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1495
1496         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1497         /* Before gen4, the registers and the GTT are behind different BARs.
1498          * However, from gen4 onwards, the registers and the GTT are shared
1499          * in the same BAR, so we want to restrict this ioremap from
1500          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1501          * the register BAR remains the same size for all the earlier
1502          * generations up to Ironlake.
1503          */
1504         if (info->gen < 5)
1505                 mmio_size = 512*1024;
1506         else
1507                 mmio_size = 2*1024*1024;
1508
1509         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1510         if (!dev_priv->regs) {
1511                 DRM_ERROR("failed to map registers\n");
1512                 ret = -EIO;
1513                 goto put_gmch;
1514         }
1515
1516         aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1517         dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
1518
1519         dev_priv->mm.gtt_mapping =
1520                 io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
1521                                      aperture_size);
1522         if (dev_priv->mm.gtt_mapping == NULL) {
1523                 ret = -EIO;
1524                 goto out_rmmap;
1525         }
1526
1527         i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
1528                         aperture_size);
1529
1530         /* The i915 workqueue is primarily used for batched retirement of
1531          * requests (and thus managing bo) once the task has been completed
1532          * by the GPU. i915_gem_retire_requests() is called directly when we
1533          * need high-priority retirement, such as waiting for an explicit
1534          * bo.
1535          *
1536          * It is also used for periodic low-priority events, such as
1537          * idle-timers and recording error state.
1538          *
1539          * All tasks on the workqueue are expected to acquire the dev mutex
1540          * so there is no point in running more than one instance of the
1541          * workqueue at any time.  Use an ordered one.
1542          */
1543         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1544         if (dev_priv->wq == NULL) {
1545                 DRM_ERROR("Failed to create our workqueue.\n");
1546                 ret = -ENOMEM;
1547                 goto out_mtrrfree;
1548         }
1549
1550         /* This must be called before any calls to HAS_PCH_* */
1551         intel_detect_pch(dev);
1552
1553         intel_irq_init(dev);
1554         intel_gt_init(dev);
1555
1556         /* Try to make sure MCHBAR is enabled before poking at it */
1557         intel_setup_mchbar(dev);
1558         intel_setup_gmbus(dev);
1559         intel_opregion_setup(dev);
1560
1561         intel_setup_bios(dev);
1562
1563         i915_gem_load(dev);
1564
1565         /* On the 945G/GM, the chipset reports the MSI capability on the
1566          * integrated graphics even though the support isn't actually there
1567          * according to the published specs.  It doesn't appear to function
1568          * correctly in testing on 945G.
1569          * This may be a side effect of MSI having been made available for PEG
1570          * and the registers being closely associated.
1571          *
1572          * According to chipset errata, on the 965GM, MSI interrupts may
1573          * be lost or delayed, but we use them anyways to avoid
1574          * stuck interrupts on some machines.
1575          */
1576         if (!IS_I945G(dev) && !IS_I945GM(dev))
1577                 pci_enable_msi(dev->pdev);
1578
1579         spin_lock_init(&dev_priv->irq_lock);
1580         spin_lock_init(&dev_priv->error_lock);
1581         spin_lock_init(&dev_priv->rps.lock);
1582         spin_lock_init(&dev_priv->dpio_lock);
1583
1584         mutex_init(&dev_priv->rps.hw_lock);
1585
1586         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1587                 dev_priv->num_pipe = 3;
1588         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1589                 dev_priv->num_pipe = 2;
1590         else
1591                 dev_priv->num_pipe = 1;
1592
1593         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1594         if (ret)
1595                 goto out_gem_unload;
1596
1597         /* Start out suspended */
1598         dev_priv->mm.suspended = 1;
1599
1600         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1601                 ret = i915_load_modeset_init(dev);
1602                 if (ret < 0) {
1603                         DRM_ERROR("failed to init modeset\n");
1604                         goto out_gem_unload;
1605                 }
1606         }
1607
1608         i915_setup_sysfs(dev);
1609
1610         /* Must be done after probing outputs */
1611         intel_opregion_init(dev);
1612         acpi_video_register();
1613
1614         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1615                     (unsigned long) dev);
1616
1617         if (IS_GEN5(dev))
1618                 intel_gpu_ips_init(dev_priv);
1619
1620         return 0;
1621
1622 out_gem_unload:
1623         if (dev_priv->mm.inactive_shrinker.shrink)
1624                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1625
1626         if (dev->pdev->msi_enabled)
1627                 pci_disable_msi(dev->pdev);
1628
1629         intel_teardown_gmbus(dev);
1630         intel_teardown_mchbar(dev);
1631         destroy_workqueue(dev_priv->wq);
1632 out_mtrrfree:
1633         if (dev_priv->mm.gtt_mtrr >= 0) {
1634                 mtrr_del(dev_priv->mm.gtt_mtrr,
1635                          dev_priv->mm.gtt_base_addr,
1636                          aperture_size);
1637                 dev_priv->mm.gtt_mtrr = -1;
1638         }
1639         io_mapping_free(dev_priv->mm.gtt_mapping);
1640 out_rmmap:
1641         pci_iounmap(dev->pdev, dev_priv->regs);
1642 put_gmch:
1643         i915_gem_gtt_fini(dev);
1644 put_bridge:
1645         pci_dev_put(dev_priv->bridge_dev);
1646 free_priv:
1647         kfree(dev_priv);
1648         return ret;
1649 }
1650
1651 int i915_driver_unload(struct drm_device *dev)
1652 {
1653         struct drm_i915_private *dev_priv = dev->dev_private;
1654         int ret;
1655
1656         intel_gpu_ips_teardown();
1657
1658         i915_teardown_sysfs(dev);
1659
1660         if (dev_priv->mm.inactive_shrinker.shrink)
1661                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1662
1663         mutex_lock(&dev->struct_mutex);
1664         ret = i915_gpu_idle(dev);
1665         if (ret)
1666                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1667         i915_gem_retire_requests(dev);
1668         mutex_unlock(&dev->struct_mutex);
1669
1670         /* Cancel the retire work handler, which should be idle now. */
1671         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1672
1673         io_mapping_free(dev_priv->mm.gtt_mapping);
1674         if (dev_priv->mm.gtt_mtrr >= 0) {
1675                 mtrr_del(dev_priv->mm.gtt_mtrr,
1676                          dev_priv->mm.gtt_base_addr,
1677                          dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1678                 dev_priv->mm.gtt_mtrr = -1;
1679         }
1680
1681         acpi_video_unregister();
1682
1683         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1684                 intel_fbdev_fini(dev);
1685                 intel_modeset_cleanup(dev);
1686                 cancel_work_sync(&dev_priv->console_resume_work);
1687
1688                 /*
1689                  * free the memory space allocated for the child device
1690                  * config parsed from VBT
1691                  */
1692                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1693                         kfree(dev_priv->child_dev);
1694                         dev_priv->child_dev = NULL;
1695                         dev_priv->child_dev_num = 0;
1696                 }
1697
1698                 vga_switcheroo_unregister_client(dev->pdev);
1699                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1700         }
1701
1702         /* Free error state after interrupts are fully disabled. */
1703         del_timer_sync(&dev_priv->hangcheck_timer);
1704         cancel_work_sync(&dev_priv->error_work);
1705         i915_destroy_error_state(dev);
1706
1707         if (dev->pdev->msi_enabled)
1708                 pci_disable_msi(dev->pdev);
1709
1710         intel_opregion_fini(dev);
1711
1712         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1713                 /* Flush any outstanding unpin_work. */
1714                 flush_workqueue(dev_priv->wq);
1715
1716                 mutex_lock(&dev->struct_mutex);
1717                 i915_gem_free_all_phys_object(dev);
1718                 i915_gem_cleanup_ringbuffer(dev);
1719                 i915_gem_context_fini(dev);
1720                 mutex_unlock(&dev->struct_mutex);
1721                 i915_gem_cleanup_aliasing_ppgtt(dev);
1722                 i915_gem_cleanup_stolen(dev);
1723                 drm_mm_takedown(&dev_priv->mm.stolen);
1724
1725                 intel_cleanup_overlay(dev);
1726
1727                 if (!I915_NEED_GFX_HWS(dev))
1728                         i915_free_hws(dev);
1729         }
1730
1731         if (dev_priv->regs != NULL)
1732                 pci_iounmap(dev->pdev, dev_priv->regs);
1733
1734         intel_teardown_gmbus(dev);
1735         intel_teardown_mchbar(dev);
1736
1737         destroy_workqueue(dev_priv->wq);
1738
1739         pci_dev_put(dev_priv->bridge_dev);
1740         kfree(dev->dev_private);
1741
1742         return 0;
1743 }
1744
1745 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1746 {
1747         struct drm_i915_file_private *file_priv;
1748
1749         DRM_DEBUG_DRIVER("\n");
1750         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
1751         if (!file_priv)
1752                 return -ENOMEM;
1753
1754         file->driver_priv = file_priv;
1755
1756         spin_lock_init(&file_priv->mm.lock);
1757         INIT_LIST_HEAD(&file_priv->mm.request_list);
1758
1759         idr_init(&file_priv->context_idr);
1760
1761         return 0;
1762 }
1763
1764 /**
1765  * i915_driver_lastclose - clean up after all DRM clients have exited
1766  * @dev: DRM device
1767  *
1768  * Take care of cleaning up after all DRM clients have exited.  In the
1769  * mode setting case, we want to restore the kernel's initial mode (just
1770  * in case the last client left us in a bad state).
1771  *
1772  * Additionally, in the non-mode setting case, we'll tear down the GTT
1773  * and DMA structures, since the kernel won't be using them, and clea
1774  * up any GEM state.
1775  */
1776 void i915_driver_lastclose(struct drm_device * dev)
1777 {
1778         drm_i915_private_t *dev_priv = dev->dev_private;
1779
1780         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1781          * goes right around and calls lastclose. Check for this and don't clean
1782          * up anything. */
1783         if (!dev_priv)
1784                 return;
1785
1786         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1787                 intel_fb_restore_mode(dev);
1788                 vga_switcheroo_process_delayed_switch();
1789                 return;
1790         }
1791
1792         i915_gem_lastclose(dev);
1793
1794         i915_dma_cleanup(dev);
1795 }
1796
1797 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1798 {
1799         i915_gem_context_close(dev, file_priv);
1800         i915_gem_release(dev, file_priv);
1801 }
1802
1803 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1804 {
1805         struct drm_i915_file_private *file_priv = file->driver_priv;
1806
1807         kfree(file_priv);
1808 }
1809
1810 struct drm_ioctl_desc i915_ioctls[] = {
1811         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1812         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1813         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1814         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1815         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1816         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1817         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1818         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1819         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1820         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1821         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1822         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1823         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1824         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1825         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1826         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1827         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1828         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1829         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1830         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1831         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1832         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1833         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1834         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1835         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1836         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1837         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1838         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1839         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1840         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1841         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1842         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1843         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1844         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1845         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1846         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1847         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1848         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1849         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1850         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1851         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1852         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1853         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1854         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1855         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1856         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1857         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1858         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1859 };
1860
1861 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1862
1863 /*
1864  * This is really ugly: Because old userspace abused the linux agp interface to
1865  * manage the gtt, we need to claim that all intel devices are agp.  For
1866  * otherwise the drm core refuses to initialize the agp support code.
1867  */
1868 int i915_driver_device_is_agp(struct drm_device * dev)
1869 {
1870         return 1;
1871 }