drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include "xhci.h"
  69
  70 /*
  71  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  72  * address of the TRB.
  73  */
  74 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  75                 union xhci_trb *trb)
  76 {
  77         unsigned long segment_offset;
  78
  79         if (!seg || !trb || trb < seg->trbs)
  80                 return 0;
  81         /* offset in TRBs */
  82         segment_offset = trb - seg->trbs;
  83         if (segment_offset > TRBS_PER_SEGMENT)
  84                 return 0;
  85         return seg->dma + (segment_offset * sizeof(*trb));
  86 }
  87
  88 /* Does this link TRB point to the first segment in a ring,
  89  * or was the previous TRB the last TRB on the last segment in the ERST?
  90  */
  91 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  92                 struct xhci_segment *seg, union xhci_trb *trb)
  93 {
  94         if (ring == xhci->event_ring)
  95                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
  96                         (seg->next == xhci->event_ring->first_seg);
  97         else
  98                 return trb->link.control & LINK_TOGGLE;
  99 }
 100
 101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 102  * segment?  I.e. would the updated event TRB pointer step off the end of the
 103  * event seg?
 104  */
 105 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 106                 struct xhci_segment *seg, union xhci_trb *trb)
 107 {
 108         if (ring == xhci->event_ring)
 109                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 110         else
 111                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 112 }
 113
 114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 115  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 116  * effect the ring dequeue or enqueue pointers.
 117  */
 118 static void next_trb(struct xhci_hcd *xhci,
 119                 struct xhci_ring *ring,
 120                 struct xhci_segment **seg,
 121                 union xhci_trb **trb)
 122 {
 123         if (last_trb(xhci, ring, *seg, *trb)) {
 124                 *seg = (*seg)->next;
 125                 *trb = ((*seg)->trbs);
 126         } else {
 127                 *trb = (*trb)++;
 128         }
 129 }
 130
 131 /*
 132  * See Cycle bit rules. SW is the consumer for the event ring only.
 133  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 134  */
 135 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 136 {
 137         union xhci_trb *next = ++(ring->dequeue);
 138         unsigned long long addr;
 139
 140         ring->deq_updates++;
 141         /* Update the dequeue pointer further if that was a link TRB or we're at
 142          * the end of an event ring segment (which doesn't have link TRBS)
 143          */
 144         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 145                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 146                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 147                         if (!in_interrupt())
 148                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 149                                                 ring,
 150                                                 (unsigned int) ring->cycle_state);
 151                 }
 152                 ring->deq_seg = ring->deq_seg->next;
 153                 ring->dequeue = ring->deq_seg->trbs;
 154                 next = ring->dequeue;
 155         }
 156         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 157         if (ring == xhci->event_ring)
 158                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 159         else if (ring == xhci->cmd_ring)
 160                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 161         else
 162                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 163 }
 164
 165 /*
 166  * See Cycle bit rules. SW is the consumer for the event ring only.
 167  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 168  *
 169  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 170  * chain bit is set), then set the chain bit in all the following link TRBs.
 171  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 172  * have their chain bit cleared (so that each Link TRB is a separate TD).
 173  *
 174  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 175  * set, but other sections talk about dealing with the chain bit set.  This was
 176  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 177  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 178  */
 179 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 180 {
 181         u32 chain;
 182         union xhci_trb *next;
 183         unsigned long long addr;
 184
 185         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 186         next = ++(ring->enqueue);
 187
 188         ring->enq_updates++;
 189         /* Update the dequeue pointer further if that was a link TRB or we're at
 190          * the end of an event ring segment (which doesn't have link TRBS)
 191          */
 192         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 193                 if (!consumer) {
 194                         if (ring != xhci->event_ring) {
 195                                 /* If we're not dealing with 0.95 hardware,
 196                                  * carry over the chain bit of the previous TRB
 197                                  * (which may mean the chain bit is cleared).
 198                                  */
 199                                 if (!xhci_link_trb_quirk(xhci)) {
 200                                         next->link.control &= ~TRB_CHAIN;
 201                                         next->link.control |= chain;
 202                                 }
 203                                 /* Give this link TRB to the hardware */
 204                                 wmb();
 205                                 if (next->link.control & TRB_CYCLE)
 206                                         next->link.control &= (u32) ~TRB_CYCLE;
 207                                 else
 208                                         next->link.control |= (u32) TRB_CYCLE;
 209                         }
 210                         /* Toggle the cycle bit after the last ring segment. */
 211                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 212                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 213                                 if (!in_interrupt())
 214                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 215                                                         ring,
 216                                                         (unsigned int) ring->cycle_state);
 217                         }
 218                 }
 219                 ring->enq_seg = ring->enq_seg->next;
 220                 ring->enqueue = ring->enq_seg->trbs;
 221                 next = ring->enqueue;
 222         }
 223         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 224         if (ring == xhci->event_ring)
 225                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 226         else if (ring == xhci->cmd_ring)
 227                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 228         else
 229                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 230 }
 231
 232 /*
 233  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 234  * above.
 235  * FIXME: this would be simpler and faster if we just kept track of the number
 236  * of free TRBs in a ring.
 237  */
 238 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 239                 unsigned int num_trbs)
 240 {
 241         int i;
 242         union xhci_trb *enq = ring->enqueue;
 243         struct xhci_segment *enq_seg = ring->enq_seg;
 244
 245         /* Check if ring is empty */
 246         if (enq == ring->dequeue)
 247                 return 1;
 248         /* Make sure there's an extra empty TRB available */
 249         for (i = 0; i <= num_trbs; ++i) {
 250                 if (enq == ring->dequeue)
 251                         return 0;
 252                 enq++;
 253                 while (last_trb(xhci, ring, enq_seg, enq)) {
 254                         enq_seg = enq_seg->next;
 255                         enq = enq_seg->trbs;
 256                 }
 257         }
 258         return 1;
 259 }
 260
 261 void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
 262 {
 263         u64 temp;
 264         dma_addr_t deq;
 265
 266         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
 267                         xhci->event_ring->dequeue);
 268         if (deq == 0 && !in_interrupt())
 269                 xhci_warn(xhci, "WARN something wrong with SW event ring "
 270                                 "dequeue ptr.\n");
 271         /* Update HC event ring dequeue pointer */
 272         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 273         temp &= ERST_PTR_MASK;
 274         /* Don't clear the EHB bit (which is RW1C) because
 275          * there might be more events to service.
 276          */
 277         temp &= ~ERST_EHB;
 278         xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n");
 279         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
 280                         &xhci->ir_set->erst_dequeue);
 281 }
 282
 283 /* Ring the host controller doorbell after placing a command on the ring */
 284 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 285 {
 286         u32 temp;
 287
 288         xhci_dbg(xhci, "// Ding dong!\n");
 289         temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
 290         xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
 291         /* Flush PCI posted writes */
 292         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 293 }
 294
 295 static void ring_ep_doorbell(struct xhci_hcd *xhci,
 296                 unsigned int slot_id,
 297                 unsigned int ep_index)
 298 {
 299         struct xhci_ring *ep_ring;
 300         u32 field;
 301         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 302
 303         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
 304         /* Don't ring the doorbell for this endpoint if there are pending
 305          * cancellations because the we don't want to interrupt processing.
 306          */
 307         if (!ep_ring->cancels_pending && !(ep_ring->state & SET_DEQ_PENDING)
 308                         && !(ep_ring->state & EP_HALTED)) {
 309                 field = xhci_readl(xhci, db_addr) & DB_MASK;
 310                 xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
 311                 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
 312                  * isn't time-critical and we shouldn't make the CPU wait for
 313                  * the flush.
 314                  */
 315                 xhci_readl(xhci, db_addr);
 316         }
 317 }
 318
 319 /*
 320  * Find the segment that trb is in.  Start searching in start_seg.
 321  * If we must move past a segment that has a link TRB with a toggle cycle state
 322  * bit set, then we will toggle the value pointed at by cycle_state.
 323  */
 324 static struct xhci_segment *find_trb_seg(
 325                 struct xhci_segment *start_seg,
 326                 union xhci_trb  *trb, int *cycle_state)
 327 {
 328         struct xhci_segment *cur_seg = start_seg;
 329         struct xhci_generic_trb *generic_trb;
 330
 331         while (cur_seg->trbs > trb ||
 332                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 333                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 334                 if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
 335                                 (generic_trb->field[3] & LINK_TOGGLE))
 336                         *cycle_state = ~(*cycle_state) & 0x1;
 337                 cur_seg = cur_seg->next;
 338                 if (cur_seg == start_seg)
 339                         /* Looped over the entire list.  Oops! */
 340                         return 0;
 341         }
 342         return cur_seg;
 343 }
 344
 345 /*
 346  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 347  * Record the new state of the xHC's endpoint ring dequeue segment,
 348  * dequeue pointer, and new consumer cycle state in state.
 349  * Update our internal representation of the ring's dequeue pointer.
 350  *
 351  * We do this in three jumps:
 352  *  - First we update our new ring state to be the same as when the xHC stopped.
 353  *  - Then we traverse the ring to find the segment that contains
 354  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 355  *    any link TRBs with the toggle cycle bit set.
 356  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 357  *    if we've moved it past a link TRB with the toggle cycle bit set.
 358  */
 359 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 360                 unsigned int slot_id, unsigned int ep_index,
 361                 struct xhci_td *cur_td, struct xhci_dequeue_state *state)
 362 {
 363         struct xhci_virt_device *dev = xhci->devs[slot_id];
 364         struct xhci_ring *ep_ring = dev->ep_rings[ep_index];
 365         struct xhci_generic_trb *trb;
 366         struct xhci_ep_ctx *ep_ctx;
 367         dma_addr_t addr;
 368
 369         state->new_cycle_state = 0;
 370         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 371         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 372                         ep_ring->stopped_trb,
 373                         &state->new_cycle_state);
 374         if (!state->new_deq_seg)
 375                 BUG();
 376         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 377         xhci_dbg(xhci, "Finding endpoint context\n");
 378         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 379         state->new_cycle_state = 0x1 & ep_ctx->deq;
 380
 381         state->new_deq_ptr = cur_td->last_trb;
 382         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 383         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 384                         state->new_deq_ptr,
 385                         &state->new_cycle_state);
 386         if (!state->new_deq_seg)
 387                 BUG();
 388
 389         trb = &state->new_deq_ptr->generic;
 390         if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
 391                                 (trb->field[3] & LINK_TOGGLE))
 392                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 393         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 394
 395         /* Don't update the ring cycle state for the producer (us). */
 396         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 397                         state->new_deq_seg);
 398         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 399         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 400                         (unsigned long long) addr);
 401         xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n");
 402         ep_ring->dequeue = state->new_deq_ptr;
 403         ep_ring->deq_seg = state->new_deq_seg;
 404 }
 405
 406 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 407                 struct xhci_td *cur_td)
 408 {
 409         struct xhci_segment *cur_seg;
 410         union xhci_trb *cur_trb;
 411
 412         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 413                         true;
 414                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 415                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 416                                 TRB_TYPE(TRB_LINK)) {
 417                         /* Unchain any chained Link TRBs, but
 418                          * leave the pointers intact.
 419                          */
 420                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 421                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 422                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 423                                         "in seg %p (0x%llx dma)\n",
 424                                         cur_trb,
 425                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 426                                         cur_seg,
 427                                         (unsigned long long)cur_seg->dma);
 428                 } else {
 429                         cur_trb->generic.field[0] = 0;
 430                         cur_trb->generic.field[1] = 0;
 431                         cur_trb->generic.field[2] = 0;
 432                         /* Preserve only the cycle bit of this TRB */
 433                         cur_trb->generic.field[3] &= TRB_CYCLE;
 434                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 435                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 436                                         "in seg %p (0x%llx dma)\n",
 437                                         cur_trb,
 438                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 439                                         cur_seg,
 440                                         (unsigned long long)cur_seg->dma);
 441                 }
 442                 if (cur_trb == cur_td->last_trb)
 443                         break;
 444         }
 445 }
 446
 447 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 448                 unsigned int ep_index, struct xhci_segment *deq_seg,
 449                 union xhci_trb *deq_ptr, u32 cycle_state);
 450
 451 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 452                 struct xhci_ring *ep_ring, unsigned int slot_id,
 453                 unsigned int ep_index, struct xhci_dequeue_state *deq_state)
 454 {
 455         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 456                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 457                         deq_state->new_deq_seg,
 458                         (unsigned long long)deq_state->new_deq_seg->dma,
 459                         deq_state->new_deq_ptr,
 460                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 461                         deq_state->new_cycle_state);
 462         queue_set_tr_deq(xhci, slot_id, ep_index,
 463                         deq_state->new_deq_seg,
 464                         deq_state->new_deq_ptr,
 465                         (u32) deq_state->new_cycle_state);
 466         /* Stop the TD queueing code from ringing the doorbell until
 467          * this command completes.  The HC won't set the dequeue pointer
 468          * if the ring is running, and ringing the doorbell starts the
 469          * ring running.
 470          */
 471         ep_ring->state |= SET_DEQ_PENDING;
 472 }
 473
 474 /*
 475  * When we get a command completion for a Stop Endpoint Command, we need to
 476  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 477  *
 478  *  1. If the HW was in the middle of processing the TD that needs to be
 479  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 480  *     in the TD with a Set Dequeue Pointer Command.
 481  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 482  *     bit cleared) so that the HW will skip over them.
 483  */
 484 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 485                 union xhci_trb *trb)
 486 {
 487         unsigned int slot_id;
 488         unsigned int ep_index;
 489         struct xhci_ring *ep_ring;
 490         struct list_head *entry;
 491         struct xhci_td *cur_td = 0;
 492         struct xhci_td *last_unlinked_td;
 493
 494         struct xhci_dequeue_state deq_state;
 495 #ifdef CONFIG_USB_HCD_STAT
 496         ktime_t stop_time = ktime_get();
 497 #endif
 498
 499         memset(&deq_state, 0, sizeof(deq_state));
 500         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 501         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 502         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
 503
 504         if (list_empty(&ep_ring->cancelled_td_list))
 505                 return;
 506
 507         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 508          * We have the xHCI lock, so nothing can modify this list until we drop
 509          * it.  We're also in the event handler, so we can't get re-interrupted
 510          * if another Stop Endpoint command completes
 511          */
 512         list_for_each(entry, &ep_ring->cancelled_td_list) {
 513                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 514                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 515                                 cur_td->first_trb,
 516                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 517                 /*
 518                  * If we stopped on the TD we need to cancel, then we have to
 519                  * move the xHC endpoint ring dequeue pointer past this TD.
 520                  */
 521                 if (cur_td == ep_ring->stopped_td)
 522                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
 523                                         &deq_state);
 524                 else
 525                         td_to_noop(xhci, ep_ring, cur_td);
 526                 /*
 527                  * The event handler won't see a completion for this TD anymore,
 528                  * so remove it from the endpoint ring's TD list.  Keep it in
 529                  * the cancelled TD list for URB completion later.
 530                  */
 531                 list_del(&cur_td->td_list);
 532                 ep_ring->cancels_pending--;
 533         }
 534         last_unlinked_td = cur_td;
 535
 536         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 537         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 538                 xhci_queue_new_dequeue_state(xhci, ep_ring,
 539                                 slot_id, ep_index, &deq_state);
 540                 xhci_ring_cmd_db(xhci);
 541         } else {
 542                 /* Otherwise just ring the doorbell to restart the ring */
 543                 ring_ep_doorbell(xhci, slot_id, ep_index);
 544         }
 545
 546         /*
 547          * Drop the lock and complete the URBs in the cancelled TD list.
 548          * New TDs to be cancelled might be added to the end of the list before
 549          * we can complete all the URBs for the TDs we already unlinked.
 550          * So stop when we've completed the URB for the last TD we unlinked.
 551          */
 552         do {
 553                 cur_td = list_entry(ep_ring->cancelled_td_list.next,
 554                                 struct xhci_td, cancelled_td_list);
 555                 list_del(&cur_td->cancelled_td_list);
 556
 557                 /* Clean up the cancelled URB */
 558 #ifdef CONFIG_USB_HCD_STAT
 559                 hcd_stat_update(xhci->tp_stat, cur_td->urb->actual_length,
 560                                 ktime_sub(stop_time, cur_td->start_time));
 561 #endif
 562                 cur_td->urb->hcpriv = NULL;
 563                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), cur_td->urb);
 564
 565                 xhci_dbg(xhci, "Giveback cancelled URB %p\n", cur_td->urb);
 566                 spin_unlock(&xhci->lock);
 567                 /* Doesn't matter what we pass for status, since the core will
 568                  * just overwrite it (because the URB has been unlinked).
 569                  */
 570                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), cur_td->urb, 0);
 571                 kfree(cur_td);
 572
 573                 spin_lock(&xhci->lock);
 574         } while (cur_td != last_unlinked_td);
 575
 576         /* Return to the event handler with xhci->lock re-acquired */
 577 }
 578
 579 /*
 580  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 581  * we need to clear the set deq pending flag in the endpoint ring state, so that
 582  * the TD queueing code can ring the doorbell again.  We also need to ring the
 583  * endpoint doorbell to restart the ring, but only if there aren't more
 584  * cancellations pending.
 585  */
 586 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 587                 struct xhci_event_cmd *event,
 588                 union xhci_trb *trb)
 589 {
 590         unsigned int slot_id;
 591         unsigned int ep_index;
 592         struct xhci_ring *ep_ring;
 593         struct xhci_virt_device *dev;
 594         struct xhci_ep_ctx *ep_ctx;
 595         struct xhci_slot_ctx *slot_ctx;
 596
 597         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 598         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 599         dev = xhci->devs[slot_id];
 600         ep_ring = dev->ep_rings[ep_index];
 601         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 602         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 603
 604         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 605                 unsigned int ep_state;
 606                 unsigned int slot_state;
 607
 608                 switch (GET_COMP_CODE(event->status)) {
 609                 case COMP_TRB_ERR:
 610                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 611                                         "of stream ID configuration\n");
 612                         break;
 613                 case COMP_CTX_STATE:
 614                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 615                                         "to incorrect slot or ep state.\n");
 616                         ep_state = ep_ctx->ep_info;
 617                         ep_state &= EP_STATE_MASK;
 618                         slot_state = slot_ctx->dev_state;
 619                         slot_state = GET_SLOT_STATE(slot_state);
 620                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 621                                         slot_state, ep_state);
 622                         break;
 623                 case COMP_EBADSLT:
 624                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 625                                         "slot %u was not enabled.\n", slot_id);
 626                         break;
 627                 default:
 628                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 629                                         "completion code of %u.\n",
 630                                         GET_COMP_CODE(event->status));
 631                         break;
 632                 }
 633                 /* OK what do we do now?  The endpoint state is hosed, and we
 634                  * should never get to this point if the synchronization between
 635                  * queueing, and endpoint state are correct.  This might happen
 636                  * if the device gets disconnected after we've finished
 637                  * cancelling URBs, which might not be an error...
 638                  */
 639         } else {
 640                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 641                                 ep_ctx->deq);
 642         }
 643
 644         ep_ring->state &= ~SET_DEQ_PENDING;
 645         ring_ep_doorbell(xhci, slot_id, ep_index);
 646 }
 647
 648 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 649                 struct xhci_event_cmd *event,
 650                 union xhci_trb *trb)
 651 {
 652         int slot_id;
 653         unsigned int ep_index;
 654         struct xhci_ring *ep_ring;
 655
 656         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 657         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 658         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
 659         /* This command will only fail if the endpoint wasn't halted,
 660          * but we don't care.
 661          */
 662         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 663                         (unsigned int) GET_COMP_CODE(event->status));
 664
 665         /* HW with the reset endpoint quirk needs to have a configure endpoint
 666          * command complete before the endpoint can be used.  Queue that here
 667          * because the HW can't handle two commands being queued in a row.
 668          */
 669         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
 670                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
 671                 xhci_queue_configure_endpoint(xhci,
 672                                 xhci->devs[slot_id]->in_ctx->dma, slot_id);
 673                 xhci_ring_cmd_db(xhci);
 674         } else {
 675                 /* Clear our internal halted state and restart the ring */
 676                 ep_ring->state &= ~EP_HALTED;
 677                 ring_ep_doorbell(xhci, slot_id, ep_index);
 678         }
 679 }
 680
 681 static void handle_cmd_completion(struct xhci_hcd *xhci,
 682                 struct xhci_event_cmd *event)
 683 {
 684         int slot_id = TRB_TO_SLOT_ID(event->flags);
 685         u64 cmd_dma;
 686         dma_addr_t cmd_dequeue_dma;
 687         struct xhci_input_control_ctx *ctrl_ctx;
 688         unsigned int ep_index;
 689         struct xhci_ring *ep_ring;
 690         unsigned int ep_state;
 691
 692         cmd_dma = event->cmd_trb;
 693         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 694                         xhci->cmd_ring->dequeue);
 695         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
 696         if (cmd_dequeue_dma == 0) {
 697                 xhci->error_bitmask |= 1 << 4;
 698                 return;
 699         }
 700         /* Does the DMA address match our internal dequeue pointer address? */
 701         if (cmd_dma != (u64) cmd_dequeue_dma) {
 702                 xhci->error_bitmask |= 1 << 5;
 703                 return;
 704         }
 705         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
 706         case TRB_TYPE(TRB_ENABLE_SLOT):
 707                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
 708                         xhci->slot_id = slot_id;
 709                 else
 710                         xhci->slot_id = 0;
 711                 complete(&xhci->addr_dev);
 712                 break;
 713         case TRB_TYPE(TRB_DISABLE_SLOT):
 714                 if (xhci->devs[slot_id])
 715                         xhci_free_virt_device(xhci, slot_id);
 716                 break;
 717         case TRB_TYPE(TRB_CONFIG_EP):
 718                 /*
 719                  * Configure endpoint commands can come from the USB core
 720                  * configuration or alt setting changes, or because the HW
 721                  * needed an extra configure endpoint command after a reset
 722                  * endpoint command.  In the latter case, the xHCI driver is
 723                  * not waiting on the configure endpoint command.
 724                  */
 725                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
 726                                 xhci->devs[slot_id]->in_ctx);
 727                 /* Input ctx add_flags are the endpoint index plus one */
 728                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
 729                 ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
 730                 if (!ep_ring) {
 731                         /* This must have been an initial configure endpoint */
 732                         xhci->devs[slot_id]->cmd_status =
 733                                 GET_COMP_CODE(event->status);
 734                         complete(&xhci->devs[slot_id]->cmd_completion);
 735                         break;
 736                 }
 737                 ep_state = ep_ring->state;
 738                 xhci_dbg(xhci, "Completed config ep cmd - last ep index = %d, "
 739                                 "state = %d\n", ep_index, ep_state);
 740                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
 741                                 ep_state & EP_HALTED) {
 742                         /* Clear our internal halted state and restart ring */
 743                         xhci->devs[slot_id]->ep_rings[ep_index]->state &=
 744                                 ~EP_HALTED;
 745                         ring_ep_doorbell(xhci, slot_id, ep_index);
 746                 } else {
 747                         xhci->devs[slot_id]->cmd_status =
 748                                 GET_COMP_CODE(event->status);
 749                         complete(&xhci->devs[slot_id]->cmd_completion);
 750                 }
 751                 break;
 752         case TRB_TYPE(TRB_EVAL_CONTEXT):
 753                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 754                 complete(&xhci->devs[slot_id]->cmd_completion);
 755                 break;
 756         case TRB_TYPE(TRB_ADDR_DEV):
 757                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
 758                 complete(&xhci->addr_dev);
 759                 break;
 760         case TRB_TYPE(TRB_STOP_RING):
 761                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
 762                 break;
 763         case TRB_TYPE(TRB_SET_DEQ):
 764                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
 765                 break;
 766         case TRB_TYPE(TRB_CMD_NOOP):
 767                 ++xhci->noops_handled;
 768                 break;
 769         case TRB_TYPE(TRB_RESET_EP):
 770                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
 771                 break;
 772         default:
 773                 /* Skip over unknown commands on the event ring */
 774                 xhci->error_bitmask |= 1 << 6;
 775                 break;
 776         }
 777         inc_deq(xhci, xhci->cmd_ring, false);
 778 }
 779
 780 static void handle_port_status(struct xhci_hcd *xhci,
 781                 union xhci_trb *event)
 782 {
 783         u32 port_id;
 784
 785         /* Port status change events always have a successful completion code */
 786         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
 787                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
 788                 xhci->error_bitmask |= 1 << 8;
 789         }
 790         /* FIXME: core doesn't care about all port link state changes yet */
 791         port_id = GET_PORT_ID(event->generic.field[0]);
 792         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
 793
 794         /* Update event ring dequeue pointer before dropping the lock */
 795         inc_deq(xhci, xhci->event_ring, true);
 796         xhci_set_hc_event_deq(xhci);
 797
 798         spin_unlock(&xhci->lock);
 799         /* Pass this up to the core */
 800         usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
 801         spin_lock(&xhci->lock);
 802 }
 803
 804 /*
 805  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
 806  * at end_trb, which may be in another segment.  If the suspect DMA address is a
 807  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
 808  * returns 0.
 809  */
 810 static struct xhci_segment *trb_in_td(
 811                 struct xhci_segment *start_seg,
 812                 union xhci_trb  *start_trb,
 813                 union xhci_trb  *end_trb,
 814                 dma_addr_t      suspect_dma)
 815 {
 816         dma_addr_t start_dma;
 817         dma_addr_t end_seg_dma;
 818         dma_addr_t end_trb_dma;
 819         struct xhci_segment *cur_seg;
 820
 821         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
 822         cur_seg = start_seg;
 823
 824         do {
 825                 /* We may get an event for a Link TRB in the middle of a TD */
 826                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
 827                                 &start_seg->trbs[TRBS_PER_SEGMENT - 1]);
 828                 /* If the end TRB isn't in this segment, this is set to 0 */
 829                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
 830
 831                 if (end_trb_dma > 0) {
 832                         /* The end TRB is in this segment, so suspect should be here */
 833                         if (start_dma <= end_trb_dma) {
 834                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
 835                                         return cur_seg;
 836                         } else {
 837                                 /* Case for one segment with
 838                                  * a TD wrapped around to the top
 839                                  */
 840                                 if ((suspect_dma >= start_dma &&
 841                                                         suspect_dma <= end_seg_dma) ||
 842                                                 (suspect_dma >= cur_seg->dma &&
 843                                                  suspect_dma <= end_trb_dma))
 844                                         return cur_seg;
 845                         }
 846                         return 0;
 847                 } else {
 848                         /* Might still be somewhere in this segment */
 849                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
 850                                 return cur_seg;
 851                 }
 852                 cur_seg = cur_seg->next;
 853                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
 854         } while (1);
 855
 856 }
 857
 858 /*
 859  * If this function returns an error condition, it means it got a Transfer
 860  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
 861  * At this point, the host controller is probably hosed and should be reset.
 862  */
 863 static int handle_tx_event(struct xhci_hcd *xhci,
 864                 struct xhci_transfer_event *event)
 865 {
 866         struct xhci_virt_device *xdev;
 867         struct xhci_ring *ep_ring;
 868         unsigned int slot_id;
 869         int ep_index;
 870         struct xhci_td *td = 0;
 871         dma_addr_t event_dma;
 872         struct xhci_segment *event_seg;
 873         union xhci_trb *event_trb;
 874         struct urb *urb = 0;
 875         int status = -EINPROGRESS;
 876         struct xhci_ep_ctx *ep_ctx;
 877
 878         xhci_dbg(xhci, "In %s\n", __func__);
 879         slot_id = TRB_TO_SLOT_ID(event->flags);
 880         xdev = xhci->devs[slot_id];
 881         if (!xdev) {
 882                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
 883                 return -ENODEV;
 884         }
 885
 886         /* Endpoint ID is 1 based, our index is zero based */
 887         ep_index = TRB_TO_EP_ID(event->flags) - 1;
 888         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
 889         ep_ring = xdev->ep_rings[ep_index];
 890         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
 891         if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
 892                 xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
 893                 return -ENODEV;
 894         }
 895
 896         event_dma = event->buffer;
 897         /* This TRB should be in the TD at the head of this ring's TD list */
 898         xhci_dbg(xhci, "%s - checking for list empty\n", __func__);
 899         if (list_empty(&ep_ring->td_list)) {
 900                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
 901                                 TRB_TO_SLOT_ID(event->flags), ep_index);
 902                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
 903                                 (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
 904                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
 905                 urb = NULL;
 906                 goto cleanup;
 907         }
 908         xhci_dbg(xhci, "%s - getting list entry\n", __func__);
 909         td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
 910
 911         /* Is this a TRB in the currently executing TD? */
 912         xhci_dbg(xhci, "%s - looking for TD\n", __func__);
 913         event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
 914                         td->last_trb, event_dma);
 915         xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg);
 916         if (!event_seg) {
 917                 /* HC is busted, give up! */
 918                 xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
 919                 return -ESHUTDOWN;
 920         }
 921         event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
 922         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
 923                         (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
 924         xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n",
 925                         lower_32_bits(event->buffer));
 926         xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n",
 927                         upper_32_bits(event->buffer));
 928         xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
 929                         (unsigned int) event->transfer_len);
 930         xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
 931                         (unsigned int) event->flags);
 932
 933         /* Look for common error cases */
 934         switch (GET_COMP_CODE(event->transfer_len)) {
 935         /* Skip codes that require special handling depending on
 936          * transfer type
 937          */
 938         case COMP_SUCCESS:
 939         case COMP_SHORT_TX:
 940                 break;
 941         case COMP_STOP:
 942                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
 943                 break;
 944         case COMP_STOP_INVAL:
 945                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
 946                 break;
 947         case COMP_STALL:
 948                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
 949                 ep_ring->state |= EP_HALTED;
 950                 status = -EPIPE;
 951                 break;
 952         case COMP_TRB_ERR:
 953                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
 954                 status = -EILSEQ;
 955                 break;
 956         case COMP_TX_ERR:
 957                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
 958                 status = -EPROTO;
 959                 break;
 960         case COMP_BABBLE:
 961                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
 962                 status = -EOVERFLOW;
 963                 break;
 964         case COMP_DB_ERR:
 965                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
 966                 status = -ENOSR;
 967                 break;
 968         default:
 969                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
 970                 urb = NULL;
 971                 goto cleanup;
 972         }
 973         /* Now update the urb's actual_length and give back to the core */
 974         /* Was this a control transfer? */
 975         if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
 976                 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
 977                 switch (GET_COMP_CODE(event->transfer_len)) {
 978                 case COMP_SUCCESS:
 979                         if (event_trb == ep_ring->dequeue) {
 980                                 xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
 981                                 status = -ESHUTDOWN;
 982                         } else if (event_trb != td->last_trb) {
 983                                 xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
 984                                 status = -ESHUTDOWN;
 985                         } else {
 986                                 xhci_dbg(xhci, "Successful control transfer!\n");
 987                                 status = 0;
 988                         }
 989                         break;
 990                 case COMP_SHORT_TX:
 991                         xhci_warn(xhci, "WARN: short transfer on control ep\n");
 992                         status = -EREMOTEIO;
 993                         break;
 994                 case COMP_STALL:
 995                         /* Did we transfer part of the data (middle) phase? */
 996                         if (event_trb != ep_ring->dequeue &&
 997                                         event_trb != td->last_trb)
 998                                 td->urb->actual_length =
 999                                         td->urb->transfer_buffer_length
1000                                         - TRB_LEN(event->transfer_len);
1001                         else
1002                                 td->urb->actual_length = 0;
1003
1004                         ep_ring->stopped_td = td;
1005                         ep_ring->stopped_trb = event_trb;
1006                         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1007                         xhci_cleanup_stalled_ring(xhci,
1008                                         td->urb->dev,
1009                                         ep_index, ep_ring);
1010                         xhci_ring_cmd_db(xhci);
1011                         goto td_cleanup;
1012                 default:
1013                         /* Others already handled above */
1014                         break;
1015                 }
1016                 /*
1017                  * Did we transfer any data, despite the errors that might have
1018                  * happened?  I.e. did we get past the setup stage?
1019                  */
1020                 if (event_trb != ep_ring->dequeue) {
1021                         /* The event was for the status stage */
1022                         if (event_trb == td->last_trb) {
1023                                 if (td->urb->actual_length != 0) {
1024                                         /* Don't overwrite a previously set error code */
1025                                         if (status == -EINPROGRESS || status == 0)
1026                                                 /* Did we already see a short data stage? */
1027                                                 status = -EREMOTEIO;
1028                                 } else {
1029                                         td->urb->actual_length =
1030                                                 td->urb->transfer_buffer_length;
1031                                 }
1032                         } else {
1033                         /* Maybe the event was for the data stage? */
1034                                 if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL) {
1035                                         /* We didn't stop on a link TRB in the middle */
1036                                         td->urb->actual_length =
1037                                                 td->urb->transfer_buffer_length -
1038                                                 TRB_LEN(event->transfer_len);
1039                                         xhci_dbg(xhci, "Waiting for status stage event\n");
1040                                         urb = NULL;
1041                                         goto cleanup;
1042                                 }
1043                         }
1044                 }
1045         } else {
1046                 switch (GET_COMP_CODE(event->transfer_len)) {
1047                 case COMP_SUCCESS:
1048                         /* Double check that the HW transferred everything. */
1049                         if (event_trb != td->last_trb) {
1050                                 xhci_warn(xhci, "WARN Successful completion "
1051                                                 "on short TX\n");
1052                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1053                                         status = -EREMOTEIO;
1054                                 else
1055                                         status = 0;
1056                         } else {
1057                                 xhci_dbg(xhci, "Successful bulk transfer!\n");
1058                                 status = 0;
1059                         }
1060                         break;
1061                 case COMP_SHORT_TX:
1062                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1063                                 status = -EREMOTEIO;
1064                         else
1065                                 status = 0;
1066                         break;
1067                 default:
1068                         /* Others already handled above */
1069                         break;
1070                 }
1071                 dev_dbg(&td->urb->dev->dev,
1072                                 "ep %#x - asked for %d bytes, "
1073                                 "%d bytes untransferred\n",
1074                                 td->urb->ep->desc.bEndpointAddress,
1075                                 td->urb->transfer_buffer_length,
1076                                 TRB_LEN(event->transfer_len));
1077                 /* Fast path - was this the last TRB in the TD for this URB? */
1078                 if (event_trb == td->last_trb) {
1079                         if (TRB_LEN(event->transfer_len) != 0) {
1080                                 td->urb->actual_length =
1081                                         td->urb->transfer_buffer_length -
1082                                         TRB_LEN(event->transfer_len);
1083                                 if (td->urb->actual_length < 0) {
1084                                         xhci_warn(xhci, "HC gave bad length "
1085                                                         "of %d bytes left\n",
1086                                                         TRB_LEN(event->transfer_len));
1087                                         td->urb->actual_length = 0;
1088                                 }
1089                                 /* Don't overwrite a previously set error code */
1090                                 if (status == -EINPROGRESS) {
1091                                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1092                                                 status = -EREMOTEIO;
1093                                         else
1094                                                 status = 0;
1095                                 }
1096                         } else {
1097                                 td->urb->actual_length = td->urb->transfer_buffer_length;
1098                                 /* Ignore a short packet completion if the
1099                                  * untransferred length was zero.
1100                                  */
1101                                 if (status == -EREMOTEIO)
1102                                         status = 0;
1103                         }
1104                 } else {
1105                         /* Slow path - walk the list, starting from the dequeue
1106                          * pointer, to get the actual length transferred.
1107                          */
1108                         union xhci_trb *cur_trb;
1109                         struct xhci_segment *cur_seg;
1110
1111                         td->urb->actual_length = 0;
1112                         for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1113                                         cur_trb != event_trb;
1114                                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1115                                 if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
1116                                                 TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
1117                                         td->urb->actual_length +=
1118                                                 TRB_LEN(cur_trb->generic.field[2]);
1119                         }
1120                         /* If the ring didn't stop on a Link or No-op TRB, add
1121                          * in the actual bytes transferred from the Normal TRB
1122                          */
1123                         if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL)
1124                                 td->urb->actual_length +=
1125                                         TRB_LEN(cur_trb->generic.field[2]) -
1126                                         TRB_LEN(event->transfer_len);
1127                 }
1128         }
1129         if (GET_COMP_CODE(event->transfer_len) == COMP_STOP_INVAL ||
1130                         GET_COMP_CODE(event->transfer_len) == COMP_STOP) {
1131                 /* The Endpoint Stop Command completion will take care of any
1132                  * stopped TDs.  A stopped TD may be restarted, so don't update
1133                  * the ring dequeue pointer or take this TD off any lists yet.
1134                  */
1135                 ep_ring->stopped_td = td;
1136                 ep_ring->stopped_trb = event_trb;
1137         } else {
1138                 if (GET_COMP_CODE(event->transfer_len) == COMP_STALL) {
1139                         /* The transfer is completed from the driver's
1140                          * perspective, but we need to issue a set dequeue
1141                          * command for this stalled endpoint to move the dequeue
1142                          * pointer past the TD.  We can't do that here because
1143                          * the halt condition must be cleared first.
1144                          */
1145                         ep_ring->stopped_td = td;
1146                         ep_ring->stopped_trb = event_trb;
1147                 } else {
1148                         /* Update ring dequeue pointer */
1149                         while (ep_ring->dequeue != td->last_trb)
1150                                 inc_deq(xhci, ep_ring, false);
1151                         inc_deq(xhci, ep_ring, false);
1152                 }
1153
1154 td_cleanup:
1155                 /* Clean up the endpoint's TD list */
1156                 urb = td->urb;
1157                 list_del(&td->td_list);
1158                 /* Was this TD slated to be cancelled but completed anyway? */
1159                 if (!list_empty(&td->cancelled_td_list)) {
1160                         list_del(&td->cancelled_td_list);
1161                         ep_ring->cancels_pending--;
1162                 }
1163                 /* Leave the TD around for the reset endpoint function to use
1164                  * (but only if it's not a control endpoint, since we already
1165                  * queued the Set TR dequeue pointer command for stalled
1166                  * control endpoints).
1167                  */
1168                 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
1169                         GET_COMP_CODE(event->transfer_len) != COMP_STALL) {
1170                         kfree(td);
1171                 }
1172                 urb->hcpriv = NULL;
1173         }
1174 cleanup:
1175         inc_deq(xhci, xhci->event_ring, true);
1176         xhci_set_hc_event_deq(xhci);
1177
1178         /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1179         if (urb) {
1180                 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
1181                 xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n",
1182                                 urb, td->urb->actual_length, status);
1183                 spin_unlock(&xhci->lock);
1184                 usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
1185                 spin_lock(&xhci->lock);
1186         }
1187         return 0;
1188 }
1189
1190 /*
1191  * This function handles all OS-owned events on the event ring.  It may drop
1192  * xhci->lock between event processing (e.g. to pass up port status changes).
1193  */
1194 void xhci_handle_event(struct xhci_hcd *xhci)
1195 {
1196         union xhci_trb *event;
1197         int update_ptrs = 1;
1198         int ret;
1199
1200         xhci_dbg(xhci, "In %s\n", __func__);
1201         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
1202                 xhci->error_bitmask |= 1 << 1;
1203                 return;
1204         }
1205
1206         event = xhci->event_ring->dequeue;
1207         /* Does the HC or OS own the TRB? */
1208         if ((event->event_cmd.flags & TRB_CYCLE) !=
1209                         xhci->event_ring->cycle_state) {
1210                 xhci->error_bitmask |= 1 << 2;
1211                 return;
1212         }
1213         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
1214
1215         /* FIXME: Handle more event types. */
1216         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
1217         case TRB_TYPE(TRB_COMPLETION):
1218                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
1219                 handle_cmd_completion(xhci, &event->event_cmd);
1220                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
1221                 break;
1222         case TRB_TYPE(TRB_PORT_STATUS):
1223                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
1224                 handle_port_status(xhci, event);
1225                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
1226                 update_ptrs = 0;
1227                 break;
1228         case TRB_TYPE(TRB_TRANSFER):
1229                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
1230                 ret = handle_tx_event(xhci, &event->trans_event);
1231                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
1232                 if (ret < 0)
1233                         xhci->error_bitmask |= 1 << 9;
1234                 else
1235                         update_ptrs = 0;
1236                 break;
1237         default:
1238                 xhci->error_bitmask |= 1 << 3;
1239         }
1240
1241         if (update_ptrs) {
1242                 /* Update SW and HC event ring dequeue pointer */
1243                 inc_deq(xhci, xhci->event_ring, true);
1244                 xhci_set_hc_event_deq(xhci);
1245         }
1246         /* Are there more items on the event ring? */
1247         xhci_handle_event(xhci);
1248 }
1249
1250 /****           Endpoint Ring Operations        ****/
1251
1252 /*
1253  * Generic function for queueing a TRB on a ring.
1254  * The caller must have checked to make sure there's room on the ring.
1255  */
1256 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
1257                 bool consumer,
1258                 u32 field1, u32 field2, u32 field3, u32 field4)
1259 {
1260         struct xhci_generic_trb *trb;
1261
1262         trb = &ring->enqueue->generic;
1263         trb->field[0] = field1;
1264         trb->field[1] = field2;
1265         trb->field[2] = field3;
1266         trb->field[3] = field4;
1267         inc_enq(xhci, ring, consumer);
1268 }
1269
1270 /*
1271  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1272  * FIXME allocate segments if the ring is full.
1273  */
1274 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
1275                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
1276 {
1277         /* Make sure the endpoint has been added to xHC schedule */
1278         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
1279         switch (ep_state) {
1280         case EP_STATE_DISABLED:
1281                 /*
1282                  * USB core changed config/interfaces without notifying us,
1283                  * or hardware is reporting the wrong state.
1284                  */
1285                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
1286                 return -ENOENT;
1287         case EP_STATE_ERROR:
1288                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
1289                 /* FIXME event handling code for error needs to clear it */
1290                 /* XXX not sure if this should be -ENOENT or not */
1291                 return -EINVAL;
1292         case EP_STATE_HALTED:
1293                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
1294         case EP_STATE_STOPPED:
1295         case EP_STATE_RUNNING:
1296                 break;
1297         default:
1298                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
1299                 /*
1300                  * FIXME issue Configure Endpoint command to try to get the HC
1301                  * back into a known state.
1302                  */
1303                 return -EINVAL;
1304         }
1305         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
1306                 /* FIXME allocate more room */
1307                 xhci_err(xhci, "ERROR no room on ep ring\n");
1308                 return -ENOMEM;
1309         }
1310         return 0;
1311 }
1312
1313 static int prepare_transfer(struct xhci_hcd *xhci,
1314                 struct xhci_virt_device *xdev,
1315                 unsigned int ep_index,
1316                 unsigned int num_trbs,
1317                 struct urb *urb,
1318                 struct xhci_td **td,
1319                 gfp_t mem_flags)
1320 {
1321         int ret;
1322         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1323         ret = prepare_ring(xhci, xdev->ep_rings[ep_index],
1324                         ep_ctx->ep_info & EP_STATE_MASK,
1325                         num_trbs, mem_flags);
1326         if (ret)
1327                 return ret;
1328         *td = kzalloc(sizeof(struct xhci_td), mem_flags);
1329         if (!*td)
1330                 return -ENOMEM;
1331         INIT_LIST_HEAD(&(*td)->td_list);
1332         INIT_LIST_HEAD(&(*td)->cancelled_td_list);
1333
1334         ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
1335         if (unlikely(ret)) {
1336                 kfree(*td);
1337                 return ret;
1338         }
1339
1340         (*td)->urb = urb;
1341         urb->hcpriv = (void *) (*td);
1342         /* Add this TD to the tail of the endpoint ring's TD list */
1343         list_add_tail(&(*td)->td_list, &xdev->ep_rings[ep_index]->td_list);
1344         (*td)->start_seg = xdev->ep_rings[ep_index]->enq_seg;
1345         (*td)->first_trb = xdev->ep_rings[ep_index]->enqueue;
1346
1347         return 0;
1348 }
1349
1350 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
1351 {
1352         int num_sgs, num_trbs, running_total, temp, i;
1353         struct scatterlist *sg;
1354
1355         sg = NULL;
1356         num_sgs = urb->num_sgs;
1357         temp = urb->transfer_buffer_length;
1358
1359         xhci_dbg(xhci, "count sg list trbs: \n");
1360         num_trbs = 0;
1361         for_each_sg(urb->sg->sg, sg, num_sgs, i) {
1362                 unsigned int previous_total_trbs = num_trbs;
1363                 unsigned int len = sg_dma_len(sg);
1364
1365                 /* Scatter gather list entries may cross 64KB boundaries */
1366                 running_total = TRB_MAX_BUFF_SIZE -
1367                         (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1368                 if (running_total != 0)
1369                         num_trbs++;
1370
1371                 /* How many more 64KB chunks to transfer, how many more TRBs? */
1372                 while (running_total < sg_dma_len(sg)) {
1373                         num_trbs++;
1374                         running_total += TRB_MAX_BUFF_SIZE;
1375                 }
1376                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1377                                 i, (unsigned long long)sg_dma_address(sg),
1378                                 len, len, num_trbs - previous_total_trbs);
1379
1380                 len = min_t(int, len, temp);
1381                 temp -= len;
1382                 if (temp == 0)
1383                         break;
1384         }
1385         xhci_dbg(xhci, "\n");
1386         if (!in_interrupt())
1387                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1388                                 urb->ep->desc.bEndpointAddress,
1389                                 urb->transfer_buffer_length,
1390                                 num_trbs);
1391         return num_trbs;
1392 }
1393
1394 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
1395 {
1396         if (num_trbs != 0)
1397                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
1398                                 "TRBs, %d left\n", __func__,
1399                                 urb->ep->desc.bEndpointAddress, num_trbs);
1400         if (running_total != urb->transfer_buffer_length)
1401                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
1402                                 "queued %#x (%d), asked for %#x (%d)\n",
1403                                 __func__,
1404                                 urb->ep->desc.bEndpointAddress,
1405                                 running_total, running_total,
1406                                 urb->transfer_buffer_length,
1407                                 urb->transfer_buffer_length);
1408 }
1409
1410 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
1411                 unsigned int ep_index, int start_cycle,
1412                 struct xhci_generic_trb *start_trb, struct xhci_td *td)
1413 {
1414         /*
1415          * Pass all the TRBs to the hardware at once and make sure this write
1416          * isn't reordered.
1417          */
1418         wmb();
1419         start_trb->field[3] |= start_cycle;
1420         ring_ep_doorbell(xhci, slot_id, ep_index);
1421 }
1422
1423 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1424                 struct urb *urb, int slot_id, unsigned int ep_index)
1425 {
1426         struct xhci_ring *ep_ring;
1427         unsigned int num_trbs;
1428         struct xhci_td *td;
1429         struct scatterlist *sg;
1430         int num_sgs;
1431         int trb_buff_len, this_sg_len, running_total;
1432         bool first_trb;
1433         u64 addr;
1434
1435         struct xhci_generic_trb *start_trb;
1436         int start_cycle;
1437
1438         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1439         num_trbs = count_sg_trbs_needed(xhci, urb);
1440         num_sgs = urb->num_sgs;
1441
1442         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
1443                         ep_index, num_trbs, urb, &td, mem_flags);
1444         if (trb_buff_len < 0)
1445                 return trb_buff_len;
1446         /*
1447          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1448          * until we've finished creating all the other TRBs.  The ring's cycle
1449          * state may change as we enqueue the other TRBs, so save it too.
1450          */
1451         start_trb = &ep_ring->enqueue->generic;
1452         start_cycle = ep_ring->cycle_state;
1453
1454         running_total = 0;
1455         /*
1456          * How much data is in the first TRB?
1457          *
1458          * There are three forces at work for TRB buffer pointers and lengths:
1459          * 1. We don't want to walk off the end of this sg-list entry buffer.
1460          * 2. The transfer length that the driver requested may be smaller than
1461          *    the amount of memory allocated for this scatter-gather list.
1462          * 3. TRBs buffers can't cross 64KB boundaries.
1463          */
1464         sg = urb->sg->sg;
1465         addr = (u64) sg_dma_address(sg);
1466         this_sg_len = sg_dma_len(sg);
1467         trb_buff_len = TRB_MAX_BUFF_SIZE -
1468                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1469         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1470         if (trb_buff_len > urb->transfer_buffer_length)
1471                 trb_buff_len = urb->transfer_buffer_length;
1472         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
1473                         trb_buff_len);
1474
1475         first_trb = true;
1476         /* Queue the first TRB, even if it's zero-length */
1477         do {
1478                 u32 field = 0;
1479                 u32 length_field = 0;
1480
1481                 /* Don't change the cycle bit of the first TRB until later */
1482                 if (first_trb)
1483                         first_trb = false;
1484                 else
1485                         field |= ep_ring->cycle_state;
1486
1487                 /* Chain all the TRBs together; clear the chain bit in the last
1488                  * TRB to indicate it's the last TRB in the chain.
1489                  */
1490                 if (num_trbs > 1) {
1491                         field |= TRB_CHAIN;
1492                 } else {
1493                         /* FIXME - add check for ZERO_PACKET flag before this */
1494                         td->last_trb = ep_ring->enqueue;
1495                         field |= TRB_IOC;
1496                 }
1497                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
1498                                 "64KB boundary at %#x, end dma = %#x\n",
1499                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
1500                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1501                                 (unsigned int) addr + trb_buff_len);
1502                 if (TRB_MAX_BUFF_SIZE -
1503                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
1504                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1505                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
1506                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
1507                                         (unsigned int) addr + trb_buff_len);
1508                 }
1509                 length_field = TRB_LEN(trb_buff_len) |
1510                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1511                         TRB_INTR_TARGET(0);
1512                 queue_trb(xhci, ep_ring, false,
1513                                 lower_32_bits(addr),
1514                                 upper_32_bits(addr),
1515                                 length_field,
1516                                 /* We always want to know if the TRB was short,
1517                                  * or we won't get an event when it completes.
1518                                  * (Unless we use event data TRBs, which are a
1519                                  * waste of space and HC resources.)
1520                                  */
1521                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1522                 --num_trbs;
1523                 running_total += trb_buff_len;
1524
1525                 /* Calculate length for next transfer --
1526                  * Are we done queueing all the TRBs for this sg entry?
1527                  */
1528                 this_sg_len -= trb_buff_len;
1529                 if (this_sg_len == 0) {
1530                         --num_sgs;
1531                         if (num_sgs == 0)
1532                                 break;
1533                         sg = sg_next(sg);
1534                         addr = (u64) sg_dma_address(sg);
1535                         this_sg_len = sg_dma_len(sg);
1536                 } else {
1537                         addr += trb_buff_len;
1538                 }
1539
1540                 trb_buff_len = TRB_MAX_BUFF_SIZE -
1541                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1542                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
1543                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
1544                         trb_buff_len =
1545                                 urb->transfer_buffer_length - running_total;
1546         } while (running_total < urb->transfer_buffer_length);
1547
1548         check_trb_math(urb, num_trbs, running_total);
1549         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1550         return 0;
1551 }
1552
1553 /* This is very similar to what ehci-q.c qtd_fill() does */
1554 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1555                 struct urb *urb, int slot_id, unsigned int ep_index)
1556 {
1557         struct xhci_ring *ep_ring;
1558         struct xhci_td *td;
1559         int num_trbs;
1560         struct xhci_generic_trb *start_trb;
1561         bool first_trb;
1562         int start_cycle;
1563         u32 field, length_field;
1564
1565         int running_total, trb_buff_len, ret;
1566         u64 addr;
1567
1568         if (urb->sg)
1569                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
1570
1571         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1572
1573         num_trbs = 0;
1574         /* How much data is (potentially) left before the 64KB boundary? */
1575         running_total = TRB_MAX_BUFF_SIZE -
1576                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1577
1578         /* If there's some data on this 64KB chunk, or we have to send a
1579          * zero-length transfer, we need at least one TRB
1580          */
1581         if (running_total != 0 || urb->transfer_buffer_length == 0)
1582                 num_trbs++;
1583         /* How many more 64KB chunks to transfer, how many more TRBs? */
1584         while (running_total < urb->transfer_buffer_length) {
1585                 num_trbs++;
1586                 running_total += TRB_MAX_BUFF_SIZE;
1587         }
1588         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1589
1590         if (!in_interrupt())
1591                 dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1592                                 urb->ep->desc.bEndpointAddress,
1593                                 urb->transfer_buffer_length,
1594                                 urb->transfer_buffer_length,
1595                                 (unsigned long long)urb->transfer_dma,
1596                                 num_trbs);
1597
1598         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
1599                         num_trbs, urb, &td, mem_flags);
1600         if (ret < 0)
1601                 return ret;
1602
1603         /*
1604          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1605          * until we've finished creating all the other TRBs.  The ring's cycle
1606          * state may change as we enqueue the other TRBs, so save it too.
1607          */
1608         start_trb = &ep_ring->enqueue->generic;
1609         start_cycle = ep_ring->cycle_state;
1610
1611         running_total = 0;
1612         /* How much data is in the first TRB? */
1613         addr = (u64) urb->transfer_dma;
1614         trb_buff_len = TRB_MAX_BUFF_SIZE -
1615                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
1616         if (urb->transfer_buffer_length < trb_buff_len)
1617                 trb_buff_len = urb->transfer_buffer_length;
1618
1619         first_trb = true;
1620
1621         /* Queue the first TRB, even if it's zero-length */
1622         do {
1623                 field = 0;
1624
1625                 /* Don't change the cycle bit of the first TRB until later */
1626                 if (first_trb)
1627                         first_trb = false;
1628                 else
1629                         field |= ep_ring->cycle_state;
1630
1631                 /* Chain all the TRBs together; clear the chain bit in the last
1632                  * TRB to indicate it's the last TRB in the chain.
1633                  */
1634                 if (num_trbs > 1) {
1635                         field |= TRB_CHAIN;
1636                 } else {
1637                         /* FIXME - add check for ZERO_PACKET flag before this */
1638                         td->last_trb = ep_ring->enqueue;
1639                         field |= TRB_IOC;
1640                 }
1641                 length_field = TRB_LEN(trb_buff_len) |
1642                         TD_REMAINDER(urb->transfer_buffer_length - running_total) |
1643                         TRB_INTR_TARGET(0);
1644                 queue_trb(xhci, ep_ring, false,
1645                                 lower_32_bits(addr),
1646                                 upper_32_bits(addr),
1647                                 length_field,
1648                                 /* We always want to know if the TRB was short,
1649                                  * or we won't get an event when it completes.
1650                                  * (Unless we use event data TRBs, which are a
1651                                  * waste of space and HC resources.)
1652                                  */
1653                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
1654                 --num_trbs;
1655                 running_total += trb_buff_len;
1656
1657                 /* Calculate length for next transfer */
1658                 addr += trb_buff_len;
1659                 trb_buff_len = urb->transfer_buffer_length - running_total;
1660                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
1661                         trb_buff_len = TRB_MAX_BUFF_SIZE;
1662         } while (running_total < urb->transfer_buffer_length);
1663
1664         check_trb_math(urb, num_trbs, running_total);
1665         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1666         return 0;
1667 }
1668
1669 /* Caller must have locked xhci->lock */
1670 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1671                 struct urb *urb, int slot_id, unsigned int ep_index)
1672 {
1673         struct xhci_ring *ep_ring;
1674         int num_trbs;
1675         int ret;
1676         struct usb_ctrlrequest *setup;
1677         struct xhci_generic_trb *start_trb;
1678         int start_cycle;
1679         u32 field, length_field;
1680         struct xhci_td *td;
1681
1682         ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
1683
1684         /*
1685          * Need to copy setup packet into setup TRB, so we can't use the setup
1686          * DMA address.
1687          */
1688         if (!urb->setup_packet)
1689                 return -EINVAL;
1690
1691         if (!in_interrupt())
1692                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
1693                                 slot_id, ep_index);
1694         /* 1 TRB for setup, 1 for status */
1695         num_trbs = 2;
1696         /*
1697          * Don't need to check if we need additional event data and normal TRBs,
1698          * since data in control transfers will never get bigger than 16MB
1699          * XXX: can we get a buffer that crosses 64KB boundaries?
1700          */
1701         if (urb->transfer_buffer_length > 0)
1702                 num_trbs++;
1703         ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
1704                         urb, &td, mem_flags);
1705         if (ret < 0)
1706                 return ret;
1707
1708         /*
1709          * Don't give the first TRB to the hardware (by toggling the cycle bit)
1710          * until we've finished creating all the other TRBs.  The ring's cycle
1711          * state may change as we enqueue the other TRBs, so save it too.
1712          */
1713         start_trb = &ep_ring->enqueue->generic;
1714         start_cycle = ep_ring->cycle_state;
1715
1716         /* Queue setup TRB - see section 6.4.1.2.1 */
1717         /* FIXME better way to translate setup_packet into two u32 fields? */
1718         setup = (struct usb_ctrlrequest *) urb->setup_packet;
1719         queue_trb(xhci, ep_ring, false,
1720                         /* FIXME endianness is probably going to bite my ass here. */
1721                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
1722                         setup->wIndex | setup->wLength << 16,
1723                         TRB_LEN(8) | TRB_INTR_TARGET(0),
1724                         /* Immediate data in pointer */
1725                         TRB_IDT | TRB_TYPE(TRB_SETUP));
1726
1727         /* If there's data, queue data TRBs */
1728         field = 0;
1729         length_field = TRB_LEN(urb->transfer_buffer_length) |
1730                 TD_REMAINDER(urb->transfer_buffer_length) |
1731                 TRB_INTR_TARGET(0);
1732         if (urb->transfer_buffer_length > 0) {
1733                 if (setup->bRequestType & USB_DIR_IN)
1734                         field |= TRB_DIR_IN;
1735                 queue_trb(xhci, ep_ring, false,
1736                                 lower_32_bits(urb->transfer_dma),
1737                                 upper_32_bits(urb->transfer_dma),
1738                                 length_field,
1739                                 /* Event on short tx */
1740                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
1741         }
1742
1743         /* Save the DMA address of the last TRB in the TD */
1744         td->last_trb = ep_ring->enqueue;
1745
1746         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1747         /* If the device sent data, the status stage is an OUT transfer */
1748         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
1749                 field = 0;
1750         else
1751                 field = TRB_DIR_IN;
1752         queue_trb(xhci, ep_ring, false,
1753                         0,
1754                         0,
1755                         TRB_INTR_TARGET(0),
1756                         /* Event on completion */
1757                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
1758
1759         giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
1760         return 0;
1761 }
1762
1763 /****           Command Ring Operations         ****/
1764
1765 /* Generic function for queueing a command TRB on the command ring */
1766 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, u32 field3, u32 field4)
1767 {
1768         if (!room_on_ring(xhci, xhci->cmd_ring, 1)) {
1769                 if (!in_interrupt())
1770                         xhci_err(xhci, "ERR: No room for command on command ring\n");
1771                 return -ENOMEM;
1772         }
1773         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
1774                         field4 | xhci->cmd_ring->cycle_state);
1775         return 0;
1776 }
1777
1778 /* Queue a no-op command on the command ring */
1779 static int queue_cmd_noop(struct xhci_hcd *xhci)
1780 {
1781         return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP));
1782 }
1783
1784 /*
1785  * Place a no-op command on the command ring to test the command and
1786  * event ring.
1787  */
1788 void *xhci_setup_one_noop(struct xhci_hcd *xhci)
1789 {
1790         if (queue_cmd_noop(xhci) < 0)
1791                 return NULL;
1792         xhci->noops_submitted++;
1793         return xhci_ring_cmd_db;
1794 }
1795
1796 /* Queue a slot enable or disable request on the command ring */
1797 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
1798 {
1799         return queue_command(xhci, 0, 0, 0,
1800                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id));
1801 }
1802
1803 /* Queue an address device command TRB */
1804 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1805                 u32 slot_id)
1806 {
1807         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1808                         upper_32_bits(in_ctx_ptr), 0,
1809                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id));
1810 }
1811
1812 /* Queue a configure endpoint command TRB */
1813 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1814                 u32 slot_id)
1815 {
1816         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1817                         upper_32_bits(in_ctx_ptr), 0,
1818                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id));
1819 }
1820
1821 /* Queue an evaluate context command TRB */
1822 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1823                 u32 slot_id)
1824 {
1825         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
1826                         upper_32_bits(in_ctx_ptr), 0,
1827                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id));
1828 }
1829
1830 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1831                 unsigned int ep_index)
1832 {
1833         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1834         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1835         u32 type = TRB_TYPE(TRB_STOP_RING);
1836
1837         return queue_command(xhci, 0, 0, 0,
1838                         trb_slot_id | trb_ep_index | type);
1839 }
1840
1841 /* Set Transfer Ring Dequeue Pointer command.
1842  * This should not be used for endpoints that have streams enabled.
1843  */
1844 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
1845                 unsigned int ep_index, struct xhci_segment *deq_seg,
1846                 union xhci_trb *deq_ptr, u32 cycle_state)
1847 {
1848         dma_addr_t addr;
1849         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1850         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1851         u32 type = TRB_TYPE(TRB_SET_DEQ);
1852
1853         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
1854         if (addr == 0) {
1855                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
1856                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
1857                                 deq_seg, deq_ptr);
1858                 return 0;
1859         }
1860         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
1861                         upper_32_bits(addr), 0,
1862                         trb_slot_id | trb_ep_index | type);
1863 }
1864
1865 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1866                 unsigned int ep_index)
1867 {
1868         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
1869         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
1870         u32 type = TRB_TYPE(TRB_RESET_EP);
1871
1872         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type);
1873 }