drivers/gpu/drm/radeon/rv6xx_dpm.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "rv6xxd.h"
  28 #include "r600_dpm.h"
  29 #include "rv6xx_dpm.h"
  30 #include "atom.h"
  31
  32 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
  33                                         u32 unscaled_count, u32 unit);
  34
  35 static struct rv6xx_ps *rv6xx_get_ps(struct radeon_ps *rps)
  36 {
  37         struct rv6xx_ps *ps = rps->ps_priv;
  38
  39         return ps;
  40 }
  41
  42 static struct rv6xx_power_info *rv6xx_get_pi(struct radeon_device *rdev)
  43 {
  44         struct rv6xx_power_info *pi = rdev->pm.dpm.priv;
  45
  46         return pi;
  47 }
  48
  49 static void rv6xx_force_pcie_gen1(struct radeon_device *rdev)
  50 {
  51         u32 tmp;
  52         int i;
  53
  54         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  55         tmp &= LC_GEN2_EN;
  56         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  57
  58         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  59         tmp |= LC_INITIATE_LINK_SPEED_CHANGE;
  60         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  61
  62         for (i = 0; i < rdev->usec_timeout; i++) {
  63                 if (!(RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE))
  64                         break;
  65                 udelay(1);
  66         }
  67
  68         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  69         tmp &= ~LC_INITIATE_LINK_SPEED_CHANGE;
  70         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  71 }
  72
  73 static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev)
  74 {
  75         u32 tmp;
  76
  77         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  78
  79         if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
  80             (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
  81                 tmp |= LC_GEN2_EN;
  82                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  83         }
  84 }
  85
  86 static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
  87                                                bool enable)
  88 {
  89         u32 tmp;
  90
  91         tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
  92         if (enable)
  93                 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
  94         else
  95                 tmp |= LC_HW_VOLTAGE_IF_CONTROL(0);
  96         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  97 }
  98
  99 static void rv6xx_enable_l0s(struct radeon_device *rdev)
 100 {
 101         u32 tmp;
 102
 103         tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
 104         tmp |= LC_L0S_INACTIVITY(3);
 105         WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
 106 }
 107
 108 static void rv6xx_enable_l1(struct radeon_device *rdev)
 109 {
 110         u32 tmp;
 111
 112         tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
 113         tmp &= ~LC_L1_INACTIVITY_MASK;
 114         tmp |= LC_L1_INACTIVITY(4);
 115         tmp &= ~LC_PMI_TO_L1_DIS;
 116         tmp &= ~LC_ASPM_TO_L1_DIS;
 117         WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
 118 }
 119
 120 static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev)
 121 {
 122         u32 tmp;
 123
 124         tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
 125         tmp |= LC_L1_INACTIVITY(8);
 126         WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
 127
 128         /* NOTE, this is a PCIE indirect reg, not PCIE PORT */
 129         tmp = RREG32_PCIE(PCIE_P_CNTL);
 130         tmp |= P_PLL_PWRDN_IN_L1L23;
 131         tmp &= ~P_PLL_BUF_PDNB;
 132         tmp &= ~P_PLL_PDNB;
 133         tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
 134         WREG32_PCIE(PCIE_P_CNTL, tmp);
 135 }
 136
 137 static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev,
 138                                            u32 clock, struct rv6xx_sclk_stepping *step)
 139 {
 140         int ret;
 141         struct atom_clock_dividers dividers;
 142
 143         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 144                                              clock, false, &dividers);
 145         if (ret)
 146                 return ret;
 147
 148         if (dividers.enable_post_div)
 149                 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);
 150         else
 151                 step->post_divider = 1;
 152
 153         step->vco_frequency = clock * step->post_divider;
 154
 155         return 0;
 156 }
 157
 158 static void rv6xx_output_stepping(struct radeon_device *rdev,
 159                                   u32 step_index, struct rv6xx_sclk_stepping *step)
 160 {
 161         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 162         u32 ref_clk = rdev->clock.spll.reference_freq;
 163         u32 fb_divider;
 164         u32 spll_step_count = rv6xx_scale_count_given_unit(rdev,
 165                                                            R600_SPLLSTEPTIME_DFLT *
 166                                                            pi->spll_ref_div,
 167                                                            R600_SPLLSTEPUNIT_DFLT);
 168
 169         r600_engine_clock_entry_enable(rdev, step_index, true);
 170         r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false);
 171
 172         if (step->post_divider == 1)
 173                 r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
 174         else {
 175                 u32 lo_len = (step->post_divider - 2) / 2;
 176                 u32 hi_len = step->post_divider - 2 - lo_len;
 177
 178                 r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);
 179                 r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len);
 180         }
 181
 182         fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >>
 183                 pi->fb_div_scale;
 184
 185         r600_engine_clock_entry_set_reference_divider(rdev, step_index,
 186                                                       pi->spll_ref_div - 1);
 187         r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider);
 188         r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count);
 189
 190 }
 191
 192 static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev,
 193                                                       struct rv6xx_sclk_stepping *cur,
 194                                                       bool increasing_vco, u32 step_size)
 195 {
 196         struct rv6xx_sclk_stepping next;
 197
 198         next.post_divider = cur->post_divider;
 199
 200         if (increasing_vco)
 201                 next.vco_frequency = (cur->vco_frequency * (100 + step_size)) / 100;
 202         else
 203                 next.vco_frequency = (cur->vco_frequency * 100 + 99 + step_size) / (100 + step_size);
 204
 205         return next;
 206 }
 207
 208 static bool rv6xx_can_step_post_div(struct radeon_device *rdev,
 209                                     struct rv6xx_sclk_stepping *cur,
 210                                     struct rv6xx_sclk_stepping *target)
 211 {
 212         return (cur->post_divider > target->post_divider) &&
 213                 ((cur->vco_frequency * target->post_divider) <=
 214                  (target->vco_frequency * (cur->post_divider - 1)));
 215 }
 216
 217 static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev,
 218                                                            struct rv6xx_sclk_stepping *cur,
 219                                                            struct rv6xx_sclk_stepping *target)
 220 {
 221         struct rv6xx_sclk_stepping next = *cur;
 222
 223         while (rv6xx_can_step_post_div(rdev, &next, target))
 224                 next.post_divider--;
 225
 226         return next;
 227 }
 228
 229 static bool rv6xx_reached_stepping_target(struct radeon_device *rdev,
 230                                           struct rv6xx_sclk_stepping *cur,
 231                                           struct rv6xx_sclk_stepping *target,
 232                                           bool increasing_vco)
 233 {
 234         return (increasing_vco && (cur->vco_frequency >= target->vco_frequency)) ||
 235                 (!increasing_vco && (cur->vco_frequency <= target->vco_frequency));
 236 }
 237
 238 static void rv6xx_generate_steps(struct radeon_device *rdev,
 239                                  u32 low, u32 high,
 240                                  u32 start_index, u8 *end_index)
 241 {
 242         struct rv6xx_sclk_stepping cur;
 243         struct rv6xx_sclk_stepping target;
 244         bool increasing_vco;
 245         u32 step_index = start_index;
 246
 247         rv6xx_convert_clock_to_stepping(rdev, low, &cur);
 248         rv6xx_convert_clock_to_stepping(rdev, high, &target);
 249
 250         rv6xx_output_stepping(rdev, step_index++, &cur);
 251
 252         increasing_vco = (target.vco_frequency >= cur.vco_frequency);
 253
 254         if (target.post_divider > cur.post_divider)
 255                 cur.post_divider = target.post_divider;
 256
 257         while (1) {
 258                 struct rv6xx_sclk_stepping next;
 259
 260                 if (rv6xx_can_step_post_div(rdev, &cur, &target))
 261                         next = rv6xx_next_post_div_step(rdev, &cur, &target);
 262                 else
 263                         next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT);
 264
 265                 if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) {
 266                         struct rv6xx_sclk_stepping tiny =
 267                                 rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT);
 268                         tiny.post_divider = next.post_divider;
 269
 270                         if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco))
 271                                 rv6xx_output_stepping(rdev, step_index++, &tiny);
 272
 273                         if ((next.post_divider != target.post_divider) &&
 274                             (next.vco_frequency != target.vco_frequency)) {
 275                                 struct rv6xx_sclk_stepping final_vco;
 276
 277                                 final_vco.vco_frequency = target.vco_frequency;
 278                                 final_vco.post_divider = next.post_divider;
 279
 280                                 rv6xx_output_stepping(rdev, step_index++, &final_vco);
 281                         }
 282
 283                         rv6xx_output_stepping(rdev, step_index++, &target);
 284                         break;
 285                 } else
 286                         rv6xx_output_stepping(rdev, step_index++, &next);
 287
 288                 cur = next;
 289         }
 290
 291         *end_index = (u8)step_index - 1;
 292
 293 }
 294
 295 static void rv6xx_generate_single_step(struct radeon_device *rdev,
 296                                        u32 clock, u32 index)
 297 {
 298         struct rv6xx_sclk_stepping step;
 299
 300         rv6xx_convert_clock_to_stepping(rdev, clock, &step);
 301         rv6xx_output_stepping(rdev, index, &step);
 302 }
 303
 304 static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev,
 305                                                       u32 start_index, u32 end_index)
 306 {
 307         u32 step_index;
 308
 309         for (step_index = start_index + 1; step_index < end_index; step_index++)
 310                 r600_engine_clock_entry_enable(rdev, step_index, false);
 311 }
 312
 313 static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev,
 314                                                    u32 index, u32 clk_s)
 315 {
 316         WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
 317                  CLKS(clk_s), ~CLKS_MASK);
 318 }
 319
 320 static void rv6xx_set_engine_spread_spectrum_clk_v(struct radeon_device *rdev,
 321                                                    u32 index, u32 clk_v)
 322 {
 323         WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
 324                  CLKV(clk_v), ~CLKV_MASK);
 325 }
 326
 327 static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev,
 328                                                 u32 index, bool enable)
 329 {
 330         if (enable)
 331                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
 332                          SSEN, ~SSEN);
 333         else
 334                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
 335                          0, ~SSEN);
 336 }
 337
 338 static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev,
 339                                                    u32 clk_s)
 340 {
 341         WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);
 342 }
 343
 344 static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev,
 345                                                    u32 clk_v)
 346 {
 347         WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);
 348 }
 349
 350 static void rv6xx_enable_memory_spread_spectrum(struct radeon_device *rdev,
 351                                                 bool enable)
 352 {
 353         if (enable)
 354                 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN);
 355         else
 356                 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
 357 }
 358
 359 static void rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev,
 360                                                  bool enable)
 361 {
 362         if (enable)
 363                 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
 364         else
 365                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
 366 }
 367
 368 static void rv6xx_memory_clock_entry_enable_post_divider(struct radeon_device *rdev,
 369                                                          u32 index, bool enable)
 370 {
 371         if (enable)
 372                 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
 373                          LEVEL0_MPLL_DIV_EN, ~LEVEL0_MPLL_DIV_EN);
 374         else
 375                 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);
 376 }
 377
 378 static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev,
 379                                                       u32 index, u32 divider)
 380 {
 381         WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
 382                  LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);
 383 }
 384
 385 static void rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev,
 386                                                           u32 index, u32 divider)
 387 {
 388         WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
 389                  ~LEVEL0_MPLL_FB_DIV_MASK);
 390 }
 391
 392 static void rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev,
 393                                                            u32 index, u32 divider)
 394 {
 395         WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
 396                  LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK);
 397 }
 398
 399 static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt)
 400 {
 401         WREG32_P(VID_RT, BRT(rt), ~BRT_MASK);
 402 }
 403
 404 static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device *rdev)
 405 {
 406         WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);
 407 }
 408
 409 static u64 rv6xx_clocks_per_unit(u32 unit)
 410 {
 411         u64 tmp = 1 << (2 * unit);
 412
 413         return tmp;
 414 }
 415
 416 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
 417                                         u32 unscaled_count, u32 unit)
 418 {
 419         u32 count_per_unit = (u32)rv6xx_clocks_per_unit(unit);
 420
 421         return (unscaled_count + count_per_unit - 1) / count_per_unit;
 422 }
 423
 424 static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev,
 425                                          u32 delay_us, u32 unit)
 426 {
 427         u32 ref_clk = rdev->clock.spll.reference_freq;
 428
 429         return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit);
 430 }
 431
 432 static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev,
 433                                                              struct rv6xx_ps *state)
 434 {
 435         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 436
 437         pi->hw.sclks[R600_POWER_LEVEL_LOW] =
 438                 state->low.sclk;
 439         pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] =
 440                 state->medium.sclk;
 441         pi->hw.sclks[R600_POWER_LEVEL_HIGH] =
 442                 state->high.sclk;
 443
 444         pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW;
 445         pi->hw.medium_sclk_index = R600_POWER_LEVEL_MEDIUM;
 446         pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;
 447 }
 448
 449 static void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev,
 450                                                              struct rv6xx_ps *state)
 451 {
 452         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 453
 454         pi->hw.mclks[R600_POWER_LEVEL_CTXSW] =
 455                 state->high.mclk;
 456         pi->hw.mclks[R600_POWER_LEVEL_HIGH] =
 457                 state->high.mclk;
 458         pi->hw.mclks[R600_POWER_LEVEL_MEDIUM] =
 459                 state->medium.mclk;
 460         pi->hw.mclks[R600_POWER_LEVEL_LOW] =
 461                 state->low.mclk;
 462
 463         pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;
 464
 465         if (state->high.mclk == state->medium.mclk)
 466                 pi->hw.medium_mclk_index =
 467                         pi->hw.high_mclk_index;
 468         else
 469                 pi->hw.medium_mclk_index = R600_POWER_LEVEL_MEDIUM;
 470
 471
 472         if (state->medium.mclk == state->low.mclk)
 473                 pi->hw.low_mclk_index =
 474                         pi->hw.medium_mclk_index;
 475         else
 476                 pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;
 477 }
 478
 479 static void rv6xx_calculate_voltage_stepping_parameters(struct radeon_device *rdev,
 480                                                         struct rv6xx_ps *state)
 481 {
 482         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 483
 484         pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc;
 485         pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;
 486         pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;
 487         pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;
 488
 489         pi->hw.backbias[R600_POWER_LEVEL_CTXSW] =
 490                 (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
 491         pi->hw.backbias[R600_POWER_LEVEL_HIGH] =
 492                 (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
 493         pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =
 494                 (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
 495         pi->hw.backbias[R600_POWER_LEVEL_LOW] =
 496                 (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
 497
 498         pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =
 499                 (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
 500         pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM] =
 501                 (state->medium.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
 502         pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW] =
 503                 (state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
 504
 505         pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH;
 506
 507         if ((state->high.vddc == state->medium.vddc) &&
 508             ((state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
 509              (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
 510                 pi->hw.medium_vddc_index =
 511                         pi->hw.high_vddc_index;
 512         else
 513                 pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM;
 514
 515         if ((state->medium.vddc == state->low.vddc) &&
 516             ((state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
 517              (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
 518                 pi->hw.low_vddc_index =
 519                         pi->hw.medium_vddc_index;
 520         else
 521                 pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW;
 522 }
 523
 524 static inline u32 rv6xx_calculate_vco_frequency(u32 ref_clock,
 525                                                 struct atom_clock_dividers *dividers,
 526                                                 u32 fb_divider_scale)
 527 {
 528         return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /
 529                 (dividers->ref_div + 1);
 530 }
 531
 532 static inline u32 rv6xx_calculate_spread_spectrum_clk_v(u32 vco_freq, u32 ref_freq,
 533                                                         u32 ss_rate, u32 ss_percent,
 534                                                         u32 fb_divider_scale)
 535 {
 536         u32 fb_divider = vco_freq / ref_freq;
 537
 538         return (ss_percent * ss_rate * 4 * (fb_divider * fb_divider) /
 539                 (5375 * ((vco_freq * 10) / (4096 >> fb_divider_scale))));
 540 }
 541
 542 static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32 ref_freq)
 543 {
 544         return (((ref_freq * 10) / (ss_rate * 2)) - 1) / 4;
 545 }
 546
 547 static void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev,
 548                                                  u32 clock, enum r600_power_level level)
 549 {
 550         u32 ref_clk = rdev->clock.spll.reference_freq;
 551         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 552         struct atom_clock_dividers dividers;
 553         struct radeon_atom_ss ss;
 554         u32 vco_freq, clk_v, clk_s;
 555
 556         rv6xx_enable_engine_spread_spectrum(rdev, level, false);
 557
 558         if (clock && pi->sclk_ss) {
 559                 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) {
 560                         vco_freq = rv6xx_calculate_vco_frequency(ref_clk, &dividers,
 561                                                                  pi->fb_div_scale);
 562
 563                         if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 564                                                              ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
 565                                 clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
 566                                                                               (ref_clk / (dividers.ref_div + 1)),
 567                                                                               ss.rate,
 568                                                                               ss.percentage,
 569                                                                               pi->fb_div_scale);
 570
 571                                 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
 572                                                                               (ref_clk / (dividers.ref_div + 1)));
 573
 574                                 rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v);
 575                                 rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s);
 576                                 rv6xx_enable_engine_spread_spectrum(rdev, level, true);
 577                         }
 578                 }
 579         }
 580 }
 581
 582 static void rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *rdev)
 583 {
 584         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 585
 586         rv6xx_program_engine_spread_spectrum(rdev,
 587                                              pi->hw.sclks[R600_POWER_LEVEL_HIGH],
 588                                              R600_POWER_LEVEL_HIGH);
 589
 590         rv6xx_program_engine_spread_spectrum(rdev,
 591                                              pi->hw.sclks[R600_POWER_LEVEL_MEDIUM],
 592                                              R600_POWER_LEVEL_MEDIUM);
 593
 594 }
 595
 596 static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev,
 597                                              u32 entry, u32 clock)
 598 {
 599         struct atom_clock_dividers dividers;
 600
 601         if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, &dividers))
 602             return -EINVAL;
 603
 604
 605         rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
 606         rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);
 607         rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);
 608
 609         if (dividers.enable_post_div)
 610                 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true);
 611         else
 612                 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false);
 613
 614         return 0;
 615 }
 616
 617 static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
 618 {
 619         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 620         int i;
 621
 622         for (i = 1; i < R600_PM_NUMBER_OF_MCLKS; i++) {
 623                 if (pi->hw.mclks[i])
 624                         rv6xx_program_mclk_stepping_entry(rdev, i,
 625                                                           pi->hw.mclks[i]);
 626         }
 627 }
 628
 629 static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev,
 630                                                      u32 requested_memory_clock,
 631                                                      u32 ref_clk,
 632                                                      struct atom_clock_dividers *dividers,
 633                                                      u32 *vco_freq)
 634 {
 635         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 636         struct atom_clock_dividers req_dividers;
 637         u32 vco_freq_temp;
 638
 639         if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
 640                                            requested_memory_clock, false, &req_dividers) == 0) {
 641                 vco_freq_temp = rv6xx_calculate_vco_frequency(ref_clk, &req_dividers,
 642                                                               pi->fb_div_scale);
 643
 644                 if (vco_freq_temp > *vco_freq) {
 645                         *dividers = req_dividers;
 646                         *vco_freq = vco_freq_temp;
 647                 }
 648         }
 649 }
 650
 651 static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev)
 652 {
 653         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 654         u32 ref_clk = rdev->clock.mpll.reference_freq;
 655         struct atom_clock_dividers dividers;
 656         struct radeon_atom_ss ss;
 657         u32 vco_freq = 0, clk_v, clk_s;
 658
 659         rv6xx_enable_memory_spread_spectrum(rdev, false);
 660
 661         if (pi->mclk_ss) {
 662                 rv6xx_find_memory_clock_with_highest_vco(rdev,
 663                                                          pi->hw.mclks[pi->hw.high_mclk_index],
 664                                                          ref_clk,
 665                                                          &dividers,
 666                                                          &vco_freq);
 667
 668                 rv6xx_find_memory_clock_with_highest_vco(rdev,
 669                                                          pi->hw.mclks[pi->hw.medium_mclk_index],
 670                                                          ref_clk,
 671                                                          &dividers,
 672                                                          &vco_freq);
 673
 674                 rv6xx_find_memory_clock_with_highest_vco(rdev,
 675                                                          pi->hw.mclks[pi->hw.low_mclk_index],
 676                                                          ref_clk,
 677                                                          &dividers,
 678                                                          &vco_freq);
 679
 680                 if (vco_freq) {
 681                         if (radeon_atombios_get_asic_ss_info(rdev, &ss,
 682                                                              ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
 683                                 clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
 684                                                                              (ref_clk / (dividers.ref_div + 1)),
 685                                                                              ss.rate,
 686                                                                              ss.percentage,
 687                                                                              pi->fb_div_scale);
 688
 689                                 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
 690                                                                              (ref_clk / (dividers.ref_div + 1)));
 691
 692                                 rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v);
 693                                 rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s);
 694                                 rv6xx_enable_memory_spread_spectrum(rdev, true);
 695                         }
 696                 }
 697         }
 698 }
 699
 700 static int rv6xx_program_voltage_stepping_entry(struct radeon_device *rdev,
 701                                                 u32 entry, u16 voltage)
 702 {
 703         u32 mask, set_pins;
 704         int ret;
 705
 706         ret = radeon_atom_get_voltage_gpio_settings(rdev, voltage,
 707                                                     SET_VOLTAGE_TYPE_ASIC_VDDC,
 708                                                     &set_pins, &mask);
 709         if (ret)
 710                 return ret;
 711
 712         r600_voltage_control_program_voltages(rdev, entry, set_pins);
 713
 714         return 0;
 715 }
 716
 717 static void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
 718 {
 719         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 720         int i;
 721
 722         for (i = 1; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++)
 723                 rv6xx_program_voltage_stepping_entry(rdev, i,
 724                                                      pi->hw.vddc[i]);
 725
 726 }
 727
 728 static void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
 729 {
 730         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 731
 732         if (pi->hw.backbias[1])
 733                 WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE);
 734         else
 735                 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE);
 736
 737         if (pi->hw.backbias[2])
 738                 WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE);
 739         else
 740                 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);
 741 }
 742
 743 static void rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(struct radeon_device *rdev)
 744 {
 745         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 746
 747         rv6xx_program_engine_spread_spectrum(rdev,
 748                                              pi->hw.sclks[R600_POWER_LEVEL_LOW],
 749                                              R600_POWER_LEVEL_LOW);
 750 }
 751
 752 static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct radeon_device *rdev)
 753 {
 754         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 755
 756         if (pi->hw.mclks[0])
 757                 rv6xx_program_mclk_stepping_entry(rdev, 0,
 758                                                   pi->hw.mclks[0]);
 759 }
 760
 761 static void rv6xx_program_voltage_stepping_parameters_lowest_entry(struct radeon_device *rdev)
 762 {
 763         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 764
 765         rv6xx_program_voltage_stepping_entry(rdev, 0,
 766                                              pi->hw.vddc[0]);
 767
 768 }
 769
 770 static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev)
 771 {
 772         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 773
 774         if (pi->hw.backbias[0])
 775                 WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE);
 776         else
 777                 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE);
 778 }
 779
 780 static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,
 781                                          u32 engine_clock)
 782 {
 783         u32 dram_rows, dram_refresh_rate;
 784         u32 tmp;
 785
 786         tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
 787         dram_rows = 1 << (tmp + 10);
 788         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3);
 789
 790         return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
 791 }
 792
 793 static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev)
 794 {
 795         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 796         u32 sqm_ratio;
 797         u32 arb_refresh_rate;
 798         u32 high_clock;
 799
 800         if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <
 801             (pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40))
 802                 high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH];
 803         else
 804                 high_clock =
 805                         pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40;
 806
 807         radeon_atom_set_engine_dram_timings(rdev, high_clock, 0);
 808
 809         sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_LOW]) |
 810                      STATE1(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) |
 811                      STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) |
 812                      STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]));
 813         WREG32(SQM_RATIO, sqm_ratio);
 814
 815         arb_refresh_rate =
 816                 (POWERMODE0(calculate_memory_refresh_rate(rdev,
 817                                                           pi->hw.sclks[R600_POWER_LEVEL_LOW])) |
 818                  POWERMODE1(calculate_memory_refresh_rate(rdev,
 819                                                           pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
 820                  POWERMODE2(calculate_memory_refresh_rate(rdev,
 821                                                           pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
 822                  POWERMODE3(calculate_memory_refresh_rate(rdev,
 823                                                           pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
 824         WREG32(ARB_RFSH_RATE, arb_refresh_rate);
 825 }
 826
 827 static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev)
 828 {
 829         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 830
 831         r600_set_mpll_lock_time(rdev, R600_MPLLLOCKTIME_DFLT *
 832                                 pi->mpll_ref_div);
 833         r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT);
 834 }
 835
 836 static void rv6xx_program_bsp(struct radeon_device *rdev)
 837 {
 838         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 839         u32 ref_clk = rdev->clock.spll.reference_freq;
 840
 841         r600_calculate_u_and_p(R600_ASI_DFLT,
 842                                ref_clk, 16,
 843                                &pi->bsp,
 844                                &pi->bsu);
 845
 846         r600_set_bsp(rdev, pi->bsu, pi->bsp);
 847 }
 848
 849 static void rv6xx_program_at(struct radeon_device *rdev)
 850 {
 851         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 852
 853         r600_set_at(rdev,
 854                     (pi->hw.rp[0] * pi->bsp) / 200,
 855                     (pi->hw.rp[1] * pi->bsp) / 200,
 856                     (pi->hw.lp[2] * pi->bsp) / 200,
 857                     (pi->hw.lp[1] * pi->bsp) / 200);
 858 }
 859
 860 static void rv6xx_program_git(struct radeon_device *rdev)
 861 {
 862         r600_set_git(rdev, R600_GICST_DFLT);
 863 }
 864
 865 static void rv6xx_program_tp(struct radeon_device *rdev)
 866 {
 867         int i;
 868
 869         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
 870                 r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]);
 871
 872         r600_select_td(rdev, R600_TD_DFLT);
 873 }
 874
 875 static void rv6xx_program_vc(struct radeon_device *rdev)
 876 {
 877         r600_set_vrc(rdev, R600_VRC_DFLT);
 878 }
 879
 880 static void rv6xx_clear_vc(struct radeon_device *rdev)
 881 {
 882         r600_set_vrc(rdev, 0);
 883 }
 884
 885 static void rv6xx_program_tpp(struct radeon_device *rdev)
 886 {
 887         r600_set_tpu(rdev, R600_TPU_DFLT);
 888         r600_set_tpc(rdev, R600_TPC_DFLT);
 889 }
 890
 891 static void rv6xx_program_sstp(struct radeon_device *rdev)
 892 {
 893         r600_set_sstu(rdev, R600_SSTU_DFLT);
 894         r600_set_sst(rdev, R600_SST_DFLT);
 895 }
 896
 897 static void rv6xx_program_fcp(struct radeon_device *rdev)
 898 {
 899         r600_set_fctu(rdev, R600_FCTU_DFLT);
 900         r600_set_fct(rdev, R600_FCT_DFLT);
 901 }
 902
 903 static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev)
 904 {
 905         r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
 906         r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
 907         r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
 908         r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
 909         r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
 910 }
 911
 912 static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev)
 913 {
 914         u32 rt;
 915
 916         r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
 917
 918         r600_vid_rt_set_vrt(rdev,
 919                             rv6xx_compute_count_for_delay(rdev,
 920                                                           rdev->pm.dpm.voltage_response_time,
 921                                                           R600_VRU_DFLT));
 922
 923         rt = rv6xx_compute_count_for_delay(rdev,
 924                                            rdev->pm.dpm.backbias_response_time,
 925                                            R600_VRU_DFLT);
 926
 927         rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5);
 928 }
 929
 930 static void rv6xx_program_engine_speed_parameters(struct radeon_device *rdev)
 931 {
 932         r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
 933         rv6xx_enable_engine_feedback_and_reference_sync(rdev);
 934 }
 935
 936 static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev)
 937 {
 938         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
 939         u64 master_mask = 0;
 940         int i;
 941
 942         for (i = 0; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++) {
 943                 u32 tmp_mask, tmp_set_pins;
 944                 int ret;
 945
 946                 ret = radeon_atom_get_voltage_gpio_settings(rdev,
 947                                                             pi->hw.vddc[i],
 948                                                             SET_VOLTAGE_TYPE_ASIC_VDDC,
 949                                                             &tmp_set_pins, &tmp_mask);
 950
 951                 if (ret == 0)
 952                         master_mask |= tmp_mask;
 953         }
 954
 955         return master_mask;
 956 }
 957
 958 static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev)
 959 {
 960         r600_voltage_control_enable_pins(rdev,
 961                                          rv6xx_get_master_voltage_mask(rdev));
 962 }
 963
 964 static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev,
 965                                                 struct radeon_ps *new_ps,
 966                                                 bool enable)
 967 {
 968         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
 969
 970         if (enable)
 971                 radeon_atom_set_voltage(rdev,
 972                                         new_state->low.vddc,
 973                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 974         else
 975                 r600_voltage_control_deactivate_static_control(rdev,
 976                                                                rv6xx_get_master_voltage_mask(rdev));
 977 }
 978
 979 static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)
 980 {
 981         if (enable) {
 982                 u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
 983                            DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
 984                            DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
 985                            DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
 986                            VBI_TIMER_COUNT(0x3FFF) |
 987                            VBI_TIMER_UNIT(7));
 988                 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
 989
 990                 WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP);
 991         } else
 992                 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP);
 993 }
 994
 995 static void rv6xx_program_power_level_enter_state(struct radeon_device *rdev)
 996 {
 997         r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM);
 998 }
 999
1000 static void rv6xx_calculate_t(u32 l_f, u32 h_f, int h,
1001                               int d_l, int d_r, u8 *l, u8 *r)
1002 {
1003         int a_n, a_d, h_r, l_r;
1004
1005         h_r = d_l;
1006         l_r = 100 - d_r;
1007
1008         a_n = (int)h_f * d_l + (int)l_f * (h - d_r);
1009         a_d = (int)l_f * l_r + (int)h_f * h_r;
1010
1011         if (a_d != 0) {
1012                 *l = d_l - h_r * a_n / a_d;
1013                 *r = d_r + l_r * a_n / a_d;
1014         }
1015 }
1016
1017 static void rv6xx_calculate_ap(struct radeon_device *rdev,
1018                                struct rv6xx_ps *state)
1019 {
1020         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1021
1022         pi->hw.lp[0] = 0;
1023         pi->hw.rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS - 1]
1024                 = 100;
1025
1026         rv6xx_calculate_t(state->low.sclk,
1027                           state->medium.sclk,
1028                           R600_AH_DFLT,
1029                           R600_LMP_DFLT,
1030                           R600_RLP_DFLT,
1031                           &pi->hw.lp[1],
1032                           &pi->hw.rp[0]);
1033
1034         rv6xx_calculate_t(state->medium.sclk,
1035                           state->high.sclk,
1036                           R600_AH_DFLT,
1037                           R600_LHP_DFLT,
1038                           R600_RMP_DFLT,
1039                           &pi->hw.lp[2],
1040                           &pi->hw.rp[1]);
1041
1042 }
1043
1044 static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev,
1045                                                 struct radeon_ps *new_ps)
1046 {
1047         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1048
1049         rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state);
1050         rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state);
1051         rv6xx_calculate_voltage_stepping_parameters(rdev, new_state);
1052         rv6xx_calculate_ap(rdev, new_state);
1053 }
1054
1055 static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
1056 {
1057         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1058
1059         rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev);
1060         if (pi->voltage_control)
1061                 rv6xx_program_voltage_stepping_parameters_except_lowest_entry(rdev);
1062         rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev);
1063         rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(rdev);
1064         rv6xx_program_mclk_spread_spectrum_parameters(rdev);
1065         rv6xx_program_memory_timing_parameters(rdev);
1066 }
1067
1068 static void rv6xx_program_stepping_parameters_lowest_entry(struct radeon_device *rdev)
1069 {
1070         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1071
1072         rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev);
1073         if (pi->voltage_control)
1074                 rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev);
1075         rv6xx_program_backbias_stepping_parameters_lowest_entry(rdev);
1076         rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev);
1077 }
1078
1079 static void rv6xx_program_power_level_low(struct radeon_device *rdev)
1080 {
1081         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1082
1083         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,
1084                                            pi->hw.low_vddc_index);
1085         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,
1086                                              pi->hw.low_mclk_index);
1087         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,
1088                                              pi->hw.low_sclk_index);
1089         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1090                                           R600_DISPLAY_WATERMARK_LOW);
1091         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1092                                        pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1093 }
1094
1095 static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev)
1096 {
1097         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1098
1099         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
1100         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1101         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1102
1103         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1104                                           R600_DISPLAY_WATERMARK_LOW);
1105
1106         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1107                                        pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1108
1109 }
1110
1111 static void rv6xx_program_power_level_medium(struct radeon_device *rdev)
1112 {
1113         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1114
1115         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,
1116                                           pi->hw.medium_vddc_index);
1117         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1118                                             pi->hw.medium_mclk_index);
1119         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1120                                             pi->hw.medium_sclk_index);
1121         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1122                                          R600_DISPLAY_WATERMARK_LOW);
1123         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1124                                       pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]);
1125 }
1126
1127 static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev)
1128 {
1129         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1130
1131         rv6xx_program_mclk_stepping_entry(rdev,
1132                                           R600_POWER_LEVEL_CTXSW,
1133                                           pi->hw.mclks[pi->hw.low_mclk_index]);
1134
1135         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1);
1136
1137         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1138                                              R600_POWER_LEVEL_CTXSW);
1139         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1140                                              pi->hw.medium_sclk_index);
1141
1142         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1143                                           R600_DISPLAY_WATERMARK_LOW);
1144
1145         rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1146
1147         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1148                                        pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1149 }
1150
1151 static void rv6xx_program_power_level_high(struct radeon_device *rdev)
1152 {
1153         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1154
1155         r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,
1156                                            pi->hw.high_vddc_index);
1157         r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1158                                              pi->hw.high_mclk_index);
1159         r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1160                                              pi->hw.high_sclk_index);
1161
1162         r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,
1163                                           R600_DISPLAY_WATERMARK_HIGH);
1164
1165         r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH,
1166                                        pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);
1167 }
1168
1169 static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
1170 {
1171         if (enable)
1172                 WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL,
1173                          ~(BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL));
1174         else
1175                 WREG32_P(GENERAL_PWRMGT, 0,
1176                          ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL));
1177 }
1178
1179 static void rv6xx_program_display_gap(struct radeon_device *rdev)
1180 {
1181         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1182
1183         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1184         if (RREG32(AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) {
1185                 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1186                 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1187         } else if (RREG32(AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) {
1188                 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1189                 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1190         } else {
1191                 tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1192                 tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1193         }
1194         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1195 }
1196
1197 static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev,
1198                                          struct radeon_ps *new_ps,
1199                                          struct radeon_ps *old_ps)
1200 {
1201         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1202         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1203         u16 safe_voltage;
1204
1205         safe_voltage = (new_state->low.vddc >= old_state->low.vddc) ?
1206                 new_state->low.vddc : old_state->low.vddc;
1207
1208         rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1209                                              safe_voltage);
1210
1211         WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1212                  ~SW_GPIO_INDEX_MASK);
1213 }
1214
1215 static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev,
1216                                         struct radeon_ps *old_ps)
1217 {
1218         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1219
1220         rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1221                                              old_state->low.vddc);
1222
1223         WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1224                 ~SW_GPIO_INDEX_MASK);
1225 }
1226
1227 static void rv6xx_set_safe_backbias(struct radeon_device *rdev,
1228                                     struct radeon_ps *new_ps,
1229                                     struct radeon_ps *old_ps)
1230 {
1231         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1232         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1233
1234         if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) &&
1235             (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE))
1236                 WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);
1237         else
1238                 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);
1239 }
1240
1241 static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev,
1242                                      struct radeon_ps *new_ps,
1243                                      struct radeon_ps *old_ps)
1244 {
1245         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1246         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1247
1248         if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) !=
1249             (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1250                 rv6xx_force_pcie_gen1(rdev);
1251 }
1252
1253 static void rv6xx_enable_dynamic_voltage_control(struct radeon_device *rdev,
1254                                                  bool enable)
1255 {
1256         if (enable)
1257                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
1258         else
1259                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
1260 }
1261
1262 static void rv6xx_enable_dynamic_backbias_control(struct radeon_device *rdev,
1263                                                   bool enable)
1264 {
1265         if (enable)
1266                 WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);
1267         else
1268                 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);
1269 }
1270
1271 static int rv6xx_step_sw_voltage(struct radeon_device *rdev,
1272                                  u16 initial_voltage,
1273                                  u16 target_voltage)
1274 {
1275         u16 current_voltage;
1276         u16 true_target_voltage;
1277         u16 voltage_step;
1278         int signed_voltage_step;
1279
1280         if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1281                                           &voltage_step)) ||
1282             (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1283                                                initial_voltage, &current_voltage)) ||
1284             (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1285                                                target_voltage, &true_target_voltage)))
1286                 return -EINVAL;
1287
1288         if (true_target_voltage < current_voltage)
1289                 signed_voltage_step = -(int)voltage_step;
1290         else
1291                 signed_voltage_step = voltage_step;
1292
1293         while (current_voltage != true_target_voltage) {
1294                 current_voltage += signed_voltage_step;
1295                 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1296                                                      current_voltage);
1297                 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1298         }
1299
1300         return 0;
1301 }
1302
1303 static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev,
1304                                             struct radeon_ps *new_ps,
1305                                             struct radeon_ps *old_ps)
1306 {
1307         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1308         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1309
1310         if (new_state->low.vddc > old_state->low.vddc)
1311                 return rv6xx_step_sw_voltage(rdev,
1312                                              old_state->low.vddc,
1313                                              new_state->low.vddc);
1314
1315         return 0;
1316 }
1317
1318 static int rv6xx_step_voltage_if_decreasing(struct radeon_device *rdev,
1319                                             struct radeon_ps *new_ps,
1320                                             struct radeon_ps *old_ps)
1321 {
1322         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1323         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1324
1325         if (new_state->low.vddc < old_state->low.vddc)
1326                 return rv6xx_step_sw_voltage(rdev,
1327                                              old_state->low.vddc,
1328                                              new_state->low.vddc);
1329         else
1330                 return 0;
1331 }
1332
1333 static void rv6xx_enable_high(struct radeon_device *rdev)
1334 {
1335         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1336
1337         if ((pi->restricted_levels < 1) ||
1338             (pi->restricted_levels == 3))
1339                 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1340 }
1341
1342 static void rv6xx_enable_medium(struct radeon_device *rdev)
1343 {
1344         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1345
1346         if (pi->restricted_levels < 2)
1347                 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1348 }
1349
1350 static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1351 {
1352         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1353         bool want_thermal_protection;
1354         enum radeon_dpm_event_src dpm_event_src;
1355
1356         switch (sources) {
1357         case 0:
1358         default:
1359                 want_thermal_protection = false;
1360                 break;
1361         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1362                 want_thermal_protection = true;
1363                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1364                 break;
1365
1366         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1367                 want_thermal_protection = true;
1368                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1369                 break;
1370
1371         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1372               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1373                 want_thermal_protection = true;
1374                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1375                 break;
1376         }
1377
1378         if (want_thermal_protection) {
1379                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
1380                 if (pi->thermal_protection)
1381                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
1382         } else {
1383                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
1384         }
1385 }
1386
1387 static void rv6xx_enable_auto_throttle_source(struct radeon_device *rdev,
1388                                               enum radeon_dpm_auto_throttle_src source,
1389                                               bool enable)
1390 {
1391         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1392
1393         if (enable) {
1394                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1395                         pi->active_auto_throttle_sources |= 1 << source;
1396                         rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1397                 }
1398         } else {
1399                 if (pi->active_auto_throttle_sources & (1 << source)) {
1400                         pi->active_auto_throttle_sources &= ~(1 << source);
1401                         rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1402                 }
1403         }
1404 }
1405
1406
1407 static void rv6xx_enable_thermal_protection(struct radeon_device *rdev,
1408                                             bool enable)
1409 {
1410         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1411
1412         if (pi->active_auto_throttle_sources)
1413                 r600_enable_thermal_protection(rdev, enable);
1414 }
1415
1416 static void rv6xx_generate_transition_stepping(struct radeon_device *rdev,
1417                                                struct radeon_ps *new_ps,
1418                                                struct radeon_ps *old_ps)
1419 {
1420         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1421         struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1422         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1423
1424         rv6xx_generate_steps(rdev,
1425                              old_state->low.sclk,
1426                              new_state->low.sclk,
1427                              0, &pi->hw.medium_sclk_index);
1428 }
1429
1430 static void rv6xx_generate_low_step(struct radeon_device *rdev,
1431                                     struct radeon_ps *new_ps)
1432 {
1433         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1434         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1435
1436         pi->hw.low_sclk_index = 0;
1437         rv6xx_generate_single_step(rdev,
1438                                    new_state->low.sclk,
1439                                    0);
1440 }
1441
1442 static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev)
1443 {
1444         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1445
1446         rv6xx_invalidate_intermediate_steps_range(rdev, 0,
1447                                                   pi->hw.medium_sclk_index);
1448 }
1449
1450 static void rv6xx_generate_stepping_table(struct radeon_device *rdev,
1451                                           struct radeon_ps *new_ps)
1452 {
1453         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1454         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1455
1456         pi->hw.low_sclk_index = 0;
1457
1458         rv6xx_generate_steps(rdev,
1459                              new_state->low.sclk,
1460                              new_state->medium.sclk,
1461                              0,
1462                              &pi->hw.medium_sclk_index);
1463         rv6xx_generate_steps(rdev,
1464                              new_state->medium.sclk,
1465                              new_state->high.sclk,
1466                              pi->hw.medium_sclk_index,
1467                              &pi->hw.high_sclk_index);
1468 }
1469
1470 static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev,
1471                                          bool enable)
1472 {
1473         if (enable)
1474                 rv6xx_enable_dynamic_spread_spectrum(rdev, true);
1475         else {
1476                 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false);
1477                 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1478                 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false);
1479                 rv6xx_enable_dynamic_spread_spectrum(rdev, false);
1480                 rv6xx_enable_memory_spread_spectrum(rdev, false);
1481         }
1482 }
1483
1484 static void rv6xx_reset_lvtm_data_sync(struct radeon_device *rdev)
1485 {
1486         if (ASIC_IS_DCE3(rdev))
1487                 WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
1488         else
1489                 WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
1490 }
1491
1492 static void rv6xx_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1493                                            struct radeon_ps *new_ps,
1494                                            bool enable)
1495 {
1496         struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1497
1498         if (enable) {
1499                 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true);
1500                 rv6xx_enable_pcie_gen2_support(rdev);
1501                 r600_enable_dynamic_pcie_gen2(rdev, true);
1502         } else {
1503                 if (!(new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1504                         rv6xx_force_pcie_gen1(rdev);
1505                 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false);
1506                 r600_enable_dynamic_pcie_gen2(rdev, false);
1507         }
1508 }
1509
1510 int rv6xx_dpm_enable(struct radeon_device *rdev)
1511 {
1512         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1513         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1514         int ret;
1515
1516         if (r600_dynamicpm_enabled(rdev))
1517                 return -EINVAL;
1518
1519         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1520                 rv6xx_enable_backbias(rdev, true);
1521
1522         if (pi->dynamic_ss)
1523                 rv6xx_enable_spread_spectrum(rdev, true);
1524
1525         rv6xx_program_mpll_timing_parameters(rdev);
1526         rv6xx_program_bsp(rdev);
1527         rv6xx_program_git(rdev);
1528         rv6xx_program_tp(rdev);
1529         rv6xx_program_tpp(rdev);
1530         rv6xx_program_sstp(rdev);
1531         rv6xx_program_fcp(rdev);
1532         rv6xx_program_vddc3d_parameters(rdev);
1533         rv6xx_program_voltage_timing_parameters(rdev);
1534         rv6xx_program_engine_speed_parameters(rdev);
1535
1536         rv6xx_enable_display_gap(rdev, true);
1537         if (pi->display_gap == false)
1538                 rv6xx_enable_display_gap(rdev, false);
1539
1540         rv6xx_program_power_level_enter_state(rdev);
1541
1542         rv6xx_calculate_stepping_parameters(rdev, boot_ps);
1543
1544         if (pi->voltage_control)
1545                 rv6xx_program_voltage_gpio_pins(rdev);
1546
1547         rv6xx_generate_stepping_table(rdev, boot_ps);
1548
1549         rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1550         rv6xx_program_stepping_parameters_lowest_entry(rdev);
1551
1552         rv6xx_program_power_level_low(rdev);
1553         rv6xx_program_power_level_medium(rdev);
1554         rv6xx_program_power_level_high(rdev);
1555         rv6xx_program_vc(rdev);
1556         rv6xx_program_at(rdev);
1557
1558         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1559         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1560         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1561
1562         if (rdev->irq.installed &&
1563             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1564                 ret = r600_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1565                 if (ret)
1566                         return ret;
1567                 rdev->irq.dpm_thermal = true;
1568                 radeon_irq_set(rdev);
1569         }
1570
1571         rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1572
1573         r600_start_dpm(rdev);
1574
1575         if (pi->voltage_control)
1576                 rv6xx_enable_static_voltage_control(rdev, boot_ps, false);
1577
1578         if (pi->dynamic_pcie_gen2)
1579                 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true);
1580
1581         if (pi->gfx_clock_gating)
1582                 r600_gfx_clockgating_enable(rdev, true);
1583
1584         return 0;
1585 }
1586
1587 void rv6xx_dpm_disable(struct radeon_device *rdev)
1588 {
1589         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1590         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1591
1592         if (!r600_dynamicpm_enabled(rdev))
1593                 return;
1594
1595         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1596         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1597         rv6xx_enable_display_gap(rdev, false);
1598         rv6xx_clear_vc(rdev);
1599         r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1600
1601         if (pi->thermal_protection)
1602                 r600_enable_thermal_protection(rdev, false);
1603
1604         r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1605         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1606         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1607
1608         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1609                 rv6xx_enable_backbias(rdev, false);
1610
1611         rv6xx_enable_spread_spectrum(rdev, false);
1612
1613         if (pi->voltage_control)
1614                 rv6xx_enable_static_voltage_control(rdev, boot_ps, true);
1615
1616         if (pi->dynamic_pcie_gen2)
1617                 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false);
1618
1619         if (rdev->irq.installed &&
1620             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1621                 rdev->irq.dpm_thermal = false;
1622                 radeon_irq_set(rdev);
1623         }
1624
1625         if (pi->gfx_clock_gating)
1626                 r600_gfx_clockgating_enable(rdev, false);
1627
1628         r600_stop_dpm(rdev);
1629 }
1630
1631 int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
1632 {
1633         struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1634         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
1635         struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1636         int ret;
1637
1638         rv6xx_clear_vc(rdev);
1639         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1640         r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1641
1642         if (pi->thermal_protection)
1643                 r600_enable_thermal_protection(rdev, false);
1644
1645         r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1646         r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1647         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1648
1649         rv6xx_generate_transition_stepping(rdev, new_ps, old_ps);
1650         rv6xx_program_power_level_medium_for_transition(rdev);
1651
1652         if (pi->voltage_control) {
1653                 rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps);
1654                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1655                         rv6xx_set_sw_voltage_to_low(rdev, old_ps);
1656         }
1657
1658         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1659                 rv6xx_set_safe_backbias(rdev, new_ps, old_ps);
1660
1661         if (pi->dynamic_pcie_gen2)
1662                 rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps);
1663
1664         if (pi->voltage_control)
1665                 rv6xx_enable_dynamic_voltage_control(rdev, false);
1666
1667         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1668                 rv6xx_enable_dynamic_backbias_control(rdev, false);
1669
1670         if (pi->voltage_control) {
1671                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1672                         rv6xx_step_voltage_if_increasing(rdev, new_ps, old_ps);
1673                 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1674         }
1675
1676         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1677         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
1678         r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW);
1679
1680         rv6xx_generate_low_step(rdev, new_ps);
1681         rv6xx_invalidate_intermediate_steps(rdev);
1682         rv6xx_calculate_stepping_parameters(rdev, new_ps);
1683         rv6xx_program_stepping_parameters_lowest_entry(rdev);
1684         rv6xx_program_power_level_low_to_lowest_state(rdev);
1685
1686         r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1687         r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1688         r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1689
1690         if (pi->voltage_control) {
1691                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) {
1692                         ret = rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps);
1693                         if (ret)
1694                                 return ret;
1695                 }
1696                 rv6xx_enable_dynamic_voltage_control(rdev, true);
1697         }
1698
1699         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1700                 rv6xx_enable_dynamic_backbias_control(rdev, true);
1701
1702         if (pi->dynamic_pcie_gen2)
1703                 rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true);
1704
1705         rv6xx_reset_lvtm_data_sync(rdev);
1706
1707         rv6xx_generate_stepping_table(rdev, new_ps);
1708         rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1709         rv6xx_program_power_level_low(rdev);
1710         rv6xx_program_power_level_medium(rdev);
1711         rv6xx_program_power_level_high(rdev);
1712         rv6xx_enable_medium(rdev);
1713         rv6xx_enable_high(rdev);
1714
1715         if (pi->thermal_protection)
1716                 rv6xx_enable_thermal_protection(rdev, true);
1717         rv6xx_program_vc(rdev);
1718         rv6xx_program_at(rdev);
1719
1720         return 0;
1721 }
1722
1723 void rv6xx_setup_asic(struct radeon_device *rdev)
1724 {
1725         r600_enable_acpi_pm(rdev);
1726
1727         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
1728                 rv6xx_enable_l0s(rdev);
1729         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
1730                 rv6xx_enable_l1(rdev);
1731         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
1732                 rv6xx_enable_pll_sleep_in_l1(rdev);
1733 }
1734
1735 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev)
1736 {
1737         rv6xx_program_display_gap(rdev);
1738 }
1739
1740 union power_info {
1741         struct _ATOM_POWERPLAY_INFO info;
1742         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1743         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1744         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1745         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1746         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1747 };
1748
1749 union pplib_clock_info {
1750         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1751         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1752         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1753         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1754 };
1755
1756 union pplib_power_state {
1757         struct _ATOM_PPLIB_STATE v1;
1758         struct _ATOM_PPLIB_STATE_V2 v2;
1759 };
1760
1761 static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
1762                                              struct radeon_ps *rps,
1763                                              struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
1764 {
1765         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1766         rps->class = le16_to_cpu(non_clock_info->usClassification);
1767         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1768
1769         if (r600_is_uvd_state(rps->class, rps->class2)) {
1770                 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ;
1771                 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ;
1772         } else {
1773                 rps->vclk = 0;
1774                 rps->dclk = 0;
1775         }
1776
1777         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
1778                 rdev->pm.dpm.boot_ps = rps;
1779         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1780                 rdev->pm.dpm.uvd_ps = rps;
1781 }
1782
1783 static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev,
1784                                          struct radeon_ps *rps, int index,
1785                                          union pplib_clock_info *clock_info)
1786 {
1787         struct rv6xx_ps *ps = rv6xx_get_ps(rps);
1788         u32 sclk, mclk;
1789         u16 vddc;
1790         struct rv6xx_pl *pl;
1791
1792         switch (index) {
1793         case 0:
1794                 pl = &ps->low;
1795                 break;
1796         case 1:
1797                 pl = &ps->medium;
1798                 break;
1799         case 2:
1800         default:
1801                 pl = &ps->high;
1802                 break;
1803         }
1804
1805         sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
1806         sclk |= clock_info->r600.ucEngineClockHigh << 16;
1807         mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
1808         mclk |= clock_info->r600.ucMemoryClockHigh << 16;
1809
1810         pl->mclk = mclk;
1811         pl->sclk = sclk;
1812         pl->vddc = le16_to_cpu(clock_info->r600.usVDDC);
1813         pl->flags = le32_to_cpu(clock_info->r600.ulFlags);
1814
1815         /* patch up vddc if necessary */
1816         if (pl->vddc == 0xff01) {
1817                 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
1818                         pl->vddc = vddc;
1819         }
1820
1821         /* fix up pcie gen2 */
1822         if (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) {
1823                 if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV630)) {
1824                         if (pl->vddc < 1100)
1825                                 pl->flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
1826                 }
1827         }
1828
1829         /* patch up boot state */
1830         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1831                 u16 vddc, vddci, mvdd;
1832                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
1833                 pl->mclk = rdev->clock.default_mclk;
1834                 pl->sclk = rdev->clock.default_sclk;
1835                 pl->vddc = vddc;
1836         }
1837 }
1838
1839 static int rv6xx_parse_power_table(struct radeon_device *rdev)
1840 {
1841         struct radeon_mode_info *mode_info = &rdev->mode_info;
1842         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1843         union pplib_power_state *power_state;
1844         int i, j;
1845         union pplib_clock_info *clock_info;
1846         union power_info *power_info;
1847         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1848         u16 data_offset;
1849         u8 frev, crev;
1850         struct rv6xx_ps *ps;
1851
1852         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1853                                    &frev, &crev, &data_offset))
1854                 return -EINVAL;
1855         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1856
1857         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1858                                   power_info->pplib.ucNumStates, GFP_KERNEL);
1859         if (!rdev->pm.dpm.ps)
1860                 return -ENOMEM;
1861         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
1862         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
1863         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
1864
1865         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
1866                 power_state = (union pplib_power_state *)
1867                         (mode_info->atom_context->bios + data_offset +
1868                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
1869                          i * power_info->pplib.ucStateEntrySize);
1870                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1871                         (mode_info->atom_context->bios + data_offset +
1872                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
1873                          (power_state->v1.ucNonClockStateIndex *
1874                           power_info->pplib.ucNonClockSize));
1875                 if (power_info->pplib.ucStateEntrySize - 1) {
1876                         ps = kzalloc(sizeof(struct rv6xx_ps), GFP_KERNEL);
1877                         if (ps == NULL) {
1878                                 kfree(rdev->pm.dpm.ps);
1879                                 return -ENOMEM;
1880                         }
1881                         rdev->pm.dpm.ps[i].ps_priv = ps;
1882                         rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1883                                                          non_clock_info);
1884                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
1885                                 clock_info = (union pplib_clock_info *)
1886                                         (mode_info->atom_context->bios + data_offset +
1887                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
1888                                          (power_state->v1.ucClockStateIndices[j] *
1889                                           power_info->pplib.ucClockInfoSize));
1890                                 rv6xx_parse_pplib_clock_info(rdev,
1891                                                              &rdev->pm.dpm.ps[i], j,
1892                                                              clock_info);
1893                         }
1894                 }
1895         }
1896         rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
1897         return 0;
1898 }
1899
1900 int rv6xx_dpm_init(struct radeon_device *rdev)
1901 {
1902         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1903         uint16_t data_offset, size;
1904         uint8_t frev, crev;
1905         struct atom_clock_dividers dividers;
1906         struct rv6xx_power_info *pi;
1907         int ret;
1908
1909         pi = kzalloc(sizeof(struct rv6xx_power_info), GFP_KERNEL);
1910         if (pi == NULL)
1911                 return -ENOMEM;
1912         rdev->pm.dpm.priv = pi;
1913
1914         ret = rv6xx_parse_power_table(rdev);
1915         if (ret)
1916                 return ret;
1917
1918         if (rdev->pm.dpm.voltage_response_time == 0)
1919                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
1920         if (rdev->pm.dpm.backbias_response_time == 0)
1921                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
1922
1923         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1924                                              0, false, &dividers);
1925         if (ret)
1926                 pi->spll_ref_div = dividers.ref_div + 1;
1927         else
1928                 pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1929
1930         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
1931                                              0, false, &dividers);
1932         if (ret)
1933                 pi->mpll_ref_div = dividers.ref_div + 1;
1934         else
1935                 pi->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1936
1937         if (rdev->family >= CHIP_RV670)
1938                 pi->fb_div_scale = 1;
1939         else
1940                 pi->fb_div_scale = 0;
1941
1942         pi->voltage_control =
1943                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
1944
1945         pi->gfx_clock_gating = true;
1946
1947         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
1948                                    &frev, &crev, &data_offset)) {
1949                 pi->sclk_ss = true;
1950                 pi->mclk_ss = true;
1951                 pi->dynamic_ss = true;
1952         } else {
1953                 pi->sclk_ss = false;
1954                 pi->mclk_ss = false;
1955                 pi->dynamic_ss = false;
1956         }
1957
1958         pi->dynamic_pcie_gen2 = true;
1959
1960         if (pi->gfx_clock_gating &&
1961             (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
1962                 pi->thermal_protection = true;
1963         else
1964                 pi->thermal_protection = false;
1965
1966         pi->display_gap = true;
1967
1968         return 0;
1969 }
1970
1971 void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
1972                                  struct radeon_ps *rps)
1973 {
1974         struct rv6xx_ps *ps = rv6xx_get_ps(rps);
1975         struct rv6xx_pl *pl;
1976
1977         r600_dpm_print_class_info(rps->class, rps->class2);
1978         r600_dpm_print_cap_info(rps->caps);
1979         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1980         pl = &ps->low;
1981         printk("\t\tpower level 0    sclk: %u mclk: %u vddc: %u\n",
1982                pl->sclk, pl->mclk, pl->vddc);
1983         pl = &ps->medium;
1984         printk("\t\tpower level 1    sclk: %u mclk: %u vddc: %u\n",
1985                pl->sclk, pl->mclk, pl->vddc);
1986         pl = &ps->high;
1987         printk("\t\tpower level 2    sclk: %u mclk: %u vddc: %u\n",
1988                pl->sclk, pl->mclk, pl->vddc);
1989         r600_dpm_print_ps_status(rdev, rps);
1990 }
1991
1992 void rv6xx_dpm_fini(struct radeon_device *rdev)
1993 {
1994         int i;
1995
1996         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1997                 kfree(rdev->pm.dpm.ps[i].ps_priv);
1998         }
1999         kfree(rdev->pm.dpm.ps);
2000         kfree(rdev->pm.dpm.priv);
2001 }
2002
2003 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
2004 {
2005         struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2006
2007         if (low)
2008                 return requested_state->low.sclk;
2009         else
2010                 return requested_state->high.sclk;
2011 }
2012
2013 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
2014 {
2015         struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2016
2017         if (low)
2018                 return requested_state->low.mclk;
2019         else
2020                 return requested_state->high.mclk;
2021 }