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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_USBCX_TYPEDEFS_H__
53 #define __CVMX_USBCX_TYPEDEFS_H__
55 #define CVMX_USBCX_DAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000818ull) + ((block_id) & 1) * 0x100000000000ull)
56 #define CVMX_USBCX_DAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F001000081Cull) + ((block_id) & 1) * 0x100000000000ull)
57 #define CVMX_USBCX_DCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000800ull) + ((block_id) & 1) * 0x100000000000ull)
58 #define CVMX_USBCX_DCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000804ull) + ((block_id) & 1) * 0x100000000000ull)
59 #define CVMX_USBCX_DIEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000900ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
60 #define CVMX_USBCX_DIEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000908ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
61 #define CVMX_USBCX_DIEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000810ull) + ((block_id) & 1) * 0x100000000000ull)
62 #define CVMX_USBCX_DIEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000910ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
63 #define CVMX_USBCX_DOEPCTLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B00ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
64 #define CVMX_USBCX_DOEPINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B08ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
65 #define CVMX_USBCX_DOEPMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000814ull) + ((block_id) & 1) * 0x100000000000ull)
66 #define CVMX_USBCX_DOEPTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000B10ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
67 #define CVMX_USBCX_DPTXFSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + (((offset) & 7) + ((block_id) & 1) * 0x40000000000ull) * 4)
68 #define CVMX_USBCX_DSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000808ull) + ((block_id) & 1) * 0x100000000000ull)
69 #define CVMX_USBCX_DTKNQR1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000820ull) + ((block_id) & 1) * 0x100000000000ull)
70 #define CVMX_USBCX_DTKNQR2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000824ull) + ((block_id) & 1) * 0x100000000000ull)
71 #define CVMX_USBCX_DTKNQR3(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000830ull) + ((block_id) & 1) * 0x100000000000ull)
72 #define CVMX_USBCX_DTKNQR4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000834ull) + ((block_id) & 1) * 0x100000000000ull)
73 #define CVMX_USBCX_GAHBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000008ull) + ((block_id) & 1) * 0x100000000000ull)
74 #define CVMX_USBCX_GHWCFG1(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000044ull) + ((block_id) & 1) * 0x100000000000ull)
75 #define CVMX_USBCX_GHWCFG2(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000048ull) + ((block_id) & 1) * 0x100000000000ull)
76 #define CVMX_USBCX_GHWCFG3(block_id) (CVMX_ADD_IO_SEG(0x00016F001000004Cull) + ((block_id) & 1) * 0x100000000000ull)
77 #define CVMX_USBCX_GHWCFG4(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000050ull) + ((block_id) & 1) * 0x100000000000ull)
78 #define CVMX_USBCX_GINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000018ull) + ((block_id) & 1) * 0x100000000000ull)
79 #define CVMX_USBCX_GINTSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000014ull) + ((block_id) & 1) * 0x100000000000ull)
80 #define CVMX_USBCX_GNPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000028ull) + ((block_id) & 1) * 0x100000000000ull)
81 #define CVMX_USBCX_GNPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F001000002Cull) + ((block_id) & 1) * 0x100000000000ull)
82 #define CVMX_USBCX_GOTGCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000000ull) + ((block_id) & 1) * 0x100000000000ull)
83 #define CVMX_USBCX_GOTGINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000004ull) + ((block_id) & 1) * 0x100000000000ull)
84 #define CVMX_USBCX_GRSTCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000010ull) + ((block_id) & 1) * 0x100000000000ull)
85 #define CVMX_USBCX_GRXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000024ull) + ((block_id) & 1) * 0x100000000000ull)
86 #define CVMX_USBCX_GRXSTSPD(block_id) (CVMX_ADD_IO_SEG(0x00016F0010040020ull) + ((block_id) & 1) * 0x100000000000ull)
87 #define CVMX_USBCX_GRXSTSPH(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000020ull) + ((block_id) & 1) * 0x100000000000ull)
88 #define CVMX_USBCX_GRXSTSRD(block_id) (CVMX_ADD_IO_SEG(0x00016F001004001Cull) + ((block_id) & 1) * 0x100000000000ull)
89 #define CVMX_USBCX_GRXSTSRH(block_id) (CVMX_ADD_IO_SEG(0x00016F001000001Cull) + ((block_id) & 1) * 0x100000000000ull)
90 #define CVMX_USBCX_GSNPSID(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000040ull) + ((block_id) & 1) * 0x100000000000ull)
91 #define CVMX_USBCX_GUSBCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F001000000Cull) + ((block_id) & 1) * 0x100000000000ull)
92 #define CVMX_USBCX_HAINT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000414ull) + ((block_id) & 1) * 0x100000000000ull)
93 #define CVMX_USBCX_HAINTMSK(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000418ull) + ((block_id) & 1) * 0x100000000000ull)
94 #define CVMX_USBCX_HCCHARX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000500ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
95 #define CVMX_USBCX_HCFG(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000400ull) + ((block_id) & 1) * 0x100000000000ull)
96 #define CVMX_USBCX_HCINTMSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F001000050Cull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
97 #define CVMX_USBCX_HCINTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000508ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
98 #define CVMX_USBCX_HCSPLTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000504ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
99 #define CVMX_USBCX_HCTSIZX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010000510ull) + (((offset) & 7) + ((block_id) & 1) * 0x8000000000ull) * 32)
100 #define CVMX_USBCX_HFIR(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000404ull) + ((block_id) & 1) * 0x100000000000ull)
101 #define CVMX_USBCX_HFNUM(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000408ull) + ((block_id) & 1) * 0x100000000000ull)
102 #define CVMX_USBCX_HPRT(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000440ull) + ((block_id) & 1) * 0x100000000000ull)
103 #define CVMX_USBCX_HPTXFSIZ(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000100ull) + ((block_id) & 1) * 0x100000000000ull)
104 #define CVMX_USBCX_HPTXSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000410ull) + ((block_id) & 1) * 0x100000000000ull)
105 #define CVMX_USBCX_NPTXDFIFOX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0010001000ull) + (((offset) & 7) + ((block_id) & 1) * 0x100000000ull) * 4096)
106 #define CVMX_USBCX_PCGCCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull)
111 * Core AHB Configuration Register (GAHBCFG)
113 * This register can be used to configure the core after power-on or a change in mode of operation.
114 * This register mainly contains AHB system-related configuration parameters. The AHB is the processor
115 * interface to the O2P USB core. In general, software need not know about this interface except to
116 * program the values as specified.
118 * The application must program this register as part of the O2P USB core initialization.
119 * Do not change this register after the initial programming.
121 union cvmx_usbcx_gahbcfg
124 struct cvmx_usbcx_gahbcfg_s
126 uint32_t reserved_9_31 : 23;
127 uint32_t ptxfemplvl : 1; /**< Periodic TxFIFO Empty Level (PTxFEmpLvl)
128 Software should set this bit to 0x1.
129 Indicates when the Periodic TxFIFO Empty Interrupt bit in the
130 Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
131 bit is used only in Slave mode.
132 * 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic
134 * 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic
135 TxFIFO is completely empty */
136 uint32_t nptxfemplvl : 1; /**< Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
137 Software should set this bit to 0x1.
138 Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
139 the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
140 This bit is used only in Slave mode.
141 * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
142 Periodic TxFIFO is half empty
143 * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
144 Periodic TxFIFO is completely empty */
145 uint32_t reserved_6_6 : 1;
146 uint32_t dmaen : 1; /**< DMA Enable (DMAEn)
147 * 1'b0: Core operates in Slave mode
148 * 1'b1: Core operates in a DMA mode */
149 uint32_t hbstlen : 4; /**< Burst Length/Type (HBstLen)
150 This field has not effect and should be left as 0x0. */
151 uint32_t glblintrmsk : 1; /**< Global Interrupt Mask (GlblIntrMsk)
152 Software should set this field to 0x1.
153 The application uses this bit to mask or unmask the interrupt
154 line assertion to itself. Irrespective of this bit's setting, the
155 interrupt status registers are updated by the core.
156 * 1'b0: Mask the interrupt assertion to the application.
157 * 1'b1: Unmask the interrupt assertion to the application. */
159 struct cvmx_usbcx_gahbcfg_s cn30xx;
160 struct cvmx_usbcx_gahbcfg_s cn31xx;
161 struct cvmx_usbcx_gahbcfg_s cn50xx;
162 struct cvmx_usbcx_gahbcfg_s cn52xx;
163 struct cvmx_usbcx_gahbcfg_s cn52xxp1;
164 struct cvmx_usbcx_gahbcfg_s cn56xx;
165 struct cvmx_usbcx_gahbcfg_s cn56xxp1;
167 typedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t;
172 * User HW Config3 Register (GHWCFG3)
174 * This register contains the configuration options of the O2P USB core.
176 union cvmx_usbcx_ghwcfg3
179 struct cvmx_usbcx_ghwcfg3_s
181 uint32_t dfifodepth : 16; /**< DFIFO Depth (DfifoDepth)
182 This value is in terms of 32-bit words.
183 * Minimum value is 32
184 * Maximum value is 32768 */
185 uint32_t reserved_13_15 : 3;
186 uint32_t ahbphysync : 1; /**< AHB and PHY Synchronous (AhbPhySync)
187 Indicates whether AHB and PHY clocks are synchronous to
191 This bit is tied to 1. */
192 uint32_t rsttype : 1; /**< Reset Style for Clocked always Blocks in RTL (RstType)
193 * 1'b0: Asynchronous reset is used in the core
194 * 1'b1: Synchronous reset is used in the core */
195 uint32_t optfeature : 1; /**< Optional Features Removed (OptFeature)
196 Indicates whether the User ID register, GPIO interface ports,
197 and SOF toggle and counter ports were removed for gate count
199 uint32_t vendor_control_interface_support : 1;/**< Vendor Control Interface Support
200 * 1'b0: Vendor Control Interface is not available on the core.
201 * 1'b1: Vendor Control Interface is available. */
202 uint32_t i2c_selection : 1; /**< I2C Selection
203 * 1'b0: I2C Interface is not available on the core.
204 * 1'b1: I2C Interface is available on the core. */
205 uint32_t otgen : 1; /**< OTG Function Enabled (OtgEn)
206 The application uses this bit to indicate the O2P USB core's
208 * 1'b0: Not OTG capable
209 * 1'b1: OTG Capable */
210 uint32_t pktsizewidth : 3; /**< Width of Packet Size Counters (PktSizeWidth)
218 * Others: Reserved */
219 uint32_t xfersizewidth : 4; /**< Width of Transfer Size Counters (XferSizeWidth)
224 * Others: Reserved */
226 struct cvmx_usbcx_ghwcfg3_s cn30xx;
227 struct cvmx_usbcx_ghwcfg3_s cn31xx;
228 struct cvmx_usbcx_ghwcfg3_s cn50xx;
229 struct cvmx_usbcx_ghwcfg3_s cn52xx;
230 struct cvmx_usbcx_ghwcfg3_s cn52xxp1;
231 struct cvmx_usbcx_ghwcfg3_s cn56xx;
232 struct cvmx_usbcx_ghwcfg3_s cn56xxp1;
234 typedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t;
239 * Core Interrupt Mask Register (GINTMSK)
241 * This register works with the Core Interrupt register to interrupt the application.
242 * When an interrupt bit is masked, the interrupt associated with that bit will not be generated.
243 * However, the Core Interrupt (GINTSTS) register bit corresponding to that interrupt will still be set.
244 * Mask interrupt: 1'b0, Unmask interrupt: 1'b1
246 union cvmx_usbcx_gintmsk
249 struct cvmx_usbcx_gintmsk_s
251 uint32_t wkupintmsk : 1; /**< Resume/Remote Wakeup Detected Interrupt Mask
253 uint32_t sessreqintmsk : 1; /**< Session Request/New Session Detected Interrupt Mask
255 uint32_t disconnintmsk : 1; /**< Disconnect Detected Interrupt Mask (DisconnIntMsk) */
256 uint32_t conidstschngmsk : 1; /**< Connector ID Status Change Mask (ConIDStsChngMsk) */
257 uint32_t reserved_27_27 : 1;
258 uint32_t ptxfempmsk : 1; /**< Periodic TxFIFO Empty Mask (PTxFEmpMsk) */
259 uint32_t hchintmsk : 1; /**< Host Channels Interrupt Mask (HChIntMsk) */
260 uint32_t prtintmsk : 1; /**< Host Port Interrupt Mask (PrtIntMsk) */
261 uint32_t reserved_23_23 : 1;
262 uint32_t fetsuspmsk : 1; /**< Data Fetch Suspended Mask (FetSuspMsk) */
263 uint32_t incomplpmsk : 1; /**< Incomplete Periodic Transfer Mask (incomplPMsk)
264 Incomplete Isochronous OUT Transfer Mask
266 uint32_t incompisoinmsk : 1; /**< Incomplete Isochronous IN Transfer Mask (incompISOINMsk) */
267 uint32_t oepintmsk : 1; /**< OUT Endpoints Interrupt Mask (OEPIntMsk) */
268 uint32_t inepintmsk : 1; /**< IN Endpoints Interrupt Mask (INEPIntMsk) */
269 uint32_t epmismsk : 1; /**< Endpoint Mismatch Interrupt Mask (EPMisMsk) */
270 uint32_t reserved_16_16 : 1;
271 uint32_t eopfmsk : 1; /**< End of Periodic Frame Interrupt Mask (EOPFMsk) */
272 uint32_t isooutdropmsk : 1; /**< Isochronous OUT Packet Dropped Interrupt Mask
274 uint32_t enumdonemsk : 1; /**< Enumeration Done Mask (EnumDoneMsk) */
275 uint32_t usbrstmsk : 1; /**< USB Reset Mask (USBRstMsk) */
276 uint32_t usbsuspmsk : 1; /**< USB Suspend Mask (USBSuspMsk) */
277 uint32_t erlysuspmsk : 1; /**< Early Suspend Mask (ErlySuspMsk) */
278 uint32_t i2cint : 1; /**< I2C Interrupt Mask (I2CINT) */
279 uint32_t ulpickintmsk : 1; /**< ULPI Carkit Interrupt Mask (ULPICKINTMsk)
280 I2C Carkit Interrupt Mask (I2CCKINTMsk) */
281 uint32_t goutnakeffmsk : 1; /**< Global OUT NAK Effective Mask (GOUTNakEffMsk) */
282 uint32_t ginnakeffmsk : 1; /**< Global Non-Periodic IN NAK Effective Mask (GINNakEffMsk) */
283 uint32_t nptxfempmsk : 1; /**< Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk) */
284 uint32_t rxflvlmsk : 1; /**< Receive FIFO Non-Empty Mask (RxFLvlMsk) */
285 uint32_t sofmsk : 1; /**< Start of (micro)Frame Mask (SofMsk) */
286 uint32_t otgintmsk : 1; /**< OTG Interrupt Mask (OTGIntMsk) */
287 uint32_t modemismsk : 1; /**< Mode Mismatch Interrupt Mask (ModeMisMsk) */
288 uint32_t reserved_0_0 : 1;
290 struct cvmx_usbcx_gintmsk_s cn30xx;
291 struct cvmx_usbcx_gintmsk_s cn31xx;
292 struct cvmx_usbcx_gintmsk_s cn50xx;
293 struct cvmx_usbcx_gintmsk_s cn52xx;
294 struct cvmx_usbcx_gintmsk_s cn52xxp1;
295 struct cvmx_usbcx_gintmsk_s cn56xx;
296 struct cvmx_usbcx_gintmsk_s cn56xxp1;
298 typedef union cvmx_usbcx_gintmsk cvmx_usbcx_gintmsk_t;
303 * Core Interrupt Register (GINTSTS)
305 * This register interrupts the application for system-level events in the current mode of operation
306 * (Device mode or Host mode). It is shown in Interrupt. Some of the bits in this register are valid only in Host mode,
307 * while others are valid in Device mode only. This register also indicates the current mode of operation.
308 * In order to clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit.
309 * The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these
310 * interrupts, FIFO interrupt conditions are cleared automatically.
312 union cvmx_usbcx_gintsts
315 struct cvmx_usbcx_gintsts_s
317 uint32_t wkupint : 1; /**< Resume/Remote Wakeup Detected Interrupt (WkUpInt)
318 In Device mode, this interrupt is asserted when a resume is
319 detected on the USB. In Host mode, this interrupt is asserted
320 when a remote wakeup is detected on the USB.
321 For more information on how to use this interrupt, see "Partial
322 Power-Down and Clock Gating Programming Model" on
324 uint32_t sessreqint : 1; /**< Session Request/New Session Detected Interrupt (SessReqInt)
325 In Host mode, this interrupt is asserted when a session request
326 is detected from the device. In Device mode, this interrupt is
327 asserted when the utmiotg_bvalid signal goes high.
328 For more information on how to use this interrupt, see "Partial
329 Power-Down and Clock Gating Programming Model" on
331 uint32_t disconnint : 1; /**< Disconnect Detected Interrupt (DisconnInt)
332 Asserted when a device disconnect is detected. */
333 uint32_t conidstschng : 1; /**< Connector ID Status Change (ConIDStsChng)
334 The core sets this bit when there is a change in connector ID
336 uint32_t reserved_27_27 : 1;
337 uint32_t ptxfemp : 1; /**< Periodic TxFIFO Empty (PTxFEmp)
338 Asserted when the Periodic Transmit FIFO is either half or
339 completely empty and there is space for at least one entry to be
340 written in the Periodic Request Queue. The half or completely
341 empty status is determined by the Periodic TxFIFO Empty Level
342 bit in the Core AHB Configuration register
343 (GAHBCFG.PTxFEmpLvl). */
344 uint32_t hchint : 1; /**< Host Channels Interrupt (HChInt)
345 The core sets this bit to indicate that an interrupt is pending on
346 one of the channels of the core (in Host mode). The application
347 must read the Host All Channels Interrupt (HAINT) register to
348 determine the exact number of the channel on which the
349 interrupt occurred, and then read the corresponding Host
350 Channel-n Interrupt (HCINTn) register to determine the exact
351 cause of the interrupt. The application must clear the
352 appropriate status bit in the HCINTn register to clear this bit. */
353 uint32_t prtint : 1; /**< Host Port Interrupt (PrtInt)
354 The core sets this bit to indicate a change in port status of one
355 of the O2P USB core ports in Host mode. The application must
356 read the Host Port Control and Status (HPRT) register to
357 determine the exact event that caused this interrupt. The
358 application must clear the appropriate status bit in the Host Port
359 Control and Status register to clear this bit. */
360 uint32_t reserved_23_23 : 1;
361 uint32_t fetsusp : 1; /**< Data Fetch Suspended (FetSusp)
362 This interrupt is valid only in DMA mode. This interrupt indicates
363 that the core has stopped fetching data for IN endpoints due to
364 the unavailability of TxFIFO space or Request Queue space.
365 This interrupt is used by the application for an endpoint
366 mismatch algorithm. */
367 uint32_t incomplp : 1; /**< Incomplete Periodic Transfer (incomplP)
368 In Host mode, the core sets this interrupt bit when there are
369 incomplete periodic transactions still pending which are
370 scheduled for the current microframe.
371 Incomplete Isochronous OUT Transfer (incompISOOUT)
372 The Device mode, the core sets this interrupt to indicate that
373 there is at least one isochronous OUT endpoint on which the
374 transfer is not completed in the current microframe. This
375 interrupt is asserted along with the End of Periodic Frame
376 Interrupt (EOPF) bit in this register. */
377 uint32_t incompisoin : 1; /**< Incomplete Isochronous IN Transfer (incompISOIN)
378 The core sets this interrupt to indicate that there is at least one
379 isochronous IN endpoint on which the transfer is not completed
380 in the current microframe. This interrupt is asserted along with
381 the End of Periodic Frame Interrupt (EOPF) bit in this register. */
382 uint32_t oepint : 1; /**< OUT Endpoints Interrupt (OEPInt)
383 The core sets this bit to indicate that an interrupt is pending on
384 one of the OUT endpoints of the core (in Device mode). The
385 application must read the Device All Endpoints Interrupt
386 (DAINT) register to determine the exact number of the OUT
387 endpoint on which the interrupt occurred, and then read the
388 corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
389 register to determine the exact cause of the interrupt. The
390 application must clear the appropriate status bit in the
391 corresponding DOEPINTn register to clear this bit. */
392 uint32_t iepint : 1; /**< IN Endpoints Interrupt (IEPInt)
393 The core sets this bit to indicate that an interrupt is pending on
394 one of the IN endpoints of the core (in Device mode). The
395 application must read the Device All Endpoints Interrupt
396 (DAINT) register to determine the exact number of the IN
397 endpoint on which the interrupt occurred, and then read the
398 corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
399 register to determine the exact cause of the interrupt. The
400 application must clear the appropriate status bit in the
401 corresponding DIEPINTn register to clear this bit. */
402 uint32_t epmis : 1; /**< Endpoint Mismatch Interrupt (EPMis)
403 Indicates that an IN token has been received for a non-periodic
404 endpoint, but the data for another endpoint is present in the top
405 of the Non-Periodic Transmit FIFO and the IN endpoint
406 mismatch count programmed by the application has expired. */
407 uint32_t reserved_16_16 : 1;
408 uint32_t eopf : 1; /**< End of Periodic Frame Interrupt (EOPF)
409 Indicates that the period specified in the Periodic Frame Interval
410 field of the Device Configuration register (DCFG.PerFrInt) has
411 been reached in the current microframe. */
412 uint32_t isooutdrop : 1; /**< Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)
413 The core sets this bit when it fails to write an isochronous OUT
414 packet into the RxFIFO because the RxFIFO doesn't have
415 enough space to accommodate a maximum packet size packet
416 for the isochronous OUT endpoint. */
417 uint32_t enumdone : 1; /**< Enumeration Done (EnumDone)
418 The core sets this bit to indicate that speed enumeration is
419 complete. The application must read the Device Status (DSTS)
420 register to obtain the enumerated speed. */
421 uint32_t usbrst : 1; /**< USB Reset (USBRst)
422 The core sets this bit to indicate that a reset is detected on the
424 uint32_t usbsusp : 1; /**< USB Suspend (USBSusp)
425 The core sets this bit to indicate that a suspend was detected
426 on the USB. The core enters the Suspended state when there
427 is no activity on the phy_line_state_i signal for an extended
429 uint32_t erlysusp : 1; /**< Early Suspend (ErlySusp)
430 The core sets this bit to indicate that an Idle state has been
431 detected on the USB for 3 ms. */
432 uint32_t i2cint : 1; /**< I2C Interrupt (I2CINT)
433 This bit is always 0x0. */
434 uint32_t ulpickint : 1; /**< ULPI Carkit Interrupt (ULPICKINT)
435 This bit is always 0x0. */
436 uint32_t goutnakeff : 1; /**< Global OUT NAK Effective (GOUTNakEff)
437 Indicates that the Set Global OUT NAK bit in the Device Control
438 register (DCTL.SGOUTNak), set by the application, has taken
439 effect in the core. This bit can be cleared by writing the Clear
440 Global OUT NAK bit in the Device Control register
442 uint32_t ginnakeff : 1; /**< Global IN Non-Periodic NAK Effective (GINNakEff)
443 Indicates that the Set Global Non-Periodic IN NAK bit in the
444 Device Control register (DCTL.SGNPInNak), set by the
445 application, has taken effect in the core. That is, the core has
446 sampled the Global IN NAK bit set by the application. This bit
447 can be cleared by clearing the Clear Global Non-Periodic IN
448 NAK bit in the Device Control register (DCTL.CGNPInNak).
449 This interrupt does not necessarily mean that a NAK handshake
450 is sent out on the USB. The STALL bit takes precedence over
452 uint32_t nptxfemp : 1; /**< Non-Periodic TxFIFO Empty (NPTxFEmp)
453 This interrupt is asserted when the Non-Periodic TxFIFO is
454 either half or completely empty, and there is space for at least
455 one entry to be written to the Non-Periodic Transmit Request
456 Queue. The half or completely empty status is determined by
457 the Non-Periodic TxFIFO Empty Level bit in the Core AHB
458 Configuration register (GAHBCFG.NPTxFEmpLvl). */
459 uint32_t rxflvl : 1; /**< RxFIFO Non-Empty (RxFLvl)
460 Indicates that there is at least one packet pending to be read
462 uint32_t sof : 1; /**< Start of (micro)Frame (Sof)
463 In Host mode, the core sets this bit to indicate that an SOF
464 (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
465 USB. The application must write a 1 to this bit to clear the
467 In Device mode, in the core sets this bit to indicate that an SOF
468 token has been received on the USB. The application can read
469 the Device Status register to get the current (micro)frame
470 number. This interrupt is seen only when the core is operating
471 at either HS or FS. */
472 uint32_t otgint : 1; /**< OTG Interrupt (OTGInt)
473 The core sets this bit to indicate an OTG protocol event. The
474 application must read the OTG Interrupt Status (GOTGINT)
475 register to determine the exact event that caused this interrupt.
476 The application must clear the appropriate status bit in the
477 GOTGINT register to clear this bit. */
478 uint32_t modemis : 1; /**< Mode Mismatch Interrupt (ModeMis)
479 The core sets this bit when the application is trying to access:
480 * A Host mode register, when the core is operating in Device
482 * A Device mode register, when the core is operating in Host
484 The register access is completed on the AHB with an OKAY
485 response, but is ignored by the core internally and doesn't
486 affect the operation of the core. */
487 uint32_t curmod : 1; /**< Current Mode of Operation (CurMod)
488 Indicates the current mode of operation.
492 struct cvmx_usbcx_gintsts_s cn30xx;
493 struct cvmx_usbcx_gintsts_s cn31xx;
494 struct cvmx_usbcx_gintsts_s cn50xx;
495 struct cvmx_usbcx_gintsts_s cn52xx;
496 struct cvmx_usbcx_gintsts_s cn52xxp1;
497 struct cvmx_usbcx_gintsts_s cn56xx;
498 struct cvmx_usbcx_gintsts_s cn56xxp1;
500 typedef union cvmx_usbcx_gintsts cvmx_usbcx_gintsts_t;
503 * cvmx_usbc#_gnptxfsiz
505 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
507 * The application can program the RAM size and the memory start address for the Non-Periodic TxFIFO.
509 union cvmx_usbcx_gnptxfsiz
512 struct cvmx_usbcx_gnptxfsiz_s
514 uint32_t nptxfdep : 16; /**< Non-Periodic TxFIFO Depth (NPTxFDep)
515 This value is in terms of 32-bit words.
517 Maximum value is 32768 */
518 uint32_t nptxfstaddr : 16; /**< Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
519 This field contains the memory start address for Non-Periodic
520 Transmit FIFO RAM. */
522 struct cvmx_usbcx_gnptxfsiz_s cn30xx;
523 struct cvmx_usbcx_gnptxfsiz_s cn31xx;
524 struct cvmx_usbcx_gnptxfsiz_s cn50xx;
525 struct cvmx_usbcx_gnptxfsiz_s cn52xx;
526 struct cvmx_usbcx_gnptxfsiz_s cn52xxp1;
527 struct cvmx_usbcx_gnptxfsiz_s cn56xx;
528 struct cvmx_usbcx_gnptxfsiz_s cn56xxp1;
530 typedef union cvmx_usbcx_gnptxfsiz cvmx_usbcx_gnptxfsiz_t;
533 * cvmx_usbc#_gnptxsts
535 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
537 * This read-only register contains the free space information for the Non-Periodic TxFIFO and
538 * the Non-Periodic Transmit Request Queue
540 union cvmx_usbcx_gnptxsts
543 struct cvmx_usbcx_gnptxsts_s
545 uint32_t reserved_31_31 : 1;
546 uint32_t nptxqtop : 7; /**< Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
547 Entry in the Non-Periodic Tx Request Queue that is currently
548 being processed by the MAC.
549 * Bits [30:27]: Channel/endpoint number
551 - 2'b00: IN/OUT token
552 - 2'b01: Zero-length transmit packet (device IN/host OUT)
553 - 2'b10: PING/CSPLIT token
554 - 2'b11: Channel halt command
555 * Bit [24]: Terminate (last entry for selected channel/endpoint) */
556 uint32_t nptxqspcavail : 8; /**< Non-Periodic Transmit Request Queue Space Available
558 Indicates the amount of free space available in the Non-
559 Periodic Transmit Request Queue. This queue holds both IN
560 and OUT requests in Host mode. Device mode has only IN
562 * 8'h0: Non-Periodic Transmit Request Queue is full
563 * 8'h1: 1 location available
564 * 8'h2: 2 locations available
565 * n: n locations available (0..8)
566 * Others: Reserved */
567 uint32_t nptxfspcavail : 16; /**< Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
568 Indicates the amount of free space available in the Non-
570 Values are in terms of 32-bit words.
571 * 16'h0: Non-Periodic TxFIFO is full
572 * 16'h1: 1 word available
573 * 16'h2: 2 words available
574 * 16'hn: n words available (where 0..32768)
575 * 16'h8000: 32768 words available
576 * Others: Reserved */
578 struct cvmx_usbcx_gnptxsts_s cn30xx;
579 struct cvmx_usbcx_gnptxsts_s cn31xx;
580 struct cvmx_usbcx_gnptxsts_s cn50xx;
581 struct cvmx_usbcx_gnptxsts_s cn52xx;
582 struct cvmx_usbcx_gnptxsts_s cn52xxp1;
583 struct cvmx_usbcx_gnptxsts_s cn56xx;
584 struct cvmx_usbcx_gnptxsts_s cn56xxp1;
586 typedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t;
591 * Core Reset Register (GRSTCTL)
593 * The application uses this register to reset various hardware features inside the core.
595 union cvmx_usbcx_grstctl
598 struct cvmx_usbcx_grstctl_s
600 uint32_t ahbidle : 1; /**< AHB Master Idle (AHBIdle)
601 Indicates that the AHB Master State Machine is in the IDLE
603 uint32_t dmareq : 1; /**< DMA Request Signal (DMAReq)
604 Indicates that the DMA request is in progress. Used for debug. */
605 uint32_t reserved_11_29 : 19;
606 uint32_t txfnum : 5; /**< TxFIFO Number (TxFNum)
607 This is the FIFO number that must be flushed using the TxFIFO
608 Flush bit. This field must not be changed until the core clears
609 the TxFIFO Flush bit.
610 * 5'h0: Non-Periodic TxFIFO flush
611 * 5'h1: Periodic TxFIFO 1 flush in Device mode or Periodic
612 TxFIFO flush in Host mode
613 * 5'h2: Periodic TxFIFO 2 flush in Device mode
615 * 5'hF: Periodic TxFIFO 15 flush in Device mode
616 * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
618 uint32_t txfflsh : 1; /**< TxFIFO Flush (TxFFlsh)
619 This bit selectively flushes a single or all transmit FIFOs, but
620 cannot do so if the core is in the midst of a transaction.
621 The application must only write this bit after checking that the
622 core is neither writing to the TxFIFO nor reading from the
624 The application must wait until the core clears this bit before
625 performing any operations. This bit takes 8 clocks (of phy_clk or
626 hclk, whichever is slower) to clear. */
627 uint32_t rxfflsh : 1; /**< RxFIFO Flush (RxFFlsh)
628 The application can flush the entire RxFIFO using this bit, but
629 must first ensure that the core is not in the middle of a
631 The application must only write to this bit after checking that the
632 core is neither reading from the RxFIFO nor writing to the
634 The application must wait until the bit is cleared before
635 performing any other operations. This bit will take 8 clocks
636 (slowest of PHY or AHB clock) to clear. */
637 uint32_t intknqflsh : 1; /**< IN Token Sequence Learning Queue Flush (INTknQFlsh)
638 The application writes this bit to flush the IN Token Sequence
640 uint32_t frmcntrrst : 1; /**< Host Frame Counter Reset (FrmCntrRst)
641 The application writes this bit to reset the (micro)frame number
642 counter inside the core. When the (micro)frame counter is reset,
643 the subsequent SOF sent out by the core will have a
644 (micro)frame number of 0. */
645 uint32_t hsftrst : 1; /**< HClk Soft Reset (HSftRst)
646 The application uses this bit to flush the control logic in the AHB
647 Clock domain. Only AHB Clock Domain pipelines are reset.
648 * FIFOs are not flushed with this bit.
649 * All state machines in the AHB clock domain are reset to the
650 Idle state after terminating the transactions on the AHB,
651 following the protocol.
652 * CSR control bits used by the AHB clock domain state
653 machines are cleared.
654 * To clear this interrupt, status mask bits that control the
655 interrupt status and are generated by the AHB clock domain
656 state machine are cleared.
657 * Because interrupt status bits are not cleared, the application
658 can get the status of any core events that occurred after it set
660 This is a self-clearing bit that the core clears after all necessary
661 logic is reset in the core. This may take several clocks,
662 depending on the core's current state. */
663 uint32_t csftrst : 1; /**< Core Soft Reset (CSftRst)
664 Resets the hclk and phy_clock domains as follows:
665 * Clears the interrupts and all the CSR registers except the
666 following register bits:
667 - PCGCCTL.RstPdwnModule
670 - PCGCCTL.StopPPhyLPwrClkSelclk
671 - GUSBCFG.PhyLPwrClkSel
675 - GUSBCFG.ULPI_UTMI_Sel
679 * All module state machines (except the AHB Slave Unit) are
680 reset to the IDLE state, and all the transmit FIFOs and the
681 receive FIFO are flushed.
682 * Any transactions on the AHB Master are terminated as soon
683 as possible, after gracefully completing the last data phase of
684 an AHB transfer. Any transactions on the USB are terminated
686 The application can write to this bit any time it wants to reset
687 the core. This is a self-clearing bit and the core clears this bit
688 after all the necessary logic is reset in the core, which may take
689 several clocks, depending on the current state of the core.
690 Once this bit is cleared software should wait at least 3 PHY
691 clocks before doing any access to the PHY domain
692 (synchronization delay). Software should also should check that
693 bit 31 of this register is 1 (AHB Master is IDLE) before starting
695 Typically software reset is used during software development
696 and also when you dynamically change the PHY selection bits
697 in the USB configuration registers listed above. When you
698 change the PHY, the corresponding clock for the PHY is
699 selected and used in the PHY domain. Once a new clock is
700 selected, the PHY domain has to be reset for proper operation. */
702 struct cvmx_usbcx_grstctl_s cn30xx;
703 struct cvmx_usbcx_grstctl_s cn31xx;
704 struct cvmx_usbcx_grstctl_s cn50xx;
705 struct cvmx_usbcx_grstctl_s cn52xx;
706 struct cvmx_usbcx_grstctl_s cn52xxp1;
707 struct cvmx_usbcx_grstctl_s cn56xx;
708 struct cvmx_usbcx_grstctl_s cn56xxp1;
710 typedef union cvmx_usbcx_grstctl cvmx_usbcx_grstctl_t;
715 * Receive FIFO Size Register (GRXFSIZ)
717 * The application can program the RAM size that must be allocated to the RxFIFO.
719 union cvmx_usbcx_grxfsiz
722 struct cvmx_usbcx_grxfsiz_s
724 uint32_t reserved_16_31 : 16;
725 uint32_t rxfdep : 16; /**< RxFIFO Depth (RxFDep)
726 This value is in terms of 32-bit words.
727 * Minimum value is 16
728 * Maximum value is 32768 */
730 struct cvmx_usbcx_grxfsiz_s cn30xx;
731 struct cvmx_usbcx_grxfsiz_s cn31xx;
732 struct cvmx_usbcx_grxfsiz_s cn50xx;
733 struct cvmx_usbcx_grxfsiz_s cn52xx;
734 struct cvmx_usbcx_grxfsiz_s cn52xxp1;
735 struct cvmx_usbcx_grxfsiz_s cn56xx;
736 struct cvmx_usbcx_grxfsiz_s cn56xxp1;
738 typedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t;
741 * cvmx_usbc#_grxstsph
743 * Receive Status Read and Pop Register, Host Mode (GRXSTSPH)
745 * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
746 * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSPD instead.
747 * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
748 * The offset difference shown in this document is for software clarity and is actually ignored by the
751 union cvmx_usbcx_grxstsph
754 struct cvmx_usbcx_grxstsph_s
756 uint32_t reserved_21_31 : 11;
757 uint32_t pktsts : 4; /**< Packet Status (PktSts)
758 Indicates the status of the received packet
759 * 4'b0010: IN data packet received
760 * 4'b0011: IN transfer completed (triggers an interrupt)
761 * 4'b0101: Data toggle error (triggers an interrupt)
762 * 4'b0111: Channel halted (triggers an interrupt)
763 * Others: Reserved */
764 uint32_t dpid : 2; /**< Data PID (DPID)
769 uint32_t bcnt : 11; /**< Byte Count (BCnt)
770 Indicates the byte count of the received IN data packet */
771 uint32_t chnum : 4; /**< Channel Number (ChNum)
772 Indicates the channel number to which the current received
775 struct cvmx_usbcx_grxstsph_s cn30xx;
776 struct cvmx_usbcx_grxstsph_s cn31xx;
777 struct cvmx_usbcx_grxstsph_s cn50xx;
778 struct cvmx_usbcx_grxstsph_s cn52xx;
779 struct cvmx_usbcx_grxstsph_s cn52xxp1;
780 struct cvmx_usbcx_grxstsph_s cn56xx;
781 struct cvmx_usbcx_grxstsph_s cn56xxp1;
783 typedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t;
788 * Core USB Configuration Register (GUSBCFG)
790 * This register can be used to configure the core after power-on or a changing to Host mode or Device mode.
791 * It contains USB and USB-PHY related configuration parameters. The application must program this register
792 * before starting any transactions on either the AHB or the USB.
793 * Do not make changes to this register after the initial programming.
795 union cvmx_usbcx_gusbcfg
798 struct cvmx_usbcx_gusbcfg_s
800 uint32_t reserved_17_31 : 15;
801 uint32_t otgi2csel : 1; /**< UTMIFS or I2C Interface Select (OtgI2CSel)
802 This bit is always 0x0. */
803 uint32_t phylpwrclksel : 1; /**< PHY Low-Power Clock Select (PhyLPwrClkSel)
804 Software should set this bit to 0x0.
805 Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
806 FS and LS modes, the PHY can usually operate on a 48-MHz
808 * 1'b0: 480-MHz Internal PLL clock
809 * 1'b1: 48-MHz External Clock
810 In 480 MHz mode, the UTMI interface operates at either 60 or
811 30-MHz, depending upon whether 8- or 16-bit data width is
812 selected. In 48-MHz mode, the UTMI interface operates at 48
813 MHz in FS mode and at either 48 or 6 MHz in LS mode
814 (depending on the PHY vendor).
815 This bit drives the utmi_fsls_low_power core output signal, and
816 is valid only for UTMI+ PHYs. */
817 uint32_t reserved_14_14 : 1;
818 uint32_t usbtrdtim : 4; /**< USB Turnaround Time (USBTrdTim)
819 Sets the turnaround time in PHY clocks.
820 Specifies the response time for a MAC request to the Packet
821 FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
822 This must be programmed to 0x5. */
823 uint32_t hnpcap : 1; /**< HNP-Capable (HNPCap)
824 This bit is always 0x0. */
825 uint32_t srpcap : 1; /**< SRP-Capable (SRPCap)
826 This bit is always 0x0. */
827 uint32_t ddrsel : 1; /**< ULPI DDR Select (DDRSel)
828 Software should set this bit to 0x0. */
829 uint32_t physel : 1; /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
830 Software should set this bit to 0x0. */
831 uint32_t fsintf : 1; /**< Full-Speed Serial Interface Select (FSIntf)
832 Software should set this bit to 0x0. */
833 uint32_t ulpi_utmi_sel : 1; /**< ULPI or UTMI+ Select (ULPI_UTMI_Sel)
834 This bit is always 0x0. */
835 uint32_t phyif : 1; /**< PHY Interface (PHYIf)
836 This bit is always 0x1. */
837 uint32_t toutcal : 3; /**< HS/FS Timeout Calibration (TOutCal)
838 The number of PHY clocks that the application programs in this
839 field is added to the high-speed/full-speed interpacket timeout
840 duration in the core to account for any additional delays
841 introduced by the PHY. This may be required, since the delay
842 introduced by the PHY in generating the linestate condition may
843 vary from one PHY to another.
844 The USB standard timeout value for high-speed operation is
845 736 to 816 (inclusive) bit times. The USB standard timeout
846 value for full-speed operation is 16 to 18 (inclusive) bit times.
847 The application must program this field based on the speed of
848 enumeration. The number of bit times added per PHY clock are:
849 High-speed operation:
850 * One 30-MHz PHY clock = 16 bit times
851 * One 60-MHz PHY clock = 8 bit times
852 Full-speed operation:
853 * One 30-MHz PHY clock = 0.4 bit times
854 * One 60-MHz PHY clock = 0.2 bit times
855 * One 48-MHz PHY clock = 0.25 bit times */
857 struct cvmx_usbcx_gusbcfg_s cn30xx;
858 struct cvmx_usbcx_gusbcfg_s cn31xx;
859 struct cvmx_usbcx_gusbcfg_s cn50xx;
860 struct cvmx_usbcx_gusbcfg_s cn52xx;
861 struct cvmx_usbcx_gusbcfg_s cn52xxp1;
862 struct cvmx_usbcx_gusbcfg_s cn56xx;
863 struct cvmx_usbcx_gusbcfg_s cn56xxp1;
865 typedef union cvmx_usbcx_gusbcfg cvmx_usbcx_gusbcfg_t;
870 * Host All Channels Interrupt Register (HAINT)
872 * When a significant event occurs on a channel, the Host All Channels Interrupt register
873 * interrupts the application using the Host Channels Interrupt bit of the Core Interrupt
874 * register (GINTSTS.HChInt). This is shown in Interrupt . There is one interrupt bit per
875 * channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the
876 * application sets and clears bits in the corresponding Host Channel-n Interrupt register.
878 union cvmx_usbcx_haint
881 struct cvmx_usbcx_haint_s
883 uint32_t reserved_16_31 : 16;
884 uint32_t haint : 16; /**< Channel Interrupts (HAINT)
885 One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15 */
887 struct cvmx_usbcx_haint_s cn30xx;
888 struct cvmx_usbcx_haint_s cn31xx;
889 struct cvmx_usbcx_haint_s cn50xx;
890 struct cvmx_usbcx_haint_s cn52xx;
891 struct cvmx_usbcx_haint_s cn52xxp1;
892 struct cvmx_usbcx_haint_s cn56xx;
893 struct cvmx_usbcx_haint_s cn56xxp1;
895 typedef union cvmx_usbcx_haint cvmx_usbcx_haint_t;
898 * cvmx_usbc#_haintmsk
900 * Host All Channels Interrupt Mask Register (HAINTMSK)
902 * The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt
903 * register to interrupt the application when an event occurs on a channel. There is one
904 * interrupt mask bit per channel, up to a maximum of 16 bits.
905 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
907 union cvmx_usbcx_haintmsk
910 struct cvmx_usbcx_haintmsk_s
912 uint32_t reserved_16_31 : 16;
913 uint32_t haintmsk : 16; /**< Channel Interrupt Mask (HAINTMsk)
914 One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 */
916 struct cvmx_usbcx_haintmsk_s cn30xx;
917 struct cvmx_usbcx_haintmsk_s cn31xx;
918 struct cvmx_usbcx_haintmsk_s cn50xx;
919 struct cvmx_usbcx_haintmsk_s cn52xx;
920 struct cvmx_usbcx_haintmsk_s cn52xxp1;
921 struct cvmx_usbcx_haintmsk_s cn56xx;
922 struct cvmx_usbcx_haintmsk_s cn56xxp1;
924 typedef union cvmx_usbcx_haintmsk cvmx_usbcx_haintmsk_t;
929 * Host Channel-n Characteristics Register (HCCHAR)
932 union cvmx_usbcx_hccharx
935 struct cvmx_usbcx_hccharx_s
937 uint32_t chena : 1; /**< Channel Enable (ChEna)
938 This field is set by the application and cleared by the OTG host.
939 * 1'b0: Channel disabled
940 * 1'b1: Channel enabled */
941 uint32_t chdis : 1; /**< Channel Disable (ChDis)
942 The application sets this bit to stop transmitting/receiving data
943 on a channel, even before the transfer for that channel is
944 complete. The application must wait for the Channel Disabled
945 interrupt before treating the channel as disabled. */
946 uint32_t oddfrm : 1; /**< Odd Frame (OddFrm)
947 This field is set (reset) by the application to indicate that the
948 OTG host must perform a transfer in an odd (micro)frame. This
949 field is applicable for only periodic (isochronous and interrupt)
951 * 1'b0: Even (micro)frame
952 * 1'b1: Odd (micro)frame */
953 uint32_t devaddr : 7; /**< Device Address (DevAddr)
954 This field selects the specific device serving as the data source
956 uint32_t ec : 2; /**< Multi Count (MC) / Error Count (EC)
957 When the Split Enable bit of the Host Channel-n Split Control
958 register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates
959 to the host the number of transactions that should be executed
960 per microframe for this endpoint.
961 * 2'b00: Reserved. This field yields undefined results.
962 * 2'b01: 1 transaction
963 * 2'b10: 2 transactions to be issued for this endpoint per
965 * 2'b11: 3 transactions to be issued for this endpoint per
967 When HCSPLTn.SpltEna is set (1'b1), this field indicates the
968 number of immediate retries to be performed for a periodic split
969 transactions on transaction errors. This field must be set to at
971 uint32_t eptype : 2; /**< Endpoint Type (EPType)
972 Indicates the transfer type selected.
976 * 2'b11: Interrupt */
977 uint32_t lspddev : 1; /**< Low-Speed Device (LSpdDev)
978 This field is set by the application to indicate that this channel is
979 communicating to a low-speed device. */
980 uint32_t reserved_16_16 : 1;
981 uint32_t epdir : 1; /**< Endpoint Direction (EPDir)
982 Indicates whether the transaction is IN or OUT.
985 uint32_t epnum : 4; /**< Endpoint Number (EPNum)
986 Indicates the endpoint number on the device serving as the
987 data source or sink. */
988 uint32_t mps : 11; /**< Maximum Packet Size (MPS)
989 Indicates the maximum packet size of the associated endpoint. */
991 struct cvmx_usbcx_hccharx_s cn30xx;
992 struct cvmx_usbcx_hccharx_s cn31xx;
993 struct cvmx_usbcx_hccharx_s cn50xx;
994 struct cvmx_usbcx_hccharx_s cn52xx;
995 struct cvmx_usbcx_hccharx_s cn52xxp1;
996 struct cvmx_usbcx_hccharx_s cn56xx;
997 struct cvmx_usbcx_hccharx_s cn56xxp1;
999 typedef union cvmx_usbcx_hccharx cvmx_usbcx_hccharx_t;
1004 * Host Configuration Register (HCFG)
1006 * This register configures the core after power-on. Do not make changes to this register after initializing the host.
1008 union cvmx_usbcx_hcfg
1011 struct cvmx_usbcx_hcfg_s
1013 uint32_t reserved_3_31 : 29;
1014 uint32_t fslssupp : 1; /**< FS- and LS-Only Support (FSLSSupp)
1015 The application uses this bit to control the core's enumeration
1016 speed. Using this bit, the application can make the core
1017 enumerate as a FS host, even if the connected device supports
1018 HS traffic. Do not make changes to this field after initial
1020 * 1'b0: HS/FS/LS, based on the maximum speed supported by
1021 the connected device
1022 * 1'b1: FS/LS-only, even if the connected device can support HS */
1023 uint32_t fslspclksel : 2; /**< FS/LS PHY Clock Select (FSLSPclkSel)
1024 When the core is in FS Host mode
1025 * 2'b00: PHY clock is running at 30/60 MHz
1026 * 2'b01: PHY clock is running at 48 MHz
1028 When the core is in LS Host mode
1029 * 2'b00: PHY clock is running at 30/60 MHz. When the
1030 UTMI+/ULPI PHY Low Power mode is not selected, use
1032 * 2'b01: PHY clock is running at 48 MHz. When the UTMI+
1033 PHY Low Power mode is selected, use 48MHz if the PHY
1034 supplies a 48 MHz clock during LS mode.
1035 * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
1036 use 6 MHz when the UTMI+ PHY Low Power mode is
1037 selected and the PHY supplies a 6 MHz clock during LS
1038 mode. If you select a 6 MHz clock during LS mode, you must
1040 * 2'b11: Reserved */
1042 struct cvmx_usbcx_hcfg_s cn30xx;
1043 struct cvmx_usbcx_hcfg_s cn31xx;
1044 struct cvmx_usbcx_hcfg_s cn50xx;
1045 struct cvmx_usbcx_hcfg_s cn52xx;
1046 struct cvmx_usbcx_hcfg_s cn52xxp1;
1047 struct cvmx_usbcx_hcfg_s cn56xx;
1048 struct cvmx_usbcx_hcfg_s cn56xxp1;
1050 typedef union cvmx_usbcx_hcfg cvmx_usbcx_hcfg_t;
1055 * Host Channel-n Interrupt Register (HCINT)
1057 * This register indicates the status of a channel with respect to USB- and AHB-related events.
1058 * The application must read this register when the Host Channels Interrupt bit of the Core Interrupt
1059 * register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read
1060 * the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n
1061 * Interrupt register. The application must clear the appropriate bit in this register to clear the
1062 * corresponding bits in the HAINT and GINTSTS registers.
1064 union cvmx_usbcx_hcintx
1067 struct cvmx_usbcx_hcintx_s
1069 uint32_t reserved_11_31 : 21;
1070 uint32_t datatglerr : 1; /**< Data Toggle Error (DataTglErr) */
1071 uint32_t frmovrun : 1; /**< Frame Overrun (FrmOvrun) */
1072 uint32_t bblerr : 1; /**< Babble Error (BblErr) */
1073 uint32_t xacterr : 1; /**< Transaction Error (XactErr) */
1074 uint32_t nyet : 1; /**< NYET Response Received Interrupt (NYET) */
1075 uint32_t ack : 1; /**< ACK Response Received Interrupt (ACK) */
1076 uint32_t nak : 1; /**< NAK Response Received Interrupt (NAK) */
1077 uint32_t stall : 1; /**< STALL Response Received Interrupt (STALL) */
1078 uint32_t ahberr : 1; /**< This bit is always 0x0. */
1079 uint32_t chhltd : 1; /**< Channel Halted (ChHltd)
1080 Indicates the transfer completed abnormally either because of
1081 any USB transaction error or in response to disable request by
1083 uint32_t xfercompl : 1; /**< Transfer Completed (XferCompl)
1084 Transfer completed normally without any errors. */
1086 struct cvmx_usbcx_hcintx_s cn30xx;
1087 struct cvmx_usbcx_hcintx_s cn31xx;
1088 struct cvmx_usbcx_hcintx_s cn50xx;
1089 struct cvmx_usbcx_hcintx_s cn52xx;
1090 struct cvmx_usbcx_hcintx_s cn52xxp1;
1091 struct cvmx_usbcx_hcintx_s cn56xx;
1092 struct cvmx_usbcx_hcintx_s cn56xxp1;
1094 typedef union cvmx_usbcx_hcintx cvmx_usbcx_hcintx_t;
1097 * cvmx_usbc#_hcintmsk#
1099 * Host Channel-n Interrupt Mask Register (HCINTMSKn)
1101 * This register reflects the mask for each channel status described in the previous section.
1102 * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
1104 union cvmx_usbcx_hcintmskx
1107 struct cvmx_usbcx_hcintmskx_s
1109 uint32_t reserved_11_31 : 21;
1110 uint32_t datatglerrmsk : 1; /**< Data Toggle Error Mask (DataTglErrMsk) */
1111 uint32_t frmovrunmsk : 1; /**< Frame Overrun Mask (FrmOvrunMsk) */
1112 uint32_t bblerrmsk : 1; /**< Babble Error Mask (BblErrMsk) */
1113 uint32_t xacterrmsk : 1; /**< Transaction Error Mask (XactErrMsk) */
1114 uint32_t nyetmsk : 1; /**< NYET Response Received Interrupt Mask (NyetMsk) */
1115 uint32_t ackmsk : 1; /**< ACK Response Received Interrupt Mask (AckMsk) */
1116 uint32_t nakmsk : 1; /**< NAK Response Received Interrupt Mask (NakMsk) */
1117 uint32_t stallmsk : 1; /**< STALL Response Received Interrupt Mask (StallMsk) */
1118 uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */
1119 uint32_t chhltdmsk : 1; /**< Channel Halted Mask (ChHltdMsk) */
1120 uint32_t xfercomplmsk : 1; /**< Transfer Completed Mask (XferComplMsk) */
1122 struct cvmx_usbcx_hcintmskx_s cn30xx;
1123 struct cvmx_usbcx_hcintmskx_s cn31xx;
1124 struct cvmx_usbcx_hcintmskx_s cn50xx;
1125 struct cvmx_usbcx_hcintmskx_s cn52xx;
1126 struct cvmx_usbcx_hcintmskx_s cn52xxp1;
1127 struct cvmx_usbcx_hcintmskx_s cn56xx;
1128 struct cvmx_usbcx_hcintmskx_s cn56xxp1;
1130 typedef union cvmx_usbcx_hcintmskx cvmx_usbcx_hcintmskx_t;
1133 * cvmx_usbc#_hcsplt#
1135 * Host Channel-n Split Control Register (HCSPLT)
1138 union cvmx_usbcx_hcspltx
1141 struct cvmx_usbcx_hcspltx_s
1143 uint32_t spltena : 1; /**< Split Enable (SpltEna)
1144 The application sets this field to indicate that this channel is
1145 enabled to perform split transactions. */
1146 uint32_t reserved_17_30 : 14;
1147 uint32_t compsplt : 1; /**< Do Complete Split (CompSplt)
1148 The application sets this field to request the OTG host to
1149 perform a complete split transaction. */
1150 uint32_t xactpos : 2; /**< Transaction Position (XactPos)
1151 This field is used to determine whether to send all, first, middle,
1152 or last payloads with each OUT transaction.
1153 * 2'b11: All. This is the entire data payload is of this transaction
1154 (which is less than or equal to 188 bytes).
1155 * 2'b10: Begin. This is the first data payload of this transaction
1156 (which is larger than 188 bytes).
1157 * 2'b00: Mid. This is the middle payload of this transaction
1158 (which is larger than 188 bytes).
1159 * 2'b01: End. This is the last payload of this transaction (which
1160 is larger than 188 bytes). */
1161 uint32_t hubaddr : 7; /**< Hub Address (HubAddr)
1162 This field holds the device address of the transaction
1163 translator's hub. */
1164 uint32_t prtaddr : 7; /**< Port Address (PrtAddr)
1165 This field is the port number of the recipient transaction
1168 struct cvmx_usbcx_hcspltx_s cn30xx;
1169 struct cvmx_usbcx_hcspltx_s cn31xx;
1170 struct cvmx_usbcx_hcspltx_s cn50xx;
1171 struct cvmx_usbcx_hcspltx_s cn52xx;
1172 struct cvmx_usbcx_hcspltx_s cn52xxp1;
1173 struct cvmx_usbcx_hcspltx_s cn56xx;
1174 struct cvmx_usbcx_hcspltx_s cn56xxp1;
1176 typedef union cvmx_usbcx_hcspltx cvmx_usbcx_hcspltx_t;
1179 * cvmx_usbc#_hctsiz#
1181 * Host Channel-n Transfer Size Register (HCTSIZ)
1184 union cvmx_usbcx_hctsizx
1187 struct cvmx_usbcx_hctsizx_s
1189 uint32_t dopng : 1; /**< Do Ping (DoPng)
1190 Setting this field to 1 directs the host to do PING protocol. */
1191 uint32_t pid : 2; /**< PID (Pid)
1192 The application programs this field with the type of PID to use
1193 for the initial transaction. The host will maintain this field for the
1194 rest of the transfer.
1198 * 2'b11: MDATA (non-control)/SETUP (control) */
1199 uint32_t pktcnt : 10; /**< Packet Count (PktCnt)
1200 This field is programmed by the application with the expected
1201 number of packets to be transmitted (OUT) or received (IN).
1202 The host decrements this count on every successful
1203 transmission or reception of an OUT/IN packet. Once this count
1204 reaches zero, the application is interrupted to indicate normal
1206 uint32_t xfersize : 19; /**< Transfer Size (XferSize)
1207 For an OUT, this field is the number of data bytes the host will
1208 send during the transfer.
1209 For an IN, this field is the buffer size that the application has
1210 reserved for the transfer. The application is expected to
1211 program this field as an integer multiple of the maximum packet
1212 size for IN transactions (periodic and non-periodic). */
1214 struct cvmx_usbcx_hctsizx_s cn30xx;
1215 struct cvmx_usbcx_hctsizx_s cn31xx;
1216 struct cvmx_usbcx_hctsizx_s cn50xx;
1217 struct cvmx_usbcx_hctsizx_s cn52xx;
1218 struct cvmx_usbcx_hctsizx_s cn52xxp1;
1219 struct cvmx_usbcx_hctsizx_s cn56xx;
1220 struct cvmx_usbcx_hctsizx_s cn56xxp1;
1222 typedef union cvmx_usbcx_hctsizx cvmx_usbcx_hctsizx_t;
1227 * Host Frame Interval Register (HFIR)
1229 * This register stores the frame interval information for the current speed to which the O2P USB core has enumerated.
1231 union cvmx_usbcx_hfir
1234 struct cvmx_usbcx_hfir_s
1236 uint32_t reserved_16_31 : 16;
1237 uint32_t frint : 16; /**< Frame Interval (FrInt)
1238 The value that the application programs to this field specifies
1239 the interval between two consecutive SOFs (FS) or micro-
1240 SOFs (HS) or Keep-Alive tokens (HS). This field contains the
1241 number of PHY clocks that constitute the required frame
1242 interval. The default value set in this field for a FS operation
1243 when the PHY clock frequency is 60 MHz. The application can
1244 write a value to this register only after the Port Enable bit of
1245 the Host Port Control and Status register (HPRT.PrtEnaPort)
1246 has been set. If no value is programmed, the core calculates
1247 the value based on the PHY clock specified in the FS/LS PHY
1248 Clock Select field of the Host Configuration register
1249 (HCFG.FSLSPclkSel). Do not change the value of this field
1250 after the initial configuration.
1251 * 125 us (PHY clock frequency for HS)
1252 * 1 ms (PHY clock frequency for FS/LS) */
1254 struct cvmx_usbcx_hfir_s cn30xx;
1255 struct cvmx_usbcx_hfir_s cn31xx;
1256 struct cvmx_usbcx_hfir_s cn50xx;
1257 struct cvmx_usbcx_hfir_s cn52xx;
1258 struct cvmx_usbcx_hfir_s cn52xxp1;
1259 struct cvmx_usbcx_hfir_s cn56xx;
1260 struct cvmx_usbcx_hfir_s cn56xxp1;
1262 typedef union cvmx_usbcx_hfir cvmx_usbcx_hfir_t;
1267 * Host Frame Number/Frame Time Remaining Register (HFNUM)
1269 * This register indicates the current frame number.
1270 * It also indicates the time remaining (in terms of the number of PHY clocks)
1271 * in the current (micro)frame.
1273 union cvmx_usbcx_hfnum
1276 struct cvmx_usbcx_hfnum_s
1278 uint32_t frrem : 16; /**< Frame Time Remaining (FrRem)
1279 Indicates the amount of time remaining in the current
1280 microframe (HS) or frame (FS/LS), in terms of PHY clocks.
1281 This field decrements on each PHY clock. When it reaches
1282 zero, this field is reloaded with the value in the Frame Interval
1283 register and a new SOF is transmitted on the USB. */
1284 uint32_t frnum : 16; /**< Frame Number (FrNum)
1285 This field increments when a new SOF is transmitted on the
1286 USB, and is reset to 0 when it reaches 16'h3FFF. */
1288 struct cvmx_usbcx_hfnum_s cn30xx;
1289 struct cvmx_usbcx_hfnum_s cn31xx;
1290 struct cvmx_usbcx_hfnum_s cn50xx;
1291 struct cvmx_usbcx_hfnum_s cn52xx;
1292 struct cvmx_usbcx_hfnum_s cn52xxp1;
1293 struct cvmx_usbcx_hfnum_s cn56xx;
1294 struct cvmx_usbcx_hfnum_s cn56xxp1;
1296 typedef union cvmx_usbcx_hfnum cvmx_usbcx_hfnum_t;
1301 * Host Port Control and Status Register (HPRT)
1303 * This register is available in both Host and Device modes.
1304 * Currently, the OTG Host supports only one port.
1305 * A single register holds USB port-related information such as USB reset, enable, suspend, resume,
1306 * connect status, and test mode for each port. The R_SS_WC bits in this register can trigger an
1307 * interrupt to the application through the Host Port Interrupt bit of the Core Interrupt
1308 * register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear
1309 * the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit
1310 * to clear the interrupt.
1312 union cvmx_usbcx_hprt
1315 struct cvmx_usbcx_hprt_s
1317 uint32_t reserved_19_31 : 13;
1318 uint32_t prtspd : 2; /**< Port Speed (PrtSpd)
1319 Indicates the speed of the device attached to this port.
1323 * 2'b11: Reserved */
1324 uint32_t prttstctl : 4; /**< Port Test Control (PrtTstCtl)
1325 The application writes a nonzero value to this field to put
1326 the port into a Test mode, and the corresponding pattern is
1327 signaled on the port.
1328 * 4'b0000: Test mode disabled
1329 * 4'b0001: Test_J mode
1330 * 4'b0010: Test_K mode
1331 * 4'b0011: Test_SE0_NAK mode
1332 * 4'b0100: Test_Packet mode
1333 * 4'b0101: Test_Force_Enable
1335 PrtSpd must be zero (i.e. the interface must be in high-speed
1336 mode) to use the PrtTstCtl test modes. */
1337 uint32_t prtpwr : 1; /**< Port Power (PrtPwr)
1338 The application uses this field to control power to this port,
1339 and the core clears this bit on an overcurrent condition.
1342 uint32_t prtlnsts : 2; /**< Port Line Status (PrtLnSts)
1343 Indicates the current logic level USB data lines
1344 * Bit [10]: Logic level of D-
1345 * Bit [11]: Logic level of D+ */
1346 uint32_t reserved_9_9 : 1;
1347 uint32_t prtrst : 1; /**< Port Reset (PrtRst)
1348 When the application sets this bit, a reset sequence is
1349 started on this port. The application must time the reset
1350 period and clear this bit after the reset sequence is
1352 * 1'b0: Port not in reset
1353 * 1'b1: Port in reset
1354 The application must leave this bit set for at least a
1355 minimum duration mentioned below to start a reset on the
1356 port. The application can leave it set for another 10 ms in
1357 addition to the required minimum duration, before clearing
1358 the bit, even though there is no maximum limit set by the
1361 * Full speed/Low speed: 10 ms */
1362 uint32_t prtsusp : 1; /**< Port Suspend (PrtSusp)
1363 The application sets this bit to put this port in Suspend
1364 mode. The core only stops sending SOFs when this is set.
1365 To stop the PHY clock, the application must set the Port
1366 Clock Stop bit, which will assert the suspend input pin of
1368 The read value of this bit reflects the current suspend
1369 status of the port. This bit is cleared by the core after a
1370 remote wakeup signal is detected or the application sets
1371 the Port Reset bit or Port Resume bit in this register or the
1372 Resume/Remote Wakeup Detected Interrupt bit or
1373 Disconnect Detected Interrupt bit in the Core Interrupt
1374 register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,
1376 * 1'b0: Port not in Suspend mode
1377 * 1'b1: Port in Suspend mode */
1378 uint32_t prtres : 1; /**< Port Resume (PrtRes)
1379 The application sets this bit to drive resume signaling on
1380 the port. The core continues to drive the resume signal
1381 until the application clears this bit.
1382 If the core detects a USB remote wakeup sequence, as
1383 indicated by the Port Resume/Remote Wakeup Detected
1384 Interrupt bit of the Core Interrupt register
1385 (GINTSTS.WkUpInt), the core starts driving resume
1386 signaling without application intervention and clears this bit
1387 when it detects a disconnect condition. The read value of
1388 this bit indicates whether the core is currently driving
1390 * 1'b0: No resume driven
1391 * 1'b1: Resume driven */
1392 uint32_t prtovrcurrchng : 1; /**< Port Overcurrent Change (PrtOvrCurrChng)
1393 The core sets this bit when the status of the Port
1394 Overcurrent Active bit (bit 4) in this register changes. */
1395 uint32_t prtovrcurract : 1; /**< Port Overcurrent Active (PrtOvrCurrAct)
1396 Indicates the overcurrent condition of the port.
1397 * 1'b0: No overcurrent condition
1398 * 1'b1: Overcurrent condition */
1399 uint32_t prtenchng : 1; /**< Port Enable/Disable Change (PrtEnChng)
1400 The core sets this bit when the status of the Port Enable bit
1401 [2] of this register changes. */
1402 uint32_t prtena : 1; /**< Port Enable (PrtEna)
1403 A port is enabled only by the core after a reset sequence,
1404 and is disabled by an overcurrent condition, a disconnect
1405 condition, or by the application clearing this bit. The
1406 application cannot set this bit by a register write. It can only
1407 clear it to disable the port. This bit does not trigger any
1408 interrupt to the application.
1409 * 1'b0: Port disabled
1410 * 1'b1: Port enabled */
1411 uint32_t prtconndet : 1; /**< Port Connect Detected (PrtConnDet)
1412 The core sets this bit when a device connection is detected
1413 to trigger an interrupt to the application using the Host Port
1414 Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).
1415 The application must write a 1 to this bit to clear the
1417 uint32_t prtconnsts : 1; /**< Port Connect Status (PrtConnSts)
1418 * 0: No device is attached to the port.
1419 * 1: A device is attached to the port. */
1421 struct cvmx_usbcx_hprt_s cn30xx;
1422 struct cvmx_usbcx_hprt_s cn31xx;
1423 struct cvmx_usbcx_hprt_s cn50xx;
1424 struct cvmx_usbcx_hprt_s cn52xx;
1425 struct cvmx_usbcx_hprt_s cn52xxp1;
1426 struct cvmx_usbcx_hprt_s cn56xx;
1427 struct cvmx_usbcx_hprt_s cn56xxp1;
1429 typedef union cvmx_usbcx_hprt cvmx_usbcx_hprt_t;
1432 * cvmx_usbc#_hptxfsiz
1434 * Host Periodic Transmit FIFO Size Register (HPTXFSIZ)
1436 * This register holds the size and the memory start address of the Periodic TxFIFO, as shown in Figures 310 and 311.
1438 union cvmx_usbcx_hptxfsiz
1441 struct cvmx_usbcx_hptxfsiz_s
1443 uint32_t ptxfsize : 16; /**< Host Periodic TxFIFO Depth (PTxFSize)
1444 This value is in terms of 32-bit words.
1445 * Minimum value is 16
1446 * Maximum value is 32768 */
1447 uint32_t ptxfstaddr : 16; /**< Host Periodic TxFIFO Start Address (PTxFStAddr) */
1449 struct cvmx_usbcx_hptxfsiz_s cn30xx;
1450 struct cvmx_usbcx_hptxfsiz_s cn31xx;
1451 struct cvmx_usbcx_hptxfsiz_s cn50xx;
1452 struct cvmx_usbcx_hptxfsiz_s cn52xx;
1453 struct cvmx_usbcx_hptxfsiz_s cn52xxp1;
1454 struct cvmx_usbcx_hptxfsiz_s cn56xx;
1455 struct cvmx_usbcx_hptxfsiz_s cn56xxp1;
1457 typedef union cvmx_usbcx_hptxfsiz cvmx_usbcx_hptxfsiz_t;
1460 * cvmx_usbc#_hptxsts
1462 * Host Periodic Transmit FIFO/Queue Status Register (HPTXSTS)
1464 * This read-only register contains the free space information for the Periodic TxFIFO and
1465 * the Periodic Transmit Request Queue
1467 union cvmx_usbcx_hptxsts
1470 struct cvmx_usbcx_hptxsts_s
1472 uint32_t ptxqtop : 8; /**< Top of the Periodic Transmit Request Queue (PTxQTop)
1473 This indicates the entry in the Periodic Tx Request Queue that
1474 is currently being processes by the MAC.
1475 This register is used for debugging.
1476 * Bit [31]: Odd/Even (micro)frame
1477 - 1'b0: send in even (micro)frame
1478 - 1'b1: send in odd (micro)frame
1479 * Bits [30:27]: Channel/endpoint number
1480 * Bits [26:25]: Type
1482 - 2'b01: Zero-length packet
1484 - 2'b11: Disable channel command
1485 * Bit [24]: Terminate (last entry for the selected
1486 channel/endpoint) */
1487 uint32_t ptxqspcavail : 8; /**< Periodic Transmit Request Queue Space Available
1489 Indicates the number of free locations available to be written in
1490 the Periodic Transmit Request Queue. This queue holds both
1491 IN and OUT requests.
1492 * 8'h0: Periodic Transmit Request Queue is full
1493 * 8'h1: 1 location available
1494 * 8'h2: 2 locations available
1495 * n: n locations available (0..8)
1496 * Others: Reserved */
1497 uint32_t ptxfspcavail : 16; /**< Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)
1498 Indicates the number of free locations available to be written to
1499 in the Periodic TxFIFO.
1500 Values are in terms of 32-bit words
1501 * 16'h0: Periodic TxFIFO is full
1502 * 16'h1: 1 word available
1503 * 16'h2: 2 words available
1504 * 16'hn: n words available (where 0..32768)
1505 * 16'h8000: 32768 words available
1506 * Others: Reserved */
1508 struct cvmx_usbcx_hptxsts_s cn30xx;
1509 struct cvmx_usbcx_hptxsts_s cn31xx;
1510 struct cvmx_usbcx_hptxsts_s cn50xx;
1511 struct cvmx_usbcx_hptxsts_s cn52xx;
1512 struct cvmx_usbcx_hptxsts_s cn52xxp1;
1513 struct cvmx_usbcx_hptxsts_s cn56xx;
1514 struct cvmx_usbcx_hptxsts_s cn56xxp1;
1516 typedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t;
projects / linux-imx.git / blob