drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * ironlake_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674                                            enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         reg = TRANSCONF(pipe);
1693         val = I915_READ(reg);
1694         pipeconf_val = I915_READ(PIPECONF(pipe));
1695
1696         if (HAS_PCH_IBX(dev_priv->dev)) {
1697                 /*
1698                  * make the BPC in transcoder be consistent with
1699                  * that in pipeconf reg.
1700                  */
1701                 val &= ~PIPE_BPC_MASK;
1702                 val |= pipeconf_val & PIPE_BPC_MASK;
1703         }
1704
1705         val &= ~TRANS_INTERLACE_MASK;
1706         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1707                 if (HAS_PCH_IBX(dev_priv->dev) &&
1708                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709                         val |= TRANS_LEGACY_INTERLACED_ILK;
1710                 else
1711                         val |= TRANS_INTERLACED;
1712         else
1713                 val |= TRANS_PROGRESSIVE;
1714
1715         I915_WRITE(reg, val | TRANS_ENABLE);
1716         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718 }
1719
1720 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721                                       enum pipe pipe)
1722 {
1723         int reg;
1724         u32 val, pipeconf_val;
1725         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1726
1727         /* PCH only available on ILK+ */
1728         BUG_ON(dev_priv->info->gen < 5);
1729
1730         /* Make sure PCH DPLL is enabled */
1731         assert_pch_pll_enabled(dev_priv,
1732                                to_intel_crtc(crtc)->pch_pll,
1733                                to_intel_crtc(crtc));
1734
1735         /* FDI must be feeding us bits for PCH ports */
1736         assert_fdi_tx_enabled(dev_priv, pipe);
1737         assert_fdi_rx_enabled(dev_priv, pipe);
1738
1739         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1740                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1741                 return;
1742         }
1743         reg = TRANSCONF(pipe);
1744         val = I915_READ(reg);
1745         pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747         val &= ~TRANS_INTERLACE_MASK;
1748         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1749                 val |= TRANS_INTERLACED;
1750         else
1751                 val |= TRANS_PROGRESSIVE;
1752
1753         I915_WRITE(reg, val | TRANS_ENABLE);
1754         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1755                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1756 }
1757
1758 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1759                                             enum pipe pipe)
1760 {
1761         int reg;
1762         u32 val;
1763
1764         /* FDI relies on the transcoder */
1765         assert_fdi_tx_disabled(dev_priv, pipe);
1766         assert_fdi_rx_disabled(dev_priv, pipe);
1767
1768         /* Ports must be off as well */
1769         assert_pch_ports_disabled(dev_priv, pipe);
1770
1771         reg = TRANSCONF(pipe);
1772         val = I915_READ(reg);
1773         val &= ~TRANS_ENABLE;
1774         I915_WRITE(reg, val);
1775         /* wait for PCH transcoder off, transcoder state */
1776         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1777                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1778 }
1779
1780 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1781                                        enum pipe pipe)
1782 {
1783         int reg;
1784         u32 val;
1785
1786         /* FDI relies on the transcoder */
1787         assert_fdi_tx_disabled(dev_priv, pipe);
1788         assert_fdi_rx_disabled(dev_priv, pipe);
1789
1790         /* Ports must be off as well */
1791         assert_pch_ports_disabled(dev_priv, pipe);
1792
1793         reg = TRANSCONF(pipe);
1794         val = I915_READ(reg);
1795         val &= ~TRANS_ENABLE;
1796         I915_WRITE(reg, val);
1797         /* wait for PCH transcoder off, transcoder state */
1798         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1799                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1800 }
1801
1802 /**
1803  * intel_enable_pipe - enable a pipe, asserting requirements
1804  * @dev_priv: i915 private structure
1805  * @pipe: pipe to enable
1806  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1807  *
1808  * Enable @pipe, making sure that various hardware specific requirements
1809  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1810  *
1811  * @pipe should be %PIPE_A or %PIPE_B.
1812  *
1813  * Will wait until the pipe is actually running (i.e. first vblank) before
1814  * returning.
1815  */
1816 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1817                               bool pch_port)
1818 {
1819         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1820                                                                       pipe);
1821         int reg;
1822         u32 val;
1823
1824         /*
1825          * A pipe without a PLL won't actually be able to drive bits from
1826          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1827          * need the check.
1828          */
1829         if (!HAS_PCH_SPLIT(dev_priv->dev))
1830                 assert_pll_enabled(dev_priv, pipe);
1831         else {
1832                 if (pch_port) {
1833                         /* if driving the PCH, we need FDI enabled */
1834                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1835                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1836                 }
1837                 /* FIXME: assert CPU port conditions for SNB+ */
1838         }
1839
1840         reg = PIPECONF(cpu_transcoder);
1841         val = I915_READ(reg);
1842         if (val & PIPECONF_ENABLE)
1843                 return;
1844
1845         I915_WRITE(reg, val | PIPECONF_ENABLE);
1846         intel_wait_for_vblank(dev_priv->dev, pipe);
1847 }
1848
1849 /**
1850  * intel_disable_pipe - disable a pipe, asserting requirements
1851  * @dev_priv: i915 private structure
1852  * @pipe: pipe to disable
1853  *
1854  * Disable @pipe, making sure that various hardware specific requirements
1855  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1856  *
1857  * @pipe should be %PIPE_A or %PIPE_B.
1858  *
1859  * Will wait until the pipe has shut down before returning.
1860  */
1861 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1862                                enum pipe pipe)
1863 {
1864         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1865                                                                       pipe);
1866         int reg;
1867         u32 val;
1868
1869         /*
1870          * Make sure planes won't keep trying to pump pixels to us,
1871          * or we might hang the display.
1872          */
1873         assert_planes_disabled(dev_priv, pipe);
1874
1875         /* Don't disable pipe A or pipe A PLLs if needed */
1876         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1877                 return;
1878
1879         reg = PIPECONF(cpu_transcoder);
1880         val = I915_READ(reg);
1881         if ((val & PIPECONF_ENABLE) == 0)
1882                 return;
1883
1884         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1885         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1886 }
1887
1888 /*
1889  * Plane regs are double buffered, going from enabled->disabled needs a
1890  * trigger in order to latch.  The display address reg provides this.
1891  */
1892 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1893                                       enum plane plane)
1894 {
1895         if (dev_priv->info->gen >= 4)
1896                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1897         else
1898                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1899 }
1900
1901 /**
1902  * intel_enable_plane - enable a display plane on a given pipe
1903  * @dev_priv: i915 private structure
1904  * @plane: plane to enable
1905  * @pipe: pipe being fed
1906  *
1907  * Enable @plane on @pipe, making sure that @pipe is running first.
1908  */
1909 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1910                                enum plane plane, enum pipe pipe)
1911 {
1912         int reg;
1913         u32 val;
1914
1915         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1916         assert_pipe_enabled(dev_priv, pipe);
1917
1918         reg = DSPCNTR(plane);
1919         val = I915_READ(reg);
1920         if (val & DISPLAY_PLANE_ENABLE)
1921                 return;
1922
1923         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1924         intel_flush_display_plane(dev_priv, plane);
1925         intel_wait_for_vblank(dev_priv->dev, pipe);
1926 }
1927
1928 /**
1929  * intel_disable_plane - disable a display plane
1930  * @dev_priv: i915 private structure
1931  * @plane: plane to disable
1932  * @pipe: pipe consuming the data
1933  *
1934  * Disable @plane; should be an independent operation.
1935  */
1936 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1937                                 enum plane plane, enum pipe pipe)
1938 {
1939         int reg;
1940         u32 val;
1941
1942         reg = DSPCNTR(plane);
1943         val = I915_READ(reg);
1944         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1945                 return;
1946
1947         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1948         intel_flush_display_plane(dev_priv, plane);
1949         intel_wait_for_vblank(dev_priv->dev, pipe);
1950 }
1951
1952 int
1953 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1954                            struct drm_i915_gem_object *obj,
1955                            struct intel_ring_buffer *pipelined)
1956 {
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         u32 alignment;
1959         int ret;
1960
1961         switch (obj->tiling_mode) {
1962         case I915_TILING_NONE:
1963                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1964                         alignment = 128 * 1024;
1965                 else if (INTEL_INFO(dev)->gen >= 4)
1966                         alignment = 4 * 1024;
1967                 else
1968                         alignment = 64 * 1024;
1969                 break;
1970         case I915_TILING_X:
1971                 /* pin() will align the object as required by fence */
1972                 alignment = 0;
1973                 break;
1974         case I915_TILING_Y:
1975                 /* FIXME: Is this true? */
1976                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1977                 return -EINVAL;
1978         default:
1979                 BUG();
1980         }
1981
1982         dev_priv->mm.interruptible = false;
1983         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1984         if (ret)
1985                 goto err_interruptible;
1986
1987         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1988          * fence, whereas 965+ only requires a fence if using
1989          * framebuffer compression.  For simplicity, we always install
1990          * a fence as the cost is not that onerous.
1991          */
1992         ret = i915_gem_object_get_fence(obj);
1993         if (ret)
1994                 goto err_unpin;
1995
1996         i915_gem_object_pin_fence(obj);
1997
1998         dev_priv->mm.interruptible = true;
1999         return 0;
2000
2001 err_unpin:
2002         i915_gem_object_unpin(obj);
2003 err_interruptible:
2004         dev_priv->mm.interruptible = true;
2005         return ret;
2006 }
2007
2008 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2009 {
2010         i915_gem_object_unpin_fence(obj);
2011         i915_gem_object_unpin(obj);
2012 }
2013
2014 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2015  * is assumed to be a power-of-two. */
2016 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2017                                                unsigned int bpp,
2018                                                unsigned int pitch)
2019 {
2020         int tile_rows, tiles;
2021
2022         tile_rows = *y / 8;
2023         *y %= 8;
2024         tiles = *x / (512/bpp);
2025         *x %= 512/bpp;
2026
2027         return tile_rows * pitch * 8 + tiles * 4096;
2028 }
2029
2030 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2031                              int x, int y)
2032 {
2033         struct drm_device *dev = crtc->dev;
2034         struct drm_i915_private *dev_priv = dev->dev_private;
2035         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2036         struct intel_framebuffer *intel_fb;
2037         struct drm_i915_gem_object *obj;
2038         int plane = intel_crtc->plane;
2039         unsigned long linear_offset;
2040         u32 dspcntr;
2041         u32 reg;
2042
2043         switch (plane) {
2044         case 0:
2045         case 1:
2046                 break;
2047         default:
2048                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2049                 return -EINVAL;
2050         }
2051
2052         intel_fb = to_intel_framebuffer(fb);
2053         obj = intel_fb->obj;
2054
2055         reg = DSPCNTR(plane);
2056         dspcntr = I915_READ(reg);
2057         /* Mask out pixel format bits in case we change it */
2058         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2059         switch (fb->pixel_format) {
2060         case DRM_FORMAT_C8:
2061                 dspcntr |= DISPPLANE_8BPP;
2062                 break;
2063         case DRM_FORMAT_XRGB1555:
2064         case DRM_FORMAT_ARGB1555:
2065                 dspcntr |= DISPPLANE_BGRX555;
2066                 break;
2067         case DRM_FORMAT_RGB565:
2068                 dspcntr |= DISPPLANE_BGRX565;
2069                 break;
2070         case DRM_FORMAT_XRGB8888:
2071         case DRM_FORMAT_ARGB8888:
2072                 dspcntr |= DISPPLANE_BGRX888;
2073                 break;
2074         case DRM_FORMAT_XBGR8888:
2075         case DRM_FORMAT_ABGR8888:
2076                 dspcntr |= DISPPLANE_RGBX888;
2077                 break;
2078         case DRM_FORMAT_XRGB2101010:
2079         case DRM_FORMAT_ARGB2101010:
2080                 dspcntr |= DISPPLANE_BGRX101010;
2081                 break;
2082         case DRM_FORMAT_XBGR2101010:
2083         case DRM_FORMAT_ABGR2101010:
2084                 dspcntr |= DISPPLANE_RGBX101010;
2085                 break;
2086         default:
2087                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2088                 return -EINVAL;
2089         }
2090
2091         if (INTEL_INFO(dev)->gen >= 4) {
2092                 if (obj->tiling_mode != I915_TILING_NONE)
2093                         dspcntr |= DISPPLANE_TILED;
2094                 else
2095                         dspcntr &= ~DISPPLANE_TILED;
2096         }
2097
2098         I915_WRITE(reg, dspcntr);
2099
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101
2102         if (INTEL_INFO(dev)->gen >= 4) {
2103                 intel_crtc->dspaddr_offset =
2104                         intel_gen4_compute_offset_xtiled(&x, &y,
2105                                                          fb->bits_per_pixel / 8,
2106                                                          fb->pitches[0]);
2107                 linear_offset -= intel_crtc->dspaddr_offset;
2108         } else {
2109                 intel_crtc->dspaddr_offset = linear_offset;
2110         }
2111
2112         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2113                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2114         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2115         if (INTEL_INFO(dev)->gen >= 4) {
2116                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2117                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2118                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2119                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2120         } else
2121                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2122         POSTING_READ(reg);
2123
2124         return 0;
2125 }
2126
2127 static int ironlake_update_plane(struct drm_crtc *crtc,
2128                                  struct drm_framebuffer *fb, int x, int y)
2129 {
2130         struct drm_device *dev = crtc->dev;
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133         struct intel_framebuffer *intel_fb;
2134         struct drm_i915_gem_object *obj;
2135         int plane = intel_crtc->plane;
2136         unsigned long linear_offset;
2137         u32 dspcntr;
2138         u32 reg;
2139
2140         switch (plane) {
2141         case 0:
2142         case 1:
2143         case 2:
2144                 break;
2145         default:
2146                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2147                 return -EINVAL;
2148         }
2149
2150         intel_fb = to_intel_framebuffer(fb);
2151         obj = intel_fb->obj;
2152
2153         reg = DSPCNTR(plane);
2154         dspcntr = I915_READ(reg);
2155         /* Mask out pixel format bits in case we change it */
2156         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2157         switch (fb->pixel_format) {
2158         case DRM_FORMAT_C8:
2159                 dspcntr |= DISPPLANE_8BPP;
2160                 break;
2161         case DRM_FORMAT_RGB565:
2162                 dspcntr |= DISPPLANE_BGRX565;
2163                 break;
2164         case DRM_FORMAT_XRGB8888:
2165         case DRM_FORMAT_ARGB8888:
2166                 dspcntr |= DISPPLANE_BGRX888;
2167                 break;
2168         case DRM_FORMAT_XBGR8888:
2169         case DRM_FORMAT_ABGR8888:
2170                 dspcntr |= DISPPLANE_RGBX888;
2171                 break;
2172         case DRM_FORMAT_XRGB2101010:
2173         case DRM_FORMAT_ARGB2101010:
2174                 dspcntr |= DISPPLANE_BGRX101010;
2175                 break;
2176         case DRM_FORMAT_XBGR2101010:
2177         case DRM_FORMAT_ABGR2101010:
2178                 dspcntr |= DISPPLANE_RGBX101010;
2179                 break;
2180         default:
2181                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2182                 return -EINVAL;
2183         }
2184
2185         if (obj->tiling_mode != I915_TILING_NONE)
2186                 dspcntr |= DISPPLANE_TILED;
2187         else
2188                 dspcntr &= ~DISPPLANE_TILED;
2189
2190         /* must disable */
2191         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2192
2193         I915_WRITE(reg, dspcntr);
2194
2195         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2196         intel_crtc->dspaddr_offset =
2197                 intel_gen4_compute_offset_xtiled(&x, &y,
2198                                                  fb->bits_per_pixel / 8,
2199                                                  fb->pitches[0]);
2200         linear_offset -= intel_crtc->dspaddr_offset;
2201
2202         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2203                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2204         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2205         I915_MODIFY_DISPBASE(DSPSURF(plane),
2206                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2207         if (IS_HASWELL(dev)) {
2208                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2209         } else {
2210                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2211                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2212         }
2213         POSTING_READ(reg);
2214
2215         return 0;
2216 }
2217
2218 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2219 static int
2220 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2221                            int x, int y, enum mode_set_atomic state)
2222 {
2223         struct drm_device *dev = crtc->dev;
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225
2226         if (dev_priv->display.disable_fbc)
2227                 dev_priv->display.disable_fbc(dev);
2228         intel_increase_pllclock(crtc);
2229
2230         return dev_priv->display.update_plane(crtc, fb, x, y);
2231 }
2232
2233 static int
2234 intel_finish_fb(struct drm_framebuffer *old_fb)
2235 {
2236         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2237         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2238         bool was_interruptible = dev_priv->mm.interruptible;
2239         int ret;
2240
2241         wait_event(dev_priv->pending_flip_queue,
2242                    atomic_read(&dev_priv->mm.wedged) ||
2243                    atomic_read(&obj->pending_flip) == 0);
2244
2245         /* Big Hammer, we also need to ensure that any pending
2246          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2247          * current scanout is retired before unpinning the old
2248          * framebuffer.
2249          *
2250          * This should only fail upon a hung GPU, in which case we
2251          * can safely continue.
2252          */
2253         dev_priv->mm.interruptible = false;
2254         ret = i915_gem_object_finish_gpu(obj);
2255         dev_priv->mm.interruptible = was_interruptible;
2256
2257         return ret;
2258 }
2259
2260 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2261 {
2262         struct drm_device *dev = crtc->dev;
2263         struct drm_i915_master_private *master_priv;
2264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266         if (!dev->primary->master)
2267                 return;
2268
2269         master_priv = dev->primary->master->driver_priv;
2270         if (!master_priv->sarea_priv)
2271                 return;
2272
2273         switch (intel_crtc->pipe) {
2274         case 0:
2275                 master_priv->sarea_priv->pipeA_x = x;
2276                 master_priv->sarea_priv->pipeA_y = y;
2277                 break;
2278         case 1:
2279                 master_priv->sarea_priv->pipeB_x = x;
2280                 master_priv->sarea_priv->pipeB_y = y;
2281                 break;
2282         default:
2283                 break;
2284         }
2285 }
2286
2287 static int
2288 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2289                     struct drm_framebuffer *fb)
2290 {
2291         struct drm_device *dev = crtc->dev;
2292         struct drm_i915_private *dev_priv = dev->dev_private;
2293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294         struct drm_framebuffer *old_fb;
2295         int ret;
2296
2297         /* no fb bound */
2298         if (!fb) {
2299                 DRM_ERROR("No FB bound\n");
2300                 return 0;
2301         }
2302
2303         if(intel_crtc->plane > dev_priv->num_pipe) {
2304                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2305                                 intel_crtc->plane,
2306                                 dev_priv->num_pipe);
2307                 return -EINVAL;
2308         }
2309
2310         mutex_lock(&dev->struct_mutex);
2311         ret = intel_pin_and_fence_fb_obj(dev,
2312                                          to_intel_framebuffer(fb)->obj,
2313                                          NULL);
2314         if (ret != 0) {
2315                 mutex_unlock(&dev->struct_mutex);
2316                 DRM_ERROR("pin & fence failed\n");
2317                 return ret;
2318         }
2319
2320         if (crtc->fb)
2321                 intel_finish_fb(crtc->fb);
2322
2323         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2324         if (ret) {
2325                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2326                 mutex_unlock(&dev->struct_mutex);
2327                 DRM_ERROR("failed to update base address\n");
2328                 return ret;
2329         }
2330
2331         old_fb = crtc->fb;
2332         crtc->fb = fb;
2333         crtc->x = x;
2334         crtc->y = y;
2335
2336         if (old_fb) {
2337                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2338                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2339         }
2340
2341         intel_update_fbc(dev);
2342         mutex_unlock(&dev->struct_mutex);
2343
2344         intel_crtc_update_sarea_pos(crtc, x, y);
2345
2346         return 0;
2347 }
2348
2349 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2350 {
2351         struct drm_device *dev = crtc->dev;
2352         struct drm_i915_private *dev_priv = dev->dev_private;
2353         u32 dpa_ctl;
2354
2355         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2356         dpa_ctl = I915_READ(DP_A);
2357         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2358
2359         if (clock < 200000) {
2360                 u32 temp;
2361                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2362                 /* workaround for 160Mhz:
2363                    1) program 0x4600c bits 15:0 = 0x8124
2364                    2) program 0x46010 bit 0 = 1
2365                    3) program 0x46034 bit 24 = 1
2366                    4) program 0x64000 bit 14 = 1
2367                    */
2368                 temp = I915_READ(0x4600c);
2369                 temp &= 0xffff0000;
2370                 I915_WRITE(0x4600c, temp | 0x8124);
2371
2372                 temp = I915_READ(0x46010);
2373                 I915_WRITE(0x46010, temp | 1);
2374
2375                 temp = I915_READ(0x46034);
2376                 I915_WRITE(0x46034, temp | (1 << 24));
2377         } else {
2378                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2379         }
2380         I915_WRITE(DP_A, dpa_ctl);
2381
2382         POSTING_READ(DP_A);
2383         udelay(500);
2384 }
2385
2386 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2387 {
2388         struct drm_device *dev = crtc->dev;
2389         struct drm_i915_private *dev_priv = dev->dev_private;
2390         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391         int pipe = intel_crtc->pipe;
2392         u32 reg, temp;
2393
2394         /* enable normal train */
2395         reg = FDI_TX_CTL(pipe);
2396         temp = I915_READ(reg);
2397         if (IS_IVYBRIDGE(dev)) {
2398                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2399                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         } else {
2401                 temp &= ~FDI_LINK_TRAIN_NONE;
2402                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2403         }
2404         I915_WRITE(reg, temp);
2405
2406         reg = FDI_RX_CTL(pipe);
2407         temp = I915_READ(reg);
2408         if (HAS_PCH_CPT(dev)) {
2409                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2410                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2411         } else {
2412                 temp &= ~FDI_LINK_TRAIN_NONE;
2413                 temp |= FDI_LINK_TRAIN_NONE;
2414         }
2415         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2416
2417         /* wait one idle pattern time */
2418         POSTING_READ(reg);
2419         udelay(1000);
2420
2421         /* IVB wants error correction enabled */
2422         if (IS_IVYBRIDGE(dev))
2423                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2424                            FDI_FE_ERRC_ENABLE);
2425 }
2426
2427 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         u32 flags = I915_READ(SOUTH_CHICKEN1);
2431
2432         flags |= FDI_PHASE_SYNC_OVR(pipe);
2433         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2434         flags |= FDI_PHASE_SYNC_EN(pipe);
2435         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2436         POSTING_READ(SOUTH_CHICKEN1);
2437 }
2438
2439 static void ivb_modeset_global_resources(struct drm_device *dev)
2440 {
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         struct intel_crtc *pipe_B_crtc =
2443                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2444         struct intel_crtc *pipe_C_crtc =
2445                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2446         uint32_t temp;
2447
2448         /* When everything is off disable fdi C so that we could enable fdi B
2449          * with all lanes. XXX: This misses the case where a pipe is not using
2450          * any pch resources and so doesn't need any fdi lanes. */
2451         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2452                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2453                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2454
2455                 temp = I915_READ(SOUTH_CHICKEN1);
2456                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2457                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2458                 I915_WRITE(SOUTH_CHICKEN1, temp);
2459         }
2460 }
2461
2462 /* The FDI link training functions for ILK/Ibexpeak. */
2463 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2464 {
2465         struct drm_device *dev = crtc->dev;
2466         struct drm_i915_private *dev_priv = dev->dev_private;
2467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468         int pipe = intel_crtc->pipe;
2469         int plane = intel_crtc->plane;
2470         u32 reg, temp, tries;
2471
2472         /* FDI needs bits from pipe & plane first */
2473         assert_pipe_enabled(dev_priv, pipe);
2474         assert_plane_enabled(dev_priv, plane);
2475
2476         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2477            for train result */
2478         reg = FDI_RX_IMR(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_RX_SYMBOL_LOCK;
2481         temp &= ~FDI_RX_BIT_LOCK;
2482         I915_WRITE(reg, temp);
2483         I915_READ(reg);
2484         udelay(150);
2485
2486         /* enable CPU FDI TX and PCH FDI RX */
2487         reg = FDI_TX_CTL(pipe);
2488         temp = I915_READ(reg);
2489         temp &= ~(7 << 19);
2490         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491         temp &= ~FDI_LINK_TRAIN_NONE;
2492         temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2494
2495         reg = FDI_RX_CTL(pipe);
2496         temp = I915_READ(reg);
2497         temp &= ~FDI_LINK_TRAIN_NONE;
2498         temp |= FDI_LINK_TRAIN_PATTERN_1;
2499         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2500
2501         POSTING_READ(reg);
2502         udelay(150);
2503
2504         /* Ironlake workaround, enable clock pointer after FDI enable*/
2505         if (HAS_PCH_IBX(dev)) {
2506                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2507                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2508                            FDI_RX_PHASE_SYNC_POINTER_EN);
2509         }
2510
2511         reg = FDI_RX_IIR(pipe);
2512         for (tries = 0; tries < 5; tries++) {
2513                 temp = I915_READ(reg);
2514                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2515
2516                 if ((temp & FDI_RX_BIT_LOCK)) {
2517                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2518                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2519                         break;
2520                 }
2521         }
2522         if (tries == 5)
2523                 DRM_ERROR("FDI train 1 fail!\n");
2524
2525         /* Train 2 */
2526         reg = FDI_TX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         temp &= ~FDI_LINK_TRAIN_NONE;
2529         temp |= FDI_LINK_TRAIN_PATTERN_2;
2530         I915_WRITE(reg, temp);
2531
2532         reg = FDI_RX_CTL(pipe);
2533         temp = I915_READ(reg);
2534         temp &= ~FDI_LINK_TRAIN_NONE;
2535         temp |= FDI_LINK_TRAIN_PATTERN_2;
2536         I915_WRITE(reg, temp);
2537
2538         POSTING_READ(reg);
2539         udelay(150);
2540
2541         reg = FDI_RX_IIR(pipe);
2542         for (tries = 0; tries < 5; tries++) {
2543                 temp = I915_READ(reg);
2544                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545
2546                 if (temp & FDI_RX_SYMBOL_LOCK) {
2547                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2548                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2549                         break;
2550                 }
2551         }
2552         if (tries == 5)
2553                 DRM_ERROR("FDI train 2 fail!\n");
2554
2555         DRM_DEBUG_KMS("FDI train done\n");
2556
2557 }
2558
2559 static const int snb_b_fdi_train_param[] = {
2560         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2561         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2562         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2563         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2564 };
2565
2566 /* The FDI link training functions for SNB/Cougarpoint. */
2567 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2568 {
2569         struct drm_device *dev = crtc->dev;
2570         struct drm_i915_private *dev_priv = dev->dev_private;
2571         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2572         int pipe = intel_crtc->pipe;
2573         u32 reg, temp, i, retry;
2574
2575         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2576            for train result */
2577         reg = FDI_RX_IMR(pipe);
2578         temp = I915_READ(reg);
2579         temp &= ~FDI_RX_SYMBOL_LOCK;
2580         temp &= ~FDI_RX_BIT_LOCK;
2581         I915_WRITE(reg, temp);
2582
2583         POSTING_READ(reg);
2584         udelay(150);
2585
2586         /* enable CPU FDI TX and PCH FDI RX */
2587         reg = FDI_TX_CTL(pipe);
2588         temp = I915_READ(reg);
2589         temp &= ~(7 << 19);
2590         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2591         temp &= ~FDI_LINK_TRAIN_NONE;
2592         temp |= FDI_LINK_TRAIN_PATTERN_1;
2593         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2594         /* SNB-B */
2595         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2596         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2597
2598         I915_WRITE(FDI_RX_MISC(pipe),
2599                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2600
2601         reg = FDI_RX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         if (HAS_PCH_CPT(dev)) {
2604                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2606         } else {
2607                 temp &= ~FDI_LINK_TRAIN_NONE;
2608                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2609         }
2610         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2611
2612         POSTING_READ(reg);
2613         udelay(150);
2614
2615         if (HAS_PCH_CPT(dev))
2616                 cpt_phase_pointer_enable(dev, pipe);
2617
2618         for (i = 0; i < 4; i++) {
2619                 reg = FDI_TX_CTL(pipe);
2620                 temp = I915_READ(reg);
2621                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622                 temp |= snb_b_fdi_train_param[i];
2623                 I915_WRITE(reg, temp);
2624
2625                 POSTING_READ(reg);
2626                 udelay(500);
2627
2628                 for (retry = 0; retry < 5; retry++) {
2629                         reg = FDI_RX_IIR(pipe);
2630                         temp = I915_READ(reg);
2631                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2632                         if (temp & FDI_RX_BIT_LOCK) {
2633                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2634                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2635                                 break;
2636                         }
2637                         udelay(50);
2638                 }
2639                 if (retry < 5)
2640                         break;
2641         }
2642         if (i == 4)
2643                 DRM_ERROR("FDI train 1 fail!\n");
2644
2645         /* Train 2 */
2646         reg = FDI_TX_CTL(pipe);
2647         temp = I915_READ(reg);
2648         temp &= ~FDI_LINK_TRAIN_NONE;
2649         temp |= FDI_LINK_TRAIN_PATTERN_2;
2650         if (IS_GEN6(dev)) {
2651                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652                 /* SNB-B */
2653                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2654         }
2655         I915_WRITE(reg, temp);
2656
2657         reg = FDI_RX_CTL(pipe);
2658         temp = I915_READ(reg);
2659         if (HAS_PCH_CPT(dev)) {
2660                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2661                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2662         } else {
2663                 temp &= ~FDI_LINK_TRAIN_NONE;
2664                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2665         }
2666         I915_WRITE(reg, temp);
2667
2668         POSTING_READ(reg);
2669         udelay(150);
2670
2671         for (i = 0; i < 4; i++) {
2672                 reg = FDI_TX_CTL(pipe);
2673                 temp = I915_READ(reg);
2674                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675                 temp |= snb_b_fdi_train_param[i];
2676                 I915_WRITE(reg, temp);
2677
2678                 POSTING_READ(reg);
2679                 udelay(500);
2680
2681                 for (retry = 0; retry < 5; retry++) {
2682                         reg = FDI_RX_IIR(pipe);
2683                         temp = I915_READ(reg);
2684                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2685                         if (temp & FDI_RX_SYMBOL_LOCK) {
2686                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2687                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2688                                 break;
2689                         }
2690                         udelay(50);
2691                 }
2692                 if (retry < 5)
2693                         break;
2694         }
2695         if (i == 4)
2696                 DRM_ERROR("FDI train 2 fail!\n");
2697
2698         DRM_DEBUG_KMS("FDI train done.\n");
2699 }
2700
2701 /* Manual link training for Ivy Bridge A0 parts */
2702 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2703 {
2704         struct drm_device *dev = crtc->dev;
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707         int pipe = intel_crtc->pipe;
2708         u32 reg, temp, i;
2709
2710         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2711            for train result */
2712         reg = FDI_RX_IMR(pipe);
2713         temp = I915_READ(reg);
2714         temp &= ~FDI_RX_SYMBOL_LOCK;
2715         temp &= ~FDI_RX_BIT_LOCK;
2716         I915_WRITE(reg, temp);
2717
2718         POSTING_READ(reg);
2719         udelay(150);
2720
2721         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2722                       I915_READ(FDI_RX_IIR(pipe)));
2723
2724         /* enable CPU FDI TX and PCH FDI RX */
2725         reg = FDI_TX_CTL(pipe);
2726         temp = I915_READ(reg);
2727         temp &= ~(7 << 19);
2728         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2729         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2730         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2731         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2733         temp |= FDI_COMPOSITE_SYNC;
2734         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2735
2736         I915_WRITE(FDI_RX_MISC(pipe),
2737                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2738
2739         reg = FDI_RX_CTL(pipe);
2740         temp = I915_READ(reg);
2741         temp &= ~FDI_LINK_TRAIN_AUTO;
2742         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2743         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2744         temp |= FDI_COMPOSITE_SYNC;
2745         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2746
2747         POSTING_READ(reg);
2748         udelay(150);
2749
2750         if (HAS_PCH_CPT(dev))
2751                 cpt_phase_pointer_enable(dev, pipe);
2752
2753         for (i = 0; i < 4; i++) {
2754                 reg = FDI_TX_CTL(pipe);
2755                 temp = I915_READ(reg);
2756                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2757                 temp |= snb_b_fdi_train_param[i];
2758                 I915_WRITE(reg, temp);
2759
2760                 POSTING_READ(reg);
2761                 udelay(500);
2762
2763                 reg = FDI_RX_IIR(pipe);
2764                 temp = I915_READ(reg);
2765                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2766
2767                 if (temp & FDI_RX_BIT_LOCK ||
2768                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2769                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2770                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2771                         break;
2772                 }
2773         }
2774         if (i == 4)
2775                 DRM_ERROR("FDI train 1 fail!\n");
2776
2777         /* Train 2 */
2778         reg = FDI_TX_CTL(pipe);
2779         temp = I915_READ(reg);
2780         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2781         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2782         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2783         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2784         I915_WRITE(reg, temp);
2785
2786         reg = FDI_RX_CTL(pipe);
2787         temp = I915_READ(reg);
2788         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2789         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2790         I915_WRITE(reg, temp);
2791
2792         POSTING_READ(reg);
2793         udelay(150);
2794
2795         for (i = 0; i < 4; i++) {
2796                 reg = FDI_TX_CTL(pipe);
2797                 temp = I915_READ(reg);
2798                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2799                 temp |= snb_b_fdi_train_param[i];
2800                 I915_WRITE(reg, temp);
2801
2802                 POSTING_READ(reg);
2803                 udelay(500);
2804
2805                 reg = FDI_RX_IIR(pipe);
2806                 temp = I915_READ(reg);
2807                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2808
2809                 if (temp & FDI_RX_SYMBOL_LOCK) {
2810                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2811                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2812                         break;
2813                 }
2814         }
2815         if (i == 4)
2816                 DRM_ERROR("FDI train 2 fail!\n");
2817
2818         DRM_DEBUG_KMS("FDI train done.\n");
2819 }
2820
2821 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2822 {
2823         struct drm_device *dev = intel_crtc->base.dev;
2824         struct drm_i915_private *dev_priv = dev->dev_private;
2825         int pipe = intel_crtc->pipe;
2826         u32 reg, temp;
2827
2828
2829         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2830         reg = FDI_RX_CTL(pipe);
2831         temp = I915_READ(reg);
2832         temp &= ~((0x7 << 19) | (0x7 << 16));
2833         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2834         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2835         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2836
2837         POSTING_READ(reg);
2838         udelay(200);
2839
2840         /* Switch from Rawclk to PCDclk */
2841         temp = I915_READ(reg);
2842         I915_WRITE(reg, temp | FDI_PCDCLK);
2843
2844         POSTING_READ(reg);
2845         udelay(200);
2846
2847         /* On Haswell, the PLL configuration for ports and pipes is handled
2848          * separately, as part of DDI setup */
2849         if (!IS_HASWELL(dev)) {
2850                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2851                 reg = FDI_TX_CTL(pipe);
2852                 temp = I915_READ(reg);
2853                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2854                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2855
2856                         POSTING_READ(reg);
2857                         udelay(100);
2858                 }
2859         }
2860 }
2861
2862 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2863 {
2864         struct drm_device *dev = intel_crtc->base.dev;
2865         struct drm_i915_private *dev_priv = dev->dev_private;
2866         int pipe = intel_crtc->pipe;
2867         u32 reg, temp;
2868
2869         /* Switch from PCDclk to Rawclk */
2870         reg = FDI_RX_CTL(pipe);
2871         temp = I915_READ(reg);
2872         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2873
2874         /* Disable CPU FDI TX PLL */
2875         reg = FDI_TX_CTL(pipe);
2876         temp = I915_READ(reg);
2877         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2878
2879         POSTING_READ(reg);
2880         udelay(100);
2881
2882         reg = FDI_RX_CTL(pipe);
2883         temp = I915_READ(reg);
2884         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2885
2886         /* Wait for the clocks to turn off. */
2887         POSTING_READ(reg);
2888         udelay(100);
2889 }
2890
2891 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2892 {
2893         struct drm_i915_private *dev_priv = dev->dev_private;
2894         u32 flags = I915_READ(SOUTH_CHICKEN1);
2895
2896         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2897         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2898         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2899         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2900         POSTING_READ(SOUTH_CHICKEN1);
2901 }
2902 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2903 {
2904         struct drm_device *dev = crtc->dev;
2905         struct drm_i915_private *dev_priv = dev->dev_private;
2906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907         int pipe = intel_crtc->pipe;
2908         u32 reg, temp;
2909
2910         /* disable CPU FDI tx and PCH FDI rx */
2911         reg = FDI_TX_CTL(pipe);
2912         temp = I915_READ(reg);
2913         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2914         POSTING_READ(reg);
2915
2916         reg = FDI_RX_CTL(pipe);
2917         temp = I915_READ(reg);
2918         temp &= ~(0x7 << 16);
2919         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2920         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2921
2922         POSTING_READ(reg);
2923         udelay(100);
2924
2925         /* Ironlake workaround, disable clock pointer after downing FDI */
2926         if (HAS_PCH_IBX(dev)) {
2927                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2928                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2929                            I915_READ(FDI_RX_CHICKEN(pipe) &
2930                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2931         } else if (HAS_PCH_CPT(dev)) {
2932                 cpt_phase_pointer_disable(dev, pipe);
2933         }
2934
2935         /* still set train pattern 1 */
2936         reg = FDI_TX_CTL(pipe);
2937         temp = I915_READ(reg);
2938         temp &= ~FDI_LINK_TRAIN_NONE;
2939         temp |= FDI_LINK_TRAIN_PATTERN_1;
2940         I915_WRITE(reg, temp);
2941
2942         reg = FDI_RX_CTL(pipe);
2943         temp = I915_READ(reg);
2944         if (HAS_PCH_CPT(dev)) {
2945                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2946                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2947         } else {
2948                 temp &= ~FDI_LINK_TRAIN_NONE;
2949                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2950         }
2951         /* BPC in FDI rx is consistent with that in PIPECONF */
2952         temp &= ~(0x07 << 16);
2953         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2954         I915_WRITE(reg, temp);
2955
2956         POSTING_READ(reg);
2957         udelay(100);
2958 }
2959
2960 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2961 {
2962         struct drm_device *dev = crtc->dev;
2963         struct drm_i915_private *dev_priv = dev->dev_private;
2964         unsigned long flags;
2965         bool pending;
2966
2967         if (atomic_read(&dev_priv->mm.wedged))
2968                 return false;
2969
2970         spin_lock_irqsave(&dev->event_lock, flags);
2971         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2972         spin_unlock_irqrestore(&dev->event_lock, flags);
2973
2974         return pending;
2975 }
2976
2977 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2978 {
2979         struct drm_device *dev = crtc->dev;
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981
2982         if (crtc->fb == NULL)
2983                 return;
2984
2985         wait_event(dev_priv->pending_flip_queue,
2986                    !intel_crtc_has_pending_flip(crtc));
2987
2988         mutex_lock(&dev->struct_mutex);
2989         intel_finish_fb(crtc->fb);
2990         mutex_unlock(&dev->struct_mutex);
2991 }
2992
2993 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2994 {
2995         struct drm_device *dev = crtc->dev;
2996         struct intel_encoder *intel_encoder;
2997
2998         /*
2999          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
3000          * must be driven by its own crtc; no sharing is possible.
3001          */
3002         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3003                 switch (intel_encoder->type) {
3004                 case INTEL_OUTPUT_EDP:
3005                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
3006                                 return false;
3007                         continue;
3008                 }
3009         }
3010
3011         return true;
3012 }
3013
3014 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3015 {
3016         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3017 }
3018
3019 /* Program iCLKIP clock to the desired frequency */
3020 static void lpt_program_iclkip(struct drm_crtc *crtc)
3021 {
3022         struct drm_device *dev = crtc->dev;
3023         struct drm_i915_private *dev_priv = dev->dev_private;
3024         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3025         u32 temp;
3026
3027         /* It is necessary to ungate the pixclk gate prior to programming
3028          * the divisors, and gate it back when it is done.
3029          */
3030         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3031
3032         /* Disable SSCCTL */
3033         intel_sbi_write(dev_priv, SBI_SSCCTL6,
3034                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3035                                         SBI_SSCCTL_DISABLE);
3036
3037         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3038         if (crtc->mode.clock == 20000) {
3039                 auxdiv = 1;
3040                 divsel = 0x41;
3041                 phaseinc = 0x20;
3042         } else {
3043                 /* The iCLK virtual clock root frequency is in MHz,
3044                  * but the crtc->mode.clock in in KHz. To get the divisors,
3045                  * it is necessary to divide one by another, so we
3046                  * convert the virtual clock precision to KHz here for higher
3047                  * precision.
3048                  */
3049                 u32 iclk_virtual_root_freq = 172800 * 1000;
3050                 u32 iclk_pi_range = 64;
3051                 u32 desired_divisor, msb_divisor_value, pi_value;
3052
3053                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3054                 msb_divisor_value = desired_divisor / iclk_pi_range;
3055                 pi_value = desired_divisor % iclk_pi_range;
3056
3057                 auxdiv = 0;
3058                 divsel = msb_divisor_value - 2;
3059                 phaseinc = pi_value;
3060         }
3061
3062         /* This should not happen with any sane values */
3063         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3064                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3065         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3066                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3067
3068         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3069                         crtc->mode.clock,
3070                         auxdiv,
3071                         divsel,
3072                         phasedir,
3073                         phaseinc);
3074
3075         /* Program SSCDIVINTPHASE6 */
3076         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3077         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3078         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3079         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3080         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3081         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3082         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3083
3084         intel_sbi_write(dev_priv,
3085                         SBI_SSCDIVINTPHASE6,
3086                         temp);
3087
3088         /* Program SSCAUXDIV */
3089         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3090         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3091         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3092         intel_sbi_write(dev_priv,
3093                         SBI_SSCAUXDIV6,
3094                         temp);
3095
3096
3097         /* Enable modulator and associated divider */
3098         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3099         temp &= ~SBI_SSCCTL_DISABLE;
3100         intel_sbi_write(dev_priv,
3101                         SBI_SSCCTL6,
3102                         temp);
3103
3104         /* Wait for initialization time */
3105         udelay(24);
3106
3107         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3108 }
3109
3110 /*
3111  * Enable PCH resources required for PCH ports:
3112  *   - PCH PLLs
3113  *   - FDI training & RX/TX
3114  *   - update transcoder timings
3115  *   - DP transcoding bits
3116  *   - transcoder
3117  */
3118 static void ironlake_pch_enable(struct drm_crtc *crtc)
3119 {
3120         struct drm_device *dev = crtc->dev;
3121         struct drm_i915_private *dev_priv = dev->dev_private;
3122         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3123         int pipe = intel_crtc->pipe;
3124         u32 reg, temp;
3125
3126         assert_transcoder_disabled(dev_priv, pipe);
3127
3128         /* Write the TU size bits before fdi link training, so that error
3129          * detection works. */
3130         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3131                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3132
3133         /* For PCH output, training FDI link */
3134         dev_priv->display.fdi_link_train(crtc);
3135
3136         /* XXX: pch pll's can be enabled any time before we enable the PCH
3137          * transcoder, and we actually should do this to not upset any PCH
3138          * transcoder that already use the clock when we share it.
3139          *
3140          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3141          * unconditionally resets the pll - we need that to have the right LVDS
3142          * enable sequence. */
3143         ironlake_enable_pch_pll(intel_crtc);
3144
3145         if (HAS_PCH_CPT(dev)) {
3146                 u32 sel;
3147
3148                 temp = I915_READ(PCH_DPLL_SEL);
3149                 switch (pipe) {
3150                 default:
3151                 case 0:
3152                         temp |= TRANSA_DPLL_ENABLE;
3153                         sel = TRANSA_DPLLB_SEL;
3154                         break;
3155                 case 1:
3156                         temp |= TRANSB_DPLL_ENABLE;
3157                         sel = TRANSB_DPLLB_SEL;
3158                         break;
3159                 case 2:
3160                         temp |= TRANSC_DPLL_ENABLE;
3161                         sel = TRANSC_DPLLB_SEL;
3162                         break;
3163                 }
3164                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3165                         temp |= sel;
3166                 else
3167                         temp &= ~sel;
3168                 I915_WRITE(PCH_DPLL_SEL, temp);
3169         }
3170
3171         /* set transcoder timing, panel must allow it */
3172         assert_panel_unlocked(dev_priv, pipe);
3173         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3174         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3175         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3176
3177         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3178         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3179         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3180         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3181
3182         intel_fdi_normal_train(crtc);
3183
3184         /* For PCH DP, enable TRANS_DP_CTL */
3185         if (HAS_PCH_CPT(dev) &&
3186             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3187              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3188                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3189                 reg = TRANS_DP_CTL(pipe);
3190                 temp = I915_READ(reg);
3191                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3192                           TRANS_DP_SYNC_MASK |
3193                           TRANS_DP_BPC_MASK);
3194                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3195                          TRANS_DP_ENH_FRAMING);
3196                 temp |= bpc << 9; /* same format but at 11:9 */
3197
3198                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3199                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3200                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3201                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3202
3203                 switch (intel_trans_dp_port_sel(crtc)) {
3204                 case PCH_DP_B:
3205                         temp |= TRANS_DP_PORT_SEL_B;
3206                         break;
3207                 case PCH_DP_C:
3208                         temp |= TRANS_DP_PORT_SEL_C;
3209                         break;
3210                 case PCH_DP_D:
3211                         temp |= TRANS_DP_PORT_SEL_D;
3212                         break;
3213                 default:
3214                         BUG();
3215                 }
3216
3217                 I915_WRITE(reg, temp);
3218         }
3219
3220         ironlake_enable_pch_transcoder(dev_priv, pipe);
3221 }
3222
3223 static void lpt_pch_enable(struct drm_crtc *crtc)
3224 {
3225         struct drm_device *dev = crtc->dev;
3226         struct drm_i915_private *dev_priv = dev->dev_private;
3227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3228         int pipe = intel_crtc->pipe;
3229         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3230
3231         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3232
3233         /* Write the TU size bits before fdi link training, so that error
3234          * detection works. */
3235         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3236                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3237
3238         /* For PCH output, training FDI link */
3239         dev_priv->display.fdi_link_train(crtc);
3240
3241         lpt_program_iclkip(crtc);
3242
3243         /* Set transcoder timing. */
3244         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3245         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3246         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3247
3248         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3249         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3250         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3251         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3252
3253         lpt_enable_pch_transcoder(dev_priv, intel_crtc->pipe);
3254 }
3255
3256 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3257 {
3258         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3259
3260         if (pll == NULL)
3261                 return;
3262
3263         if (pll->refcount == 0) {
3264                 WARN(1, "bad PCH PLL refcount\n");
3265                 return;
3266         }
3267
3268         --pll->refcount;
3269         intel_crtc->pch_pll = NULL;
3270 }
3271
3272 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3273 {
3274         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3275         struct intel_pch_pll *pll;
3276         int i;
3277
3278         pll = intel_crtc->pch_pll;
3279         if (pll) {
3280                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3281                               intel_crtc->base.base.id, pll->pll_reg);
3282                 goto prepare;
3283         }
3284
3285         if (HAS_PCH_IBX(dev_priv->dev)) {
3286                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3287                 i = intel_crtc->pipe;
3288                 pll = &dev_priv->pch_plls[i];
3289
3290                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3291                               intel_crtc->base.base.id, pll->pll_reg);
3292
3293                 goto found;
3294         }
3295
3296         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3297                 pll = &dev_priv->pch_plls[i];
3298
3299                 /* Only want to check enabled timings first */
3300                 if (pll->refcount == 0)
3301                         continue;
3302
3303                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3304                     fp == I915_READ(pll->fp0_reg)) {
3305                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3306                                       intel_crtc->base.base.id,
3307                                       pll->pll_reg, pll->refcount, pll->active);
3308
3309                         goto found;
3310                 }
3311         }
3312
3313         /* Ok no matching timings, maybe there's a free one? */
3314         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3315                 pll = &dev_priv->pch_plls[i];
3316                 if (pll->refcount == 0) {
3317                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3318                                       intel_crtc->base.base.id, pll->pll_reg);
3319                         goto found;
3320                 }
3321         }
3322
3323         return NULL;
3324
3325 found:
3326         intel_crtc->pch_pll = pll;
3327         pll->refcount++;
3328         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3329 prepare: /* separate function? */
3330         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3331
3332         /* Wait for the clocks to stabilize before rewriting the regs */
3333         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3334         POSTING_READ(pll->pll_reg);
3335         udelay(150);
3336
3337         I915_WRITE(pll->fp0_reg, fp);
3338         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3339         pll->on = false;
3340         return pll;
3341 }
3342
3343 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3344 {
3345         struct drm_i915_private *dev_priv = dev->dev_private;
3346         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3347         u32 temp;
3348
3349         temp = I915_READ(dslreg);
3350         udelay(500);
3351         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3352                 /* Without this, mode sets may fail silently on FDI */
3353                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3354                 udelay(250);
3355                 I915_WRITE(tc2reg, 0);
3356                 if (wait_for(I915_READ(dslreg) != temp, 5))
3357                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3358         }
3359 }
3360
3361 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3362 {
3363         struct drm_device *dev = crtc->dev;
3364         struct drm_i915_private *dev_priv = dev->dev_private;
3365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366         struct intel_encoder *encoder;
3367         int pipe = intel_crtc->pipe;
3368         int plane = intel_crtc->plane;
3369         u32 temp;
3370         bool is_pch_port;
3371
3372         WARN_ON(!crtc->enabled);
3373
3374         if (intel_crtc->active)
3375                 return;
3376
3377         intel_crtc->active = true;
3378         intel_update_watermarks(dev);
3379
3380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3381                 temp = I915_READ(PCH_LVDS);
3382                 if ((temp & LVDS_PORT_EN) == 0)
3383                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3384         }
3385
3386         is_pch_port = ironlake_crtc_driving_pch(crtc);
3387
3388         if (is_pch_port) {
3389                 /* Note: FDI PLL enabling _must_ be done before we enable the
3390                  * cpu pipes, hence this is separate from all the other fdi/pch
3391                  * enabling. */
3392                 ironlake_fdi_pll_enable(intel_crtc);
3393         } else {
3394                 assert_fdi_tx_disabled(dev_priv, pipe);
3395                 assert_fdi_rx_disabled(dev_priv, pipe);
3396         }
3397
3398         for_each_encoder_on_crtc(dev, crtc, encoder)
3399                 if (encoder->pre_enable)
3400                         encoder->pre_enable(encoder);
3401
3402         /* Enable panel fitting for LVDS */
3403         if (dev_priv->pch_pf_size &&
3404             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3405                 /* Force use of hard-coded filter coefficients
3406                  * as some pre-programmed values are broken,
3407                  * e.g. x201.
3408                  */
3409                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3410                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3411                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3412         }
3413
3414         /*
3415          * On ILK+ LUT must be loaded before the pipe is running but with
3416          * clocks enabled
3417          */
3418         intel_crtc_load_lut(crtc);
3419
3420         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3421         intel_enable_plane(dev_priv, plane, pipe);
3422
3423         if (is_pch_port)
3424                 ironlake_pch_enable(crtc);
3425
3426         mutex_lock(&dev->struct_mutex);
3427         intel_update_fbc(dev);
3428         mutex_unlock(&dev->struct_mutex);
3429
3430         intel_crtc_update_cursor(crtc, true);
3431
3432         for_each_encoder_on_crtc(dev, crtc, encoder)
3433                 encoder->enable(encoder);
3434
3435         if (HAS_PCH_CPT(dev))
3436                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3437
3438         /*
3439          * There seems to be a race in PCH platform hw (at least on some
3440          * outputs) where an enabled pipe still completes any pageflip right
3441          * away (as if the pipe is off) instead of waiting for vblank. As soon
3442          * as the first vblank happend, everything works as expected. Hence just
3443          * wait for one vblank before returning to avoid strange things
3444          * happening.
3445          */
3446         intel_wait_for_vblank(dev, intel_crtc->pipe);
3447 }
3448
3449 static void haswell_crtc_enable(struct drm_crtc *crtc)
3450 {
3451         struct drm_device *dev = crtc->dev;
3452         struct drm_i915_private *dev_priv = dev->dev_private;
3453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454         struct intel_encoder *encoder;
3455         int pipe = intel_crtc->pipe;
3456         int plane = intel_crtc->plane;
3457         bool is_pch_port;
3458
3459         WARN_ON(!crtc->enabled);
3460
3461         if (intel_crtc->active)
3462                 return;
3463
3464         intel_crtc->active = true;
3465         intel_update_watermarks(dev);
3466
3467         is_pch_port = haswell_crtc_driving_pch(crtc);
3468
3469         if (is_pch_port)
3470                 ironlake_fdi_pll_enable(intel_crtc);
3471
3472         for_each_encoder_on_crtc(dev, crtc, encoder)
3473                 if (encoder->pre_enable)
3474                         encoder->pre_enable(encoder);
3475
3476         intel_ddi_enable_pipe_clock(intel_crtc);
3477
3478         /* Enable panel fitting for eDP */
3479         if (dev_priv->pch_pf_size && HAS_eDP) {
3480                 /* Force use of hard-coded filter coefficients
3481                  * as some pre-programmed values are broken,
3482                  * e.g. x201.
3483                  */
3484                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3485                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3486                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3487         }
3488
3489         /*
3490          * On ILK+ LUT must be loaded before the pipe is running but with
3491          * clocks enabled
3492          */
3493         intel_crtc_load_lut(crtc);
3494
3495         intel_ddi_set_pipe_settings(crtc);
3496         intel_ddi_enable_pipe_func(crtc);
3497
3498         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3499         intel_enable_plane(dev_priv, plane, pipe);
3500
3501         if (is_pch_port)
3502                 lpt_pch_enable(crtc);
3503
3504         mutex_lock(&dev->struct_mutex);
3505         intel_update_fbc(dev);
3506         mutex_unlock(&dev->struct_mutex);
3507
3508         intel_crtc_update_cursor(crtc, true);
3509
3510         for_each_encoder_on_crtc(dev, crtc, encoder)
3511                 encoder->enable(encoder);
3512
3513         /*
3514          * There seems to be a race in PCH platform hw (at least on some
3515          * outputs) where an enabled pipe still completes any pageflip right
3516          * away (as if the pipe is off) instead of waiting for vblank. As soon
3517          * as the first vblank happend, everything works as expected. Hence just
3518          * wait for one vblank before returning to avoid strange things
3519          * happening.
3520          */
3521         intel_wait_for_vblank(dev, intel_crtc->pipe);
3522 }
3523
3524 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3525 {
3526         struct drm_device *dev = crtc->dev;
3527         struct drm_i915_private *dev_priv = dev->dev_private;
3528         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3529         struct intel_encoder *encoder;
3530         int pipe = intel_crtc->pipe;
3531         int plane = intel_crtc->plane;
3532         u32 reg, temp;
3533
3534
3535         if (!intel_crtc->active)
3536                 return;
3537
3538         for_each_encoder_on_crtc(dev, crtc, encoder)
3539                 encoder->disable(encoder);
3540
3541         intel_crtc_wait_for_pending_flips(crtc);
3542         drm_vblank_off(dev, pipe);
3543         intel_crtc_update_cursor(crtc, false);
3544
3545         intel_disable_plane(dev_priv, plane, pipe);
3546
3547         if (dev_priv->cfb_plane == plane)
3548                 intel_disable_fbc(dev);
3549
3550         intel_disable_pipe(dev_priv, pipe);
3551
3552         /* Disable PF */
3553         I915_WRITE(PF_CTL(pipe), 0);
3554         I915_WRITE(PF_WIN_SZ(pipe), 0);
3555
3556         for_each_encoder_on_crtc(dev, crtc, encoder)
3557                 if (encoder->post_disable)
3558                         encoder->post_disable(encoder);
3559
3560         ironlake_fdi_disable(crtc);
3561
3562         ironlake_disable_pch_transcoder(dev_priv, pipe);
3563
3564         if (HAS_PCH_CPT(dev)) {
3565                 /* disable TRANS_DP_CTL */
3566                 reg = TRANS_DP_CTL(pipe);
3567                 temp = I915_READ(reg);
3568                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3569                 temp |= TRANS_DP_PORT_SEL_NONE;
3570                 I915_WRITE(reg, temp);
3571
3572                 /* disable DPLL_SEL */
3573                 temp = I915_READ(PCH_DPLL_SEL);
3574                 switch (pipe) {
3575                 case 0:
3576                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3577                         break;
3578                 case 1:
3579                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3580                         break;
3581                 case 2:
3582                         /* C shares PLL A or B */
3583                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3584                         break;
3585                 default:
3586                         BUG(); /* wtf */
3587                 }
3588                 I915_WRITE(PCH_DPLL_SEL, temp);
3589         }
3590
3591         /* disable PCH DPLL */
3592         intel_disable_pch_pll(intel_crtc);
3593
3594         ironlake_fdi_pll_disable(intel_crtc);
3595
3596         intel_crtc->active = false;
3597         intel_update_watermarks(dev);
3598
3599         mutex_lock(&dev->struct_mutex);
3600         intel_update_fbc(dev);
3601         mutex_unlock(&dev->struct_mutex);
3602 }
3603
3604 static void haswell_crtc_disable(struct drm_crtc *crtc)
3605 {
3606         struct drm_device *dev = crtc->dev;
3607         struct drm_i915_private *dev_priv = dev->dev_private;
3608         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609         struct intel_encoder *encoder;
3610         int pipe = intel_crtc->pipe;
3611         int plane = intel_crtc->plane;
3612         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3613         bool is_pch_port;
3614
3615         if (!intel_crtc->active)
3616                 return;
3617
3618         is_pch_port = haswell_crtc_driving_pch(crtc);
3619
3620         for_each_encoder_on_crtc(dev, crtc, encoder)
3621                 encoder->disable(encoder);
3622
3623         intel_crtc_wait_for_pending_flips(crtc);
3624         drm_vblank_off(dev, pipe);
3625         intel_crtc_update_cursor(crtc, false);
3626
3627         intel_disable_plane(dev_priv, plane, pipe);
3628
3629         if (dev_priv->cfb_plane == plane)
3630                 intel_disable_fbc(dev);
3631
3632         intel_disable_pipe(dev_priv, pipe);
3633
3634         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3635
3636         /* Disable PF */
3637         I915_WRITE(PF_CTL(pipe), 0);
3638         I915_WRITE(PF_WIN_SZ(pipe), 0);
3639
3640         intel_ddi_disable_pipe_clock(intel_crtc);
3641
3642         for_each_encoder_on_crtc(dev, crtc, encoder)
3643                 if (encoder->post_disable)
3644                         encoder->post_disable(encoder);
3645
3646         if (is_pch_port) {
3647                 ironlake_fdi_disable(crtc);
3648                 lpt_disable_pch_transcoder(dev_priv, pipe);
3649                 intel_disable_pch_pll(intel_crtc);
3650                 ironlake_fdi_pll_disable(intel_crtc);
3651         }
3652
3653         intel_crtc->active = false;
3654         intel_update_watermarks(dev);
3655
3656         mutex_lock(&dev->struct_mutex);
3657         intel_update_fbc(dev);
3658         mutex_unlock(&dev->struct_mutex);
3659 }
3660
3661 static void ironlake_crtc_off(struct drm_crtc *crtc)
3662 {
3663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3664         intel_put_pch_pll(intel_crtc);
3665 }
3666
3667 static void haswell_crtc_off(struct drm_crtc *crtc)
3668 {
3669         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3670
3671         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3672          * start using it. */
3673         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3674
3675         intel_ddi_put_crtc_pll(crtc);
3676 }
3677
3678 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3679 {
3680         if (!enable && intel_crtc->overlay) {
3681                 struct drm_device *dev = intel_crtc->base.dev;
3682                 struct drm_i915_private *dev_priv = dev->dev_private;
3683
3684                 mutex_lock(&dev->struct_mutex);
3685                 dev_priv->mm.interruptible = false;
3686                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3687                 dev_priv->mm.interruptible = true;
3688                 mutex_unlock(&dev->struct_mutex);
3689         }
3690
3691         /* Let userspace switch the overlay on again. In most cases userspace
3692          * has to recompute where to put it anyway.
3693          */
3694 }
3695
3696 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3697 {
3698         struct drm_device *dev = crtc->dev;
3699         struct drm_i915_private *dev_priv = dev->dev_private;
3700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3701         struct intel_encoder *encoder;
3702         int pipe = intel_crtc->pipe;
3703         int plane = intel_crtc->plane;
3704
3705         WARN_ON(!crtc->enabled);
3706
3707         if (intel_crtc->active)
3708                 return;
3709
3710         intel_crtc->active = true;
3711         intel_update_watermarks(dev);
3712
3713         intel_enable_pll(dev_priv, pipe);
3714         intel_enable_pipe(dev_priv, pipe, false);
3715         intel_enable_plane(dev_priv, plane, pipe);
3716
3717         intel_crtc_load_lut(crtc);
3718         intel_update_fbc(dev);
3719
3720         /* Give the overlay scaler a chance to enable if it's on this pipe */
3721         intel_crtc_dpms_overlay(intel_crtc, true);
3722         intel_crtc_update_cursor(crtc, true);
3723
3724         for_each_encoder_on_crtc(dev, crtc, encoder)
3725                 encoder->enable(encoder);
3726 }
3727
3728 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3729 {
3730         struct drm_device *dev = crtc->dev;
3731         struct drm_i915_private *dev_priv = dev->dev_private;
3732         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3733         struct intel_encoder *encoder;
3734         int pipe = intel_crtc->pipe;
3735         int plane = intel_crtc->plane;
3736
3737
3738         if (!intel_crtc->active)
3739                 return;
3740
3741         for_each_encoder_on_crtc(dev, crtc, encoder)
3742                 encoder->disable(encoder);
3743
3744         /* Give the overlay scaler a chance to disable if it's on this pipe */
3745         intel_crtc_wait_for_pending_flips(crtc);
3746         drm_vblank_off(dev, pipe);
3747         intel_crtc_dpms_overlay(intel_crtc, false);
3748         intel_crtc_update_cursor(crtc, false);
3749
3750         if (dev_priv->cfb_plane == plane)
3751                 intel_disable_fbc(dev);
3752
3753         intel_disable_plane(dev_priv, plane, pipe);
3754         intel_disable_pipe(dev_priv, pipe);
3755         intel_disable_pll(dev_priv, pipe);
3756
3757         intel_crtc->active = false;
3758         intel_update_fbc(dev);
3759         intel_update_watermarks(dev);
3760 }
3761
3762 static void i9xx_crtc_off(struct drm_crtc *crtc)
3763 {
3764 }
3765
3766 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3767                                     bool enabled)
3768 {
3769         struct drm_device *dev = crtc->dev;
3770         struct drm_i915_master_private *master_priv;
3771         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3772         int pipe = intel_crtc->pipe;
3773
3774         if (!dev->primary->master)
3775                 return;
3776
3777         master_priv = dev->primary->master->driver_priv;
3778         if (!master_priv->sarea_priv)
3779                 return;
3780
3781         switch (pipe) {
3782         case 0:
3783                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3784                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3785                 break;
3786         case 1:
3787                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3788                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3789                 break;
3790         default:
3791                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3792                 break;
3793         }
3794 }
3795
3796 /**
3797  * Sets the power management mode of the pipe and plane.
3798  */
3799 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3800 {
3801         struct drm_device *dev = crtc->dev;
3802         struct drm_i915_private *dev_priv = dev->dev_private;
3803         struct intel_encoder *intel_encoder;
3804         bool enable = false;
3805
3806         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3807                 enable |= intel_encoder->connectors_active;
3808
3809         if (enable)
3810                 dev_priv->display.crtc_enable(crtc);
3811         else
3812                 dev_priv->display.crtc_disable(crtc);
3813
3814         intel_crtc_update_sarea(crtc, enable);
3815 }
3816
3817 static void intel_crtc_noop(struct drm_crtc *crtc)
3818 {
3819 }
3820
3821 static void intel_crtc_disable(struct drm_crtc *crtc)
3822 {
3823         struct drm_device *dev = crtc->dev;
3824         struct drm_connector *connector;
3825         struct drm_i915_private *dev_priv = dev->dev_private;
3826
3827         /* crtc should still be enabled when we disable it. */
3828         WARN_ON(!crtc->enabled);
3829
3830         dev_priv->display.crtc_disable(crtc);
3831         intel_crtc_update_sarea(crtc, false);
3832         dev_priv->display.off(crtc);
3833
3834         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3835         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3836
3837         if (crtc->fb) {
3838                 mutex_lock(&dev->struct_mutex);
3839                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3840                 mutex_unlock(&dev->struct_mutex);
3841                 crtc->fb = NULL;
3842         }
3843
3844         /* Update computed state. */
3845         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3846                 if (!connector->encoder || !connector->encoder->crtc)
3847                         continue;
3848
3849                 if (connector->encoder->crtc != crtc)
3850                         continue;
3851
3852                 connector->dpms = DRM_MODE_DPMS_OFF;
3853                 to_intel_encoder(connector->encoder)->connectors_active = false;
3854         }
3855 }
3856
3857 void intel_modeset_disable(struct drm_device *dev)
3858 {
3859         struct drm_crtc *crtc;
3860
3861         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3862                 if (crtc->enabled)
3863                         intel_crtc_disable(crtc);
3864         }
3865 }
3866
3867 void intel_encoder_noop(struct drm_encoder *encoder)
3868 {
3869 }
3870
3871 void intel_encoder_destroy(struct drm_encoder *encoder)
3872 {
3873         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3874
3875         drm_encoder_cleanup(encoder);
3876         kfree(intel_encoder);
3877 }
3878
3879 /* Simple dpms helper for encodres with just one connector, no cloning and only
3880  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3881  * state of the entire output pipe. */
3882 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3883 {
3884         if (mode == DRM_MODE_DPMS_ON) {
3885                 encoder->connectors_active = true;
3886
3887                 intel_crtc_update_dpms(encoder->base.crtc);
3888         } else {
3889                 encoder->connectors_active = false;
3890
3891                 intel_crtc_update_dpms(encoder->base.crtc);
3892         }
3893 }
3894
3895 /* Cross check the actual hw state with our own modeset state tracking (and it's
3896  * internal consistency). */
3897 static void intel_connector_check_state(struct intel_connector *connector)
3898 {
3899         if (connector->get_hw_state(connector)) {
3900                 struct intel_encoder *encoder = connector->encoder;
3901                 struct drm_crtc *crtc;
3902                 bool encoder_enabled;
3903                 enum pipe pipe;
3904
3905                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3906                               connector->base.base.id,
3907                               drm_get_connector_name(&connector->base));
3908
3909                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3910                      "wrong connector dpms state\n");
3911                 WARN(connector->base.encoder != &encoder->base,
3912                      "active connector not linked to encoder\n");
3913                 WARN(!encoder->connectors_active,
3914                      "encoder->connectors_active not set\n");
3915
3916                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3917                 WARN(!encoder_enabled, "encoder not enabled\n");
3918                 if (WARN_ON(!encoder->base.crtc))
3919                         return;
3920
3921                 crtc = encoder->base.crtc;
3922
3923                 WARN(!crtc->enabled, "crtc not enabled\n");
3924                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3925                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3926                      "encoder active on the wrong pipe\n");
3927         }
3928 }
3929
3930 /* Even simpler default implementation, if there's really no special case to
3931  * consider. */
3932 void intel_connector_dpms(struct drm_connector *connector, int mode)
3933 {
3934         struct intel_encoder *encoder = intel_attached_encoder(connector);
3935
3936         /* All the simple cases only support two dpms states. */
3937         if (mode != DRM_MODE_DPMS_ON)
3938                 mode = DRM_MODE_DPMS_OFF;
3939
3940         if (mode == connector->dpms)
3941                 return;
3942
3943         connector->dpms = mode;
3944
3945         /* Only need to change hw state when actually enabled */
3946         if (encoder->base.crtc)
3947                 intel_encoder_dpms(encoder, mode);
3948         else
3949                 WARN_ON(encoder->connectors_active != false);
3950
3951         intel_modeset_check_state(connector->dev);
3952 }
3953
3954 /* Simple connector->get_hw_state implementation for encoders that support only
3955  * one connector and no cloning and hence the encoder state determines the state
3956  * of the connector. */
3957 bool intel_connector_get_hw_state(struct intel_connector *connector)
3958 {
3959         enum pipe pipe = 0;
3960         struct intel_encoder *encoder = connector->encoder;
3961
3962         return encoder->get_hw_state(encoder, &pipe);
3963 }
3964
3965 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3966                                   const struct drm_display_mode *mode,
3967                                   struct drm_display_mode *adjusted_mode)
3968 {
3969         struct drm_device *dev = crtc->dev;
3970
3971         if (HAS_PCH_SPLIT(dev)) {
3972                 /* FDI link clock is fixed at 2.7G */
3973                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3974                         return false;
3975         }
3976
3977         /* All interlaced capable intel hw wants timings in frames. Note though
3978          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3979          * timings, so we need to be careful not to clobber these.*/
3980         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3981                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3982
3983         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3984          * with a hsync front porch of 0.
3985          */
3986         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3987                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3988                 return false;
3989
3990         return true;
3991 }
3992
3993 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3994 {
3995         return 400000; /* FIXME */
3996 }
3997
3998 static int i945_get_display_clock_speed(struct drm_device *dev)
3999 {
4000         return 400000;
4001 }
4002
4003 static int i915_get_display_clock_speed(struct drm_device *dev)
4004 {
4005         return 333000;
4006 }
4007
4008 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4009 {
4010         return 200000;
4011 }
4012
4013 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4014 {
4015         u16 gcfgc = 0;
4016
4017         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4018
4019         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4020                 return 133000;
4021         else {
4022                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4023                 case GC_DISPLAY_CLOCK_333_MHZ:
4024                         return 333000;
4025                 default:
4026                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4027                         return 190000;
4028                 }
4029         }
4030 }
4031
4032 static int i865_get_display_clock_speed(struct drm_device *dev)
4033 {
4034         return 266000;
4035 }
4036
4037 static int i855_get_display_clock_speed(struct drm_device *dev)
4038 {
4039         u16 hpllcc = 0;
4040         /* Assume that the hardware is in the high speed state.  This
4041          * should be the default.
4042          */
4043         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4044         case GC_CLOCK_133_200:
4045         case GC_CLOCK_100_200:
4046                 return 200000;
4047         case GC_CLOCK_166_250:
4048                 return 250000;
4049         case GC_CLOCK_100_133:
4050                 return 133000;
4051         }
4052
4053         /* Shouldn't happen */
4054         return 0;
4055 }
4056
4057 static int i830_get_display_clock_speed(struct drm_device *dev)
4058 {
4059         return 133000;
4060 }
4061
4062 struct fdi_m_n {
4063         u32        tu;
4064         u32        gmch_m;
4065         u32        gmch_n;
4066         u32        link_m;
4067         u32        link_n;
4068 };
4069
4070 static void
4071 fdi_reduce_ratio(u32 *num, u32 *den)
4072 {
4073         while (*num > 0xffffff || *den > 0xffffff) {
4074                 *num >>= 1;
4075                 *den >>= 1;
4076         }
4077 }
4078
4079 static void
4080 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4081                      int link_clock, struct fdi_m_n *m_n)
4082 {
4083         m_n->tu = 64; /* default size */
4084
4085         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4086         m_n->gmch_m = bits_per_pixel * pixel_clock;
4087         m_n->gmch_n = link_clock * nlanes * 8;
4088         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4089
4090         m_n->link_m = pixel_clock;
4091         m_n->link_n = link_clock;
4092         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4093 }
4094
4095 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4096 {
4097         if (i915_panel_use_ssc >= 0)
4098                 return i915_panel_use_ssc != 0;
4099         return dev_priv->lvds_use_ssc
4100                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4101 }
4102
4103 /**
4104  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4105  * @crtc: CRTC structure
4106  * @mode: requested mode
4107  *
4108  * A pipe may be connected to one or more outputs.  Based on the depth of the
4109  * attached framebuffer, choose a good color depth to use on the pipe.
4110  *
4111  * If possible, match the pipe depth to the fb depth.  In some cases, this
4112  * isn't ideal, because the connected output supports a lesser or restricted
4113  * set of depths.  Resolve that here:
4114  *    LVDS typically supports only 6bpc, so clamp down in that case
4115  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4116  *    Displays may support a restricted set as well, check EDID and clamp as
4117  *      appropriate.
4118  *    DP may want to dither down to 6bpc to fit larger modes
4119  *
4120  * RETURNS:
4121  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4122  * true if they don't match).
4123  */
4124 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4125                                          struct drm_framebuffer *fb,
4126                                          unsigned int *pipe_bpp,
4127                                          struct drm_display_mode *mode)
4128 {
4129         struct drm_device *dev = crtc->dev;
4130         struct drm_i915_private *dev_priv = dev->dev_private;
4131         struct drm_connector *connector;
4132         struct intel_encoder *intel_encoder;
4133         unsigned int display_bpc = UINT_MAX, bpc;
4134
4135         /* Walk the encoders & connectors on this crtc, get min bpc */
4136         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4137
4138                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4139                         unsigned int lvds_bpc;
4140
4141                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4142                             LVDS_A3_POWER_UP)
4143                                 lvds_bpc = 8;
4144                         else
4145                                 lvds_bpc = 6;
4146
4147                         if (lvds_bpc < display_bpc) {
4148                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4149                                 display_bpc = lvds_bpc;
4150                         }
4151                         continue;
4152                 }
4153
4154                 /* Not one of the known troublemakers, check the EDID */
4155                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4156                                     head) {
4157                         if (connector->encoder != &intel_encoder->base)
4158                                 continue;
4159
4160                         /* Don't use an invalid EDID bpc value */
4161                         if (connector->display_info.bpc &&
4162                             connector->display_info.bpc < display_bpc) {
4163                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4164                                 display_bpc = connector->display_info.bpc;
4165                         }
4166                 }
4167
4168                 /*
4169                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4170                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4171                  */
4172                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4173                         if (display_bpc > 8 && display_bpc < 12) {
4174                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4175                                 display_bpc = 12;
4176                         } else {
4177                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4178                                 display_bpc = 8;
4179                         }
4180                 }
4181         }
4182
4183         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4184                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4185                 display_bpc = 6;
4186         }
4187
4188         /*
4189          * We could just drive the pipe at the highest bpc all the time and
4190          * enable dithering as needed, but that costs bandwidth.  So choose
4191          * the minimum value that expresses the full color range of the fb but
4192          * also stays within the max display bpc discovered above.
4193          */
4194
4195         switch (fb->depth) {
4196         case 8:
4197                 bpc = 8; /* since we go through a colormap */
4198                 break;
4199         case 15:
4200         case 16:
4201                 bpc = 6; /* min is 18bpp */
4202                 break;
4203         case 24:
4204                 bpc = 8;
4205                 break;
4206         case 30:
4207                 bpc = 10;
4208                 break;
4209         case 48:
4210                 bpc = 12;
4211                 break;
4212         default:
4213                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4214                 bpc = min((unsigned int)8, display_bpc);
4215                 break;
4216         }
4217
4218         display_bpc = min(display_bpc, bpc);
4219
4220         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4221                       bpc, display_bpc);
4222
4223         *pipe_bpp = display_bpc * 3;
4224
4225         return display_bpc != bpc;
4226 }
4227
4228 static int vlv_get_refclk(struct drm_crtc *crtc)
4229 {
4230         struct drm_device *dev = crtc->dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         int refclk = 27000; /* for DP & HDMI */
4233
4234         return 100000; /* only one validated so far */
4235
4236         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4237                 refclk = 96000;
4238         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4239                 if (intel_panel_use_ssc(dev_priv))
4240                         refclk = 100000;
4241                 else
4242                         refclk = 96000;
4243         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4244                 refclk = 100000;
4245         }
4246
4247         return refclk;
4248 }
4249
4250 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4251 {
4252         struct drm_device *dev = crtc->dev;
4253         struct drm_i915_private *dev_priv = dev->dev_private;
4254         int refclk;
4255
4256         if (IS_VALLEYVIEW(dev)) {
4257                 refclk = vlv_get_refclk(crtc);
4258         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4259             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4260                 refclk = dev_priv->lvds_ssc_freq * 1000;
4261                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4262                               refclk / 1000);
4263         } else if (!IS_GEN2(dev)) {
4264                 refclk = 96000;
4265         } else {
4266                 refclk = 48000;
4267         }
4268
4269         return refclk;
4270 }
4271
4272 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4273                                       intel_clock_t *clock)
4274 {
4275         /* SDVO TV has fixed PLL values depend on its clock range,
4276            this mirrors vbios setting. */
4277         if (adjusted_mode->clock >= 100000
4278             && adjusted_mode->clock < 140500) {
4279                 clock->p1 = 2;
4280                 clock->p2 = 10;
4281                 clock->n = 3;
4282                 clock->m1 = 16;
4283                 clock->m2 = 8;
4284         } else if (adjusted_mode->clock >= 140500
4285                    && adjusted_mode->clock <= 200000) {
4286                 clock->p1 = 1;
4287                 clock->p2 = 10;
4288                 clock->n = 6;
4289                 clock->m1 = 12;
4290                 clock->m2 = 8;
4291         }
4292 }
4293
4294 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4295                                      intel_clock_t *clock,
4296                                      intel_clock_t *reduced_clock)
4297 {
4298         struct drm_device *dev = crtc->dev;
4299         struct drm_i915_private *dev_priv = dev->dev_private;
4300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4301         int pipe = intel_crtc->pipe;
4302         u32 fp, fp2 = 0;
4303
4304         if (IS_PINEVIEW(dev)) {
4305                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4306                 if (reduced_clock)
4307                         fp2 = (1 << reduced_clock->n) << 16 |
4308                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4309         } else {
4310                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4311                 if (reduced_clock)
4312                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4313                                 reduced_clock->m2;
4314         }
4315
4316         I915_WRITE(FP0(pipe), fp);
4317
4318         intel_crtc->lowfreq_avail = false;
4319         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4320             reduced_clock && i915_powersave) {
4321                 I915_WRITE(FP1(pipe), fp2);
4322                 intel_crtc->lowfreq_avail = true;
4323         } else {
4324                 I915_WRITE(FP1(pipe), fp);
4325         }
4326 }
4327
4328 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4329                               struct drm_display_mode *adjusted_mode)
4330 {
4331         struct drm_device *dev = crtc->dev;
4332         struct drm_i915_private *dev_priv = dev->dev_private;
4333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4334         int pipe = intel_crtc->pipe;
4335         u32 temp;
4336
4337         temp = I915_READ(LVDS);
4338         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4339         if (pipe == 1) {
4340                 temp |= LVDS_PIPEB_SELECT;
4341         } else {
4342                 temp &= ~LVDS_PIPEB_SELECT;
4343         }
4344         /* set the corresponsding LVDS_BORDER bit */
4345         temp |= dev_priv->lvds_border_bits;
4346         /* Set the B0-B3 data pairs corresponding to whether we're going to
4347          * set the DPLLs for dual-channel mode or not.
4348          */
4349         if (clock->p2 == 7)
4350                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4351         else
4352                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4353
4354         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4355          * appropriately here, but we need to look more thoroughly into how
4356          * panels behave in the two modes.
4357          */
4358         /* set the dithering flag on LVDS as needed */
4359         if (INTEL_INFO(dev)->gen >= 4) {
4360                 if (dev_priv->lvds_dither)
4361                         temp |= LVDS_ENABLE_DITHER;
4362                 else
4363                         temp &= ~LVDS_ENABLE_DITHER;
4364         }
4365         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4366         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4367                 temp |= LVDS_HSYNC_POLARITY;
4368         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4369                 temp |= LVDS_VSYNC_POLARITY;
4370         I915_WRITE(LVDS, temp);
4371 }
4372
4373 static void vlv_update_pll(struct drm_crtc *crtc,
4374                            struct drm_display_mode *mode,
4375                            struct drm_display_mode *adjusted_mode,
4376                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4377                            int num_connectors)
4378 {
4379         struct drm_device *dev = crtc->dev;
4380         struct drm_i915_private *dev_priv = dev->dev_private;
4381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4382         int pipe = intel_crtc->pipe;
4383         u32 dpll, mdiv, pdiv;
4384         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4385         bool is_sdvo;
4386         u32 temp;
4387
4388         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4389                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4390
4391         dpll = DPLL_VGA_MODE_DIS;
4392         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4393         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4394         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4395
4396         I915_WRITE(DPLL(pipe), dpll);
4397         POSTING_READ(DPLL(pipe));
4398
4399         bestn = clock->n;
4400         bestm1 = clock->m1;
4401         bestm2 = clock->m2;
4402         bestp1 = clock->p1;
4403         bestp2 = clock->p2;
4404
4405         /*
4406          * In Valleyview PLL and program lane counter registers are exposed
4407          * through DPIO interface
4408          */
4409         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4410         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4411         mdiv |= ((bestn << DPIO_N_SHIFT));
4412         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4413         mdiv |= (1 << DPIO_K_SHIFT);
4414         mdiv |= DPIO_ENABLE_CALIBRATION;
4415         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4416
4417         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4418
4419         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4420                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4421                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4422                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4423         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4424
4425         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4426
4427         dpll |= DPLL_VCO_ENABLE;
4428         I915_WRITE(DPLL(pipe), dpll);
4429         POSTING_READ(DPLL(pipe));
4430         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4431                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4432
4433         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4434
4435         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4436                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4437
4438         I915_WRITE(DPLL(pipe), dpll);
4439
4440         /* Wait for the clocks to stabilize. */
4441         POSTING_READ(DPLL(pipe));
4442         udelay(150);
4443
4444         temp = 0;
4445         if (is_sdvo) {
4446                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4447                 if (temp > 1)
4448                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4449                 else
4450                         temp = 0;
4451         }
4452         I915_WRITE(DPLL_MD(pipe), temp);
4453         POSTING_READ(DPLL_MD(pipe));
4454
4455         /* Now program lane control registers */
4456         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4457                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4458         {
4459                 temp = 0x1000C4;
4460                 if(pipe == 1)
4461                         temp |= (1 << 21);
4462                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4463         }
4464         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4465         {
4466                 temp = 0x1000C4;
4467                 if(pipe == 1)
4468                         temp |= (1 << 21);
4469                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4470         }
4471 }
4472
4473 static void i9xx_update_pll(struct drm_crtc *crtc,
4474                             struct drm_display_mode *mode,
4475                             struct drm_display_mode *adjusted_mode,
4476                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4477                             int num_connectors)
4478 {
4479         struct drm_device *dev = crtc->dev;
4480         struct drm_i915_private *dev_priv = dev->dev_private;
4481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4482         int pipe = intel_crtc->pipe;
4483         u32 dpll;
4484         bool is_sdvo;
4485
4486         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4487
4488         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4489                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4490
4491         dpll = DPLL_VGA_MODE_DIS;
4492
4493         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4494                 dpll |= DPLLB_MODE_LVDS;
4495         else
4496                 dpll |= DPLLB_MODE_DAC_SERIAL;
4497         if (is_sdvo) {
4498                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4499                 if (pixel_multiplier > 1) {
4500                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4501                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4502                 }
4503                 dpll |= DPLL_DVO_HIGH_SPEED;
4504         }
4505         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4506                 dpll |= DPLL_DVO_HIGH_SPEED;
4507
4508         /* compute bitmask from p1 value */
4509         if (IS_PINEVIEW(dev))
4510                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4511         else {
4512                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4513                 if (IS_G4X(dev) && reduced_clock)
4514                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4515         }
4516         switch (clock->p2) {
4517         case 5:
4518                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4519                 break;
4520         case 7:
4521                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4522                 break;
4523         case 10:
4524                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4525                 break;
4526         case 14:
4527                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4528                 break;
4529         }
4530         if (INTEL_INFO(dev)->gen >= 4)
4531                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4532
4533         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4534                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4535         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4536                 /* XXX: just matching BIOS for now */
4537                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4538                 dpll |= 3;
4539         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4540                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4541                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4542         else
4543                 dpll |= PLL_REF_INPUT_DREFCLK;
4544
4545         dpll |= DPLL_VCO_ENABLE;
4546         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4547         POSTING_READ(DPLL(pipe));
4548         udelay(150);
4549
4550         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4551          * This is an exception to the general rule that mode_set doesn't turn
4552          * things on.
4553          */
4554         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4555                 intel_update_lvds(crtc, clock, adjusted_mode);
4556
4557         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4558                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4559
4560         I915_WRITE(DPLL(pipe), dpll);
4561
4562         /* Wait for the clocks to stabilize. */
4563         POSTING_READ(DPLL(pipe));
4564         udelay(150);
4565
4566         if (INTEL_INFO(dev)->gen >= 4) {
4567                 u32 temp = 0;
4568                 if (is_sdvo) {
4569                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4570                         if (temp > 1)
4571                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4572                         else
4573                                 temp = 0;
4574                 }
4575                 I915_WRITE(DPLL_MD(pipe), temp);
4576         } else {
4577                 /* The pixel multiplier can only be updated once the
4578                  * DPLL is enabled and the clocks are stable.
4579                  *
4580                  * So write it again.
4581                  */
4582                 I915_WRITE(DPLL(pipe), dpll);
4583         }
4584 }
4585
4586 static void i8xx_update_pll(struct drm_crtc *crtc,
4587                             struct drm_display_mode *adjusted_mode,
4588                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4589                             int num_connectors)
4590 {
4591         struct drm_device *dev = crtc->dev;
4592         struct drm_i915_private *dev_priv = dev->dev_private;
4593         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4594         int pipe = intel_crtc->pipe;
4595         u32 dpll;
4596
4597         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4598
4599         dpll = DPLL_VGA_MODE_DIS;
4600
4601         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4602                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4603         } else {
4604                 if (clock->p1 == 2)
4605                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4606                 else
4607                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4608                 if (clock->p2 == 4)
4609                         dpll |= PLL_P2_DIVIDE_BY_4;
4610         }
4611
4612         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4613                 /* XXX: just matching BIOS for now */
4614                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4615                 dpll |= 3;
4616         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4617                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4618                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4619         else
4620                 dpll |= PLL_REF_INPUT_DREFCLK;
4621
4622         dpll |= DPLL_VCO_ENABLE;
4623         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4624         POSTING_READ(DPLL(pipe));
4625         udelay(150);
4626
4627         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4628          * This is an exception to the general rule that mode_set doesn't turn
4629          * things on.
4630          */
4631         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4632                 intel_update_lvds(crtc, clock, adjusted_mode);
4633
4634         I915_WRITE(DPLL(pipe), dpll);
4635
4636         /* Wait for the clocks to stabilize. */
4637         POSTING_READ(DPLL(pipe));
4638         udelay(150);
4639
4640         /* The pixel multiplier can only be updated once the
4641          * DPLL is enabled and the clocks are stable.
4642          *
4643          * So write it again.
4644          */
4645         I915_WRITE(DPLL(pipe), dpll);
4646 }
4647
4648 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4649                                    struct drm_display_mode *mode,
4650                                    struct drm_display_mode *adjusted_mode)
4651 {
4652         struct drm_device *dev = intel_crtc->base.dev;
4653         struct drm_i915_private *dev_priv = dev->dev_private;
4654         enum pipe pipe = intel_crtc->pipe;
4655         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4656         uint32_t vsyncshift;
4657
4658         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4659                 /* the chip adds 2 halflines automatically */
4660                 adjusted_mode->crtc_vtotal -= 1;
4661                 adjusted_mode->crtc_vblank_end -= 1;
4662                 vsyncshift = adjusted_mode->crtc_hsync_start
4663                              - adjusted_mode->crtc_htotal / 2;
4664         } else {
4665                 vsyncshift = 0;
4666         }
4667
4668         if (INTEL_INFO(dev)->gen > 3)
4669                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4670
4671         I915_WRITE(HTOTAL(cpu_transcoder),
4672                    (adjusted_mode->crtc_hdisplay - 1) |
4673                    ((adjusted_mode->crtc_htotal - 1) << 16));
4674         I915_WRITE(HBLANK(cpu_transcoder),
4675                    (adjusted_mode->crtc_hblank_start - 1) |
4676                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4677         I915_WRITE(HSYNC(cpu_transcoder),
4678                    (adjusted_mode->crtc_hsync_start - 1) |
4679                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4680
4681         I915_WRITE(VTOTAL(cpu_transcoder),
4682                    (adjusted_mode->crtc_vdisplay - 1) |
4683                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4684         I915_WRITE(VBLANK(cpu_transcoder),
4685                    (adjusted_mode->crtc_vblank_start - 1) |
4686                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4687         I915_WRITE(VSYNC(cpu_transcoder),
4688                    (adjusted_mode->crtc_vsync_start - 1) |
4689                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4690
4691         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4692          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4693          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4694          * bits. */
4695         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4696             (pipe == PIPE_B || pipe == PIPE_C))
4697                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4698
4699         /* pipesrc controls the size that is scaled from, which should
4700          * always be the user's requested size.
4701          */
4702         I915_WRITE(PIPESRC(pipe),
4703                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4704 }
4705
4706 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4707                               struct drm_display_mode *mode,
4708                               struct drm_display_mode *adjusted_mode,
4709                               int x, int y,
4710                               struct drm_framebuffer *fb)
4711 {
4712         struct drm_device *dev = crtc->dev;
4713         struct drm_i915_private *dev_priv = dev->dev_private;
4714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4715         int pipe = intel_crtc->pipe;
4716         int plane = intel_crtc->plane;
4717         int refclk, num_connectors = 0;
4718         intel_clock_t clock, reduced_clock;
4719         u32 dspcntr, pipeconf;
4720         bool ok, has_reduced_clock = false, is_sdvo = false;
4721         bool is_lvds = false, is_tv = false, is_dp = false;
4722         struct intel_encoder *encoder;
4723         const intel_limit_t *limit;
4724         int ret;
4725
4726         for_each_encoder_on_crtc(dev, crtc, encoder) {
4727                 switch (encoder->type) {
4728                 case INTEL_OUTPUT_LVDS:
4729                         is_lvds = true;
4730                         break;
4731                 case INTEL_OUTPUT_SDVO:
4732                 case INTEL_OUTPUT_HDMI:
4733                         is_sdvo = true;
4734                         if (encoder->needs_tv_clock)
4735                                 is_tv = true;
4736                         break;
4737                 case INTEL_OUTPUT_TVOUT:
4738                         is_tv = true;
4739                         break;
4740                 case INTEL_OUTPUT_DISPLAYPORT:
4741                         is_dp = true;
4742                         break;
4743                 }
4744
4745                 num_connectors++;
4746         }
4747
4748         refclk = i9xx_get_refclk(crtc, num_connectors);
4749
4750         /*
4751          * Returns a set of divisors for the desired target clock with the given
4752          * refclk, or FALSE.  The returned values represent the clock equation:
4753          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4754          */
4755         limit = intel_limit(crtc, refclk);
4756         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4757                              &clock);
4758         if (!ok) {
4759                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4760                 return -EINVAL;
4761         }
4762
4763         /* Ensure that the cursor is valid for the new mode before changing... */
4764         intel_crtc_update_cursor(crtc, true);
4765
4766         if (is_lvds && dev_priv->lvds_downclock_avail) {
4767                 /*
4768                  * Ensure we match the reduced clock's P to the target clock.
4769                  * If the clocks don't match, we can't switch the display clock
4770                  * by using the FP0/FP1. In such case we will disable the LVDS
4771                  * downclock feature.
4772                 */
4773                 has_reduced_clock = limit->find_pll(limit, crtc,
4774                                                     dev_priv->lvds_downclock,
4775                                                     refclk,
4776                                                     &clock,
4777                                                     &reduced_clock);
4778         }
4779
4780         if (is_sdvo && is_tv)
4781                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4782
4783         if (IS_GEN2(dev))
4784                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4785                                 has_reduced_clock ? &reduced_clock : NULL,
4786                                 num_connectors);
4787         else if (IS_VALLEYVIEW(dev))
4788                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4789                                 has_reduced_clock ? &reduced_clock : NULL,
4790                                 num_connectors);
4791         else
4792                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4793                                 has_reduced_clock ? &reduced_clock : NULL,
4794                                 num_connectors);
4795
4796         /* setup pipeconf */
4797         pipeconf = I915_READ(PIPECONF(pipe));
4798
4799         /* Set up the display plane register */
4800         dspcntr = DISPPLANE_GAMMA_ENABLE;
4801
4802         if (pipe == 0)
4803                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4804         else
4805                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4806
4807         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4808                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4809                  * core speed.
4810                  *
4811                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4812                  * pipe == 0 check?
4813                  */
4814                 if (mode->clock >
4815                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4816                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4817                 else
4818                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4819         }
4820
4821         /* default to 8bpc */
4822         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4823         if (is_dp) {
4824                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4825                         pipeconf |= PIPECONF_BPP_6 |
4826                                     PIPECONF_DITHER_EN |
4827                                     PIPECONF_DITHER_TYPE_SP;
4828                 }
4829         }
4830
4831         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4832                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4833                         pipeconf |= PIPECONF_BPP_6 |
4834                                         PIPECONF_ENABLE |
4835                                         I965_PIPECONF_ACTIVE;
4836                 }
4837         }
4838
4839         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4840         drm_mode_debug_printmodeline(mode);
4841
4842         if (HAS_PIPE_CXSR(dev)) {
4843                 if (intel_crtc->lowfreq_avail) {
4844                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4845                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4846                 } else {
4847                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4848                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4849                 }
4850         }
4851
4852         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4853         if (!IS_GEN2(dev) &&
4854             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4855                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4856         else
4857                 pipeconf |= PIPECONF_PROGRESSIVE;
4858
4859         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4860
4861         /* pipesrc and dspsize control the size that is scaled from,
4862          * which should always be the user's requested size.
4863          */
4864         I915_WRITE(DSPSIZE(plane),
4865                    ((mode->vdisplay - 1) << 16) |
4866                    (mode->hdisplay - 1));
4867         I915_WRITE(DSPPOS(plane), 0);
4868
4869         I915_WRITE(PIPECONF(pipe), pipeconf);
4870         POSTING_READ(PIPECONF(pipe));
4871         intel_enable_pipe(dev_priv, pipe, false);
4872
4873         intel_wait_for_vblank(dev, pipe);
4874
4875         I915_WRITE(DSPCNTR(plane), dspcntr);
4876         POSTING_READ(DSPCNTR(plane));
4877
4878         ret = intel_pipe_set_base(crtc, x, y, fb);
4879
4880         intel_update_watermarks(dev);
4881
4882         return ret;
4883 }
4884
4885 /*
4886  * Initialize reference clocks when the driver loads
4887  */
4888 void ironlake_init_pch_refclk(struct drm_device *dev)
4889 {
4890         struct drm_i915_private *dev_priv = dev->dev_private;
4891         struct drm_mode_config *mode_config = &dev->mode_config;
4892         struct intel_encoder *encoder;
4893         u32 temp;
4894         bool has_lvds = false;
4895         bool has_cpu_edp = false;
4896         bool has_pch_edp = false;
4897         bool has_panel = false;
4898         bool has_ck505 = false;
4899         bool can_ssc = false;
4900
4901         /* We need to take the global config into account */
4902         list_for_each_entry(encoder, &mode_config->encoder_list,
4903                             base.head) {
4904                 switch (encoder->type) {
4905                 case INTEL_OUTPUT_LVDS:
4906                         has_panel = true;
4907                         has_lvds = true;
4908                         break;
4909                 case INTEL_OUTPUT_EDP:
4910                         has_panel = true;
4911                         if (intel_encoder_is_pch_edp(&encoder->base))
4912                                 has_pch_edp = true;
4913                         else
4914                                 has_cpu_edp = true;
4915                         break;
4916                 }
4917         }
4918
4919         if (HAS_PCH_IBX(dev)) {
4920                 has_ck505 = dev_priv->display_clock_mode;
4921                 can_ssc = has_ck505;
4922         } else {
4923                 has_ck505 = false;
4924                 can_ssc = true;
4925         }
4926
4927         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4928                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4929                       has_ck505);
4930
4931         /* Ironlake: try to setup display ref clock before DPLL
4932          * enabling. This is only under driver's control after
4933          * PCH B stepping, previous chipset stepping should be
4934          * ignoring this setting.
4935          */
4936         temp = I915_READ(PCH_DREF_CONTROL);
4937         /* Always enable nonspread source */
4938         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4939
4940         if (has_ck505)
4941                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4942         else
4943                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4944
4945         if (has_panel) {
4946                 temp &= ~DREF_SSC_SOURCE_MASK;
4947                 temp |= DREF_SSC_SOURCE_ENABLE;
4948
4949                 /* SSC must be turned on before enabling the CPU output  */
4950                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4951                         DRM_DEBUG_KMS("Using SSC on panel\n");
4952                         temp |= DREF_SSC1_ENABLE;
4953                 } else
4954                         temp &= ~DREF_SSC1_ENABLE;
4955
4956                 /* Get SSC going before enabling the outputs */
4957                 I915_WRITE(PCH_DREF_CONTROL, temp);
4958                 POSTING_READ(PCH_DREF_CONTROL);
4959                 udelay(200);
4960
4961                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4962
4963                 /* Enable CPU source on CPU attached eDP */
4964                 if (has_cpu_edp) {
4965                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4966                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4967                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4968                         }
4969                         else
4970                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4971                 } else
4972                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4973
4974                 I915_WRITE(PCH_DREF_CONTROL, temp);
4975                 POSTING_READ(PCH_DREF_CONTROL);
4976                 udelay(200);
4977         } else {
4978                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4979
4980                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4981
4982                 /* Turn off CPU output */
4983                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4984
4985                 I915_WRITE(PCH_DREF_CONTROL, temp);
4986                 POSTING_READ(PCH_DREF_CONTROL);
4987                 udelay(200);
4988
4989                 /* Turn off the SSC source */
4990                 temp &= ~DREF_SSC_SOURCE_MASK;
4991                 temp |= DREF_SSC_SOURCE_DISABLE;
4992
4993                 /* Turn off SSC1 */
4994                 temp &= ~ DREF_SSC1_ENABLE;
4995
4996                 I915_WRITE(PCH_DREF_CONTROL, temp);
4997                 POSTING_READ(PCH_DREF_CONTROL);
4998                 udelay(200);
4999         }
5000 }
5001
5002 static int ironlake_get_refclk(struct drm_crtc *crtc)
5003 {
5004         struct drm_device *dev = crtc->dev;
5005         struct drm_i915_private *dev_priv = dev->dev_private;
5006         struct intel_encoder *encoder;
5007         struct intel_encoder *edp_encoder = NULL;
5008         int num_connectors = 0;
5009         bool is_lvds = false;
5010
5011         for_each_encoder_on_crtc(dev, crtc, encoder) {
5012                 switch (encoder->type) {
5013                 case INTEL_OUTPUT_LVDS:
5014                         is_lvds = true;
5015                         break;
5016                 case INTEL_OUTPUT_EDP:
5017                         edp_encoder = encoder;
5018                         break;
5019                 }
5020                 num_connectors++;
5021         }
5022
5023         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5024                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5025                               dev_priv->lvds_ssc_freq);
5026                 return dev_priv->lvds_ssc_freq * 1000;
5027         }
5028
5029         return 120000;
5030 }
5031
5032 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5033                                   struct drm_display_mode *adjusted_mode,
5034                                   bool dither)
5035 {
5036         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5038         int pipe = intel_crtc->pipe;
5039         uint32_t val;
5040
5041         val = I915_READ(PIPECONF(pipe));
5042
5043         val &= ~PIPE_BPC_MASK;
5044         switch (intel_crtc->bpp) {
5045         case 18:
5046                 val |= PIPE_6BPC;
5047                 break;
5048         case 24:
5049                 val |= PIPE_8BPC;
5050                 break;
5051         case 30:
5052                 val |= PIPE_10BPC;
5053                 break;
5054         case 36:
5055                 val |= PIPE_12BPC;
5056                 break;
5057         default:
5058                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5059                 BUG();
5060         }
5061
5062         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5063         if (dither)
5064                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5065
5066         val &= ~PIPECONF_INTERLACE_MASK;
5067         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5068                 val |= PIPECONF_INTERLACED_ILK;
5069         else
5070                 val |= PIPECONF_PROGRESSIVE;
5071
5072         I915_WRITE(PIPECONF(pipe), val);
5073         POSTING_READ(PIPECONF(pipe));
5074 }
5075
5076 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5077                                  struct drm_display_mode *adjusted_mode,
5078                                  bool dither)
5079 {
5080         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5082         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5083         uint32_t val;
5084
5085         val = I915_READ(PIPECONF(cpu_transcoder));
5086
5087         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5088         if (dither)
5089                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5090
5091         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5092         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5093                 val |= PIPECONF_INTERLACED_ILK;
5094         else
5095                 val |= PIPECONF_PROGRESSIVE;
5096
5097         I915_WRITE(PIPECONF(cpu_transcoder), val);
5098         POSTING_READ(PIPECONF(cpu_transcoder));
5099 }
5100
5101 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5102                                     struct drm_display_mode *adjusted_mode,
5103                                     intel_clock_t *clock,
5104                                     bool *has_reduced_clock,
5105                                     intel_clock_t *reduced_clock)
5106 {
5107         struct drm_device *dev = crtc->dev;
5108         struct drm_i915_private *dev_priv = dev->dev_private;
5109         struct intel_encoder *intel_encoder;
5110         int refclk;
5111         const intel_limit_t *limit;
5112         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5113
5114         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5115                 switch (intel_encoder->type) {
5116                 case INTEL_OUTPUT_LVDS:
5117                         is_lvds = true;
5118                         break;
5119                 case INTEL_OUTPUT_SDVO:
5120                 case INTEL_OUTPUT_HDMI:
5121                         is_sdvo = true;
5122                         if (intel_encoder->needs_tv_clock)
5123                                 is_tv = true;
5124                         break;
5125                 case INTEL_OUTPUT_TVOUT:
5126                         is_tv = true;
5127                         break;
5128                 }
5129         }
5130
5131         refclk = ironlake_get_refclk(crtc);
5132
5133         /*
5134          * Returns a set of divisors for the desired target clock with the given
5135          * refclk, or FALSE.  The returned values represent the clock equation:
5136          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5137          */
5138         limit = intel_limit(crtc, refclk);
5139         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5140                               clock);
5141         if (!ret)
5142                 return false;
5143
5144         if (is_lvds && dev_priv->lvds_downclock_avail) {
5145                 /*
5146                  * Ensure we match the reduced clock's P to the target clock.
5147                  * If the clocks don't match, we can't switch the display clock
5148                  * by using the FP0/FP1. In such case we will disable the LVDS
5149                  * downclock feature.
5150                 */
5151                 *has_reduced_clock = limit->find_pll(limit, crtc,
5152                                                      dev_priv->lvds_downclock,
5153                                                      refclk,
5154                                                      clock,
5155                                                      reduced_clock);
5156         }
5157
5158         if (is_sdvo && is_tv)
5159                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5160
5161         return true;
5162 }
5163
5164 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5165 {
5166         struct drm_i915_private *dev_priv = dev->dev_private;
5167         uint32_t temp;
5168
5169         temp = I915_READ(SOUTH_CHICKEN1);
5170         if (temp & FDI_BC_BIFURCATION_SELECT)
5171                 return;
5172
5173         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5174         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5175
5176         temp |= FDI_BC_BIFURCATION_SELECT;
5177         DRM_DEBUG_KMS("enabling fdi C rx\n");
5178         I915_WRITE(SOUTH_CHICKEN1, temp);
5179         POSTING_READ(SOUTH_CHICKEN1);
5180 }
5181
5182 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5183 {
5184         struct drm_device *dev = intel_crtc->base.dev;
5185         struct drm_i915_private *dev_priv = dev->dev_private;
5186         struct intel_crtc *pipe_B_crtc =
5187                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5188
5189         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5190                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5191         if (intel_crtc->fdi_lanes > 4) {
5192                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5193                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5194                 /* Clamp lanes to avoid programming the hw with bogus values. */
5195                 intel_crtc->fdi_lanes = 4;
5196
5197                 return false;
5198         }
5199
5200         if (dev_priv->num_pipe == 2)
5201                 return true;
5202
5203         switch (intel_crtc->pipe) {
5204         case PIPE_A:
5205                 return true;
5206         case PIPE_B:
5207                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5208                     intel_crtc->fdi_lanes > 2) {
5209                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5210                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5211                         /* Clamp lanes to avoid programming the hw with bogus values. */
5212                         intel_crtc->fdi_lanes = 2;
5213
5214                         return false;
5215                 }
5216
5217                 if (intel_crtc->fdi_lanes > 2)
5218                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5219                 else
5220                         cpt_enable_fdi_bc_bifurcation(dev);
5221
5222                 return true;
5223         case PIPE_C:
5224                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5225                         if (intel_crtc->fdi_lanes > 2) {
5226                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5227                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5228                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5229                                 intel_crtc->fdi_lanes = 2;
5230
5231                                 return false;
5232                         }
5233                 } else {
5234                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5235                         return false;
5236                 }
5237
5238                 cpt_enable_fdi_bc_bifurcation(dev);
5239
5240                 return true;
5241         default:
5242                 BUG();
5243         }
5244 }
5245
5246 static void ironlake_set_m_n(struct drm_crtc *crtc,
5247                              struct drm_display_mode *mode,
5248                              struct drm_display_mode *adjusted_mode)
5249 {
5250         struct drm_device *dev = crtc->dev;
5251         struct drm_i915_private *dev_priv = dev->dev_private;
5252         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5253         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5254         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5255         struct fdi_m_n m_n = {0};
5256         int target_clock, pixel_multiplier, lane, link_bw;
5257         bool is_dp = false, is_cpu_edp = false;
5258
5259         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5260                 switch (intel_encoder->type) {
5261                 case INTEL_OUTPUT_DISPLAYPORT:
5262                         is_dp = true;
5263                         break;
5264                 case INTEL_OUTPUT_EDP:
5265                         is_dp = true;
5266                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5267                                 is_cpu_edp = true;
5268                         edp_encoder = intel_encoder;
5269                         break;
5270                 }
5271         }
5272
5273         /* FDI link */
5274         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5275         lane = 0;
5276         /* CPU eDP doesn't require FDI link, so just set DP M/N
5277            according to current link config */
5278         if (is_cpu_edp) {
5279                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5280         } else {
5281                 /* FDI is a binary signal running at ~2.7GHz, encoding
5282                  * each output octet as 10 bits. The actual frequency
5283                  * is stored as a divider into a 100MHz clock, and the
5284                  * mode pixel clock is stored in units of 1KHz.
5285                  * Hence the bw of each lane in terms of the mode signal
5286                  * is:
5287                  */
5288                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5289         }
5290
5291         /* [e]DP over FDI requires target mode clock instead of link clock. */
5292         if (edp_encoder)
5293                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5294         else if (is_dp)
5295                 target_clock = mode->clock;
5296         else
5297                 target_clock = adjusted_mode->clock;
5298
5299         if (!lane) {
5300                 /*
5301                  * Account for spread spectrum to avoid
5302                  * oversubscribing the link. Max center spread
5303                  * is 2.5%; use 5% for safety's sake.
5304                  */
5305                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5306                 lane = bps / (link_bw * 8) + 1;
5307         }
5308
5309         intel_crtc->fdi_lanes = lane;
5310
5311         if (pixel_multiplier > 1)
5312                 link_bw *= pixel_multiplier;
5313         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5314                              &m_n);
5315
5316         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5317         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5318         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5319         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5320 }
5321
5322 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5323                                       struct drm_display_mode *adjusted_mode,
5324                                       intel_clock_t *clock, u32 fp)
5325 {
5326         struct drm_crtc *crtc = &intel_crtc->base;
5327         struct drm_device *dev = crtc->dev;
5328         struct drm_i915_private *dev_priv = dev->dev_private;
5329         struct intel_encoder *intel_encoder;
5330         uint32_t dpll;
5331         int factor, pixel_multiplier, num_connectors = 0;
5332         bool is_lvds = false, is_sdvo = false, is_tv = false;
5333         bool is_dp = false, is_cpu_edp = false;
5334
5335         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5336                 switch (intel_encoder->type) {
5337                 case INTEL_OUTPUT_LVDS:
5338                         is_lvds = true;
5339                         break;
5340                 case INTEL_OUTPUT_SDVO:
5341                 case INTEL_OUTPUT_HDMI:
5342                         is_sdvo = true;
5343                         if (intel_encoder->needs_tv_clock)
5344                                 is_tv = true;
5345                         break;
5346                 case INTEL_OUTPUT_TVOUT:
5347                         is_tv = true;
5348                         break;
5349                 case INTEL_OUTPUT_DISPLAYPORT:
5350                         is_dp = true;
5351                         break;
5352                 case INTEL_OUTPUT_EDP:
5353                         is_dp = true;
5354                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5355                                 is_cpu_edp = true;
5356                         break;
5357                 }
5358
5359                 num_connectors++;
5360         }
5361
5362         /* Enable autotuning of the PLL clock (if permissible) */
5363         factor = 21;
5364         if (is_lvds) {
5365                 if ((intel_panel_use_ssc(dev_priv) &&
5366                      dev_priv->lvds_ssc_freq == 100) ||
5367                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5368                         factor = 25;
5369         } else if (is_sdvo && is_tv)
5370                 factor = 20;
5371
5372         if (clock->m < factor * clock->n)
5373                 fp |= FP_CB_TUNE;
5374
5375         dpll = 0;
5376
5377         if (is_lvds)
5378                 dpll |= DPLLB_MODE_LVDS;
5379         else
5380                 dpll |= DPLLB_MODE_DAC_SERIAL;
5381         if (is_sdvo) {
5382                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5383                 if (pixel_multiplier > 1) {
5384                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5385                 }
5386                 dpll |= DPLL_DVO_HIGH_SPEED;
5387         }
5388         if (is_dp && !is_cpu_edp)
5389                 dpll |= DPLL_DVO_HIGH_SPEED;
5390
5391         /* compute bitmask from p1 value */
5392         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5393         /* also FPA1 */
5394         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5395
5396         switch (clock->p2) {
5397         case 5:
5398                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5399                 break;
5400         case 7:
5401                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5402                 break;
5403         case 10:
5404                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5405                 break;
5406         case 14:
5407                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5408                 break;
5409         }
5410
5411         if (is_sdvo && is_tv)
5412                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5413         else if (is_tv)
5414                 /* XXX: just matching BIOS for now */
5415                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5416                 dpll |= 3;
5417         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5418                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5419         else
5420                 dpll |= PLL_REF_INPUT_DREFCLK;
5421
5422         return dpll;
5423 }
5424
5425 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5426                                   struct drm_display_mode *mode,
5427                                   struct drm_display_mode *adjusted_mode,
5428                                   int x, int y,
5429                                   struct drm_framebuffer *fb)
5430 {
5431         struct drm_device *dev = crtc->dev;
5432         struct drm_i915_private *dev_priv = dev->dev_private;
5433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5434         int pipe = intel_crtc->pipe;
5435         int plane = intel_crtc->plane;
5436         int num_connectors = 0;
5437         intel_clock_t clock, reduced_clock;
5438         u32 dpll, fp = 0, fp2 = 0;
5439         bool ok, has_reduced_clock = false;
5440         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5441         struct intel_encoder *encoder;
5442         u32 temp;
5443         int ret;
5444         bool dither, fdi_config_ok;
5445
5446         for_each_encoder_on_crtc(dev, crtc, encoder) {
5447                 switch (encoder->type) {
5448                 case INTEL_OUTPUT_LVDS:
5449                         is_lvds = true;
5450                         break;
5451                 case INTEL_OUTPUT_DISPLAYPORT:
5452                         is_dp = true;
5453                         break;
5454                 case INTEL_OUTPUT_EDP:
5455                         is_dp = true;
5456                         if (!intel_encoder_is_pch_edp(&encoder->base))
5457                                 is_cpu_edp = true;
5458                         break;
5459                 }
5460
5461                 num_connectors++;
5462         }
5463
5464         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5465              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5466
5467         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5468                                      &has_reduced_clock, &reduced_clock);
5469         if (!ok) {
5470                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5471                 return -EINVAL;
5472         }
5473
5474         /* Ensure that the cursor is valid for the new mode before changing... */
5475         intel_crtc_update_cursor(crtc, true);
5476
5477         /* determine panel color depth */
5478         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5479                                               adjusted_mode);
5480         if (is_lvds && dev_priv->lvds_dither)
5481                 dither = true;
5482
5483         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5484         if (has_reduced_clock)
5485                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5486                         reduced_clock.m2;
5487
5488         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5489
5490         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5491         drm_mode_debug_printmodeline(mode);
5492
5493         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5494         if (!is_cpu_edp) {
5495                 struct intel_pch_pll *pll;
5496
5497                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5498                 if (pll == NULL) {
5499                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5500                                          pipe);
5501                         return -EINVAL;
5502                 }
5503         } else
5504                 intel_put_pch_pll(intel_crtc);
5505
5506         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5507          * This is an exception to the general rule that mode_set doesn't turn
5508          * things on.
5509          */
5510         if (is_lvds) {
5511                 temp = I915_READ(PCH_LVDS);
5512                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5513                 if (HAS_PCH_CPT(dev)) {
5514                         temp &= ~PORT_TRANS_SEL_MASK;
5515                         temp |= PORT_TRANS_SEL_CPT(pipe);
5516                 } else {
5517                         if (pipe == 1)
5518                                 temp |= LVDS_PIPEB_SELECT;
5519                         else
5520                                 temp &= ~LVDS_PIPEB_SELECT;
5521                 }
5522
5523                 /* set the corresponsding LVDS_BORDER bit */
5524                 temp |= dev_priv->lvds_border_bits;
5525                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5526                  * set the DPLLs for dual-channel mode or not.
5527                  */
5528                 if (clock.p2 == 7)
5529                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5530                 else
5531                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5532
5533                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5534                  * appropriately here, but we need to look more thoroughly into how
5535                  * panels behave in the two modes.
5536                  */
5537                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5538                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5539                         temp |= LVDS_HSYNC_POLARITY;
5540                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5541                         temp |= LVDS_VSYNC_POLARITY;
5542                 I915_WRITE(PCH_LVDS, temp);
5543         }
5544
5545         if (is_dp && !is_cpu_edp) {
5546                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5547         } else {
5548                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5549                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5550                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5551                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5552                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5553         }
5554
5555         if (intel_crtc->pch_pll) {
5556                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5557
5558                 /* Wait for the clocks to stabilize. */
5559                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5560                 udelay(150);
5561
5562                 /* The pixel multiplier can only be updated once the
5563                  * DPLL is enabled and the clocks are stable.
5564                  *
5565                  * So write it again.
5566                  */
5567                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5568         }
5569
5570         intel_crtc->lowfreq_avail = false;
5571         if (intel_crtc->pch_pll) {
5572                 if (is_lvds && has_reduced_clock && i915_powersave) {
5573                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5574                         intel_crtc->lowfreq_avail = true;
5575                 } else {
5576                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5577                 }
5578         }
5579
5580         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5581
5582         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5583          * ironlake_check_fdi_lanes. */
5584         ironlake_set_m_n(crtc, mode, adjusted_mode);
5585
5586         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5587
5588         if (is_cpu_edp)
5589                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5590
5591         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5592
5593         intel_wait_for_vblank(dev, pipe);
5594
5595         /* Set up the display plane register */
5596         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5597         POSTING_READ(DSPCNTR(plane));
5598
5599         ret = intel_pipe_set_base(crtc, x, y, fb);
5600
5601         intel_update_watermarks(dev);
5602
5603         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5604
5605         return fdi_config_ok ? ret : -EINVAL;
5606 }
5607
5608 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5609                                  struct drm_display_mode *mode,
5610                                  struct drm_display_mode *adjusted_mode,
5611                                  int x, int y,
5612                                  struct drm_framebuffer *fb)
5613 {
5614         struct drm_device *dev = crtc->dev;
5615         struct drm_i915_private *dev_priv = dev->dev_private;
5616         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5617         int pipe = intel_crtc->pipe;
5618         int plane = intel_crtc->plane;
5619         int num_connectors = 0;
5620         intel_clock_t clock, reduced_clock;
5621         u32 dpll = 0, fp = 0, fp2 = 0;
5622         bool ok, has_reduced_clock = false;
5623         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5624         struct intel_encoder *encoder;
5625         u32 temp;
5626         int ret;
5627         bool dither;
5628
5629         for_each_encoder_on_crtc(dev, crtc, encoder) {
5630                 switch (encoder->type) {
5631                 case INTEL_OUTPUT_LVDS:
5632                         is_lvds = true;
5633                         break;
5634                 case INTEL_OUTPUT_DISPLAYPORT:
5635                         is_dp = true;
5636                         break;
5637                 case INTEL_OUTPUT_EDP:
5638                         is_dp = true;
5639                         if (!intel_encoder_is_pch_edp(&encoder->base))
5640                                 is_cpu_edp = true;
5641                         break;
5642                 }
5643
5644                 num_connectors++;
5645         }
5646
5647         if (is_cpu_edp)
5648                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5649         else
5650                 intel_crtc->cpu_transcoder = pipe;
5651
5652         /* We are not sure yet this won't happen. */
5653         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5654              INTEL_PCH_TYPE(dev));
5655
5656         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5657              num_connectors, pipe_name(pipe));
5658
5659         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5660                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5661
5662         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5663
5664         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5665                 return -EINVAL;
5666
5667         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5668                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5669                                              &has_reduced_clock,
5670                                              &reduced_clock);
5671                 if (!ok) {
5672                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5673                         return -EINVAL;
5674                 }
5675         }
5676
5677         /* Ensure that the cursor is valid for the new mode before changing... */
5678         intel_crtc_update_cursor(crtc, true);
5679
5680         /* determine panel color depth */
5681         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5682                                               adjusted_mode);
5683         if (is_lvds && dev_priv->lvds_dither)
5684                 dither = true;
5685
5686         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5687         drm_mode_debug_printmodeline(mode);
5688
5689         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5690                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5691                 if (has_reduced_clock)
5692                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5693                               reduced_clock.m2;
5694
5695                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5696                                              fp);
5697
5698                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5699                  * own on pre-Haswell/LPT generation */
5700                 if (!is_cpu_edp) {
5701                         struct intel_pch_pll *pll;
5702
5703                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5704                         if (pll == NULL) {
5705                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5706                                                  pipe);
5707                                 return -EINVAL;
5708                         }
5709                 } else
5710                         intel_put_pch_pll(intel_crtc);
5711
5712                 /* The LVDS pin pair needs to be on before the DPLLs are
5713                  * enabled.  This is an exception to the general rule that
5714                  * mode_set doesn't turn things on.
5715                  */
5716                 if (is_lvds) {
5717                         temp = I915_READ(PCH_LVDS);
5718                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5719                         if (HAS_PCH_CPT(dev)) {
5720                                 temp &= ~PORT_TRANS_SEL_MASK;
5721                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5722                         } else {
5723                                 if (pipe == 1)
5724                                         temp |= LVDS_PIPEB_SELECT;
5725                                 else
5726                                         temp &= ~LVDS_PIPEB_SELECT;
5727                         }
5728
5729                         /* set the corresponsding LVDS_BORDER bit */
5730                         temp |= dev_priv->lvds_border_bits;
5731                         /* Set the B0-B3 data pairs corresponding to whether
5732                          * we're going to set the DPLLs for dual-channel mode or
5733                          * not.
5734                          */
5735                         if (clock.p2 == 7)
5736                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5737                         else
5738                                 temp &= ~(LVDS_B0B3_POWER_UP |
5739                                           LVDS_CLKB_POWER_UP);
5740
5741                         /* It would be nice to set 24 vs 18-bit mode
5742                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5743                          * look more thoroughly into how panels behave in the
5744                          * two modes.
5745                          */
5746                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5747                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5748                                 temp |= LVDS_HSYNC_POLARITY;
5749                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5750                                 temp |= LVDS_VSYNC_POLARITY;
5751                         I915_WRITE(PCH_LVDS, temp);
5752                 }
5753         }
5754
5755         if (is_dp && !is_cpu_edp) {
5756                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5757         } else {
5758                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5759                         /* For non-DP output, clear any trans DP clock recovery
5760                          * setting.*/
5761                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5762                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5763                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5764                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5765                 }
5766         }
5767
5768         intel_crtc->lowfreq_avail = false;
5769         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5770                 if (intel_crtc->pch_pll) {
5771                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5772
5773                         /* Wait for the clocks to stabilize. */
5774                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5775                         udelay(150);
5776
5777                         /* The pixel multiplier can only be updated once the
5778                          * DPLL is enabled and the clocks are stable.
5779                          *
5780                          * So write it again.
5781                          */
5782                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5783                 }
5784
5785                 if (intel_crtc->pch_pll) {
5786                         if (is_lvds && has_reduced_clock && i915_powersave) {
5787                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5788                                 intel_crtc->lowfreq_avail = true;
5789                         } else {
5790                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5791                         }
5792                 }
5793         }
5794
5795         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5796
5797         if (!is_dp || is_cpu_edp)
5798                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5799
5800         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5801                 if (is_cpu_edp)
5802                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5803
5804         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5805
5806         /* Set up the display plane register */
5807         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5808         POSTING_READ(DSPCNTR(plane));
5809
5810         ret = intel_pipe_set_base(crtc, x, y, fb);
5811
5812         intel_update_watermarks(dev);
5813
5814         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5815
5816         return ret;
5817 }
5818
5819 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5820                                struct drm_display_mode *mode,
5821                                struct drm_display_mode *adjusted_mode,
5822                                int x, int y,
5823                                struct drm_framebuffer *fb)
5824 {
5825         struct drm_device *dev = crtc->dev;
5826         struct drm_i915_private *dev_priv = dev->dev_private;
5827         struct drm_encoder_helper_funcs *encoder_funcs;
5828         struct intel_encoder *encoder;
5829         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5830         int pipe = intel_crtc->pipe;
5831         int ret;
5832
5833         drm_vblank_pre_modeset(dev, pipe);
5834
5835         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5836                                               x, y, fb);
5837         drm_vblank_post_modeset(dev, pipe);
5838
5839         if (ret != 0)
5840                 return ret;
5841
5842         for_each_encoder_on_crtc(dev, crtc, encoder) {
5843                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5844                         encoder->base.base.id,
5845                         drm_get_encoder_name(&encoder->base),
5846                         mode->base.id, mode->name);
5847                 encoder_funcs = encoder->base.helper_private;
5848                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5849         }
5850
5851         return 0;
5852 }
5853
5854 static bool intel_eld_uptodate(struct drm_connector *connector,
5855                                int reg_eldv, uint32_t bits_eldv,
5856                                int reg_elda, uint32_t bits_elda,
5857                                int reg_edid)
5858 {
5859         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5860         uint8_t *eld = connector->eld;
5861         uint32_t i;
5862
5863         i = I915_READ(reg_eldv);
5864         i &= bits_eldv;
5865
5866         if (!eld[0])
5867                 return !i;
5868
5869         if (!i)
5870                 return false;
5871
5872         i = I915_READ(reg_elda);
5873         i &= ~bits_elda;
5874         I915_WRITE(reg_elda, i);
5875
5876         for (i = 0; i < eld[2]; i++)
5877                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5878                         return false;
5879
5880         return true;
5881 }
5882
5883 static void g4x_write_eld(struct drm_connector *connector,
5884                           struct drm_crtc *crtc)
5885 {
5886         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5887         uint8_t *eld = connector->eld;
5888         uint32_t eldv;
5889         uint32_t len;
5890         uint32_t i;
5891
5892         i = I915_READ(G4X_AUD_VID_DID);
5893
5894         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5895                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5896         else
5897                 eldv = G4X_ELDV_DEVCTG;
5898
5899         if (intel_eld_uptodate(connector,
5900                                G4X_AUD_CNTL_ST, eldv,
5901                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5902                                G4X_HDMIW_HDMIEDID))
5903                 return;
5904
5905         i = I915_READ(G4X_AUD_CNTL_ST);
5906         i &= ~(eldv | G4X_ELD_ADDR);
5907         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5908         I915_WRITE(G4X_AUD_CNTL_ST, i);
5909
5910         if (!eld[0])
5911                 return;
5912
5913         len = min_t(uint8_t, eld[2], len);
5914         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5915         for (i = 0; i < len; i++)
5916                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5917
5918         i = I915_READ(G4X_AUD_CNTL_ST);
5919         i |= eldv;
5920         I915_WRITE(G4X_AUD_CNTL_ST, i);
5921 }
5922
5923 static void haswell_write_eld(struct drm_connector *connector,
5924                                      struct drm_crtc *crtc)
5925 {
5926         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5927         uint8_t *eld = connector->eld;
5928         struct drm_device *dev = crtc->dev;
5929         uint32_t eldv;
5930         uint32_t i;
5931         int len;
5932         int pipe = to_intel_crtc(crtc)->pipe;
5933         int tmp;
5934
5935         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5936         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5937         int aud_config = HSW_AUD_CFG(pipe);
5938         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5939
5940
5941         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5942
5943         /* Audio output enable */
5944         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5945         tmp = I915_READ(aud_cntrl_st2);
5946         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5947         I915_WRITE(aud_cntrl_st2, tmp);
5948
5949         /* Wait for 1 vertical blank */
5950         intel_wait_for_vblank(dev, pipe);
5951
5952         /* Set ELD valid state */
5953         tmp = I915_READ(aud_cntrl_st2);
5954         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5955         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5956         I915_WRITE(aud_cntrl_st2, tmp);
5957         tmp = I915_READ(aud_cntrl_st2);
5958         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5959
5960         /* Enable HDMI mode */
5961         tmp = I915_READ(aud_config);
5962         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5963         /* clear N_programing_enable and N_value_index */
5964         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5965         I915_WRITE(aud_config, tmp);
5966
5967         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5968
5969         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5970
5971         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5972                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5973                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5974                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5975         } else
5976                 I915_WRITE(aud_config, 0);
5977
5978         if (intel_eld_uptodate(connector,
5979                                aud_cntrl_st2, eldv,
5980                                aud_cntl_st, IBX_ELD_ADDRESS,
5981                                hdmiw_hdmiedid))
5982                 return;
5983
5984         i = I915_READ(aud_cntrl_st2);
5985         i &= ~eldv;
5986         I915_WRITE(aud_cntrl_st2, i);
5987
5988         if (!eld[0])
5989                 return;
5990
5991         i = I915_READ(aud_cntl_st);
5992         i &= ~IBX_ELD_ADDRESS;
5993         I915_WRITE(aud_cntl_st, i);
5994         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5995         DRM_DEBUG_DRIVER("port num:%d\n", i);
5996
5997         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5998         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5999         for (i = 0; i < len; i++)
6000                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6001
6002         i = I915_READ(aud_cntrl_st2);
6003         i |= eldv;
6004         I915_WRITE(aud_cntrl_st2, i);
6005
6006 }
6007
6008 static void ironlake_write_eld(struct drm_connector *connector,
6009                                      struct drm_crtc *crtc)
6010 {
6011         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6012         uint8_t *eld = connector->eld;
6013         uint32_t eldv;
6014         uint32_t i;
6015         int len;
6016         int hdmiw_hdmiedid;
6017         int aud_config;
6018         int aud_cntl_st;
6019         int aud_cntrl_st2;
6020         int pipe = to_intel_crtc(crtc)->pipe;
6021
6022         if (HAS_PCH_IBX(connector->dev)) {
6023                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6024                 aud_config = IBX_AUD_CFG(pipe);
6025                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6026                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6027         } else {
6028                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6029                 aud_config = CPT_AUD_CFG(pipe);
6030                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6031                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6032         }
6033
6034         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6035
6036         i = I915_READ(aud_cntl_st);
6037         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6038         if (!i) {
6039                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6040                 /* operate blindly on all ports */
6041                 eldv = IBX_ELD_VALIDB;
6042                 eldv |= IBX_ELD_VALIDB << 4;
6043                 eldv |= IBX_ELD_VALIDB << 8;
6044         } else {
6045                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6046                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6047         }
6048
6049         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6050                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6051                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6052                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6053         } else
6054                 I915_WRITE(aud_config, 0);
6055
6056         if (intel_eld_uptodate(connector,
6057                                aud_cntrl_st2, eldv,
6058                                aud_cntl_st, IBX_ELD_ADDRESS,
6059                                hdmiw_hdmiedid))
6060                 return;
6061
6062         i = I915_READ(aud_cntrl_st2);
6063         i &= ~eldv;
6064         I915_WRITE(aud_cntrl_st2, i);
6065
6066         if (!eld[0])
6067                 return;
6068
6069         i = I915_READ(aud_cntl_st);
6070         i &= ~IBX_ELD_ADDRESS;
6071         I915_WRITE(aud_cntl_st, i);
6072
6073         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6074         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6075         for (i = 0; i < len; i++)
6076                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6077
6078         i = I915_READ(aud_cntrl_st2);
6079         i |= eldv;
6080         I915_WRITE(aud_cntrl_st2, i);
6081 }
6082
6083 void intel_write_eld(struct drm_encoder *encoder,
6084                      struct drm_display_mode *mode)
6085 {
6086         struct drm_crtc *crtc = encoder->crtc;
6087         struct drm_connector *connector;
6088         struct drm_device *dev = encoder->dev;
6089         struct drm_i915_private *dev_priv = dev->dev_private;
6090
6091         connector = drm_select_eld(encoder, mode);
6092         if (!connector)
6093                 return;
6094
6095         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6096                          connector->base.id,
6097                          drm_get_connector_name(connector),
6098                          connector->encoder->base.id,
6099                          drm_get_encoder_name(connector->encoder));
6100
6101         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6102
6103         if (dev_priv->display.write_eld)
6104                 dev_priv->display.write_eld(connector, crtc);
6105 }
6106
6107 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6108 void intel_crtc_load_lut(struct drm_crtc *crtc)
6109 {
6110         struct drm_device *dev = crtc->dev;
6111         struct drm_i915_private *dev_priv = dev->dev_private;
6112         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6113         int palreg = PALETTE(intel_crtc->pipe);
6114         int i;
6115
6116         /* The clocks have to be on to load the palette. */
6117         if (!crtc->enabled || !intel_crtc->active)
6118                 return;
6119
6120         /* use legacy palette for Ironlake */
6121         if (HAS_PCH_SPLIT(dev))
6122                 palreg = LGC_PALETTE(intel_crtc->pipe);
6123
6124         for (i = 0; i < 256; i++) {
6125                 I915_WRITE(palreg + 4 * i,
6126                            (intel_crtc->lut_r[i] << 16) |
6127                            (intel_crtc->lut_g[i] << 8) |
6128                            intel_crtc->lut_b[i]);
6129         }
6130 }
6131
6132 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6133 {
6134         struct drm_device *dev = crtc->dev;
6135         struct drm_i915_private *dev_priv = dev->dev_private;
6136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6137         bool visible = base != 0;
6138         u32 cntl;
6139
6140         if (intel_crtc->cursor_visible == visible)
6141                 return;
6142
6143         cntl = I915_READ(_CURACNTR);
6144         if (visible) {
6145                 /* On these chipsets we can only modify the base whilst
6146                  * the cursor is disabled.
6147                  */
6148                 I915_WRITE(_CURABASE, base);
6149
6150                 cntl &= ~(CURSOR_FORMAT_MASK);
6151                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6152                 cntl |= CURSOR_ENABLE |
6153                         CURSOR_GAMMA_ENABLE |
6154                         CURSOR_FORMAT_ARGB;
6155         } else
6156                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6157         I915_WRITE(_CURACNTR, cntl);
6158
6159         intel_crtc->cursor_visible = visible;
6160 }
6161
6162 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6163 {
6164         struct drm_device *dev = crtc->dev;
6165         struct drm_i915_private *dev_priv = dev->dev_private;
6166         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6167         int pipe = intel_crtc->pipe;
6168         bool visible = base != 0;
6169
6170         if (intel_crtc->cursor_visible != visible) {
6171                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6172                 if (base) {
6173                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6174                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6175                         cntl |= pipe << 28; /* Connect to correct pipe */
6176                 } else {
6177                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6178                         cntl |= CURSOR_MODE_DISABLE;
6179                 }
6180                 I915_WRITE(CURCNTR(pipe), cntl);
6181
6182                 intel_crtc->cursor_visible = visible;
6183         }
6184         /* and commit changes on next vblank */
6185         I915_WRITE(CURBASE(pipe), base);
6186 }
6187
6188 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6189 {
6190         struct drm_device *dev = crtc->dev;
6191         struct drm_i915_private *dev_priv = dev->dev_private;
6192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6193         int pipe = intel_crtc->pipe;
6194         bool visible = base != 0;
6195
6196         if (intel_crtc->cursor_visible != visible) {
6197                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6198                 if (base) {
6199                         cntl &= ~CURSOR_MODE;
6200                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6201                 } else {
6202                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6203                         cntl |= CURSOR_MODE_DISABLE;
6204                 }
6205                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6206
6207                 intel_crtc->cursor_visible = visible;
6208         }
6209         /* and commit changes on next vblank */
6210         I915_WRITE(CURBASE_IVB(pipe), base);
6211 }
6212
6213 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6214 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6215                                      bool on)
6216 {
6217         struct drm_device *dev = crtc->dev;
6218         struct drm_i915_private *dev_priv = dev->dev_private;
6219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6220         int pipe = intel_crtc->pipe;
6221         int x = intel_crtc->cursor_x;
6222         int y = intel_crtc->cursor_y;
6223         u32 base, pos;
6224         bool visible;
6225
6226         pos = 0;
6227
6228         if (on && crtc->enabled && crtc->fb) {
6229                 base = intel_crtc->cursor_addr;
6230                 if (x > (int) crtc->fb->width)
6231                         base = 0;
6232
6233                 if (y > (int) crtc->fb->height)
6234                         base = 0;
6235         } else
6236                 base = 0;
6237
6238         if (x < 0) {
6239                 if (x + intel_crtc->cursor_width < 0)
6240                         base = 0;
6241
6242                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6243                 x = -x;
6244         }
6245         pos |= x << CURSOR_X_SHIFT;
6246
6247         if (y < 0) {
6248                 if (y + intel_crtc->cursor_height < 0)
6249                         base = 0;
6250
6251                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6252                 y = -y;
6253         }
6254         pos |= y << CURSOR_Y_SHIFT;
6255
6256         visible = base != 0;
6257         if (!visible && !intel_crtc->cursor_visible)
6258                 return;
6259
6260         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6261                 I915_WRITE(CURPOS_IVB(pipe), pos);
6262                 ivb_update_cursor(crtc, base);
6263         } else {
6264                 I915_WRITE(CURPOS(pipe), pos);
6265                 if (IS_845G(dev) || IS_I865G(dev))
6266                         i845_update_cursor(crtc, base);
6267                 else
6268                         i9xx_update_cursor(crtc, base);
6269         }
6270 }
6271
6272 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6273                                  struct drm_file *file,
6274                                  uint32_t handle,
6275                                  uint32_t width, uint32_t height)
6276 {
6277         struct drm_device *dev = crtc->dev;
6278         struct drm_i915_private *dev_priv = dev->dev_private;
6279         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6280         struct drm_i915_gem_object *obj;
6281         uint32_t addr;
6282         int ret;
6283
6284         /* if we want to turn off the cursor ignore width and height */
6285         if (!handle) {
6286                 DRM_DEBUG_KMS("cursor off\n");
6287                 addr = 0;
6288                 obj = NULL;
6289                 mutex_lock(&dev->struct_mutex);
6290                 goto finish;
6291         }
6292
6293         /* Currently we only support 64x64 cursors */
6294         if (width != 64 || height != 64) {
6295                 DRM_ERROR("we currently only support 64x64 cursors\n");
6296                 return -EINVAL;
6297         }
6298
6299         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6300         if (&obj->base == NULL)
6301                 return -ENOENT;
6302
6303         if (obj->base.size < width * height * 4) {
6304                 DRM_ERROR("buffer is to small\n");
6305                 ret = -ENOMEM;
6306                 goto fail;
6307         }
6308
6309         /* we only need to pin inside GTT if cursor is non-phy */
6310         mutex_lock(&dev->struct_mutex);
6311         if (!dev_priv->info->cursor_needs_physical) {
6312                 if (obj->tiling_mode) {
6313                         DRM_ERROR("cursor cannot be tiled\n");
6314                         ret = -EINVAL;
6315                         goto fail_locked;
6316                 }
6317
6318                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6319                 if (ret) {
6320                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6321                         goto fail_locked;
6322                 }
6323
6324                 ret = i915_gem_object_put_fence(obj);
6325                 if (ret) {
6326                         DRM_ERROR("failed to release fence for cursor");
6327                         goto fail_unpin;
6328                 }
6329
6330                 addr = obj->gtt_offset;
6331         } else {
6332                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6333                 ret = i915_gem_attach_phys_object(dev, obj,
6334                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6335                                                   align);
6336                 if (ret) {
6337                         DRM_ERROR("failed to attach phys object\n");
6338                         goto fail_locked;
6339                 }
6340                 addr = obj->phys_obj->handle->busaddr;
6341         }
6342
6343         if (IS_GEN2(dev))
6344                 I915_WRITE(CURSIZE, (height << 12) | width);
6345
6346  finish:
6347         if (intel_crtc->cursor_bo) {
6348                 if (dev_priv->info->cursor_needs_physical) {
6349                         if (intel_crtc->cursor_bo != obj)
6350                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6351                 } else
6352                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6353                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6354         }
6355
6356         mutex_unlock(&dev->struct_mutex);
6357
6358         intel_crtc->cursor_addr = addr;
6359         intel_crtc->cursor_bo = obj;
6360         intel_crtc->cursor_width = width;
6361         intel_crtc->cursor_height = height;
6362
6363         intel_crtc_update_cursor(crtc, true);
6364
6365         return 0;
6366 fail_unpin:
6367         i915_gem_object_unpin(obj);
6368 fail_locked:
6369         mutex_unlock(&dev->struct_mutex);
6370 fail:
6371         drm_gem_object_unreference_unlocked(&obj->base);
6372         return ret;
6373 }
6374
6375 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6376 {
6377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6378
6379         intel_crtc->cursor_x = x;
6380         intel_crtc->cursor_y = y;
6381
6382         intel_crtc_update_cursor(crtc, true);
6383
6384         return 0;
6385 }
6386
6387 /** Sets the color ramps on behalf of RandR */
6388 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6389                                  u16 blue, int regno)
6390 {
6391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6392
6393         intel_crtc->lut_r[regno] = red >> 8;
6394         intel_crtc->lut_g[regno] = green >> 8;
6395         intel_crtc->lut_b[regno] = blue >> 8;
6396 }
6397
6398 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6399                              u16 *blue, int regno)
6400 {
6401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6402
6403         *red = intel_crtc->lut_r[regno] << 8;
6404         *green = intel_crtc->lut_g[regno] << 8;
6405         *blue = intel_crtc->lut_b[regno] << 8;
6406 }
6407
6408 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6409                                  u16 *blue, uint32_t start, uint32_t size)
6410 {
6411         int end = (start + size > 256) ? 256 : start + size, i;
6412         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6413
6414         for (i = start; i < end; i++) {
6415                 intel_crtc->lut_r[i] = red[i] >> 8;
6416                 intel_crtc->lut_g[i] = green[i] >> 8;
6417                 intel_crtc->lut_b[i] = blue[i] >> 8;
6418         }
6419
6420         intel_crtc_load_lut(crtc);
6421 }
6422
6423 /**
6424  * Get a pipe with a simple mode set on it for doing load-based monitor
6425  * detection.
6426  *
6427  * It will be up to the load-detect code to adjust the pipe as appropriate for
6428  * its requirements.  The pipe will be connected to no other encoders.
6429  *
6430  * Currently this code will only succeed if there is a pipe with no encoders
6431  * configured for it.  In the future, it could choose to temporarily disable
6432  * some outputs to free up a pipe for its use.
6433  *
6434  * \return crtc, or NULL if no pipes are available.
6435  */
6436
6437 /* VESA 640x480x72Hz mode to set on the pipe */
6438 static struct drm_display_mode load_detect_mode = {
6439         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6440                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6441 };
6442
6443 static struct drm_framebuffer *
6444 intel_framebuffer_create(struct drm_device *dev,
6445                          struct drm_mode_fb_cmd2 *mode_cmd,
6446                          struct drm_i915_gem_object *obj)
6447 {
6448         struct intel_framebuffer *intel_fb;
6449         int ret;
6450
6451         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6452         if (!intel_fb) {
6453                 drm_gem_object_unreference_unlocked(&obj->base);
6454                 return ERR_PTR(-ENOMEM);
6455         }
6456
6457         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6458         if (ret) {
6459                 drm_gem_object_unreference_unlocked(&obj->base);
6460                 kfree(intel_fb);
6461                 return ERR_PTR(ret);
6462         }
6463
6464         return &intel_fb->base;
6465 }
6466
6467 static u32
6468 intel_framebuffer_pitch_for_width(int width, int bpp)
6469 {
6470         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6471         return ALIGN(pitch, 64);
6472 }
6473
6474 static u32
6475 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6476 {
6477         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6478         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6479 }
6480
6481 static struct drm_framebuffer *
6482 intel_framebuffer_create_for_mode(struct drm_device *dev,
6483                                   struct drm_display_mode *mode,
6484                                   int depth, int bpp)
6485 {
6486         struct drm_i915_gem_object *obj;
6487         struct drm_mode_fb_cmd2 mode_cmd;
6488
6489         obj = i915_gem_alloc_object(dev,
6490                                     intel_framebuffer_size_for_mode(mode, bpp));
6491         if (obj == NULL)
6492                 return ERR_PTR(-ENOMEM);
6493
6494         mode_cmd.width = mode->hdisplay;
6495         mode_cmd.height = mode->vdisplay;
6496         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6497                                                                 bpp);
6498         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6499
6500         return intel_framebuffer_create(dev, &mode_cmd, obj);
6501 }
6502
6503 static struct drm_framebuffer *
6504 mode_fits_in_fbdev(struct drm_device *dev,
6505                    struct drm_display_mode *mode)
6506 {
6507         struct drm_i915_private *dev_priv = dev->dev_private;
6508         struct drm_i915_gem_object *obj;
6509         struct drm_framebuffer *fb;
6510
6511         if (dev_priv->fbdev == NULL)
6512                 return NULL;
6513
6514         obj = dev_priv->fbdev->ifb.obj;
6515         if (obj == NULL)
6516                 return NULL;
6517
6518         fb = &dev_priv->fbdev->ifb.base;
6519         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6520                                                                fb->bits_per_pixel))
6521                 return NULL;
6522
6523         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6524                 return NULL;
6525
6526         return fb;
6527 }
6528
6529 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6530                                 struct drm_display_mode *mode,
6531                                 struct intel_load_detect_pipe *old)
6532 {
6533         struct intel_crtc *intel_crtc;
6534         struct intel_encoder *intel_encoder =
6535                 intel_attached_encoder(connector);
6536         struct drm_crtc *possible_crtc;
6537         struct drm_encoder *encoder = &intel_encoder->base;
6538         struct drm_crtc *crtc = NULL;
6539         struct drm_device *dev = encoder->dev;
6540         struct drm_framebuffer *fb;
6541         int i = -1;
6542
6543         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6544                       connector->base.id, drm_get_connector_name(connector),
6545                       encoder->base.id, drm_get_encoder_name(encoder));
6546
6547         /*
6548          * Algorithm gets a little messy:
6549          *
6550          *   - if the connector already has an assigned crtc, use it (but make
6551          *     sure it's on first)
6552          *
6553          *   - try to find the first unused crtc that can drive this connector,
6554          *     and use that if we find one
6555          */
6556
6557         /* See if we already have a CRTC for this connector */
6558         if (encoder->crtc) {
6559                 crtc = encoder->crtc;
6560
6561                 old->dpms_mode = connector->dpms;
6562                 old->load_detect_temp = false;
6563
6564                 /* Make sure the crtc and connector are running */
6565                 if (connector->dpms != DRM_MODE_DPMS_ON)
6566                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6567
6568                 return true;
6569         }
6570
6571         /* Find an unused one (if possible) */
6572         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6573                 i++;
6574                 if (!(encoder->possible_crtcs & (1 << i)))
6575                         continue;
6576                 if (!possible_crtc->enabled) {
6577                         crtc = possible_crtc;
6578                         break;
6579                 }
6580         }
6581
6582         /*
6583          * If we didn't find an unused CRTC, don't use any.
6584          */
6585         if (!crtc) {
6586                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6587                 return false;
6588         }
6589
6590         intel_encoder->new_crtc = to_intel_crtc(crtc);
6591         to_intel_connector(connector)->new_encoder = intel_encoder;
6592
6593         intel_crtc = to_intel_crtc(crtc);
6594         old->dpms_mode = connector->dpms;
6595         old->load_detect_temp = true;
6596         old->release_fb = NULL;
6597
6598         if (!mode)
6599                 mode = &load_detect_mode;
6600
6601         /* We need a framebuffer large enough to accommodate all accesses
6602          * that the plane may generate whilst we perform load detection.
6603          * We can not rely on the fbcon either being present (we get called
6604          * during its initialisation to detect all boot displays, or it may
6605          * not even exist) or that it is large enough to satisfy the
6606          * requested mode.
6607          */
6608         fb = mode_fits_in_fbdev(dev, mode);
6609         if (fb == NULL) {
6610                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6611                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6612                 old->release_fb = fb;
6613         } else
6614                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6615         if (IS_ERR(fb)) {
6616                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6617                 goto fail;
6618         }
6619
6620         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6621                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6622                 if (old->release_fb)
6623                         old->release_fb->funcs->destroy(old->release_fb);
6624                 goto fail;
6625         }
6626
6627         /* let the connector get through one full cycle before testing */
6628         intel_wait_for_vblank(dev, intel_crtc->pipe);
6629
6630         return true;
6631 fail:
6632         connector->encoder = NULL;
6633         encoder->crtc = NULL;
6634         return false;
6635 }
6636
6637 void intel_release_load_detect_pipe(struct drm_connector *connector,
6638                                     struct intel_load_detect_pipe *old)
6639 {
6640         struct intel_encoder *intel_encoder =
6641                 intel_attached_encoder(connector);
6642         struct drm_encoder *encoder = &intel_encoder->base;
6643
6644         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6645                       connector->base.id, drm_get_connector_name(connector),
6646                       encoder->base.id, drm_get_encoder_name(encoder));
6647
6648         if (old->load_detect_temp) {
6649                 struct drm_crtc *crtc = encoder->crtc;
6650
6651                 to_intel_connector(connector)->new_encoder = NULL;
6652                 intel_encoder->new_crtc = NULL;
6653                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6654
6655                 if (old->release_fb)
6656                         old->release_fb->funcs->destroy(old->release_fb);
6657
6658                 return;
6659         }
6660
6661         /* Switch crtc and encoder back off if necessary */
6662         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6663                 connector->funcs->dpms(connector, old->dpms_mode);
6664 }
6665
6666 /* Returns the clock of the currently programmed mode of the given pipe. */
6667 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6668 {
6669         struct drm_i915_private *dev_priv = dev->dev_private;
6670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6671         int pipe = intel_crtc->pipe;
6672         u32 dpll = I915_READ(DPLL(pipe));
6673         u32 fp;
6674         intel_clock_t clock;
6675
6676         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6677                 fp = I915_READ(FP0(pipe));
6678         else
6679                 fp = I915_READ(FP1(pipe));
6680
6681         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6682         if (IS_PINEVIEW(dev)) {
6683                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6684                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6685         } else {
6686                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6687                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6688         }
6689
6690         if (!IS_GEN2(dev)) {
6691                 if (IS_PINEVIEW(dev))
6692                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6693                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6694                 else
6695                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6696                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6697
6698                 switch (dpll & DPLL_MODE_MASK) {
6699                 case DPLLB_MODE_DAC_SERIAL:
6700                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6701                                 5 : 10;
6702                         break;
6703                 case DPLLB_MODE_LVDS:
6704                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6705                                 7 : 14;
6706                         break;
6707                 default:
6708                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6709                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6710                         return 0;
6711                 }
6712
6713                 /* XXX: Handle the 100Mhz refclk */
6714                 intel_clock(dev, 96000, &clock);
6715         } else {
6716                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6717
6718                 if (is_lvds) {
6719                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6720                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6721                         clock.p2 = 14;
6722
6723                         if ((dpll & PLL_REF_INPUT_MASK) ==
6724                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6725                                 /* XXX: might not be 66MHz */
6726                                 intel_clock(dev, 66000, &clock);
6727                         } else
6728                                 intel_clock(dev, 48000, &clock);
6729                 } else {
6730                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6731                                 clock.p1 = 2;
6732                         else {
6733                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6734                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6735                         }
6736                         if (dpll & PLL_P2_DIVIDE_BY_4)
6737                                 clock.p2 = 4;
6738                         else
6739                                 clock.p2 = 2;
6740
6741                         intel_clock(dev, 48000, &clock);
6742                 }
6743         }
6744
6745         /* XXX: It would be nice to validate the clocks, but we can't reuse
6746          * i830PllIsValid() because it relies on the xf86_config connector
6747          * configuration being accurate, which it isn't necessarily.
6748          */
6749
6750         return clock.dot;
6751 }
6752
6753 /** Returns the currently programmed mode of the given pipe. */
6754 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6755                                              struct drm_crtc *crtc)
6756 {
6757         struct drm_i915_private *dev_priv = dev->dev_private;
6758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6759         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6760         struct drm_display_mode *mode;
6761         int htot = I915_READ(HTOTAL(cpu_transcoder));
6762         int hsync = I915_READ(HSYNC(cpu_transcoder));
6763         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6764         int vsync = I915_READ(VSYNC(cpu_transcoder));
6765
6766         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6767         if (!mode)
6768                 return NULL;
6769
6770         mode->clock = intel_crtc_clock_get(dev, crtc);
6771         mode->hdisplay = (htot & 0xffff) + 1;
6772         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6773         mode->hsync_start = (hsync & 0xffff) + 1;
6774         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6775         mode->vdisplay = (vtot & 0xffff) + 1;
6776         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6777         mode->vsync_start = (vsync & 0xffff) + 1;
6778         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6779
6780         drm_mode_set_name(mode);
6781
6782         return mode;
6783 }
6784
6785 static void intel_increase_pllclock(struct drm_crtc *crtc)
6786 {
6787         struct drm_device *dev = crtc->dev;
6788         drm_i915_private_t *dev_priv = dev->dev_private;
6789         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6790         int pipe = intel_crtc->pipe;
6791         int dpll_reg = DPLL(pipe);
6792         int dpll;
6793
6794         if (HAS_PCH_SPLIT(dev))
6795                 return;
6796
6797         if (!dev_priv->lvds_downclock_avail)
6798                 return;
6799
6800         dpll = I915_READ(dpll_reg);
6801         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6802                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6803
6804                 assert_panel_unlocked(dev_priv, pipe);
6805
6806                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6807                 I915_WRITE(dpll_reg, dpll);
6808                 intel_wait_for_vblank(dev, pipe);
6809
6810                 dpll = I915_READ(dpll_reg);
6811                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6812                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6813         }
6814 }
6815
6816 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6817 {
6818         struct drm_device *dev = crtc->dev;
6819         drm_i915_private_t *dev_priv = dev->dev_private;
6820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6821
6822         if (HAS_PCH_SPLIT(dev))
6823                 return;
6824
6825         if (!dev_priv->lvds_downclock_avail)
6826                 return;
6827
6828         /*
6829          * Since this is called by a timer, we should never get here in
6830          * the manual case.
6831          */
6832         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6833                 int pipe = intel_crtc->pipe;
6834                 int dpll_reg = DPLL(pipe);
6835                 int dpll;
6836
6837                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6838
6839                 assert_panel_unlocked(dev_priv, pipe);
6840
6841                 dpll = I915_READ(dpll_reg);
6842                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6843                 I915_WRITE(dpll_reg, dpll);
6844                 intel_wait_for_vblank(dev, pipe);
6845                 dpll = I915_READ(dpll_reg);
6846                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6847                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6848         }
6849
6850 }
6851
6852 void intel_mark_busy(struct drm_device *dev)
6853 {
6854         i915_update_gfx_val(dev->dev_private);
6855 }
6856
6857 void intel_mark_idle(struct drm_device *dev)
6858 {
6859 }
6860
6861 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6862 {
6863         struct drm_device *dev = obj->base.dev;
6864         struct drm_crtc *crtc;
6865
6866         if (!i915_powersave)
6867                 return;
6868
6869         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6870                 if (!crtc->fb)
6871                         continue;
6872
6873                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6874                         intel_increase_pllclock(crtc);
6875         }
6876 }
6877
6878 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6879 {
6880         struct drm_device *dev = obj->base.dev;
6881         struct drm_crtc *crtc;
6882
6883         if (!i915_powersave)
6884                 return;
6885
6886         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6887                 if (!crtc->fb)
6888                         continue;
6889
6890                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6891                         intel_decrease_pllclock(crtc);
6892         }
6893 }
6894
6895 static void intel_crtc_destroy(struct drm_crtc *crtc)
6896 {
6897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6898         struct drm_device *dev = crtc->dev;
6899         struct intel_unpin_work *work;
6900         unsigned long flags;
6901
6902         spin_lock_irqsave(&dev->event_lock, flags);
6903         work = intel_crtc->unpin_work;
6904         intel_crtc->unpin_work = NULL;
6905         spin_unlock_irqrestore(&dev->event_lock, flags);
6906
6907         if (work) {
6908                 cancel_work_sync(&work->work);
6909                 kfree(work);
6910         }
6911
6912         drm_crtc_cleanup(crtc);
6913
6914         kfree(intel_crtc);
6915 }
6916
6917 static void intel_unpin_work_fn(struct work_struct *__work)
6918 {
6919         struct intel_unpin_work *work =
6920                 container_of(__work, struct intel_unpin_work, work);
6921
6922         mutex_lock(&work->dev->struct_mutex);
6923         intel_unpin_fb_obj(work->old_fb_obj);
6924         drm_gem_object_unreference(&work->pending_flip_obj->base);
6925         drm_gem_object_unreference(&work->old_fb_obj->base);
6926
6927         intel_update_fbc(work->dev);
6928         mutex_unlock(&work->dev->struct_mutex);
6929         kfree(work);
6930 }
6931
6932 static void do_intel_finish_page_flip(struct drm_device *dev,
6933                                       struct drm_crtc *crtc)
6934 {
6935         drm_i915_private_t *dev_priv = dev->dev_private;
6936         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6937         struct intel_unpin_work *work;
6938         struct drm_i915_gem_object *obj;
6939         struct drm_pending_vblank_event *e;
6940         struct timeval tvbl;
6941         unsigned long flags;
6942
6943         /* Ignore early vblank irqs */
6944         if (intel_crtc == NULL)
6945                 return;
6946
6947         spin_lock_irqsave(&dev->event_lock, flags);
6948         work = intel_crtc->unpin_work;
6949         if (work == NULL || !work->pending) {
6950                 spin_unlock_irqrestore(&dev->event_lock, flags);
6951                 return;
6952         }
6953
6954         intel_crtc->unpin_work = NULL;
6955
6956         if (work->event) {
6957                 e = work->event;
6958                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6959
6960                 e->event.tv_sec = tvbl.tv_sec;
6961                 e->event.tv_usec = tvbl.tv_usec;
6962
6963                 list_add_tail(&e->base.link,
6964                               &e->base.file_priv->event_list);
6965                 wake_up_interruptible(&e->base.file_priv->event_wait);
6966         }
6967
6968         drm_vblank_put(dev, intel_crtc->pipe);
6969
6970         spin_unlock_irqrestore(&dev->event_lock, flags);
6971
6972         obj = work->old_fb_obj;
6973
6974         atomic_clear_mask(1 << intel_crtc->plane,
6975                           &obj->pending_flip.counter);
6976
6977         wake_up(&dev_priv->pending_flip_queue);
6978         schedule_work(&work->work);
6979
6980         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6981 }
6982
6983 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6984 {
6985         drm_i915_private_t *dev_priv = dev->dev_private;
6986         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6987
6988         do_intel_finish_page_flip(dev, crtc);
6989 }
6990
6991 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6992 {
6993         drm_i915_private_t *dev_priv = dev->dev_private;
6994         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6995
6996         do_intel_finish_page_flip(dev, crtc);
6997 }
6998
6999 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7000 {
7001         drm_i915_private_t *dev_priv = dev->dev_private;
7002         struct intel_crtc *intel_crtc =
7003                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7004         unsigned long flags;
7005
7006         spin_lock_irqsave(&dev->event_lock, flags);
7007         if (intel_crtc->unpin_work) {
7008                 if ((++intel_crtc->unpin_work->pending) > 1)
7009                         DRM_ERROR("Prepared flip multiple times\n");
7010         } else {
7011                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7012         }
7013         spin_unlock_irqrestore(&dev->event_lock, flags);
7014 }
7015
7016 static int intel_gen2_queue_flip(struct drm_device *dev,
7017                                  struct drm_crtc *crtc,
7018                                  struct drm_framebuffer *fb,
7019                                  struct drm_i915_gem_object *obj)
7020 {
7021         struct drm_i915_private *dev_priv = dev->dev_private;
7022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023         u32 flip_mask;
7024         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7025         int ret;
7026
7027         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7028         if (ret)
7029                 goto err;
7030
7031         ret = intel_ring_begin(ring, 6);
7032         if (ret)
7033                 goto err_unpin;
7034
7035         /* Can't queue multiple flips, so wait for the previous
7036          * one to finish before executing the next.
7037          */
7038         if (intel_crtc->plane)
7039                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7040         else
7041                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7042         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7043         intel_ring_emit(ring, MI_NOOP);
7044         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7045                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7046         intel_ring_emit(ring, fb->pitches[0]);
7047         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7048         intel_ring_emit(ring, 0); /* aux display base address, unused */
7049         intel_ring_advance(ring);
7050         return 0;
7051
7052 err_unpin:
7053         intel_unpin_fb_obj(obj);
7054 err:
7055         return ret;
7056 }
7057
7058 static int intel_gen3_queue_flip(struct drm_device *dev,
7059                                  struct drm_crtc *crtc,
7060                                  struct drm_framebuffer *fb,
7061                                  struct drm_i915_gem_object *obj)
7062 {
7063         struct drm_i915_private *dev_priv = dev->dev_private;
7064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7065         u32 flip_mask;
7066         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7067         int ret;
7068
7069         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7070         if (ret)
7071                 goto err;
7072
7073         ret = intel_ring_begin(ring, 6);
7074         if (ret)
7075                 goto err_unpin;
7076
7077         if (intel_crtc->plane)
7078                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7079         else
7080                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7081         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7082         intel_ring_emit(ring, MI_NOOP);
7083         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7084                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7085         intel_ring_emit(ring, fb->pitches[0]);
7086         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7087         intel_ring_emit(ring, MI_NOOP);
7088
7089         intel_ring_advance(ring);
7090         return 0;
7091
7092 err_unpin:
7093         intel_unpin_fb_obj(obj);
7094 err:
7095         return ret;
7096 }
7097
7098 static int intel_gen4_queue_flip(struct drm_device *dev,
7099                                  struct drm_crtc *crtc,
7100                                  struct drm_framebuffer *fb,
7101                                  struct drm_i915_gem_object *obj)
7102 {
7103         struct drm_i915_private *dev_priv = dev->dev_private;
7104         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7105         uint32_t pf, pipesrc;
7106         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7107         int ret;
7108
7109         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7110         if (ret)
7111                 goto err;
7112
7113         ret = intel_ring_begin(ring, 4);
7114         if (ret)
7115                 goto err_unpin;
7116
7117         /* i965+ uses the linear or tiled offsets from the
7118          * Display Registers (which do not change across a page-flip)
7119          * so we need only reprogram the base address.
7120          */
7121         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7122                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7123         intel_ring_emit(ring, fb->pitches[0]);
7124         intel_ring_emit(ring,
7125                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7126                         obj->tiling_mode);
7127
7128         /* XXX Enabling the panel-fitter across page-flip is so far
7129          * untested on non-native modes, so ignore it for now.
7130          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7131          */
7132         pf = 0;
7133         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7134         intel_ring_emit(ring, pf | pipesrc);
7135         intel_ring_advance(ring);
7136         return 0;
7137
7138 err_unpin:
7139         intel_unpin_fb_obj(obj);
7140 err:
7141         return ret;
7142 }
7143
7144 static int intel_gen6_queue_flip(struct drm_device *dev,
7145                                  struct drm_crtc *crtc,
7146                                  struct drm_framebuffer *fb,
7147                                  struct drm_i915_gem_object *obj)
7148 {
7149         struct drm_i915_private *dev_priv = dev->dev_private;
7150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7151         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7152         uint32_t pf, pipesrc;
7153         int ret;
7154
7155         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7156         if (ret)
7157                 goto err;
7158
7159         ret = intel_ring_begin(ring, 4);
7160         if (ret)
7161                 goto err_unpin;
7162
7163         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7164                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7165         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7166         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7167
7168         /* Contrary to the suggestions in the documentation,
7169          * "Enable Panel Fitter" does not seem to be required when page
7170          * flipping with a non-native mode, and worse causes a normal
7171          * modeset to fail.
7172          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7173          */
7174         pf = 0;
7175         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7176         intel_ring_emit(ring, pf | pipesrc);
7177         intel_ring_advance(ring);
7178         return 0;
7179
7180 err_unpin:
7181         intel_unpin_fb_obj(obj);
7182 err:
7183         return ret;
7184 }
7185
7186 /*
7187  * On gen7 we currently use the blit ring because (in early silicon at least)
7188  * the render ring doesn't give us interrpts for page flip completion, which
7189  * means clients will hang after the first flip is queued.  Fortunately the
7190  * blit ring generates interrupts properly, so use it instead.
7191  */
7192 static int intel_gen7_queue_flip(struct drm_device *dev,
7193                                  struct drm_crtc *crtc,
7194                                  struct drm_framebuffer *fb,
7195                                  struct drm_i915_gem_object *obj)
7196 {
7197         struct drm_i915_private *dev_priv = dev->dev_private;
7198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7199         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7200         uint32_t plane_bit = 0;
7201         int ret;
7202
7203         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7204         if (ret)
7205                 goto err;
7206
7207         switch(intel_crtc->plane) {
7208         case PLANE_A:
7209                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7210                 break;
7211         case PLANE_B:
7212                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7213                 break;
7214         case PLANE_C:
7215                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7216                 break;
7217         default:
7218                 WARN_ONCE(1, "unknown plane in flip command\n");
7219                 ret = -ENODEV;
7220                 goto err_unpin;
7221         }
7222
7223         ret = intel_ring_begin(ring, 4);
7224         if (ret)
7225                 goto err_unpin;
7226
7227         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7228         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7229         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7230         intel_ring_emit(ring, (MI_NOOP));
7231         intel_ring_advance(ring);
7232         return 0;
7233
7234 err_unpin:
7235         intel_unpin_fb_obj(obj);
7236 err:
7237         return ret;
7238 }
7239
7240 static int intel_default_queue_flip(struct drm_device *dev,
7241                                     struct drm_crtc *crtc,
7242                                     struct drm_framebuffer *fb,
7243                                     struct drm_i915_gem_object *obj)
7244 {
7245         return -ENODEV;
7246 }
7247
7248 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7249                                 struct drm_framebuffer *fb,
7250                                 struct drm_pending_vblank_event *event)
7251 {
7252         struct drm_device *dev = crtc->dev;
7253         struct drm_i915_private *dev_priv = dev->dev_private;
7254         struct intel_framebuffer *intel_fb;
7255         struct drm_i915_gem_object *obj;
7256         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7257         struct intel_unpin_work *work;
7258         unsigned long flags;
7259         int ret;
7260
7261         /* Can't change pixel format via MI display flips. */
7262         if (fb->pixel_format != crtc->fb->pixel_format)
7263                 return -EINVAL;
7264
7265         /*
7266          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7267          * Note that pitch changes could also affect these register.
7268          */
7269         if (INTEL_INFO(dev)->gen > 3 &&
7270             (fb->offsets[0] != crtc->fb->offsets[0] ||
7271              fb->pitches[0] != crtc->fb->pitches[0]))
7272                 return -EINVAL;
7273
7274         work = kzalloc(sizeof *work, GFP_KERNEL);
7275         if (work == NULL)
7276                 return -ENOMEM;
7277
7278         work->event = event;
7279         work->dev = crtc->dev;
7280         intel_fb = to_intel_framebuffer(crtc->fb);
7281         work->old_fb_obj = intel_fb->obj;
7282         INIT_WORK(&work->work, intel_unpin_work_fn);
7283
7284         ret = drm_vblank_get(dev, intel_crtc->pipe);
7285         if (ret)
7286                 goto free_work;
7287
7288         /* We borrow the event spin lock for protecting unpin_work */
7289         spin_lock_irqsave(&dev->event_lock, flags);
7290         if (intel_crtc->unpin_work) {
7291                 spin_unlock_irqrestore(&dev->event_lock, flags);
7292                 kfree(work);
7293                 drm_vblank_put(dev, intel_crtc->pipe);
7294
7295                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7296                 return -EBUSY;
7297         }
7298         intel_crtc->unpin_work = work;
7299         spin_unlock_irqrestore(&dev->event_lock, flags);
7300
7301         intel_fb = to_intel_framebuffer(fb);
7302         obj = intel_fb->obj;
7303
7304         ret = i915_mutex_lock_interruptible(dev);
7305         if (ret)
7306                 goto cleanup;
7307
7308         /* Reference the objects for the scheduled work. */
7309         drm_gem_object_reference(&work->old_fb_obj->base);
7310         drm_gem_object_reference(&obj->base);
7311
7312         crtc->fb = fb;
7313
7314         work->pending_flip_obj = obj;
7315
7316         work->enable_stall_check = true;
7317
7318         /* Block clients from rendering to the new back buffer until
7319          * the flip occurs and the object is no longer visible.
7320          */
7321         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7322
7323         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7324         if (ret)
7325                 goto cleanup_pending;
7326
7327         intel_disable_fbc(dev);
7328         intel_mark_fb_busy(obj);
7329         mutex_unlock(&dev->struct_mutex);
7330
7331         trace_i915_flip_request(intel_crtc->plane, obj);
7332
7333         return 0;
7334
7335 cleanup_pending:
7336         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7337         drm_gem_object_unreference(&work->old_fb_obj->base);
7338         drm_gem_object_unreference(&obj->base);
7339         mutex_unlock(&dev->struct_mutex);
7340
7341 cleanup:
7342         spin_lock_irqsave(&dev->event_lock, flags);
7343         intel_crtc->unpin_work = NULL;
7344         spin_unlock_irqrestore(&dev->event_lock, flags);
7345
7346         drm_vblank_put(dev, intel_crtc->pipe);
7347 free_work:
7348         kfree(work);
7349
7350         return ret;
7351 }
7352
7353 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7354         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7355         .load_lut = intel_crtc_load_lut,
7356         .disable = intel_crtc_noop,
7357 };
7358
7359 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7360 {
7361         struct intel_encoder *other_encoder;
7362         struct drm_crtc *crtc = &encoder->new_crtc->base;
7363
7364         if (WARN_ON(!crtc))
7365                 return false;
7366
7367         list_for_each_entry(other_encoder,
7368                             &crtc->dev->mode_config.encoder_list,
7369                             base.head) {
7370
7371                 if (&other_encoder->new_crtc->base != crtc ||
7372                     encoder == other_encoder)
7373                         continue;
7374                 else
7375                         return true;
7376         }
7377
7378         return false;
7379 }
7380
7381 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7382                                   struct drm_crtc *crtc)
7383 {
7384         struct drm_device *dev;
7385         struct drm_crtc *tmp;
7386         int crtc_mask = 1;
7387
7388         WARN(!crtc, "checking null crtc?\n");
7389
7390         dev = crtc->dev;
7391
7392         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7393                 if (tmp == crtc)
7394                         break;
7395                 crtc_mask <<= 1;
7396         }
7397
7398         if (encoder->possible_crtcs & crtc_mask)
7399                 return true;
7400         return false;
7401 }
7402
7403 /**
7404  * intel_modeset_update_staged_output_state
7405  *
7406  * Updates the staged output configuration state, e.g. after we've read out the
7407  * current hw state.
7408  */
7409 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7410 {
7411         struct intel_encoder *encoder;
7412         struct intel_connector *connector;
7413
7414         list_for_each_entry(connector, &dev->mode_config.connector_list,
7415                             base.head) {
7416                 connector->new_encoder =
7417                         to_intel_encoder(connector->base.encoder);
7418         }
7419
7420         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7421                             base.head) {
7422                 encoder->new_crtc =
7423                         to_intel_crtc(encoder->base.crtc);
7424         }
7425 }
7426
7427 /**
7428  * intel_modeset_commit_output_state
7429  *
7430  * This function copies the stage display pipe configuration to the real one.
7431  */
7432 static void intel_modeset_commit_output_state(struct drm_device *dev)
7433 {
7434         struct intel_encoder *encoder;
7435         struct intel_connector *connector;
7436
7437         list_for_each_entry(connector, &dev->mode_config.connector_list,
7438                             base.head) {
7439                 connector->base.encoder = &connector->new_encoder->base;
7440         }
7441
7442         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7443                             base.head) {
7444                 encoder->base.crtc = &encoder->new_crtc->base;
7445         }
7446 }
7447
7448 static struct drm_display_mode *
7449 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7450                             struct drm_display_mode *mode)
7451 {
7452         struct drm_device *dev = crtc->dev;
7453         struct drm_display_mode *adjusted_mode;
7454         struct drm_encoder_helper_funcs *encoder_funcs;
7455         struct intel_encoder *encoder;
7456
7457         adjusted_mode = drm_mode_duplicate(dev, mode);
7458         if (!adjusted_mode)
7459                 return ERR_PTR(-ENOMEM);
7460
7461         /* Pass our mode to the connectors and the CRTC to give them a chance to
7462          * adjust it according to limitations or connector properties, and also
7463          * a chance to reject the mode entirely.
7464          */
7465         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7466                             base.head) {
7467
7468                 if (&encoder->new_crtc->base != crtc)
7469                         continue;
7470                 encoder_funcs = encoder->base.helper_private;
7471                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7472                                                 adjusted_mode))) {
7473                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7474                         goto fail;
7475                 }
7476         }
7477
7478         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7479                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7480                 goto fail;
7481         }
7482         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7483
7484         return adjusted_mode;
7485 fail:
7486         drm_mode_destroy(dev, adjusted_mode);
7487         return ERR_PTR(-EINVAL);
7488 }
7489
7490 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7491  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7492 static void
7493 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7494                              unsigned *prepare_pipes, unsigned *disable_pipes)
7495 {
7496         struct intel_crtc *intel_crtc;
7497         struct drm_device *dev = crtc->dev;
7498         struct intel_encoder *encoder;
7499         struct intel_connector *connector;
7500         struct drm_crtc *tmp_crtc;
7501
7502         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7503
7504         /* Check which crtcs have changed outputs connected to them, these need
7505          * to be part of the prepare_pipes mask. We don't (yet) support global
7506          * modeset across multiple crtcs, so modeset_pipes will only have one
7507          * bit set at most. */
7508         list_for_each_entry(connector, &dev->mode_config.connector_list,
7509                             base.head) {
7510                 if (connector->base.encoder == &connector->new_encoder->base)
7511                         continue;
7512
7513                 if (connector->base.encoder) {
7514                         tmp_crtc = connector->base.encoder->crtc;
7515
7516                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7517                 }
7518
7519                 if (connector->new_encoder)
7520                         *prepare_pipes |=
7521                                 1 << connector->new_encoder->new_crtc->pipe;
7522         }
7523
7524         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7525                             base.head) {
7526                 if (encoder->base.crtc == &encoder->new_crtc->base)
7527                         continue;
7528
7529                 if (encoder->base.crtc) {
7530                         tmp_crtc = encoder->base.crtc;
7531
7532                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7533                 }
7534
7535                 if (encoder->new_crtc)
7536                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7537         }
7538
7539         /* Check for any pipes that will be fully disabled ... */
7540         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7541                             base.head) {
7542                 bool used = false;
7543
7544                 /* Don't try to disable disabled crtcs. */
7545                 if (!intel_crtc->base.enabled)
7546                         continue;
7547
7548                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7549                                     base.head) {
7550                         if (encoder->new_crtc == intel_crtc)
7551                                 used = true;
7552                 }
7553
7554                 if (!used)
7555                         *disable_pipes |= 1 << intel_crtc->pipe;
7556         }
7557
7558
7559         /* set_mode is also used to update properties on life display pipes. */
7560         intel_crtc = to_intel_crtc(crtc);
7561         if (crtc->enabled)
7562                 *prepare_pipes |= 1 << intel_crtc->pipe;
7563
7564         /* We only support modeset on one single crtc, hence we need to do that
7565          * only for the passed in crtc iff we change anything else than just
7566          * disable crtcs.
7567          *
7568          * This is actually not true, to be fully compatible with the old crtc
7569          * helper we automatically disable _any_ output (i.e. doesn't need to be
7570          * connected to the crtc we're modesetting on) if it's disconnected.
7571          * Which is a rather nutty api (since changed the output configuration
7572          * without userspace's explicit request can lead to confusion), but
7573          * alas. Hence we currently need to modeset on all pipes we prepare. */
7574         if (*prepare_pipes)
7575                 *modeset_pipes = *prepare_pipes;
7576
7577         /* ... and mask these out. */
7578         *modeset_pipes &= ~(*disable_pipes);
7579         *prepare_pipes &= ~(*disable_pipes);
7580 }
7581
7582 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7583 {
7584         struct drm_encoder *encoder;
7585         struct drm_device *dev = crtc->dev;
7586
7587         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7588                 if (encoder->crtc == crtc)
7589                         return true;
7590
7591         return false;
7592 }
7593
7594 static void
7595 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7596 {
7597         struct intel_encoder *intel_encoder;
7598         struct intel_crtc *intel_crtc;
7599         struct drm_connector *connector;
7600
7601         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7602                             base.head) {
7603                 if (!intel_encoder->base.crtc)
7604                         continue;
7605
7606                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7607
7608                 if (prepare_pipes & (1 << intel_crtc->pipe))
7609                         intel_encoder->connectors_active = false;
7610         }
7611
7612         intel_modeset_commit_output_state(dev);
7613
7614         /* Update computed state. */
7615         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7616                             base.head) {
7617                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7618         }
7619
7620         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7621                 if (!connector->encoder || !connector->encoder->crtc)
7622                         continue;
7623
7624                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7625
7626                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7627                         struct drm_property *dpms_property =
7628                                 dev->mode_config.dpms_property;
7629
7630                         connector->dpms = DRM_MODE_DPMS_ON;
7631                         drm_connector_property_set_value(connector,
7632                                                          dpms_property,
7633                                                          DRM_MODE_DPMS_ON);
7634
7635                         intel_encoder = to_intel_encoder(connector->encoder);
7636                         intel_encoder->connectors_active = true;
7637                 }
7638         }
7639
7640 }
7641
7642 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7643         list_for_each_entry((intel_crtc), \
7644                             &(dev)->mode_config.crtc_list, \
7645                             base.head) \
7646                 if (mask & (1 <<(intel_crtc)->pipe)) \
7647
7648 void
7649 intel_modeset_check_state(struct drm_device *dev)
7650 {
7651         struct intel_crtc *crtc;
7652         struct intel_encoder *encoder;
7653         struct intel_connector *connector;
7654
7655         list_for_each_entry(connector, &dev->mode_config.connector_list,
7656                             base.head) {
7657                 /* This also checks the encoder/connector hw state with the
7658                  * ->get_hw_state callbacks. */
7659                 intel_connector_check_state(connector);
7660
7661                 WARN(&connector->new_encoder->base != connector->base.encoder,
7662                      "connector's staged encoder doesn't match current encoder\n");
7663         }
7664
7665         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7666                             base.head) {
7667                 bool enabled = false;
7668                 bool active = false;
7669                 enum pipe pipe, tracked_pipe;
7670
7671                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7672                               encoder->base.base.id,
7673                               drm_get_encoder_name(&encoder->base));
7674
7675                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7676                      "encoder's stage crtc doesn't match current crtc\n");
7677                 WARN(encoder->connectors_active && !encoder->base.crtc,
7678                      "encoder's active_connectors set, but no crtc\n");
7679
7680                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7681                                     base.head) {
7682                         if (connector->base.encoder != &encoder->base)
7683                                 continue;
7684                         enabled = true;
7685                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7686                                 active = true;
7687                 }
7688                 WARN(!!encoder->base.crtc != enabled,
7689                      "encoder's enabled state mismatch "
7690                      "(expected %i, found %i)\n",
7691                      !!encoder->base.crtc, enabled);
7692                 WARN(active && !encoder->base.crtc,
7693                      "active encoder with no crtc\n");
7694
7695                 WARN(encoder->connectors_active != active,
7696                      "encoder's computed active state doesn't match tracked active state "
7697                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7698
7699                 active = encoder->get_hw_state(encoder, &pipe);
7700                 WARN(active != encoder->connectors_active,
7701                      "encoder's hw state doesn't match sw tracking "
7702                      "(expected %i, found %i)\n",
7703                      encoder->connectors_active, active);
7704
7705                 if (!encoder->base.crtc)
7706                         continue;
7707
7708                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7709                 WARN(active && pipe != tracked_pipe,
7710                      "active encoder's pipe doesn't match"
7711                      "(expected %i, found %i)\n",
7712                      tracked_pipe, pipe);
7713
7714         }
7715
7716         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7717                             base.head) {
7718                 bool enabled = false;
7719                 bool active = false;
7720
7721                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7722                               crtc->base.base.id);
7723
7724                 WARN(crtc->active && !crtc->base.enabled,
7725                      "active crtc, but not enabled in sw tracking\n");
7726
7727                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7728                                     base.head) {
7729                         if (encoder->base.crtc != &crtc->base)
7730                                 continue;
7731                         enabled = true;
7732                         if (encoder->connectors_active)
7733                                 active = true;
7734                 }
7735                 WARN(active != crtc->active,
7736                      "crtc's computed active state doesn't match tracked active state "
7737                      "(expected %i, found %i)\n", active, crtc->active);
7738                 WARN(enabled != crtc->base.enabled,
7739                      "crtc's computed enabled state doesn't match tracked enabled state "
7740                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7741
7742                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7743         }
7744 }
7745
7746 bool intel_set_mode(struct drm_crtc *crtc,
7747                     struct drm_display_mode *mode,
7748                     int x, int y, struct drm_framebuffer *fb)
7749 {
7750         struct drm_device *dev = crtc->dev;
7751         drm_i915_private_t *dev_priv = dev->dev_private;
7752         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7753         struct intel_crtc *intel_crtc;
7754         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7755         bool ret = true;
7756
7757         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7758                                      &prepare_pipes, &disable_pipes);
7759
7760         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7761                       modeset_pipes, prepare_pipes, disable_pipes);
7762
7763         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7764                 intel_crtc_disable(&intel_crtc->base);
7765
7766         saved_hwmode = crtc->hwmode;
7767         saved_mode = crtc->mode;
7768
7769         /* Hack: Because we don't (yet) support global modeset on multiple
7770          * crtcs, we don't keep track of the new mode for more than one crtc.
7771          * Hence simply check whether any bit is set in modeset_pipes in all the
7772          * pieces of code that are not yet converted to deal with mutliple crtcs
7773          * changing their mode at the same time. */
7774         adjusted_mode = NULL;
7775         if (modeset_pipes) {
7776                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7777                 if (IS_ERR(adjusted_mode)) {
7778                         return false;
7779                 }
7780         }
7781
7782         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7783                 if (intel_crtc->base.enabled)
7784                         dev_priv->display.crtc_disable(&intel_crtc->base);
7785         }
7786
7787         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7788          * to set it here already despite that we pass it down the callchain.
7789          */
7790         if (modeset_pipes)
7791                 crtc->mode = *mode;
7792
7793         /* Only after disabling all output pipelines that will be changed can we
7794          * update the the output configuration. */
7795         intel_modeset_update_state(dev, prepare_pipes);
7796
7797         if (dev_priv->display.modeset_global_resources)
7798                 dev_priv->display.modeset_global_resources(dev);
7799
7800         /* Set up the DPLL and any encoders state that needs to adjust or depend
7801          * on the DPLL.
7802          */
7803         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7804                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7805                                            mode, adjusted_mode,
7806                                            x, y, fb);
7807                 if (!ret)
7808                     goto done;
7809         }
7810
7811         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7812         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7813                 dev_priv->display.crtc_enable(&intel_crtc->base);
7814
7815         if (modeset_pipes) {
7816                 /* Store real post-adjustment hardware mode. */
7817                 crtc->hwmode = *adjusted_mode;
7818
7819                 /* Calculate and store various constants which
7820                  * are later needed by vblank and swap-completion
7821                  * timestamping. They are derived from true hwmode.
7822                  */
7823                 drm_calc_timestamping_constants(crtc);
7824         }
7825
7826         /* FIXME: add subpixel order */
7827 done:
7828         drm_mode_destroy(dev, adjusted_mode);
7829         if (!ret && crtc->enabled) {
7830                 crtc->hwmode = saved_hwmode;
7831                 crtc->mode = saved_mode;
7832         } else {
7833                 intel_modeset_check_state(dev);
7834         }
7835
7836         return ret;
7837 }
7838
7839 #undef for_each_intel_crtc_masked
7840
7841 static void intel_set_config_free(struct intel_set_config *config)
7842 {
7843         if (!config)
7844                 return;
7845
7846         kfree(config->save_connector_encoders);
7847         kfree(config->save_encoder_crtcs);
7848         kfree(config);
7849 }
7850
7851 static int intel_set_config_save_state(struct drm_device *dev,
7852                                        struct intel_set_config *config)
7853 {
7854         struct drm_encoder *encoder;
7855         struct drm_connector *connector;
7856         int count;
7857
7858         config->save_encoder_crtcs =
7859                 kcalloc(dev->mode_config.num_encoder,
7860                         sizeof(struct drm_crtc *), GFP_KERNEL);
7861         if (!config->save_encoder_crtcs)
7862                 return -ENOMEM;
7863
7864         config->save_connector_encoders =
7865                 kcalloc(dev->mode_config.num_connector,
7866                         sizeof(struct drm_encoder *), GFP_KERNEL);
7867         if (!config->save_connector_encoders)
7868                 return -ENOMEM;
7869
7870         /* Copy data. Note that driver private data is not affected.
7871          * Should anything bad happen only the expected state is
7872          * restored, not the drivers personal bookkeeping.
7873          */
7874         count = 0;
7875         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7876                 config->save_encoder_crtcs[count++] = encoder->crtc;
7877         }
7878
7879         count = 0;
7880         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7881                 config->save_connector_encoders[count++] = connector->encoder;
7882         }
7883
7884         return 0;
7885 }
7886
7887 static void intel_set_config_restore_state(struct drm_device *dev,
7888                                            struct intel_set_config *config)
7889 {
7890         struct intel_encoder *encoder;
7891         struct intel_connector *connector;
7892         int count;
7893
7894         count = 0;
7895         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7896                 encoder->new_crtc =
7897                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7898         }
7899
7900         count = 0;
7901         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7902                 connector->new_encoder =
7903                         to_intel_encoder(config->save_connector_encoders[count++]);
7904         }
7905 }
7906
7907 static void
7908 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7909                                       struct intel_set_config *config)
7910 {
7911
7912         /* We should be able to check here if the fb has the same properties
7913          * and then just flip_or_move it */
7914         if (set->crtc->fb != set->fb) {
7915                 /* If we have no fb then treat it as a full mode set */
7916                 if (set->crtc->fb == NULL) {
7917                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7918                         config->mode_changed = true;
7919                 } else if (set->fb == NULL) {
7920                         config->mode_changed = true;
7921                 } else if (set->fb->depth != set->crtc->fb->depth) {
7922                         config->mode_changed = true;
7923                 } else if (set->fb->bits_per_pixel !=
7924                            set->crtc->fb->bits_per_pixel) {
7925                         config->mode_changed = true;
7926                 } else
7927                         config->fb_changed = true;
7928         }
7929
7930         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7931                 config->fb_changed = true;
7932
7933         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7934                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7935                 drm_mode_debug_printmodeline(&set->crtc->mode);
7936                 drm_mode_debug_printmodeline(set->mode);
7937                 config->mode_changed = true;
7938         }
7939 }
7940
7941 static int
7942 intel_modeset_stage_output_state(struct drm_device *dev,
7943                                  struct drm_mode_set *set,
7944                                  struct intel_set_config *config)
7945 {
7946         struct drm_crtc *new_crtc;
7947         struct intel_connector *connector;
7948         struct intel_encoder *encoder;
7949         int count, ro;
7950
7951         /* The upper layers ensure that we either disabl a crtc or have a list
7952          * of connectors. For paranoia, double-check this. */
7953         WARN_ON(!set->fb && (set->num_connectors != 0));
7954         WARN_ON(set->fb && (set->num_connectors == 0));
7955
7956         count = 0;
7957         list_for_each_entry(connector, &dev->mode_config.connector_list,
7958                             base.head) {
7959                 /* Otherwise traverse passed in connector list and get encoders
7960                  * for them. */
7961                 for (ro = 0; ro < set->num_connectors; ro++) {
7962                         if (set->connectors[ro] == &connector->base) {
7963                                 connector->new_encoder = connector->encoder;
7964                                 break;
7965                         }
7966                 }
7967
7968                 /* If we disable the crtc, disable all its connectors. Also, if
7969                  * the connector is on the changing crtc but not on the new
7970                  * connector list, disable it. */
7971                 if ((!set->fb || ro == set->num_connectors) &&
7972                     connector->base.encoder &&
7973                     connector->base.encoder->crtc == set->crtc) {
7974                         connector->new_encoder = NULL;
7975
7976                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7977                                 connector->base.base.id,
7978                                 drm_get_connector_name(&connector->base));
7979                 }
7980
7981
7982                 if (&connector->new_encoder->base != connector->base.encoder) {
7983                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7984                         config->mode_changed = true;
7985                 }
7986
7987                 /* Disable all disconnected encoders. */
7988                 if (connector->base.status == connector_status_disconnected)
7989                         connector->new_encoder = NULL;
7990         }
7991         /* connector->new_encoder is now updated for all connectors. */
7992
7993         /* Update crtc of enabled connectors. */
7994         count = 0;
7995         list_for_each_entry(connector, &dev->mode_config.connector_list,
7996                             base.head) {
7997                 if (!connector->new_encoder)
7998                         continue;
7999
8000                 new_crtc = connector->new_encoder->base.crtc;
8001
8002                 for (ro = 0; ro < set->num_connectors; ro++) {
8003                         if (set->connectors[ro] == &connector->base)
8004                                 new_crtc = set->crtc;
8005                 }
8006
8007                 /* Make sure the new CRTC will work with the encoder */
8008                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8009                                            new_crtc)) {
8010                         return -EINVAL;
8011                 }
8012                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8013
8014                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8015                         connector->base.base.id,
8016                         drm_get_connector_name(&connector->base),
8017                         new_crtc->base.id);
8018         }
8019
8020         /* Check for any encoders that needs to be disabled. */
8021         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8022                             base.head) {
8023                 list_for_each_entry(connector,
8024                                     &dev->mode_config.connector_list,
8025                                     base.head) {
8026                         if (connector->new_encoder == encoder) {
8027                                 WARN_ON(!connector->new_encoder->new_crtc);
8028
8029                                 goto next_encoder;
8030                         }
8031                 }
8032                 encoder->new_crtc = NULL;
8033 next_encoder:
8034                 /* Only now check for crtc changes so we don't miss encoders
8035                  * that will be disabled. */
8036                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8037                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8038                         config->mode_changed = true;
8039                 }
8040         }
8041         /* Now we've also updated encoder->new_crtc for all encoders. */
8042
8043         return 0;
8044 }
8045
8046 static int intel_crtc_set_config(struct drm_mode_set *set)
8047 {
8048         struct drm_device *dev;
8049         struct drm_mode_set save_set;
8050         struct intel_set_config *config;
8051         int ret;
8052
8053         BUG_ON(!set);
8054         BUG_ON(!set->crtc);
8055         BUG_ON(!set->crtc->helper_private);
8056
8057         if (!set->mode)
8058                 set->fb = NULL;
8059
8060         /* The fb helper likes to play gross jokes with ->mode_set_config.
8061          * Unfortunately the crtc helper doesn't do much at all for this case,
8062          * so we have to cope with this madness until the fb helper is fixed up. */
8063         if (set->fb && set->num_connectors == 0)
8064                 return 0;
8065
8066         if (set->fb) {
8067                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8068                                 set->crtc->base.id, set->fb->base.id,
8069                                 (int)set->num_connectors, set->x, set->y);
8070         } else {
8071                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8072         }
8073
8074         dev = set->crtc->dev;
8075
8076         ret = -ENOMEM;
8077         config = kzalloc(sizeof(*config), GFP_KERNEL);
8078         if (!config)
8079                 goto out_config;
8080
8081         ret = intel_set_config_save_state(dev, config);
8082         if (ret)
8083                 goto out_config;
8084
8085         save_set.crtc = set->crtc;
8086         save_set.mode = &set->crtc->mode;
8087         save_set.x = set->crtc->x;
8088         save_set.y = set->crtc->y;
8089         save_set.fb = set->crtc->fb;
8090
8091         /* Compute whether we need a full modeset, only an fb base update or no
8092          * change at all. In the future we might also check whether only the
8093          * mode changed, e.g. for LVDS where we only change the panel fitter in
8094          * such cases. */
8095         intel_set_config_compute_mode_changes(set, config);
8096
8097         ret = intel_modeset_stage_output_state(dev, set, config);
8098         if (ret)
8099                 goto fail;
8100
8101         if (config->mode_changed) {
8102                 if (set->mode) {
8103                         DRM_DEBUG_KMS("attempting to set mode from"
8104                                         " userspace\n");
8105                         drm_mode_debug_printmodeline(set->mode);
8106                 }
8107
8108                 if (!intel_set_mode(set->crtc, set->mode,
8109                                     set->x, set->y, set->fb)) {
8110                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8111                                   set->crtc->base.id);
8112                         ret = -EINVAL;
8113                         goto fail;
8114                 }
8115         } else if (config->fb_changed) {
8116                 ret = intel_pipe_set_base(set->crtc,
8117                                           set->x, set->y, set->fb);
8118         }
8119
8120         intel_set_config_free(config);
8121
8122         return 0;
8123
8124 fail:
8125         intel_set_config_restore_state(dev, config);
8126
8127         /* Try to restore the config */
8128         if (config->mode_changed &&
8129             !intel_set_mode(save_set.crtc, save_set.mode,
8130                             save_set.x, save_set.y, save_set.fb))
8131                 DRM_ERROR("failed to restore config after modeset failure\n");
8132
8133 out_config:
8134         intel_set_config_free(config);
8135         return ret;
8136 }
8137
8138 static const struct drm_crtc_funcs intel_crtc_funcs = {
8139         .cursor_set = intel_crtc_cursor_set,
8140         .cursor_move = intel_crtc_cursor_move,
8141         .gamma_set = intel_crtc_gamma_set,
8142         .set_config = intel_crtc_set_config,
8143         .destroy = intel_crtc_destroy,
8144         .page_flip = intel_crtc_page_flip,
8145 };
8146
8147 static void intel_cpu_pll_init(struct drm_device *dev)
8148 {
8149         if (IS_HASWELL(dev))
8150                 intel_ddi_pll_init(dev);
8151 }
8152
8153 static void intel_pch_pll_init(struct drm_device *dev)
8154 {
8155         drm_i915_private_t *dev_priv = dev->dev_private;
8156         int i;
8157
8158         if (dev_priv->num_pch_pll == 0) {
8159                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8160                 return;
8161         }
8162
8163         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8164                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8165                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8166                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8167         }
8168 }
8169
8170 static void intel_crtc_init(struct drm_device *dev, int pipe)
8171 {
8172         drm_i915_private_t *dev_priv = dev->dev_private;
8173         struct intel_crtc *intel_crtc;
8174         int i;
8175
8176         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8177         if (intel_crtc == NULL)
8178                 return;
8179
8180         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8181
8182         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8183         for (i = 0; i < 256; i++) {
8184                 intel_crtc->lut_r[i] = i;
8185                 intel_crtc->lut_g[i] = i;
8186                 intel_crtc->lut_b[i] = i;
8187         }
8188
8189         /* Swap pipes & planes for FBC on pre-965 */
8190         intel_crtc->pipe = pipe;
8191         intel_crtc->plane = pipe;
8192         intel_crtc->cpu_transcoder = pipe;
8193         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8194                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8195                 intel_crtc->plane = !pipe;
8196         }
8197
8198         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8199                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8200         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8201         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8202
8203         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8204
8205         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8206 }
8207
8208 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8209                                 struct drm_file *file)
8210 {
8211         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8212         struct drm_mode_object *drmmode_obj;
8213         struct intel_crtc *crtc;
8214
8215         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8216                 return -ENODEV;
8217
8218         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8219                         DRM_MODE_OBJECT_CRTC);
8220
8221         if (!drmmode_obj) {
8222                 DRM_ERROR("no such CRTC id\n");
8223                 return -EINVAL;
8224         }
8225
8226         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8227         pipe_from_crtc_id->pipe = crtc->pipe;
8228
8229         return 0;
8230 }
8231
8232 static int intel_encoder_clones(struct intel_encoder *encoder)
8233 {
8234         struct drm_device *dev = encoder->base.dev;
8235         struct intel_encoder *source_encoder;
8236         int index_mask = 0;
8237         int entry = 0;
8238
8239         list_for_each_entry(source_encoder,
8240                             &dev->mode_config.encoder_list, base.head) {
8241
8242                 if (encoder == source_encoder)
8243                         index_mask |= (1 << entry);
8244
8245                 /* Intel hw has only one MUX where enocoders could be cloned. */
8246                 if (encoder->cloneable && source_encoder->cloneable)
8247                         index_mask |= (1 << entry);
8248
8249                 entry++;
8250         }
8251
8252         return index_mask;
8253 }
8254
8255 static bool has_edp_a(struct drm_device *dev)
8256 {
8257         struct drm_i915_private *dev_priv = dev->dev_private;
8258
8259         if (!IS_MOBILE(dev))
8260                 return false;
8261
8262         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8263                 return false;
8264
8265         if (IS_GEN5(dev) &&
8266             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8267                 return false;
8268
8269         return true;
8270 }
8271
8272 static void intel_setup_outputs(struct drm_device *dev)
8273 {
8274         struct drm_i915_private *dev_priv = dev->dev_private;
8275         struct intel_encoder *encoder;
8276         bool dpd_is_edp = false;
8277         bool has_lvds;
8278
8279         has_lvds = intel_lvds_init(dev);
8280         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8281                 /* disable the panel fitter on everything but LVDS */
8282                 I915_WRITE(PFIT_CONTROL, 0);
8283         }
8284
8285         if (HAS_PCH_SPLIT(dev)) {
8286                 dpd_is_edp = intel_dpd_is_edp(dev);
8287
8288                 if (has_edp_a(dev))
8289                         intel_dp_init(dev, DP_A, PORT_A);
8290
8291                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8292                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8293         }
8294
8295         intel_crt_init(dev);
8296
8297         if (IS_HASWELL(dev)) {
8298                 int found;
8299
8300                 /* Haswell uses DDI functions to detect digital outputs */
8301                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8302                 /* DDI A only supports eDP */
8303                 if (found)
8304                         intel_ddi_init(dev, PORT_A);
8305
8306                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8307                  * register */
8308                 found = I915_READ(SFUSE_STRAP);
8309
8310                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8311                         intel_ddi_init(dev, PORT_B);
8312                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8313                         intel_ddi_init(dev, PORT_C);
8314                 if (found & SFUSE_STRAP_DDID_DETECTED)
8315                         intel_ddi_init(dev, PORT_D);
8316         } else if (HAS_PCH_SPLIT(dev)) {
8317                 int found;
8318
8319                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8320                         /* PCH SDVOB multiplex with HDMIB */
8321                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8322                         if (!found)
8323                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8324                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8325                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8326                 }
8327
8328                 if (I915_READ(HDMIC) & PORT_DETECTED)
8329                         intel_hdmi_init(dev, HDMIC, PORT_C);
8330
8331                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8332                         intel_hdmi_init(dev, HDMID, PORT_D);
8333
8334                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8335                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8336
8337                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8338                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8339         } else if (IS_VALLEYVIEW(dev)) {
8340                 int found;
8341
8342                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8343                 if (I915_READ(DP_C) & DP_DETECTED)
8344                         intel_dp_init(dev, DP_C, PORT_C);
8345
8346                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8347                         /* SDVOB multiplex with HDMIB */
8348                         found = intel_sdvo_init(dev, SDVOB, true);
8349                         if (!found)
8350                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8351                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8352                                 intel_dp_init(dev, DP_B, PORT_B);
8353                 }
8354
8355                 if (I915_READ(SDVOC) & PORT_DETECTED)
8356                         intel_hdmi_init(dev, SDVOC, PORT_C);
8357
8358         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8359                 bool found = false;
8360
8361                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8362                         DRM_DEBUG_KMS("probing SDVOB\n");
8363                         found = intel_sdvo_init(dev, SDVOB, true);
8364                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8365                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8366                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8367                         }
8368
8369                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8370                                 DRM_DEBUG_KMS("probing DP_B\n");
8371                                 intel_dp_init(dev, DP_B, PORT_B);
8372                         }
8373                 }
8374
8375                 /* Before G4X SDVOC doesn't have its own detect register */
8376
8377                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8378                         DRM_DEBUG_KMS("probing SDVOC\n");
8379                         found = intel_sdvo_init(dev, SDVOC, false);
8380                 }
8381
8382                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8383
8384                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8385                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8386                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8387                         }
8388                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8389                                 DRM_DEBUG_KMS("probing DP_C\n");
8390                                 intel_dp_init(dev, DP_C, PORT_C);
8391                         }
8392                 }
8393
8394                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8395                     (I915_READ(DP_D) & DP_DETECTED)) {
8396                         DRM_DEBUG_KMS("probing DP_D\n");
8397                         intel_dp_init(dev, DP_D, PORT_D);
8398                 }
8399         } else if (IS_GEN2(dev))
8400                 intel_dvo_init(dev);
8401
8402         if (SUPPORTS_TV(dev))
8403                 intel_tv_init(dev);
8404
8405         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8406                 encoder->base.possible_crtcs = encoder->crtc_mask;
8407                 encoder->base.possible_clones =
8408                         intel_encoder_clones(encoder);
8409         }
8410
8411         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8412                 ironlake_init_pch_refclk(dev);
8413 }
8414
8415 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8416 {
8417         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8418
8419         drm_framebuffer_cleanup(fb);
8420         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8421
8422         kfree(intel_fb);
8423 }
8424
8425 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8426                                                 struct drm_file *file,
8427                                                 unsigned int *handle)
8428 {
8429         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8430         struct drm_i915_gem_object *obj = intel_fb->obj;
8431
8432         return drm_gem_handle_create(file, &obj->base, handle);
8433 }
8434
8435 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8436         .destroy = intel_user_framebuffer_destroy,
8437         .create_handle = intel_user_framebuffer_create_handle,
8438 };
8439
8440 int intel_framebuffer_init(struct drm_device *dev,
8441                            struct intel_framebuffer *intel_fb,
8442                            struct drm_mode_fb_cmd2 *mode_cmd,
8443                            struct drm_i915_gem_object *obj)
8444 {
8445         int ret;
8446
8447         if (obj->tiling_mode == I915_TILING_Y)
8448                 return -EINVAL;
8449
8450         if (mode_cmd->pitches[0] & 63)
8451                 return -EINVAL;
8452
8453         /* FIXME <= Gen4 stride limits are bit unclear */
8454         if (mode_cmd->pitches[0] > 32768)
8455                 return -EINVAL;
8456
8457         if (obj->tiling_mode != I915_TILING_NONE &&
8458             mode_cmd->pitches[0] != obj->stride)
8459                 return -EINVAL;
8460
8461         /* Reject formats not supported by any plane early. */
8462         switch (mode_cmd->pixel_format) {
8463         case DRM_FORMAT_C8:
8464         case DRM_FORMAT_RGB565:
8465         case DRM_FORMAT_XRGB8888:
8466         case DRM_FORMAT_ARGB8888:
8467                 break;
8468         case DRM_FORMAT_XRGB1555:
8469         case DRM_FORMAT_ARGB1555:
8470                 if (INTEL_INFO(dev)->gen > 3)
8471                         return -EINVAL;
8472                 break;
8473         case DRM_FORMAT_XBGR8888:
8474         case DRM_FORMAT_ABGR8888:
8475         case DRM_FORMAT_XRGB2101010:
8476         case DRM_FORMAT_ARGB2101010:
8477         case DRM_FORMAT_XBGR2101010:
8478         case DRM_FORMAT_ABGR2101010:
8479                 if (INTEL_INFO(dev)->gen < 4)
8480                         return -EINVAL;
8481                 break;
8482         case DRM_FORMAT_YUYV:
8483         case DRM_FORMAT_UYVY:
8484         case DRM_FORMAT_YVYU:
8485         case DRM_FORMAT_VYUY:
8486                 if (INTEL_INFO(dev)->gen < 6)
8487                         return -EINVAL;
8488                 break;
8489         default:
8490                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8491                 return -EINVAL;
8492         }
8493
8494         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8495         if (mode_cmd->offsets[0] != 0)
8496                 return -EINVAL;
8497
8498         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8499         if (ret) {
8500                 DRM_ERROR("framebuffer init failed %d\n", ret);
8501                 return ret;
8502         }
8503
8504         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8505         intel_fb->obj = obj;
8506         return 0;
8507 }
8508
8509 static struct drm_framebuffer *
8510 intel_user_framebuffer_create(struct drm_device *dev,
8511                               struct drm_file *filp,
8512                               struct drm_mode_fb_cmd2 *mode_cmd)
8513 {
8514         struct drm_i915_gem_object *obj;
8515
8516         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8517                                                 mode_cmd->handles[0]));
8518         if (&obj->base == NULL)
8519                 return ERR_PTR(-ENOENT);
8520
8521         return intel_framebuffer_create(dev, mode_cmd, obj);
8522 }
8523
8524 static const struct drm_mode_config_funcs intel_mode_funcs = {
8525         .fb_create = intel_user_framebuffer_create,
8526         .output_poll_changed = intel_fb_output_poll_changed,
8527 };
8528
8529 /* Set up chip specific display functions */
8530 static void intel_init_display(struct drm_device *dev)
8531 {
8532         struct drm_i915_private *dev_priv = dev->dev_private;
8533
8534         /* We always want a DPMS function */
8535         if (IS_HASWELL(dev)) {
8536                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8537                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8538                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8539                 dev_priv->display.off = haswell_crtc_off;
8540                 dev_priv->display.update_plane = ironlake_update_plane;
8541         } else if (HAS_PCH_SPLIT(dev)) {
8542                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8543                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8544                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8545                 dev_priv->display.off = ironlake_crtc_off;
8546                 dev_priv->display.update_plane = ironlake_update_plane;
8547         } else {
8548                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8549                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8550                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8551                 dev_priv->display.off = i9xx_crtc_off;
8552                 dev_priv->display.update_plane = i9xx_update_plane;
8553         }
8554
8555         /* Returns the core display clock speed */
8556         if (IS_VALLEYVIEW(dev))
8557                 dev_priv->display.get_display_clock_speed =
8558                         valleyview_get_display_clock_speed;
8559         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8560                 dev_priv->display.get_display_clock_speed =
8561                         i945_get_display_clock_speed;
8562         else if (IS_I915G(dev))
8563                 dev_priv->display.get_display_clock_speed =
8564                         i915_get_display_clock_speed;
8565         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8566                 dev_priv->display.get_display_clock_speed =
8567                         i9xx_misc_get_display_clock_speed;
8568         else if (IS_I915GM(dev))
8569                 dev_priv->display.get_display_clock_speed =
8570                         i915gm_get_display_clock_speed;
8571         else if (IS_I865G(dev))
8572                 dev_priv->display.get_display_clock_speed =
8573                         i865_get_display_clock_speed;
8574         else if (IS_I85X(dev))
8575                 dev_priv->display.get_display_clock_speed =
8576                         i855_get_display_clock_speed;
8577         else /* 852, 830 */
8578                 dev_priv->display.get_display_clock_speed =
8579                         i830_get_display_clock_speed;
8580
8581         if (HAS_PCH_SPLIT(dev)) {
8582                 if (IS_GEN5(dev)) {
8583                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8584                         dev_priv->display.write_eld = ironlake_write_eld;
8585                 } else if (IS_GEN6(dev)) {
8586                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8587                         dev_priv->display.write_eld = ironlake_write_eld;
8588                 } else if (IS_IVYBRIDGE(dev)) {
8589                         /* FIXME: detect B0+ stepping and use auto training */
8590                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8591                         dev_priv->display.write_eld = ironlake_write_eld;
8592                         dev_priv->display.modeset_global_resources =
8593                                 ivb_modeset_global_resources;
8594                 } else if (IS_HASWELL(dev)) {
8595                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8596                         dev_priv->display.write_eld = haswell_write_eld;
8597                 } else
8598                         dev_priv->display.update_wm = NULL;
8599         } else if (IS_G4X(dev)) {
8600                 dev_priv->display.write_eld = g4x_write_eld;
8601         }
8602
8603         /* Default just returns -ENODEV to indicate unsupported */
8604         dev_priv->display.queue_flip = intel_default_queue_flip;
8605
8606         switch (INTEL_INFO(dev)->gen) {
8607         case 2:
8608                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8609                 break;
8610
8611         case 3:
8612                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8613                 break;
8614
8615         case 4:
8616         case 5:
8617                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8618                 break;
8619
8620         case 6:
8621                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8622                 break;
8623         case 7:
8624                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8625                 break;
8626         }
8627 }
8628
8629 /*
8630  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8631  * resume, or other times.  This quirk makes sure that's the case for
8632  * affected systems.
8633  */
8634 static void quirk_pipea_force(struct drm_device *dev)
8635 {
8636         struct drm_i915_private *dev_priv = dev->dev_private;
8637
8638         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8639         DRM_INFO("applying pipe a force quirk\n");
8640 }
8641
8642 /*
8643  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8644  */
8645 static void quirk_ssc_force_disable(struct drm_device *dev)
8646 {
8647         struct drm_i915_private *dev_priv = dev->dev_private;
8648         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8649         DRM_INFO("applying lvds SSC disable quirk\n");
8650 }
8651
8652 /*
8653  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8654  * brightness value
8655  */
8656 static void quirk_invert_brightness(struct drm_device *dev)
8657 {
8658         struct drm_i915_private *dev_priv = dev->dev_private;
8659         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8660         DRM_INFO("applying inverted panel brightness quirk\n");
8661 }
8662
8663 struct intel_quirk {
8664         int device;
8665         int subsystem_vendor;
8666         int subsystem_device;
8667         void (*hook)(struct drm_device *dev);
8668 };
8669
8670 static struct intel_quirk intel_quirks[] = {
8671         /* HP Mini needs pipe A force quirk (LP: #322104) */
8672         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8673
8674         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8675         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8676
8677         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8678         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8679
8680         /* 830/845 need to leave pipe A & dpll A up */
8681         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8682         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8683
8684         /* Lenovo U160 cannot use SSC on LVDS */
8685         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8686
8687         /* Sony Vaio Y cannot use SSC on LVDS */
8688         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8689
8690         /* Acer Aspire 5734Z must invert backlight brightness */
8691         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8692 };
8693
8694 static void intel_init_quirks(struct drm_device *dev)
8695 {
8696         struct pci_dev *d = dev->pdev;
8697         int i;
8698
8699         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8700                 struct intel_quirk *q = &intel_quirks[i];
8701
8702                 if (d->device == q->device &&
8703                     (d->subsystem_vendor == q->subsystem_vendor ||
8704                      q->subsystem_vendor == PCI_ANY_ID) &&
8705                     (d->subsystem_device == q->subsystem_device ||
8706                      q->subsystem_device == PCI_ANY_ID))
8707                         q->hook(dev);
8708         }
8709 }
8710
8711 /* Disable the VGA plane that we never use */
8712 static void i915_disable_vga(struct drm_device *dev)
8713 {
8714         struct drm_i915_private *dev_priv = dev->dev_private;
8715         u8 sr1;
8716         u32 vga_reg;
8717
8718         if (HAS_PCH_SPLIT(dev))
8719                 vga_reg = CPU_VGACNTRL;
8720         else
8721                 vga_reg = VGACNTRL;
8722
8723         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8724         outb(SR01, VGA_SR_INDEX);
8725         sr1 = inb(VGA_SR_DATA);
8726         outb(sr1 | 1<<5, VGA_SR_DATA);
8727         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8728         udelay(300);
8729
8730         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8731         POSTING_READ(vga_reg);
8732 }
8733
8734 void intel_modeset_init_hw(struct drm_device *dev)
8735 {
8736         /* We attempt to init the necessary power wells early in the initialization
8737          * time, so the subsystems that expect power to be enabled can work.
8738          */
8739         intel_init_power_wells(dev);
8740
8741         intel_prepare_ddi(dev);
8742
8743         intel_init_clock_gating(dev);
8744
8745         mutex_lock(&dev->struct_mutex);
8746         intel_enable_gt_powersave(dev);
8747         mutex_unlock(&dev->struct_mutex);
8748 }
8749
8750 void intel_modeset_init(struct drm_device *dev)
8751 {
8752         struct drm_i915_private *dev_priv = dev->dev_private;
8753         int i, ret;
8754
8755         drm_mode_config_init(dev);
8756
8757         dev->mode_config.min_width = 0;
8758         dev->mode_config.min_height = 0;
8759
8760         dev->mode_config.preferred_depth = 24;
8761         dev->mode_config.prefer_shadow = 1;
8762
8763         dev->mode_config.funcs = &intel_mode_funcs;
8764
8765         intel_init_quirks(dev);
8766
8767         intel_init_pm(dev);
8768
8769         intel_init_display(dev);
8770
8771         if (IS_GEN2(dev)) {
8772                 dev->mode_config.max_width = 2048;
8773                 dev->mode_config.max_height = 2048;
8774         } else if (IS_GEN3(dev)) {
8775                 dev->mode_config.max_width = 4096;
8776                 dev->mode_config.max_height = 4096;
8777         } else {
8778                 dev->mode_config.max_width = 8192;
8779                 dev->mode_config.max_height = 8192;
8780         }
8781         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8782
8783         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8784                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8785
8786         for (i = 0; i < dev_priv->num_pipe; i++) {
8787                 intel_crtc_init(dev, i);
8788                 ret = intel_plane_init(dev, i);
8789                 if (ret)
8790                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8791         }
8792
8793         intel_cpu_pll_init(dev);
8794         intel_pch_pll_init(dev);
8795
8796         /* Just disable it once at startup */
8797         i915_disable_vga(dev);
8798         intel_setup_outputs(dev);
8799 }
8800
8801 static void
8802 intel_connector_break_all_links(struct intel_connector *connector)
8803 {
8804         connector->base.dpms = DRM_MODE_DPMS_OFF;
8805         connector->base.encoder = NULL;
8806         connector->encoder->connectors_active = false;
8807         connector->encoder->base.crtc = NULL;
8808 }
8809
8810 static void intel_enable_pipe_a(struct drm_device *dev)
8811 {
8812         struct intel_connector *connector;
8813         struct drm_connector *crt = NULL;
8814         struct intel_load_detect_pipe load_detect_temp;
8815
8816         /* We can't just switch on the pipe A, we need to set things up with a
8817          * proper mode and output configuration. As a gross hack, enable pipe A
8818          * by enabling the load detect pipe once. */
8819         list_for_each_entry(connector,
8820                             &dev->mode_config.connector_list,
8821                             base.head) {
8822                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8823                         crt = &connector->base;
8824                         break;
8825                 }
8826         }
8827
8828         if (!crt)
8829                 return;
8830
8831         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8832                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8833
8834
8835 }
8836
8837 static bool
8838 intel_check_plane_mapping(struct intel_crtc *crtc)
8839 {
8840         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8841         u32 reg, val;
8842
8843         if (dev_priv->num_pipe == 1)
8844                 return true;
8845
8846         reg = DSPCNTR(!crtc->plane);
8847         val = I915_READ(reg);
8848
8849         if ((val & DISPLAY_PLANE_ENABLE) &&
8850             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8851                 return false;
8852
8853         return true;
8854 }
8855
8856 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8857 {
8858         struct drm_device *dev = crtc->base.dev;
8859         struct drm_i915_private *dev_priv = dev->dev_private;
8860         u32 reg;
8861
8862         /* Clear any frame start delays used for debugging left by the BIOS */
8863         reg = PIPECONF(crtc->cpu_transcoder);
8864         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8865
8866         /* We need to sanitize the plane -> pipe mapping first because this will
8867          * disable the crtc (and hence change the state) if it is wrong. Note
8868          * that gen4+ has a fixed plane -> pipe mapping.  */
8869         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8870                 struct intel_connector *connector;
8871                 bool plane;
8872
8873                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8874                               crtc->base.base.id);
8875
8876                 /* Pipe has the wrong plane attached and the plane is active.
8877                  * Temporarily change the plane mapping and disable everything
8878                  * ...  */
8879                 plane = crtc->plane;
8880                 crtc->plane = !plane;
8881                 dev_priv->display.crtc_disable(&crtc->base);
8882                 crtc->plane = plane;
8883
8884                 /* ... and break all links. */
8885                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8886                                     base.head) {
8887                         if (connector->encoder->base.crtc != &crtc->base)
8888                                 continue;
8889
8890                         intel_connector_break_all_links(connector);
8891                 }
8892
8893                 WARN_ON(crtc->active);
8894                 crtc->base.enabled = false;
8895         }
8896
8897         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8898             crtc->pipe == PIPE_A && !crtc->active) {
8899                 /* BIOS forgot to enable pipe A, this mostly happens after
8900                  * resume. Force-enable the pipe to fix this, the update_dpms
8901                  * call below we restore the pipe to the right state, but leave
8902                  * the required bits on. */
8903                 intel_enable_pipe_a(dev);
8904         }
8905
8906         /* Adjust the state of the output pipe according to whether we
8907          * have active connectors/encoders. */
8908         intel_crtc_update_dpms(&crtc->base);
8909
8910         if (crtc->active != crtc->base.enabled) {
8911                 struct intel_encoder *encoder;
8912
8913                 /* This can happen either due to bugs in the get_hw_state
8914                  * functions or because the pipe is force-enabled due to the
8915                  * pipe A quirk. */
8916                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8917                               crtc->base.base.id,
8918                               crtc->base.enabled ? "enabled" : "disabled",
8919                               crtc->active ? "enabled" : "disabled");
8920
8921                 crtc->base.enabled = crtc->active;
8922
8923                 /* Because we only establish the connector -> encoder ->
8924                  * crtc links if something is active, this means the
8925                  * crtc is now deactivated. Break the links. connector
8926                  * -> encoder links are only establish when things are
8927                  *  actually up, hence no need to break them. */
8928                 WARN_ON(crtc->active);
8929
8930                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8931                         WARN_ON(encoder->connectors_active);
8932                         encoder->base.crtc = NULL;
8933                 }
8934         }
8935 }
8936
8937 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8938 {
8939         struct intel_connector *connector;
8940         struct drm_device *dev = encoder->base.dev;
8941
8942         /* We need to check both for a crtc link (meaning that the
8943          * encoder is active and trying to read from a pipe) and the
8944          * pipe itself being active. */
8945         bool has_active_crtc = encoder->base.crtc &&
8946                 to_intel_crtc(encoder->base.crtc)->active;
8947
8948         if (encoder->connectors_active && !has_active_crtc) {
8949                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8950                               encoder->base.base.id,
8951                               drm_get_encoder_name(&encoder->base));
8952
8953                 /* Connector is active, but has no active pipe. This is
8954                  * fallout from our resume register restoring. Disable
8955                  * the encoder manually again. */
8956                 if (encoder->base.crtc) {
8957                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8958                                       encoder->base.base.id,
8959                                       drm_get_encoder_name(&encoder->base));
8960                         encoder->disable(encoder);
8961                 }
8962
8963                 /* Inconsistent output/port/pipe state happens presumably due to
8964                  * a bug in one of the get_hw_state functions. Or someplace else
8965                  * in our code, like the register restore mess on resume. Clamp
8966                  * things to off as a safer default. */
8967                 list_for_each_entry(connector,
8968                                     &dev->mode_config.connector_list,
8969                                     base.head) {
8970                         if (connector->encoder != encoder)
8971                                 continue;
8972
8973                         intel_connector_break_all_links(connector);
8974                 }
8975         }
8976         /* Enabled encoders without active connectors will be fixed in
8977          * the crtc fixup. */
8978 }
8979
8980 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8981  * and i915 state tracking structures. */
8982 void intel_modeset_setup_hw_state(struct drm_device *dev)
8983 {
8984         struct drm_i915_private *dev_priv = dev->dev_private;
8985         enum pipe pipe;
8986         u32 tmp;
8987         struct intel_crtc *crtc;
8988         struct intel_encoder *encoder;
8989         struct intel_connector *connector;
8990
8991         if (IS_HASWELL(dev)) {
8992                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8993
8994                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8995                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8996                         case TRANS_DDI_EDP_INPUT_A_ON:
8997                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8998                                 pipe = PIPE_A;
8999                                 break;
9000                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9001                                 pipe = PIPE_B;
9002                                 break;
9003                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9004                                 pipe = PIPE_C;
9005                                 break;
9006                         }
9007
9008                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9009                         crtc->cpu_transcoder = TRANSCODER_EDP;
9010
9011                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9012                                       pipe_name(pipe));
9013                 }
9014         }
9015
9016         for_each_pipe(pipe) {
9017                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9018
9019                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9020                 if (tmp & PIPECONF_ENABLE)
9021                         crtc->active = true;
9022                 else
9023                         crtc->active = false;
9024
9025                 crtc->base.enabled = crtc->active;
9026
9027                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9028                               crtc->base.base.id,
9029                               crtc->active ? "enabled" : "disabled");
9030         }
9031
9032         if (IS_HASWELL(dev))
9033                 intel_ddi_setup_hw_pll_state(dev);
9034
9035         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9036                             base.head) {
9037                 pipe = 0;
9038
9039                 if (encoder->get_hw_state(encoder, &pipe)) {
9040                         encoder->base.crtc =
9041                                 dev_priv->pipe_to_crtc_mapping[pipe];
9042                 } else {
9043                         encoder->base.crtc = NULL;
9044                 }
9045
9046                 encoder->connectors_active = false;
9047                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9048                               encoder->base.base.id,
9049                               drm_get_encoder_name(&encoder->base),
9050                               encoder->base.crtc ? "enabled" : "disabled",
9051                               pipe);
9052         }
9053
9054         list_for_each_entry(connector, &dev->mode_config.connector_list,
9055                             base.head) {
9056                 if (connector->get_hw_state(connector)) {
9057                         connector->base.dpms = DRM_MODE_DPMS_ON;
9058                         connector->encoder->connectors_active = true;
9059                         connector->base.encoder = &connector->encoder->base;
9060                 } else {
9061                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9062                         connector->base.encoder = NULL;
9063                 }
9064                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9065                               connector->base.base.id,
9066                               drm_get_connector_name(&connector->base),
9067                               connector->base.encoder ? "enabled" : "disabled");
9068         }
9069
9070         /* HW state is read out, now we need to sanitize this mess. */
9071         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9072                             base.head) {
9073                 intel_sanitize_encoder(encoder);
9074         }
9075
9076         for_each_pipe(pipe) {
9077                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9078                 intel_sanitize_crtc(crtc);
9079         }
9080
9081         intel_modeset_update_staged_output_state(dev);
9082
9083         intel_modeset_check_state(dev);
9084
9085         drm_mode_config_reset(dev);
9086 }
9087
9088 void intel_modeset_gem_init(struct drm_device *dev)
9089 {
9090         intel_modeset_init_hw(dev);
9091
9092         intel_setup_overlay(dev);
9093
9094         intel_modeset_setup_hw_state(dev);
9095 }
9096
9097 void intel_modeset_cleanup(struct drm_device *dev)
9098 {
9099         struct drm_i915_private *dev_priv = dev->dev_private;
9100         struct drm_crtc *crtc;
9101         struct intel_crtc *intel_crtc;
9102
9103         drm_kms_helper_poll_fini(dev);
9104         mutex_lock(&dev->struct_mutex);
9105
9106         intel_unregister_dsm_handler();
9107
9108
9109         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9110                 /* Skip inactive CRTCs */
9111                 if (!crtc->fb)
9112                         continue;
9113
9114                 intel_crtc = to_intel_crtc(crtc);
9115                 intel_increase_pllclock(crtc);
9116         }
9117
9118         intel_disable_fbc(dev);
9119
9120         intel_disable_gt_powersave(dev);
9121
9122         ironlake_teardown_rc6(dev);
9123
9124         if (IS_VALLEYVIEW(dev))
9125                 vlv_init_dpio(dev);
9126
9127         mutex_unlock(&dev->struct_mutex);
9128
9129         /* Disable the irq before mode object teardown, for the irq might
9130          * enqueue unpin/hotplug work. */
9131         drm_irq_uninstall(dev);
9132         cancel_work_sync(&dev_priv->hotplug_work);
9133         cancel_work_sync(&dev_priv->rps.work);
9134
9135         /* flush any delayed tasks or pending work */
9136         flush_scheduled_work();
9137
9138         drm_mode_config_cleanup(dev);
9139 }
9140
9141 /*
9142  * Return which encoder is currently attached for connector.
9143  */
9144 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9145 {
9146         return &intel_attached_encoder(connector)->base;
9147 }
9148
9149 void intel_connector_attach_encoder(struct intel_connector *connector,
9150                                     struct intel_encoder *encoder)
9151 {
9152         connector->encoder = encoder;
9153         drm_mode_connector_attach_encoder(&connector->base,
9154                                           &encoder->base);
9155 }
9156
9157 /*
9158  * set vga decode state - true == enable VGA decode
9159  */
9160 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9161 {
9162         struct drm_i915_private *dev_priv = dev->dev_private;
9163         u16 gmch_ctrl;
9164
9165         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9166         if (state)
9167                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9168         else
9169                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9170         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9171         return 0;
9172 }
9173
9174 #ifdef CONFIG_DEBUG_FS
9175 #include <linux/seq_file.h>
9176
9177 struct intel_display_error_state {
9178         struct intel_cursor_error_state {
9179                 u32 control;
9180                 u32 position;
9181                 u32 base;
9182                 u32 size;
9183         } cursor[I915_MAX_PIPES];
9184
9185         struct intel_pipe_error_state {
9186                 u32 conf;
9187                 u32 source;
9188
9189                 u32 htotal;
9190                 u32 hblank;
9191                 u32 hsync;
9192                 u32 vtotal;
9193                 u32 vblank;
9194                 u32 vsync;
9195         } pipe[I915_MAX_PIPES];
9196
9197         struct intel_plane_error_state {
9198                 u32 control;
9199                 u32 stride;
9200                 u32 size;
9201                 u32 pos;
9202                 u32 addr;
9203                 u32 surface;
9204                 u32 tile_offset;
9205         } plane[I915_MAX_PIPES];
9206 };
9207
9208 struct intel_display_error_state *
9209 intel_display_capture_error_state(struct drm_device *dev)
9210 {
9211         drm_i915_private_t *dev_priv = dev->dev_private;
9212         struct intel_display_error_state *error;
9213         enum transcoder cpu_transcoder;
9214         int i;
9215
9216         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9217         if (error == NULL)
9218                 return NULL;
9219
9220         for_each_pipe(i) {
9221                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9222
9223                 error->cursor[i].control = I915_READ(CURCNTR(i));
9224                 error->cursor[i].position = I915_READ(CURPOS(i));
9225                 error->cursor[i].base = I915_READ(CURBASE(i));
9226
9227                 error->plane[i].control = I915_READ(DSPCNTR(i));
9228                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9229                 error->plane[i].size = I915_READ(DSPSIZE(i));
9230                 error->plane[i].pos = I915_READ(DSPPOS(i));
9231                 error->plane[i].addr = I915_READ(DSPADDR(i));
9232                 if (INTEL_INFO(dev)->gen >= 4) {
9233                         error->plane[i].surface = I915_READ(DSPSURF(i));
9234                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9235                 }
9236
9237                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9238                 error->pipe[i].source = I915_READ(PIPESRC(i));
9239                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9240                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9241                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9242                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9243                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9244                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9245         }
9246
9247         return error;
9248 }
9249
9250 void
9251 intel_display_print_error_state(struct seq_file *m,
9252                                 struct drm_device *dev,
9253                                 struct intel_display_error_state *error)
9254 {
9255         drm_i915_private_t *dev_priv = dev->dev_private;
9256         int i;
9257
9258         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9259         for_each_pipe(i) {
9260                 seq_printf(m, "Pipe [%d]:\n", i);
9261                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9262                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9263                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9264                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9265                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9266                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9267                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9268                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9269
9270                 seq_printf(m, "Plane [%d]:\n", i);
9271                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9272                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9273                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9274                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9275                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9276                 if (INTEL_INFO(dev)->gen >= 4) {
9277                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9278                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9279                 }
9280
9281                 seq_printf(m, "Cursor [%d]:\n", i);
9282                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9283                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9284                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9285         }
9286 }
9287 #endif