drivers/gpu/drm/nouveau/nvd0_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_encoder.h"
  33 #include "nouveau_crtc.h"
  34 #include "nouveau_dma.h"
  35 #include "nouveau_fb.h"
  36 #include "nouveau_software.h"
  37 #include "nv50_display.h"
  38
  39 #define EVO_DMA_NR 9
  40
  41 #define EVO_MASTER  (0x00)
  42 #define EVO_FLIP(c) (0x01 + (c))
  43 #define EVO_OVLY(c) (0x05 + (c))
  44 #define EVO_OIMM(c) (0x09 + (c))
  45 #define EVO_CURS(c) (0x0d + (c))
  46
  47 /* offsets in shared sync bo of various structures */
  48 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  49 #define EVO_MAST_NTFY     EVO_SYNC(  0, 0x00)
  50 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c), 0x00)
  51 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c), 0x10)
  52
  53 struct evo {
  54         int idx;
  55         dma_addr_t handle;
  56         u32 *ptr;
  57         struct {
  58                 u32 offset;
  59                 u16 value;
  60         } sem;
  61 };
  62
  63 struct nvd0_display {
  64         struct nouveau_gpuobj *mem;
  65         struct nouveau_bo *sync;
  66         struct evo evo[9];
  67
  68         struct tasklet_struct tasklet;
  69         u32 modeset;
  70 };
  71
  72 static struct nvd0_display *
  73 nvd0_display(struct drm_device *dev)
  74 {
  75         struct drm_nouveau_private *dev_priv = dev->dev_private;
  76         return dev_priv->engine.display.priv;
  77 }
  78
  79 static struct drm_crtc *
  80 nvd0_display_crtc_get(struct drm_encoder *encoder)
  81 {
  82         return nouveau_encoder(encoder)->crtc;
  83 }
  84
  85 /******************************************************************************
  86  * EVO channel helpers
  87  *****************************************************************************/
  88 static inline int
  89 evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
  90 {
  91         int ret = 0;
  92         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
  93         nv_wr32(dev, 0x610704 + (id * 0x10), data);
  94         nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
  95         if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
  96                 ret = -EBUSY;
  97         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
  98         return ret;
  99 }
 100
 101 static u32 *
 102 evo_wait(struct drm_device *dev, int id, int nr)
 103 {
 104         struct nvd0_display *disp = nvd0_display(dev);
 105         u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
 106
 107         if (put + nr >= (PAGE_SIZE / 4)) {
 108                 disp->evo[id].ptr[put] = 0x20000000;
 109
 110                 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
 111                 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
 112                         NV_ERROR(dev, "evo %d dma stalled\n", id);
 113                         return NULL;
 114                 }
 115
 116                 put = 0;
 117         }
 118
 119         if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
 120                 NV_INFO(dev, "Evo%d: %p START\n", id, disp->evo[id].ptr + put);
 121
 122         return disp->evo[id].ptr + put;
 123 }
 124
 125 static void
 126 evo_kick(u32 *push, struct drm_device *dev, int id)
 127 {
 128         struct nvd0_display *disp = nvd0_display(dev);
 129
 130         if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) {
 131                 u32 curp = nv_rd32(dev, 0x640000 + (id * 0x1000)) >> 2;
 132                 u32 *cur = disp->evo[id].ptr + curp;
 133
 134                 while (cur < push)
 135                         NV_INFO(dev, "Evo%d: 0x%08x\n", id, *cur++);
 136                 NV_INFO(dev, "Evo%d: %p KICK!\n", id, push);
 137         }
 138
 139         nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
 140 }
 141
 142 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 143 #define evo_data(p,d)   *((p)++) = (d)
 144
 145 static int
 146 evo_init_dma(struct drm_device *dev, int ch)
 147 {
 148         struct nvd0_display *disp = nvd0_display(dev);
 149         u32 flags;
 150
 151         flags = 0x00000000;
 152         if (ch == EVO_MASTER)
 153                 flags |= 0x01000000;
 154
 155         nv_wr32(dev, 0x610494 + (ch * 0x0010), (disp->evo[ch].handle >> 8) | 3);
 156         nv_wr32(dev, 0x610498 + (ch * 0x0010), 0x00010000);
 157         nv_wr32(dev, 0x61049c + (ch * 0x0010), 0x00000001);
 158         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
 159         nv_wr32(dev, 0x640000 + (ch * 0x1000), 0x00000000);
 160         nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000013 | flags);
 161         if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000)) {
 162                 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch,
 163                               nv_rd32(dev, 0x610490 + (ch * 0x0010)));
 164                 return -EBUSY;
 165         }
 166
 167         nv_mask(dev, 0x610090, (1 << ch), (1 << ch));
 168         nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch));
 169         return 0;
 170 }
 171
 172 static void
 173 evo_fini_dma(struct drm_device *dev, int ch)
 174 {
 175         if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000010))
 176                 return;
 177
 178         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000000);
 179         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000003, 0x00000000);
 180         nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000);
 181         nv_mask(dev, 0x610090, (1 << ch), 0x00000000);
 182         nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000);
 183 }
 184
 185 static inline void
 186 evo_piow(struct drm_device *dev, int ch, u16 mthd, u32 data)
 187 {
 188         nv_wr32(dev, 0x640000 + (ch * 0x1000) + mthd, data);
 189 }
 190
 191 static int
 192 evo_init_pio(struct drm_device *dev, int ch)
 193 {
 194         nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000001);
 195         if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00010000)) {
 196                 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch,
 197                               nv_rd32(dev, 0x610490 + (ch * 0x0010)));
 198                 return -EBUSY;
 199         }
 200
 201         nv_mask(dev, 0x610090, (1 << ch), (1 << ch));
 202         nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch));
 203         return 0;
 204 }
 205
 206 static void
 207 evo_fini_pio(struct drm_device *dev, int ch)
 208 {
 209         if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000001))
 210                 return;
 211
 212         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
 213         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000001, 0x00000000);
 214         nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00000000);
 215         nv_mask(dev, 0x610090, (1 << ch), 0x00000000);
 216         nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000);
 217 }
 218
 219 static bool
 220 evo_sync_wait(void *data)
 221 {
 222         return nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000;
 223 }
 224
 225 static int
 226 evo_sync(struct drm_device *dev, int ch)
 227 {
 228         struct nvd0_display *disp = nvd0_display(dev);
 229         u32 *push = evo_wait(dev, ch, 8);
 230         if (push) {
 231                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 232                 evo_mthd(push, 0x0084, 1);
 233                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 234                 evo_mthd(push, 0x0080, 2);
 235                 evo_data(push, 0x00000000);
 236                 evo_data(push, 0x00000000);
 237                 evo_kick(push, dev, ch);
 238                 if (nv_wait_cb(dev, evo_sync_wait, disp->sync))
 239                         return 0;
 240         }
 241
 242         return -EBUSY;
 243 }
 244
 245 /******************************************************************************
 246  * Page flipping channel
 247  *****************************************************************************/
 248 struct nouveau_bo *
 249 nvd0_display_crtc_sema(struct drm_device *dev, int crtc)
 250 {
 251         return nvd0_display(dev)->sync;
 252 }
 253
 254 void
 255 nvd0_display_flip_stop(struct drm_crtc *crtc)
 256 {
 257         struct nvd0_display *disp = nvd0_display(crtc->dev);
 258         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 259         struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)];
 260         u32 *push;
 261
 262         push = evo_wait(crtc->dev, evo->idx, 8);
 263         if (push) {
 264                 evo_mthd(push, 0x0084, 1);
 265                 evo_data(push, 0x00000000);
 266                 evo_mthd(push, 0x0094, 1);
 267                 evo_data(push, 0x00000000);
 268                 evo_mthd(push, 0x00c0, 1);
 269                 evo_data(push, 0x00000000);
 270                 evo_mthd(push, 0x0080, 1);
 271                 evo_data(push, 0x00000000);
 272                 evo_kick(push, crtc->dev, evo->idx);
 273         }
 274 }
 275
 276 int
 277 nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 278                        struct nouveau_channel *chan, u32 swap_interval)
 279 {
 280         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 281         struct nvd0_display *disp = nvd0_display(crtc->dev);
 282         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 283         struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)];
 284         u64 offset;
 285         u32 *push;
 286         int ret;
 287
 288         swap_interval <<= 4;
 289         if (swap_interval == 0)
 290                 swap_interval |= 0x100;
 291
 292         push = evo_wait(crtc->dev, evo->idx, 128);
 293         if (unlikely(push == NULL))
 294                 return -EBUSY;
 295
 296         /* synchronise with the rendering channel, if necessary */
 297         if (likely(chan)) {
 298                 ret = RING_SPACE(chan, 10);
 299                 if (ret)
 300                         return ret;
 301
 302
 303                 offset  = nvc0_software_crtc(chan, nv_crtc->index);
 304                 offset += evo->sem.offset;
 305
 306                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 307                 OUT_RING  (chan, upper_32_bits(offset));
 308                 OUT_RING  (chan, lower_32_bits(offset));
 309                 OUT_RING  (chan, 0xf00d0000 | evo->sem.value);
 310                 OUT_RING  (chan, 0x1002);
 311                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 312                 OUT_RING  (chan, upper_32_bits(offset));
 313                 OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 314                 OUT_RING  (chan, 0x74b1e000);
 315                 OUT_RING  (chan, 0x1001);
 316                 FIRE_RING (chan);
 317         } else {
 318                 nouveau_bo_wr32(disp->sync, evo->sem.offset / 4,
 319                                 0xf00d0000 | evo->sem.value);
 320                 evo_sync(crtc->dev, EVO_MASTER);
 321         }
 322
 323         /* queue the flip */
 324         evo_mthd(push, 0x0100, 1);
 325         evo_data(push, 0xfffe0000);
 326         evo_mthd(push, 0x0084, 1);
 327         evo_data(push, swap_interval);
 328         if (!(swap_interval & 0x00000100)) {
 329                 evo_mthd(push, 0x00e0, 1);
 330                 evo_data(push, 0x40000000);
 331         }
 332         evo_mthd(push, 0x0088, 4);
 333         evo_data(push, evo->sem.offset);
 334         evo_data(push, 0xf00d0000 | evo->sem.value);
 335         evo_data(push, 0x74b1e000);
 336         evo_data(push, NvEvoSync);
 337         evo_mthd(push, 0x00a0, 2);
 338         evo_data(push, 0x00000000);
 339         evo_data(push, 0x00000000);
 340         evo_mthd(push, 0x00c0, 1);
 341         evo_data(push, nv_fb->r_dma);
 342         evo_mthd(push, 0x0110, 2);
 343         evo_data(push, 0x00000000);
 344         evo_data(push, 0x00000000);
 345         evo_mthd(push, 0x0400, 5);
 346         evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 347         evo_data(push, 0);
 348         evo_data(push, (fb->height << 16) | fb->width);
 349         evo_data(push, nv_fb->r_pitch);
 350         evo_data(push, nv_fb->r_format);
 351         evo_mthd(push, 0x0080, 1);
 352         evo_data(push, 0x00000000);
 353         evo_kick(push, crtc->dev, evo->idx);
 354
 355         evo->sem.offset ^= 0x10;
 356         evo->sem.value++;
 357         return 0;
 358 }
 359
 360 /******************************************************************************
 361  * CRTC
 362  *****************************************************************************/
 363 static int
 364 nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 365 {
 366         struct drm_nouveau_private *dev_priv = nv_crtc->base.dev->dev_private;
 367         struct drm_device *dev = nv_crtc->base.dev;
 368         struct nouveau_connector *nv_connector;
 369         struct drm_connector *connector;
 370         u32 *push, mode = 0x00;
 371         u32 mthd;
 372
 373         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 374         connector = &nv_connector->base;
 375         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 376                 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
 377                         mode = DITHERING_MODE_DYNAMIC2X2;
 378         } else {
 379                 mode = nv_connector->dithering_mode;
 380         }
 381
 382         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 383                 if (connector->display_info.bpc >= 8)
 384                         mode |= DITHERING_DEPTH_8BPC;
 385         } else {
 386                 mode |= nv_connector->dithering_depth;
 387         }
 388
 389         if (dev_priv->card_type < NV_E0)
 390                 mthd = 0x0490 + (nv_crtc->index * 0x0300);
 391         else
 392                 mthd = 0x04a0 + (nv_crtc->index * 0x0300);
 393
 394         push = evo_wait(dev, EVO_MASTER, 4);
 395         if (push) {
 396                 evo_mthd(push, mthd, 1);
 397                 evo_data(push, mode);
 398                 if (update) {
 399                         evo_mthd(push, 0x0080, 1);
 400                         evo_data(push, 0x00000000);
 401                 }
 402                 evo_kick(push, dev, EVO_MASTER);
 403         }
 404
 405         return 0;
 406 }
 407
 408 static int
 409 nvd0_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 410 {
 411         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 412         struct drm_device *dev = nv_crtc->base.dev;
 413         struct drm_crtc *crtc = &nv_crtc->base;
 414         struct nouveau_connector *nv_connector;
 415         int mode = DRM_MODE_SCALE_NONE;
 416         u32 oX, oY, *push;
 417
 418         /* start off at the resolution we programmed the crtc for, this
 419          * effectively handles NONE/FULL scaling
 420          */
 421         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 422         if (nv_connector && nv_connector->native_mode)
 423                 mode = nv_connector->scaling_mode;
 424
 425         if (mode != DRM_MODE_SCALE_NONE)
 426                 omode = nv_connector->native_mode;
 427         else
 428                 omode = umode;
 429
 430         oX = omode->hdisplay;
 431         oY = omode->vdisplay;
 432         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 433                 oY *= 2;
 434
 435         /* add overscan compensation if necessary, will keep the aspect
 436          * ratio the same as the backend mode unless overridden by the
 437          * user setting both hborder and vborder properties.
 438          */
 439         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 440                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 441                               nv_connector->edid &&
 442                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 443                 u32 bX = nv_connector->underscan_hborder;
 444                 u32 bY = nv_connector->underscan_vborder;
 445                 u32 aspect = (oY << 19) / oX;
 446
 447                 if (bX) {
 448                         oX -= (bX * 2);
 449                         if (bY) oY -= (bY * 2);
 450                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 451                 } else {
 452                         oX -= (oX >> 4) + 32;
 453                         if (bY) oY -= (bY * 2);
 454                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 455                 }
 456         }
 457
 458         /* handle CENTER/ASPECT scaling, taking into account the areas
 459          * removed already for overscan compensation
 460          */
 461         switch (mode) {
 462         case DRM_MODE_SCALE_CENTER:
 463                 oX = min((u32)umode->hdisplay, oX);
 464                 oY = min((u32)umode->vdisplay, oY);
 465                 /* fall-through */
 466         case DRM_MODE_SCALE_ASPECT:
 467                 if (oY < oX) {
 468                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 469                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 470                 } else {
 471                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 472                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 473                 }
 474                 break;
 475         default:
 476                 break;
 477         }
 478
 479         push = evo_wait(dev, EVO_MASTER, 8);
 480         if (push) {
 481                 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 482                 evo_data(push, (oY << 16) | oX);
 483                 evo_data(push, (oY << 16) | oX);
 484                 evo_data(push, (oY << 16) | oX);
 485                 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 486                 evo_data(push, 0x00000000);
 487                 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 488                 evo_data(push, (umode->vdisplay << 16) | umode->hdisplay);
 489                 evo_kick(push, dev, EVO_MASTER);
 490                 if (update) {
 491                         nvd0_display_flip_stop(crtc);
 492                         nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
 493                 }
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int
 500 nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 501                     int x, int y, bool update)
 502 {
 503         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 504         u32 *push;
 505
 506         push = evo_wait(fb->dev, EVO_MASTER, 16);
 507         if (push) {
 508                 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 509                 evo_data(push, nvfb->nvbo->bo.offset >> 8);
 510                 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 511                 evo_data(push, (fb->height << 16) | fb->width);
 512                 evo_data(push, nvfb->r_pitch);
 513                 evo_data(push, nvfb->r_format);
 514                 evo_data(push, nvfb->r_dma);
 515                 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 516                 evo_data(push, (y << 16) | x);
 517                 if (update) {
 518                         evo_mthd(push, 0x0080, 1);
 519                         evo_data(push, 0x00000000);
 520                 }
 521                 evo_kick(push, fb->dev, EVO_MASTER);
 522         }
 523
 524         nv_crtc->fb.tile_flags = nvfb->r_dma;
 525         return 0;
 526 }
 527
 528 static void
 529 nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
 530 {
 531         struct drm_device *dev = nv_crtc->base.dev;
 532         u32 *push = evo_wait(dev, EVO_MASTER, 16);
 533         if (push) {
 534                 if (show) {
 535                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 536                         evo_data(push, 0x85000000);
 537                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 538                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 539                         evo_data(push, NvEvoVRAM);
 540                 } else {
 541                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 542                         evo_data(push, 0x05000000);
 543                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 544                         evo_data(push, 0x00000000);
 545                 }
 546
 547                 if (update) {
 548                         evo_mthd(push, 0x0080, 1);
 549                         evo_data(push, 0x00000000);
 550                 }
 551
 552                 evo_kick(push, dev, EVO_MASTER);
 553         }
 554 }
 555
 556 static void
 557 nvd0_crtc_dpms(struct drm_crtc *crtc, int mode)
 558 {
 559 }
 560
 561 static void
 562 nvd0_crtc_prepare(struct drm_crtc *crtc)
 563 {
 564         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 565         u32 *push;
 566
 567         nvd0_display_flip_stop(crtc);
 568
 569         push = evo_wait(crtc->dev, EVO_MASTER, 2);
 570         if (push) {
 571                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 572                 evo_data(push, 0x00000000);
 573                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 574                 evo_data(push, 0x03000000);
 575                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 576                 evo_data(push, 0x00000000);
 577                 evo_kick(push, crtc->dev, EVO_MASTER);
 578         }
 579
 580         nvd0_crtc_cursor_show(nv_crtc, false, false);
 581 }
 582
 583 static void
 584 nvd0_crtc_commit(struct drm_crtc *crtc)
 585 {
 586         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 587         u32 *push;
 588
 589         push = evo_wait(crtc->dev, EVO_MASTER, 32);
 590         if (push) {
 591                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 592                 evo_data(push, nv_crtc->fb.tile_flags);
 593                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
 594                 evo_data(push, 0x83000000);
 595                 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 596                 evo_data(push, 0x00000000);
 597                 evo_data(push, 0x00000000);
 598                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 599                 evo_data(push, NvEvoVRAM);
 600                 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
 601                 evo_data(push, 0xffffff00);
 602                 evo_kick(push, crtc->dev, EVO_MASTER);
 603         }
 604
 605         nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true);
 606         nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
 607 }
 608
 609 static bool
 610 nvd0_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
 611                      struct drm_display_mode *adjusted_mode)
 612 {
 613         return true;
 614 }
 615
 616 static int
 617 nvd0_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
 618 {
 619         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
 620         int ret;
 621
 622         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
 623         if (ret)
 624                 return ret;
 625
 626         if (old_fb) {
 627                 nvfb = nouveau_framebuffer(old_fb);
 628                 nouveau_bo_unpin(nvfb->nvbo);
 629         }
 630
 631         return 0;
 632 }
 633
 634 static int
 635 nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
 636                    struct drm_display_mode *mode, int x, int y,
 637                    struct drm_framebuffer *old_fb)
 638 {
 639         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 640         struct nouveau_connector *nv_connector;
 641         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
 642         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
 643         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
 644         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
 645         u32 vblan2e = 0, vblan2s = 1;
 646         u32 *push;
 647         int ret;
 648
 649         hactive = mode->htotal;
 650         hsynce  = mode->hsync_end - mode->hsync_start - 1;
 651         hbackp  = mode->htotal - mode->hsync_end;
 652         hblanke = hsynce + hbackp;
 653         hfrontp = mode->hsync_start - mode->hdisplay;
 654         hblanks = mode->htotal - hfrontp - 1;
 655
 656         vactive = mode->vtotal * vscan / ilace;
 657         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
 658         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
 659         vblanke = vsynce + vbackp;
 660         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
 661         vblanks = vactive - vfrontp - 1;
 662         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 663                 vblan2e = vactive + vsynce + vbackp;
 664                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
 665                 vactive = (vactive * 2) + 1;
 666         }
 667
 668         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 669         if (ret)
 670                 return ret;
 671
 672         push = evo_wait(crtc->dev, EVO_MASTER, 64);
 673         if (push) {
 674                 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
 675                 evo_data(push, 0x00000000);
 676                 evo_data(push, (vactive << 16) | hactive);
 677                 evo_data(push, ( vsynce << 16) | hsynce);
 678                 evo_data(push, (vblanke << 16) | hblanke);
 679                 evo_data(push, (vblanks << 16) | hblanks);
 680                 evo_data(push, (vblan2e << 16) | vblan2s);
 681                 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
 682                 evo_data(push, 0x00000000); /* ??? */
 683                 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
 684                 evo_data(push, mode->clock * 1000);
 685                 evo_data(push, 0x00200000); /* ??? */
 686                 evo_data(push, mode->clock * 1000);
 687                 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
 688                 evo_data(push, 0x00000311);
 689                 evo_data(push, 0x00000100);
 690                 evo_kick(push, crtc->dev, EVO_MASTER);
 691         }
 692
 693         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 694         nvd0_crtc_set_dither(nv_crtc, false);
 695         nvd0_crtc_set_scale(nv_crtc, false);
 696         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
 697         return 0;
 698 }
 699
 700 static int
 701 nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 702                         struct drm_framebuffer *old_fb)
 703 {
 704         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 705         int ret;
 706
 707         if (!crtc->fb) {
 708                 NV_DEBUG_KMS(crtc->dev, "No FB bound\n");
 709                 return 0;
 710         }
 711
 712         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 713         if (ret)
 714                 return ret;
 715
 716         nvd0_display_flip_stop(crtc);
 717         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
 718         nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
 719         return 0;
 720 }
 721
 722 static int
 723 nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
 724                                struct drm_framebuffer *fb, int x, int y,
 725                                enum mode_set_atomic state)
 726 {
 727         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 728         nvd0_display_flip_stop(crtc);
 729         nvd0_crtc_set_image(nv_crtc, fb, x, y, true);
 730         return 0;
 731 }
 732
 733 static void
 734 nvd0_crtc_lut_load(struct drm_crtc *crtc)
 735 {
 736         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 737         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
 738         int i;
 739
 740         for (i = 0; i < 256; i++) {
 741                 writew(0x6000 + (nv_crtc->lut.r[i] >> 2), lut + (i * 0x20) + 0);
 742                 writew(0x6000 + (nv_crtc->lut.g[i] >> 2), lut + (i * 0x20) + 2);
 743                 writew(0x6000 + (nv_crtc->lut.b[i] >> 2), lut + (i * 0x20) + 4);
 744         }
 745 }
 746
 747 static int
 748 nvd0_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 749                      uint32_t handle, uint32_t width, uint32_t height)
 750 {
 751         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 752         struct drm_device *dev = crtc->dev;
 753         struct drm_gem_object *gem;
 754         struct nouveau_bo *nvbo;
 755         bool visible = (handle != 0);
 756         int i, ret = 0;
 757
 758         if (visible) {
 759                 if (width != 64 || height != 64)
 760                         return -EINVAL;
 761
 762                 gem = drm_gem_object_lookup(dev, file_priv, handle);
 763                 if (unlikely(!gem))
 764                         return -ENOENT;
 765                 nvbo = nouveau_gem_object(gem);
 766
 767                 ret = nouveau_bo_map(nvbo);
 768                 if (ret == 0) {
 769                         for (i = 0; i < 64 * 64; i++) {
 770                                 u32 v = nouveau_bo_rd32(nvbo, i);
 771                                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
 772                         }
 773                         nouveau_bo_unmap(nvbo);
 774                 }
 775
 776                 drm_gem_object_unreference_unlocked(gem);
 777         }
 778
 779         if (visible != nv_crtc->cursor.visible) {
 780                 nvd0_crtc_cursor_show(nv_crtc, visible, true);
 781                 nv_crtc->cursor.visible = visible;
 782         }
 783
 784         return ret;
 785 }
 786
 787 static int
 788 nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 789 {
 790         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 791         int ch = EVO_CURS(nv_crtc->index);
 792
 793         evo_piow(crtc->dev, ch, 0x0084, (y << 16) | (x & 0xffff));
 794         evo_piow(crtc->dev, ch, 0x0080, 0x00000000);
 795         return 0;
 796 }
 797
 798 static void
 799 nvd0_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 800                     uint32_t start, uint32_t size)
 801 {
 802         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 803         u32 end = max(start + size, (u32)256);
 804         u32 i;
 805
 806         for (i = start; i < end; i++) {
 807                 nv_crtc->lut.r[i] = r[i];
 808                 nv_crtc->lut.g[i] = g[i];
 809                 nv_crtc->lut.b[i] = b[i];
 810         }
 811
 812         nvd0_crtc_lut_load(crtc);
 813 }
 814
 815 static void
 816 nvd0_crtc_destroy(struct drm_crtc *crtc)
 817 {
 818         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 819         nouveau_bo_unmap(nv_crtc->cursor.nvbo);
 820         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 821         nouveau_bo_unmap(nv_crtc->lut.nvbo);
 822         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 823         drm_crtc_cleanup(crtc);
 824         kfree(crtc);
 825 }
 826
 827 static const struct drm_crtc_helper_funcs nvd0_crtc_hfunc = {
 828         .dpms = nvd0_crtc_dpms,
 829         .prepare = nvd0_crtc_prepare,
 830         .commit = nvd0_crtc_commit,
 831         .mode_fixup = nvd0_crtc_mode_fixup,
 832         .mode_set = nvd0_crtc_mode_set,
 833         .mode_set_base = nvd0_crtc_mode_set_base,
 834         .mode_set_base_atomic = nvd0_crtc_mode_set_base_atomic,
 835         .load_lut = nvd0_crtc_lut_load,
 836 };
 837
 838 static const struct drm_crtc_funcs nvd0_crtc_func = {
 839         .cursor_set = nvd0_crtc_cursor_set,
 840         .cursor_move = nvd0_crtc_cursor_move,
 841         .gamma_set = nvd0_crtc_gamma_set,
 842         .set_config = drm_crtc_helper_set_config,
 843         .destroy = nvd0_crtc_destroy,
 844         .page_flip = nouveau_crtc_page_flip,
 845 };
 846
 847 static void
 848 nvd0_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
 849 {
 850 }
 851
 852 static void
 853 nvd0_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
 854 {
 855 }
 856
 857 static int
 858 nvd0_crtc_create(struct drm_device *dev, int index)
 859 {
 860         struct nouveau_crtc *nv_crtc;
 861         struct drm_crtc *crtc;
 862         int ret, i;
 863
 864         nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
 865         if (!nv_crtc)
 866                 return -ENOMEM;
 867
 868         nv_crtc->index = index;
 869         nv_crtc->set_dither = nvd0_crtc_set_dither;
 870         nv_crtc->set_scale = nvd0_crtc_set_scale;
 871         nv_crtc->cursor.set_offset = nvd0_cursor_set_offset;
 872         nv_crtc->cursor.set_pos = nvd0_cursor_set_pos;
 873         for (i = 0; i < 256; i++) {
 874                 nv_crtc->lut.r[i] = i << 8;
 875                 nv_crtc->lut.g[i] = i << 8;
 876                 nv_crtc->lut.b[i] = i << 8;
 877         }
 878
 879         crtc = &nv_crtc->base;
 880         drm_crtc_init(dev, crtc, &nvd0_crtc_func);
 881         drm_crtc_helper_add(crtc, &nvd0_crtc_hfunc);
 882         drm_mode_crtc_set_gamma_size(crtc, 256);
 883
 884         ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
 885                              0, 0x0000, NULL, &nv_crtc->cursor.nvbo);
 886         if (!ret) {
 887                 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
 888                 if (!ret)
 889                         ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
 890                 if (ret)
 891                         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 892         }
 893
 894         if (ret)
 895                 goto out;
 896
 897         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
 898                              0, 0x0000, NULL, &nv_crtc->lut.nvbo);
 899         if (!ret) {
 900                 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
 901                 if (!ret)
 902                         ret = nouveau_bo_map(nv_crtc->lut.nvbo);
 903                 if (ret)
 904                         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 905         }
 906
 907         if (ret)
 908                 goto out;
 909
 910         nvd0_crtc_lut_load(crtc);
 911
 912 out:
 913         if (ret)
 914                 nvd0_crtc_destroy(crtc);
 915         return ret;
 916 }
 917
 918 /******************************************************************************
 919  * DAC
 920  *****************************************************************************/
 921 static void
 922 nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
 923 {
 924         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 925         struct drm_device *dev = encoder->dev;
 926         int or = nv_encoder->or;
 927         u32 dpms_ctrl;
 928
 929         dpms_ctrl = 0x80000000;
 930         if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
 931                 dpms_ctrl |= 0x00000001;
 932         if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
 933                 dpms_ctrl |= 0x00000004;
 934
 935         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 936         nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl);
 937         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 938 }
 939
 940 static bool
 941 nvd0_dac_mode_fixup(struct drm_encoder *encoder,
 942                     const struct drm_display_mode *mode,
 943                     struct drm_display_mode *adjusted_mode)
 944 {
 945         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 946         struct nouveau_connector *nv_connector;
 947
 948         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 949         if (nv_connector && nv_connector->native_mode) {
 950                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 951                         int id = adjusted_mode->base.id;
 952                         *adjusted_mode = *nv_connector->native_mode;
 953                         adjusted_mode->base.id = id;
 954                 }
 955         }
 956
 957         return true;
 958 }
 959
 960 static void
 961 nvd0_dac_commit(struct drm_encoder *encoder)
 962 {
 963 }
 964
 965 static void
 966 nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 967                   struct drm_display_mode *adjusted_mode)
 968 {
 969         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 970         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 971         u32 syncs, magic, *push;
 972
 973         syncs = 0x00000001;
 974         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 975                 syncs |= 0x00000008;
 976         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 977                 syncs |= 0x00000010;
 978
 979         magic = 0x31ec6000 | (nv_crtc->index << 25);
 980         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 981                 magic |= 0x00000001;
 982
 983         nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 984
 985         push = evo_wait(encoder->dev, EVO_MASTER, 8);
 986         if (push) {
 987                 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
 988                 evo_data(push, syncs);
 989                 evo_data(push, magic);
 990                 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 2);
 991                 evo_data(push, 1 << nv_crtc->index);
 992                 evo_data(push, 0x00ff);
 993                 evo_kick(push, encoder->dev, EVO_MASTER);
 994         }
 995
 996         nv_encoder->crtc = encoder->crtc;
 997 }
 998
 999 static void
1000 nvd0_dac_disconnect(struct drm_encoder *encoder)
1001 {
1002         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1003         struct drm_device *dev = encoder->dev;
1004         u32 *push;
1005
1006         if (nv_encoder->crtc) {
1007                 nvd0_crtc_prepare(nv_encoder->crtc);
1008
1009                 push = evo_wait(dev, EVO_MASTER, 4);
1010                 if (push) {
1011                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1);
1012                         evo_data(push, 0x00000000);
1013                         evo_mthd(push, 0x0080, 1);
1014                         evo_data(push, 0x00000000);
1015                         evo_kick(push, dev, EVO_MASTER);
1016                 }
1017
1018                 nv_encoder->crtc = NULL;
1019         }
1020 }
1021
1022 static enum drm_connector_status
1023 nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1024 {
1025         enum drm_connector_status status = connector_status_disconnected;
1026         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1027         struct drm_device *dev = encoder->dev;
1028         int or = nv_encoder->or;
1029         u32 load;
1030
1031         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00100000);
1032         udelay(9500);
1033         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x80000000);
1034
1035         load = nv_rd32(dev, 0x61a00c + (or * 0x800));
1036         if ((load & 0x38000000) == 0x38000000)
1037                 status = connector_status_connected;
1038
1039         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00000000);
1040         return status;
1041 }
1042
1043 static void
1044 nvd0_dac_destroy(struct drm_encoder *encoder)
1045 {
1046         drm_encoder_cleanup(encoder);
1047         kfree(encoder);
1048 }
1049
1050 static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = {
1051         .dpms = nvd0_dac_dpms,
1052         .mode_fixup = nvd0_dac_mode_fixup,
1053         .prepare = nvd0_dac_disconnect,
1054         .commit = nvd0_dac_commit,
1055         .mode_set = nvd0_dac_mode_set,
1056         .disable = nvd0_dac_disconnect,
1057         .get_crtc = nvd0_display_crtc_get,
1058         .detect = nvd0_dac_detect
1059 };
1060
1061 static const struct drm_encoder_funcs nvd0_dac_func = {
1062         .destroy = nvd0_dac_destroy,
1063 };
1064
1065 static int
1066 nvd0_dac_create(struct drm_connector *connector, struct dcb_entry *dcbe)
1067 {
1068         struct drm_device *dev = connector->dev;
1069         struct nouveau_encoder *nv_encoder;
1070         struct drm_encoder *encoder;
1071
1072         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1073         if (!nv_encoder)
1074                 return -ENOMEM;
1075         nv_encoder->dcb = dcbe;
1076         nv_encoder->or = ffs(dcbe->or) - 1;
1077
1078         encoder = to_drm_encoder(nv_encoder);
1079         encoder->possible_crtcs = dcbe->heads;
1080         encoder->possible_clones = 0;
1081         drm_encoder_init(dev, encoder, &nvd0_dac_func, DRM_MODE_ENCODER_DAC);
1082         drm_encoder_helper_add(encoder, &nvd0_dac_hfunc);
1083
1084         drm_mode_connector_attach_encoder(connector, encoder);
1085         return 0;
1086 }
1087
1088 /******************************************************************************
1089  * Audio
1090  *****************************************************************************/
1091 static void
1092 nvd0_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1093 {
1094         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1095         struct nouveau_connector *nv_connector;
1096         struct drm_device *dev = encoder->dev;
1097         int i, or = nv_encoder->or * 0x30;
1098
1099         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1100         if (!drm_detect_monitor_audio(nv_connector->edid))
1101                 return;
1102
1103         nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000001);
1104
1105         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1106         if (nv_connector->base.eld[0]) {
1107                 u8 *eld = nv_connector->base.eld;
1108
1109                 for (i = 0; i < eld[2] * 4; i++)
1110                         nv_wr32(dev, 0x10ec00 + or, (i << 8) | eld[i]);
1111                 for (i = eld[2] * 4; i < 0x60; i++)
1112                         nv_wr32(dev, 0x10ec00 + or, (i << 8) | 0x00);
1113
1114                 nv_mask(dev, 0x10ec10 + or, 0x80000002, 0x80000002);
1115         }
1116 }
1117
1118 static void
1119 nvd0_audio_disconnect(struct drm_encoder *encoder)
1120 {
1121         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1122         struct drm_device *dev = encoder->dev;
1123         int or = nv_encoder->or * 0x30;
1124
1125         nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000000);
1126 }
1127
1128 /******************************************************************************
1129  * HDMI
1130  *****************************************************************************/
1131 static void
1132 nvd0_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1133 {
1134         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1135         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1136         struct nouveau_connector *nv_connector;
1137         struct drm_device *dev = encoder->dev;
1138         int head = nv_crtc->index * 0x800;
1139         u32 rekey = 56; /* binary driver, and tegra constant */
1140         u32 max_ac_packet;
1141
1142         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1143         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1144                 return;
1145
1146         max_ac_packet  = mode->htotal - mode->hdisplay;
1147         max_ac_packet -= rekey;
1148         max_ac_packet -= 18; /* constant from tegra */
1149         max_ac_packet /= 32;
1150
1151         /* AVI InfoFrame */
1152         nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000);
1153         nv_wr32(dev, 0x61671c + head, 0x000d0282);
1154         nv_wr32(dev, 0x616720 + head, 0x0000006f);
1155         nv_wr32(dev, 0x616724 + head, 0x00000000);
1156         nv_wr32(dev, 0x616728 + head, 0x00000000);
1157         nv_wr32(dev, 0x61672c + head, 0x00000000);
1158         nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000001);
1159
1160         /* ??? InfoFrame? */
1161         nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000);
1162         nv_wr32(dev, 0x6167ac + head, 0x00000010);
1163         nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000001);
1164
1165         /* HDMI_CTRL */
1166         nv_mask(dev, 0x616798 + head, 0x401f007f, 0x40000000 | rekey |
1167                                                   max_ac_packet << 16);
1168
1169         /* NFI, audio doesn't work without it though.. */
1170         nv_mask(dev, 0x616548 + head, 0x00000070, 0x00000000);
1171
1172         nvd0_audio_mode_set(encoder, mode);
1173 }
1174
1175 static void
1176 nvd0_hdmi_disconnect(struct drm_encoder *encoder)
1177 {
1178         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1179         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1180         struct drm_device *dev = encoder->dev;
1181         int head = nv_crtc->index * 0x800;
1182
1183         nvd0_audio_disconnect(encoder);
1184
1185         nv_mask(dev, 0x616798 + head, 0x40000000, 0x00000000);
1186         nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000);
1187         nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000);
1188 }
1189
1190 /******************************************************************************
1191  * SOR
1192  *****************************************************************************/
1193 static inline u32
1194 nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane)
1195 {
1196         static const u8 nvd0[] = { 16, 8, 0, 24 };
1197         return nvd0[lane];
1198 }
1199
1200 static void
1201 nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_entry *dcb, u8 pattern)
1202 {
1203         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1204         const u32 loff = (or * 0x800) + (link * 0x80);
1205         nv_mask(dev, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
1206 }
1207
1208 static void
1209 nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb,
1210                       u8 lane, u8 swing, u8 preem)
1211 {
1212         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1213         const u32 loff = (or * 0x800) + (link * 0x80);
1214         u32 shift = nvd0_sor_dp_lane_map(dev, dcb, lane);
1215         u32 mask = 0x000000ff << shift;
1216         u8 *table, *entry, *config = NULL;
1217
1218         switch (swing) {
1219         case 0: preem += 0; break;
1220         case 1: preem += 4; break;
1221         case 2: preem += 7; break;
1222         case 3: preem += 9; break;
1223         }
1224
1225         table = nouveau_dp_bios_data(dev, dcb, &entry);
1226         if (table) {
1227                 if (table[0] == 0x30) {
1228                         config  = entry + table[4];
1229                         config += table[5] * preem;
1230                 } else
1231                 if (table[0] == 0x40) {
1232                         config  = table + table[1];
1233                         config += table[2] * table[3];
1234                         config += table[6] * preem;
1235                 }
1236         }
1237
1238         if (!config) {
1239                 NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
1240                 return;
1241         }
1242
1243         nv_mask(dev, 0x61c118 + loff, mask, config[1] << shift);
1244         nv_mask(dev, 0x61c120 + loff, mask, config[2] << shift);
1245         nv_mask(dev, 0x61c130 + loff, 0x0000ff00, config[3] << 8);
1246         nv_mask(dev, 0x61c13c + loff, 0x00000000, 0x00000000);
1247 }
1248
1249 static void
1250 nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_entry *dcb, int crtc,
1251                      int link_nr, u32 link_bw, bool enhframe)
1252 {
1253         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1254         const u32 loff = (or * 0x800) + (link * 0x80);
1255         const u32 soff = (or * 0x800);
1256         u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & ~0x001f4000;
1257         u32 clksor = nv_rd32(dev, 0x612300 + soff) & ~0x007c0000;
1258         u32 script = 0x0000, lane_mask = 0;
1259         u8 *table, *entry;
1260         int i;
1261
1262         link_bw /= 27000;
1263
1264         table = nouveau_dp_bios_data(dev, dcb, &entry);
1265         if (table) {
1266                 if      (table[0] == 0x30) entry = ROMPTR(dev, entry[10]);
1267                 else if (table[0] == 0x40) entry = ROMPTR(dev, entry[9]);
1268                 else                       entry = NULL;
1269
1270                 while (entry) {
1271                         if (entry[0] >= link_bw)
1272                                 break;
1273                         entry += 3;
1274                 }
1275
1276                 nouveau_bios_run_init_table(dev, script, dcb, crtc);
1277         }
1278
1279         clksor |= link_bw << 18;
1280         dpctrl |= ((1 << link_nr) - 1) << 16;
1281         if (enhframe)
1282                 dpctrl |= 0x00004000;
1283
1284         for (i = 0; i < link_nr; i++)
1285                 lane_mask |= 1 << (nvd0_sor_dp_lane_map(dev, dcb, i) >> 3);
1286
1287         nv_wr32(dev, 0x612300 + soff, clksor);
1288         nv_wr32(dev, 0x61c10c + loff, dpctrl);
1289         nv_mask(dev, 0x61c130 + loff, 0x0000000f, lane_mask);
1290 }
1291
1292 static void
1293 nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_entry *dcb,
1294                      u32 *link_nr, u32 *link_bw)
1295 {
1296         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1297         const u32 loff = (or * 0x800) + (link * 0x80);
1298         const u32 soff = (or * 0x800);
1299         u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & 0x000f0000;
1300         u32 clksor = nv_rd32(dev, 0x612300 + soff);
1301
1302         if      (dpctrl > 0x00030000) *link_nr = 4;
1303         else if (dpctrl > 0x00010000) *link_nr = 2;
1304         else                          *link_nr = 1;
1305
1306         *link_bw  = (clksor & 0x007c0000) >> 18;
1307         *link_bw *= 27000;
1308 }
1309
1310 static void
1311 nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_entry *dcb,
1312                     u32 crtc, u32 datarate)
1313 {
1314         const u32 symbol = 100000;
1315         const u32 TU = 64;
1316         u32 link_nr, link_bw;
1317         u64 ratio, value;
1318
1319         nvd0_sor_dp_link_get(dev, dcb, &link_nr, &link_bw);
1320
1321         ratio  = datarate;
1322         ratio *= symbol;
1323         do_div(ratio, link_nr * link_bw);
1324
1325         value  = (symbol - ratio) * TU;
1326         value *= ratio;
1327         do_div(value, symbol);
1328         do_div(value, symbol);
1329
1330         value += 5;
1331         value |= 0x08000000;
1332
1333         nv_wr32(dev, 0x616610 + (crtc * 0x800), value);
1334 }
1335
1336 static void
1337 nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
1338 {
1339         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1340         struct drm_device *dev = encoder->dev;
1341         struct drm_encoder *partner;
1342         int or = nv_encoder->or;
1343         u32 dpms_ctrl;
1344
1345         nv_encoder->last_dpms = mode;
1346
1347         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1348                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1349
1350                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1351                         continue;
1352
1353                 if (nv_partner != nv_encoder &&
1354                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1355                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1356                                 return;
1357                         break;
1358                 }
1359         }
1360
1361         dpms_ctrl  = (mode == DRM_MODE_DPMS_ON);
1362         dpms_ctrl |= 0x80000000;
1363
1364         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1365         nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
1366         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1367         nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
1368
1369         if (nv_encoder->dcb->type == OUTPUT_DP) {
1370                 struct dp_train_func func = {
1371                         .link_set = nvd0_sor_dp_link_set,
1372                         .train_set = nvd0_sor_dp_train_set,
1373                         .train_adj = nvd0_sor_dp_train_adj
1374                 };
1375
1376                 nouveau_dp_dpms(encoder, mode, nv_encoder->dp.datarate, &func);
1377         }
1378 }
1379
1380 static bool
1381 nvd0_sor_mode_fixup(struct drm_encoder *encoder,
1382                     const struct drm_display_mode *mode,
1383                     struct drm_display_mode *adjusted_mode)
1384 {
1385         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1386         struct nouveau_connector *nv_connector;
1387
1388         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1389         if (nv_connector && nv_connector->native_mode) {
1390                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1391                         int id = adjusted_mode->base.id;
1392                         *adjusted_mode = *nv_connector->native_mode;
1393                         adjusted_mode->base.id = id;
1394                 }
1395         }
1396
1397         return true;
1398 }
1399
1400 static void
1401 nvd0_sor_disconnect(struct drm_encoder *encoder)
1402 {
1403         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1404         struct drm_device *dev = encoder->dev;
1405         u32 *push;
1406
1407         if (nv_encoder->crtc) {
1408                 nvd0_crtc_prepare(nv_encoder->crtc);
1409
1410                 push = evo_wait(dev, EVO_MASTER, 4);
1411                 if (push) {
1412                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1413                         evo_data(push, 0x00000000);
1414                         evo_mthd(push, 0x0080, 1);
1415                         evo_data(push, 0x00000000);
1416                         evo_kick(push, dev, EVO_MASTER);
1417                 }
1418
1419                 nvd0_hdmi_disconnect(encoder);
1420
1421                 nv_encoder->crtc = NULL;
1422                 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1423         }
1424 }
1425
1426 static void
1427 nvd0_sor_prepare(struct drm_encoder *encoder)
1428 {
1429         nvd0_sor_disconnect(encoder);
1430         if (nouveau_encoder(encoder)->dcb->type == OUTPUT_DP)
1431                 evo_sync(encoder->dev, EVO_MASTER);
1432 }
1433
1434 static void
1435 nvd0_sor_commit(struct drm_encoder *encoder)
1436 {
1437 }
1438
1439 static void
1440 nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1441                   struct drm_display_mode *mode)
1442 {
1443         struct drm_device *dev = encoder->dev;
1444         struct drm_nouveau_private *dev_priv = dev->dev_private;
1445         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1446         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1447         struct nouveau_connector *nv_connector;
1448         struct nvbios *bios = &dev_priv->vbios;
1449         u32 mode_ctrl = (1 << nv_crtc->index);
1450         u32 syncs, magic, *push;
1451         u32 or_config;
1452
1453         syncs = 0x00000001;
1454         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1455                 syncs |= 0x00000008;
1456         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1457                 syncs |= 0x00000010;
1458
1459         magic = 0x31ec6000 | (nv_crtc->index << 25);
1460         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1461                 magic |= 0x00000001;
1462
1463         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1464         switch (nv_encoder->dcb->type) {
1465         case OUTPUT_TMDS:
1466                 if (nv_encoder->dcb->sorconf.link & 1) {
1467                         if (mode->clock < 165000)
1468                                 mode_ctrl |= 0x00000100;
1469                         else
1470                                 mode_ctrl |= 0x00000500;
1471                 } else {
1472                         mode_ctrl |= 0x00000200;
1473                 }
1474
1475                 or_config = (mode_ctrl & 0x00000f00) >> 8;
1476                 if (mode->clock >= 165000)
1477                         or_config |= 0x0100;
1478
1479                 nvd0_hdmi_mode_set(encoder, mode);
1480                 break;
1481         case OUTPUT_LVDS:
1482                 or_config = (mode_ctrl & 0x00000f00) >> 8;
1483                 if (bios->fp_no_ddc) {
1484                         if (bios->fp.dual_link)
1485                                 or_config |= 0x0100;
1486                         if (bios->fp.if_is_24bit)
1487                                 or_config |= 0x0200;
1488                 } else {
1489                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1490                                 if (((u8 *)nv_connector->edid)[121] == 2)
1491                                         or_config |= 0x0100;
1492                         } else
1493                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1494                                 or_config |= 0x0100;
1495                         }
1496
1497                         if (or_config & 0x0100) {
1498                                 if (bios->fp.strapless_is_24bit & 2)
1499                                         or_config |= 0x0200;
1500                         } else {
1501                                 if (bios->fp.strapless_is_24bit & 1)
1502                                         or_config |= 0x0200;
1503                         }
1504
1505                         if (nv_connector->base.display_info.bpc == 8)
1506                                 or_config |= 0x0200;
1507
1508                 }
1509                 break;
1510         case OUTPUT_DP:
1511                 if (nv_connector->base.display_info.bpc == 6) {
1512                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
1513                         syncs |= 0x00000140;
1514                 } else {
1515                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
1516                         syncs |= 0x00000180;
1517                 }
1518
1519                 if (nv_encoder->dcb->sorconf.link & 1)
1520                         mode_ctrl |= 0x00000800;
1521                 else
1522                         mode_ctrl |= 0x00000900;
1523
1524                 or_config = (mode_ctrl & 0x00000f00) >> 8;
1525                 break;
1526         default:
1527                 BUG_ON(1);
1528                 break;
1529         }
1530
1531         nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1532
1533         if (nv_encoder->dcb->type == OUTPUT_DP) {
1534                 nvd0_sor_dp_calc_tu(dev, nv_encoder->dcb, nv_crtc->index,
1535                                          nv_encoder->dp.datarate);
1536         }
1537
1538         push = evo_wait(dev, EVO_MASTER, 8);
1539         if (push) {
1540                 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1541                 evo_data(push, syncs);
1542                 evo_data(push, magic);
1543                 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 2);
1544                 evo_data(push, mode_ctrl);
1545                 evo_data(push, or_config);
1546                 evo_kick(push, dev, EVO_MASTER);
1547         }
1548
1549         nv_encoder->crtc = encoder->crtc;
1550 }
1551
1552 static void
1553 nvd0_sor_destroy(struct drm_encoder *encoder)
1554 {
1555         drm_encoder_cleanup(encoder);
1556         kfree(encoder);
1557 }
1558
1559 static const struct drm_encoder_helper_funcs nvd0_sor_hfunc = {
1560         .dpms = nvd0_sor_dpms,
1561         .mode_fixup = nvd0_sor_mode_fixup,
1562         .prepare = nvd0_sor_prepare,
1563         .commit = nvd0_sor_commit,
1564         .mode_set = nvd0_sor_mode_set,
1565         .disable = nvd0_sor_disconnect,
1566         .get_crtc = nvd0_display_crtc_get,
1567 };
1568
1569 static const struct drm_encoder_funcs nvd0_sor_func = {
1570         .destroy = nvd0_sor_destroy,
1571 };
1572
1573 static int
1574 nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe)
1575 {
1576         struct drm_device *dev = connector->dev;
1577         struct nouveau_encoder *nv_encoder;
1578         struct drm_encoder *encoder;
1579
1580         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1581         if (!nv_encoder)
1582                 return -ENOMEM;
1583         nv_encoder->dcb = dcbe;
1584         nv_encoder->or = ffs(dcbe->or) - 1;
1585         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1586
1587         encoder = to_drm_encoder(nv_encoder);
1588         encoder->possible_crtcs = dcbe->heads;
1589         encoder->possible_clones = 0;
1590         drm_encoder_init(dev, encoder, &nvd0_sor_func, DRM_MODE_ENCODER_TMDS);
1591         drm_encoder_helper_add(encoder, &nvd0_sor_hfunc);
1592
1593         drm_mode_connector_attach_encoder(connector, encoder);
1594         return 0;
1595 }
1596
1597 /******************************************************************************
1598  * IRQ
1599  *****************************************************************************/
1600 static struct dcb_entry *
1601 lookup_dcb(struct drm_device *dev, int id, u32 mc)
1602 {
1603         struct drm_nouveau_private *dev_priv = dev->dev_private;
1604         int type, or, i, link = -1;
1605
1606         if (id < 4) {
1607                 type = OUTPUT_ANALOG;
1608                 or   = id;
1609         } else {
1610                 switch (mc & 0x00000f00) {
1611                 case 0x00000000: link = 0; type = OUTPUT_LVDS; break;
1612                 case 0x00000100: link = 0; type = OUTPUT_TMDS; break;
1613                 case 0x00000200: link = 1; type = OUTPUT_TMDS; break;
1614                 case 0x00000500: link = 0; type = OUTPUT_TMDS; break;
1615                 case 0x00000800: link = 0; type = OUTPUT_DP; break;
1616                 case 0x00000900: link = 1; type = OUTPUT_DP; break;
1617                 default:
1618                         NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc);
1619                         return NULL;
1620                 }
1621
1622                 or = id - 4;
1623         }
1624
1625         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
1626                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
1627                 if (dcb->type == type && (dcb->or & (1 << or)) &&
1628                     (link < 0 || link == !(dcb->sorconf.link & 1)))
1629                         return dcb;
1630         }
1631
1632         NV_ERROR(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc);
1633         return NULL;
1634 }
1635
1636 static void
1637 nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
1638 {
1639         struct dcb_entry *dcb;
1640         int i;
1641
1642         for (i = 0; mask && i < 8; i++) {
1643                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1644                 if (!(mcc & (1 << crtc)))
1645                         continue;
1646
1647                 dcb = lookup_dcb(dev, i, mcc);
1648                 if (!dcb)
1649                         continue;
1650
1651                 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc);
1652         }
1653
1654         nv_wr32(dev, 0x6101d4, 0x00000000);
1655         nv_wr32(dev, 0x6109d4, 0x00000000);
1656         nv_wr32(dev, 0x6101d0, 0x80000000);
1657 }
1658
1659 static void
1660 nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1661 {
1662         struct dcb_entry *dcb;
1663         u32 or, tmp, pclk;
1664         int i;
1665
1666         for (i = 0; mask && i < 8; i++) {
1667                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1668                 if (!(mcc & (1 << crtc)))
1669                         continue;
1670
1671                 dcb = lookup_dcb(dev, i, mcc);
1672                 if (!dcb)
1673                         continue;
1674
1675                 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc);
1676         }
1677
1678         pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1679         NV_DEBUG_KMS(dev, "PDISP: crtc %d pclk %d mask 0x%08x\n",
1680                           crtc, pclk, mask);
1681         if (pclk && (mask & 0x00010000)) {
1682                 nv50_crtc_set_clock(dev, crtc, pclk);
1683         }
1684
1685         for (i = 0; mask && i < 8; i++) {
1686                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1687                 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1688                 if (!(mcp & (1 << crtc)))
1689                         continue;
1690
1691                 dcb = lookup_dcb(dev, i, mcp);
1692                 if (!dcb)
1693                         continue;
1694                 or = ffs(dcb->or) - 1;
1695
1696                 nouveau_bios_run_display_table(dev, cfg, pclk, dcb, crtc);
1697
1698                 nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000);
1699                 switch (dcb->type) {
1700                 case OUTPUT_ANALOG:
1701                         nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000);
1702                         break;
1703                 case OUTPUT_TMDS:
1704                 case OUTPUT_LVDS:
1705                 case OUTPUT_DP:
1706                         if (cfg & 0x00000100)
1707                                 tmp = 0x00000101;
1708                         else
1709                                 tmp = 0x00000000;
1710
1711                         nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp);
1712                         break;
1713                 default:
1714                         break;
1715                 }
1716
1717                 break;
1718         }
1719
1720         nv_wr32(dev, 0x6101d4, 0x00000000);
1721         nv_wr32(dev, 0x6109d4, 0x00000000);
1722         nv_wr32(dev, 0x6101d0, 0x80000000);
1723 }
1724
1725 static void
1726 nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask)
1727 {
1728         struct dcb_entry *dcb;
1729         int pclk, i;
1730
1731         pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1732
1733         for (i = 0; mask && i < 8; i++) {
1734                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1735                 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1736                 if (!(mcp & (1 << crtc)))
1737                         continue;
1738
1739                 dcb = lookup_dcb(dev, i, mcp);
1740                 if (!dcb)
1741                         continue;
1742
1743                 nouveau_bios_run_display_table(dev, cfg, -pclk, dcb, crtc);
1744         }
1745
1746         nv_wr32(dev, 0x6101d4, 0x00000000);
1747         nv_wr32(dev, 0x6109d4, 0x00000000);
1748         nv_wr32(dev, 0x6101d0, 0x80000000);
1749 }
1750
1751 static void
1752 nvd0_display_bh(unsigned long data)
1753 {
1754         struct drm_device *dev = (struct drm_device *)data;
1755         struct nvd0_display *disp = nvd0_display(dev);
1756         u32 mask = 0, crtc = ~0;
1757         int i;
1758
1759         if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
1760                 NV_INFO(dev, "PDISP: modeset req %d\n", disp->modeset);
1761                 NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n",
1762                          nv_rd32(dev, 0x6101d0),
1763                          nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
1764                 for (i = 0; i < 8; i++) {
1765                         NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n",
1766                                 i < 4 ? "DAC" : "SOR", i,
1767                                 nv_rd32(dev, 0x640180 + (i * 0x20)),
1768                                 nv_rd32(dev, 0x660180 + (i * 0x20)));
1769                 }
1770         }
1771
1772         while (!mask && ++crtc < dev->mode_config.num_crtc)
1773                 mask = nv_rd32(dev, 0x6101d4 + (crtc * 0x800));
1774
1775         if (disp->modeset & 0x00000001)
1776                 nvd0_display_unk1_handler(dev, crtc, mask);
1777         if (disp->modeset & 0x00000002)
1778                 nvd0_display_unk2_handler(dev, crtc, mask);
1779         if (disp->modeset & 0x00000004)
1780                 nvd0_display_unk4_handler(dev, crtc, mask);
1781 }
1782
1783 static void
1784 nvd0_display_intr(struct drm_device *dev)
1785 {
1786         struct nvd0_display *disp = nvd0_display(dev);
1787         u32 intr = nv_rd32(dev, 0x610088);
1788         int i;
1789
1790         if (intr & 0x00000001) {
1791                 u32 stat = nv_rd32(dev, 0x61008c);
1792                 nv_wr32(dev, 0x61008c, stat);
1793                 intr &= ~0x00000001;
1794         }
1795
1796         if (intr & 0x00000002) {
1797                 u32 stat = nv_rd32(dev, 0x61009c);
1798                 int chid = ffs(stat) - 1;
1799                 if (chid >= 0) {
1800                         u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
1801                         u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
1802                         u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
1803
1804                         NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
1805                                      "0x%08x 0x%08x\n",
1806                                 chid, (mthd & 0x0000ffc), data, mthd, unkn);
1807                         nv_wr32(dev, 0x61009c, (1 << chid));
1808                         nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
1809                 }
1810
1811                 intr &= ~0x00000002;
1812         }
1813
1814         if (intr & 0x00100000) {
1815                 u32 stat = nv_rd32(dev, 0x6100ac);
1816
1817                 if (stat & 0x00000007) {
1818                         disp->modeset = stat;
1819                         tasklet_schedule(&disp->tasklet);
1820
1821                         nv_wr32(dev, 0x6100ac, (stat & 0x00000007));
1822                         stat &= ~0x00000007;
1823                 }
1824
1825                 if (stat) {
1826                         NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat);
1827                         nv_wr32(dev, 0x6100ac, stat);
1828                 }
1829
1830                 intr &= ~0x00100000;
1831         }
1832
1833         for (i = 0; i < dev->mode_config.num_crtc; i++) {
1834                 u32 mask = 0x01000000 << i;
1835                 if (intr & mask) {
1836                         u32 stat = nv_rd32(dev, 0x6100bc + (i * 0x800));
1837                         nv_wr32(dev, 0x6100bc + (i * 0x800), stat);
1838                         intr &= ~mask;
1839                 }
1840         }
1841
1842         if (intr)
1843                 NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
1844 }
1845
1846 /******************************************************************************
1847  * Init
1848  *****************************************************************************/
1849 void
1850 nvd0_display_fini(struct drm_device *dev)
1851 {
1852         int i;
1853
1854         /* fini cursors + overlays + flips */
1855         for (i = 1; i >= 0; i--) {
1856                 evo_fini_pio(dev, EVO_CURS(i));
1857                 evo_fini_pio(dev, EVO_OIMM(i));
1858                 evo_fini_dma(dev, EVO_OVLY(i));
1859                 evo_fini_dma(dev, EVO_FLIP(i));
1860         }
1861
1862         /* fini master */
1863         evo_fini_dma(dev, EVO_MASTER);
1864 }
1865
1866 int
1867 nvd0_display_init(struct drm_device *dev)
1868 {
1869         struct nvd0_display *disp = nvd0_display(dev);
1870         int ret, i;
1871         u32 *push;
1872
1873         if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
1874                 nv_wr32(dev, 0x6100ac, 0x00000100);
1875                 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
1876                 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
1877                         NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
1878                                  nv_rd32(dev, 0x6194e8));
1879                         return -EBUSY;
1880                 }
1881         }
1882
1883         /* nfi what these are exactly, i do know that SOR_MODE_CTRL won't
1884          * work at all unless you do the SOR part below.
1885          */
1886         for (i = 0; i < 3; i++) {
1887                 u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800));
1888                 nv_wr32(dev, 0x6101c0 + (i * 0x800), dac);
1889         }
1890
1891         for (i = 0; i < 4; i++) {
1892                 u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800));
1893                 nv_wr32(dev, 0x6301c4 + (i * 0x800), sor);
1894         }
1895
1896         for (i = 0; i < dev->mode_config.num_crtc; i++) {
1897                 u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800));
1898                 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800));
1899                 u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800));
1900                 nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0);
1901                 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1);
1902                 nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2);
1903         }
1904
1905         /* point at our hash table / objects, enable interrupts */
1906         nv_wr32(dev, 0x610010, (disp->mem->vinst >> 8) | 9);
1907         nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307);
1908
1909         /* init master */
1910         ret = evo_init_dma(dev, EVO_MASTER);
1911         if (ret)
1912                 goto error;
1913
1914         /* init flips + overlays + cursors */
1915         for (i = 0; i < dev->mode_config.num_crtc; i++) {
1916                 if ((ret = evo_init_dma(dev, EVO_FLIP(i))) ||
1917                     (ret = evo_init_dma(dev, EVO_OVLY(i))) ||
1918                     (ret = evo_init_pio(dev, EVO_OIMM(i))) ||
1919                     (ret = evo_init_pio(dev, EVO_CURS(i))))
1920                         goto error;
1921         }
1922
1923         push = evo_wait(dev, EVO_MASTER, 32);
1924         if (!push) {
1925                 ret = -EBUSY;
1926                 goto error;
1927         }
1928         evo_mthd(push, 0x0088, 1);
1929         evo_data(push, NvEvoSync);
1930         evo_mthd(push, 0x0084, 1);
1931         evo_data(push, 0x00000000);
1932         evo_mthd(push, 0x0084, 1);
1933         evo_data(push, 0x80000000);
1934         evo_mthd(push, 0x008c, 1);
1935         evo_data(push, 0x00000000);
1936         evo_kick(push, dev, EVO_MASTER);
1937
1938 error:
1939         if (ret)
1940                 nvd0_display_fini(dev);
1941         return ret;
1942 }
1943
1944 void
1945 nvd0_display_destroy(struct drm_device *dev)
1946 {
1947         struct drm_nouveau_private *dev_priv = dev->dev_private;
1948         struct nvd0_display *disp = nvd0_display(dev);
1949         struct pci_dev *pdev = dev->pdev;
1950         int i;
1951
1952         for (i = 0; i < EVO_DMA_NR; i++) {
1953                 struct evo *evo = &disp->evo[i];
1954                 pci_free_consistent(pdev, PAGE_SIZE, evo->ptr, evo->handle);
1955         }
1956
1957         nouveau_gpuobj_ref(NULL, &disp->mem);
1958         nouveau_bo_unmap(disp->sync);
1959         nouveau_bo_ref(NULL, &disp->sync);
1960         nouveau_irq_unregister(dev, 26);
1961
1962         dev_priv->engine.display.priv = NULL;
1963         kfree(disp);
1964 }
1965
1966 int
1967 nvd0_display_create(struct drm_device *dev)
1968 {
1969         struct drm_nouveau_private *dev_priv = dev->dev_private;
1970         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
1971         struct dcb_table *dcb = &dev_priv->vbios.dcb;
1972         struct drm_connector *connector, *tmp;
1973         struct pci_dev *pdev = dev->pdev;
1974         struct nvd0_display *disp;
1975         struct dcb_entry *dcbe;
1976         int crtcs, ret, i;
1977
1978         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1979         if (!disp)
1980                 return -ENOMEM;
1981         dev_priv->engine.display.priv = disp;
1982
1983         /* create crtc objects to represent the hw heads */
1984         crtcs = nv_rd32(dev, 0x022448);
1985         for (i = 0; i < crtcs; i++) {
1986                 ret = nvd0_crtc_create(dev, i);
1987                 if (ret)
1988                         goto out;
1989         }
1990
1991         /* create encoder/connector objects based on VBIOS DCB table */
1992         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
1993                 connector = nouveau_connector_create(dev, dcbe->connector);
1994                 if (IS_ERR(connector))
1995                         continue;
1996
1997                 if (dcbe->location != DCB_LOC_ON_CHIP) {
1998                         NV_WARN(dev, "skipping off-chip encoder %d/%d\n",
1999                                 dcbe->type, ffs(dcbe->or) - 1);
2000                         continue;
2001                 }
2002
2003                 switch (dcbe->type) {
2004                 case OUTPUT_TMDS:
2005                 case OUTPUT_LVDS:
2006                 case OUTPUT_DP:
2007                         nvd0_sor_create(connector, dcbe);
2008                         break;
2009                 case OUTPUT_ANALOG:
2010                         nvd0_dac_create(connector, dcbe);
2011                         break;
2012                 default:
2013                         NV_WARN(dev, "skipping unsupported encoder %d/%d\n",
2014                                 dcbe->type, ffs(dcbe->or) - 1);
2015                         continue;
2016                 }
2017         }
2018
2019         /* cull any connectors we created that don't have an encoder */
2020         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2021                 if (connector->encoder_ids[0])
2022                         continue;
2023
2024                 NV_WARN(dev, "%s has no encoders, removing\n",
2025                         drm_get_connector_name(connector));
2026                 connector->funcs->destroy(connector);
2027         }
2028
2029         /* setup interrupt handling */
2030         tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev);
2031         nouveau_irq_register(dev, 26, nvd0_display_intr);
2032
2033         /* small shared memory area we use for notifiers and semaphores */
2034         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2035                              0, 0x0000, NULL, &disp->sync);
2036         if (!ret) {
2037                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2038                 if (!ret)
2039                         ret = nouveau_bo_map(disp->sync);
2040                 if (ret)
2041                         nouveau_bo_ref(NULL, &disp->sync);
2042         }
2043
2044         if (ret)
2045                 goto out;
2046
2047         /* hash table and dma objects for the memory areas we care about */
2048         ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
2049                                  NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
2050         if (ret)
2051                 goto out;
2052
2053         /* create evo dma channels */
2054         for (i = 0; i < EVO_DMA_NR; i++) {
2055                 struct evo *evo = &disp->evo[i];
2056                 u64 offset = disp->sync->bo.offset;
2057                 u32 dmao = 0x1000 + (i * 0x100);
2058                 u32 hash = 0x0000 + (i * 0x040);
2059
2060                 evo->idx = i;
2061                 evo->sem.offset = EVO_SYNC(evo->idx, 0x00);
2062                 evo->ptr = pci_alloc_consistent(pdev, PAGE_SIZE, &evo->handle);
2063                 if (!evo->ptr) {
2064                         ret = -ENOMEM;
2065                         goto out;
2066                 }
2067
2068                 nv_wo32(disp->mem, dmao + 0x00, 0x00000049);
2069                 nv_wo32(disp->mem, dmao + 0x04, (offset + 0x0000) >> 8);
2070                 nv_wo32(disp->mem, dmao + 0x08, (offset + 0x0fff) >> 8);
2071                 nv_wo32(disp->mem, dmao + 0x0c, 0x00000000);
2072                 nv_wo32(disp->mem, dmao + 0x10, 0x00000000);
2073                 nv_wo32(disp->mem, dmao + 0x14, 0x00000000);
2074                 nv_wo32(disp->mem, hash + 0x00, NvEvoSync);
2075                 nv_wo32(disp->mem, hash + 0x04, 0x00000001 | (i << 27) |
2076                                                 ((dmao + 0x00) << 9));
2077
2078                 nv_wo32(disp->mem, dmao + 0x20, 0x00000049);
2079                 nv_wo32(disp->mem, dmao + 0x24, 0x00000000);
2080                 nv_wo32(disp->mem, dmao + 0x28, (dev_priv->vram_size - 1) >> 8);
2081                 nv_wo32(disp->mem, dmao + 0x2c, 0x00000000);
2082                 nv_wo32(disp->mem, dmao + 0x30, 0x00000000);
2083                 nv_wo32(disp->mem, dmao + 0x34, 0x00000000);
2084                 nv_wo32(disp->mem, hash + 0x08, NvEvoVRAM);
2085                 nv_wo32(disp->mem, hash + 0x0c, 0x00000001 | (i << 27) |
2086                                                 ((dmao + 0x20) << 9));
2087
2088                 nv_wo32(disp->mem, dmao + 0x40, 0x00000009);
2089                 nv_wo32(disp->mem, dmao + 0x44, 0x00000000);
2090                 nv_wo32(disp->mem, dmao + 0x48, (dev_priv->vram_size - 1) >> 8);
2091                 nv_wo32(disp->mem, dmao + 0x4c, 0x00000000);
2092                 nv_wo32(disp->mem, dmao + 0x50, 0x00000000);
2093                 nv_wo32(disp->mem, dmao + 0x54, 0x00000000);
2094                 nv_wo32(disp->mem, hash + 0x10, NvEvoVRAM_LP);
2095                 nv_wo32(disp->mem, hash + 0x14, 0x00000001 | (i << 27) |
2096                                                 ((dmao + 0x40) << 9));
2097
2098                 nv_wo32(disp->mem, dmao + 0x60, 0x0fe00009);
2099                 nv_wo32(disp->mem, dmao + 0x64, 0x00000000);
2100                 nv_wo32(disp->mem, dmao + 0x68, (dev_priv->vram_size - 1) >> 8);
2101                 nv_wo32(disp->mem, dmao + 0x6c, 0x00000000);
2102                 nv_wo32(disp->mem, dmao + 0x70, 0x00000000);
2103                 nv_wo32(disp->mem, dmao + 0x74, 0x00000000);
2104                 nv_wo32(disp->mem, hash + 0x18, NvEvoFB32);
2105                 nv_wo32(disp->mem, hash + 0x1c, 0x00000001 | (i << 27) |
2106                                                 ((dmao + 0x60) << 9));
2107         }
2108
2109         pinstmem->flush(dev);
2110
2111 out:
2112         if (ret)
2113                 nvd0_display_destroy(dev);
2114         return ret;
2115 }