drivers/spi/spi-bcm63xx.c

   1 /*
   2  * Broadcom BCM63xx SPI controller support
   3  *
   4  * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
   5  * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the
  19  * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/completion.h>
  32 #include <linux/err.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/pm_runtime.h>
  35
  36 #include <bcm63xx_dev_spi.h>
  37
  38 #define PFX             KBUILD_MODNAME
  39
  40 #define BCM63XX_SPI_MAX_PREPEND         15
  41
  42 struct bcm63xx_spi {
  43         struct completion       done;
  44
  45         void __iomem            *regs;
  46         int                     irq;
  47
  48         /* Platform data */
  49         unsigned                fifo_size;
  50         unsigned int            msg_type_shift;
  51         unsigned int            msg_ctl_width;
  52
  53         /* data iomem */
  54         u8 __iomem              *tx_io;
  55         const u8 __iomem        *rx_io;
  56
  57         struct clk              *clk;
  58         struct platform_device  *pdev;
  59 };
  60
  61 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
  62                                 unsigned int offset)
  63 {
  64         return bcm_readb(bs->regs + bcm63xx_spireg(offset));
  65 }
  66
  67 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
  68                                 unsigned int offset)
  69 {
  70         return bcm_readw(bs->regs + bcm63xx_spireg(offset));
  71 }
  72
  73 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
  74                                   u8 value, unsigned int offset)
  75 {
  76         bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
  77 }
  78
  79 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
  80                                   u16 value, unsigned int offset)
  81 {
  82         bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
  83 }
  84
  85 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
  86         { 20000000, SPI_CLK_20MHZ },
  87         { 12500000, SPI_CLK_12_50MHZ },
  88         {  6250000, SPI_CLK_6_250MHZ },
  89         {  3125000, SPI_CLK_3_125MHZ },
  90         {  1563000, SPI_CLK_1_563MHZ },
  91         {   781000, SPI_CLK_0_781MHZ },
  92         {   391000, SPI_CLK_0_391MHZ }
  93 };
  94
  95 static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
  96                                       struct spi_transfer *t)
  97 {
  98         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
  99         u8 clk_cfg, reg;
 100         int i;
 101
 102         /* Find the closest clock configuration */
 103         for (i = 0; i < SPI_CLK_MASK; i++) {
 104                 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
 105                         clk_cfg = bcm63xx_spi_freq_table[i][1];
 106                         break;
 107                 }
 108         }
 109
 110         /* No matching configuration found, default to lowest */
 111         if (i == SPI_CLK_MASK)
 112                 clk_cfg = SPI_CLK_0_391MHZ;
 113
 114         /* clear existing clock configuration bits of the register */
 115         reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 116         reg &= ~SPI_CLK_MASK;
 117         reg |= clk_cfg;
 118
 119         bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 120         dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 121                 clk_cfg, t->speed_hz);
 122 }
 123
 124 /* the spi->mode bits understood by this driver: */
 125 #define MODEBITS (SPI_CPOL | SPI_CPHA)
 126
 127 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
 128                                 unsigned int num_transfers)
 129 {
 130         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 131         u16 msg_ctl;
 132         u16 cmd;
 133         u8 rx_tail;
 134         unsigned int i, timeout = 0, prepend_len = 0, len = 0;
 135         struct spi_transfer *t = first;
 136         bool do_rx = false;
 137         bool do_tx = false;
 138
 139         /* Disable the CMD_DONE interrupt */
 140         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 141
 142         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 143                 t->tx_buf, t->rx_buf, t->len);
 144
 145         if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
 146                 prepend_len = t->len;
 147
 148         /* prepare the buffer */
 149         for (i = 0; i < num_transfers; i++) {
 150                 if (t->tx_buf) {
 151                         do_tx = true;
 152                         memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
 153
 154                         /* don't prepend more than one tx */
 155                         if (t != first)
 156                                 prepend_len = 0;
 157                 }
 158
 159                 if (t->rx_buf) {
 160                         do_rx = true;
 161                         /* prepend is half-duplex write only */
 162                         if (t == first)
 163                                 prepend_len = 0;
 164                 }
 165
 166                 len += t->len;
 167
 168                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 169                                transfer_list);
 170         }
 171
 172         len -= prepend_len;
 173
 174         init_completion(&bs->done);
 175
 176         /* Fill in the Message control register */
 177         msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
 178
 179         if (do_rx && do_tx && prepend_len == 0)
 180                 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
 181         else if (do_rx)
 182                 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
 183         else if (do_tx)
 184                 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
 185
 186         switch (bs->msg_ctl_width) {
 187         case 8:
 188                 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
 189                 break;
 190         case 16:
 191                 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 192                 break;
 193         }
 194
 195         /* Issue the transfer */
 196         cmd = SPI_CMD_START_IMMEDIATE;
 197         cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 198         cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 199         bcm_spi_writew(bs, cmd, SPI_CMD);
 200
 201         /* Enable the CMD_DONE interrupt */
 202         bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 203
 204         timeout = wait_for_completion_timeout(&bs->done, HZ);
 205         if (!timeout)
 206                 return -ETIMEDOUT;
 207
 208         /* read out all data */
 209         rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
 210
 211         if (do_rx && rx_tail != len)
 212                 return -EIO;
 213
 214         if (!rx_tail)
 215                 return 0;
 216
 217         len = 0;
 218         t = first;
 219         /* Read out all the data */
 220         for (i = 0; i < num_transfers; i++) {
 221                 if (t->rx_buf)
 222                         memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
 223
 224                 if (t != first || prepend_len == 0)
 225                         len += t->len;
 226
 227                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 228                                transfer_list);
 229         }
 230
 231         return 0;
 232 }
 233
 234 static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
 235 {
 236         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 237
 238         pm_runtime_get_sync(&bs->pdev->dev);
 239
 240         return 0;
 241 }
 242
 243 static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
 244 {
 245         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 246
 247         pm_runtime_put(&bs->pdev->dev);
 248
 249         return 0;
 250 }
 251
 252 static int bcm63xx_spi_transfer_one(struct spi_master *master,
 253                                         struct spi_message *m)
 254 {
 255         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 256         struct spi_transfer *t, *first = NULL;
 257         struct spi_device *spi = m->spi;
 258         int status = 0;
 259         unsigned int n_transfers = 0, total_len = 0;
 260         bool can_use_prepend = false;
 261
 262         /*
 263          * This SPI controller does not support keeping CS active after a
 264          * transfer.
 265          * Work around this by merging as many transfers we can into one big
 266          * full-duplex transfers.
 267          */
 268         list_for_each_entry(t, &m->transfers, transfer_list) {
 269                 if (!first)
 270                         first = t;
 271
 272                 n_transfers++;
 273                 total_len += t->len;
 274
 275                 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
 276                     first->len <= BCM63XX_SPI_MAX_PREPEND)
 277                         can_use_prepend = true;
 278                 else if (can_use_prepend && t->tx_buf)
 279                         can_use_prepend = false;
 280
 281                 /* we can only transfer one fifo worth of data */
 282                 if ((can_use_prepend &&
 283                      total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
 284                     (!can_use_prepend && total_len > bs->fifo_size)) {
 285                         dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
 286                                 total_len, bs->fifo_size);
 287                         status = -EINVAL;
 288                         goto exit;
 289                 }
 290
 291                 /* all combined transfers have to have the same speed */
 292                 if (t->speed_hz != first->speed_hz) {
 293                         dev_err(&spi->dev, "unable to change speed between transfers\n");
 294                         status = -EINVAL;
 295                         goto exit;
 296                 }
 297
 298                 /* CS will be deasserted directly after transfer */
 299                 if (t->delay_usecs) {
 300                         dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
 301                         status = -EINVAL;
 302                         goto exit;
 303                 }
 304
 305                 if (t->cs_change ||
 306                     list_is_last(&t->transfer_list, &m->transfers)) {
 307                         /* configure adapter for a new transfer */
 308                         bcm63xx_spi_setup_transfer(spi, first);
 309
 310                         /* send the data */
 311                         status = bcm63xx_txrx_bufs(spi, first, n_transfers);
 312                         if (status)
 313                                 goto exit;
 314
 315                         m->actual_length += total_len;
 316
 317                         first = NULL;
 318                         n_transfers = 0;
 319                         total_len = 0;
 320                         can_use_prepend = false;
 321                 }
 322         }
 323 exit:
 324         m->status = status;
 325         spi_finalize_current_message(master);
 326
 327         return 0;
 328 }
 329
 330 /* This driver supports single master mode only. Hence
 331  * CMD_DONE is the only interrupt we care about
 332  */
 333 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 334 {
 335         struct spi_master *master = (struct spi_master *)dev_id;
 336         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 337         u8 intr;
 338
 339         /* Read interupts and clear them immediately */
 340         intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 341         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 342         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 343
 344         /* A transfer completed */
 345         if (intr & SPI_INTR_CMD_DONE)
 346                 complete(&bs->done);
 347
 348         return IRQ_HANDLED;
 349 }
 350
 351
 352 static int bcm63xx_spi_probe(struct platform_device *pdev)
 353 {
 354         struct resource *r;
 355         struct device *dev = &pdev->dev;
 356         struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 357         int irq;
 358         struct spi_master *master;
 359         struct clk *clk;
 360         struct bcm63xx_spi *bs;
 361         int ret;
 362
 363         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 364         if (!r) {
 365                 dev_err(dev, "no iomem\n");
 366                 ret = -ENXIO;
 367                 goto out;
 368         }
 369
 370         irq = platform_get_irq(pdev, 0);
 371         if (irq < 0) {
 372                 dev_err(dev, "no irq\n");
 373                 ret = -ENXIO;
 374                 goto out;
 375         }
 376
 377         clk = clk_get(dev, "spi");
 378         if (IS_ERR(clk)) {
 379                 dev_err(dev, "no clock for device\n");
 380                 ret = PTR_ERR(clk);
 381                 goto out;
 382         }
 383
 384         master = spi_alloc_master(dev, sizeof(*bs));
 385         if (!master) {
 386                 dev_err(dev, "out of memory\n");
 387                 ret = -ENOMEM;
 388                 goto out_clk;
 389         }
 390
 391         bs = spi_master_get_devdata(master);
 392
 393         platform_set_drvdata(pdev, master);
 394         bs->pdev = pdev;
 395
 396         bs->regs = devm_ioremap_resource(&pdev->dev, r);
 397         if (IS_ERR(bs->regs)) {
 398                 ret = PTR_ERR(bs->regs);
 399                 goto out_err;
 400         }
 401
 402         bs->irq = irq;
 403         bs->clk = clk;
 404         bs->fifo_size = pdata->fifo_size;
 405
 406         ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 407                                                         pdev->name, master);
 408         if (ret) {
 409                 dev_err(dev, "unable to request irq\n");
 410                 goto out_err;
 411         }
 412
 413         master->bus_num = pdata->bus_num;
 414         master->num_chipselect = pdata->num_chipselect;
 415         master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
 416         master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
 417         master->transfer_one_message = bcm63xx_spi_transfer_one;
 418         master->mode_bits = MODEBITS;
 419         master->bits_per_word_mask = SPI_BPW_MASK(8);
 420         bs->msg_type_shift = pdata->msg_type_shift;
 421         bs->msg_ctl_width = pdata->msg_ctl_width;
 422         bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 423         bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 424
 425         switch (bs->msg_ctl_width) {
 426         case 8:
 427         case 16:
 428                 break;
 429         default:
 430                 dev_err(dev, "unsupported MSG_CTL width: %d\n",
 431                          bs->msg_ctl_width);
 432                 goto out_err;
 433         }
 434
 435         /* Initialize hardware */
 436         clk_prepare_enable(bs->clk);
 437         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 438
 439         /* register and we are done */
 440         ret = spi_register_master(master);
 441         if (ret) {
 442                 dev_err(dev, "spi register failed\n");
 443                 goto out_clk_disable;
 444         }
 445
 446         dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n",
 447                  r->start, irq, bs->fifo_size);
 448
 449         return 0;
 450
 451 out_clk_disable:
 452         clk_disable_unprepare(clk);
 453 out_err:
 454         spi_master_put(master);
 455 out_clk:
 456         clk_put(clk);
 457 out:
 458         return ret;
 459 }
 460
 461 static int bcm63xx_spi_remove(struct platform_device *pdev)
 462 {
 463         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
 464         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 465
 466         spi_unregister_master(master);
 467
 468         /* reset spi block */
 469         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 470
 471         /* HW shutdown */
 472         clk_disable_unprepare(bs->clk);
 473         clk_put(bs->clk);
 474
 475         spi_master_put(master);
 476
 477         return 0;
 478 }
 479
 480 #ifdef CONFIG_PM
 481 static int bcm63xx_spi_suspend(struct device *dev)
 482 {
 483         struct spi_master *master =
 484                         platform_get_drvdata(to_platform_device(dev));
 485         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 486
 487         spi_master_suspend(master);
 488
 489         clk_disable_unprepare(bs->clk);
 490
 491         return 0;
 492 }
 493
 494 static int bcm63xx_spi_resume(struct device *dev)
 495 {
 496         struct spi_master *master =
 497                         platform_get_drvdata(to_platform_device(dev));
 498         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 499
 500         clk_prepare_enable(bs->clk);
 501
 502         spi_master_resume(master);
 503
 504         return 0;
 505 }
 506
 507 static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 508         .suspend        = bcm63xx_spi_suspend,
 509         .resume         = bcm63xx_spi_resume,
 510 };
 511
 512 #define BCM63XX_SPI_PM_OPS      (&bcm63xx_spi_pm_ops)
 513 #else
 514 #define BCM63XX_SPI_PM_OPS      NULL
 515 #endif
 516
 517 static struct platform_driver bcm63xx_spi_driver = {
 518         .driver = {
 519                 .name   = "bcm63xx-spi",
 520                 .owner  = THIS_MODULE,
 521                 .pm     = BCM63XX_SPI_PM_OPS,
 522         },
 523         .probe          = bcm63xx_spi_probe,
 524         .remove         = bcm63xx_spi_remove,
 525 };
 526
 527 module_platform_driver(bcm63xx_spi_driver);
 528
 529 MODULE_ALIAS("platform:bcm63xx_spi");
 530 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 531 MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
 532 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 533 MODULE_LICENSE("GPL");