3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of_device.h>
20 #include <linux/pm_runtime.h>
22 #include <video/of_display_timing.h>
23 #include <video/samsung_fimd.h>
24 #include <drm/exynos_drm.h>
26 #include "exynos_drm_drv.h"
27 #include "exynos_drm_fbdev.h"
28 #include "exynos_drm_crtc.h"
29 #include "exynos_drm_iommu.h"
32 * FIMD is stand for Fully Interactive Mobile Display and
33 * as a display controller, it transfers contents drawn on memory
34 * to a LCD Panel through Display Interfaces such as RGB or
38 /* position control register for hardware window 0, 2 ~ 4.*/
39 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
40 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
42 * size control register for hardware windows 0 and alpha control register
43 * for hardware windows 1 ~ 4
45 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
46 /* size control register for hardware windows 1 ~ 2. */
47 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
49 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
50 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
51 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
53 /* color key control register for hardware window 1 ~ 4. */
54 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
55 /* color key value register for hardware window 1 ~ 4. */
56 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
58 /* FIMD has totally five hardware windows. */
61 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
63 struct fimd_driver_data {
64 unsigned int timing_base;
66 unsigned int has_shadowcon:1;
67 unsigned int has_clksel:1;
70 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
75 static struct fimd_driver_data exynos4_fimd_driver_data = {
80 static struct fimd_driver_data exynos5_fimd_driver_data = {
81 .timing_base = 0x20000,
85 struct fimd_win_data {
86 unsigned int offset_x;
87 unsigned int offset_y;
88 unsigned int ovl_width;
89 unsigned int ovl_height;
90 unsigned int fb_width;
91 unsigned int fb_height;
94 unsigned int buf_offsize;
95 unsigned int line_size; /* bytes */
100 struct fimd_context {
101 struct exynos_drm_subdrv subdrv;
103 struct drm_crtc *crtc;
107 struct fimd_win_data win_data[WINDOWS_NR];
109 unsigned int default_win;
110 unsigned long irq_flags;
115 wait_queue_head_t wait_vsync_queue;
116 atomic_t wait_vsync_event;
118 struct exynos_drm_panel_info *panel;
119 struct fimd_driver_data *driver_data;
123 static const struct of_device_id fimd_driver_dt_match[] = {
124 { .compatible = "samsung,s3c6400-fimd",
125 .data = &s3c64xx_fimd_driver_data },
126 { .compatible = "samsung,exynos4210-fimd",
127 .data = &exynos4_fimd_driver_data },
128 { .compatible = "samsung,exynos5250-fimd",
129 .data = &exynos5_fimd_driver_data },
134 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
135 struct platform_device *pdev)
138 const struct of_device_id *of_id =
139 of_match_device(fimd_driver_dt_match, &pdev->dev);
142 return (struct fimd_driver_data *)of_id->data;
145 return (struct fimd_driver_data *)
146 platform_get_device_id(pdev)->driver_data;
149 static bool fimd_display_is_connected(struct device *dev)
156 static void *fimd_get_panel(struct device *dev)
158 struct fimd_context *ctx = get_fimd_context(dev);
163 static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode)
170 static int fimd_display_power_on(struct device *dev, int mode)
177 static struct exynos_drm_display_ops fimd_display_ops = {
178 .type = EXYNOS_DISPLAY_TYPE_LCD,
179 .is_connected = fimd_display_is_connected,
180 .get_panel = fimd_get_panel,
181 .check_mode = fimd_check_mode,
182 .power_on = fimd_display_power_on,
185 static void fimd_dpms(struct device *subdrv_dev, int mode)
187 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
189 DRM_DEBUG_KMS("%d\n", mode);
191 mutex_lock(&ctx->lock);
194 case DRM_MODE_DPMS_ON:
196 * enable fimd hardware only if suspended status.
198 * P.S. fimd_dpms function would be called at booting time so
199 * clk_enable could be called double time.
202 pm_runtime_get_sync(subdrv_dev);
204 case DRM_MODE_DPMS_STANDBY:
205 case DRM_MODE_DPMS_SUSPEND:
206 case DRM_MODE_DPMS_OFF:
208 pm_runtime_put_sync(subdrv_dev);
211 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
215 mutex_unlock(&ctx->lock);
218 static void fimd_apply(struct device *subdrv_dev)
220 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
221 struct exynos_drm_manager *mgr = ctx->subdrv.manager;
222 struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
223 struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
224 struct fimd_win_data *win_data;
227 for (i = 0; i < WINDOWS_NR; i++) {
228 win_data = &ctx->win_data[i];
229 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
230 ovl_ops->commit(subdrv_dev, i);
233 if (mgr_ops && mgr_ops->commit)
234 mgr_ops->commit(subdrv_dev);
237 static void fimd_commit(struct device *dev)
239 struct fimd_context *ctx = get_fimd_context(dev);
240 struct exynos_drm_panel_info *panel = ctx->panel;
241 struct fb_videomode *timing = &panel->timing;
242 struct fimd_driver_data *driver_data;
245 driver_data = ctx->driver_data;
249 /* setup polarity values from machine code. */
250 writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
252 /* setup vertical timing values. */
253 val = VIDTCON0_VBPD(timing->upper_margin - 1) |
254 VIDTCON0_VFPD(timing->lower_margin - 1) |
255 VIDTCON0_VSPW(timing->vsync_len - 1);
256 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
258 /* setup horizontal timing values. */
259 val = VIDTCON1_HBPD(timing->left_margin - 1) |
260 VIDTCON1_HFPD(timing->right_margin - 1) |
261 VIDTCON1_HSPW(timing->hsync_len - 1);
262 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
264 /* setup horizontal and vertical display size. */
265 val = VIDTCON2_LINEVAL(timing->yres - 1) |
266 VIDTCON2_HOZVAL(timing->xres - 1) |
267 VIDTCON2_LINEVAL_E(timing->yres - 1) |
268 VIDTCON2_HOZVAL_E(timing->xres - 1);
269 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
271 /* setup clock source, clock divider, enable dma. */
273 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
275 if (ctx->driver_data->has_clksel) {
276 val &= ~VIDCON0_CLKSEL_MASK;
277 val |= VIDCON0_CLKSEL_LCD;
281 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
283 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
286 * fields of register with prefix '_F' would be updated
287 * at vsync(same as dma start)
289 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
290 writel(val, ctx->regs + VIDCON0);
293 static int fimd_enable_vblank(struct device *dev)
295 struct fimd_context *ctx = get_fimd_context(dev);
301 if (!test_and_set_bit(0, &ctx->irq_flags)) {
302 val = readl(ctx->regs + VIDINTCON0);
304 val |= VIDINTCON0_INT_ENABLE;
305 val |= VIDINTCON0_INT_FRAME;
307 val &= ~VIDINTCON0_FRAMESEL0_MASK;
308 val |= VIDINTCON0_FRAMESEL0_VSYNC;
309 val &= ~VIDINTCON0_FRAMESEL1_MASK;
310 val |= VIDINTCON0_FRAMESEL1_NONE;
312 writel(val, ctx->regs + VIDINTCON0);
318 static void fimd_disable_vblank(struct device *dev)
320 struct fimd_context *ctx = get_fimd_context(dev);
326 if (test_and_clear_bit(0, &ctx->irq_flags)) {
327 val = readl(ctx->regs + VIDINTCON0);
329 val &= ~VIDINTCON0_INT_FRAME;
330 val &= ~VIDINTCON0_INT_ENABLE;
332 writel(val, ctx->regs + VIDINTCON0);
336 static void fimd_wait_for_vblank(struct device *dev)
338 struct fimd_context *ctx = get_fimd_context(dev);
343 atomic_set(&ctx->wait_vsync_event, 1);
346 * wait for FIMD to signal VSYNC interrupt or return after
347 * timeout which is set to 50ms (refresh rate of 20).
349 if (!wait_event_timeout(ctx->wait_vsync_queue,
350 !atomic_read(&ctx->wait_vsync_event),
352 DRM_DEBUG_KMS("vblank wait timed out.\n");
355 static struct exynos_drm_manager_ops fimd_manager_ops = {
358 .commit = fimd_commit,
359 .enable_vblank = fimd_enable_vblank,
360 .disable_vblank = fimd_disable_vblank,
361 .wait_for_vblank = fimd_wait_for_vblank,
364 static void fimd_win_mode_set(struct device *dev,
365 struct exynos_drm_overlay *overlay)
367 struct fimd_context *ctx = get_fimd_context(dev);
368 struct fimd_win_data *win_data;
370 unsigned long offset;
373 dev_err(dev, "overlay is NULL\n");
378 if (win == DEFAULT_ZPOS)
379 win = ctx->default_win;
381 if (win < 0 || win >= WINDOWS_NR)
384 offset = overlay->fb_x * (overlay->bpp >> 3);
385 offset += overlay->fb_y * overlay->pitch;
387 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
389 win_data = &ctx->win_data[win];
391 win_data->offset_x = overlay->crtc_x;
392 win_data->offset_y = overlay->crtc_y;
393 win_data->ovl_width = overlay->crtc_width;
394 win_data->ovl_height = overlay->crtc_height;
395 win_data->fb_width = overlay->fb_width;
396 win_data->fb_height = overlay->fb_height;
397 win_data->dma_addr = overlay->dma_addr[0] + offset;
398 win_data->bpp = overlay->bpp;
399 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
401 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
403 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
404 win_data->offset_x, win_data->offset_y);
405 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
406 win_data->ovl_width, win_data->ovl_height);
407 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
408 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
409 overlay->fb_width, overlay->crtc_width);
412 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
414 struct fimd_context *ctx = get_fimd_context(dev);
415 struct fimd_win_data *win_data = &ctx->win_data[win];
420 switch (win_data->bpp) {
422 val |= WINCON0_BPPMODE_1BPP;
423 val |= WINCONx_BITSWP;
424 val |= WINCONx_BURSTLEN_4WORD;
427 val |= WINCON0_BPPMODE_2BPP;
428 val |= WINCONx_BITSWP;
429 val |= WINCONx_BURSTLEN_8WORD;
432 val |= WINCON0_BPPMODE_4BPP;
433 val |= WINCONx_BITSWP;
434 val |= WINCONx_BURSTLEN_8WORD;
437 val |= WINCON0_BPPMODE_8BPP_PALETTE;
438 val |= WINCONx_BURSTLEN_8WORD;
439 val |= WINCONx_BYTSWP;
442 val |= WINCON0_BPPMODE_16BPP_565;
443 val |= WINCONx_HAWSWP;
444 val |= WINCONx_BURSTLEN_16WORD;
447 val |= WINCON0_BPPMODE_24BPP_888;
449 val |= WINCONx_BURSTLEN_16WORD;
452 val |= WINCON1_BPPMODE_28BPP_A4888
453 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
455 val |= WINCONx_BURSTLEN_16WORD;
458 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
460 val |= WINCON0_BPPMODE_24BPP_888;
462 val |= WINCONx_BURSTLEN_16WORD;
466 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
468 writel(val, ctx->regs + WINCON(win));
471 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
473 struct fimd_context *ctx = get_fimd_context(dev);
474 unsigned int keycon0 = 0, keycon1 = 0;
476 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
477 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
479 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
481 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
482 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
486 * shadow_protect_win() - disable updating values from shadow registers at vsync
488 * @win: window to protect registers for
489 * @protect: 1 to protect (disable updates)
491 static void fimd_shadow_protect_win(struct fimd_context *ctx,
492 int win, bool protect)
496 if (ctx->driver_data->has_shadowcon) {
498 bits = SHADOWCON_WINx_PROTECT(win);
501 bits = PRTCON_PROTECT;
504 val = readl(ctx->regs + reg);
509 writel(val, ctx->regs + reg);
512 static void fimd_win_commit(struct device *dev, int zpos)
514 struct fimd_context *ctx = get_fimd_context(dev);
515 struct fimd_win_data *win_data;
517 unsigned long val, alpha, size;
524 if (win == DEFAULT_ZPOS)
525 win = ctx->default_win;
527 if (win < 0 || win >= WINDOWS_NR)
530 win_data = &ctx->win_data[win];
533 * SHADOWCON/PRTCON register is used for enabling timing.
535 * for example, once only width value of a register is set,
536 * if the dma is started then fimd hardware could malfunction so
537 * with protect window setting, the register fields with prefix '_F'
538 * wouldn't be updated at vsync also but updated once unprotect window
542 /* protect windows */
543 fimd_shadow_protect_win(ctx, win, true);
545 /* buffer start address */
546 val = (unsigned long)win_data->dma_addr;
547 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
549 /* buffer end address */
550 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
551 val = (unsigned long)(win_data->dma_addr + size);
552 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
554 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
555 (unsigned long)win_data->dma_addr, val, size);
556 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
557 win_data->ovl_width, win_data->ovl_height);
560 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
561 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
562 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
563 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
564 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
567 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
568 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
569 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
570 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
571 writel(val, ctx->regs + VIDOSD_A(win));
573 last_x = win_data->offset_x + win_data->ovl_width;
576 last_y = win_data->offset_y + win_data->ovl_height;
580 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
581 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
583 writel(val, ctx->regs + VIDOSD_B(win));
585 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
586 win_data->offset_x, win_data->offset_y, last_x, last_y);
588 /* hardware window 0 doesn't support alpha channel. */
591 alpha = VIDISD14C_ALPHA1_R(0xf) |
592 VIDISD14C_ALPHA1_G(0xf) |
593 VIDISD14C_ALPHA1_B(0xf);
595 writel(alpha, ctx->regs + VIDOSD_C(win));
599 if (win != 3 && win != 4) {
600 u32 offset = VIDOSD_D(win);
602 offset = VIDOSD_C(win);
603 val = win_data->ovl_width * win_data->ovl_height;
604 writel(val, ctx->regs + offset);
606 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
609 fimd_win_set_pixfmt(dev, win);
611 /* hardware window 0 doesn't support color key. */
613 fimd_win_set_colkey(dev, win);
616 val = readl(ctx->regs + WINCON(win));
617 val |= WINCONx_ENWIN;
618 writel(val, ctx->regs + WINCON(win));
620 /* Enable DMA channel and unprotect windows */
621 fimd_shadow_protect_win(ctx, win, false);
623 if (ctx->driver_data->has_shadowcon) {
624 val = readl(ctx->regs + SHADOWCON);
625 val |= SHADOWCON_CHx_ENABLE(win);
626 writel(val, ctx->regs + SHADOWCON);
629 win_data->enabled = true;
632 static void fimd_win_disable(struct device *dev, int zpos)
634 struct fimd_context *ctx = get_fimd_context(dev);
635 struct fimd_win_data *win_data;
639 if (win == DEFAULT_ZPOS)
640 win = ctx->default_win;
642 if (win < 0 || win >= WINDOWS_NR)
645 win_data = &ctx->win_data[win];
647 if (ctx->suspended) {
648 /* do not resume this window*/
649 win_data->resume = false;
653 /* protect windows */
654 fimd_shadow_protect_win(ctx, win, true);
657 val = readl(ctx->regs + WINCON(win));
658 val &= ~WINCONx_ENWIN;
659 writel(val, ctx->regs + WINCON(win));
661 /* unprotect windows */
662 if (ctx->driver_data->has_shadowcon) {
663 val = readl(ctx->regs + SHADOWCON);
664 val &= ~SHADOWCON_CHx_ENABLE(win);
665 writel(val, ctx->regs + SHADOWCON);
668 fimd_shadow_protect_win(ctx, win, false);
670 win_data->enabled = false;
673 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
674 .mode_set = fimd_win_mode_set,
675 .commit = fimd_win_commit,
676 .disable = fimd_win_disable,
679 static struct exynos_drm_manager fimd_manager = {
681 .ops = &fimd_manager_ops,
682 .overlay_ops = &fimd_overlay_ops,
683 .display_ops = &fimd_display_ops,
686 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
688 struct fimd_context *ctx = (struct fimd_context *)dev_id;
689 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
690 struct drm_device *drm_dev = subdrv->drm_dev;
691 struct exynos_drm_manager *manager = subdrv->manager;
694 val = readl(ctx->regs + VIDINTCON1);
696 if (val & VIDINTCON1_INT_FRAME)
697 /* VSYNC interrupt */
698 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
700 /* check the crtc is detached already from encoder */
701 if (manager->pipe < 0)
704 drm_handle_vblank(drm_dev, manager->pipe);
705 exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe);
707 /* set wait vsync event to zero and wake up queue. */
708 if (atomic_read(&ctx->wait_vsync_event)) {
709 atomic_set(&ctx->wait_vsync_event, 0);
710 DRM_WAKEUP(&ctx->wait_vsync_queue);
716 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
719 * enable drm irq mode.
720 * - with irq_enabled = 1, we can use the vblank feature.
722 * P.S. note that we wouldn't use drm irq handler but
723 * just specific driver own one instead because
724 * drm framework supports only one irq handler.
726 drm_dev->irq_enabled = 1;
729 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
730 * by drm timer once a current process gives up ownership of
731 * vblank event.(after drm_vblank_put function is called)
733 drm_dev->vblank_disable_allowed = 1;
735 /* attach this sub driver to iommu mapping if supported. */
736 if (is_drm_iommu_supported(drm_dev))
737 drm_iommu_attach_device(drm_dev, dev);
742 static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
744 /* detach this sub driver from iommu mapping if supported. */
745 if (is_drm_iommu_supported(drm_dev))
746 drm_iommu_detach_device(drm_dev, dev);
749 static int fimd_calc_clkdiv(struct fimd_context *ctx,
750 struct fb_videomode *timing)
752 unsigned long clk = clk_get_rate(ctx->lcd_clk);
755 u32 best_framerate = 0;
758 retrace = timing->left_margin + timing->hsync_len +
759 timing->right_margin + timing->xres;
760 retrace *= timing->upper_margin + timing->vsync_len +
761 timing->lower_margin + timing->yres;
763 /* default framerate is 60Hz */
764 if (!timing->refresh)
765 timing->refresh = 60;
769 for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
772 /* get best framerate */
773 framerate = clk / clkdiv;
774 tmp = timing->refresh - framerate;
776 best_framerate = framerate;
780 best_framerate = framerate;
781 else if (tmp < (best_framerate - framerate))
782 best_framerate = framerate;
790 static void fimd_clear_win(struct fimd_context *ctx, int win)
792 writel(0, ctx->regs + WINCON(win));
793 writel(0, ctx->regs + VIDOSD_A(win));
794 writel(0, ctx->regs + VIDOSD_B(win));
795 writel(0, ctx->regs + VIDOSD_C(win));
797 if (win == 1 || win == 2)
798 writel(0, ctx->regs + VIDOSD_D(win));
800 fimd_shadow_protect_win(ctx, win, false);
803 static int fimd_clock(struct fimd_context *ctx, bool enable)
808 ret = clk_prepare_enable(ctx->bus_clk);
812 ret = clk_prepare_enable(ctx->lcd_clk);
814 clk_disable_unprepare(ctx->bus_clk);
818 clk_disable_unprepare(ctx->lcd_clk);
819 clk_disable_unprepare(ctx->bus_clk);
825 static void fimd_window_suspend(struct device *dev)
827 struct fimd_context *ctx = get_fimd_context(dev);
828 struct fimd_win_data *win_data;
831 for (i = 0; i < WINDOWS_NR; i++) {
832 win_data = &ctx->win_data[i];
833 win_data->resume = win_data->enabled;
834 fimd_win_disable(dev, i);
836 fimd_wait_for_vblank(dev);
839 static void fimd_window_resume(struct device *dev)
841 struct fimd_context *ctx = get_fimd_context(dev);
842 struct fimd_win_data *win_data;
845 for (i = 0; i < WINDOWS_NR; i++) {
846 win_data = &ctx->win_data[i];
847 win_data->enabled = win_data->resume;
848 win_data->resume = false;
852 static int fimd_activate(struct fimd_context *ctx, bool enable)
854 struct device *dev = ctx->subdrv.dev;
858 ret = fimd_clock(ctx, true);
862 ctx->suspended = false;
864 /* if vblank was enabled status, enable it again. */
865 if (test_and_clear_bit(0, &ctx->irq_flags))
866 fimd_enable_vblank(dev);
868 fimd_window_resume(dev);
870 fimd_window_suspend(dev);
872 fimd_clock(ctx, false);
873 ctx->suspended = true;
879 static int fimd_probe(struct platform_device *pdev)
881 struct device *dev = &pdev->dev;
882 struct fimd_context *ctx;
883 struct exynos_drm_subdrv *subdrv;
884 struct exynos_drm_fimd_pdata *pdata;
885 struct exynos_drm_panel_info *panel;
886 struct resource *res;
891 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
893 DRM_ERROR("memory allocation for pdata failed\n");
897 ret = of_get_fb_videomode(dev->of_node, &pdata->panel.timing,
900 DRM_ERROR("failed: of_get_fb_videomode() : %d\n", ret);
904 pdata = dev->platform_data;
906 DRM_ERROR("no platform data specified\n");
911 panel = &pdata->panel;
913 dev_err(dev, "panel is null.\n");
917 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
921 ctx->bus_clk = devm_clk_get(dev, "fimd");
922 if (IS_ERR(ctx->bus_clk)) {
923 dev_err(dev, "failed to get bus clock\n");
924 return PTR_ERR(ctx->bus_clk);
927 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
928 if (IS_ERR(ctx->lcd_clk)) {
929 dev_err(dev, "failed to get lcd clock\n");
930 return PTR_ERR(ctx->lcd_clk);
933 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
935 ctx->regs = devm_ioremap_resource(dev, res);
936 if (IS_ERR(ctx->regs))
937 return PTR_ERR(ctx->regs);
939 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync");
941 dev_err(dev, "irq request failed.\n");
945 ctx->irq = res->start;
947 ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler,
950 dev_err(dev, "irq request failed.\n");
954 ctx->driver_data = drm_fimd_get_driver_data(pdev);
955 ctx->vidcon0 = pdata->vidcon0;
956 ctx->vidcon1 = pdata->vidcon1;
957 ctx->default_win = pdata->default_win;
959 DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue);
960 atomic_set(&ctx->wait_vsync_event, 0);
962 subdrv = &ctx->subdrv;
965 subdrv->manager = &fimd_manager;
966 subdrv->probe = fimd_subdrv_probe;
967 subdrv->remove = fimd_subdrv_remove;
969 mutex_init(&ctx->lock);
971 platform_set_drvdata(pdev, ctx);
973 pm_runtime_enable(dev);
974 pm_runtime_get_sync(dev);
976 ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
977 panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
979 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
980 panel->timing.pixclock, ctx->clkdiv);
982 for (win = 0; win < WINDOWS_NR; win++)
983 fimd_clear_win(ctx, win);
985 exynos_drm_subdrv_register(subdrv);
990 static int fimd_remove(struct platform_device *pdev)
992 struct device *dev = &pdev->dev;
993 struct fimd_context *ctx = platform_get_drvdata(pdev);
995 exynos_drm_subdrv_unregister(&ctx->subdrv);
1000 pm_runtime_set_suspended(dev);
1001 pm_runtime_put_sync(dev);
1004 pm_runtime_disable(dev);
1009 #ifdef CONFIG_PM_SLEEP
1010 static int fimd_suspend(struct device *dev)
1012 struct fimd_context *ctx = get_fimd_context(dev);
1015 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
1016 * called here, an error would be returned by that interface
1017 * because the usage_count of pm runtime is more than 1.
1019 if (!pm_runtime_suspended(dev))
1020 return fimd_activate(ctx, false);
1025 static int fimd_resume(struct device *dev)
1027 struct fimd_context *ctx = get_fimd_context(dev);
1030 * if entered to sleep when lcd panel was on, the usage_count
1031 * of pm runtime would still be 1 so in this case, fimd driver
1032 * should be on directly not drawing on pm runtime interface.
1034 if (!pm_runtime_suspended(dev)) {
1037 ret = fimd_activate(ctx, true);
1042 * in case of dpms on(standby), fimd_apply function will
1043 * be called by encoder's dpms callback to update fimd's
1044 * registers but in case of sleep wakeup, it's not.
1045 * so fimd_apply function should be called at here.
1054 #ifdef CONFIG_PM_RUNTIME
1055 static int fimd_runtime_suspend(struct device *dev)
1057 struct fimd_context *ctx = get_fimd_context(dev);
1059 return fimd_activate(ctx, false);
1062 static int fimd_runtime_resume(struct device *dev)
1064 struct fimd_context *ctx = get_fimd_context(dev);
1066 return fimd_activate(ctx, true);
1070 static struct platform_device_id fimd_driver_ids[] = {
1072 .name = "s3c64xx-fb",
1073 .driver_data = (unsigned long)&s3c64xx_fimd_driver_data,
1075 .name = "exynos4-fb",
1076 .driver_data = (unsigned long)&exynos4_fimd_driver_data,
1078 .name = "exynos5-fb",
1079 .driver_data = (unsigned long)&exynos5_fimd_driver_data,
1084 static const struct dev_pm_ops fimd_pm_ops = {
1085 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1086 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1089 struct platform_driver fimd_driver = {
1090 .probe = fimd_probe,
1091 .remove = fimd_remove,
1092 .id_table = fimd_driver_ids,
1094 .name = "exynos4-fb",
1095 .owner = THIS_MODULE,
1097 .of_match_table = of_match_ptr(fimd_driver_dt_match),