arch/arm/mach-omap2/cpuidle44xx.c

   1 /*
   2  * OMAP4 CPU idle Routines
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  * Rajendra Nayak <rnayak@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/sched.h>
  14 #include <linux/cpuidle.h>
  15 #include <linux/cpu_pm.h>
  16 #include <linux/export.h>
  17 #include <linux/clockchips.h>
  18
  19 #include <asm/proc-fns.h>
  20
  21 #include "common.h"
  22 #include "pm.h"
  23 #include "prm.h"
  24
  25 #ifdef CONFIG_CPU_IDLE
  26
  27 /* Machine specific information to be recorded in the C-state driver_data */
  28 struct omap4_idle_statedata {
  29         u32 cpu_state;
  30         u32 mpu_logic_state;
  31         u32 mpu_state;
  32         u8 valid;
  33 };
  34
  35 static struct cpuidle_params cpuidle_params_table[] = {
  36         /* C1 - CPU0 ON + CPU1 ON + MPU ON */
  37         {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
  38         /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
  39         {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
  40         /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
  41         {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
  42 };
  43
  44 #define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
  45
  46 struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
  47 static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
  48
  49 /**
  50  * omap4_enter_idle - Programs OMAP4 to enter the specified state
  51  * @dev: cpuidle device
  52  * @drv: cpuidle driver
  53  * @index: the index of state to be entered
  54  *
  55  * Called from the CPUidle framework to program the device to the
  56  * specified low power state selected by the governor.
  57  * Returns the amount of time spent in the low power state.
  58  */
  59 static int omap4_enter_idle(struct cpuidle_device *dev,
  60                         struct cpuidle_driver *drv,
  61                         int index)
  62 {
  63         struct omap4_idle_statedata *cx =
  64                         cpuidle_get_statedata(&dev->states_usage[index]);
  65         struct timespec ts_preidle, ts_postidle, ts_idle;
  66         u32 cpu1_state;
  67         int idle_time;
  68         int new_state_idx;
  69         int cpu_id = smp_processor_id();
  70
  71         /* Used to keep track of the total time in idle */
  72         getnstimeofday(&ts_preidle);
  73
  74         local_irq_disable();
  75         local_fiq_disable();
  76
  77         /*
  78          * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
  79          * This is necessary to honour hardware recommondation
  80          * of triggeing all the possible low power modes once CPU1 is
  81          * out of coherency and in OFF mode.
  82          * Update dev->last_state so that governor stats reflects right
  83          * data.
  84          */
  85         cpu1_state = pwrdm_read_pwrst(cpu1_pd);
  86         if (cpu1_state != PWRDM_POWER_OFF) {
  87                 new_state_idx = drv->safe_state_index;
  88                 cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
  89         }
  90
  91         if (index > 0)
  92                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
  93
  94         /*
  95          * Call idle CPU PM enter notifier chain so that
  96          * VFP and per CPU interrupt context is saved.
  97          */
  98         if (cx->cpu_state == PWRDM_POWER_OFF)
  99                 cpu_pm_enter();
 100
 101         pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
 102         omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
 103
 104         /*
 105          * Call idle CPU cluster PM enter notifier chain
 106          * to save GIC and wakeupgen context.
 107          */
 108         if ((cx->mpu_state == PWRDM_POWER_RET) &&
 109                 (cx->mpu_logic_state == PWRDM_POWER_OFF))
 110                         cpu_cluster_pm_enter();
 111
 112         omap4_enter_lowpower(dev->cpu, cx->cpu_state);
 113
 114         /*
 115          * Call idle CPU PM exit notifier chain to restore
 116          * VFP and per CPU IRQ context. Only CPU0 state is
 117          * considered since CPU1 is managed by CPU hotplug.
 118          */
 119         if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
 120                 cpu_pm_exit();
 121
 122         /*
 123          * Call idle CPU cluster PM exit notifier chain
 124          * to restore GIC and wakeupgen context.
 125          */
 126         if (omap4_mpuss_read_prev_context_state())
 127                 cpu_cluster_pm_exit();
 128
 129         if (index > 0)
 130                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
 131
 132         getnstimeofday(&ts_postidle);
 133         ts_idle = timespec_sub(ts_postidle, ts_preidle);
 134
 135         local_irq_enable();
 136         local_fiq_enable();
 137
 138         idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
 139                                                                 USEC_PER_SEC;
 140
 141         /* Update cpuidle counters */
 142         dev->last_residency = idle_time;
 143
 144         return index;
 145 }
 146
 147 DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
 148
 149 struct cpuidle_driver omap4_idle_driver = {
 150         .name =         "omap4_idle",
 151         .owner =        THIS_MODULE,
 152 };
 153
 154 static inline void _fill_cstate(struct cpuidle_driver *drv,
 155                                         int idx, const char *descr)
 156 {
 157         struct cpuidle_state *state = &drv->states[idx];
 158
 159         state->exit_latency     = cpuidle_params_table[idx].exit_latency;
 160         state->target_residency = cpuidle_params_table[idx].target_residency;
 161         state->flags            = CPUIDLE_FLAG_TIME_VALID;
 162         state->enter            = omap4_enter_idle;
 163         sprintf(state->name, "C%d", idx + 1);
 164         strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
 165 }
 166
 167 static inline struct omap4_idle_statedata *_fill_cstate_usage(
 168                                         struct cpuidle_device *dev,
 169                                         int idx)
 170 {
 171         struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
 172         struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
 173
 174         cx->valid               = cpuidle_params_table[idx].valid;
 175         cpuidle_set_statedata(state_usage, cx);
 176
 177         return cx;
 178 }
 179
 180
 181
 182 /**
 183  * omap4_idle_init - Init routine for OMAP4 idle
 184  *
 185  * Registers the OMAP4 specific cpuidle driver to the cpuidle
 186  * framework with the valid set of states.
 187  */
 188 int __init omap4_idle_init(void)
 189 {
 190         struct omap4_idle_statedata *cx;
 191         struct cpuidle_device *dev;
 192         struct cpuidle_driver *drv = &omap4_idle_driver;
 193         unsigned int cpu_id = 0;
 194
 195         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 196         cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
 197         cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
 198         if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
 199                 return -ENODEV;
 200
 201
 202         drv->safe_state_index = -1;
 203         dev = &per_cpu(omap4_idle_dev, cpu_id);
 204         dev->cpu = cpu_id;
 205
 206         /* C1 - CPU0 ON + CPU1 ON + MPU ON */
 207         _fill_cstate(drv, 0, "MPUSS ON");
 208         drv->safe_state_index = 0;
 209         cx = _fill_cstate_usage(dev, 0);
 210         cx->valid = 1;  /* C1 is always valid */
 211         cx->cpu_state = PWRDM_POWER_ON;
 212         cx->mpu_state = PWRDM_POWER_ON;
 213         cx->mpu_logic_state = PWRDM_POWER_RET;
 214
 215         /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
 216         _fill_cstate(drv, 1, "MPUSS CSWR");
 217         cx = _fill_cstate_usage(dev, 1);
 218         cx->cpu_state = PWRDM_POWER_OFF;
 219         cx->mpu_state = PWRDM_POWER_RET;
 220         cx->mpu_logic_state = PWRDM_POWER_RET;
 221
 222         /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
 223         _fill_cstate(drv, 2, "MPUSS OSWR");
 224         cx = _fill_cstate_usage(dev, 2);
 225         cx->cpu_state = PWRDM_POWER_OFF;
 226         cx->mpu_state = PWRDM_POWER_RET;
 227         cx->mpu_logic_state = PWRDM_POWER_OFF;
 228
 229         drv->state_count = OMAP4_NUM_STATES;
 230         cpuidle_register_driver(&omap4_idle_driver);
 231
 232         dev->state_count = OMAP4_NUM_STATES;
 233         if (cpuidle_register_device(dev)) {
 234                 pr_err("%s: CPUidle register device failed\n", __func__);
 235                         return -EIO;
 236                 }
 237
 238         return 0;
 239 }
 240 #else
 241 int __init omap4_idle_init(void)
 242 {
 243         return 0;
 244 }
 245 #endif /* CONFIG_CPU_IDLE */