drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * intel_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674                                     enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694                 return;
1695         }
1696         reg = TRANSCONF(pipe);
1697         val = I915_READ(reg);
1698         pipeconf_val = I915_READ(PIPECONF(pipe));
1699
1700         if (HAS_PCH_IBX(dev_priv->dev)) {
1701                 /*
1702                  * make the BPC in transcoder be consistent with
1703                  * that in pipeconf reg.
1704                  */
1705                 val &= ~PIPE_BPC_MASK;
1706                 val |= pipeconf_val & PIPE_BPC_MASK;
1707         }
1708
1709         val &= ~TRANS_INTERLACE_MASK;
1710         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711                 if (HAS_PCH_IBX(dev_priv->dev) &&
1712                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713                         val |= TRANS_LEGACY_INTERLACED_ILK;
1714                 else
1715                         val |= TRANS_INTERLACED;
1716         else
1717                 val |= TRANS_PROGRESSIVE;
1718
1719         I915_WRITE(reg, val | TRANS_ENABLE);
1720         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722 }
1723
1724 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725                                      enum pipe pipe)
1726 {
1727         int reg;
1728         u32 val;
1729
1730         /* FDI relies on the transcoder */
1731         assert_fdi_tx_disabled(dev_priv, pipe);
1732         assert_fdi_rx_disabled(dev_priv, pipe);
1733
1734         /* Ports must be off as well */
1735         assert_pch_ports_disabled(dev_priv, pipe);
1736
1737         reg = TRANSCONF(pipe);
1738         val = I915_READ(reg);
1739         val &= ~TRANS_ENABLE;
1740         I915_WRITE(reg, val);
1741         /* wait for PCH transcoder off, transcoder state */
1742         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1743                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1744 }
1745
1746 /**
1747  * intel_enable_pipe - enable a pipe, asserting requirements
1748  * @dev_priv: i915 private structure
1749  * @pipe: pipe to enable
1750  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1751  *
1752  * Enable @pipe, making sure that various hardware specific requirements
1753  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754  *
1755  * @pipe should be %PIPE_A or %PIPE_B.
1756  *
1757  * Will wait until the pipe is actually running (i.e. first vblank) before
1758  * returning.
1759  */
1760 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761                               bool pch_port)
1762 {
1763         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764                                                                       pipe);
1765         int reg;
1766         u32 val;
1767
1768         /*
1769          * A pipe without a PLL won't actually be able to drive bits from
1770          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1771          * need the check.
1772          */
1773         if (!HAS_PCH_SPLIT(dev_priv->dev))
1774                 assert_pll_enabled(dev_priv, pipe);
1775         else {
1776                 if (pch_port) {
1777                         /* if driving the PCH, we need FDI enabled */
1778                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780                 }
1781                 /* FIXME: assert CPU port conditions for SNB+ */
1782         }
1783
1784         reg = PIPECONF(cpu_transcoder);
1785         val = I915_READ(reg);
1786         if (val & PIPECONF_ENABLE)
1787                 return;
1788
1789         I915_WRITE(reg, val | PIPECONF_ENABLE);
1790         intel_wait_for_vblank(dev_priv->dev, pipe);
1791 }
1792
1793 /**
1794  * intel_disable_pipe - disable a pipe, asserting requirements
1795  * @dev_priv: i915 private structure
1796  * @pipe: pipe to disable
1797  *
1798  * Disable @pipe, making sure that various hardware specific requirements
1799  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800  *
1801  * @pipe should be %PIPE_A or %PIPE_B.
1802  *
1803  * Will wait until the pipe has shut down before returning.
1804  */
1805 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806                                enum pipe pipe)
1807 {
1808         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809                                                                       pipe);
1810         int reg;
1811         u32 val;
1812
1813         /*
1814          * Make sure planes won't keep trying to pump pixels to us,
1815          * or we might hang the display.
1816          */
1817         assert_planes_disabled(dev_priv, pipe);
1818
1819         /* Don't disable pipe A or pipe A PLLs if needed */
1820         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821                 return;
1822
1823         reg = PIPECONF(cpu_transcoder);
1824         val = I915_READ(reg);
1825         if ((val & PIPECONF_ENABLE) == 0)
1826                 return;
1827
1828         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1829         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830 }
1831
1832 /*
1833  * Plane regs are double buffered, going from enabled->disabled needs a
1834  * trigger in order to latch.  The display address reg provides this.
1835  */
1836 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1837                                       enum plane plane)
1838 {
1839         if (dev_priv->info->gen >= 4)
1840                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841         else
1842                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1843 }
1844
1845 /**
1846  * intel_enable_plane - enable a display plane on a given pipe
1847  * @dev_priv: i915 private structure
1848  * @plane: plane to enable
1849  * @pipe: pipe being fed
1850  *
1851  * Enable @plane on @pipe, making sure that @pipe is running first.
1852  */
1853 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1854                                enum plane plane, enum pipe pipe)
1855 {
1856         int reg;
1857         u32 val;
1858
1859         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860         assert_pipe_enabled(dev_priv, pipe);
1861
1862         reg = DSPCNTR(plane);
1863         val = I915_READ(reg);
1864         if (val & DISPLAY_PLANE_ENABLE)
1865                 return;
1866
1867         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1868         intel_flush_display_plane(dev_priv, plane);
1869         intel_wait_for_vblank(dev_priv->dev, pipe);
1870 }
1871
1872 /**
1873  * intel_disable_plane - disable a display plane
1874  * @dev_priv: i915 private structure
1875  * @plane: plane to disable
1876  * @pipe: pipe consuming the data
1877  *
1878  * Disable @plane; should be an independent operation.
1879  */
1880 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1881                                 enum plane plane, enum pipe pipe)
1882 {
1883         int reg;
1884         u32 val;
1885
1886         reg = DSPCNTR(plane);
1887         val = I915_READ(reg);
1888         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1889                 return;
1890
1891         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1892         intel_flush_display_plane(dev_priv, plane);
1893         intel_wait_for_vblank(dev_priv->dev, pipe);
1894 }
1895
1896 int
1897 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1898                            struct drm_i915_gem_object *obj,
1899                            struct intel_ring_buffer *pipelined)
1900 {
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         u32 alignment;
1903         int ret;
1904
1905         switch (obj->tiling_mode) {
1906         case I915_TILING_NONE:
1907                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908                         alignment = 128 * 1024;
1909                 else if (INTEL_INFO(dev)->gen >= 4)
1910                         alignment = 4 * 1024;
1911                 else
1912                         alignment = 64 * 1024;
1913                 break;
1914         case I915_TILING_X:
1915                 /* pin() will align the object as required by fence */
1916                 alignment = 0;
1917                 break;
1918         case I915_TILING_Y:
1919                 /* FIXME: Is this true? */
1920                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1921                 return -EINVAL;
1922         default:
1923                 BUG();
1924         }
1925
1926         dev_priv->mm.interruptible = false;
1927         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1928         if (ret)
1929                 goto err_interruptible;
1930
1931         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932          * fence, whereas 965+ only requires a fence if using
1933          * framebuffer compression.  For simplicity, we always install
1934          * a fence as the cost is not that onerous.
1935          */
1936         ret = i915_gem_object_get_fence(obj);
1937         if (ret)
1938                 goto err_unpin;
1939
1940         i915_gem_object_pin_fence(obj);
1941
1942         dev_priv->mm.interruptible = true;
1943         return 0;
1944
1945 err_unpin:
1946         i915_gem_object_unpin(obj);
1947 err_interruptible:
1948         dev_priv->mm.interruptible = true;
1949         return ret;
1950 }
1951
1952 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1953 {
1954         i915_gem_object_unpin_fence(obj);
1955         i915_gem_object_unpin(obj);
1956 }
1957
1958 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959  * is assumed to be a power-of-two. */
1960 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1961                                                unsigned int bpp,
1962                                                unsigned int pitch)
1963 {
1964         int tile_rows, tiles;
1965
1966         tile_rows = *y / 8;
1967         *y %= 8;
1968         tiles = *x / (512/bpp);
1969         *x %= 512/bpp;
1970
1971         return tile_rows * pitch * 8 + tiles * 4096;
1972 }
1973
1974 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975                              int x, int y)
1976 {
1977         struct drm_device *dev = crtc->dev;
1978         struct drm_i915_private *dev_priv = dev->dev_private;
1979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980         struct intel_framebuffer *intel_fb;
1981         struct drm_i915_gem_object *obj;
1982         int plane = intel_crtc->plane;
1983         unsigned long linear_offset;
1984         u32 dspcntr;
1985         u32 reg;
1986
1987         switch (plane) {
1988         case 0:
1989         case 1:
1990                 break;
1991         default:
1992                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1993                 return -EINVAL;
1994         }
1995
1996         intel_fb = to_intel_framebuffer(fb);
1997         obj = intel_fb->obj;
1998
1999         reg = DSPCNTR(plane);
2000         dspcntr = I915_READ(reg);
2001         /* Mask out pixel format bits in case we change it */
2002         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2003         switch (fb->pixel_format) {
2004         case DRM_FORMAT_C8:
2005                 dspcntr |= DISPPLANE_8BPP;
2006                 break;
2007         case DRM_FORMAT_XRGB1555:
2008         case DRM_FORMAT_ARGB1555:
2009                 dspcntr |= DISPPLANE_BGRX555;
2010                 break;
2011         case DRM_FORMAT_RGB565:
2012                 dspcntr |= DISPPLANE_BGRX565;
2013                 break;
2014         case DRM_FORMAT_XRGB8888:
2015         case DRM_FORMAT_ARGB8888:
2016                 dspcntr |= DISPPLANE_BGRX888;
2017                 break;
2018         case DRM_FORMAT_XBGR8888:
2019         case DRM_FORMAT_ABGR8888:
2020                 dspcntr |= DISPPLANE_RGBX888;
2021                 break;
2022         case DRM_FORMAT_XRGB2101010:
2023         case DRM_FORMAT_ARGB2101010:
2024                 dspcntr |= DISPPLANE_BGRX101010;
2025                 break;
2026         case DRM_FORMAT_XBGR2101010:
2027         case DRM_FORMAT_ABGR2101010:
2028                 dspcntr |= DISPPLANE_RGBX101010;
2029                 break;
2030         default:
2031                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2032                 return -EINVAL;
2033         }
2034
2035         if (INTEL_INFO(dev)->gen >= 4) {
2036                 if (obj->tiling_mode != I915_TILING_NONE)
2037                         dspcntr |= DISPPLANE_TILED;
2038                 else
2039                         dspcntr &= ~DISPPLANE_TILED;
2040         }
2041
2042         I915_WRITE(reg, dspcntr);
2043
2044         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2045
2046         if (INTEL_INFO(dev)->gen >= 4) {
2047                 intel_crtc->dspaddr_offset =
2048                         intel_gen4_compute_offset_xtiled(&x, &y,
2049                                                          fb->bits_per_pixel / 8,
2050                                                          fb->pitches[0]);
2051                 linear_offset -= intel_crtc->dspaddr_offset;
2052         } else {
2053                 intel_crtc->dspaddr_offset = linear_offset;
2054         }
2055
2056         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2057                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2058         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2059         if (INTEL_INFO(dev)->gen >= 4) {
2060                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2061                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2062                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2063                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2064         } else
2065                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2066         POSTING_READ(reg);
2067
2068         return 0;
2069 }
2070
2071 static int ironlake_update_plane(struct drm_crtc *crtc,
2072                                  struct drm_framebuffer *fb, int x, int y)
2073 {
2074         struct drm_device *dev = crtc->dev;
2075         struct drm_i915_private *dev_priv = dev->dev_private;
2076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077         struct intel_framebuffer *intel_fb;
2078         struct drm_i915_gem_object *obj;
2079         int plane = intel_crtc->plane;
2080         unsigned long linear_offset;
2081         u32 dspcntr;
2082         u32 reg;
2083
2084         switch (plane) {
2085         case 0:
2086         case 1:
2087         case 2:
2088                 break;
2089         default:
2090                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091                 return -EINVAL;
2092         }
2093
2094         intel_fb = to_intel_framebuffer(fb);
2095         obj = intel_fb->obj;
2096
2097         reg = DSPCNTR(plane);
2098         dspcntr = I915_READ(reg);
2099         /* Mask out pixel format bits in case we change it */
2100         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2101         switch (fb->pixel_format) {
2102         case DRM_FORMAT_C8:
2103                 dspcntr |= DISPPLANE_8BPP;
2104                 break;
2105         case DRM_FORMAT_RGB565:
2106                 dspcntr |= DISPPLANE_BGRX565;
2107                 break;
2108         case DRM_FORMAT_XRGB8888:
2109         case DRM_FORMAT_ARGB8888:
2110                 dspcntr |= DISPPLANE_BGRX888;
2111                 break;
2112         case DRM_FORMAT_XBGR8888:
2113         case DRM_FORMAT_ABGR8888:
2114                 dspcntr |= DISPPLANE_RGBX888;
2115                 break;
2116         case DRM_FORMAT_XRGB2101010:
2117         case DRM_FORMAT_ARGB2101010:
2118                 dspcntr |= DISPPLANE_BGRX101010;
2119                 break;
2120         case DRM_FORMAT_XBGR2101010:
2121         case DRM_FORMAT_ABGR2101010:
2122                 dspcntr |= DISPPLANE_RGBX101010;
2123                 break;
2124         default:
2125                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2126                 return -EINVAL;
2127         }
2128
2129         if (obj->tiling_mode != I915_TILING_NONE)
2130                 dspcntr |= DISPPLANE_TILED;
2131         else
2132                 dspcntr &= ~DISPPLANE_TILED;
2133
2134         /* must disable */
2135         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137         I915_WRITE(reg, dspcntr);
2138
2139         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2140         intel_crtc->dspaddr_offset =
2141                 intel_gen4_compute_offset_xtiled(&x, &y,
2142                                                  fb->bits_per_pixel / 8,
2143                                                  fb->pitches[0]);
2144         linear_offset -= intel_crtc->dspaddr_offset;
2145
2146         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2148         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2149         I915_MODIFY_DISPBASE(DSPSURF(plane),
2150                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2151         if (IS_HASWELL(dev)) {
2152                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2153         } else {
2154                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2155                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2156         }
2157         POSTING_READ(reg);
2158
2159         return 0;
2160 }
2161
2162 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2163 static int
2164 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2165                            int x, int y, enum mode_set_atomic state)
2166 {
2167         struct drm_device *dev = crtc->dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169
2170         if (dev_priv->display.disable_fbc)
2171                 dev_priv->display.disable_fbc(dev);
2172         intel_increase_pllclock(crtc);
2173
2174         return dev_priv->display.update_plane(crtc, fb, x, y);
2175 }
2176
2177 static int
2178 intel_finish_fb(struct drm_framebuffer *old_fb)
2179 {
2180         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2181         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2182         bool was_interruptible = dev_priv->mm.interruptible;
2183         int ret;
2184
2185         wait_event(dev_priv->pending_flip_queue,
2186                    atomic_read(&dev_priv->mm.wedged) ||
2187                    atomic_read(&obj->pending_flip) == 0);
2188
2189         /* Big Hammer, we also need to ensure that any pending
2190          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2191          * current scanout is retired before unpinning the old
2192          * framebuffer.
2193          *
2194          * This should only fail upon a hung GPU, in which case we
2195          * can safely continue.
2196          */
2197         dev_priv->mm.interruptible = false;
2198         ret = i915_gem_object_finish_gpu(obj);
2199         dev_priv->mm.interruptible = was_interruptible;
2200
2201         return ret;
2202 }
2203
2204 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2205 {
2206         struct drm_device *dev = crtc->dev;
2207         struct drm_i915_master_private *master_priv;
2208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209
2210         if (!dev->primary->master)
2211                 return;
2212
2213         master_priv = dev->primary->master->driver_priv;
2214         if (!master_priv->sarea_priv)
2215                 return;
2216
2217         switch (intel_crtc->pipe) {
2218         case 0:
2219                 master_priv->sarea_priv->pipeA_x = x;
2220                 master_priv->sarea_priv->pipeA_y = y;
2221                 break;
2222         case 1:
2223                 master_priv->sarea_priv->pipeB_x = x;
2224                 master_priv->sarea_priv->pipeB_y = y;
2225                 break;
2226         default:
2227                 break;
2228         }
2229 }
2230
2231 static int
2232 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2233                     struct drm_framebuffer *fb)
2234 {
2235         struct drm_device *dev = crtc->dev;
2236         struct drm_i915_private *dev_priv = dev->dev_private;
2237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2238         struct drm_framebuffer *old_fb;
2239         int ret;
2240
2241         /* no fb bound */
2242         if (!fb) {
2243                 DRM_ERROR("No FB bound\n");
2244                 return 0;
2245         }
2246
2247         if(intel_crtc->plane > dev_priv->num_pipe) {
2248                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2249                                 intel_crtc->plane,
2250                                 dev_priv->num_pipe);
2251                 return -EINVAL;
2252         }
2253
2254         mutex_lock(&dev->struct_mutex);
2255         ret = intel_pin_and_fence_fb_obj(dev,
2256                                          to_intel_framebuffer(fb)->obj,
2257                                          NULL);
2258         if (ret != 0) {
2259                 mutex_unlock(&dev->struct_mutex);
2260                 DRM_ERROR("pin & fence failed\n");
2261                 return ret;
2262         }
2263
2264         if (crtc->fb)
2265                 intel_finish_fb(crtc->fb);
2266
2267         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2268         if (ret) {
2269                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2270                 mutex_unlock(&dev->struct_mutex);
2271                 DRM_ERROR("failed to update base address\n");
2272                 return ret;
2273         }
2274
2275         old_fb = crtc->fb;
2276         crtc->fb = fb;
2277         crtc->x = x;
2278         crtc->y = y;
2279
2280         if (old_fb) {
2281                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2282                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2283         }
2284
2285         intel_update_fbc(dev);
2286         mutex_unlock(&dev->struct_mutex);
2287
2288         intel_crtc_update_sarea_pos(crtc, x, y);
2289
2290         return 0;
2291 }
2292
2293 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2294 {
2295         struct drm_device *dev = crtc->dev;
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         u32 dpa_ctl;
2298
2299         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2300         dpa_ctl = I915_READ(DP_A);
2301         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2302
2303         if (clock < 200000) {
2304                 u32 temp;
2305                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2306                 /* workaround for 160Mhz:
2307                    1) program 0x4600c bits 15:0 = 0x8124
2308                    2) program 0x46010 bit 0 = 1
2309                    3) program 0x46034 bit 24 = 1
2310                    4) program 0x64000 bit 14 = 1
2311                    */
2312                 temp = I915_READ(0x4600c);
2313                 temp &= 0xffff0000;
2314                 I915_WRITE(0x4600c, temp | 0x8124);
2315
2316                 temp = I915_READ(0x46010);
2317                 I915_WRITE(0x46010, temp | 1);
2318
2319                 temp = I915_READ(0x46034);
2320                 I915_WRITE(0x46034, temp | (1 << 24));
2321         } else {
2322                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2323         }
2324         I915_WRITE(DP_A, dpa_ctl);
2325
2326         POSTING_READ(DP_A);
2327         udelay(500);
2328 }
2329
2330 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2331 {
2332         struct drm_device *dev = crtc->dev;
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335         int pipe = intel_crtc->pipe;
2336         u32 reg, temp;
2337
2338         /* enable normal train */
2339         reg = FDI_TX_CTL(pipe);
2340         temp = I915_READ(reg);
2341         if (IS_IVYBRIDGE(dev)) {
2342                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2343                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2344         } else {
2345                 temp &= ~FDI_LINK_TRAIN_NONE;
2346                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2347         }
2348         I915_WRITE(reg, temp);
2349
2350         reg = FDI_RX_CTL(pipe);
2351         temp = I915_READ(reg);
2352         if (HAS_PCH_CPT(dev)) {
2353                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2354                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2355         } else {
2356                 temp &= ~FDI_LINK_TRAIN_NONE;
2357                 temp |= FDI_LINK_TRAIN_NONE;
2358         }
2359         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2360
2361         /* wait one idle pattern time */
2362         POSTING_READ(reg);
2363         udelay(1000);
2364
2365         /* IVB wants error correction enabled */
2366         if (IS_IVYBRIDGE(dev))
2367                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2368                            FDI_FE_ERRC_ENABLE);
2369 }
2370
2371 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2372 {
2373         struct drm_i915_private *dev_priv = dev->dev_private;
2374         u32 flags = I915_READ(SOUTH_CHICKEN1);
2375
2376         flags |= FDI_PHASE_SYNC_OVR(pipe);
2377         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2378         flags |= FDI_PHASE_SYNC_EN(pipe);
2379         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2380         POSTING_READ(SOUTH_CHICKEN1);
2381 }
2382
2383 static void ivb_modeset_global_resources(struct drm_device *dev)
2384 {
2385         struct drm_i915_private *dev_priv = dev->dev_private;
2386         struct intel_crtc *pipe_B_crtc =
2387                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2388         struct intel_crtc *pipe_C_crtc =
2389                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2390         uint32_t temp;
2391
2392         /* When everything is off disable fdi C so that we could enable fdi B
2393          * with all lanes. XXX: This misses the case where a pipe is not using
2394          * any pch resources and so doesn't need any fdi lanes. */
2395         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2396                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2397                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2398
2399                 temp = I915_READ(SOUTH_CHICKEN1);
2400                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2401                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2402                 I915_WRITE(SOUTH_CHICKEN1, temp);
2403         }
2404 }
2405
2406 /* The FDI link training functions for ILK/Ibexpeak. */
2407 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2408 {
2409         struct drm_device *dev = crtc->dev;
2410         struct drm_i915_private *dev_priv = dev->dev_private;
2411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412         int pipe = intel_crtc->pipe;
2413         int plane = intel_crtc->plane;
2414         u32 reg, temp, tries;
2415
2416         /* FDI needs bits from pipe & plane first */
2417         assert_pipe_enabled(dev_priv, pipe);
2418         assert_plane_enabled(dev_priv, plane);
2419
2420         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2421            for train result */
2422         reg = FDI_RX_IMR(pipe);
2423         temp = I915_READ(reg);
2424         temp &= ~FDI_RX_SYMBOL_LOCK;
2425         temp &= ~FDI_RX_BIT_LOCK;
2426         I915_WRITE(reg, temp);
2427         I915_READ(reg);
2428         udelay(150);
2429
2430         /* enable CPU FDI TX and PCH FDI RX */
2431         reg = FDI_TX_CTL(pipe);
2432         temp = I915_READ(reg);
2433         temp &= ~(7 << 19);
2434         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2435         temp &= ~FDI_LINK_TRAIN_NONE;
2436         temp |= FDI_LINK_TRAIN_PATTERN_1;
2437         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2438
2439         reg = FDI_RX_CTL(pipe);
2440         temp = I915_READ(reg);
2441         temp &= ~FDI_LINK_TRAIN_NONE;
2442         temp |= FDI_LINK_TRAIN_PATTERN_1;
2443         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2444
2445         POSTING_READ(reg);
2446         udelay(150);
2447
2448         /* Ironlake workaround, enable clock pointer after FDI enable*/
2449         if (HAS_PCH_IBX(dev)) {
2450                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2451                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2452                            FDI_RX_PHASE_SYNC_POINTER_EN);
2453         }
2454
2455         reg = FDI_RX_IIR(pipe);
2456         for (tries = 0; tries < 5; tries++) {
2457                 temp = I915_READ(reg);
2458                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460                 if ((temp & FDI_RX_BIT_LOCK)) {
2461                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2462                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2463                         break;
2464                 }
2465         }
2466         if (tries == 5)
2467                 DRM_ERROR("FDI train 1 fail!\n");
2468
2469         /* Train 2 */
2470         reg = FDI_TX_CTL(pipe);
2471         temp = I915_READ(reg);
2472         temp &= ~FDI_LINK_TRAIN_NONE;
2473         temp |= FDI_LINK_TRAIN_PATTERN_2;
2474         I915_WRITE(reg, temp);
2475
2476         reg = FDI_RX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~FDI_LINK_TRAIN_NONE;
2479         temp |= FDI_LINK_TRAIN_PATTERN_2;
2480         I915_WRITE(reg, temp);
2481
2482         POSTING_READ(reg);
2483         udelay(150);
2484
2485         reg = FDI_RX_IIR(pipe);
2486         for (tries = 0; tries < 5; tries++) {
2487                 temp = I915_READ(reg);
2488                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490                 if (temp & FDI_RX_SYMBOL_LOCK) {
2491                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2492                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2493                         break;
2494                 }
2495         }
2496         if (tries == 5)
2497                 DRM_ERROR("FDI train 2 fail!\n");
2498
2499         DRM_DEBUG_KMS("FDI train done\n");
2500
2501 }
2502
2503 static const int snb_b_fdi_train_param[] = {
2504         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508 };
2509
2510 /* The FDI link training functions for SNB/Cougarpoint. */
2511 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         struct drm_i915_private *dev_priv = dev->dev_private;
2515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516         int pipe = intel_crtc->pipe;
2517         u32 reg, temp, i, retry;
2518
2519         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520            for train result */
2521         reg = FDI_RX_IMR(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_RX_SYMBOL_LOCK;
2524         temp &= ~FDI_RX_BIT_LOCK;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         /* enable CPU FDI TX and PCH FDI RX */
2531         reg = FDI_TX_CTL(pipe);
2532         temp = I915_READ(reg);
2533         temp &= ~(7 << 19);
2534         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2535         temp &= ~FDI_LINK_TRAIN_NONE;
2536         temp |= FDI_LINK_TRAIN_PATTERN_1;
2537         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538         /* SNB-B */
2539         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2540         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2541
2542         I915_WRITE(FDI_RX_MISC(pipe),
2543                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
2545         reg = FDI_RX_CTL(pipe);
2546         temp = I915_READ(reg);
2547         if (HAS_PCH_CPT(dev)) {
2548                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550         } else {
2551                 temp &= ~FDI_LINK_TRAIN_NONE;
2552                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553         }
2554         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556         POSTING_READ(reg);
2557         udelay(150);
2558
2559         if (HAS_PCH_CPT(dev))
2560                 cpt_phase_pointer_enable(dev, pipe);
2561
2562         for (i = 0; i < 4; i++) {
2563                 reg = FDI_TX_CTL(pipe);
2564                 temp = I915_READ(reg);
2565                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566                 temp |= snb_b_fdi_train_param[i];
2567                 I915_WRITE(reg, temp);
2568
2569                 POSTING_READ(reg);
2570                 udelay(500);
2571
2572                 for (retry = 0; retry < 5; retry++) {
2573                         reg = FDI_RX_IIR(pipe);
2574                         temp = I915_READ(reg);
2575                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576                         if (temp & FDI_RX_BIT_LOCK) {
2577                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2578                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579                                 break;
2580                         }
2581                         udelay(50);
2582                 }
2583                 if (retry < 5)
2584                         break;
2585         }
2586         if (i == 4)
2587                 DRM_ERROR("FDI train 1 fail!\n");
2588
2589         /* Train 2 */
2590         reg = FDI_TX_CTL(pipe);
2591         temp = I915_READ(reg);
2592         temp &= ~FDI_LINK_TRAIN_NONE;
2593         temp |= FDI_LINK_TRAIN_PATTERN_2;
2594         if (IS_GEN6(dev)) {
2595                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596                 /* SNB-B */
2597                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598         }
2599         I915_WRITE(reg, temp);
2600
2601         reg = FDI_RX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         if (HAS_PCH_CPT(dev)) {
2604                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606         } else {
2607                 temp &= ~FDI_LINK_TRAIN_NONE;
2608                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2609         }
2610         I915_WRITE(reg, temp);
2611
2612         POSTING_READ(reg);
2613         udelay(150);
2614
2615         for (i = 0; i < 4; i++) {
2616                 reg = FDI_TX_CTL(pipe);
2617                 temp = I915_READ(reg);
2618                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619                 temp |= snb_b_fdi_train_param[i];
2620                 I915_WRITE(reg, temp);
2621
2622                 POSTING_READ(reg);
2623                 udelay(500);
2624
2625                 for (retry = 0; retry < 5; retry++) {
2626                         reg = FDI_RX_IIR(pipe);
2627                         temp = I915_READ(reg);
2628                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629                         if (temp & FDI_RX_SYMBOL_LOCK) {
2630                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2631                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632                                 break;
2633                         }
2634                         udelay(50);
2635                 }
2636                 if (retry < 5)
2637                         break;
2638         }
2639         if (i == 4)
2640                 DRM_ERROR("FDI train 2 fail!\n");
2641
2642         DRM_DEBUG_KMS("FDI train done.\n");
2643 }
2644
2645 /* Manual link training for Ivy Bridge A0 parts */
2646 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2647 {
2648         struct drm_device *dev = crtc->dev;
2649         struct drm_i915_private *dev_priv = dev->dev_private;
2650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651         int pipe = intel_crtc->pipe;
2652         u32 reg, temp, i;
2653
2654         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2655            for train result */
2656         reg = FDI_RX_IMR(pipe);
2657         temp = I915_READ(reg);
2658         temp &= ~FDI_RX_SYMBOL_LOCK;
2659         temp &= ~FDI_RX_BIT_LOCK;
2660         I915_WRITE(reg, temp);
2661
2662         POSTING_READ(reg);
2663         udelay(150);
2664
2665         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2666                       I915_READ(FDI_RX_IIR(pipe)));
2667
2668         /* enable CPU FDI TX and PCH FDI RX */
2669         reg = FDI_TX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~(7 << 19);
2672         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2673         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2674         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2675         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2677         temp |= FDI_COMPOSITE_SYNC;
2678         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2679
2680         I915_WRITE(FDI_RX_MISC(pipe),
2681                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2682
2683         reg = FDI_RX_CTL(pipe);
2684         temp = I915_READ(reg);
2685         temp &= ~FDI_LINK_TRAIN_AUTO;
2686         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2688         temp |= FDI_COMPOSITE_SYNC;
2689         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2690
2691         POSTING_READ(reg);
2692         udelay(150);
2693
2694         if (HAS_PCH_CPT(dev))
2695                 cpt_phase_pointer_enable(dev, pipe);
2696
2697         for (i = 0; i < 4; i++) {
2698                 reg = FDI_TX_CTL(pipe);
2699                 temp = I915_READ(reg);
2700                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701                 temp |= snb_b_fdi_train_param[i];
2702                 I915_WRITE(reg, temp);
2703
2704                 POSTING_READ(reg);
2705                 udelay(500);
2706
2707                 reg = FDI_RX_IIR(pipe);
2708                 temp = I915_READ(reg);
2709                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2710
2711                 if (temp & FDI_RX_BIT_LOCK ||
2712                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2713                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2714                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2715                         break;
2716                 }
2717         }
2718         if (i == 4)
2719                 DRM_ERROR("FDI train 1 fail!\n");
2720
2721         /* Train 2 */
2722         reg = FDI_TX_CTL(pipe);
2723         temp = I915_READ(reg);
2724         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2725         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2726         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2727         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2728         I915_WRITE(reg, temp);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2733         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2734         I915_WRITE(reg, temp);
2735
2736         POSTING_READ(reg);
2737         udelay(150);
2738
2739         for (i = 0; i < 4; i++) {
2740                 reg = FDI_TX_CTL(pipe);
2741                 temp = I915_READ(reg);
2742                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743                 temp |= snb_b_fdi_train_param[i];
2744                 I915_WRITE(reg, temp);
2745
2746                 POSTING_READ(reg);
2747                 udelay(500);
2748
2749                 reg = FDI_RX_IIR(pipe);
2750                 temp = I915_READ(reg);
2751                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753                 if (temp & FDI_RX_SYMBOL_LOCK) {
2754                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2755                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2756                         break;
2757                 }
2758         }
2759         if (i == 4)
2760                 DRM_ERROR("FDI train 2 fail!\n");
2761
2762         DRM_DEBUG_KMS("FDI train done.\n");
2763 }
2764
2765 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2766 {
2767         struct drm_device *dev = intel_crtc->base.dev;
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         int pipe = intel_crtc->pipe;
2770         u32 reg, temp;
2771
2772
2773         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2774         reg = FDI_RX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         temp &= ~((0x7 << 19) | (0x7 << 16));
2777         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2778         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2780
2781         POSTING_READ(reg);
2782         udelay(200);
2783
2784         /* Switch from Rawclk to PCDclk */
2785         temp = I915_READ(reg);
2786         I915_WRITE(reg, temp | FDI_PCDCLK);
2787
2788         POSTING_READ(reg);
2789         udelay(200);
2790
2791         /* On Haswell, the PLL configuration for ports and pipes is handled
2792          * separately, as part of DDI setup */
2793         if (!IS_HASWELL(dev)) {
2794                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2795                 reg = FDI_TX_CTL(pipe);
2796                 temp = I915_READ(reg);
2797                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2798                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2799
2800                         POSTING_READ(reg);
2801                         udelay(100);
2802                 }
2803         }
2804 }
2805
2806 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2807 {
2808         struct drm_device *dev = intel_crtc->base.dev;
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         int pipe = intel_crtc->pipe;
2811         u32 reg, temp;
2812
2813         /* Switch from PCDclk to Rawclk */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2817
2818         /* Disable CPU FDI TX PLL */
2819         reg = FDI_TX_CTL(pipe);
2820         temp = I915_READ(reg);
2821         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2822
2823         POSTING_READ(reg);
2824         udelay(100);
2825
2826         reg = FDI_RX_CTL(pipe);
2827         temp = I915_READ(reg);
2828         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2829
2830         /* Wait for the clocks to turn off. */
2831         POSTING_READ(reg);
2832         udelay(100);
2833 }
2834
2835 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2836 {
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         u32 flags = I915_READ(SOUTH_CHICKEN1);
2839
2840         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2841         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2842         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2843         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2844         POSTING_READ(SOUTH_CHICKEN1);
2845 }
2846 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2847 {
2848         struct drm_device *dev = crtc->dev;
2849         struct drm_i915_private *dev_priv = dev->dev_private;
2850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851         int pipe = intel_crtc->pipe;
2852         u32 reg, temp;
2853
2854         /* disable CPU FDI tx and PCH FDI rx */
2855         reg = FDI_TX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2858         POSTING_READ(reg);
2859
2860         reg = FDI_RX_CTL(pipe);
2861         temp = I915_READ(reg);
2862         temp &= ~(0x7 << 16);
2863         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2864         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2865
2866         POSTING_READ(reg);
2867         udelay(100);
2868
2869         /* Ironlake workaround, disable clock pointer after downing FDI */
2870         if (HAS_PCH_IBX(dev)) {
2871                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2872                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2873                            I915_READ(FDI_RX_CHICKEN(pipe) &
2874                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2875         } else if (HAS_PCH_CPT(dev)) {
2876                 cpt_phase_pointer_disable(dev, pipe);
2877         }
2878
2879         /* still set train pattern 1 */
2880         reg = FDI_TX_CTL(pipe);
2881         temp = I915_READ(reg);
2882         temp &= ~FDI_LINK_TRAIN_NONE;
2883         temp |= FDI_LINK_TRAIN_PATTERN_1;
2884         I915_WRITE(reg, temp);
2885
2886         reg = FDI_RX_CTL(pipe);
2887         temp = I915_READ(reg);
2888         if (HAS_PCH_CPT(dev)) {
2889                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2890                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2891         } else {
2892                 temp &= ~FDI_LINK_TRAIN_NONE;
2893                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2894         }
2895         /* BPC in FDI rx is consistent with that in PIPECONF */
2896         temp &= ~(0x07 << 16);
2897         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2898         I915_WRITE(reg, temp);
2899
2900         POSTING_READ(reg);
2901         udelay(100);
2902 }
2903
2904 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2905 {
2906         struct drm_device *dev = crtc->dev;
2907         struct drm_i915_private *dev_priv = dev->dev_private;
2908         unsigned long flags;
2909         bool pending;
2910
2911         if (atomic_read(&dev_priv->mm.wedged))
2912                 return false;
2913
2914         spin_lock_irqsave(&dev->event_lock, flags);
2915         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916         spin_unlock_irqrestore(&dev->event_lock, flags);
2917
2918         return pending;
2919 }
2920
2921 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2922 {
2923         struct drm_device *dev = crtc->dev;
2924         struct drm_i915_private *dev_priv = dev->dev_private;
2925
2926         if (crtc->fb == NULL)
2927                 return;
2928
2929         wait_event(dev_priv->pending_flip_queue,
2930                    !intel_crtc_has_pending_flip(crtc));
2931
2932         mutex_lock(&dev->struct_mutex);
2933         intel_finish_fb(crtc->fb);
2934         mutex_unlock(&dev->struct_mutex);
2935 }
2936
2937 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2938 {
2939         struct drm_device *dev = crtc->dev;
2940         struct intel_encoder *intel_encoder;
2941
2942         /*
2943          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2944          * must be driven by its own crtc; no sharing is possible.
2945          */
2946         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2947                 switch (intel_encoder->type) {
2948                 case INTEL_OUTPUT_EDP:
2949                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2950                                 return false;
2951                         continue;
2952                 }
2953         }
2954
2955         return true;
2956 }
2957
2958 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2959 {
2960         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2961 }
2962
2963 /* Program iCLKIP clock to the desired frequency */
2964 static void lpt_program_iclkip(struct drm_crtc *crtc)
2965 {
2966         struct drm_device *dev = crtc->dev;
2967         struct drm_i915_private *dev_priv = dev->dev_private;
2968         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2969         u32 temp;
2970
2971         /* It is necessary to ungate the pixclk gate prior to programming
2972          * the divisors, and gate it back when it is done.
2973          */
2974         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2975
2976         /* Disable SSCCTL */
2977         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2978                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2979                                         SBI_SSCCTL_DISABLE);
2980
2981         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2982         if (crtc->mode.clock == 20000) {
2983                 auxdiv = 1;
2984                 divsel = 0x41;
2985                 phaseinc = 0x20;
2986         } else {
2987                 /* The iCLK virtual clock root frequency is in MHz,
2988                  * but the crtc->mode.clock in in KHz. To get the divisors,
2989                  * it is necessary to divide one by another, so we
2990                  * convert the virtual clock precision to KHz here for higher
2991                  * precision.
2992                  */
2993                 u32 iclk_virtual_root_freq = 172800 * 1000;
2994                 u32 iclk_pi_range = 64;
2995                 u32 desired_divisor, msb_divisor_value, pi_value;
2996
2997                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2998                 msb_divisor_value = desired_divisor / iclk_pi_range;
2999                 pi_value = desired_divisor % iclk_pi_range;
3000
3001                 auxdiv = 0;
3002                 divsel = msb_divisor_value - 2;
3003                 phaseinc = pi_value;
3004         }
3005
3006         /* This should not happen with any sane values */
3007         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3008                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3009         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3010                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3011
3012         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3013                         crtc->mode.clock,
3014                         auxdiv,
3015                         divsel,
3016                         phasedir,
3017                         phaseinc);
3018
3019         /* Program SSCDIVINTPHASE6 */
3020         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3021         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3022         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3023         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3024         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3025         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3026         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3027
3028         intel_sbi_write(dev_priv,
3029                         SBI_SSCDIVINTPHASE6,
3030                         temp);
3031
3032         /* Program SSCAUXDIV */
3033         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3034         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3035         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3036         intel_sbi_write(dev_priv,
3037                         SBI_SSCAUXDIV6,
3038                         temp);
3039
3040
3041         /* Enable modulator and associated divider */
3042         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3043         temp &= ~SBI_SSCCTL_DISABLE;
3044         intel_sbi_write(dev_priv,
3045                         SBI_SSCCTL6,
3046                         temp);
3047
3048         /* Wait for initialization time */
3049         udelay(24);
3050
3051         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3052 }
3053
3054 /*
3055  * Enable PCH resources required for PCH ports:
3056  *   - PCH PLLs
3057  *   - FDI training & RX/TX
3058  *   - update transcoder timings
3059  *   - DP transcoding bits
3060  *   - transcoder
3061  */
3062 static void ironlake_pch_enable(struct drm_crtc *crtc)
3063 {
3064         struct drm_device *dev = crtc->dev;
3065         struct drm_i915_private *dev_priv = dev->dev_private;
3066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067         int pipe = intel_crtc->pipe;
3068         u32 reg, temp;
3069
3070         assert_transcoder_disabled(dev_priv, pipe);
3071
3072         /* Write the TU size bits before fdi link training, so that error
3073          * detection works. */
3074         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3075                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3076
3077         /* For PCH output, training FDI link */
3078         dev_priv->display.fdi_link_train(crtc);
3079
3080         /* XXX: pch pll's can be enabled any time before we enable the PCH
3081          * transcoder, and we actually should do this to not upset any PCH
3082          * transcoder that already use the clock when we share it.
3083          *
3084          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3085          * unconditionally resets the pll - we need that to have the right LVDS
3086          * enable sequence. */
3087         intel_enable_pch_pll(intel_crtc);
3088
3089         if (HAS_PCH_LPT(dev)) {
3090                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3091                 lpt_program_iclkip(crtc);
3092         } else if (HAS_PCH_CPT(dev)) {
3093                 u32 sel;
3094
3095                 temp = I915_READ(PCH_DPLL_SEL);
3096                 switch (pipe) {
3097                 default:
3098                 case 0:
3099                         temp |= TRANSA_DPLL_ENABLE;
3100                         sel = TRANSA_DPLLB_SEL;
3101                         break;
3102                 case 1:
3103                         temp |= TRANSB_DPLL_ENABLE;
3104                         sel = TRANSB_DPLLB_SEL;
3105                         break;
3106                 case 2:
3107                         temp |= TRANSC_DPLL_ENABLE;
3108                         sel = TRANSC_DPLLB_SEL;
3109                         break;
3110                 }
3111                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3112                         temp |= sel;
3113                 else
3114                         temp &= ~sel;
3115                 I915_WRITE(PCH_DPLL_SEL, temp);
3116         }
3117
3118         /* set transcoder timing, panel must allow it */
3119         assert_panel_unlocked(dev_priv, pipe);
3120         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3121         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3122         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3123
3124         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3125         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3126         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3127         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3128
3129         if (!IS_HASWELL(dev))
3130                 intel_fdi_normal_train(crtc);
3131
3132         /* For PCH DP, enable TRANS_DP_CTL */
3133         if (HAS_PCH_CPT(dev) &&
3134             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3135              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3136                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3137                 reg = TRANS_DP_CTL(pipe);
3138                 temp = I915_READ(reg);
3139                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3140                           TRANS_DP_SYNC_MASK |
3141                           TRANS_DP_BPC_MASK);
3142                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3143                          TRANS_DP_ENH_FRAMING);
3144                 temp |= bpc << 9; /* same format but at 11:9 */
3145
3146                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3147                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3148                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3149                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3150
3151                 switch (intel_trans_dp_port_sel(crtc)) {
3152                 case PCH_DP_B:
3153                         temp |= TRANS_DP_PORT_SEL_B;
3154                         break;
3155                 case PCH_DP_C:
3156                         temp |= TRANS_DP_PORT_SEL_C;
3157                         break;
3158                 case PCH_DP_D:
3159                         temp |= TRANS_DP_PORT_SEL_D;
3160                         break;
3161                 default:
3162                         BUG();
3163                 }
3164
3165                 I915_WRITE(reg, temp);
3166         }
3167
3168         intel_enable_transcoder(dev_priv, pipe);
3169 }
3170
3171 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3172 {
3173         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3174
3175         if (pll == NULL)
3176                 return;
3177
3178         if (pll->refcount == 0) {
3179                 WARN(1, "bad PCH PLL refcount\n");
3180                 return;
3181         }
3182
3183         --pll->refcount;
3184         intel_crtc->pch_pll = NULL;
3185 }
3186
3187 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3188 {
3189         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3190         struct intel_pch_pll *pll;
3191         int i;
3192
3193         pll = intel_crtc->pch_pll;
3194         if (pll) {
3195                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3196                               intel_crtc->base.base.id, pll->pll_reg);
3197                 goto prepare;
3198         }
3199
3200         if (HAS_PCH_IBX(dev_priv->dev)) {
3201                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3202                 i = intel_crtc->pipe;
3203                 pll = &dev_priv->pch_plls[i];
3204
3205                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3206                               intel_crtc->base.base.id, pll->pll_reg);
3207
3208                 goto found;
3209         }
3210
3211         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3212                 pll = &dev_priv->pch_plls[i];
3213
3214                 /* Only want to check enabled timings first */
3215                 if (pll->refcount == 0)
3216                         continue;
3217
3218                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3219                     fp == I915_READ(pll->fp0_reg)) {
3220                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3221                                       intel_crtc->base.base.id,
3222                                       pll->pll_reg, pll->refcount, pll->active);
3223
3224                         goto found;
3225                 }
3226         }
3227
3228         /* Ok no matching timings, maybe there's a free one? */
3229         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3230                 pll = &dev_priv->pch_plls[i];
3231                 if (pll->refcount == 0) {
3232                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3233                                       intel_crtc->base.base.id, pll->pll_reg);
3234                         goto found;
3235                 }
3236         }
3237
3238         return NULL;
3239
3240 found:
3241         intel_crtc->pch_pll = pll;
3242         pll->refcount++;
3243         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3244 prepare: /* separate function? */
3245         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3246
3247         /* Wait for the clocks to stabilize before rewriting the regs */
3248         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3249         POSTING_READ(pll->pll_reg);
3250         udelay(150);
3251
3252         I915_WRITE(pll->fp0_reg, fp);
3253         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3254         pll->on = false;
3255         return pll;
3256 }
3257
3258 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3259 {
3260         struct drm_i915_private *dev_priv = dev->dev_private;
3261         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3262         u32 temp;
3263
3264         temp = I915_READ(dslreg);
3265         udelay(500);
3266         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3267                 /* Without this, mode sets may fail silently on FDI */
3268                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3269                 udelay(250);
3270                 I915_WRITE(tc2reg, 0);
3271                 if (wait_for(I915_READ(dslreg) != temp, 5))
3272                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3273         }
3274 }
3275
3276 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3277 {
3278         struct drm_device *dev = crtc->dev;
3279         struct drm_i915_private *dev_priv = dev->dev_private;
3280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3281         struct intel_encoder *encoder;
3282         int pipe = intel_crtc->pipe;
3283         int plane = intel_crtc->plane;
3284         u32 temp;
3285         bool is_pch_port;
3286
3287         WARN_ON(!crtc->enabled);
3288
3289         if (intel_crtc->active)
3290                 return;
3291
3292         intel_crtc->active = true;
3293         intel_update_watermarks(dev);
3294
3295         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3296                 temp = I915_READ(PCH_LVDS);
3297                 if ((temp & LVDS_PORT_EN) == 0)
3298                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3299         }
3300
3301         is_pch_port = ironlake_crtc_driving_pch(crtc);
3302
3303         if (is_pch_port) {
3304                 /* Note: FDI PLL enabling _must_ be done before we enable the
3305                  * cpu pipes, hence this is separate from all the other fdi/pch
3306                  * enabling. */
3307                 ironlake_fdi_pll_enable(intel_crtc);
3308         } else {
3309                 assert_fdi_tx_disabled(dev_priv, pipe);
3310                 assert_fdi_rx_disabled(dev_priv, pipe);
3311         }
3312
3313         for_each_encoder_on_crtc(dev, crtc, encoder)
3314                 if (encoder->pre_enable)
3315                         encoder->pre_enable(encoder);
3316
3317         /* Enable panel fitting for LVDS */
3318         if (dev_priv->pch_pf_size &&
3319             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3320                 /* Force use of hard-coded filter coefficients
3321                  * as some pre-programmed values are broken,
3322                  * e.g. x201.
3323                  */
3324                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3325                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3326                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3327         }
3328
3329         /*
3330          * On ILK+ LUT must be loaded before the pipe is running but with
3331          * clocks enabled
3332          */
3333         intel_crtc_load_lut(crtc);
3334
3335         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3336         intel_enable_plane(dev_priv, plane, pipe);
3337
3338         if (is_pch_port)
3339                 ironlake_pch_enable(crtc);
3340
3341         mutex_lock(&dev->struct_mutex);
3342         intel_update_fbc(dev);
3343         mutex_unlock(&dev->struct_mutex);
3344
3345         intel_crtc_update_cursor(crtc, true);
3346
3347         for_each_encoder_on_crtc(dev, crtc, encoder)
3348                 encoder->enable(encoder);
3349
3350         if (HAS_PCH_CPT(dev))
3351                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3352
3353         /*
3354          * There seems to be a race in PCH platform hw (at least on some
3355          * outputs) where an enabled pipe still completes any pageflip right
3356          * away (as if the pipe is off) instead of waiting for vblank. As soon
3357          * as the first vblank happend, everything works as expected. Hence just
3358          * wait for one vblank before returning to avoid strange things
3359          * happening.
3360          */
3361         intel_wait_for_vblank(dev, intel_crtc->pipe);
3362 }
3363
3364 static void haswell_crtc_enable(struct drm_crtc *crtc)
3365 {
3366         struct drm_device *dev = crtc->dev;
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369         struct intel_encoder *encoder;
3370         int pipe = intel_crtc->pipe;
3371         int plane = intel_crtc->plane;
3372         bool is_pch_port;
3373
3374         WARN_ON(!crtc->enabled);
3375
3376         if (intel_crtc->active)
3377                 return;
3378
3379         intel_crtc->active = true;
3380         intel_update_watermarks(dev);
3381
3382         is_pch_port = haswell_crtc_driving_pch(crtc);
3383
3384         if (is_pch_port)
3385                 ironlake_fdi_pll_enable(intel_crtc);
3386
3387         for_each_encoder_on_crtc(dev, crtc, encoder)
3388                 if (encoder->pre_enable)
3389                         encoder->pre_enable(encoder);
3390
3391         intel_ddi_enable_pipe_clock(intel_crtc);
3392
3393         /* Enable panel fitting for eDP */
3394         if (dev_priv->pch_pf_size && HAS_eDP) {
3395                 /* Force use of hard-coded filter coefficients
3396                  * as some pre-programmed values are broken,
3397                  * e.g. x201.
3398                  */
3399                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3400                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3401                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3402         }
3403
3404         /*
3405          * On ILK+ LUT must be loaded before the pipe is running but with
3406          * clocks enabled
3407          */
3408         intel_crtc_load_lut(crtc);
3409
3410         intel_ddi_set_pipe_settings(crtc);
3411         intel_ddi_enable_pipe_func(crtc);
3412
3413         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3414         intel_enable_plane(dev_priv, plane, pipe);
3415
3416         if (is_pch_port)
3417                 ironlake_pch_enable(crtc);
3418
3419         mutex_lock(&dev->struct_mutex);
3420         intel_update_fbc(dev);
3421         mutex_unlock(&dev->struct_mutex);
3422
3423         intel_crtc_update_cursor(crtc, true);
3424
3425         for_each_encoder_on_crtc(dev, crtc, encoder)
3426                 encoder->enable(encoder);
3427
3428         /*
3429          * There seems to be a race in PCH platform hw (at least on some
3430          * outputs) where an enabled pipe still completes any pageflip right
3431          * away (as if the pipe is off) instead of waiting for vblank. As soon
3432          * as the first vblank happend, everything works as expected. Hence just
3433          * wait for one vblank before returning to avoid strange things
3434          * happening.
3435          */
3436         intel_wait_for_vblank(dev, intel_crtc->pipe);
3437 }
3438
3439 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3440 {
3441         struct drm_device *dev = crtc->dev;
3442         struct drm_i915_private *dev_priv = dev->dev_private;
3443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3444         struct intel_encoder *encoder;
3445         int pipe = intel_crtc->pipe;
3446         int plane = intel_crtc->plane;
3447         u32 reg, temp;
3448
3449
3450         if (!intel_crtc->active)
3451                 return;
3452
3453         for_each_encoder_on_crtc(dev, crtc, encoder)
3454                 encoder->disable(encoder);
3455
3456         intel_crtc_wait_for_pending_flips(crtc);
3457         drm_vblank_off(dev, pipe);
3458         intel_crtc_update_cursor(crtc, false);
3459
3460         intel_disable_plane(dev_priv, plane, pipe);
3461
3462         if (dev_priv->cfb_plane == plane)
3463                 intel_disable_fbc(dev);
3464
3465         intel_disable_pipe(dev_priv, pipe);
3466
3467         /* Disable PF */
3468         I915_WRITE(PF_CTL(pipe), 0);
3469         I915_WRITE(PF_WIN_SZ(pipe), 0);
3470
3471         for_each_encoder_on_crtc(dev, crtc, encoder)
3472                 if (encoder->post_disable)
3473                         encoder->post_disable(encoder);
3474
3475         ironlake_fdi_disable(crtc);
3476
3477         intel_disable_transcoder(dev_priv, pipe);
3478
3479         if (HAS_PCH_CPT(dev)) {
3480                 /* disable TRANS_DP_CTL */
3481                 reg = TRANS_DP_CTL(pipe);
3482                 temp = I915_READ(reg);
3483                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3484                 temp |= TRANS_DP_PORT_SEL_NONE;
3485                 I915_WRITE(reg, temp);
3486
3487                 /* disable DPLL_SEL */
3488                 temp = I915_READ(PCH_DPLL_SEL);
3489                 switch (pipe) {
3490                 case 0:
3491                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3492                         break;
3493                 case 1:
3494                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3495                         break;
3496                 case 2:
3497                         /* C shares PLL A or B */
3498                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3499                         break;
3500                 default:
3501                         BUG(); /* wtf */
3502                 }
3503                 I915_WRITE(PCH_DPLL_SEL, temp);
3504         }
3505
3506         /* disable PCH DPLL */
3507         intel_disable_pch_pll(intel_crtc);
3508
3509         ironlake_fdi_pll_disable(intel_crtc);
3510
3511         intel_crtc->active = false;
3512         intel_update_watermarks(dev);
3513
3514         mutex_lock(&dev->struct_mutex);
3515         intel_update_fbc(dev);
3516         mutex_unlock(&dev->struct_mutex);
3517 }
3518
3519 static void haswell_crtc_disable(struct drm_crtc *crtc)
3520 {
3521         struct drm_device *dev = crtc->dev;
3522         struct drm_i915_private *dev_priv = dev->dev_private;
3523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3524         struct intel_encoder *encoder;
3525         int pipe = intel_crtc->pipe;
3526         int plane = intel_crtc->plane;
3527         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3528         bool is_pch_port;
3529
3530         if (!intel_crtc->active)
3531                 return;
3532
3533         is_pch_port = haswell_crtc_driving_pch(crtc);
3534
3535         for_each_encoder_on_crtc(dev, crtc, encoder)
3536                 encoder->disable(encoder);
3537
3538         intel_crtc_wait_for_pending_flips(crtc);
3539         drm_vblank_off(dev, pipe);
3540         intel_crtc_update_cursor(crtc, false);
3541
3542         intel_disable_plane(dev_priv, plane, pipe);
3543
3544         if (dev_priv->cfb_plane == plane)
3545                 intel_disable_fbc(dev);
3546
3547         intel_disable_pipe(dev_priv, pipe);
3548
3549         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3550
3551         /* Disable PF */
3552         I915_WRITE(PF_CTL(pipe), 0);
3553         I915_WRITE(PF_WIN_SZ(pipe), 0);
3554
3555         intel_ddi_disable_pipe_clock(intel_crtc);
3556
3557         for_each_encoder_on_crtc(dev, crtc, encoder)
3558                 if (encoder->post_disable)
3559                         encoder->post_disable(encoder);
3560
3561         if (is_pch_port) {
3562                 ironlake_fdi_disable(crtc);
3563                 intel_disable_transcoder(dev_priv, pipe);
3564                 intel_disable_pch_pll(intel_crtc);
3565                 ironlake_fdi_pll_disable(intel_crtc);
3566         }
3567
3568         intel_crtc->active = false;
3569         intel_update_watermarks(dev);
3570
3571         mutex_lock(&dev->struct_mutex);
3572         intel_update_fbc(dev);
3573         mutex_unlock(&dev->struct_mutex);
3574 }
3575
3576 static void ironlake_crtc_off(struct drm_crtc *crtc)
3577 {
3578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3579         intel_put_pch_pll(intel_crtc);
3580 }
3581
3582 static void haswell_crtc_off(struct drm_crtc *crtc)
3583 {
3584         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3585
3586         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3587          * start using it. */
3588         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3589
3590         intel_ddi_put_crtc_pll(crtc);
3591 }
3592
3593 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3594 {
3595         if (!enable && intel_crtc->overlay) {
3596                 struct drm_device *dev = intel_crtc->base.dev;
3597                 struct drm_i915_private *dev_priv = dev->dev_private;
3598
3599                 mutex_lock(&dev->struct_mutex);
3600                 dev_priv->mm.interruptible = false;
3601                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3602                 dev_priv->mm.interruptible = true;
3603                 mutex_unlock(&dev->struct_mutex);
3604         }
3605
3606         /* Let userspace switch the overlay on again. In most cases userspace
3607          * has to recompute where to put it anyway.
3608          */
3609 }
3610
3611 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3612 {
3613         struct drm_device *dev = crtc->dev;
3614         struct drm_i915_private *dev_priv = dev->dev_private;
3615         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3616         struct intel_encoder *encoder;
3617         int pipe = intel_crtc->pipe;
3618         int plane = intel_crtc->plane;
3619
3620         WARN_ON(!crtc->enabled);
3621
3622         if (intel_crtc->active)
3623                 return;
3624
3625         intel_crtc->active = true;
3626         intel_update_watermarks(dev);
3627
3628         intel_enable_pll(dev_priv, pipe);
3629         intel_enable_pipe(dev_priv, pipe, false);
3630         intel_enable_plane(dev_priv, plane, pipe);
3631
3632         intel_crtc_load_lut(crtc);
3633         intel_update_fbc(dev);
3634
3635         /* Give the overlay scaler a chance to enable if it's on this pipe */
3636         intel_crtc_dpms_overlay(intel_crtc, true);
3637         intel_crtc_update_cursor(crtc, true);
3638
3639         for_each_encoder_on_crtc(dev, crtc, encoder)
3640                 encoder->enable(encoder);
3641 }
3642
3643 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3644 {
3645         struct drm_device *dev = crtc->dev;
3646         struct drm_i915_private *dev_priv = dev->dev_private;
3647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648         struct intel_encoder *encoder;
3649         int pipe = intel_crtc->pipe;
3650         int plane = intel_crtc->plane;
3651
3652
3653         if (!intel_crtc->active)
3654                 return;
3655
3656         for_each_encoder_on_crtc(dev, crtc, encoder)
3657                 encoder->disable(encoder);
3658
3659         /* Give the overlay scaler a chance to disable if it's on this pipe */
3660         intel_crtc_wait_for_pending_flips(crtc);
3661         drm_vblank_off(dev, pipe);
3662         intel_crtc_dpms_overlay(intel_crtc, false);
3663         intel_crtc_update_cursor(crtc, false);
3664
3665         if (dev_priv->cfb_plane == plane)
3666                 intel_disable_fbc(dev);
3667
3668         intel_disable_plane(dev_priv, plane, pipe);
3669         intel_disable_pipe(dev_priv, pipe);
3670         intel_disable_pll(dev_priv, pipe);
3671
3672         intel_crtc->active = false;
3673         intel_update_fbc(dev);
3674         intel_update_watermarks(dev);
3675 }
3676
3677 static void i9xx_crtc_off(struct drm_crtc *crtc)
3678 {
3679 }
3680
3681 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3682                                     bool enabled)
3683 {
3684         struct drm_device *dev = crtc->dev;
3685         struct drm_i915_master_private *master_priv;
3686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3687         int pipe = intel_crtc->pipe;
3688
3689         if (!dev->primary->master)
3690                 return;
3691
3692         master_priv = dev->primary->master->driver_priv;
3693         if (!master_priv->sarea_priv)
3694                 return;
3695
3696         switch (pipe) {
3697         case 0:
3698                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3699                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3700                 break;
3701         case 1:
3702                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3703                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3704                 break;
3705         default:
3706                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3707                 break;
3708         }
3709 }
3710
3711 /**
3712  * Sets the power management mode of the pipe and plane.
3713  */
3714 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3715 {
3716         struct drm_device *dev = crtc->dev;
3717         struct drm_i915_private *dev_priv = dev->dev_private;
3718         struct intel_encoder *intel_encoder;
3719         bool enable = false;
3720
3721         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3722                 enable |= intel_encoder->connectors_active;
3723
3724         if (enable)
3725                 dev_priv->display.crtc_enable(crtc);
3726         else
3727                 dev_priv->display.crtc_disable(crtc);
3728
3729         intel_crtc_update_sarea(crtc, enable);
3730 }
3731
3732 static void intel_crtc_noop(struct drm_crtc *crtc)
3733 {
3734 }
3735
3736 static void intel_crtc_disable(struct drm_crtc *crtc)
3737 {
3738         struct drm_device *dev = crtc->dev;
3739         struct drm_connector *connector;
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741
3742         /* crtc should still be enabled when we disable it. */
3743         WARN_ON(!crtc->enabled);
3744
3745         dev_priv->display.crtc_disable(crtc);
3746         intel_crtc_update_sarea(crtc, false);
3747         dev_priv->display.off(crtc);
3748
3749         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3750         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3751
3752         if (crtc->fb) {
3753                 mutex_lock(&dev->struct_mutex);
3754                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3755                 mutex_unlock(&dev->struct_mutex);
3756                 crtc->fb = NULL;
3757         }
3758
3759         /* Update computed state. */
3760         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3761                 if (!connector->encoder || !connector->encoder->crtc)
3762                         continue;
3763
3764                 if (connector->encoder->crtc != crtc)
3765                         continue;
3766
3767                 connector->dpms = DRM_MODE_DPMS_OFF;
3768                 to_intel_encoder(connector->encoder)->connectors_active = false;
3769         }
3770 }
3771
3772 void intel_modeset_disable(struct drm_device *dev)
3773 {
3774         struct drm_crtc *crtc;
3775
3776         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3777                 if (crtc->enabled)
3778                         intel_crtc_disable(crtc);
3779         }
3780 }
3781
3782 void intel_encoder_noop(struct drm_encoder *encoder)
3783 {
3784 }
3785
3786 void intel_encoder_destroy(struct drm_encoder *encoder)
3787 {
3788         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3789
3790         drm_encoder_cleanup(encoder);
3791         kfree(intel_encoder);
3792 }
3793
3794 /* Simple dpms helper for encodres with just one connector, no cloning and only
3795  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3796  * state of the entire output pipe. */
3797 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3798 {
3799         if (mode == DRM_MODE_DPMS_ON) {
3800                 encoder->connectors_active = true;
3801
3802                 intel_crtc_update_dpms(encoder->base.crtc);
3803         } else {
3804                 encoder->connectors_active = false;
3805
3806                 intel_crtc_update_dpms(encoder->base.crtc);
3807         }
3808 }
3809
3810 /* Cross check the actual hw state with our own modeset state tracking (and it's
3811  * internal consistency). */
3812 static void intel_connector_check_state(struct intel_connector *connector)
3813 {
3814         if (connector->get_hw_state(connector)) {
3815                 struct intel_encoder *encoder = connector->encoder;
3816                 struct drm_crtc *crtc;
3817                 bool encoder_enabled;
3818                 enum pipe pipe;
3819
3820                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3821                               connector->base.base.id,
3822                               drm_get_connector_name(&connector->base));
3823
3824                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3825                      "wrong connector dpms state\n");
3826                 WARN(connector->base.encoder != &encoder->base,
3827                      "active connector not linked to encoder\n");
3828                 WARN(!encoder->connectors_active,
3829                      "encoder->connectors_active not set\n");
3830
3831                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3832                 WARN(!encoder_enabled, "encoder not enabled\n");
3833                 if (WARN_ON(!encoder->base.crtc))
3834                         return;
3835
3836                 crtc = encoder->base.crtc;
3837
3838                 WARN(!crtc->enabled, "crtc not enabled\n");
3839                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3840                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3841                      "encoder active on the wrong pipe\n");
3842         }
3843 }
3844
3845 /* Even simpler default implementation, if there's really no special case to
3846  * consider. */
3847 void intel_connector_dpms(struct drm_connector *connector, int mode)
3848 {
3849         struct intel_encoder *encoder = intel_attached_encoder(connector);
3850
3851         /* All the simple cases only support two dpms states. */
3852         if (mode != DRM_MODE_DPMS_ON)
3853                 mode = DRM_MODE_DPMS_OFF;
3854
3855         if (mode == connector->dpms)
3856                 return;
3857
3858         connector->dpms = mode;
3859
3860         /* Only need to change hw state when actually enabled */
3861         if (encoder->base.crtc)
3862                 intel_encoder_dpms(encoder, mode);
3863         else
3864                 WARN_ON(encoder->connectors_active != false);
3865
3866         intel_modeset_check_state(connector->dev);
3867 }
3868
3869 /* Simple connector->get_hw_state implementation for encoders that support only
3870  * one connector and no cloning and hence the encoder state determines the state
3871  * of the connector. */
3872 bool intel_connector_get_hw_state(struct intel_connector *connector)
3873 {
3874         enum pipe pipe = 0;
3875         struct intel_encoder *encoder = connector->encoder;
3876
3877         return encoder->get_hw_state(encoder, &pipe);
3878 }
3879
3880 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3881                                   const struct drm_display_mode *mode,
3882                                   struct drm_display_mode *adjusted_mode)
3883 {
3884         struct drm_device *dev = crtc->dev;
3885
3886         if (HAS_PCH_SPLIT(dev)) {
3887                 /* FDI link clock is fixed at 2.7G */
3888                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3889                         return false;
3890         }
3891
3892         /* All interlaced capable intel hw wants timings in frames. Note though
3893          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3894          * timings, so we need to be careful not to clobber these.*/
3895         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3896                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3897
3898         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3899          * with a hsync front porch of 0.
3900          */
3901         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3902                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3903                 return false;
3904
3905         return true;
3906 }
3907
3908 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3909 {
3910         return 400000; /* FIXME */
3911 }
3912
3913 static int i945_get_display_clock_speed(struct drm_device *dev)
3914 {
3915         return 400000;
3916 }
3917
3918 static int i915_get_display_clock_speed(struct drm_device *dev)
3919 {
3920         return 333000;
3921 }
3922
3923 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3924 {
3925         return 200000;
3926 }
3927
3928 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3929 {
3930         u16 gcfgc = 0;
3931
3932         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3933
3934         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3935                 return 133000;
3936         else {
3937                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3938                 case GC_DISPLAY_CLOCK_333_MHZ:
3939                         return 333000;
3940                 default:
3941                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3942                         return 190000;
3943                 }
3944         }
3945 }
3946
3947 static int i865_get_display_clock_speed(struct drm_device *dev)
3948 {
3949         return 266000;
3950 }
3951
3952 static int i855_get_display_clock_speed(struct drm_device *dev)
3953 {
3954         u16 hpllcc = 0;
3955         /* Assume that the hardware is in the high speed state.  This
3956          * should be the default.
3957          */
3958         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3959         case GC_CLOCK_133_200:
3960         case GC_CLOCK_100_200:
3961                 return 200000;
3962         case GC_CLOCK_166_250:
3963                 return 250000;
3964         case GC_CLOCK_100_133:
3965                 return 133000;
3966         }
3967
3968         /* Shouldn't happen */
3969         return 0;
3970 }
3971
3972 static int i830_get_display_clock_speed(struct drm_device *dev)
3973 {
3974         return 133000;
3975 }
3976
3977 struct fdi_m_n {
3978         u32        tu;
3979         u32        gmch_m;
3980         u32        gmch_n;
3981         u32        link_m;
3982         u32        link_n;
3983 };
3984
3985 static void
3986 fdi_reduce_ratio(u32 *num, u32 *den)
3987 {
3988         while (*num > 0xffffff || *den > 0xffffff) {
3989                 *num >>= 1;
3990                 *den >>= 1;
3991         }
3992 }
3993
3994 static void
3995 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3996                      int link_clock, struct fdi_m_n *m_n)
3997 {
3998         m_n->tu = 64; /* default size */
3999
4000         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4001         m_n->gmch_m = bits_per_pixel * pixel_clock;
4002         m_n->gmch_n = link_clock * nlanes * 8;
4003         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4004
4005         m_n->link_m = pixel_clock;
4006         m_n->link_n = link_clock;
4007         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4008 }
4009
4010 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4011 {
4012         if (i915_panel_use_ssc >= 0)
4013                 return i915_panel_use_ssc != 0;
4014         return dev_priv->lvds_use_ssc
4015                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4016 }
4017
4018 /**
4019  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4020  * @crtc: CRTC structure
4021  * @mode: requested mode
4022  *
4023  * A pipe may be connected to one or more outputs.  Based on the depth of the
4024  * attached framebuffer, choose a good color depth to use on the pipe.
4025  *
4026  * If possible, match the pipe depth to the fb depth.  In some cases, this
4027  * isn't ideal, because the connected output supports a lesser or restricted
4028  * set of depths.  Resolve that here:
4029  *    LVDS typically supports only 6bpc, so clamp down in that case
4030  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4031  *    Displays may support a restricted set as well, check EDID and clamp as
4032  *      appropriate.
4033  *    DP may want to dither down to 6bpc to fit larger modes
4034  *
4035  * RETURNS:
4036  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4037  * true if they don't match).
4038  */
4039 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4040                                          struct drm_framebuffer *fb,
4041                                          unsigned int *pipe_bpp,
4042                                          struct drm_display_mode *mode)
4043 {
4044         struct drm_device *dev = crtc->dev;
4045         struct drm_i915_private *dev_priv = dev->dev_private;
4046         struct drm_connector *connector;
4047         struct intel_encoder *intel_encoder;
4048         unsigned int display_bpc = UINT_MAX, bpc;
4049
4050         /* Walk the encoders & connectors on this crtc, get min bpc */
4051         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4052
4053                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4054                         unsigned int lvds_bpc;
4055
4056                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4057                             LVDS_A3_POWER_UP)
4058                                 lvds_bpc = 8;
4059                         else
4060                                 lvds_bpc = 6;
4061
4062                         if (lvds_bpc < display_bpc) {
4063                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4064                                 display_bpc = lvds_bpc;
4065                         }
4066                         continue;
4067                 }
4068
4069                 /* Not one of the known troublemakers, check the EDID */
4070                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4071                                     head) {
4072                         if (connector->encoder != &intel_encoder->base)
4073                                 continue;
4074
4075                         /* Don't use an invalid EDID bpc value */
4076                         if (connector->display_info.bpc &&
4077                             connector->display_info.bpc < display_bpc) {
4078                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4079                                 display_bpc = connector->display_info.bpc;
4080                         }
4081                 }
4082
4083                 /*
4084                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4085                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4086                  */
4087                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4088                         if (display_bpc > 8 && display_bpc < 12) {
4089                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4090                                 display_bpc = 12;
4091                         } else {
4092                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4093                                 display_bpc = 8;
4094                         }
4095                 }
4096         }
4097
4098         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4099                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4100                 display_bpc = 6;
4101         }
4102
4103         /*
4104          * We could just drive the pipe at the highest bpc all the time and
4105          * enable dithering as needed, but that costs bandwidth.  So choose
4106          * the minimum value that expresses the full color range of the fb but
4107          * also stays within the max display bpc discovered above.
4108          */
4109
4110         switch (fb->depth) {
4111         case 8:
4112                 bpc = 8; /* since we go through a colormap */
4113                 break;
4114         case 15:
4115         case 16:
4116                 bpc = 6; /* min is 18bpp */
4117                 break;
4118         case 24:
4119                 bpc = 8;
4120                 break;
4121         case 30:
4122                 bpc = 10;
4123                 break;
4124         case 48:
4125                 bpc = 12;
4126                 break;
4127         default:
4128                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4129                 bpc = min((unsigned int)8, display_bpc);
4130                 break;
4131         }
4132
4133         display_bpc = min(display_bpc, bpc);
4134
4135         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4136                       bpc, display_bpc);
4137
4138         *pipe_bpp = display_bpc * 3;
4139
4140         return display_bpc != bpc;
4141 }
4142
4143 static int vlv_get_refclk(struct drm_crtc *crtc)
4144 {
4145         struct drm_device *dev = crtc->dev;
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         int refclk = 27000; /* for DP & HDMI */
4148
4149         return 100000; /* only one validated so far */
4150
4151         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4152                 refclk = 96000;
4153         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4154                 if (intel_panel_use_ssc(dev_priv))
4155                         refclk = 100000;
4156                 else
4157                         refclk = 96000;
4158         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4159                 refclk = 100000;
4160         }
4161
4162         return refclk;
4163 }
4164
4165 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4166 {
4167         struct drm_device *dev = crtc->dev;
4168         struct drm_i915_private *dev_priv = dev->dev_private;
4169         int refclk;
4170
4171         if (IS_VALLEYVIEW(dev)) {
4172                 refclk = vlv_get_refclk(crtc);
4173         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4174             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4175                 refclk = dev_priv->lvds_ssc_freq * 1000;
4176                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4177                               refclk / 1000);
4178         } else if (!IS_GEN2(dev)) {
4179                 refclk = 96000;
4180         } else {
4181                 refclk = 48000;
4182         }
4183
4184         return refclk;
4185 }
4186
4187 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4188                                       intel_clock_t *clock)
4189 {
4190         /* SDVO TV has fixed PLL values depend on its clock range,
4191            this mirrors vbios setting. */
4192         if (adjusted_mode->clock >= 100000
4193             && adjusted_mode->clock < 140500) {
4194                 clock->p1 = 2;
4195                 clock->p2 = 10;
4196                 clock->n = 3;
4197                 clock->m1 = 16;
4198                 clock->m2 = 8;
4199         } else if (adjusted_mode->clock >= 140500
4200                    && adjusted_mode->clock <= 200000) {
4201                 clock->p1 = 1;
4202                 clock->p2 = 10;
4203                 clock->n = 6;
4204                 clock->m1 = 12;
4205                 clock->m2 = 8;
4206         }
4207 }
4208
4209 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4210                                      intel_clock_t *clock,
4211                                      intel_clock_t *reduced_clock)
4212 {
4213         struct drm_device *dev = crtc->dev;
4214         struct drm_i915_private *dev_priv = dev->dev_private;
4215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4216         int pipe = intel_crtc->pipe;
4217         u32 fp, fp2 = 0;
4218
4219         if (IS_PINEVIEW(dev)) {
4220                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4221                 if (reduced_clock)
4222                         fp2 = (1 << reduced_clock->n) << 16 |
4223                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4224         } else {
4225                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4226                 if (reduced_clock)
4227                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4228                                 reduced_clock->m2;
4229         }
4230
4231         I915_WRITE(FP0(pipe), fp);
4232
4233         intel_crtc->lowfreq_avail = false;
4234         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4235             reduced_clock && i915_powersave) {
4236                 I915_WRITE(FP1(pipe), fp2);
4237                 intel_crtc->lowfreq_avail = true;
4238         } else {
4239                 I915_WRITE(FP1(pipe), fp);
4240         }
4241 }
4242
4243 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4244                               struct drm_display_mode *adjusted_mode)
4245 {
4246         struct drm_device *dev = crtc->dev;
4247         struct drm_i915_private *dev_priv = dev->dev_private;
4248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249         int pipe = intel_crtc->pipe;
4250         u32 temp;
4251
4252         temp = I915_READ(LVDS);
4253         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4254         if (pipe == 1) {
4255                 temp |= LVDS_PIPEB_SELECT;
4256         } else {
4257                 temp &= ~LVDS_PIPEB_SELECT;
4258         }
4259         /* set the corresponsding LVDS_BORDER bit */
4260         temp |= dev_priv->lvds_border_bits;
4261         /* Set the B0-B3 data pairs corresponding to whether we're going to
4262          * set the DPLLs for dual-channel mode or not.
4263          */
4264         if (clock->p2 == 7)
4265                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4266         else
4267                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4268
4269         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4270          * appropriately here, but we need to look more thoroughly into how
4271          * panels behave in the two modes.
4272          */
4273         /* set the dithering flag on LVDS as needed */
4274         if (INTEL_INFO(dev)->gen >= 4) {
4275                 if (dev_priv->lvds_dither)
4276                         temp |= LVDS_ENABLE_DITHER;
4277                 else
4278                         temp &= ~LVDS_ENABLE_DITHER;
4279         }
4280         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4281         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4282                 temp |= LVDS_HSYNC_POLARITY;
4283         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4284                 temp |= LVDS_VSYNC_POLARITY;
4285         I915_WRITE(LVDS, temp);
4286 }
4287
4288 static void vlv_update_pll(struct drm_crtc *crtc,
4289                            struct drm_display_mode *mode,
4290                            struct drm_display_mode *adjusted_mode,
4291                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4292                            int num_connectors)
4293 {
4294         struct drm_device *dev = crtc->dev;
4295         struct drm_i915_private *dev_priv = dev->dev_private;
4296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4297         int pipe = intel_crtc->pipe;
4298         u32 dpll, mdiv, pdiv;
4299         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4300         bool is_sdvo;
4301         u32 temp;
4302
4303         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4304                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4305
4306         dpll = DPLL_VGA_MODE_DIS;
4307         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4308         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4309         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4310
4311         I915_WRITE(DPLL(pipe), dpll);
4312         POSTING_READ(DPLL(pipe));
4313
4314         bestn = clock->n;
4315         bestm1 = clock->m1;
4316         bestm2 = clock->m2;
4317         bestp1 = clock->p1;
4318         bestp2 = clock->p2;
4319
4320         /*
4321          * In Valleyview PLL and program lane counter registers are exposed
4322          * through DPIO interface
4323          */
4324         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4325         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4326         mdiv |= ((bestn << DPIO_N_SHIFT));
4327         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4328         mdiv |= (1 << DPIO_K_SHIFT);
4329         mdiv |= DPIO_ENABLE_CALIBRATION;
4330         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4331
4332         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4333
4334         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4335                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4336                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4337                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4338         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4339
4340         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4341
4342         dpll |= DPLL_VCO_ENABLE;
4343         I915_WRITE(DPLL(pipe), dpll);
4344         POSTING_READ(DPLL(pipe));
4345         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4346                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4347
4348         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4349
4350         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4351                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4352
4353         I915_WRITE(DPLL(pipe), dpll);
4354
4355         /* Wait for the clocks to stabilize. */
4356         POSTING_READ(DPLL(pipe));
4357         udelay(150);
4358
4359         temp = 0;
4360         if (is_sdvo) {
4361                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4362                 if (temp > 1)
4363                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4364                 else
4365                         temp = 0;
4366         }
4367         I915_WRITE(DPLL_MD(pipe), temp);
4368         POSTING_READ(DPLL_MD(pipe));
4369
4370         /* Now program lane control registers */
4371         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4372                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4373         {
4374                 temp = 0x1000C4;
4375                 if(pipe == 1)
4376                         temp |= (1 << 21);
4377                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4378         }
4379         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4380         {
4381                 temp = 0x1000C4;
4382                 if(pipe == 1)
4383                         temp |= (1 << 21);
4384                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4385         }
4386 }
4387
4388 static void i9xx_update_pll(struct drm_crtc *crtc,
4389                             struct drm_display_mode *mode,
4390                             struct drm_display_mode *adjusted_mode,
4391                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4392                             int num_connectors)
4393 {
4394         struct drm_device *dev = crtc->dev;
4395         struct drm_i915_private *dev_priv = dev->dev_private;
4396         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4397         int pipe = intel_crtc->pipe;
4398         u32 dpll;
4399         bool is_sdvo;
4400
4401         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4402
4403         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4404                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4405
4406         dpll = DPLL_VGA_MODE_DIS;
4407
4408         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4409                 dpll |= DPLLB_MODE_LVDS;
4410         else
4411                 dpll |= DPLLB_MODE_DAC_SERIAL;
4412         if (is_sdvo) {
4413                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4414                 if (pixel_multiplier > 1) {
4415                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4416                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4417                 }
4418                 dpll |= DPLL_DVO_HIGH_SPEED;
4419         }
4420         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4421                 dpll |= DPLL_DVO_HIGH_SPEED;
4422
4423         /* compute bitmask from p1 value */
4424         if (IS_PINEVIEW(dev))
4425                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4426         else {
4427                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4428                 if (IS_G4X(dev) && reduced_clock)
4429                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4430         }
4431         switch (clock->p2) {
4432         case 5:
4433                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4434                 break;
4435         case 7:
4436                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4437                 break;
4438         case 10:
4439                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4440                 break;
4441         case 14:
4442                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4443                 break;
4444         }
4445         if (INTEL_INFO(dev)->gen >= 4)
4446                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4447
4448         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4449                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4450         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4451                 /* XXX: just matching BIOS for now */
4452                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4453                 dpll |= 3;
4454         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4455                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4456                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4457         else
4458                 dpll |= PLL_REF_INPUT_DREFCLK;
4459
4460         dpll |= DPLL_VCO_ENABLE;
4461         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4462         POSTING_READ(DPLL(pipe));
4463         udelay(150);
4464
4465         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4466          * This is an exception to the general rule that mode_set doesn't turn
4467          * things on.
4468          */
4469         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4470                 intel_update_lvds(crtc, clock, adjusted_mode);
4471
4472         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4473                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4474
4475         I915_WRITE(DPLL(pipe), dpll);
4476
4477         /* Wait for the clocks to stabilize. */
4478         POSTING_READ(DPLL(pipe));
4479         udelay(150);
4480
4481         if (INTEL_INFO(dev)->gen >= 4) {
4482                 u32 temp = 0;
4483                 if (is_sdvo) {
4484                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4485                         if (temp > 1)
4486                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4487                         else
4488                                 temp = 0;
4489                 }
4490                 I915_WRITE(DPLL_MD(pipe), temp);
4491         } else {
4492                 /* The pixel multiplier can only be updated once the
4493                  * DPLL is enabled and the clocks are stable.
4494                  *
4495                  * So write it again.
4496                  */
4497                 I915_WRITE(DPLL(pipe), dpll);
4498         }
4499 }
4500
4501 static void i8xx_update_pll(struct drm_crtc *crtc,
4502                             struct drm_display_mode *adjusted_mode,
4503                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4504                             int num_connectors)
4505 {
4506         struct drm_device *dev = crtc->dev;
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509         int pipe = intel_crtc->pipe;
4510         u32 dpll;
4511
4512         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4513
4514         dpll = DPLL_VGA_MODE_DIS;
4515
4516         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4517                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4518         } else {
4519                 if (clock->p1 == 2)
4520                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4521                 else
4522                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4523                 if (clock->p2 == 4)
4524                         dpll |= PLL_P2_DIVIDE_BY_4;
4525         }
4526
4527         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4528                 /* XXX: just matching BIOS for now */
4529                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4530                 dpll |= 3;
4531         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4532                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4533                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4534         else
4535                 dpll |= PLL_REF_INPUT_DREFCLK;
4536
4537         dpll |= DPLL_VCO_ENABLE;
4538         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4539         POSTING_READ(DPLL(pipe));
4540         udelay(150);
4541
4542         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4543          * This is an exception to the general rule that mode_set doesn't turn
4544          * things on.
4545          */
4546         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4547                 intel_update_lvds(crtc, clock, adjusted_mode);
4548
4549         I915_WRITE(DPLL(pipe), dpll);
4550
4551         /* Wait for the clocks to stabilize. */
4552         POSTING_READ(DPLL(pipe));
4553         udelay(150);
4554
4555         /* The pixel multiplier can only be updated once the
4556          * DPLL is enabled and the clocks are stable.
4557          *
4558          * So write it again.
4559          */
4560         I915_WRITE(DPLL(pipe), dpll);
4561 }
4562
4563 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4564                                    struct drm_display_mode *mode,
4565                                    struct drm_display_mode *adjusted_mode)
4566 {
4567         struct drm_device *dev = intel_crtc->base.dev;
4568         struct drm_i915_private *dev_priv = dev->dev_private;
4569         enum pipe pipe = intel_crtc->pipe;
4570         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4571         uint32_t vsyncshift;
4572
4573         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4574                 /* the chip adds 2 halflines automatically */
4575                 adjusted_mode->crtc_vtotal -= 1;
4576                 adjusted_mode->crtc_vblank_end -= 1;
4577                 vsyncshift = adjusted_mode->crtc_hsync_start
4578                              - adjusted_mode->crtc_htotal / 2;
4579         } else {
4580                 vsyncshift = 0;
4581         }
4582
4583         if (INTEL_INFO(dev)->gen > 3)
4584                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4585
4586         I915_WRITE(HTOTAL(cpu_transcoder),
4587                    (adjusted_mode->crtc_hdisplay - 1) |
4588                    ((adjusted_mode->crtc_htotal - 1) << 16));
4589         I915_WRITE(HBLANK(cpu_transcoder),
4590                    (adjusted_mode->crtc_hblank_start - 1) |
4591                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4592         I915_WRITE(HSYNC(cpu_transcoder),
4593                    (adjusted_mode->crtc_hsync_start - 1) |
4594                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4595
4596         I915_WRITE(VTOTAL(cpu_transcoder),
4597                    (adjusted_mode->crtc_vdisplay - 1) |
4598                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4599         I915_WRITE(VBLANK(cpu_transcoder),
4600                    (adjusted_mode->crtc_vblank_start - 1) |
4601                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4602         I915_WRITE(VSYNC(cpu_transcoder),
4603                    (adjusted_mode->crtc_vsync_start - 1) |
4604                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4605
4606         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4607          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4608          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4609          * bits. */
4610         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4611             (pipe == PIPE_B || pipe == PIPE_C))
4612                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4613
4614         /* pipesrc controls the size that is scaled from, which should
4615          * always be the user's requested size.
4616          */
4617         I915_WRITE(PIPESRC(pipe),
4618                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4619 }
4620
4621 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4622                               struct drm_display_mode *mode,
4623                               struct drm_display_mode *adjusted_mode,
4624                               int x, int y,
4625                               struct drm_framebuffer *fb)
4626 {
4627         struct drm_device *dev = crtc->dev;
4628         struct drm_i915_private *dev_priv = dev->dev_private;
4629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4630         int pipe = intel_crtc->pipe;
4631         int plane = intel_crtc->plane;
4632         int refclk, num_connectors = 0;
4633         intel_clock_t clock, reduced_clock;
4634         u32 dspcntr, pipeconf;
4635         bool ok, has_reduced_clock = false, is_sdvo = false;
4636         bool is_lvds = false, is_tv = false, is_dp = false;
4637         struct intel_encoder *encoder;
4638         const intel_limit_t *limit;
4639         int ret;
4640
4641         for_each_encoder_on_crtc(dev, crtc, encoder) {
4642                 switch (encoder->type) {
4643                 case INTEL_OUTPUT_LVDS:
4644                         is_lvds = true;
4645                         break;
4646                 case INTEL_OUTPUT_SDVO:
4647                 case INTEL_OUTPUT_HDMI:
4648                         is_sdvo = true;
4649                         if (encoder->needs_tv_clock)
4650                                 is_tv = true;
4651                         break;
4652                 case INTEL_OUTPUT_TVOUT:
4653                         is_tv = true;
4654                         break;
4655                 case INTEL_OUTPUT_DISPLAYPORT:
4656                         is_dp = true;
4657                         break;
4658                 }
4659
4660                 num_connectors++;
4661         }
4662
4663         refclk = i9xx_get_refclk(crtc, num_connectors);
4664
4665         /*
4666          * Returns a set of divisors for the desired target clock with the given
4667          * refclk, or FALSE.  The returned values represent the clock equation:
4668          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4669          */
4670         limit = intel_limit(crtc, refclk);
4671         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4672                              &clock);
4673         if (!ok) {
4674                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4675                 return -EINVAL;
4676         }
4677
4678         /* Ensure that the cursor is valid for the new mode before changing... */
4679         intel_crtc_update_cursor(crtc, true);
4680
4681         if (is_lvds && dev_priv->lvds_downclock_avail) {
4682                 /*
4683                  * Ensure we match the reduced clock's P to the target clock.
4684                  * If the clocks don't match, we can't switch the display clock
4685                  * by using the FP0/FP1. In such case we will disable the LVDS
4686                  * downclock feature.
4687                 */
4688                 has_reduced_clock = limit->find_pll(limit, crtc,
4689                                                     dev_priv->lvds_downclock,
4690                                                     refclk,
4691                                                     &clock,
4692                                                     &reduced_clock);
4693         }
4694
4695         if (is_sdvo && is_tv)
4696                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4697
4698         if (IS_GEN2(dev))
4699                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4700                                 has_reduced_clock ? &reduced_clock : NULL,
4701                                 num_connectors);
4702         else if (IS_VALLEYVIEW(dev))
4703                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4704                                 has_reduced_clock ? &reduced_clock : NULL,
4705                                 num_connectors);
4706         else
4707                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4708                                 has_reduced_clock ? &reduced_clock : NULL,
4709                                 num_connectors);
4710
4711         /* setup pipeconf */
4712         pipeconf = I915_READ(PIPECONF(pipe));
4713
4714         /* Set up the display plane register */
4715         dspcntr = DISPPLANE_GAMMA_ENABLE;
4716
4717         if (pipe == 0)
4718                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4719         else
4720                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4721
4722         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4723                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4724                  * core speed.
4725                  *
4726                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4727                  * pipe == 0 check?
4728                  */
4729                 if (mode->clock >
4730                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4731                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4732                 else
4733                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4734         }
4735
4736         /* default to 8bpc */
4737         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4738         if (is_dp) {
4739                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4740                         pipeconf |= PIPECONF_BPP_6 |
4741                                     PIPECONF_DITHER_EN |
4742                                     PIPECONF_DITHER_TYPE_SP;
4743                 }
4744         }
4745
4746         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4747                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4748                         pipeconf |= PIPECONF_BPP_6 |
4749                                         PIPECONF_ENABLE |
4750                                         I965_PIPECONF_ACTIVE;
4751                 }
4752         }
4753
4754         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4755         drm_mode_debug_printmodeline(mode);
4756
4757         if (HAS_PIPE_CXSR(dev)) {
4758                 if (intel_crtc->lowfreq_avail) {
4759                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4760                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4761                 } else {
4762                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4763                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4764                 }
4765         }
4766
4767         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4768         if (!IS_GEN2(dev) &&
4769             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4770                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4771         else
4772                 pipeconf |= PIPECONF_PROGRESSIVE;
4773
4774         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4775
4776         /* pipesrc and dspsize control the size that is scaled from,
4777          * which should always be the user's requested size.
4778          */
4779         I915_WRITE(DSPSIZE(plane),
4780                    ((mode->vdisplay - 1) << 16) |
4781                    (mode->hdisplay - 1));
4782         I915_WRITE(DSPPOS(plane), 0);
4783
4784         I915_WRITE(PIPECONF(pipe), pipeconf);
4785         POSTING_READ(PIPECONF(pipe));
4786         intel_enable_pipe(dev_priv, pipe, false);
4787
4788         intel_wait_for_vblank(dev, pipe);
4789
4790         I915_WRITE(DSPCNTR(plane), dspcntr);
4791         POSTING_READ(DSPCNTR(plane));
4792
4793         ret = intel_pipe_set_base(crtc, x, y, fb);
4794
4795         intel_update_watermarks(dev);
4796
4797         return ret;
4798 }
4799
4800 /*
4801  * Initialize reference clocks when the driver loads
4802  */
4803 void ironlake_init_pch_refclk(struct drm_device *dev)
4804 {
4805         struct drm_i915_private *dev_priv = dev->dev_private;
4806         struct drm_mode_config *mode_config = &dev->mode_config;
4807         struct intel_encoder *encoder;
4808         u32 temp;
4809         bool has_lvds = false;
4810         bool has_cpu_edp = false;
4811         bool has_pch_edp = false;
4812         bool has_panel = false;
4813         bool has_ck505 = false;
4814         bool can_ssc = false;
4815
4816         /* We need to take the global config into account */
4817         list_for_each_entry(encoder, &mode_config->encoder_list,
4818                             base.head) {
4819                 switch (encoder->type) {
4820                 case INTEL_OUTPUT_LVDS:
4821                         has_panel = true;
4822                         has_lvds = true;
4823                         break;
4824                 case INTEL_OUTPUT_EDP:
4825                         has_panel = true;
4826                         if (intel_encoder_is_pch_edp(&encoder->base))
4827                                 has_pch_edp = true;
4828                         else
4829                                 has_cpu_edp = true;
4830                         break;
4831                 }
4832         }
4833
4834         if (HAS_PCH_IBX(dev)) {
4835                 has_ck505 = dev_priv->display_clock_mode;
4836                 can_ssc = has_ck505;
4837         } else {
4838                 has_ck505 = false;
4839                 can_ssc = true;
4840         }
4841
4842         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4843                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4844                       has_ck505);
4845
4846         /* Ironlake: try to setup display ref clock before DPLL
4847          * enabling. This is only under driver's control after
4848          * PCH B stepping, previous chipset stepping should be
4849          * ignoring this setting.
4850          */
4851         temp = I915_READ(PCH_DREF_CONTROL);
4852         /* Always enable nonspread source */
4853         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4854
4855         if (has_ck505)
4856                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4857         else
4858                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4859
4860         if (has_panel) {
4861                 temp &= ~DREF_SSC_SOURCE_MASK;
4862                 temp |= DREF_SSC_SOURCE_ENABLE;
4863
4864                 /* SSC must be turned on before enabling the CPU output  */
4865                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4866                         DRM_DEBUG_KMS("Using SSC on panel\n");
4867                         temp |= DREF_SSC1_ENABLE;
4868                 } else
4869                         temp &= ~DREF_SSC1_ENABLE;
4870
4871                 /* Get SSC going before enabling the outputs */
4872                 I915_WRITE(PCH_DREF_CONTROL, temp);
4873                 POSTING_READ(PCH_DREF_CONTROL);
4874                 udelay(200);
4875
4876                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4877
4878                 /* Enable CPU source on CPU attached eDP */
4879                 if (has_cpu_edp) {
4880                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4881                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4882                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4883                         }
4884                         else
4885                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4886                 } else
4887                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4888
4889                 I915_WRITE(PCH_DREF_CONTROL, temp);
4890                 POSTING_READ(PCH_DREF_CONTROL);
4891                 udelay(200);
4892         } else {
4893                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4894
4895                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4896
4897                 /* Turn off CPU output */
4898                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4899
4900                 I915_WRITE(PCH_DREF_CONTROL, temp);
4901                 POSTING_READ(PCH_DREF_CONTROL);
4902                 udelay(200);
4903
4904                 /* Turn off the SSC source */
4905                 temp &= ~DREF_SSC_SOURCE_MASK;
4906                 temp |= DREF_SSC_SOURCE_DISABLE;
4907
4908                 /* Turn off SSC1 */
4909                 temp &= ~ DREF_SSC1_ENABLE;
4910
4911                 I915_WRITE(PCH_DREF_CONTROL, temp);
4912                 POSTING_READ(PCH_DREF_CONTROL);
4913                 udelay(200);
4914         }
4915 }
4916
4917 static int ironlake_get_refclk(struct drm_crtc *crtc)
4918 {
4919         struct drm_device *dev = crtc->dev;
4920         struct drm_i915_private *dev_priv = dev->dev_private;
4921         struct intel_encoder *encoder;
4922         struct intel_encoder *edp_encoder = NULL;
4923         int num_connectors = 0;
4924         bool is_lvds = false;
4925
4926         for_each_encoder_on_crtc(dev, crtc, encoder) {
4927                 switch (encoder->type) {
4928                 case INTEL_OUTPUT_LVDS:
4929                         is_lvds = true;
4930                         break;
4931                 case INTEL_OUTPUT_EDP:
4932                         edp_encoder = encoder;
4933                         break;
4934                 }
4935                 num_connectors++;
4936         }
4937
4938         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4939                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4940                               dev_priv->lvds_ssc_freq);
4941                 return dev_priv->lvds_ssc_freq * 1000;
4942         }
4943
4944         return 120000;
4945 }
4946
4947 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4948                                   struct drm_display_mode *adjusted_mode,
4949                                   bool dither)
4950 {
4951         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4952         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4953         int pipe = intel_crtc->pipe;
4954         uint32_t val;
4955
4956         val = I915_READ(PIPECONF(pipe));
4957
4958         val &= ~PIPE_BPC_MASK;
4959         switch (intel_crtc->bpp) {
4960         case 18:
4961                 val |= PIPE_6BPC;
4962                 break;
4963         case 24:
4964                 val |= PIPE_8BPC;
4965                 break;
4966         case 30:
4967                 val |= PIPE_10BPC;
4968                 break;
4969         case 36:
4970                 val |= PIPE_12BPC;
4971                 break;
4972         default:
4973                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4974                 BUG();
4975         }
4976
4977         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4978         if (dither)
4979                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4980
4981         val &= ~PIPECONF_INTERLACE_MASK;
4982         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4983                 val |= PIPECONF_INTERLACED_ILK;
4984         else
4985                 val |= PIPECONF_PROGRESSIVE;
4986
4987         I915_WRITE(PIPECONF(pipe), val);
4988         POSTING_READ(PIPECONF(pipe));
4989 }
4990
4991 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4992                                  struct drm_display_mode *adjusted_mode,
4993                                  bool dither)
4994 {
4995         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4997         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4998         uint32_t val;
4999
5000         val = I915_READ(PIPECONF(cpu_transcoder));
5001
5002         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5003         if (dither)
5004                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5005
5006         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5007         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5008                 val |= PIPECONF_INTERLACED_ILK;
5009         else
5010                 val |= PIPECONF_PROGRESSIVE;
5011
5012         I915_WRITE(PIPECONF(cpu_transcoder), val);
5013         POSTING_READ(PIPECONF(cpu_transcoder));
5014 }
5015
5016 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5017                                     struct drm_display_mode *adjusted_mode,
5018                                     intel_clock_t *clock,
5019                                     bool *has_reduced_clock,
5020                                     intel_clock_t *reduced_clock)
5021 {
5022         struct drm_device *dev = crtc->dev;
5023         struct drm_i915_private *dev_priv = dev->dev_private;
5024         struct intel_encoder *intel_encoder;
5025         int refclk;
5026         const intel_limit_t *limit;
5027         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5028
5029         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5030                 switch (intel_encoder->type) {
5031                 case INTEL_OUTPUT_LVDS:
5032                         is_lvds = true;
5033                         break;
5034                 case INTEL_OUTPUT_SDVO:
5035                 case INTEL_OUTPUT_HDMI:
5036                         is_sdvo = true;
5037                         if (intel_encoder->needs_tv_clock)
5038                                 is_tv = true;
5039                         break;
5040                 case INTEL_OUTPUT_TVOUT:
5041                         is_tv = true;
5042                         break;
5043                 }
5044         }
5045
5046         refclk = ironlake_get_refclk(crtc);
5047
5048         /*
5049          * Returns a set of divisors for the desired target clock with the given
5050          * refclk, or FALSE.  The returned values represent the clock equation:
5051          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5052          */
5053         limit = intel_limit(crtc, refclk);
5054         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5055                               clock);
5056         if (!ret)
5057                 return false;
5058
5059         if (is_lvds && dev_priv->lvds_downclock_avail) {
5060                 /*
5061                  * Ensure we match the reduced clock's P to the target clock.
5062                  * If the clocks don't match, we can't switch the display clock
5063                  * by using the FP0/FP1. In such case we will disable the LVDS
5064                  * downclock feature.
5065                 */
5066                 *has_reduced_clock = limit->find_pll(limit, crtc,
5067                                                      dev_priv->lvds_downclock,
5068                                                      refclk,
5069                                                      clock,
5070                                                      reduced_clock);
5071         }
5072
5073         if (is_sdvo && is_tv)
5074                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5075
5076         return true;
5077 }
5078
5079 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5080 {
5081         struct drm_i915_private *dev_priv = dev->dev_private;
5082         uint32_t temp;
5083
5084         temp = I915_READ(SOUTH_CHICKEN1);
5085         if (temp & FDI_BC_BIFURCATION_SELECT)
5086                 return;
5087
5088         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5089         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5090
5091         temp |= FDI_BC_BIFURCATION_SELECT;
5092         DRM_DEBUG_KMS("enabling fdi C rx\n");
5093         I915_WRITE(SOUTH_CHICKEN1, temp);
5094         POSTING_READ(SOUTH_CHICKEN1);
5095 }
5096
5097 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5098 {
5099         struct drm_device *dev = intel_crtc->base.dev;
5100         struct drm_i915_private *dev_priv = dev->dev_private;
5101         struct intel_crtc *pipe_B_crtc =
5102                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5103
5104         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5105                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5106         if (intel_crtc->fdi_lanes > 4) {
5107                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5108                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5109                 /* Clamp lanes to avoid programming the hw with bogus values. */
5110                 intel_crtc->fdi_lanes = 4;
5111
5112                 return false;
5113         }
5114
5115         if (dev_priv->num_pipe == 2)
5116                 return true;
5117
5118         switch (intel_crtc->pipe) {
5119         case PIPE_A:
5120                 return true;
5121         case PIPE_B:
5122                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5123                     intel_crtc->fdi_lanes > 2) {
5124                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5125                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5126                         /* Clamp lanes to avoid programming the hw with bogus values. */
5127                         intel_crtc->fdi_lanes = 2;
5128
5129                         return false;
5130                 }
5131
5132                 if (intel_crtc->fdi_lanes > 2)
5133                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5134                 else
5135                         cpt_enable_fdi_bc_bifurcation(dev);
5136
5137                 return true;
5138         case PIPE_C:
5139                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5140                         if (intel_crtc->fdi_lanes > 2) {
5141                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5142                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5143                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5144                                 intel_crtc->fdi_lanes = 2;
5145
5146                                 return false;
5147                         }
5148                 } else {
5149                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5150                         return false;
5151                 }
5152
5153                 cpt_enable_fdi_bc_bifurcation(dev);
5154
5155                 return true;
5156         default:
5157                 BUG();
5158         }
5159 }
5160
5161 static void ironlake_set_m_n(struct drm_crtc *crtc,
5162                              struct drm_display_mode *mode,
5163                              struct drm_display_mode *adjusted_mode)
5164 {
5165         struct drm_device *dev = crtc->dev;
5166         struct drm_i915_private *dev_priv = dev->dev_private;
5167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5168         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5169         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5170         struct fdi_m_n m_n = {0};
5171         int target_clock, pixel_multiplier, lane, link_bw;
5172         bool is_dp = false, is_cpu_edp = false;
5173
5174         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5175                 switch (intel_encoder->type) {
5176                 case INTEL_OUTPUT_DISPLAYPORT:
5177                         is_dp = true;
5178                         break;
5179                 case INTEL_OUTPUT_EDP:
5180                         is_dp = true;
5181                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5182                                 is_cpu_edp = true;
5183                         edp_encoder = intel_encoder;
5184                         break;
5185                 }
5186         }
5187
5188         /* FDI link */
5189         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5190         lane = 0;
5191         /* CPU eDP doesn't require FDI link, so just set DP M/N
5192            according to current link config */
5193         if (is_cpu_edp) {
5194                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5195         } else {
5196                 /* FDI is a binary signal running at ~2.7GHz, encoding
5197                  * each output octet as 10 bits. The actual frequency
5198                  * is stored as a divider into a 100MHz clock, and the
5199                  * mode pixel clock is stored in units of 1KHz.
5200                  * Hence the bw of each lane in terms of the mode signal
5201                  * is:
5202                  */
5203                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5204         }
5205
5206         /* [e]DP over FDI requires target mode clock instead of link clock. */
5207         if (edp_encoder)
5208                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5209         else if (is_dp)
5210                 target_clock = mode->clock;
5211         else
5212                 target_clock = adjusted_mode->clock;
5213
5214         if (!lane) {
5215                 /*
5216                  * Account for spread spectrum to avoid
5217                  * oversubscribing the link. Max center spread
5218                  * is 2.5%; use 5% for safety's sake.
5219                  */
5220                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5221                 lane = bps / (link_bw * 8) + 1;
5222         }
5223
5224         intel_crtc->fdi_lanes = lane;
5225
5226         if (pixel_multiplier > 1)
5227                 link_bw *= pixel_multiplier;
5228         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5229                              &m_n);
5230
5231         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5232         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5233         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5234         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5235 }
5236
5237 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5238                                       struct drm_display_mode *adjusted_mode,
5239                                       intel_clock_t *clock, u32 fp)
5240 {
5241         struct drm_crtc *crtc = &intel_crtc->base;
5242         struct drm_device *dev = crtc->dev;
5243         struct drm_i915_private *dev_priv = dev->dev_private;
5244         struct intel_encoder *intel_encoder;
5245         uint32_t dpll;
5246         int factor, pixel_multiplier, num_connectors = 0;
5247         bool is_lvds = false, is_sdvo = false, is_tv = false;
5248         bool is_dp = false, is_cpu_edp = false;
5249
5250         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5251                 switch (intel_encoder->type) {
5252                 case INTEL_OUTPUT_LVDS:
5253                         is_lvds = true;
5254                         break;
5255                 case INTEL_OUTPUT_SDVO:
5256                 case INTEL_OUTPUT_HDMI:
5257                         is_sdvo = true;
5258                         if (intel_encoder->needs_tv_clock)
5259                                 is_tv = true;
5260                         break;
5261                 case INTEL_OUTPUT_TVOUT:
5262                         is_tv = true;
5263                         break;
5264                 case INTEL_OUTPUT_DISPLAYPORT:
5265                         is_dp = true;
5266                         break;
5267                 case INTEL_OUTPUT_EDP:
5268                         is_dp = true;
5269                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5270                                 is_cpu_edp = true;
5271                         break;
5272                 }
5273
5274                 num_connectors++;
5275         }
5276
5277         /* Enable autotuning of the PLL clock (if permissible) */
5278         factor = 21;
5279         if (is_lvds) {
5280                 if ((intel_panel_use_ssc(dev_priv) &&
5281                      dev_priv->lvds_ssc_freq == 100) ||
5282                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5283                         factor = 25;
5284         } else if (is_sdvo && is_tv)
5285                 factor = 20;
5286
5287         if (clock->m < factor * clock->n)
5288                 fp |= FP_CB_TUNE;
5289
5290         dpll = 0;
5291
5292         if (is_lvds)
5293                 dpll |= DPLLB_MODE_LVDS;
5294         else
5295                 dpll |= DPLLB_MODE_DAC_SERIAL;
5296         if (is_sdvo) {
5297                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5298                 if (pixel_multiplier > 1) {
5299                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5300                 }
5301                 dpll |= DPLL_DVO_HIGH_SPEED;
5302         }
5303         if (is_dp && !is_cpu_edp)
5304                 dpll |= DPLL_DVO_HIGH_SPEED;
5305
5306         /* compute bitmask from p1 value */
5307         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5308         /* also FPA1 */
5309         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5310
5311         switch (clock->p2) {
5312         case 5:
5313                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5314                 break;
5315         case 7:
5316                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5317                 break;
5318         case 10:
5319                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5320                 break;
5321         case 14:
5322                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5323                 break;
5324         }
5325
5326         if (is_sdvo && is_tv)
5327                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5328         else if (is_tv)
5329                 /* XXX: just matching BIOS for now */
5330                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5331                 dpll |= 3;
5332         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5333                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5334         else
5335                 dpll |= PLL_REF_INPUT_DREFCLK;
5336
5337         return dpll;
5338 }
5339
5340 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5341                                   struct drm_display_mode *mode,
5342                                   struct drm_display_mode *adjusted_mode,
5343                                   int x, int y,
5344                                   struct drm_framebuffer *fb)
5345 {
5346         struct drm_device *dev = crtc->dev;
5347         struct drm_i915_private *dev_priv = dev->dev_private;
5348         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5349         int pipe = intel_crtc->pipe;
5350         int plane = intel_crtc->plane;
5351         int num_connectors = 0;
5352         intel_clock_t clock, reduced_clock;
5353         u32 dpll, fp = 0, fp2 = 0;
5354         bool ok, has_reduced_clock = false;
5355         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5356         struct intel_encoder *encoder;
5357         u32 temp;
5358         int ret;
5359         bool dither, fdi_config_ok;
5360
5361         for_each_encoder_on_crtc(dev, crtc, encoder) {
5362                 switch (encoder->type) {
5363                 case INTEL_OUTPUT_LVDS:
5364                         is_lvds = true;
5365                         break;
5366                 case INTEL_OUTPUT_DISPLAYPORT:
5367                         is_dp = true;
5368                         break;
5369                 case INTEL_OUTPUT_EDP:
5370                         is_dp = true;
5371                         if (!intel_encoder_is_pch_edp(&encoder->base))
5372                                 is_cpu_edp = true;
5373                         break;
5374                 }
5375
5376                 num_connectors++;
5377         }
5378
5379         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5380              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5381
5382         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5383                                      &has_reduced_clock, &reduced_clock);
5384         if (!ok) {
5385                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5386                 return -EINVAL;
5387         }
5388
5389         /* Ensure that the cursor is valid for the new mode before changing... */
5390         intel_crtc_update_cursor(crtc, true);
5391
5392         /* determine panel color depth */
5393         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5394                                               adjusted_mode);
5395         if (is_lvds && dev_priv->lvds_dither)
5396                 dither = true;
5397
5398         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5399         if (has_reduced_clock)
5400                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5401                         reduced_clock.m2;
5402
5403         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5404
5405         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5406         drm_mode_debug_printmodeline(mode);
5407
5408         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5409         if (!is_cpu_edp) {
5410                 struct intel_pch_pll *pll;
5411
5412                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5413                 if (pll == NULL) {
5414                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5415                                          pipe);
5416                         return -EINVAL;
5417                 }
5418         } else
5419                 intel_put_pch_pll(intel_crtc);
5420
5421         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5422          * This is an exception to the general rule that mode_set doesn't turn
5423          * things on.
5424          */
5425         if (is_lvds) {
5426                 temp = I915_READ(PCH_LVDS);
5427                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5428                 if (HAS_PCH_CPT(dev)) {
5429                         temp &= ~PORT_TRANS_SEL_MASK;
5430                         temp |= PORT_TRANS_SEL_CPT(pipe);
5431                 } else {
5432                         if (pipe == 1)
5433                                 temp |= LVDS_PIPEB_SELECT;
5434                         else
5435                                 temp &= ~LVDS_PIPEB_SELECT;
5436                 }
5437
5438                 /* set the corresponsding LVDS_BORDER bit */
5439                 temp |= dev_priv->lvds_border_bits;
5440                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5441                  * set the DPLLs for dual-channel mode or not.
5442                  */
5443                 if (clock.p2 == 7)
5444                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5445                 else
5446                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5447
5448                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5449                  * appropriately here, but we need to look more thoroughly into how
5450                  * panels behave in the two modes.
5451                  */
5452                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5453                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5454                         temp |= LVDS_HSYNC_POLARITY;
5455                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5456                         temp |= LVDS_VSYNC_POLARITY;
5457                 I915_WRITE(PCH_LVDS, temp);
5458         }
5459
5460         if (is_dp && !is_cpu_edp) {
5461                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5462         } else {
5463                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5464                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5465                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5466                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5467                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5468         }
5469
5470         if (intel_crtc->pch_pll) {
5471                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5472
5473                 /* Wait for the clocks to stabilize. */
5474                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5475                 udelay(150);
5476
5477                 /* The pixel multiplier can only be updated once the
5478                  * DPLL is enabled and the clocks are stable.
5479                  *
5480                  * So write it again.
5481                  */
5482                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5483         }
5484
5485         intel_crtc->lowfreq_avail = false;
5486         if (intel_crtc->pch_pll) {
5487                 if (is_lvds && has_reduced_clock && i915_powersave) {
5488                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5489                         intel_crtc->lowfreq_avail = true;
5490                 } else {
5491                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5492                 }
5493         }
5494
5495         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5496
5497         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5498          * ironlake_check_fdi_lanes. */
5499         ironlake_set_m_n(crtc, mode, adjusted_mode);
5500
5501         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5502
5503         if (is_cpu_edp)
5504                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5505
5506         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5507
5508         intel_wait_for_vblank(dev, pipe);
5509
5510         /* Set up the display plane register */
5511         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5512         POSTING_READ(DSPCNTR(plane));
5513
5514         ret = intel_pipe_set_base(crtc, x, y, fb);
5515
5516         intel_update_watermarks(dev);
5517
5518         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5519
5520         return fdi_config_ok ? ret : -EINVAL;
5521 }
5522
5523 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5524                                  struct drm_display_mode *mode,
5525                                  struct drm_display_mode *adjusted_mode,
5526                                  int x, int y,
5527                                  struct drm_framebuffer *fb)
5528 {
5529         struct drm_device *dev = crtc->dev;
5530         struct drm_i915_private *dev_priv = dev->dev_private;
5531         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5532         int pipe = intel_crtc->pipe;
5533         int plane = intel_crtc->plane;
5534         int num_connectors = 0;
5535         intel_clock_t clock, reduced_clock;
5536         u32 dpll = 0, fp = 0, fp2 = 0;
5537         bool ok, has_reduced_clock = false;
5538         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5539         struct intel_encoder *encoder;
5540         u32 temp;
5541         int ret;
5542         bool dither;
5543
5544         for_each_encoder_on_crtc(dev, crtc, encoder) {
5545                 switch (encoder->type) {
5546                 case INTEL_OUTPUT_LVDS:
5547                         is_lvds = true;
5548                         break;
5549                 case INTEL_OUTPUT_DISPLAYPORT:
5550                         is_dp = true;
5551                         break;
5552                 case INTEL_OUTPUT_EDP:
5553                         is_dp = true;
5554                         if (!intel_encoder_is_pch_edp(&encoder->base))
5555                                 is_cpu_edp = true;
5556                         break;
5557                 }
5558
5559                 num_connectors++;
5560         }
5561
5562         if (is_cpu_edp)
5563                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5564         else
5565                 intel_crtc->cpu_transcoder = pipe;
5566
5567         /* We are not sure yet this won't happen. */
5568         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5569              INTEL_PCH_TYPE(dev));
5570
5571         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5572              num_connectors, pipe_name(pipe));
5573
5574         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5575                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5576
5577         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5578
5579         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5580                 return -EINVAL;
5581
5582         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5583                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5584                                              &has_reduced_clock,
5585                                              &reduced_clock);
5586                 if (!ok) {
5587                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5588                         return -EINVAL;
5589                 }
5590         }
5591
5592         /* Ensure that the cursor is valid for the new mode before changing... */
5593         intel_crtc_update_cursor(crtc, true);
5594
5595         /* determine panel color depth */
5596         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5597                                               adjusted_mode);
5598         if (is_lvds && dev_priv->lvds_dither)
5599                 dither = true;
5600
5601         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5602         drm_mode_debug_printmodeline(mode);
5603
5604         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5605                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5606                 if (has_reduced_clock)
5607                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5608                               reduced_clock.m2;
5609
5610                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5611                                              fp);
5612
5613                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5614                  * own on pre-Haswell/LPT generation */
5615                 if (!is_cpu_edp) {
5616                         struct intel_pch_pll *pll;
5617
5618                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5619                         if (pll == NULL) {
5620                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5621                                                  pipe);
5622                                 return -EINVAL;
5623                         }
5624                 } else
5625                         intel_put_pch_pll(intel_crtc);
5626
5627                 /* The LVDS pin pair needs to be on before the DPLLs are
5628                  * enabled.  This is an exception to the general rule that
5629                  * mode_set doesn't turn things on.
5630                  */
5631                 if (is_lvds) {
5632                         temp = I915_READ(PCH_LVDS);
5633                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5634                         if (HAS_PCH_CPT(dev)) {
5635                                 temp &= ~PORT_TRANS_SEL_MASK;
5636                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5637                         } else {
5638                                 if (pipe == 1)
5639                                         temp |= LVDS_PIPEB_SELECT;
5640                                 else
5641                                         temp &= ~LVDS_PIPEB_SELECT;
5642                         }
5643
5644                         /* set the corresponsding LVDS_BORDER bit */
5645                         temp |= dev_priv->lvds_border_bits;
5646                         /* Set the B0-B3 data pairs corresponding to whether
5647                          * we're going to set the DPLLs for dual-channel mode or
5648                          * not.
5649                          */
5650                         if (clock.p2 == 7)
5651                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5652                         else
5653                                 temp &= ~(LVDS_B0B3_POWER_UP |
5654                                           LVDS_CLKB_POWER_UP);
5655
5656                         /* It would be nice to set 24 vs 18-bit mode
5657                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5658                          * look more thoroughly into how panels behave in the
5659                          * two modes.
5660                          */
5661                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5662                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5663                                 temp |= LVDS_HSYNC_POLARITY;
5664                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5665                                 temp |= LVDS_VSYNC_POLARITY;
5666                         I915_WRITE(PCH_LVDS, temp);
5667                 }
5668         }
5669
5670         if (is_dp && !is_cpu_edp) {
5671                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5672         } else {
5673                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5674                         /* For non-DP output, clear any trans DP clock recovery
5675                          * setting.*/
5676                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5677                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5678                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5679                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5680                 }
5681         }
5682
5683         intel_crtc->lowfreq_avail = false;
5684         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5685                 if (intel_crtc->pch_pll) {
5686                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5687
5688                         /* Wait for the clocks to stabilize. */
5689                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5690                         udelay(150);
5691
5692                         /* The pixel multiplier can only be updated once the
5693                          * DPLL is enabled and the clocks are stable.
5694                          *
5695                          * So write it again.
5696                          */
5697                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5698                 }
5699
5700                 if (intel_crtc->pch_pll) {
5701                         if (is_lvds && has_reduced_clock && i915_powersave) {
5702                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5703                                 intel_crtc->lowfreq_avail = true;
5704                         } else {
5705                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5706                         }
5707                 }
5708         }
5709
5710         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5711
5712         if (!is_dp || is_cpu_edp)
5713                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5714
5715         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5716                 if (is_cpu_edp)
5717                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5718
5719         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5720
5721         /* Set up the display plane register */
5722         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5723         POSTING_READ(DSPCNTR(plane));
5724
5725         ret = intel_pipe_set_base(crtc, x, y, fb);
5726
5727         intel_update_watermarks(dev);
5728
5729         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5730
5731         return ret;
5732 }
5733
5734 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5735                                struct drm_display_mode *mode,
5736                                struct drm_display_mode *adjusted_mode,
5737                                int x, int y,
5738                                struct drm_framebuffer *fb)
5739 {
5740         struct drm_device *dev = crtc->dev;
5741         struct drm_i915_private *dev_priv = dev->dev_private;
5742         struct drm_encoder_helper_funcs *encoder_funcs;
5743         struct intel_encoder *encoder;
5744         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5745         int pipe = intel_crtc->pipe;
5746         int ret;
5747
5748         drm_vblank_pre_modeset(dev, pipe);
5749
5750         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5751                                               x, y, fb);
5752         drm_vblank_post_modeset(dev, pipe);
5753
5754         if (ret != 0)
5755                 return ret;
5756
5757         for_each_encoder_on_crtc(dev, crtc, encoder) {
5758                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5759                         encoder->base.base.id,
5760                         drm_get_encoder_name(&encoder->base),
5761                         mode->base.id, mode->name);
5762                 encoder_funcs = encoder->base.helper_private;
5763                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5764         }
5765
5766         return 0;
5767 }
5768
5769 static bool intel_eld_uptodate(struct drm_connector *connector,
5770                                int reg_eldv, uint32_t bits_eldv,
5771                                int reg_elda, uint32_t bits_elda,
5772                                int reg_edid)
5773 {
5774         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5775         uint8_t *eld = connector->eld;
5776         uint32_t i;
5777
5778         i = I915_READ(reg_eldv);
5779         i &= bits_eldv;
5780
5781         if (!eld[0])
5782                 return !i;
5783
5784         if (!i)
5785                 return false;
5786
5787         i = I915_READ(reg_elda);
5788         i &= ~bits_elda;
5789         I915_WRITE(reg_elda, i);
5790
5791         for (i = 0; i < eld[2]; i++)
5792                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5793                         return false;
5794
5795         return true;
5796 }
5797
5798 static void g4x_write_eld(struct drm_connector *connector,
5799                           struct drm_crtc *crtc)
5800 {
5801         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5802         uint8_t *eld = connector->eld;
5803         uint32_t eldv;
5804         uint32_t len;
5805         uint32_t i;
5806
5807         i = I915_READ(G4X_AUD_VID_DID);
5808
5809         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5810                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5811         else
5812                 eldv = G4X_ELDV_DEVCTG;
5813
5814         if (intel_eld_uptodate(connector,
5815                                G4X_AUD_CNTL_ST, eldv,
5816                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5817                                G4X_HDMIW_HDMIEDID))
5818                 return;
5819
5820         i = I915_READ(G4X_AUD_CNTL_ST);
5821         i &= ~(eldv | G4X_ELD_ADDR);
5822         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5823         I915_WRITE(G4X_AUD_CNTL_ST, i);
5824
5825         if (!eld[0])
5826                 return;
5827
5828         len = min_t(uint8_t, eld[2], len);
5829         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5830         for (i = 0; i < len; i++)
5831                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5832
5833         i = I915_READ(G4X_AUD_CNTL_ST);
5834         i |= eldv;
5835         I915_WRITE(G4X_AUD_CNTL_ST, i);
5836 }
5837
5838 static void haswell_write_eld(struct drm_connector *connector,
5839                                      struct drm_crtc *crtc)
5840 {
5841         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5842         uint8_t *eld = connector->eld;
5843         struct drm_device *dev = crtc->dev;
5844         uint32_t eldv;
5845         uint32_t i;
5846         int len;
5847         int pipe = to_intel_crtc(crtc)->pipe;
5848         int tmp;
5849
5850         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5851         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5852         int aud_config = HSW_AUD_CFG(pipe);
5853         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5854
5855
5856         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5857
5858         /* Audio output enable */
5859         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5860         tmp = I915_READ(aud_cntrl_st2);
5861         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5862         I915_WRITE(aud_cntrl_st2, tmp);
5863
5864         /* Wait for 1 vertical blank */
5865         intel_wait_for_vblank(dev, pipe);
5866
5867         /* Set ELD valid state */
5868         tmp = I915_READ(aud_cntrl_st2);
5869         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5870         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5871         I915_WRITE(aud_cntrl_st2, tmp);
5872         tmp = I915_READ(aud_cntrl_st2);
5873         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5874
5875         /* Enable HDMI mode */
5876         tmp = I915_READ(aud_config);
5877         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5878         /* clear N_programing_enable and N_value_index */
5879         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5880         I915_WRITE(aud_config, tmp);
5881
5882         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5883
5884         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5885
5886         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5887                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5888                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5889                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5890         } else
5891                 I915_WRITE(aud_config, 0);
5892
5893         if (intel_eld_uptodate(connector,
5894                                aud_cntrl_st2, eldv,
5895                                aud_cntl_st, IBX_ELD_ADDRESS,
5896                                hdmiw_hdmiedid))
5897                 return;
5898
5899         i = I915_READ(aud_cntrl_st2);
5900         i &= ~eldv;
5901         I915_WRITE(aud_cntrl_st2, i);
5902
5903         if (!eld[0])
5904                 return;
5905
5906         i = I915_READ(aud_cntl_st);
5907         i &= ~IBX_ELD_ADDRESS;
5908         I915_WRITE(aud_cntl_st, i);
5909         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5910         DRM_DEBUG_DRIVER("port num:%d\n", i);
5911
5912         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5913         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5914         for (i = 0; i < len; i++)
5915                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5916
5917         i = I915_READ(aud_cntrl_st2);
5918         i |= eldv;
5919         I915_WRITE(aud_cntrl_st2, i);
5920
5921 }
5922
5923 static void ironlake_write_eld(struct drm_connector *connector,
5924                                      struct drm_crtc *crtc)
5925 {
5926         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5927         uint8_t *eld = connector->eld;
5928         uint32_t eldv;
5929         uint32_t i;
5930         int len;
5931         int hdmiw_hdmiedid;
5932         int aud_config;
5933         int aud_cntl_st;
5934         int aud_cntrl_st2;
5935         int pipe = to_intel_crtc(crtc)->pipe;
5936
5937         if (HAS_PCH_IBX(connector->dev)) {
5938                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5939                 aud_config = IBX_AUD_CFG(pipe);
5940                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5941                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5942         } else {
5943                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5944                 aud_config = CPT_AUD_CFG(pipe);
5945                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5946                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5947         }
5948
5949         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5950
5951         i = I915_READ(aud_cntl_st);
5952         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5953         if (!i) {
5954                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5955                 /* operate blindly on all ports */
5956                 eldv = IBX_ELD_VALIDB;
5957                 eldv |= IBX_ELD_VALIDB << 4;
5958                 eldv |= IBX_ELD_VALIDB << 8;
5959         } else {
5960                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5961                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5962         }
5963
5964         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5965                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5966                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5967                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5968         } else
5969                 I915_WRITE(aud_config, 0);
5970
5971         if (intel_eld_uptodate(connector,
5972                                aud_cntrl_st2, eldv,
5973                                aud_cntl_st, IBX_ELD_ADDRESS,
5974                                hdmiw_hdmiedid))
5975                 return;
5976
5977         i = I915_READ(aud_cntrl_st2);
5978         i &= ~eldv;
5979         I915_WRITE(aud_cntrl_st2, i);
5980
5981         if (!eld[0])
5982                 return;
5983
5984         i = I915_READ(aud_cntl_st);
5985         i &= ~IBX_ELD_ADDRESS;
5986         I915_WRITE(aud_cntl_st, i);
5987
5988         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5989         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5990         for (i = 0; i < len; i++)
5991                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5992
5993         i = I915_READ(aud_cntrl_st2);
5994         i |= eldv;
5995         I915_WRITE(aud_cntrl_st2, i);
5996 }
5997
5998 void intel_write_eld(struct drm_encoder *encoder,
5999                      struct drm_display_mode *mode)
6000 {
6001         struct drm_crtc *crtc = encoder->crtc;
6002         struct drm_connector *connector;
6003         struct drm_device *dev = encoder->dev;
6004         struct drm_i915_private *dev_priv = dev->dev_private;
6005
6006         connector = drm_select_eld(encoder, mode);
6007         if (!connector)
6008                 return;
6009
6010         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6011                          connector->base.id,
6012                          drm_get_connector_name(connector),
6013                          connector->encoder->base.id,
6014                          drm_get_encoder_name(connector->encoder));
6015
6016         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6017
6018         if (dev_priv->display.write_eld)
6019                 dev_priv->display.write_eld(connector, crtc);
6020 }
6021
6022 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6023 void intel_crtc_load_lut(struct drm_crtc *crtc)
6024 {
6025         struct drm_device *dev = crtc->dev;
6026         struct drm_i915_private *dev_priv = dev->dev_private;
6027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6028         int palreg = PALETTE(intel_crtc->pipe);
6029         int i;
6030
6031         /* The clocks have to be on to load the palette. */
6032         if (!crtc->enabled || !intel_crtc->active)
6033                 return;
6034
6035         /* use legacy palette for Ironlake */
6036         if (HAS_PCH_SPLIT(dev))
6037                 palreg = LGC_PALETTE(intel_crtc->pipe);
6038
6039         for (i = 0; i < 256; i++) {
6040                 I915_WRITE(palreg + 4 * i,
6041                            (intel_crtc->lut_r[i] << 16) |
6042                            (intel_crtc->lut_g[i] << 8) |
6043                            intel_crtc->lut_b[i]);
6044         }
6045 }
6046
6047 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6048 {
6049         struct drm_device *dev = crtc->dev;
6050         struct drm_i915_private *dev_priv = dev->dev_private;
6051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6052         bool visible = base != 0;
6053         u32 cntl;
6054
6055         if (intel_crtc->cursor_visible == visible)
6056                 return;
6057
6058         cntl = I915_READ(_CURACNTR);
6059         if (visible) {
6060                 /* On these chipsets we can only modify the base whilst
6061                  * the cursor is disabled.
6062                  */
6063                 I915_WRITE(_CURABASE, base);
6064
6065                 cntl &= ~(CURSOR_FORMAT_MASK);
6066                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6067                 cntl |= CURSOR_ENABLE |
6068                         CURSOR_GAMMA_ENABLE |
6069                         CURSOR_FORMAT_ARGB;
6070         } else
6071                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6072         I915_WRITE(_CURACNTR, cntl);
6073
6074         intel_crtc->cursor_visible = visible;
6075 }
6076
6077 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6078 {
6079         struct drm_device *dev = crtc->dev;
6080         struct drm_i915_private *dev_priv = dev->dev_private;
6081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6082         int pipe = intel_crtc->pipe;
6083         bool visible = base != 0;
6084
6085         if (intel_crtc->cursor_visible != visible) {
6086                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6087                 if (base) {
6088                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6089                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6090                         cntl |= pipe << 28; /* Connect to correct pipe */
6091                 } else {
6092                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6093                         cntl |= CURSOR_MODE_DISABLE;
6094                 }
6095                 I915_WRITE(CURCNTR(pipe), cntl);
6096
6097                 intel_crtc->cursor_visible = visible;
6098         }
6099         /* and commit changes on next vblank */
6100         I915_WRITE(CURBASE(pipe), base);
6101 }
6102
6103 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6104 {
6105         struct drm_device *dev = crtc->dev;
6106         struct drm_i915_private *dev_priv = dev->dev_private;
6107         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6108         int pipe = intel_crtc->pipe;
6109         bool visible = base != 0;
6110
6111         if (intel_crtc->cursor_visible != visible) {
6112                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6113                 if (base) {
6114                         cntl &= ~CURSOR_MODE;
6115                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6116                 } else {
6117                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6118                         cntl |= CURSOR_MODE_DISABLE;
6119                 }
6120                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6121
6122                 intel_crtc->cursor_visible = visible;
6123         }
6124         /* and commit changes on next vblank */
6125         I915_WRITE(CURBASE_IVB(pipe), base);
6126 }
6127
6128 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6129 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6130                                      bool on)
6131 {
6132         struct drm_device *dev = crtc->dev;
6133         struct drm_i915_private *dev_priv = dev->dev_private;
6134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6135         int pipe = intel_crtc->pipe;
6136         int x = intel_crtc->cursor_x;
6137         int y = intel_crtc->cursor_y;
6138         u32 base, pos;
6139         bool visible;
6140
6141         pos = 0;
6142
6143         if (on && crtc->enabled && crtc->fb) {
6144                 base = intel_crtc->cursor_addr;
6145                 if (x > (int) crtc->fb->width)
6146                         base = 0;
6147
6148                 if (y > (int) crtc->fb->height)
6149                         base = 0;
6150         } else
6151                 base = 0;
6152
6153         if (x < 0) {
6154                 if (x + intel_crtc->cursor_width < 0)
6155                         base = 0;
6156
6157                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6158                 x = -x;
6159         }
6160         pos |= x << CURSOR_X_SHIFT;
6161
6162         if (y < 0) {
6163                 if (y + intel_crtc->cursor_height < 0)
6164                         base = 0;
6165
6166                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6167                 y = -y;
6168         }
6169         pos |= y << CURSOR_Y_SHIFT;
6170
6171         visible = base != 0;
6172         if (!visible && !intel_crtc->cursor_visible)
6173                 return;
6174
6175         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6176                 I915_WRITE(CURPOS_IVB(pipe), pos);
6177                 ivb_update_cursor(crtc, base);
6178         } else {
6179                 I915_WRITE(CURPOS(pipe), pos);
6180                 if (IS_845G(dev) || IS_I865G(dev))
6181                         i845_update_cursor(crtc, base);
6182                 else
6183                         i9xx_update_cursor(crtc, base);
6184         }
6185 }
6186
6187 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6188                                  struct drm_file *file,
6189                                  uint32_t handle,
6190                                  uint32_t width, uint32_t height)
6191 {
6192         struct drm_device *dev = crtc->dev;
6193         struct drm_i915_private *dev_priv = dev->dev_private;
6194         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6195         struct drm_i915_gem_object *obj;
6196         uint32_t addr;
6197         int ret;
6198
6199         /* if we want to turn off the cursor ignore width and height */
6200         if (!handle) {
6201                 DRM_DEBUG_KMS("cursor off\n");
6202                 addr = 0;
6203                 obj = NULL;
6204                 mutex_lock(&dev->struct_mutex);
6205                 goto finish;
6206         }
6207
6208         /* Currently we only support 64x64 cursors */
6209         if (width != 64 || height != 64) {
6210                 DRM_ERROR("we currently only support 64x64 cursors\n");
6211                 return -EINVAL;
6212         }
6213
6214         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6215         if (&obj->base == NULL)
6216                 return -ENOENT;
6217
6218         if (obj->base.size < width * height * 4) {
6219                 DRM_ERROR("buffer is to small\n");
6220                 ret = -ENOMEM;
6221                 goto fail;
6222         }
6223
6224         /* we only need to pin inside GTT if cursor is non-phy */
6225         mutex_lock(&dev->struct_mutex);
6226         if (!dev_priv->info->cursor_needs_physical) {
6227                 if (obj->tiling_mode) {
6228                         DRM_ERROR("cursor cannot be tiled\n");
6229                         ret = -EINVAL;
6230                         goto fail_locked;
6231                 }
6232
6233                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6234                 if (ret) {
6235                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6236                         goto fail_locked;
6237                 }
6238
6239                 ret = i915_gem_object_put_fence(obj);
6240                 if (ret) {
6241                         DRM_ERROR("failed to release fence for cursor");
6242                         goto fail_unpin;
6243                 }
6244
6245                 addr = obj->gtt_offset;
6246         } else {
6247                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6248                 ret = i915_gem_attach_phys_object(dev, obj,
6249                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6250                                                   align);
6251                 if (ret) {
6252                         DRM_ERROR("failed to attach phys object\n");
6253                         goto fail_locked;
6254                 }
6255                 addr = obj->phys_obj->handle->busaddr;
6256         }
6257
6258         if (IS_GEN2(dev))
6259                 I915_WRITE(CURSIZE, (height << 12) | width);
6260
6261  finish:
6262         if (intel_crtc->cursor_bo) {
6263                 if (dev_priv->info->cursor_needs_physical) {
6264                         if (intel_crtc->cursor_bo != obj)
6265                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6266                 } else
6267                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6268                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6269         }
6270
6271         mutex_unlock(&dev->struct_mutex);
6272
6273         intel_crtc->cursor_addr = addr;
6274         intel_crtc->cursor_bo = obj;
6275         intel_crtc->cursor_width = width;
6276         intel_crtc->cursor_height = height;
6277
6278         intel_crtc_update_cursor(crtc, true);
6279
6280         return 0;
6281 fail_unpin:
6282         i915_gem_object_unpin(obj);
6283 fail_locked:
6284         mutex_unlock(&dev->struct_mutex);
6285 fail:
6286         drm_gem_object_unreference_unlocked(&obj->base);
6287         return ret;
6288 }
6289
6290 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6291 {
6292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6293
6294         intel_crtc->cursor_x = x;
6295         intel_crtc->cursor_y = y;
6296
6297         intel_crtc_update_cursor(crtc, true);
6298
6299         return 0;
6300 }
6301
6302 /** Sets the color ramps on behalf of RandR */
6303 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6304                                  u16 blue, int regno)
6305 {
6306         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307
6308         intel_crtc->lut_r[regno] = red >> 8;
6309         intel_crtc->lut_g[regno] = green >> 8;
6310         intel_crtc->lut_b[regno] = blue >> 8;
6311 }
6312
6313 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6314                              u16 *blue, int regno)
6315 {
6316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6317
6318         *red = intel_crtc->lut_r[regno] << 8;
6319         *green = intel_crtc->lut_g[regno] << 8;
6320         *blue = intel_crtc->lut_b[regno] << 8;
6321 }
6322
6323 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6324                                  u16 *blue, uint32_t start, uint32_t size)
6325 {
6326         int end = (start + size > 256) ? 256 : start + size, i;
6327         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6328
6329         for (i = start; i < end; i++) {
6330                 intel_crtc->lut_r[i] = red[i] >> 8;
6331                 intel_crtc->lut_g[i] = green[i] >> 8;
6332                 intel_crtc->lut_b[i] = blue[i] >> 8;
6333         }
6334
6335         intel_crtc_load_lut(crtc);
6336 }
6337
6338 /**
6339  * Get a pipe with a simple mode set on it for doing load-based monitor
6340  * detection.
6341  *
6342  * It will be up to the load-detect code to adjust the pipe as appropriate for
6343  * its requirements.  The pipe will be connected to no other encoders.
6344  *
6345  * Currently this code will only succeed if there is a pipe with no encoders
6346  * configured for it.  In the future, it could choose to temporarily disable
6347  * some outputs to free up a pipe for its use.
6348  *
6349  * \return crtc, or NULL if no pipes are available.
6350  */
6351
6352 /* VESA 640x480x72Hz mode to set on the pipe */
6353 static struct drm_display_mode load_detect_mode = {
6354         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6355                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6356 };
6357
6358 static struct drm_framebuffer *
6359 intel_framebuffer_create(struct drm_device *dev,
6360                          struct drm_mode_fb_cmd2 *mode_cmd,
6361                          struct drm_i915_gem_object *obj)
6362 {
6363         struct intel_framebuffer *intel_fb;
6364         int ret;
6365
6366         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6367         if (!intel_fb) {
6368                 drm_gem_object_unreference_unlocked(&obj->base);
6369                 return ERR_PTR(-ENOMEM);
6370         }
6371
6372         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6373         if (ret) {
6374                 drm_gem_object_unreference_unlocked(&obj->base);
6375                 kfree(intel_fb);
6376                 return ERR_PTR(ret);
6377         }
6378
6379         return &intel_fb->base;
6380 }
6381
6382 static u32
6383 intel_framebuffer_pitch_for_width(int width, int bpp)
6384 {
6385         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6386         return ALIGN(pitch, 64);
6387 }
6388
6389 static u32
6390 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6391 {
6392         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6393         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6394 }
6395
6396 static struct drm_framebuffer *
6397 intel_framebuffer_create_for_mode(struct drm_device *dev,
6398                                   struct drm_display_mode *mode,
6399                                   int depth, int bpp)
6400 {
6401         struct drm_i915_gem_object *obj;
6402         struct drm_mode_fb_cmd2 mode_cmd;
6403
6404         obj = i915_gem_alloc_object(dev,
6405                                     intel_framebuffer_size_for_mode(mode, bpp));
6406         if (obj == NULL)
6407                 return ERR_PTR(-ENOMEM);
6408
6409         mode_cmd.width = mode->hdisplay;
6410         mode_cmd.height = mode->vdisplay;
6411         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6412                                                                 bpp);
6413         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6414
6415         return intel_framebuffer_create(dev, &mode_cmd, obj);
6416 }
6417
6418 static struct drm_framebuffer *
6419 mode_fits_in_fbdev(struct drm_device *dev,
6420                    struct drm_display_mode *mode)
6421 {
6422         struct drm_i915_private *dev_priv = dev->dev_private;
6423         struct drm_i915_gem_object *obj;
6424         struct drm_framebuffer *fb;
6425
6426         if (dev_priv->fbdev == NULL)
6427                 return NULL;
6428
6429         obj = dev_priv->fbdev->ifb.obj;
6430         if (obj == NULL)
6431                 return NULL;
6432
6433         fb = &dev_priv->fbdev->ifb.base;
6434         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6435                                                                fb->bits_per_pixel))
6436                 return NULL;
6437
6438         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6439                 return NULL;
6440
6441         return fb;
6442 }
6443
6444 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6445                                 struct drm_display_mode *mode,
6446                                 struct intel_load_detect_pipe *old)
6447 {
6448         struct intel_crtc *intel_crtc;
6449         struct intel_encoder *intel_encoder =
6450                 intel_attached_encoder(connector);
6451         struct drm_crtc *possible_crtc;
6452         struct drm_encoder *encoder = &intel_encoder->base;
6453         struct drm_crtc *crtc = NULL;
6454         struct drm_device *dev = encoder->dev;
6455         struct drm_framebuffer *fb;
6456         int i = -1;
6457
6458         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6459                       connector->base.id, drm_get_connector_name(connector),
6460                       encoder->base.id, drm_get_encoder_name(encoder));
6461
6462         /*
6463          * Algorithm gets a little messy:
6464          *
6465          *   - if the connector already has an assigned crtc, use it (but make
6466          *     sure it's on first)
6467          *
6468          *   - try to find the first unused crtc that can drive this connector,
6469          *     and use that if we find one
6470          */
6471
6472         /* See if we already have a CRTC for this connector */
6473         if (encoder->crtc) {
6474                 crtc = encoder->crtc;
6475
6476                 old->dpms_mode = connector->dpms;
6477                 old->load_detect_temp = false;
6478
6479                 /* Make sure the crtc and connector are running */
6480                 if (connector->dpms != DRM_MODE_DPMS_ON)
6481                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6482
6483                 return true;
6484         }
6485
6486         /* Find an unused one (if possible) */
6487         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6488                 i++;
6489                 if (!(encoder->possible_crtcs & (1 << i)))
6490                         continue;
6491                 if (!possible_crtc->enabled) {
6492                         crtc = possible_crtc;
6493                         break;
6494                 }
6495         }
6496
6497         /*
6498          * If we didn't find an unused CRTC, don't use any.
6499          */
6500         if (!crtc) {
6501                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6502                 return false;
6503         }
6504
6505         intel_encoder->new_crtc = to_intel_crtc(crtc);
6506         to_intel_connector(connector)->new_encoder = intel_encoder;
6507
6508         intel_crtc = to_intel_crtc(crtc);
6509         old->dpms_mode = connector->dpms;
6510         old->load_detect_temp = true;
6511         old->release_fb = NULL;
6512
6513         if (!mode)
6514                 mode = &load_detect_mode;
6515
6516         /* We need a framebuffer large enough to accommodate all accesses
6517          * that the plane may generate whilst we perform load detection.
6518          * We can not rely on the fbcon either being present (we get called
6519          * during its initialisation to detect all boot displays, or it may
6520          * not even exist) or that it is large enough to satisfy the
6521          * requested mode.
6522          */
6523         fb = mode_fits_in_fbdev(dev, mode);
6524         if (fb == NULL) {
6525                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6526                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6527                 old->release_fb = fb;
6528         } else
6529                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6530         if (IS_ERR(fb)) {
6531                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6532                 goto fail;
6533         }
6534
6535         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6536                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6537                 if (old->release_fb)
6538                         old->release_fb->funcs->destroy(old->release_fb);
6539                 goto fail;
6540         }
6541
6542         /* let the connector get through one full cycle before testing */
6543         intel_wait_for_vblank(dev, intel_crtc->pipe);
6544
6545         return true;
6546 fail:
6547         connector->encoder = NULL;
6548         encoder->crtc = NULL;
6549         return false;
6550 }
6551
6552 void intel_release_load_detect_pipe(struct drm_connector *connector,
6553                                     struct intel_load_detect_pipe *old)
6554 {
6555         struct intel_encoder *intel_encoder =
6556                 intel_attached_encoder(connector);
6557         struct drm_encoder *encoder = &intel_encoder->base;
6558
6559         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6560                       connector->base.id, drm_get_connector_name(connector),
6561                       encoder->base.id, drm_get_encoder_name(encoder));
6562
6563         if (old->load_detect_temp) {
6564                 struct drm_crtc *crtc = encoder->crtc;
6565
6566                 to_intel_connector(connector)->new_encoder = NULL;
6567                 intel_encoder->new_crtc = NULL;
6568                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6569
6570                 if (old->release_fb)
6571                         old->release_fb->funcs->destroy(old->release_fb);
6572
6573                 return;
6574         }
6575
6576         /* Switch crtc and encoder back off if necessary */
6577         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6578                 connector->funcs->dpms(connector, old->dpms_mode);
6579 }
6580
6581 /* Returns the clock of the currently programmed mode of the given pipe. */
6582 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6583 {
6584         struct drm_i915_private *dev_priv = dev->dev_private;
6585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6586         int pipe = intel_crtc->pipe;
6587         u32 dpll = I915_READ(DPLL(pipe));
6588         u32 fp;
6589         intel_clock_t clock;
6590
6591         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6592                 fp = I915_READ(FP0(pipe));
6593         else
6594                 fp = I915_READ(FP1(pipe));
6595
6596         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6597         if (IS_PINEVIEW(dev)) {
6598                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6599                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6600         } else {
6601                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6602                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6603         }
6604
6605         if (!IS_GEN2(dev)) {
6606                 if (IS_PINEVIEW(dev))
6607                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6608                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6609                 else
6610                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6611                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6612
6613                 switch (dpll & DPLL_MODE_MASK) {
6614                 case DPLLB_MODE_DAC_SERIAL:
6615                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6616                                 5 : 10;
6617                         break;
6618                 case DPLLB_MODE_LVDS:
6619                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6620                                 7 : 14;
6621                         break;
6622                 default:
6623                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6624                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6625                         return 0;
6626                 }
6627
6628                 /* XXX: Handle the 100Mhz refclk */
6629                 intel_clock(dev, 96000, &clock);
6630         } else {
6631                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6632
6633                 if (is_lvds) {
6634                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6635                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6636                         clock.p2 = 14;
6637
6638                         if ((dpll & PLL_REF_INPUT_MASK) ==
6639                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6640                                 /* XXX: might not be 66MHz */
6641                                 intel_clock(dev, 66000, &clock);
6642                         } else
6643                                 intel_clock(dev, 48000, &clock);
6644                 } else {
6645                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6646                                 clock.p1 = 2;
6647                         else {
6648                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6649                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6650                         }
6651                         if (dpll & PLL_P2_DIVIDE_BY_4)
6652                                 clock.p2 = 4;
6653                         else
6654                                 clock.p2 = 2;
6655
6656                         intel_clock(dev, 48000, &clock);
6657                 }
6658         }
6659
6660         /* XXX: It would be nice to validate the clocks, but we can't reuse
6661          * i830PllIsValid() because it relies on the xf86_config connector
6662          * configuration being accurate, which it isn't necessarily.
6663          */
6664
6665         return clock.dot;
6666 }
6667
6668 /** Returns the currently programmed mode of the given pipe. */
6669 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6670                                              struct drm_crtc *crtc)
6671 {
6672         struct drm_i915_private *dev_priv = dev->dev_private;
6673         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6674         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6675         struct drm_display_mode *mode;
6676         int htot = I915_READ(HTOTAL(cpu_transcoder));
6677         int hsync = I915_READ(HSYNC(cpu_transcoder));
6678         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6679         int vsync = I915_READ(VSYNC(cpu_transcoder));
6680
6681         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6682         if (!mode)
6683                 return NULL;
6684
6685         mode->clock = intel_crtc_clock_get(dev, crtc);
6686         mode->hdisplay = (htot & 0xffff) + 1;
6687         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6688         mode->hsync_start = (hsync & 0xffff) + 1;
6689         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6690         mode->vdisplay = (vtot & 0xffff) + 1;
6691         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6692         mode->vsync_start = (vsync & 0xffff) + 1;
6693         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6694
6695         drm_mode_set_name(mode);
6696
6697         return mode;
6698 }
6699
6700 static void intel_increase_pllclock(struct drm_crtc *crtc)
6701 {
6702         struct drm_device *dev = crtc->dev;
6703         drm_i915_private_t *dev_priv = dev->dev_private;
6704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6705         int pipe = intel_crtc->pipe;
6706         int dpll_reg = DPLL(pipe);
6707         int dpll;
6708
6709         if (HAS_PCH_SPLIT(dev))
6710                 return;
6711
6712         if (!dev_priv->lvds_downclock_avail)
6713                 return;
6714
6715         dpll = I915_READ(dpll_reg);
6716         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6717                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6718
6719                 assert_panel_unlocked(dev_priv, pipe);
6720
6721                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6722                 I915_WRITE(dpll_reg, dpll);
6723                 intel_wait_for_vblank(dev, pipe);
6724
6725                 dpll = I915_READ(dpll_reg);
6726                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6727                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6728         }
6729 }
6730
6731 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6732 {
6733         struct drm_device *dev = crtc->dev;
6734         drm_i915_private_t *dev_priv = dev->dev_private;
6735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6736
6737         if (HAS_PCH_SPLIT(dev))
6738                 return;
6739
6740         if (!dev_priv->lvds_downclock_avail)
6741                 return;
6742
6743         /*
6744          * Since this is called by a timer, we should never get here in
6745          * the manual case.
6746          */
6747         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6748                 int pipe = intel_crtc->pipe;
6749                 int dpll_reg = DPLL(pipe);
6750                 int dpll;
6751
6752                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6753
6754                 assert_panel_unlocked(dev_priv, pipe);
6755
6756                 dpll = I915_READ(dpll_reg);
6757                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6758                 I915_WRITE(dpll_reg, dpll);
6759                 intel_wait_for_vblank(dev, pipe);
6760                 dpll = I915_READ(dpll_reg);
6761                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6762                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6763         }
6764
6765 }
6766
6767 void intel_mark_busy(struct drm_device *dev)
6768 {
6769         i915_update_gfx_val(dev->dev_private);
6770 }
6771
6772 void intel_mark_idle(struct drm_device *dev)
6773 {
6774 }
6775
6776 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6777 {
6778         struct drm_device *dev = obj->base.dev;
6779         struct drm_crtc *crtc;
6780
6781         if (!i915_powersave)
6782                 return;
6783
6784         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6785                 if (!crtc->fb)
6786                         continue;
6787
6788                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6789                         intel_increase_pllclock(crtc);
6790         }
6791 }
6792
6793 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6794 {
6795         struct drm_device *dev = obj->base.dev;
6796         struct drm_crtc *crtc;
6797
6798         if (!i915_powersave)
6799                 return;
6800
6801         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6802                 if (!crtc->fb)
6803                         continue;
6804
6805                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6806                         intel_decrease_pllclock(crtc);
6807         }
6808 }
6809
6810 static void intel_crtc_destroy(struct drm_crtc *crtc)
6811 {
6812         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6813         struct drm_device *dev = crtc->dev;
6814         struct intel_unpin_work *work;
6815         unsigned long flags;
6816
6817         spin_lock_irqsave(&dev->event_lock, flags);
6818         work = intel_crtc->unpin_work;
6819         intel_crtc->unpin_work = NULL;
6820         spin_unlock_irqrestore(&dev->event_lock, flags);
6821
6822         if (work) {
6823                 cancel_work_sync(&work->work);
6824                 kfree(work);
6825         }
6826
6827         drm_crtc_cleanup(crtc);
6828
6829         kfree(intel_crtc);
6830 }
6831
6832 static void intel_unpin_work_fn(struct work_struct *__work)
6833 {
6834         struct intel_unpin_work *work =
6835                 container_of(__work, struct intel_unpin_work, work);
6836
6837         mutex_lock(&work->dev->struct_mutex);
6838         intel_unpin_fb_obj(work->old_fb_obj);
6839         drm_gem_object_unreference(&work->pending_flip_obj->base);
6840         drm_gem_object_unreference(&work->old_fb_obj->base);
6841
6842         intel_update_fbc(work->dev);
6843         mutex_unlock(&work->dev->struct_mutex);
6844         kfree(work);
6845 }
6846
6847 static void do_intel_finish_page_flip(struct drm_device *dev,
6848                                       struct drm_crtc *crtc)
6849 {
6850         drm_i915_private_t *dev_priv = dev->dev_private;
6851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6852         struct intel_unpin_work *work;
6853         struct drm_i915_gem_object *obj;
6854         struct drm_pending_vblank_event *e;
6855         struct timeval tvbl;
6856         unsigned long flags;
6857
6858         /* Ignore early vblank irqs */
6859         if (intel_crtc == NULL)
6860                 return;
6861
6862         spin_lock_irqsave(&dev->event_lock, flags);
6863         work = intel_crtc->unpin_work;
6864         if (work == NULL || !work->pending) {
6865                 spin_unlock_irqrestore(&dev->event_lock, flags);
6866                 return;
6867         }
6868
6869         intel_crtc->unpin_work = NULL;
6870
6871         if (work->event) {
6872                 e = work->event;
6873                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6874
6875                 e->event.tv_sec = tvbl.tv_sec;
6876                 e->event.tv_usec = tvbl.tv_usec;
6877
6878                 list_add_tail(&e->base.link,
6879                               &e->base.file_priv->event_list);
6880                 wake_up_interruptible(&e->base.file_priv->event_wait);
6881         }
6882
6883         drm_vblank_put(dev, intel_crtc->pipe);
6884
6885         spin_unlock_irqrestore(&dev->event_lock, flags);
6886
6887         obj = work->old_fb_obj;
6888
6889         atomic_clear_mask(1 << intel_crtc->plane,
6890                           &obj->pending_flip.counter);
6891
6892         wake_up(&dev_priv->pending_flip_queue);
6893         schedule_work(&work->work);
6894
6895         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6896 }
6897
6898 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6899 {
6900         drm_i915_private_t *dev_priv = dev->dev_private;
6901         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6902
6903         do_intel_finish_page_flip(dev, crtc);
6904 }
6905
6906 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6907 {
6908         drm_i915_private_t *dev_priv = dev->dev_private;
6909         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6910
6911         do_intel_finish_page_flip(dev, crtc);
6912 }
6913
6914 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6915 {
6916         drm_i915_private_t *dev_priv = dev->dev_private;
6917         struct intel_crtc *intel_crtc =
6918                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6919         unsigned long flags;
6920
6921         spin_lock_irqsave(&dev->event_lock, flags);
6922         if (intel_crtc->unpin_work) {
6923                 if ((++intel_crtc->unpin_work->pending) > 1)
6924                         DRM_ERROR("Prepared flip multiple times\n");
6925         } else {
6926                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6927         }
6928         spin_unlock_irqrestore(&dev->event_lock, flags);
6929 }
6930
6931 static int intel_gen2_queue_flip(struct drm_device *dev,
6932                                  struct drm_crtc *crtc,
6933                                  struct drm_framebuffer *fb,
6934                                  struct drm_i915_gem_object *obj)
6935 {
6936         struct drm_i915_private *dev_priv = dev->dev_private;
6937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6938         u32 flip_mask;
6939         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6940         int ret;
6941
6942         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6943         if (ret)
6944                 goto err;
6945
6946         ret = intel_ring_begin(ring, 6);
6947         if (ret)
6948                 goto err_unpin;
6949
6950         /* Can't queue multiple flips, so wait for the previous
6951          * one to finish before executing the next.
6952          */
6953         if (intel_crtc->plane)
6954                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6955         else
6956                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6957         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6958         intel_ring_emit(ring, MI_NOOP);
6959         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6960                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6961         intel_ring_emit(ring, fb->pitches[0]);
6962         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6963         intel_ring_emit(ring, 0); /* aux display base address, unused */
6964         intel_ring_advance(ring);
6965         return 0;
6966
6967 err_unpin:
6968         intel_unpin_fb_obj(obj);
6969 err:
6970         return ret;
6971 }
6972
6973 static int intel_gen3_queue_flip(struct drm_device *dev,
6974                                  struct drm_crtc *crtc,
6975                                  struct drm_framebuffer *fb,
6976                                  struct drm_i915_gem_object *obj)
6977 {
6978         struct drm_i915_private *dev_priv = dev->dev_private;
6979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6980         u32 flip_mask;
6981         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6982         int ret;
6983
6984         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6985         if (ret)
6986                 goto err;
6987
6988         ret = intel_ring_begin(ring, 6);
6989         if (ret)
6990                 goto err_unpin;
6991
6992         if (intel_crtc->plane)
6993                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6994         else
6995                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6996         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6997         intel_ring_emit(ring, MI_NOOP);
6998         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6999                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7000         intel_ring_emit(ring, fb->pitches[0]);
7001         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7002         intel_ring_emit(ring, MI_NOOP);
7003
7004         intel_ring_advance(ring);
7005         return 0;
7006
7007 err_unpin:
7008         intel_unpin_fb_obj(obj);
7009 err:
7010         return ret;
7011 }
7012
7013 static int intel_gen4_queue_flip(struct drm_device *dev,
7014                                  struct drm_crtc *crtc,
7015                                  struct drm_framebuffer *fb,
7016                                  struct drm_i915_gem_object *obj)
7017 {
7018         struct drm_i915_private *dev_priv = dev->dev_private;
7019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7020         uint32_t pf, pipesrc;
7021         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7022         int ret;
7023
7024         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7025         if (ret)
7026                 goto err;
7027
7028         ret = intel_ring_begin(ring, 4);
7029         if (ret)
7030                 goto err_unpin;
7031
7032         /* i965+ uses the linear or tiled offsets from the
7033          * Display Registers (which do not change across a page-flip)
7034          * so we need only reprogram the base address.
7035          */
7036         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7037                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7038         intel_ring_emit(ring, fb->pitches[0]);
7039         intel_ring_emit(ring,
7040                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7041                         obj->tiling_mode);
7042
7043         /* XXX Enabling the panel-fitter across page-flip is so far
7044          * untested on non-native modes, so ignore it for now.
7045          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7046          */
7047         pf = 0;
7048         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7049         intel_ring_emit(ring, pf | pipesrc);
7050         intel_ring_advance(ring);
7051         return 0;
7052
7053 err_unpin:
7054         intel_unpin_fb_obj(obj);
7055 err:
7056         return ret;
7057 }
7058
7059 static int intel_gen6_queue_flip(struct drm_device *dev,
7060                                  struct drm_crtc *crtc,
7061                                  struct drm_framebuffer *fb,
7062                                  struct drm_i915_gem_object *obj)
7063 {
7064         struct drm_i915_private *dev_priv = dev->dev_private;
7065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7066         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7067         uint32_t pf, pipesrc;
7068         int ret;
7069
7070         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7071         if (ret)
7072                 goto err;
7073
7074         ret = intel_ring_begin(ring, 4);
7075         if (ret)
7076                 goto err_unpin;
7077
7078         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7079                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7080         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7081         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7082
7083         /* Contrary to the suggestions in the documentation,
7084          * "Enable Panel Fitter" does not seem to be required when page
7085          * flipping with a non-native mode, and worse causes a normal
7086          * modeset to fail.
7087          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7088          */
7089         pf = 0;
7090         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7091         intel_ring_emit(ring, pf | pipesrc);
7092         intel_ring_advance(ring);
7093         return 0;
7094
7095 err_unpin:
7096         intel_unpin_fb_obj(obj);
7097 err:
7098         return ret;
7099 }
7100
7101 /*
7102  * On gen7 we currently use the blit ring because (in early silicon at least)
7103  * the render ring doesn't give us interrpts for page flip completion, which
7104  * means clients will hang after the first flip is queued.  Fortunately the
7105  * blit ring generates interrupts properly, so use it instead.
7106  */
7107 static int intel_gen7_queue_flip(struct drm_device *dev,
7108                                  struct drm_crtc *crtc,
7109                                  struct drm_framebuffer *fb,
7110                                  struct drm_i915_gem_object *obj)
7111 {
7112         struct drm_i915_private *dev_priv = dev->dev_private;
7113         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7114         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7115         uint32_t plane_bit = 0;
7116         int ret;
7117
7118         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7119         if (ret)
7120                 goto err;
7121
7122         switch(intel_crtc->plane) {
7123         case PLANE_A:
7124                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7125                 break;
7126         case PLANE_B:
7127                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7128                 break;
7129         case PLANE_C:
7130                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7131                 break;
7132         default:
7133                 WARN_ONCE(1, "unknown plane in flip command\n");
7134                 ret = -ENODEV;
7135                 goto err_unpin;
7136         }
7137
7138         ret = intel_ring_begin(ring, 4);
7139         if (ret)
7140                 goto err_unpin;
7141
7142         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7143         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7144         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7145         intel_ring_emit(ring, (MI_NOOP));
7146         intel_ring_advance(ring);
7147         return 0;
7148
7149 err_unpin:
7150         intel_unpin_fb_obj(obj);
7151 err:
7152         return ret;
7153 }
7154
7155 static int intel_default_queue_flip(struct drm_device *dev,
7156                                     struct drm_crtc *crtc,
7157                                     struct drm_framebuffer *fb,
7158                                     struct drm_i915_gem_object *obj)
7159 {
7160         return -ENODEV;
7161 }
7162
7163 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7164                                 struct drm_framebuffer *fb,
7165                                 struct drm_pending_vblank_event *event)
7166 {
7167         struct drm_device *dev = crtc->dev;
7168         struct drm_i915_private *dev_priv = dev->dev_private;
7169         struct intel_framebuffer *intel_fb;
7170         struct drm_i915_gem_object *obj;
7171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7172         struct intel_unpin_work *work;
7173         unsigned long flags;
7174         int ret;
7175
7176         /* Can't change pixel format via MI display flips. */
7177         if (fb->pixel_format != crtc->fb->pixel_format)
7178                 return -EINVAL;
7179
7180         /*
7181          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7182          * Note that pitch changes could also affect these register.
7183          */
7184         if (INTEL_INFO(dev)->gen > 3 &&
7185             (fb->offsets[0] != crtc->fb->offsets[0] ||
7186              fb->pitches[0] != crtc->fb->pitches[0]))
7187                 return -EINVAL;
7188
7189         work = kzalloc(sizeof *work, GFP_KERNEL);
7190         if (work == NULL)
7191                 return -ENOMEM;
7192
7193         work->event = event;
7194         work->dev = crtc->dev;
7195         intel_fb = to_intel_framebuffer(crtc->fb);
7196         work->old_fb_obj = intel_fb->obj;
7197         INIT_WORK(&work->work, intel_unpin_work_fn);
7198
7199         ret = drm_vblank_get(dev, intel_crtc->pipe);
7200         if (ret)
7201                 goto free_work;
7202
7203         /* We borrow the event spin lock for protecting unpin_work */
7204         spin_lock_irqsave(&dev->event_lock, flags);
7205         if (intel_crtc->unpin_work) {
7206                 spin_unlock_irqrestore(&dev->event_lock, flags);
7207                 kfree(work);
7208                 drm_vblank_put(dev, intel_crtc->pipe);
7209
7210                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7211                 return -EBUSY;
7212         }
7213         intel_crtc->unpin_work = work;
7214         spin_unlock_irqrestore(&dev->event_lock, flags);
7215
7216         intel_fb = to_intel_framebuffer(fb);
7217         obj = intel_fb->obj;
7218
7219         ret = i915_mutex_lock_interruptible(dev);
7220         if (ret)
7221                 goto cleanup;
7222
7223         /* Reference the objects for the scheduled work. */
7224         drm_gem_object_reference(&work->old_fb_obj->base);
7225         drm_gem_object_reference(&obj->base);
7226
7227         crtc->fb = fb;
7228
7229         work->pending_flip_obj = obj;
7230
7231         work->enable_stall_check = true;
7232
7233         /* Block clients from rendering to the new back buffer until
7234          * the flip occurs and the object is no longer visible.
7235          */
7236         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7237
7238         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7239         if (ret)
7240                 goto cleanup_pending;
7241
7242         intel_disable_fbc(dev);
7243         intel_mark_fb_busy(obj);
7244         mutex_unlock(&dev->struct_mutex);
7245
7246         trace_i915_flip_request(intel_crtc->plane, obj);
7247
7248         return 0;
7249
7250 cleanup_pending:
7251         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7252         drm_gem_object_unreference(&work->old_fb_obj->base);
7253         drm_gem_object_unreference(&obj->base);
7254         mutex_unlock(&dev->struct_mutex);
7255
7256 cleanup:
7257         spin_lock_irqsave(&dev->event_lock, flags);
7258         intel_crtc->unpin_work = NULL;
7259         spin_unlock_irqrestore(&dev->event_lock, flags);
7260
7261         drm_vblank_put(dev, intel_crtc->pipe);
7262 free_work:
7263         kfree(work);
7264
7265         return ret;
7266 }
7267
7268 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7269         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7270         .load_lut = intel_crtc_load_lut,
7271         .disable = intel_crtc_noop,
7272 };
7273
7274 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7275 {
7276         struct intel_encoder *other_encoder;
7277         struct drm_crtc *crtc = &encoder->new_crtc->base;
7278
7279         if (WARN_ON(!crtc))
7280                 return false;
7281
7282         list_for_each_entry(other_encoder,
7283                             &crtc->dev->mode_config.encoder_list,
7284                             base.head) {
7285
7286                 if (&other_encoder->new_crtc->base != crtc ||
7287                     encoder == other_encoder)
7288                         continue;
7289                 else
7290                         return true;
7291         }
7292
7293         return false;
7294 }
7295
7296 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7297                                   struct drm_crtc *crtc)
7298 {
7299         struct drm_device *dev;
7300         struct drm_crtc *tmp;
7301         int crtc_mask = 1;
7302
7303         WARN(!crtc, "checking null crtc?\n");
7304
7305         dev = crtc->dev;
7306
7307         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7308                 if (tmp == crtc)
7309                         break;
7310                 crtc_mask <<= 1;
7311         }
7312
7313         if (encoder->possible_crtcs & crtc_mask)
7314                 return true;
7315         return false;
7316 }
7317
7318 /**
7319  * intel_modeset_update_staged_output_state
7320  *
7321  * Updates the staged output configuration state, e.g. after we've read out the
7322  * current hw state.
7323  */
7324 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7325 {
7326         struct intel_encoder *encoder;
7327         struct intel_connector *connector;
7328
7329         list_for_each_entry(connector, &dev->mode_config.connector_list,
7330                             base.head) {
7331                 connector->new_encoder =
7332                         to_intel_encoder(connector->base.encoder);
7333         }
7334
7335         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7336                             base.head) {
7337                 encoder->new_crtc =
7338                         to_intel_crtc(encoder->base.crtc);
7339         }
7340 }
7341
7342 /**
7343  * intel_modeset_commit_output_state
7344  *
7345  * This function copies the stage display pipe configuration to the real one.
7346  */
7347 static void intel_modeset_commit_output_state(struct drm_device *dev)
7348 {
7349         struct intel_encoder *encoder;
7350         struct intel_connector *connector;
7351
7352         list_for_each_entry(connector, &dev->mode_config.connector_list,
7353                             base.head) {
7354                 connector->base.encoder = &connector->new_encoder->base;
7355         }
7356
7357         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7358                             base.head) {
7359                 encoder->base.crtc = &encoder->new_crtc->base;
7360         }
7361 }
7362
7363 static struct drm_display_mode *
7364 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7365                             struct drm_display_mode *mode)
7366 {
7367         struct drm_device *dev = crtc->dev;
7368         struct drm_display_mode *adjusted_mode;
7369         struct drm_encoder_helper_funcs *encoder_funcs;
7370         struct intel_encoder *encoder;
7371
7372         adjusted_mode = drm_mode_duplicate(dev, mode);
7373         if (!adjusted_mode)
7374                 return ERR_PTR(-ENOMEM);
7375
7376         /* Pass our mode to the connectors and the CRTC to give them a chance to
7377          * adjust it according to limitations or connector properties, and also
7378          * a chance to reject the mode entirely.
7379          */
7380         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7381                             base.head) {
7382
7383                 if (&encoder->new_crtc->base != crtc)
7384                         continue;
7385                 encoder_funcs = encoder->base.helper_private;
7386                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7387                                                 adjusted_mode))) {
7388                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7389                         goto fail;
7390                 }
7391         }
7392
7393         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7394                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7395                 goto fail;
7396         }
7397         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7398
7399         return adjusted_mode;
7400 fail:
7401         drm_mode_destroy(dev, adjusted_mode);
7402         return ERR_PTR(-EINVAL);
7403 }
7404
7405 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7406  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7407 static void
7408 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7409                              unsigned *prepare_pipes, unsigned *disable_pipes)
7410 {
7411         struct intel_crtc *intel_crtc;
7412         struct drm_device *dev = crtc->dev;
7413         struct intel_encoder *encoder;
7414         struct intel_connector *connector;
7415         struct drm_crtc *tmp_crtc;
7416
7417         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7418
7419         /* Check which crtcs have changed outputs connected to them, these need
7420          * to be part of the prepare_pipes mask. We don't (yet) support global
7421          * modeset across multiple crtcs, so modeset_pipes will only have one
7422          * bit set at most. */
7423         list_for_each_entry(connector, &dev->mode_config.connector_list,
7424                             base.head) {
7425                 if (connector->base.encoder == &connector->new_encoder->base)
7426                         continue;
7427
7428                 if (connector->base.encoder) {
7429                         tmp_crtc = connector->base.encoder->crtc;
7430
7431                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7432                 }
7433
7434                 if (connector->new_encoder)
7435                         *prepare_pipes |=
7436                                 1 << connector->new_encoder->new_crtc->pipe;
7437         }
7438
7439         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7440                             base.head) {
7441                 if (encoder->base.crtc == &encoder->new_crtc->base)
7442                         continue;
7443
7444                 if (encoder->base.crtc) {
7445                         tmp_crtc = encoder->base.crtc;
7446
7447                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7448                 }
7449
7450                 if (encoder->new_crtc)
7451                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7452         }
7453
7454         /* Check for any pipes that will be fully disabled ... */
7455         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7456                             base.head) {
7457                 bool used = false;
7458
7459                 /* Don't try to disable disabled crtcs. */
7460                 if (!intel_crtc->base.enabled)
7461                         continue;
7462
7463                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7464                                     base.head) {
7465                         if (encoder->new_crtc == intel_crtc)
7466                                 used = true;
7467                 }
7468
7469                 if (!used)
7470                         *disable_pipes |= 1 << intel_crtc->pipe;
7471         }
7472
7473
7474         /* set_mode is also used to update properties on life display pipes. */
7475         intel_crtc = to_intel_crtc(crtc);
7476         if (crtc->enabled)
7477                 *prepare_pipes |= 1 << intel_crtc->pipe;
7478
7479         /* We only support modeset on one single crtc, hence we need to do that
7480          * only for the passed in crtc iff we change anything else than just
7481          * disable crtcs.
7482          *
7483          * This is actually not true, to be fully compatible with the old crtc
7484          * helper we automatically disable _any_ output (i.e. doesn't need to be
7485          * connected to the crtc we're modesetting on) if it's disconnected.
7486          * Which is a rather nutty api (since changed the output configuration
7487          * without userspace's explicit request can lead to confusion), but
7488          * alas. Hence we currently need to modeset on all pipes we prepare. */
7489         if (*prepare_pipes)
7490                 *modeset_pipes = *prepare_pipes;
7491
7492         /* ... and mask these out. */
7493         *modeset_pipes &= ~(*disable_pipes);
7494         *prepare_pipes &= ~(*disable_pipes);
7495 }
7496
7497 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7498 {
7499         struct drm_encoder *encoder;
7500         struct drm_device *dev = crtc->dev;
7501
7502         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7503                 if (encoder->crtc == crtc)
7504                         return true;
7505
7506         return false;
7507 }
7508
7509 static void
7510 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7511 {
7512         struct intel_encoder *intel_encoder;
7513         struct intel_crtc *intel_crtc;
7514         struct drm_connector *connector;
7515
7516         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7517                             base.head) {
7518                 if (!intel_encoder->base.crtc)
7519                         continue;
7520
7521                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7522
7523                 if (prepare_pipes & (1 << intel_crtc->pipe))
7524                         intel_encoder->connectors_active = false;
7525         }
7526
7527         intel_modeset_commit_output_state(dev);
7528
7529         /* Update computed state. */
7530         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7531                             base.head) {
7532                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7533         }
7534
7535         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7536                 if (!connector->encoder || !connector->encoder->crtc)
7537                         continue;
7538
7539                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7540
7541                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7542                         struct drm_property *dpms_property =
7543                                 dev->mode_config.dpms_property;
7544
7545                         connector->dpms = DRM_MODE_DPMS_ON;
7546                         drm_connector_property_set_value(connector,
7547                                                          dpms_property,
7548                                                          DRM_MODE_DPMS_ON);
7549
7550                         intel_encoder = to_intel_encoder(connector->encoder);
7551                         intel_encoder->connectors_active = true;
7552                 }
7553         }
7554
7555 }
7556
7557 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7558         list_for_each_entry((intel_crtc), \
7559                             &(dev)->mode_config.crtc_list, \
7560                             base.head) \
7561                 if (mask & (1 <<(intel_crtc)->pipe)) \
7562
7563 void
7564 intel_modeset_check_state(struct drm_device *dev)
7565 {
7566         struct intel_crtc *crtc;
7567         struct intel_encoder *encoder;
7568         struct intel_connector *connector;
7569
7570         list_for_each_entry(connector, &dev->mode_config.connector_list,
7571                             base.head) {
7572                 /* This also checks the encoder/connector hw state with the
7573                  * ->get_hw_state callbacks. */
7574                 intel_connector_check_state(connector);
7575
7576                 WARN(&connector->new_encoder->base != connector->base.encoder,
7577                      "connector's staged encoder doesn't match current encoder\n");
7578         }
7579
7580         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7581                             base.head) {
7582                 bool enabled = false;
7583                 bool active = false;
7584                 enum pipe pipe, tracked_pipe;
7585
7586                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7587                               encoder->base.base.id,
7588                               drm_get_encoder_name(&encoder->base));
7589
7590                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7591                      "encoder's stage crtc doesn't match current crtc\n");
7592                 WARN(encoder->connectors_active && !encoder->base.crtc,
7593                      "encoder's active_connectors set, but no crtc\n");
7594
7595                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7596                                     base.head) {
7597                         if (connector->base.encoder != &encoder->base)
7598                                 continue;
7599                         enabled = true;
7600                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7601                                 active = true;
7602                 }
7603                 WARN(!!encoder->base.crtc != enabled,
7604                      "encoder's enabled state mismatch "
7605                      "(expected %i, found %i)\n",
7606                      !!encoder->base.crtc, enabled);
7607                 WARN(active && !encoder->base.crtc,
7608                      "active encoder with no crtc\n");
7609
7610                 WARN(encoder->connectors_active != active,
7611                      "encoder's computed active state doesn't match tracked active state "
7612                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7613
7614                 active = encoder->get_hw_state(encoder, &pipe);
7615                 WARN(active != encoder->connectors_active,
7616                      "encoder's hw state doesn't match sw tracking "
7617                      "(expected %i, found %i)\n",
7618                      encoder->connectors_active, active);
7619
7620                 if (!encoder->base.crtc)
7621                         continue;
7622
7623                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7624                 WARN(active && pipe != tracked_pipe,
7625                      "active encoder's pipe doesn't match"
7626                      "(expected %i, found %i)\n",
7627                      tracked_pipe, pipe);
7628
7629         }
7630
7631         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7632                             base.head) {
7633                 bool enabled = false;
7634                 bool active = false;
7635
7636                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7637                               crtc->base.base.id);
7638
7639                 WARN(crtc->active && !crtc->base.enabled,
7640                      "active crtc, but not enabled in sw tracking\n");
7641
7642                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7643                                     base.head) {
7644                         if (encoder->base.crtc != &crtc->base)
7645                                 continue;
7646                         enabled = true;
7647                         if (encoder->connectors_active)
7648                                 active = true;
7649                 }
7650                 WARN(active != crtc->active,
7651                      "crtc's computed active state doesn't match tracked active state "
7652                      "(expected %i, found %i)\n", active, crtc->active);
7653                 WARN(enabled != crtc->base.enabled,
7654                      "crtc's computed enabled state doesn't match tracked enabled state "
7655                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7656
7657                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7658         }
7659 }
7660
7661 bool intel_set_mode(struct drm_crtc *crtc,
7662                     struct drm_display_mode *mode,
7663                     int x, int y, struct drm_framebuffer *fb)
7664 {
7665         struct drm_device *dev = crtc->dev;
7666         drm_i915_private_t *dev_priv = dev->dev_private;
7667         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7668         struct intel_crtc *intel_crtc;
7669         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7670         bool ret = true;
7671
7672         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7673                                      &prepare_pipes, &disable_pipes);
7674
7675         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7676                       modeset_pipes, prepare_pipes, disable_pipes);
7677
7678         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7679                 intel_crtc_disable(&intel_crtc->base);
7680
7681         saved_hwmode = crtc->hwmode;
7682         saved_mode = crtc->mode;
7683
7684         /* Hack: Because we don't (yet) support global modeset on multiple
7685          * crtcs, we don't keep track of the new mode for more than one crtc.
7686          * Hence simply check whether any bit is set in modeset_pipes in all the
7687          * pieces of code that are not yet converted to deal with mutliple crtcs
7688          * changing their mode at the same time. */
7689         adjusted_mode = NULL;
7690         if (modeset_pipes) {
7691                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7692                 if (IS_ERR(adjusted_mode)) {
7693                         return false;
7694                 }
7695         }
7696
7697         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7698                 if (intel_crtc->base.enabled)
7699                         dev_priv->display.crtc_disable(&intel_crtc->base);
7700         }
7701
7702         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7703          * to set it here already despite that we pass it down the callchain.
7704          */
7705         if (modeset_pipes)
7706                 crtc->mode = *mode;
7707
7708         /* Only after disabling all output pipelines that will be changed can we
7709          * update the the output configuration. */
7710         intel_modeset_update_state(dev, prepare_pipes);
7711
7712         if (dev_priv->display.modeset_global_resources)
7713                 dev_priv->display.modeset_global_resources(dev);
7714
7715         /* Set up the DPLL and any encoders state that needs to adjust or depend
7716          * on the DPLL.
7717          */
7718         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7719                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7720                                            mode, adjusted_mode,
7721                                            x, y, fb);
7722                 if (!ret)
7723                     goto done;
7724         }
7725
7726         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7727         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7728                 dev_priv->display.crtc_enable(&intel_crtc->base);
7729
7730         if (modeset_pipes) {
7731                 /* Store real post-adjustment hardware mode. */
7732                 crtc->hwmode = *adjusted_mode;
7733
7734                 /* Calculate and store various constants which
7735                  * are later needed by vblank and swap-completion
7736                  * timestamping. They are derived from true hwmode.
7737                  */
7738                 drm_calc_timestamping_constants(crtc);
7739         }
7740
7741         /* FIXME: add subpixel order */
7742 done:
7743         drm_mode_destroy(dev, adjusted_mode);
7744         if (!ret && crtc->enabled) {
7745                 crtc->hwmode = saved_hwmode;
7746                 crtc->mode = saved_mode;
7747         } else {
7748                 intel_modeset_check_state(dev);
7749         }
7750
7751         return ret;
7752 }
7753
7754 #undef for_each_intel_crtc_masked
7755
7756 static void intel_set_config_free(struct intel_set_config *config)
7757 {
7758         if (!config)
7759                 return;
7760
7761         kfree(config->save_connector_encoders);
7762         kfree(config->save_encoder_crtcs);
7763         kfree(config);
7764 }
7765
7766 static int intel_set_config_save_state(struct drm_device *dev,
7767                                        struct intel_set_config *config)
7768 {
7769         struct drm_encoder *encoder;
7770         struct drm_connector *connector;
7771         int count;
7772
7773         config->save_encoder_crtcs =
7774                 kcalloc(dev->mode_config.num_encoder,
7775                         sizeof(struct drm_crtc *), GFP_KERNEL);
7776         if (!config->save_encoder_crtcs)
7777                 return -ENOMEM;
7778
7779         config->save_connector_encoders =
7780                 kcalloc(dev->mode_config.num_connector,
7781                         sizeof(struct drm_encoder *), GFP_KERNEL);
7782         if (!config->save_connector_encoders)
7783                 return -ENOMEM;
7784
7785         /* Copy data. Note that driver private data is not affected.
7786          * Should anything bad happen only the expected state is
7787          * restored, not the drivers personal bookkeeping.
7788          */
7789         count = 0;
7790         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7791                 config->save_encoder_crtcs[count++] = encoder->crtc;
7792         }
7793
7794         count = 0;
7795         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7796                 config->save_connector_encoders[count++] = connector->encoder;
7797         }
7798
7799         return 0;
7800 }
7801
7802 static void intel_set_config_restore_state(struct drm_device *dev,
7803                                            struct intel_set_config *config)
7804 {
7805         struct intel_encoder *encoder;
7806         struct intel_connector *connector;
7807         int count;
7808
7809         count = 0;
7810         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7811                 encoder->new_crtc =
7812                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7813         }
7814
7815         count = 0;
7816         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7817                 connector->new_encoder =
7818                         to_intel_encoder(config->save_connector_encoders[count++]);
7819         }
7820 }
7821
7822 static void
7823 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7824                                       struct intel_set_config *config)
7825 {
7826
7827         /* We should be able to check here if the fb has the same properties
7828          * and then just flip_or_move it */
7829         if (set->crtc->fb != set->fb) {
7830                 /* If we have no fb then treat it as a full mode set */
7831                 if (set->crtc->fb == NULL) {
7832                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7833                         config->mode_changed = true;
7834                 } else if (set->fb == NULL) {
7835                         config->mode_changed = true;
7836                 } else if (set->fb->depth != set->crtc->fb->depth) {
7837                         config->mode_changed = true;
7838                 } else if (set->fb->bits_per_pixel !=
7839                            set->crtc->fb->bits_per_pixel) {
7840                         config->mode_changed = true;
7841                 } else
7842                         config->fb_changed = true;
7843         }
7844
7845         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7846                 config->fb_changed = true;
7847
7848         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7849                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7850                 drm_mode_debug_printmodeline(&set->crtc->mode);
7851                 drm_mode_debug_printmodeline(set->mode);
7852                 config->mode_changed = true;
7853         }
7854 }
7855
7856 static int
7857 intel_modeset_stage_output_state(struct drm_device *dev,
7858                                  struct drm_mode_set *set,
7859                                  struct intel_set_config *config)
7860 {
7861         struct drm_crtc *new_crtc;
7862         struct intel_connector *connector;
7863         struct intel_encoder *encoder;
7864         int count, ro;
7865
7866         /* The upper layers ensure that we either disabl a crtc or have a list
7867          * of connectors. For paranoia, double-check this. */
7868         WARN_ON(!set->fb && (set->num_connectors != 0));
7869         WARN_ON(set->fb && (set->num_connectors == 0));
7870
7871         count = 0;
7872         list_for_each_entry(connector, &dev->mode_config.connector_list,
7873                             base.head) {
7874                 /* Otherwise traverse passed in connector list and get encoders
7875                  * for them. */
7876                 for (ro = 0; ro < set->num_connectors; ro++) {
7877                         if (set->connectors[ro] == &connector->base) {
7878                                 connector->new_encoder = connector->encoder;
7879                                 break;
7880                         }
7881                 }
7882
7883                 /* If we disable the crtc, disable all its connectors. Also, if
7884                  * the connector is on the changing crtc but not on the new
7885                  * connector list, disable it. */
7886                 if ((!set->fb || ro == set->num_connectors) &&
7887                     connector->base.encoder &&
7888                     connector->base.encoder->crtc == set->crtc) {
7889                         connector->new_encoder = NULL;
7890
7891                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7892                                 connector->base.base.id,
7893                                 drm_get_connector_name(&connector->base));
7894                 }
7895
7896
7897                 if (&connector->new_encoder->base != connector->base.encoder) {
7898                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7899                         config->mode_changed = true;
7900                 }
7901
7902                 /* Disable all disconnected encoders. */
7903                 if (connector->base.status == connector_status_disconnected)
7904                         connector->new_encoder = NULL;
7905         }
7906         /* connector->new_encoder is now updated for all connectors. */
7907
7908         /* Update crtc of enabled connectors. */
7909         count = 0;
7910         list_for_each_entry(connector, &dev->mode_config.connector_list,
7911                             base.head) {
7912                 if (!connector->new_encoder)
7913                         continue;
7914
7915                 new_crtc = connector->new_encoder->base.crtc;
7916
7917                 for (ro = 0; ro < set->num_connectors; ro++) {
7918                         if (set->connectors[ro] == &connector->base)
7919                                 new_crtc = set->crtc;
7920                 }
7921
7922                 /* Make sure the new CRTC will work with the encoder */
7923                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7924                                            new_crtc)) {
7925                         return -EINVAL;
7926                 }
7927                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7928
7929                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7930                         connector->base.base.id,
7931                         drm_get_connector_name(&connector->base),
7932                         new_crtc->base.id);
7933         }
7934
7935         /* Check for any encoders that needs to be disabled. */
7936         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7937                             base.head) {
7938                 list_for_each_entry(connector,
7939                                     &dev->mode_config.connector_list,
7940                                     base.head) {
7941                         if (connector->new_encoder == encoder) {
7942                                 WARN_ON(!connector->new_encoder->new_crtc);
7943
7944                                 goto next_encoder;
7945                         }
7946                 }
7947                 encoder->new_crtc = NULL;
7948 next_encoder:
7949                 /* Only now check for crtc changes so we don't miss encoders
7950                  * that will be disabled. */
7951                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7952                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7953                         config->mode_changed = true;
7954                 }
7955         }
7956         /* Now we've also updated encoder->new_crtc for all encoders. */
7957
7958         return 0;
7959 }
7960
7961 static int intel_crtc_set_config(struct drm_mode_set *set)
7962 {
7963         struct drm_device *dev;
7964         struct drm_mode_set save_set;
7965         struct intel_set_config *config;
7966         int ret;
7967
7968         BUG_ON(!set);
7969         BUG_ON(!set->crtc);
7970         BUG_ON(!set->crtc->helper_private);
7971
7972         if (!set->mode)
7973                 set->fb = NULL;
7974
7975         /* The fb helper likes to play gross jokes with ->mode_set_config.
7976          * Unfortunately the crtc helper doesn't do much at all for this case,
7977          * so we have to cope with this madness until the fb helper is fixed up. */
7978         if (set->fb && set->num_connectors == 0)
7979                 return 0;
7980
7981         if (set->fb) {
7982                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7983                                 set->crtc->base.id, set->fb->base.id,
7984                                 (int)set->num_connectors, set->x, set->y);
7985         } else {
7986                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7987         }
7988
7989         dev = set->crtc->dev;
7990
7991         ret = -ENOMEM;
7992         config = kzalloc(sizeof(*config), GFP_KERNEL);
7993         if (!config)
7994                 goto out_config;
7995
7996         ret = intel_set_config_save_state(dev, config);
7997         if (ret)
7998                 goto out_config;
7999
8000         save_set.crtc = set->crtc;
8001         save_set.mode = &set->crtc->mode;
8002         save_set.x = set->crtc->x;
8003         save_set.y = set->crtc->y;
8004         save_set.fb = set->crtc->fb;
8005
8006         /* Compute whether we need a full modeset, only an fb base update or no
8007          * change at all. In the future we might also check whether only the
8008          * mode changed, e.g. for LVDS where we only change the panel fitter in
8009          * such cases. */
8010         intel_set_config_compute_mode_changes(set, config);
8011
8012         ret = intel_modeset_stage_output_state(dev, set, config);
8013         if (ret)
8014                 goto fail;
8015
8016         if (config->mode_changed) {
8017                 if (set->mode) {
8018                         DRM_DEBUG_KMS("attempting to set mode from"
8019                                         " userspace\n");
8020                         drm_mode_debug_printmodeline(set->mode);
8021                 }
8022
8023                 if (!intel_set_mode(set->crtc, set->mode,
8024                                     set->x, set->y, set->fb)) {
8025                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8026                                   set->crtc->base.id);
8027                         ret = -EINVAL;
8028                         goto fail;
8029                 }
8030         } else if (config->fb_changed) {
8031                 ret = intel_pipe_set_base(set->crtc,
8032                                           set->x, set->y, set->fb);
8033         }
8034
8035         intel_set_config_free(config);
8036
8037         return 0;
8038
8039 fail:
8040         intel_set_config_restore_state(dev, config);
8041
8042         /* Try to restore the config */
8043         if (config->mode_changed &&
8044             !intel_set_mode(save_set.crtc, save_set.mode,
8045                             save_set.x, save_set.y, save_set.fb))
8046                 DRM_ERROR("failed to restore config after modeset failure\n");
8047
8048 out_config:
8049         intel_set_config_free(config);
8050         return ret;
8051 }
8052
8053 static const struct drm_crtc_funcs intel_crtc_funcs = {
8054         .cursor_set = intel_crtc_cursor_set,
8055         .cursor_move = intel_crtc_cursor_move,
8056         .gamma_set = intel_crtc_gamma_set,
8057         .set_config = intel_crtc_set_config,
8058         .destroy = intel_crtc_destroy,
8059         .page_flip = intel_crtc_page_flip,
8060 };
8061
8062 static void intel_cpu_pll_init(struct drm_device *dev)
8063 {
8064         if (IS_HASWELL(dev))
8065                 intel_ddi_pll_init(dev);
8066 }
8067
8068 static void intel_pch_pll_init(struct drm_device *dev)
8069 {
8070         drm_i915_private_t *dev_priv = dev->dev_private;
8071         int i;
8072
8073         if (dev_priv->num_pch_pll == 0) {
8074                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8075                 return;
8076         }
8077
8078         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8079                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8080                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8081                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8082         }
8083 }
8084
8085 static void intel_crtc_init(struct drm_device *dev, int pipe)
8086 {
8087         drm_i915_private_t *dev_priv = dev->dev_private;
8088         struct intel_crtc *intel_crtc;
8089         int i;
8090
8091         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8092         if (intel_crtc == NULL)
8093                 return;
8094
8095         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8096
8097         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8098         for (i = 0; i < 256; i++) {
8099                 intel_crtc->lut_r[i] = i;
8100                 intel_crtc->lut_g[i] = i;
8101                 intel_crtc->lut_b[i] = i;
8102         }
8103
8104         /* Swap pipes & planes for FBC on pre-965 */
8105         intel_crtc->pipe = pipe;
8106         intel_crtc->plane = pipe;
8107         intel_crtc->cpu_transcoder = pipe;
8108         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8109                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8110                 intel_crtc->plane = !pipe;
8111         }
8112
8113         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8114                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8115         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8116         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8117
8118         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8119
8120         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8121 }
8122
8123 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8124                                 struct drm_file *file)
8125 {
8126         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8127         struct drm_mode_object *drmmode_obj;
8128         struct intel_crtc *crtc;
8129
8130         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8131                 return -ENODEV;
8132
8133         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8134                         DRM_MODE_OBJECT_CRTC);
8135
8136         if (!drmmode_obj) {
8137                 DRM_ERROR("no such CRTC id\n");
8138                 return -EINVAL;
8139         }
8140
8141         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8142         pipe_from_crtc_id->pipe = crtc->pipe;
8143
8144         return 0;
8145 }
8146
8147 static int intel_encoder_clones(struct intel_encoder *encoder)
8148 {
8149         struct drm_device *dev = encoder->base.dev;
8150         struct intel_encoder *source_encoder;
8151         int index_mask = 0;
8152         int entry = 0;
8153
8154         list_for_each_entry(source_encoder,
8155                             &dev->mode_config.encoder_list, base.head) {
8156
8157                 if (encoder == source_encoder)
8158                         index_mask |= (1 << entry);
8159
8160                 /* Intel hw has only one MUX where enocoders could be cloned. */
8161                 if (encoder->cloneable && source_encoder->cloneable)
8162                         index_mask |= (1 << entry);
8163
8164                 entry++;
8165         }
8166
8167         return index_mask;
8168 }
8169
8170 static bool has_edp_a(struct drm_device *dev)
8171 {
8172         struct drm_i915_private *dev_priv = dev->dev_private;
8173
8174         if (!IS_MOBILE(dev))
8175                 return false;
8176
8177         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8178                 return false;
8179
8180         if (IS_GEN5(dev) &&
8181             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8182                 return false;
8183
8184         return true;
8185 }
8186
8187 static void intel_setup_outputs(struct drm_device *dev)
8188 {
8189         struct drm_i915_private *dev_priv = dev->dev_private;
8190         struct intel_encoder *encoder;
8191         bool dpd_is_edp = false;
8192         bool has_lvds;
8193
8194         has_lvds = intel_lvds_init(dev);
8195         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8196                 /* disable the panel fitter on everything but LVDS */
8197                 I915_WRITE(PFIT_CONTROL, 0);
8198         }
8199
8200         if (HAS_PCH_SPLIT(dev)) {
8201                 dpd_is_edp = intel_dpd_is_edp(dev);
8202
8203                 if (has_edp_a(dev))
8204                         intel_dp_init(dev, DP_A, PORT_A);
8205
8206                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8207                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8208         }
8209
8210         intel_crt_init(dev);
8211
8212         if (IS_HASWELL(dev)) {
8213                 int found;
8214
8215                 /* Haswell uses DDI functions to detect digital outputs */
8216                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8217                 /* DDI A only supports eDP */
8218                 if (found)
8219                         intel_ddi_init(dev, PORT_A);
8220
8221                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8222                  * register */
8223                 found = I915_READ(SFUSE_STRAP);
8224
8225                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8226                         intel_ddi_init(dev, PORT_B);
8227                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8228                         intel_ddi_init(dev, PORT_C);
8229                 if (found & SFUSE_STRAP_DDID_DETECTED)
8230                         intel_ddi_init(dev, PORT_D);
8231         } else if (HAS_PCH_SPLIT(dev)) {
8232                 int found;
8233
8234                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8235                         /* PCH SDVOB multiplex with HDMIB */
8236                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8237                         if (!found)
8238                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8239                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8240                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8241                 }
8242
8243                 if (I915_READ(HDMIC) & PORT_DETECTED)
8244                         intel_hdmi_init(dev, HDMIC, PORT_C);
8245
8246                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8247                         intel_hdmi_init(dev, HDMID, PORT_D);
8248
8249                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8250                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8251
8252                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8253                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8254         } else if (IS_VALLEYVIEW(dev)) {
8255                 int found;
8256
8257                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8258                 if (I915_READ(DP_C) & DP_DETECTED)
8259                         intel_dp_init(dev, DP_C, PORT_C);
8260
8261                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8262                         /* SDVOB multiplex with HDMIB */
8263                         found = intel_sdvo_init(dev, SDVOB, true);
8264                         if (!found)
8265                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8266                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8267                                 intel_dp_init(dev, DP_B, PORT_B);
8268                 }
8269
8270                 if (I915_READ(SDVOC) & PORT_DETECTED)
8271                         intel_hdmi_init(dev, SDVOC, PORT_C);
8272
8273         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8274                 bool found = false;
8275
8276                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8277                         DRM_DEBUG_KMS("probing SDVOB\n");
8278                         found = intel_sdvo_init(dev, SDVOB, true);
8279                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8280                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8281                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8282                         }
8283
8284                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8285                                 DRM_DEBUG_KMS("probing DP_B\n");
8286                                 intel_dp_init(dev, DP_B, PORT_B);
8287                         }
8288                 }
8289
8290                 /* Before G4X SDVOC doesn't have its own detect register */
8291
8292                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8293                         DRM_DEBUG_KMS("probing SDVOC\n");
8294                         found = intel_sdvo_init(dev, SDVOC, false);
8295                 }
8296
8297                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8298
8299                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8300                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8301                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8302                         }
8303                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8304                                 DRM_DEBUG_KMS("probing DP_C\n");
8305                                 intel_dp_init(dev, DP_C, PORT_C);
8306                         }
8307                 }
8308
8309                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8310                     (I915_READ(DP_D) & DP_DETECTED)) {
8311                         DRM_DEBUG_KMS("probing DP_D\n");
8312                         intel_dp_init(dev, DP_D, PORT_D);
8313                 }
8314         } else if (IS_GEN2(dev))
8315                 intel_dvo_init(dev);
8316
8317         if (SUPPORTS_TV(dev))
8318                 intel_tv_init(dev);
8319
8320         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8321                 encoder->base.possible_crtcs = encoder->crtc_mask;
8322                 encoder->base.possible_clones =
8323                         intel_encoder_clones(encoder);
8324         }
8325
8326         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8327                 ironlake_init_pch_refclk(dev);
8328 }
8329
8330 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8331 {
8332         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8333
8334         drm_framebuffer_cleanup(fb);
8335         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8336
8337         kfree(intel_fb);
8338 }
8339
8340 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8341                                                 struct drm_file *file,
8342                                                 unsigned int *handle)
8343 {
8344         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8345         struct drm_i915_gem_object *obj = intel_fb->obj;
8346
8347         return drm_gem_handle_create(file, &obj->base, handle);
8348 }
8349
8350 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8351         .destroy = intel_user_framebuffer_destroy,
8352         .create_handle = intel_user_framebuffer_create_handle,
8353 };
8354
8355 int intel_framebuffer_init(struct drm_device *dev,
8356                            struct intel_framebuffer *intel_fb,
8357                            struct drm_mode_fb_cmd2 *mode_cmd,
8358                            struct drm_i915_gem_object *obj)
8359 {
8360         int ret;
8361
8362         if (obj->tiling_mode == I915_TILING_Y)
8363                 return -EINVAL;
8364
8365         if (mode_cmd->pitches[0] & 63)
8366                 return -EINVAL;
8367
8368         /* FIXME <= Gen4 stride limits are bit unclear */
8369         if (mode_cmd->pitches[0] > 32768)
8370                 return -EINVAL;
8371
8372         if (obj->tiling_mode != I915_TILING_NONE &&
8373             mode_cmd->pitches[0] != obj->stride)
8374                 return -EINVAL;
8375
8376         /* Reject formats not supported by any plane early. */
8377         switch (mode_cmd->pixel_format) {
8378         case DRM_FORMAT_C8:
8379         case DRM_FORMAT_RGB565:
8380         case DRM_FORMAT_XRGB8888:
8381         case DRM_FORMAT_ARGB8888:
8382                 break;
8383         case DRM_FORMAT_XRGB1555:
8384         case DRM_FORMAT_ARGB1555:
8385                 if (INTEL_INFO(dev)->gen > 3)
8386                         return -EINVAL;
8387                 break;
8388         case DRM_FORMAT_XBGR8888:
8389         case DRM_FORMAT_ABGR8888:
8390         case DRM_FORMAT_XRGB2101010:
8391         case DRM_FORMAT_ARGB2101010:
8392         case DRM_FORMAT_XBGR2101010:
8393         case DRM_FORMAT_ABGR2101010:
8394                 if (INTEL_INFO(dev)->gen < 4)
8395                         return -EINVAL;
8396                 break;
8397         case DRM_FORMAT_YUYV:
8398         case DRM_FORMAT_UYVY:
8399         case DRM_FORMAT_YVYU:
8400         case DRM_FORMAT_VYUY:
8401                 if (INTEL_INFO(dev)->gen < 6)
8402                         return -EINVAL;
8403                 break;
8404         default:
8405                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8406                 return -EINVAL;
8407         }
8408
8409         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8410         if (mode_cmd->offsets[0] != 0)
8411                 return -EINVAL;
8412
8413         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8414         if (ret) {
8415                 DRM_ERROR("framebuffer init failed %d\n", ret);
8416                 return ret;
8417         }
8418
8419         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8420         intel_fb->obj = obj;
8421         return 0;
8422 }
8423
8424 static struct drm_framebuffer *
8425 intel_user_framebuffer_create(struct drm_device *dev,
8426                               struct drm_file *filp,
8427                               struct drm_mode_fb_cmd2 *mode_cmd)
8428 {
8429         struct drm_i915_gem_object *obj;
8430
8431         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8432                                                 mode_cmd->handles[0]));
8433         if (&obj->base == NULL)
8434                 return ERR_PTR(-ENOENT);
8435
8436         return intel_framebuffer_create(dev, mode_cmd, obj);
8437 }
8438
8439 static const struct drm_mode_config_funcs intel_mode_funcs = {
8440         .fb_create = intel_user_framebuffer_create,
8441         .output_poll_changed = intel_fb_output_poll_changed,
8442 };
8443
8444 /* Set up chip specific display functions */
8445 static void intel_init_display(struct drm_device *dev)
8446 {
8447         struct drm_i915_private *dev_priv = dev->dev_private;
8448
8449         /* We always want a DPMS function */
8450         if (IS_HASWELL(dev)) {
8451                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8452                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8453                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8454                 dev_priv->display.off = haswell_crtc_off;
8455                 dev_priv->display.update_plane = ironlake_update_plane;
8456         } else if (HAS_PCH_SPLIT(dev)) {
8457                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8458                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8459                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8460                 dev_priv->display.off = ironlake_crtc_off;
8461                 dev_priv->display.update_plane = ironlake_update_plane;
8462         } else {
8463                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8464                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8465                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8466                 dev_priv->display.off = i9xx_crtc_off;
8467                 dev_priv->display.update_plane = i9xx_update_plane;
8468         }
8469
8470         /* Returns the core display clock speed */
8471         if (IS_VALLEYVIEW(dev))
8472                 dev_priv->display.get_display_clock_speed =
8473                         valleyview_get_display_clock_speed;
8474         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8475                 dev_priv->display.get_display_clock_speed =
8476                         i945_get_display_clock_speed;
8477         else if (IS_I915G(dev))
8478                 dev_priv->display.get_display_clock_speed =
8479                         i915_get_display_clock_speed;
8480         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8481                 dev_priv->display.get_display_clock_speed =
8482                         i9xx_misc_get_display_clock_speed;
8483         else if (IS_I915GM(dev))
8484                 dev_priv->display.get_display_clock_speed =
8485                         i915gm_get_display_clock_speed;
8486         else if (IS_I865G(dev))
8487                 dev_priv->display.get_display_clock_speed =
8488                         i865_get_display_clock_speed;
8489         else if (IS_I85X(dev))
8490                 dev_priv->display.get_display_clock_speed =
8491                         i855_get_display_clock_speed;
8492         else /* 852, 830 */
8493                 dev_priv->display.get_display_clock_speed =
8494                         i830_get_display_clock_speed;
8495
8496         if (HAS_PCH_SPLIT(dev)) {
8497                 if (IS_GEN5(dev)) {
8498                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8499                         dev_priv->display.write_eld = ironlake_write_eld;
8500                 } else if (IS_GEN6(dev)) {
8501                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8502                         dev_priv->display.write_eld = ironlake_write_eld;
8503                 } else if (IS_IVYBRIDGE(dev)) {
8504                         /* FIXME: detect B0+ stepping and use auto training */
8505                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8506                         dev_priv->display.write_eld = ironlake_write_eld;
8507                         dev_priv->display.modeset_global_resources =
8508                                 ivb_modeset_global_resources;
8509                 } else if (IS_HASWELL(dev)) {
8510                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8511                         dev_priv->display.write_eld = haswell_write_eld;
8512                 } else
8513                         dev_priv->display.update_wm = NULL;
8514         } else if (IS_G4X(dev)) {
8515                 dev_priv->display.write_eld = g4x_write_eld;
8516         }
8517
8518         /* Default just returns -ENODEV to indicate unsupported */
8519         dev_priv->display.queue_flip = intel_default_queue_flip;
8520
8521         switch (INTEL_INFO(dev)->gen) {
8522         case 2:
8523                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8524                 break;
8525
8526         case 3:
8527                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8528                 break;
8529
8530         case 4:
8531         case 5:
8532                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8533                 break;
8534
8535         case 6:
8536                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8537                 break;
8538         case 7:
8539                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8540                 break;
8541         }
8542 }
8543
8544 /*
8545  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8546  * resume, or other times.  This quirk makes sure that's the case for
8547  * affected systems.
8548  */
8549 static void quirk_pipea_force(struct drm_device *dev)
8550 {
8551         struct drm_i915_private *dev_priv = dev->dev_private;
8552
8553         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8554         DRM_INFO("applying pipe a force quirk\n");
8555 }
8556
8557 /*
8558  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8559  */
8560 static void quirk_ssc_force_disable(struct drm_device *dev)
8561 {
8562         struct drm_i915_private *dev_priv = dev->dev_private;
8563         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8564         DRM_INFO("applying lvds SSC disable quirk\n");
8565 }
8566
8567 /*
8568  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8569  * brightness value
8570  */
8571 static void quirk_invert_brightness(struct drm_device *dev)
8572 {
8573         struct drm_i915_private *dev_priv = dev->dev_private;
8574         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8575         DRM_INFO("applying inverted panel brightness quirk\n");
8576 }
8577
8578 struct intel_quirk {
8579         int device;
8580         int subsystem_vendor;
8581         int subsystem_device;
8582         void (*hook)(struct drm_device *dev);
8583 };
8584
8585 static struct intel_quirk intel_quirks[] = {
8586         /* HP Mini needs pipe A force quirk (LP: #322104) */
8587         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8588
8589         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8590         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8591
8592         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8593         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8594
8595         /* 830/845 need to leave pipe A & dpll A up */
8596         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8597         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8598
8599         /* Lenovo U160 cannot use SSC on LVDS */
8600         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8601
8602         /* Sony Vaio Y cannot use SSC on LVDS */
8603         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8604
8605         /* Acer Aspire 5734Z must invert backlight brightness */
8606         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8607 };
8608
8609 static void intel_init_quirks(struct drm_device *dev)
8610 {
8611         struct pci_dev *d = dev->pdev;
8612         int i;
8613
8614         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8615                 struct intel_quirk *q = &intel_quirks[i];
8616
8617                 if (d->device == q->device &&
8618                     (d->subsystem_vendor == q->subsystem_vendor ||
8619                      q->subsystem_vendor == PCI_ANY_ID) &&
8620                     (d->subsystem_device == q->subsystem_device ||
8621                      q->subsystem_device == PCI_ANY_ID))
8622                         q->hook(dev);
8623         }
8624 }
8625
8626 /* Disable the VGA plane that we never use */
8627 static void i915_disable_vga(struct drm_device *dev)
8628 {
8629         struct drm_i915_private *dev_priv = dev->dev_private;
8630         u8 sr1;
8631         u32 vga_reg;
8632
8633         if (HAS_PCH_SPLIT(dev))
8634                 vga_reg = CPU_VGACNTRL;
8635         else
8636                 vga_reg = VGACNTRL;
8637
8638         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8639         outb(SR01, VGA_SR_INDEX);
8640         sr1 = inb(VGA_SR_DATA);
8641         outb(sr1 | 1<<5, VGA_SR_DATA);
8642         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8643         udelay(300);
8644
8645         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8646         POSTING_READ(vga_reg);
8647 }
8648
8649 void intel_modeset_init_hw(struct drm_device *dev)
8650 {
8651         /* We attempt to init the necessary power wells early in the initialization
8652          * time, so the subsystems that expect power to be enabled can work.
8653          */
8654         intel_init_power_wells(dev);
8655
8656         intel_prepare_ddi(dev);
8657
8658         intel_init_clock_gating(dev);
8659
8660         mutex_lock(&dev->struct_mutex);
8661         intel_enable_gt_powersave(dev);
8662         mutex_unlock(&dev->struct_mutex);
8663 }
8664
8665 void intel_modeset_init(struct drm_device *dev)
8666 {
8667         struct drm_i915_private *dev_priv = dev->dev_private;
8668         int i, ret;
8669
8670         drm_mode_config_init(dev);
8671
8672         dev->mode_config.min_width = 0;
8673         dev->mode_config.min_height = 0;
8674
8675         dev->mode_config.preferred_depth = 24;
8676         dev->mode_config.prefer_shadow = 1;
8677
8678         dev->mode_config.funcs = &intel_mode_funcs;
8679
8680         intel_init_quirks(dev);
8681
8682         intel_init_pm(dev);
8683
8684         intel_init_display(dev);
8685
8686         if (IS_GEN2(dev)) {
8687                 dev->mode_config.max_width = 2048;
8688                 dev->mode_config.max_height = 2048;
8689         } else if (IS_GEN3(dev)) {
8690                 dev->mode_config.max_width = 4096;
8691                 dev->mode_config.max_height = 4096;
8692         } else {
8693                 dev->mode_config.max_width = 8192;
8694                 dev->mode_config.max_height = 8192;
8695         }
8696         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8697
8698         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8699                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8700
8701         for (i = 0; i < dev_priv->num_pipe; i++) {
8702                 intel_crtc_init(dev, i);
8703                 ret = intel_plane_init(dev, i);
8704                 if (ret)
8705                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8706         }
8707
8708         intel_cpu_pll_init(dev);
8709         intel_pch_pll_init(dev);
8710
8711         /* Just disable it once at startup */
8712         i915_disable_vga(dev);
8713         intel_setup_outputs(dev);
8714 }
8715
8716 static void
8717 intel_connector_break_all_links(struct intel_connector *connector)
8718 {
8719         connector->base.dpms = DRM_MODE_DPMS_OFF;
8720         connector->base.encoder = NULL;
8721         connector->encoder->connectors_active = false;
8722         connector->encoder->base.crtc = NULL;
8723 }
8724
8725 static void intel_enable_pipe_a(struct drm_device *dev)
8726 {
8727         struct intel_connector *connector;
8728         struct drm_connector *crt = NULL;
8729         struct intel_load_detect_pipe load_detect_temp;
8730
8731         /* We can't just switch on the pipe A, we need to set things up with a
8732          * proper mode and output configuration. As a gross hack, enable pipe A
8733          * by enabling the load detect pipe once. */
8734         list_for_each_entry(connector,
8735                             &dev->mode_config.connector_list,
8736                             base.head) {
8737                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8738                         crt = &connector->base;
8739                         break;
8740                 }
8741         }
8742
8743         if (!crt)
8744                 return;
8745
8746         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8747                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8748
8749
8750 }
8751
8752 static bool
8753 intel_check_plane_mapping(struct intel_crtc *crtc)
8754 {
8755         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8756         u32 reg, val;
8757
8758         if (dev_priv->num_pipe == 1)
8759                 return true;
8760
8761         reg = DSPCNTR(!crtc->plane);
8762         val = I915_READ(reg);
8763
8764         if ((val & DISPLAY_PLANE_ENABLE) &&
8765             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8766                 return false;
8767
8768         return true;
8769 }
8770
8771 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8772 {
8773         struct drm_device *dev = crtc->base.dev;
8774         struct drm_i915_private *dev_priv = dev->dev_private;
8775         u32 reg;
8776
8777         /* Clear any frame start delays used for debugging left by the BIOS */
8778         reg = PIPECONF(crtc->cpu_transcoder);
8779         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8780
8781         /* We need to sanitize the plane -> pipe mapping first because this will
8782          * disable the crtc (and hence change the state) if it is wrong. Note
8783          * that gen4+ has a fixed plane -> pipe mapping.  */
8784         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8785                 struct intel_connector *connector;
8786                 bool plane;
8787
8788                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8789                               crtc->base.base.id);
8790
8791                 /* Pipe has the wrong plane attached and the plane is active.
8792                  * Temporarily change the plane mapping and disable everything
8793                  * ...  */
8794                 plane = crtc->plane;
8795                 crtc->plane = !plane;
8796                 dev_priv->display.crtc_disable(&crtc->base);
8797                 crtc->plane = plane;
8798
8799                 /* ... and break all links. */
8800                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8801                                     base.head) {
8802                         if (connector->encoder->base.crtc != &crtc->base)
8803                                 continue;
8804
8805                         intel_connector_break_all_links(connector);
8806                 }
8807
8808                 WARN_ON(crtc->active);
8809                 crtc->base.enabled = false;
8810         }
8811
8812         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8813             crtc->pipe == PIPE_A && !crtc->active) {
8814                 /* BIOS forgot to enable pipe A, this mostly happens after
8815                  * resume. Force-enable the pipe to fix this, the update_dpms
8816                  * call below we restore the pipe to the right state, but leave
8817                  * the required bits on. */
8818                 intel_enable_pipe_a(dev);
8819         }
8820
8821         /* Adjust the state of the output pipe according to whether we
8822          * have active connectors/encoders. */
8823         intel_crtc_update_dpms(&crtc->base);
8824
8825         if (crtc->active != crtc->base.enabled) {
8826                 struct intel_encoder *encoder;
8827
8828                 /* This can happen either due to bugs in the get_hw_state
8829                  * functions or because the pipe is force-enabled due to the
8830                  * pipe A quirk. */
8831                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8832                               crtc->base.base.id,
8833                               crtc->base.enabled ? "enabled" : "disabled",
8834                               crtc->active ? "enabled" : "disabled");
8835
8836                 crtc->base.enabled = crtc->active;
8837
8838                 /* Because we only establish the connector -> encoder ->
8839                  * crtc links if something is active, this means the
8840                  * crtc is now deactivated. Break the links. connector
8841                  * -> encoder links are only establish when things are
8842                  *  actually up, hence no need to break them. */
8843                 WARN_ON(crtc->active);
8844
8845                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8846                         WARN_ON(encoder->connectors_active);
8847                         encoder->base.crtc = NULL;
8848                 }
8849         }
8850 }
8851
8852 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8853 {
8854         struct intel_connector *connector;
8855         struct drm_device *dev = encoder->base.dev;
8856
8857         /* We need to check both for a crtc link (meaning that the
8858          * encoder is active and trying to read from a pipe) and the
8859          * pipe itself being active. */
8860         bool has_active_crtc = encoder->base.crtc &&
8861                 to_intel_crtc(encoder->base.crtc)->active;
8862
8863         if (encoder->connectors_active && !has_active_crtc) {
8864                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8865                               encoder->base.base.id,
8866                               drm_get_encoder_name(&encoder->base));
8867
8868                 /* Connector is active, but has no active pipe. This is
8869                  * fallout from our resume register restoring. Disable
8870                  * the encoder manually again. */
8871                 if (encoder->base.crtc) {
8872                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8873                                       encoder->base.base.id,
8874                                       drm_get_encoder_name(&encoder->base));
8875                         encoder->disable(encoder);
8876                 }
8877
8878                 /* Inconsistent output/port/pipe state happens presumably due to
8879                  * a bug in one of the get_hw_state functions. Or someplace else
8880                  * in our code, like the register restore mess on resume. Clamp
8881                  * things to off as a safer default. */
8882                 list_for_each_entry(connector,
8883                                     &dev->mode_config.connector_list,
8884                                     base.head) {
8885                         if (connector->encoder != encoder)
8886                                 continue;
8887
8888                         intel_connector_break_all_links(connector);
8889                 }
8890         }
8891         /* Enabled encoders without active connectors will be fixed in
8892          * the crtc fixup. */
8893 }
8894
8895 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8896  * and i915 state tracking structures. */
8897 void intel_modeset_setup_hw_state(struct drm_device *dev)
8898 {
8899         struct drm_i915_private *dev_priv = dev->dev_private;
8900         enum pipe pipe;
8901         u32 tmp;
8902         struct intel_crtc *crtc;
8903         struct intel_encoder *encoder;
8904         struct intel_connector *connector;
8905
8906         if (IS_HASWELL(dev)) {
8907                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8908
8909                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8910                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8911                         case TRANS_DDI_EDP_INPUT_A_ON:
8912                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8913                                 pipe = PIPE_A;
8914                                 break;
8915                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8916                                 pipe = PIPE_B;
8917                                 break;
8918                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8919                                 pipe = PIPE_C;
8920                                 break;
8921                         }
8922
8923                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8924                         crtc->cpu_transcoder = TRANSCODER_EDP;
8925
8926                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8927                                       pipe_name(pipe));
8928                 }
8929         }
8930
8931         for_each_pipe(pipe) {
8932                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8933
8934                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8935                 if (tmp & PIPECONF_ENABLE)
8936                         crtc->active = true;
8937                 else
8938                         crtc->active = false;
8939
8940                 crtc->base.enabled = crtc->active;
8941
8942                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8943                               crtc->base.base.id,
8944                               crtc->active ? "enabled" : "disabled");
8945         }
8946
8947         if (IS_HASWELL(dev))
8948                 intel_ddi_setup_hw_pll_state(dev);
8949
8950         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8951                             base.head) {
8952                 pipe = 0;
8953
8954                 if (encoder->get_hw_state(encoder, &pipe)) {
8955                         encoder->base.crtc =
8956                                 dev_priv->pipe_to_crtc_mapping[pipe];
8957                 } else {
8958                         encoder->base.crtc = NULL;
8959                 }
8960
8961                 encoder->connectors_active = false;
8962                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8963                               encoder->base.base.id,
8964                               drm_get_encoder_name(&encoder->base),
8965                               encoder->base.crtc ? "enabled" : "disabled",
8966                               pipe);
8967         }
8968
8969         list_for_each_entry(connector, &dev->mode_config.connector_list,
8970                             base.head) {
8971                 if (connector->get_hw_state(connector)) {
8972                         connector->base.dpms = DRM_MODE_DPMS_ON;
8973                         connector->encoder->connectors_active = true;
8974                         connector->base.encoder = &connector->encoder->base;
8975                 } else {
8976                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8977                         connector->base.encoder = NULL;
8978                 }
8979                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8980                               connector->base.base.id,
8981                               drm_get_connector_name(&connector->base),
8982                               connector->base.encoder ? "enabled" : "disabled");
8983         }
8984
8985         /* HW state is read out, now we need to sanitize this mess. */
8986         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8987                             base.head) {
8988                 intel_sanitize_encoder(encoder);
8989         }
8990
8991         for_each_pipe(pipe) {
8992                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8993                 intel_sanitize_crtc(crtc);
8994         }
8995
8996         intel_modeset_update_staged_output_state(dev);
8997
8998         intel_modeset_check_state(dev);
8999
9000         drm_mode_config_reset(dev);
9001 }
9002
9003 void intel_modeset_gem_init(struct drm_device *dev)
9004 {
9005         intel_modeset_init_hw(dev);
9006
9007         intel_setup_overlay(dev);
9008
9009         intel_modeset_setup_hw_state(dev);
9010 }
9011
9012 void intel_modeset_cleanup(struct drm_device *dev)
9013 {
9014         struct drm_i915_private *dev_priv = dev->dev_private;
9015         struct drm_crtc *crtc;
9016         struct intel_crtc *intel_crtc;
9017
9018         drm_kms_helper_poll_fini(dev);
9019         mutex_lock(&dev->struct_mutex);
9020
9021         intel_unregister_dsm_handler();
9022
9023
9024         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9025                 /* Skip inactive CRTCs */
9026                 if (!crtc->fb)
9027                         continue;
9028
9029                 intel_crtc = to_intel_crtc(crtc);
9030                 intel_increase_pllclock(crtc);
9031         }
9032
9033         intel_disable_fbc(dev);
9034
9035         intel_disable_gt_powersave(dev);
9036
9037         ironlake_teardown_rc6(dev);
9038
9039         if (IS_VALLEYVIEW(dev))
9040                 vlv_init_dpio(dev);
9041
9042         mutex_unlock(&dev->struct_mutex);
9043
9044         /* Disable the irq before mode object teardown, for the irq might
9045          * enqueue unpin/hotplug work. */
9046         drm_irq_uninstall(dev);
9047         cancel_work_sync(&dev_priv->hotplug_work);
9048         cancel_work_sync(&dev_priv->rps.work);
9049
9050         /* flush any delayed tasks or pending work */
9051         flush_scheduled_work();
9052
9053         drm_mode_config_cleanup(dev);
9054 }
9055
9056 /*
9057  * Return which encoder is currently attached for connector.
9058  */
9059 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9060 {
9061         return &intel_attached_encoder(connector)->base;
9062 }
9063
9064 void intel_connector_attach_encoder(struct intel_connector *connector,
9065                                     struct intel_encoder *encoder)
9066 {
9067         connector->encoder = encoder;
9068         drm_mode_connector_attach_encoder(&connector->base,
9069                                           &encoder->base);
9070 }
9071
9072 /*
9073  * set vga decode state - true == enable VGA decode
9074  */
9075 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9076 {
9077         struct drm_i915_private *dev_priv = dev->dev_private;
9078         u16 gmch_ctrl;
9079
9080         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9081         if (state)
9082                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9083         else
9084                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9085         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9086         return 0;
9087 }
9088
9089 #ifdef CONFIG_DEBUG_FS
9090 #include <linux/seq_file.h>
9091
9092 struct intel_display_error_state {
9093         struct intel_cursor_error_state {
9094                 u32 control;
9095                 u32 position;
9096                 u32 base;
9097                 u32 size;
9098         } cursor[I915_MAX_PIPES];
9099
9100         struct intel_pipe_error_state {
9101                 u32 conf;
9102                 u32 source;
9103
9104                 u32 htotal;
9105                 u32 hblank;
9106                 u32 hsync;
9107                 u32 vtotal;
9108                 u32 vblank;
9109                 u32 vsync;
9110         } pipe[I915_MAX_PIPES];
9111
9112         struct intel_plane_error_state {
9113                 u32 control;
9114                 u32 stride;
9115                 u32 size;
9116                 u32 pos;
9117                 u32 addr;
9118                 u32 surface;
9119                 u32 tile_offset;
9120         } plane[I915_MAX_PIPES];
9121 };
9122
9123 struct intel_display_error_state *
9124 intel_display_capture_error_state(struct drm_device *dev)
9125 {
9126         drm_i915_private_t *dev_priv = dev->dev_private;
9127         struct intel_display_error_state *error;
9128         enum transcoder cpu_transcoder;
9129         int i;
9130
9131         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9132         if (error == NULL)
9133                 return NULL;
9134
9135         for_each_pipe(i) {
9136                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9137
9138                 error->cursor[i].control = I915_READ(CURCNTR(i));
9139                 error->cursor[i].position = I915_READ(CURPOS(i));
9140                 error->cursor[i].base = I915_READ(CURBASE(i));
9141
9142                 error->plane[i].control = I915_READ(DSPCNTR(i));
9143                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9144                 error->plane[i].size = I915_READ(DSPSIZE(i));
9145                 error->plane[i].pos = I915_READ(DSPPOS(i));
9146                 error->plane[i].addr = I915_READ(DSPADDR(i));
9147                 if (INTEL_INFO(dev)->gen >= 4) {
9148                         error->plane[i].surface = I915_READ(DSPSURF(i));
9149                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9150                 }
9151
9152                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9153                 error->pipe[i].source = I915_READ(PIPESRC(i));
9154                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9155                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9156                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9157                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9158                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9159                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9160         }
9161
9162         return error;
9163 }
9164
9165 void
9166 intel_display_print_error_state(struct seq_file *m,
9167                                 struct drm_device *dev,
9168                                 struct intel_display_error_state *error)
9169 {
9170         drm_i915_private_t *dev_priv = dev->dev_private;
9171         int i;
9172
9173         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9174         for_each_pipe(i) {
9175                 seq_printf(m, "Pipe [%d]:\n", i);
9176                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9177                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9178                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9179                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9180                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9181                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9182                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9183                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9184
9185                 seq_printf(m, "Plane [%d]:\n", i);
9186                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9187                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9188                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9189                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9190                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9191                 if (INTEL_INFO(dev)->gen >= 4) {
9192                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9193                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9194                 }
9195
9196                 seq_printf(m, "Cursor [%d]:\n", i);
9197                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9198                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9199                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9200         }
9201 }
9202 #endif