drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  50 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  51 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  52 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  53 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  54
  55 #ifdef RTL8169_DEBUG
  56 #define assert(expr) \
  57         if (!(expr)) {                                  \
  58                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  59                 #expr,__FILE__,__func__,__LINE__);              \
  60         }
  61 #define dprintk(fmt, args...) \
  62         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  63 #else
  64 #define assert(expr) do {} while (0)
  65 #define dprintk(fmt, args...)   do {} while (0)
  66 #endif /* RTL8169_DEBUG */
  67
  68 #define R8169_MSG_DEFAULT \
  69         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  70
  71 #define TX_SLOTS_AVAIL(tp) \
  72         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  73
  74 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  75 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  76         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  77
  78 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  79    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  80 static const int multicast_filter_limit = 32;
  81
  82 #define MAX_READ_REQUEST_SHIFT  12
  83 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  84 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  85
  86 #define R8169_REGS_SIZE         256
  87 #define R8169_NAPI_WEIGHT       64
  88 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  89 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  90 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  91 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  92
  93 #define RTL8169_TX_TIMEOUT      (6*HZ)
  94 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  95
  96 /* write/read MMIO register */
  97 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  98 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  99 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 100 #define RTL_R8(reg)             readb (ioaddr + (reg))
 101 #define RTL_R16(reg)            readw (ioaddr + (reg))
 102 #define RTL_R32(reg)            readl (ioaddr + (reg))
 103
 104 enum mac_version {
 105         RTL_GIGA_MAC_VER_01 = 0,
 106         RTL_GIGA_MAC_VER_02,
 107         RTL_GIGA_MAC_VER_03,
 108         RTL_GIGA_MAC_VER_04,
 109         RTL_GIGA_MAC_VER_05,
 110         RTL_GIGA_MAC_VER_06,
 111         RTL_GIGA_MAC_VER_07,
 112         RTL_GIGA_MAC_VER_08,
 113         RTL_GIGA_MAC_VER_09,
 114         RTL_GIGA_MAC_VER_10,
 115         RTL_GIGA_MAC_VER_11,
 116         RTL_GIGA_MAC_VER_12,
 117         RTL_GIGA_MAC_VER_13,
 118         RTL_GIGA_MAC_VER_14,
 119         RTL_GIGA_MAC_VER_15,
 120         RTL_GIGA_MAC_VER_16,
 121         RTL_GIGA_MAC_VER_17,
 122         RTL_GIGA_MAC_VER_18,
 123         RTL_GIGA_MAC_VER_19,
 124         RTL_GIGA_MAC_VER_20,
 125         RTL_GIGA_MAC_VER_21,
 126         RTL_GIGA_MAC_VER_22,
 127         RTL_GIGA_MAC_VER_23,
 128         RTL_GIGA_MAC_VER_24,
 129         RTL_GIGA_MAC_VER_25,
 130         RTL_GIGA_MAC_VER_26,
 131         RTL_GIGA_MAC_VER_27,
 132         RTL_GIGA_MAC_VER_28,
 133         RTL_GIGA_MAC_VER_29,
 134         RTL_GIGA_MAC_VER_30,
 135         RTL_GIGA_MAC_VER_31,
 136         RTL_GIGA_MAC_VER_32,
 137         RTL_GIGA_MAC_VER_33,
 138         RTL_GIGA_MAC_VER_34,
 139         RTL_GIGA_MAC_VER_35,
 140         RTL_GIGA_MAC_VER_36,
 141         RTL_GIGA_MAC_VER_37,
 142         RTL_GIGA_MAC_VER_38,
 143         RTL_GIGA_MAC_VER_39,
 144         RTL_GIGA_MAC_VER_40,
 145         RTL_GIGA_MAC_VER_41,
 146         RTL_GIGA_MAC_VER_42,
 147         RTL_GIGA_MAC_VER_43,
 148         RTL_GIGA_MAC_VER_44,
 149         RTL_GIGA_MAC_NONE   = 0xff,
 150 };
 151
 152 enum rtl_tx_desc_version {
 153         RTL_TD_0        = 0,
 154         RTL_TD_1        = 1,
 155 };
 156
 157 #define JUMBO_1K        ETH_DATA_LEN
 158 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 159 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 160 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 161 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 162
 163 #define _R(NAME,TD,FW,SZ,B) {   \
 164         .name = NAME,           \
 165         .txd_version = TD,      \
 166         .fw_name = FW,          \
 167         .jumbo_max = SZ,        \
 168         .jumbo_tx_csum = B      \
 169 }
 170
 171 static const struct {
 172         const char *name;
 173         enum rtl_tx_desc_version txd_version;
 174         const char *fw_name;
 175         u16 jumbo_max;
 176         bool jumbo_tx_csum;
 177 } rtl_chip_infos[] = {
 178         /* PCI devices. */
 179         [RTL_GIGA_MAC_VER_01] =
 180                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 181         [RTL_GIGA_MAC_VER_02] =
 182                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 183         [RTL_GIGA_MAC_VER_03] =
 184                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 185         [RTL_GIGA_MAC_VER_04] =
 186                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 187         [RTL_GIGA_MAC_VER_05] =
 188                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 189         [RTL_GIGA_MAC_VER_06] =
 190                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 191         /* PCI-E devices. */
 192         [RTL_GIGA_MAC_VER_07] =
 193                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 194         [RTL_GIGA_MAC_VER_08] =
 195                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 196         [RTL_GIGA_MAC_VER_09] =
 197                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 198         [RTL_GIGA_MAC_VER_10] =
 199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 200         [RTL_GIGA_MAC_VER_11] =
 201                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 202         [RTL_GIGA_MAC_VER_12] =
 203                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 204         [RTL_GIGA_MAC_VER_13] =
 205                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_14] =
 207                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_15] =
 209                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_16] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_17] =
 213                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_18] =
 215                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 216         [RTL_GIGA_MAC_VER_19] =
 217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 218         [RTL_GIGA_MAC_VER_20] =
 219                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 220         [RTL_GIGA_MAC_VER_21] =
 221                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 222         [RTL_GIGA_MAC_VER_22] =
 223                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 224         [RTL_GIGA_MAC_VER_23] =
 225                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 226         [RTL_GIGA_MAC_VER_24] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_25] =
 229                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 230                                                         JUMBO_9K, false),
 231         [RTL_GIGA_MAC_VER_26] =
 232                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 233                                                         JUMBO_9K, false),
 234         [RTL_GIGA_MAC_VER_27] =
 235                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 236         [RTL_GIGA_MAC_VER_28] =
 237                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 238         [RTL_GIGA_MAC_VER_29] =
 239                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 240                                                         JUMBO_1K, true),
 241         [RTL_GIGA_MAC_VER_30] =
 242                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 243                                                         JUMBO_1K, true),
 244         [RTL_GIGA_MAC_VER_31] =
 245                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_32] =
 247                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_33] =
 250                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 251                                                         JUMBO_9K, false),
 252         [RTL_GIGA_MAC_VER_34] =
 253                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 254                                                         JUMBO_9K, false),
 255         [RTL_GIGA_MAC_VER_35] =
 256                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 257                                                         JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_36] =
 259                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_37] =
 262                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 263                                                         JUMBO_1K, true),
 264         [RTL_GIGA_MAC_VER_38] =
 265                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_39] =
 268                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 269                                                         JUMBO_1K, true),
 270         [RTL_GIGA_MAC_VER_40] =
 271                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_41] =
 274                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 275         [RTL_GIGA_MAC_VER_42] =
 276                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 277                                                         JUMBO_9K, false),
 278         [RTL_GIGA_MAC_VER_43] =
 279                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 280                                                         JUMBO_1K, true),
 281         [RTL_GIGA_MAC_VER_44] =
 282                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 283                                                         JUMBO_9K, false),
 284 };
 285 #undef _R
 286
 287 enum cfg_version {
 288         RTL_CFG_0 = 0x00,
 289         RTL_CFG_1,
 290         RTL_CFG_2
 291 };
 292
 293 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 294         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 295         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 296         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 297         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 298         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 299         { PCI_VENDOR_ID_DLINK,                  0x4300,
 300                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 301         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 302         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 303         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 304         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 305         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 306                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 307         { 0x0001,                               0x8168,
 308                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 309         {0,},
 310 };
 311
 312 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 313
 314 static int rx_buf_sz = 16383;
 315 static int use_dac;
 316 static struct {
 317         u32 msg_enable;
 318 } debug = { -1 };
 319
 320 enum rtl_registers {
 321         MAC0            = 0,    /* Ethernet hardware address. */
 322         MAC4            = 4,
 323         MAR0            = 8,    /* Multicast filter. */
 324         CounterAddrLow          = 0x10,
 325         CounterAddrHigh         = 0x14,
 326         TxDescStartAddrLow      = 0x20,
 327         TxDescStartAddrHigh     = 0x24,
 328         TxHDescStartAddrLow     = 0x28,
 329         TxHDescStartAddrHigh    = 0x2c,
 330         FLASH           = 0x30,
 331         ERSR            = 0x36,
 332         ChipCmd         = 0x37,
 333         TxPoll          = 0x38,
 334         IntrMask        = 0x3c,
 335         IntrStatus      = 0x3e,
 336
 337         TxConfig        = 0x40,
 338 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 339 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 340
 341         RxConfig        = 0x44,
 342 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 343 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 344 #define RXCFG_FIFO_SHIFT                13
 345                                         /* No threshold before first PCI xfer */
 346 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 347 #define RX_EARLY_OFF                    (1 << 11)
 348 #define RXCFG_DMA_SHIFT                 8
 349                                         /* Unlimited maximum PCI burst. */
 350 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 351
 352         RxMissed        = 0x4c,
 353         Cfg9346         = 0x50,
 354         Config0         = 0x51,
 355         Config1         = 0x52,
 356         Config2         = 0x53,
 357 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 358
 359         Config3         = 0x54,
 360         Config4         = 0x55,
 361         Config5         = 0x56,
 362         MultiIntr       = 0x5c,
 363         PHYAR           = 0x60,
 364         PHYstatus       = 0x6c,
 365         RxMaxSize       = 0xda,
 366         CPlusCmd        = 0xe0,
 367         IntrMitigate    = 0xe2,
 368         RxDescAddrLow   = 0xe4,
 369         RxDescAddrHigh  = 0xe8,
 370         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 371
 372 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 373
 374         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 375
 376 #define TxPacketMax     (8064 >> 7)
 377 #define EarlySize       0x27
 378
 379         FuncEvent       = 0xf0,
 380         FuncEventMask   = 0xf4,
 381         FuncPresetState = 0xf8,
 382         FuncForceEvent  = 0xfc,
 383 };
 384
 385 enum rtl8110_registers {
 386         TBICSR                  = 0x64,
 387         TBI_ANAR                = 0x68,
 388         TBI_LPAR                = 0x6a,
 389 };
 390
 391 enum rtl8168_8101_registers {
 392         CSIDR                   = 0x64,
 393         CSIAR                   = 0x68,
 394 #define CSIAR_FLAG                      0x80000000
 395 #define CSIAR_WRITE_CMD                 0x80000000
 396 #define CSIAR_BYTE_ENABLE               0x0f
 397 #define CSIAR_BYTE_ENABLE_SHIFT         12
 398 #define CSIAR_ADDR_MASK                 0x0fff
 399 #define CSIAR_FUNC_CARD                 0x00000000
 400 #define CSIAR_FUNC_SDIO                 0x00010000
 401 #define CSIAR_FUNC_NIC                  0x00020000
 402 #define CSIAR_FUNC_NIC2                 0x00010000
 403         PMCH                    = 0x6f,
 404         EPHYAR                  = 0x80,
 405 #define EPHYAR_FLAG                     0x80000000
 406 #define EPHYAR_WRITE_CMD                0x80000000
 407 #define EPHYAR_REG_MASK                 0x1f
 408 #define EPHYAR_REG_SHIFT                16
 409 #define EPHYAR_DATA_MASK                0xffff
 410         DLLPR                   = 0xd0,
 411 #define PFM_EN                          (1 << 6)
 412         DBG_REG                 = 0xd1,
 413 #define FIX_NAK_1                       (1 << 4)
 414 #define FIX_NAK_2                       (1 << 3)
 415         TWSI                    = 0xd2,
 416         MCU                     = 0xd3,
 417 #define NOW_IS_OOB                      (1 << 7)
 418 #define TX_EMPTY                        (1 << 5)
 419 #define RX_EMPTY                        (1 << 4)
 420 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 421 #define EN_NDP                          (1 << 3)
 422 #define EN_OOB_RESET                    (1 << 2)
 423 #define LINK_LIST_RDY                   (1 << 1)
 424         EFUSEAR                 = 0xdc,
 425 #define EFUSEAR_FLAG                    0x80000000
 426 #define EFUSEAR_WRITE_CMD               0x80000000
 427 #define EFUSEAR_READ_CMD                0x00000000
 428 #define EFUSEAR_REG_MASK                0x03ff
 429 #define EFUSEAR_REG_SHIFT               8
 430 #define EFUSEAR_DATA_MASK               0xff
 431 };
 432
 433 enum rtl8168_registers {
 434         LED_FREQ                = 0x1a,
 435         EEE_LED                 = 0x1b,
 436         ERIDR                   = 0x70,
 437         ERIAR                   = 0x74,
 438 #define ERIAR_FLAG                      0x80000000
 439 #define ERIAR_WRITE_CMD                 0x80000000
 440 #define ERIAR_READ_CMD                  0x00000000
 441 #define ERIAR_ADDR_BYTE_ALIGN           4
 442 #define ERIAR_TYPE_SHIFT                16
 443 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 444 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 445 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 446 #define ERIAR_MASK_SHIFT                12
 447 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 448 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 449 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 450 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 451         EPHY_RXER_NUM           = 0x7c,
 452         OCPDR                   = 0xb0, /* OCP GPHY access */
 453 #define OCPDR_WRITE_CMD                 0x80000000
 454 #define OCPDR_READ_CMD                  0x00000000
 455 #define OCPDR_REG_MASK                  0x7f
 456 #define OCPDR_GPHY_REG_SHIFT            16
 457 #define OCPDR_DATA_MASK                 0xffff
 458         OCPAR                   = 0xb4,
 459 #define OCPAR_FLAG                      0x80000000
 460 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 461 #define OCPAR_GPHY_READ_CMD             0x0000f060
 462         GPHY_OCP                = 0xb8,
 463         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 464         MISC                    = 0xf0, /* 8168e only. */
 465 #define TXPLA_RST                       (1 << 29)
 466 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 467 #define PWM_EN                          (1 << 22)
 468 #define RXDV_GATED_EN                   (1 << 19)
 469 #define EARLY_TALLY_EN                  (1 << 16)
 470 };
 471
 472 enum rtl_register_content {
 473         /* InterruptStatusBits */
 474         SYSErr          = 0x8000,
 475         PCSTimeout      = 0x4000,
 476         SWInt           = 0x0100,
 477         TxDescUnavail   = 0x0080,
 478         RxFIFOOver      = 0x0040,
 479         LinkChg         = 0x0020,
 480         RxOverflow      = 0x0010,
 481         TxErr           = 0x0008,
 482         TxOK            = 0x0004,
 483         RxErr           = 0x0002,
 484         RxOK            = 0x0001,
 485
 486         /* RxStatusDesc */
 487         RxBOVF  = (1 << 24),
 488         RxFOVF  = (1 << 23),
 489         RxRWT   = (1 << 22),
 490         RxRES   = (1 << 21),
 491         RxRUNT  = (1 << 20),
 492         RxCRC   = (1 << 19),
 493
 494         /* ChipCmdBits */
 495         StopReq         = 0x80,
 496         CmdReset        = 0x10,
 497         CmdRxEnb        = 0x08,
 498         CmdTxEnb        = 0x04,
 499         RxBufEmpty      = 0x01,
 500
 501         /* TXPoll register p.5 */
 502         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 503         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 504         FSWInt          = 0x01,         /* Forced software interrupt */
 505
 506         /* Cfg9346Bits */
 507         Cfg9346_Lock    = 0x00,
 508         Cfg9346_Unlock  = 0xc0,
 509
 510         /* rx_mode_bits */
 511         AcceptErr       = 0x20,
 512         AcceptRunt      = 0x10,
 513         AcceptBroadcast = 0x08,
 514         AcceptMulticast = 0x04,
 515         AcceptMyPhys    = 0x02,
 516         AcceptAllPhys   = 0x01,
 517 #define RX_CONFIG_ACCEPT_MASK           0x3f
 518
 519         /* TxConfigBits */
 520         TxInterFrameGapShift = 24,
 521         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 522
 523         /* Config1 register p.24 */
 524         LEDS1           = (1 << 7),
 525         LEDS0           = (1 << 6),
 526         Speed_down      = (1 << 4),
 527         MEMMAP          = (1 << 3),
 528         IOMAP           = (1 << 2),
 529         VPD             = (1 << 1),
 530         PMEnable        = (1 << 0),     /* Power Management Enable */
 531
 532         /* Config2 register p. 25 */
 533         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 534         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 535         PCI_Clock_66MHz = 0x01,
 536         PCI_Clock_33MHz = 0x00,
 537
 538         /* Config3 register p.25 */
 539         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 540         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 541         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 542         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 543
 544         /* Config4 register */
 545         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 546
 547         /* Config5 register p.27 */
 548         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 549         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 550         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 551         Spi_en          = (1 << 3),
 552         LanWake         = (1 << 1),     /* LanWake enable/disable */
 553         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 554         ASPM_en         = (1 << 0),     /* ASPM enable */
 555
 556         /* TBICSR p.28 */
 557         TBIReset        = 0x80000000,
 558         TBILoopback     = 0x40000000,
 559         TBINwEnable     = 0x20000000,
 560         TBINwRestart    = 0x10000000,
 561         TBILinkOk       = 0x02000000,
 562         TBINwComplete   = 0x01000000,
 563
 564         /* CPlusCmd p.31 */
 565         EnableBist      = (1 << 15),    // 8168 8101
 566         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 567         Normal_mode     = (1 << 13),    // unused
 568         Force_half_dup  = (1 << 12),    // 8168 8101
 569         Force_rxflow_en = (1 << 11),    // 8168 8101
 570         Force_txflow_en = (1 << 10),    // 8168 8101
 571         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 572         ASF             = (1 << 8),     // 8168 8101
 573         PktCntrDisable  = (1 << 7),     // 8168 8101
 574         Mac_dbgo_sel    = 0x001c,       // 8168
 575         RxVlan          = (1 << 6),
 576         RxChkSum        = (1 << 5),
 577         PCIDAC          = (1 << 4),
 578         PCIMulRW        = (1 << 3),
 579         INTT_0          = 0x0000,       // 8168
 580         INTT_1          = 0x0001,       // 8168
 581         INTT_2          = 0x0002,       // 8168
 582         INTT_3          = 0x0003,       // 8168
 583
 584         /* rtl8169_PHYstatus */
 585         TBI_Enable      = 0x80,
 586         TxFlowCtrl      = 0x40,
 587         RxFlowCtrl      = 0x20,
 588         _1000bpsF       = 0x10,
 589         _100bps         = 0x08,
 590         _10bps          = 0x04,
 591         LinkStatus      = 0x02,
 592         FullDup         = 0x01,
 593
 594         /* _TBICSRBit */
 595         TBILinkOK       = 0x02000000,
 596
 597         /* DumpCounterCommand */
 598         CounterDump     = 0x8,
 599 };
 600
 601 enum rtl_desc_bit {
 602         /* First doubleword. */
 603         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 604         RingEnd         = (1 << 30), /* End of descriptor ring */
 605         FirstFrag       = (1 << 29), /* First segment of a packet */
 606         LastFrag        = (1 << 28), /* Final segment of a packet */
 607 };
 608
 609 /* Generic case. */
 610 enum rtl_tx_desc_bit {
 611         /* First doubleword. */
 612         TD_LSO          = (1 << 27),            /* Large Send Offload */
 613 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 614
 615         /* Second doubleword. */
 616         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 617 };
 618
 619 /* 8169, 8168b and 810x except 8102e. */
 620 enum rtl_tx_desc_bit_0 {
 621         /* First doubleword. */
 622 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 623         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 624         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 625         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 626 };
 627
 628 /* 8102e, 8168c and beyond. */
 629 enum rtl_tx_desc_bit_1 {
 630         /* Second doubleword. */
 631 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 632         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 633         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 634         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 635 };
 636
 637 static const struct rtl_tx_desc_info {
 638         struct {
 639                 u32 udp;
 640                 u32 tcp;
 641         } checksum;
 642         u16 mss_shift;
 643         u16 opts_offset;
 644 } tx_desc_info [] = {
 645         [RTL_TD_0] = {
 646                 .checksum = {
 647                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 648                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 649                 },
 650                 .mss_shift      = TD0_MSS_SHIFT,
 651                 .opts_offset    = 0
 652         },
 653         [RTL_TD_1] = {
 654                 .checksum = {
 655                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 656                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 657                 },
 658                 .mss_shift      = TD1_MSS_SHIFT,
 659                 .opts_offset    = 1
 660         }
 661 };
 662
 663 enum rtl_rx_desc_bit {
 664         /* Rx private */
 665         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 666         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 667
 668 #define RxProtoUDP      (PID1)
 669 #define RxProtoTCP      (PID0)
 670 #define RxProtoIP       (PID1 | PID0)
 671 #define RxProtoMask     RxProtoIP
 672
 673         IPFail          = (1 << 16), /* IP checksum failed */
 674         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 675         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 676         RxVlanTag       = (1 << 16), /* VLAN tag available */
 677 };
 678
 679 #define RsvdMask        0x3fffc000
 680
 681 struct TxDesc {
 682         __le32 opts1;
 683         __le32 opts2;
 684         __le64 addr;
 685 };
 686
 687 struct RxDesc {
 688         __le32 opts1;
 689         __le32 opts2;
 690         __le64 addr;
 691 };
 692
 693 struct ring_info {
 694         struct sk_buff  *skb;
 695         u32             len;
 696         u8              __pad[sizeof(void *) - sizeof(u32)];
 697 };
 698
 699 enum features {
 700         RTL_FEATURE_WOL         = (1 << 0),
 701         RTL_FEATURE_MSI         = (1 << 1),
 702         RTL_FEATURE_GMII        = (1 << 2),
 703 };
 704
 705 struct rtl8169_counters {
 706         __le64  tx_packets;
 707         __le64  rx_packets;
 708         __le64  tx_errors;
 709         __le32  rx_errors;
 710         __le16  rx_missed;
 711         __le16  align_errors;
 712         __le32  tx_one_collision;
 713         __le32  tx_multi_collision;
 714         __le64  rx_unicast;
 715         __le64  rx_broadcast;
 716         __le32  rx_multicast;
 717         __le16  tx_aborted;
 718         __le16  tx_underun;
 719 };
 720
 721 enum rtl_flag {
 722         RTL_FLAG_TASK_ENABLED,
 723         RTL_FLAG_TASK_SLOW_PENDING,
 724         RTL_FLAG_TASK_RESET_PENDING,
 725         RTL_FLAG_TASK_PHY_PENDING,
 726         RTL_FLAG_MAX
 727 };
 728
 729 struct rtl8169_stats {
 730         u64                     packets;
 731         u64                     bytes;
 732         struct u64_stats_sync   syncp;
 733 };
 734
 735 struct rtl8169_private {
 736         void __iomem *mmio_addr;        /* memory map physical address */
 737         struct pci_dev *pci_dev;
 738         struct net_device *dev;
 739         struct napi_struct napi;
 740         u32 msg_enable;
 741         u16 txd_version;
 742         u16 mac_version;
 743         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 744         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 745         u32 dirty_tx;
 746         struct rtl8169_stats rx_stats;
 747         struct rtl8169_stats tx_stats;
 748         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 749         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 750         dma_addr_t TxPhyAddr;
 751         dma_addr_t RxPhyAddr;
 752         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 753         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 754         struct timer_list timer;
 755         u16 cp_cmd;
 756
 757         u16 event_slow;
 758
 759         struct mdio_ops {
 760                 void (*write)(struct rtl8169_private *, int, int);
 761                 int (*read)(struct rtl8169_private *, int);
 762         } mdio_ops;
 763
 764         struct pll_power_ops {
 765                 void (*down)(struct rtl8169_private *);
 766                 void (*up)(struct rtl8169_private *);
 767         } pll_power_ops;
 768
 769         struct jumbo_ops {
 770                 void (*enable)(struct rtl8169_private *);
 771                 void (*disable)(struct rtl8169_private *);
 772         } jumbo_ops;
 773
 774         struct csi_ops {
 775                 void (*write)(struct rtl8169_private *, int, int);
 776                 u32 (*read)(struct rtl8169_private *, int);
 777         } csi_ops;
 778
 779         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 780         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 781         void (*phy_reset_enable)(struct rtl8169_private *tp);
 782         void (*hw_start)(struct net_device *);
 783         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 784         unsigned int (*link_ok)(void __iomem *);
 785         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 786
 787         struct {
 788                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 789                 struct mutex mutex;
 790                 struct work_struct work;
 791         } wk;
 792
 793         unsigned features;
 794
 795         struct mii_if_info mii;
 796         struct rtl8169_counters counters;
 797         u32 saved_wolopts;
 798         u32 opts1_mask;
 799
 800         struct rtl_fw {
 801                 const struct firmware *fw;
 802
 803 #define RTL_VER_SIZE            32
 804
 805                 char version[RTL_VER_SIZE];
 806
 807                 struct rtl_fw_phy_action {
 808                         __le32 *code;
 809                         size_t size;
 810                 } phy_action;
 811         } *rtl_fw;
 812 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 813
 814         u32 ocp_base;
 815 };
 816
 817 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 818 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 819 module_param(use_dac, int, 0);
 820 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 821 module_param_named(debug, debug.msg_enable, int, 0);
 822 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 823 MODULE_LICENSE("GPL");
 824 MODULE_VERSION(RTL8169_VERSION);
 825 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 826 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 827 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 828 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 829 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 830 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 831 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 832 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 833 MODULE_FIRMWARE(FIRMWARE_8402_1);
 834 MODULE_FIRMWARE(FIRMWARE_8411_1);
 835 MODULE_FIRMWARE(FIRMWARE_8411_2);
 836 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 837 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 838 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 839 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 840
 841 static void rtl_lock_work(struct rtl8169_private *tp)
 842 {
 843         mutex_lock(&tp->wk.mutex);
 844 }
 845
 846 static void rtl_unlock_work(struct rtl8169_private *tp)
 847 {
 848         mutex_unlock(&tp->wk.mutex);
 849 }
 850
 851 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 852 {
 853         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 854                                            PCI_EXP_DEVCTL_READRQ, force);
 855 }
 856
 857 struct rtl_cond {
 858         bool (*check)(struct rtl8169_private *);
 859         const char *msg;
 860 };
 861
 862 static void rtl_udelay(unsigned int d)
 863 {
 864         udelay(d);
 865 }
 866
 867 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 868                           void (*delay)(unsigned int), unsigned int d, int n,
 869                           bool high)
 870 {
 871         int i;
 872
 873         for (i = 0; i < n; i++) {
 874                 delay(d);
 875                 if (c->check(tp) == high)
 876                         return true;
 877         }
 878         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 879                   c->msg, !high, n, d);
 880         return false;
 881 }
 882
 883 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 884                                       const struct rtl_cond *c,
 885                                       unsigned int d, int n)
 886 {
 887         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 888 }
 889
 890 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 891                                      const struct rtl_cond *c,
 892                                      unsigned int d, int n)
 893 {
 894         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 895 }
 896
 897 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 898                                       const struct rtl_cond *c,
 899                                       unsigned int d, int n)
 900 {
 901         return rtl_loop_wait(tp, c, msleep, d, n, true);
 902 }
 903
 904 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 905                                      const struct rtl_cond *c,
 906                                      unsigned int d, int n)
 907 {
 908         return rtl_loop_wait(tp, c, msleep, d, n, false);
 909 }
 910
 911 #define DECLARE_RTL_COND(name)                          \
 912 static bool name ## _check(struct rtl8169_private *);   \
 913                                                         \
 914 static const struct rtl_cond name = {                   \
 915         .check  = name ## _check,                       \
 916         .msg    = #name                                 \
 917 };                                                      \
 918                                                         \
 919 static bool name ## _check(struct rtl8169_private *tp)
 920
 921 DECLARE_RTL_COND(rtl_ocpar_cond)
 922 {
 923         void __iomem *ioaddr = tp->mmio_addr;
 924
 925         return RTL_R32(OCPAR) & OCPAR_FLAG;
 926 }
 927
 928 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 929 {
 930         void __iomem *ioaddr = tp->mmio_addr;
 931
 932         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 933
 934         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
 935                 RTL_R32(OCPDR) : ~0;
 936 }
 937
 938 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 939 {
 940         void __iomem *ioaddr = tp->mmio_addr;
 941
 942         RTL_W32(OCPDR, data);
 943         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 944
 945         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
 946 }
 947
 948 DECLARE_RTL_COND(rtl_eriar_cond)
 949 {
 950         void __iomem *ioaddr = tp->mmio_addr;
 951
 952         return RTL_R32(ERIAR) & ERIAR_FLAG;
 953 }
 954
 955 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 956 {
 957         void __iomem *ioaddr = tp->mmio_addr;
 958
 959         RTL_W8(ERIDR, cmd);
 960         RTL_W32(ERIAR, 0x800010e8);
 961         msleep(2);
 962
 963         if (!rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 5))
 964                 return;
 965
 966         ocp_write(tp, 0x1, 0x30, 0x00000001);
 967 }
 968
 969 #define OOB_CMD_RESET           0x00
 970 #define OOB_CMD_DRIVER_START    0x05
 971 #define OOB_CMD_DRIVER_STOP     0x06
 972
 973 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 974 {
 975         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 976 }
 977
 978 DECLARE_RTL_COND(rtl_ocp_read_cond)
 979 {
 980         u16 reg;
 981
 982         reg = rtl8168_get_ocp_reg(tp);
 983
 984         return ocp_read(tp, 0x0f, reg) & 0x00000800;
 985 }
 986
 987 static void rtl8168_driver_start(struct rtl8169_private *tp)
 988 {
 989         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 990
 991         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
 992 }
 993
 994 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 995 {
 996         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 997
 998         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
 999 }
1000
1001 static int r8168dp_check_dash(struct rtl8169_private *tp)
1002 {
1003         u16 reg = rtl8168_get_ocp_reg(tp);
1004
1005         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1006 }
1007
1008 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
1009 {
1010         if (reg & 0xffff0001) {
1011                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
1012                 return true;
1013         }
1014         return false;
1015 }
1016
1017 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1018 {
1019         void __iomem *ioaddr = tp->mmio_addr;
1020
1021         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
1022 }
1023
1024 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1025 {
1026         void __iomem *ioaddr = tp->mmio_addr;
1027
1028         if (rtl_ocp_reg_failure(tp, reg))
1029                 return;
1030
1031         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1032
1033         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1034 }
1035
1036 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1037 {
1038         void __iomem *ioaddr = tp->mmio_addr;
1039
1040         if (rtl_ocp_reg_failure(tp, reg))
1041                 return 0;
1042
1043         RTL_W32(GPHY_OCP, reg << 15);
1044
1045         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1046                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1047 }
1048
1049 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1050 {
1051         void __iomem *ioaddr = tp->mmio_addr;
1052
1053         if (rtl_ocp_reg_failure(tp, reg))
1054                 return;
1055
1056         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1057 }
1058
1059 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1060 {
1061         void __iomem *ioaddr = tp->mmio_addr;
1062
1063         if (rtl_ocp_reg_failure(tp, reg))
1064                 return 0;
1065
1066         RTL_W32(OCPDR, reg << 15);
1067
1068         return RTL_R32(OCPDR);
1069 }
1070
1071 #define OCP_STD_PHY_BASE        0xa400
1072
1073 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1074 {
1075         if (reg == 0x1f) {
1076                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1077                 return;
1078         }
1079
1080         if (tp->ocp_base != OCP_STD_PHY_BASE)
1081                 reg -= 0x10;
1082
1083         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1084 }
1085
1086 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1087 {
1088         if (tp->ocp_base != OCP_STD_PHY_BASE)
1089                 reg -= 0x10;
1090
1091         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1092 }
1093
1094 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1095 {
1096         if (reg == 0x1f) {
1097                 tp->ocp_base = value << 4;
1098                 return;
1099         }
1100
1101         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1102 }
1103
1104 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1105 {
1106         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1107 }
1108
1109 DECLARE_RTL_COND(rtl_phyar_cond)
1110 {
1111         void __iomem *ioaddr = tp->mmio_addr;
1112
1113         return RTL_R32(PHYAR) & 0x80000000;
1114 }
1115
1116 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1117 {
1118         void __iomem *ioaddr = tp->mmio_addr;
1119
1120         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1121
1122         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1123         /*
1124          * According to hardware specs a 20us delay is required after write
1125          * complete indication, but before sending next command.
1126          */
1127         udelay(20);
1128 }
1129
1130 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1131 {
1132         void __iomem *ioaddr = tp->mmio_addr;
1133         int value;
1134
1135         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1136
1137         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1138                 RTL_R32(PHYAR) & 0xffff : ~0;
1139
1140         /*
1141          * According to hardware specs a 20us delay is required after read
1142          * complete indication, but before sending next command.
1143          */
1144         udelay(20);
1145
1146         return value;
1147 }
1148
1149 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1150 {
1151         void __iomem *ioaddr = tp->mmio_addr;
1152
1153         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1154         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1155         RTL_W32(EPHY_RXER_NUM, 0);
1156
1157         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1158 }
1159
1160 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1161 {
1162         r8168dp_1_mdio_access(tp, reg,
1163                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1164 }
1165
1166 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1167 {
1168         void __iomem *ioaddr = tp->mmio_addr;
1169
1170         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1171
1172         mdelay(1);
1173         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1174         RTL_W32(EPHY_RXER_NUM, 0);
1175
1176         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1177                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1178 }
1179
1180 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1181
1182 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1183 {
1184         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1185 }
1186
1187 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1188 {
1189         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1190 }
1191
1192 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1193 {
1194         void __iomem *ioaddr = tp->mmio_addr;
1195
1196         r8168dp_2_mdio_start(ioaddr);
1197
1198         r8169_mdio_write(tp, reg, value);
1199
1200         r8168dp_2_mdio_stop(ioaddr);
1201 }
1202
1203 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1204 {
1205         void __iomem *ioaddr = tp->mmio_addr;
1206         int value;
1207
1208         r8168dp_2_mdio_start(ioaddr);
1209
1210         value = r8169_mdio_read(tp, reg);
1211
1212         r8168dp_2_mdio_stop(ioaddr);
1213
1214         return value;
1215 }
1216
1217 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1218 {
1219         tp->mdio_ops.write(tp, location, val);
1220 }
1221
1222 static int rtl_readphy(struct rtl8169_private *tp, int location)
1223 {
1224         return tp->mdio_ops.read(tp, location);
1225 }
1226
1227 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1228 {
1229         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1230 }
1231
1232 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1233 {
1234         int val;
1235
1236         val = rtl_readphy(tp, reg_addr);
1237         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1238 }
1239
1240 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1241                            int val)
1242 {
1243         struct rtl8169_private *tp = netdev_priv(dev);
1244
1245         rtl_writephy(tp, location, val);
1246 }
1247
1248 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1249 {
1250         struct rtl8169_private *tp = netdev_priv(dev);
1251
1252         return rtl_readphy(tp, location);
1253 }
1254
1255 DECLARE_RTL_COND(rtl_ephyar_cond)
1256 {
1257         void __iomem *ioaddr = tp->mmio_addr;
1258
1259         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1260 }
1261
1262 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1263 {
1264         void __iomem *ioaddr = tp->mmio_addr;
1265
1266         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1267                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1268
1269         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1270
1271         udelay(10);
1272 }
1273
1274 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1275 {
1276         void __iomem *ioaddr = tp->mmio_addr;
1277
1278         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1279
1280         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1281                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1282 }
1283
1284 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1285                           u32 val, int type)
1286 {
1287         void __iomem *ioaddr = tp->mmio_addr;
1288
1289         BUG_ON((addr & 3) || (mask == 0));
1290         RTL_W32(ERIDR, val);
1291         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1292
1293         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1294 }
1295
1296 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1297 {
1298         void __iomem *ioaddr = tp->mmio_addr;
1299
1300         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1301
1302         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1303                 RTL_R32(ERIDR) : ~0;
1304 }
1305
1306 static void rtl_w1w0_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1307                          u32 m, int type)
1308 {
1309         u32 val;
1310
1311         val = rtl_eri_read(tp, addr, type);
1312         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1313 }
1314
1315 struct exgmac_reg {
1316         u16 addr;
1317         u16 mask;
1318         u32 val;
1319 };
1320
1321 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1322                                    const struct exgmac_reg *r, int len)
1323 {
1324         while (len-- > 0) {
1325                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1326                 r++;
1327         }
1328 }
1329
1330 DECLARE_RTL_COND(rtl_efusear_cond)
1331 {
1332         void __iomem *ioaddr = tp->mmio_addr;
1333
1334         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1335 }
1336
1337 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1338 {
1339         void __iomem *ioaddr = tp->mmio_addr;
1340
1341         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1342
1343         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1344                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1345 }
1346
1347 static u16 rtl_get_events(struct rtl8169_private *tp)
1348 {
1349         void __iomem *ioaddr = tp->mmio_addr;
1350
1351         return RTL_R16(IntrStatus);
1352 }
1353
1354 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1355 {
1356         void __iomem *ioaddr = tp->mmio_addr;
1357
1358         RTL_W16(IntrStatus, bits);
1359         mmiowb();
1360 }
1361
1362 static void rtl_irq_disable(struct rtl8169_private *tp)
1363 {
1364         void __iomem *ioaddr = tp->mmio_addr;
1365
1366         RTL_W16(IntrMask, 0);
1367         mmiowb();
1368 }
1369
1370 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1371 {
1372         void __iomem *ioaddr = tp->mmio_addr;
1373
1374         RTL_W16(IntrMask, bits);
1375 }
1376
1377 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1378 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1379 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1380
1381 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1382 {
1383         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1384 }
1385
1386 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1387 {
1388         void __iomem *ioaddr = tp->mmio_addr;
1389
1390         rtl_irq_disable(tp);
1391         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1392         RTL_R8(ChipCmd);
1393 }
1394
1395 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1396 {
1397         void __iomem *ioaddr = tp->mmio_addr;
1398
1399         return RTL_R32(TBICSR) & TBIReset;
1400 }
1401
1402 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1403 {
1404         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1405 }
1406
1407 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1408 {
1409         return RTL_R32(TBICSR) & TBILinkOk;
1410 }
1411
1412 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1413 {
1414         return RTL_R8(PHYstatus) & LinkStatus;
1415 }
1416
1417 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1418 {
1419         void __iomem *ioaddr = tp->mmio_addr;
1420
1421         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1422 }
1423
1424 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1425 {
1426         unsigned int val;
1427
1428         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1429         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1430 }
1431
1432 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1433 {
1434         void __iomem *ioaddr = tp->mmio_addr;
1435         struct net_device *dev = tp->dev;
1436
1437         if (!netif_running(dev))
1438                 return;
1439
1440         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1441             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1442                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1443                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1444                                       ERIAR_EXGMAC);
1445                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1446                                       ERIAR_EXGMAC);
1447                 } else if (RTL_R8(PHYstatus) & _100bps) {
1448                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1449                                       ERIAR_EXGMAC);
1450                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1451                                       ERIAR_EXGMAC);
1452                 } else {
1453                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1454                                       ERIAR_EXGMAC);
1455                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1456                                       ERIAR_EXGMAC);
1457                 }
1458                 /* Reset packet filter */
1459                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1460                              ERIAR_EXGMAC);
1461                 rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1462                              ERIAR_EXGMAC);
1463         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1464                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1465                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1466                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1467                                       ERIAR_EXGMAC);
1468                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1469                                       ERIAR_EXGMAC);
1470                 } else {
1471                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1472                                       ERIAR_EXGMAC);
1473                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1474                                       ERIAR_EXGMAC);
1475                 }
1476         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1477                 if (RTL_R8(PHYstatus) & _10bps) {
1478                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1479                                       ERIAR_EXGMAC);
1480                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1481                                       ERIAR_EXGMAC);
1482                 } else {
1483                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1484                                       ERIAR_EXGMAC);
1485                 }
1486         }
1487 }
1488
1489 static void __rtl8169_check_link_status(struct net_device *dev,
1490                                         struct rtl8169_private *tp,
1491                                         void __iomem *ioaddr, bool pm)
1492 {
1493         if (tp->link_ok(ioaddr)) {
1494                 rtl_link_chg_patch(tp);
1495                 /* This is to cancel a scheduled suspend if there's one. */
1496                 if (pm)
1497                         pm_request_resume(&tp->pci_dev->dev);
1498                 netif_carrier_on(dev);
1499                 if (net_ratelimit())
1500                         netif_info(tp, ifup, dev, "link up\n");
1501         } else {
1502                 netif_carrier_off(dev);
1503                 netif_info(tp, ifdown, dev, "link down\n");
1504                 if (pm)
1505                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1506         }
1507 }
1508
1509 static void rtl8169_check_link_status(struct net_device *dev,
1510                                       struct rtl8169_private *tp,
1511                                       void __iomem *ioaddr)
1512 {
1513         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1514 }
1515
1516 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1517
1518 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1519 {
1520         void __iomem *ioaddr = tp->mmio_addr;
1521         u8 options;
1522         u32 wolopts = 0;
1523
1524         options = RTL_R8(Config1);
1525         if (!(options & PMEnable))
1526                 return 0;
1527
1528         options = RTL_R8(Config3);
1529         if (options & LinkUp)
1530                 wolopts |= WAKE_PHY;
1531         if (options & MagicPacket)
1532                 wolopts |= WAKE_MAGIC;
1533
1534         options = RTL_R8(Config5);
1535         if (options & UWF)
1536                 wolopts |= WAKE_UCAST;
1537         if (options & BWF)
1538                 wolopts |= WAKE_BCAST;
1539         if (options & MWF)
1540                 wolopts |= WAKE_MCAST;
1541
1542         return wolopts;
1543 }
1544
1545 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1546 {
1547         struct rtl8169_private *tp = netdev_priv(dev);
1548
1549         rtl_lock_work(tp);
1550
1551         wol->supported = WAKE_ANY;
1552         wol->wolopts = __rtl8169_get_wol(tp);
1553
1554         rtl_unlock_work(tp);
1555 }
1556
1557 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1558 {
1559         void __iomem *ioaddr = tp->mmio_addr;
1560         unsigned int i;
1561         static const struct {
1562                 u32 opt;
1563                 u16 reg;
1564                 u8  mask;
1565         } cfg[] = {
1566                 { WAKE_PHY,   Config3, LinkUp },
1567                 { WAKE_MAGIC, Config3, MagicPacket },
1568                 { WAKE_UCAST, Config5, UWF },
1569                 { WAKE_BCAST, Config5, BWF },
1570                 { WAKE_MCAST, Config5, MWF },
1571                 { WAKE_ANY,   Config5, LanWake }
1572         };
1573         u8 options;
1574
1575         RTL_W8(Cfg9346, Cfg9346_Unlock);
1576
1577         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1578                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1579                 if (wolopts & cfg[i].opt)
1580                         options |= cfg[i].mask;
1581                 RTL_W8(cfg[i].reg, options);
1582         }
1583
1584         switch (tp->mac_version) {
1585         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1586                 options = RTL_R8(Config1) & ~PMEnable;
1587                 if (wolopts)
1588                         options |= PMEnable;
1589                 RTL_W8(Config1, options);
1590                 break;
1591         default:
1592                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1593                 if (wolopts)
1594                         options |= PME_SIGNAL;
1595                 RTL_W8(Config2, options);
1596                 break;
1597         }
1598
1599         RTL_W8(Cfg9346, Cfg9346_Lock);
1600 }
1601
1602 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1603 {
1604         struct rtl8169_private *tp = netdev_priv(dev);
1605
1606         rtl_lock_work(tp);
1607
1608         if (wol->wolopts)
1609                 tp->features |= RTL_FEATURE_WOL;
1610         else
1611                 tp->features &= ~RTL_FEATURE_WOL;
1612         __rtl8169_set_wol(tp, wol->wolopts);
1613
1614         rtl_unlock_work(tp);
1615
1616         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1617
1618         return 0;
1619 }
1620
1621 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1622 {
1623         return rtl_chip_infos[tp->mac_version].fw_name;
1624 }
1625
1626 static void rtl8169_get_drvinfo(struct net_device *dev,
1627                                 struct ethtool_drvinfo *info)
1628 {
1629         struct rtl8169_private *tp = netdev_priv(dev);
1630         struct rtl_fw *rtl_fw = tp->rtl_fw;
1631
1632         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1633         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1634         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1635         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1636         if (!IS_ERR_OR_NULL(rtl_fw))
1637                 strlcpy(info->fw_version, rtl_fw->version,
1638                         sizeof(info->fw_version));
1639 }
1640
1641 static int rtl8169_get_regs_len(struct net_device *dev)
1642 {
1643         return R8169_REGS_SIZE;
1644 }
1645
1646 static int rtl8169_set_speed_tbi(struct net_device *dev,
1647                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1648 {
1649         struct rtl8169_private *tp = netdev_priv(dev);
1650         void __iomem *ioaddr = tp->mmio_addr;
1651         int ret = 0;
1652         u32 reg;
1653
1654         reg = RTL_R32(TBICSR);
1655         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1656             (duplex == DUPLEX_FULL)) {
1657                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1658         } else if (autoneg == AUTONEG_ENABLE)
1659                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1660         else {
1661                 netif_warn(tp, link, dev,
1662                            "incorrect speed setting refused in TBI mode\n");
1663                 ret = -EOPNOTSUPP;
1664         }
1665
1666         return ret;
1667 }
1668
1669 static int rtl8169_set_speed_xmii(struct net_device *dev,
1670                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1671 {
1672         struct rtl8169_private *tp = netdev_priv(dev);
1673         int giga_ctrl, bmcr;
1674         int rc = -EINVAL;
1675
1676         rtl_writephy(tp, 0x1f, 0x0000);
1677
1678         if (autoneg == AUTONEG_ENABLE) {
1679                 int auto_nego;
1680
1681                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1682                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1683                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1684
1685                 if (adv & ADVERTISED_10baseT_Half)
1686                         auto_nego |= ADVERTISE_10HALF;
1687                 if (adv & ADVERTISED_10baseT_Full)
1688                         auto_nego |= ADVERTISE_10FULL;
1689                 if (adv & ADVERTISED_100baseT_Half)
1690                         auto_nego |= ADVERTISE_100HALF;
1691                 if (adv & ADVERTISED_100baseT_Full)
1692                         auto_nego |= ADVERTISE_100FULL;
1693
1694                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1695
1696                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1697                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1698
1699                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1700                 if (tp->mii.supports_gmii) {
1701                         if (adv & ADVERTISED_1000baseT_Half)
1702                                 giga_ctrl |= ADVERTISE_1000HALF;
1703                         if (adv & ADVERTISED_1000baseT_Full)
1704                                 giga_ctrl |= ADVERTISE_1000FULL;
1705                 } else if (adv & (ADVERTISED_1000baseT_Half |
1706                                   ADVERTISED_1000baseT_Full)) {
1707                         netif_info(tp, link, dev,
1708                                    "PHY does not support 1000Mbps\n");
1709                         goto out;
1710                 }
1711
1712                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1713
1714                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1715                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1716         } else {
1717                 giga_ctrl = 0;
1718
1719                 if (speed == SPEED_10)
1720                         bmcr = 0;
1721                 else if (speed == SPEED_100)
1722                         bmcr = BMCR_SPEED100;
1723                 else
1724                         goto out;
1725
1726                 if (duplex == DUPLEX_FULL)
1727                         bmcr |= BMCR_FULLDPLX;
1728         }
1729
1730         rtl_writephy(tp, MII_BMCR, bmcr);
1731
1732         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1733             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1734                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1735                         rtl_writephy(tp, 0x17, 0x2138);
1736                         rtl_writephy(tp, 0x0e, 0x0260);
1737                 } else {
1738                         rtl_writephy(tp, 0x17, 0x2108);
1739                         rtl_writephy(tp, 0x0e, 0x0000);
1740                 }
1741         }
1742
1743         rc = 0;
1744 out:
1745         return rc;
1746 }
1747
1748 static int rtl8169_set_speed(struct net_device *dev,
1749                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1750 {
1751         struct rtl8169_private *tp = netdev_priv(dev);
1752         int ret;
1753
1754         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1755         if (ret < 0)
1756                 goto out;
1757
1758         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1759             (advertising & ADVERTISED_1000baseT_Full)) {
1760                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1761         }
1762 out:
1763         return ret;
1764 }
1765
1766 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1767 {
1768         struct rtl8169_private *tp = netdev_priv(dev);
1769         int ret;
1770
1771         del_timer_sync(&tp->timer);
1772
1773         rtl_lock_work(tp);
1774         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1775                                 cmd->duplex, cmd->advertising);
1776         rtl_unlock_work(tp);
1777
1778         return ret;
1779 }
1780
1781 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1782         netdev_features_t features)
1783 {
1784         struct rtl8169_private *tp = netdev_priv(dev);
1785
1786         if (dev->mtu > TD_MSS_MAX)
1787                 features &= ~NETIF_F_ALL_TSO;
1788
1789         if (dev->mtu > JUMBO_1K &&
1790             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1791                 features &= ~NETIF_F_IP_CSUM;
1792
1793         return features;
1794 }
1795
1796 static void __rtl8169_set_features(struct net_device *dev,
1797                                    netdev_features_t features)
1798 {
1799         struct rtl8169_private *tp = netdev_priv(dev);
1800         netdev_features_t changed = features ^ dev->features;
1801         void __iomem *ioaddr = tp->mmio_addr;
1802
1803         if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
1804                          NETIF_F_HW_VLAN_CTAG_RX)))
1805                 return;
1806
1807         if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
1808                 if (features & NETIF_F_RXCSUM)
1809                         tp->cp_cmd |= RxChkSum;
1810                 else
1811                         tp->cp_cmd &= ~RxChkSum;
1812
1813                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
1814                         tp->cp_cmd |= RxVlan;
1815                 else
1816                         tp->cp_cmd &= ~RxVlan;
1817
1818                 RTL_W16(CPlusCmd, tp->cp_cmd);
1819                 RTL_R16(CPlusCmd);
1820         }
1821         if (changed & NETIF_F_RXALL) {
1822                 int tmp = (RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt));
1823                 if (features & NETIF_F_RXALL)
1824                         tmp |= (AcceptErr | AcceptRunt);
1825                 RTL_W32(RxConfig, tmp);
1826         }
1827 }
1828
1829 static int rtl8169_set_features(struct net_device *dev,
1830                                 netdev_features_t features)
1831 {
1832         struct rtl8169_private *tp = netdev_priv(dev);
1833
1834         rtl_lock_work(tp);
1835         __rtl8169_set_features(dev, features);
1836         rtl_unlock_work(tp);
1837
1838         return 0;
1839 }
1840
1841
1842 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1843 {
1844         return (vlan_tx_tag_present(skb)) ?
1845                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1846 }
1847
1848 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1849 {
1850         u32 opts2 = le32_to_cpu(desc->opts2);
1851
1852         if (opts2 & RxVlanTag)
1853                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1854 }
1855
1856 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1857 {
1858         struct rtl8169_private *tp = netdev_priv(dev);
1859         void __iomem *ioaddr = tp->mmio_addr;
1860         u32 status;
1861
1862         cmd->supported =
1863                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1864         cmd->port = PORT_FIBRE;
1865         cmd->transceiver = XCVR_INTERNAL;
1866
1867         status = RTL_R32(TBICSR);
1868         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1869         cmd->autoneg = !!(status & TBINwEnable);
1870
1871         ethtool_cmd_speed_set(cmd, SPEED_1000);
1872         cmd->duplex = DUPLEX_FULL; /* Always set */
1873
1874         return 0;
1875 }
1876
1877 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1878 {
1879         struct rtl8169_private *tp = netdev_priv(dev);
1880
1881         return mii_ethtool_gset(&tp->mii, cmd);
1882 }
1883
1884 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1885 {
1886         struct rtl8169_private *tp = netdev_priv(dev);
1887         int rc;
1888
1889         rtl_lock_work(tp);
1890         rc = tp->get_settings(dev, cmd);
1891         rtl_unlock_work(tp);
1892
1893         return rc;
1894 }
1895
1896 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1897                              void *p)
1898 {
1899         struct rtl8169_private *tp = netdev_priv(dev);
1900
1901         if (regs->len > R8169_REGS_SIZE)
1902                 regs->len = R8169_REGS_SIZE;
1903
1904         rtl_lock_work(tp);
1905         memcpy_fromio(p, tp->mmio_addr, regs->len);
1906         rtl_unlock_work(tp);
1907 }
1908
1909 static u32 rtl8169_get_msglevel(struct net_device *dev)
1910 {
1911         struct rtl8169_private *tp = netdev_priv(dev);
1912
1913         return tp->msg_enable;
1914 }
1915
1916 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1917 {
1918         struct rtl8169_private *tp = netdev_priv(dev);
1919
1920         tp->msg_enable = value;
1921 }
1922
1923 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1924         "tx_packets",
1925         "rx_packets",
1926         "tx_errors",
1927         "rx_errors",
1928         "rx_missed",
1929         "align_errors",
1930         "tx_single_collisions",
1931         "tx_multi_collisions",
1932         "unicast",
1933         "broadcast",
1934         "multicast",
1935         "tx_aborted",
1936         "tx_underrun",
1937 };
1938
1939 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1940 {
1941         switch (sset) {
1942         case ETH_SS_STATS:
1943                 return ARRAY_SIZE(rtl8169_gstrings);
1944         default:
1945                 return -EOPNOTSUPP;
1946         }
1947 }
1948
1949 DECLARE_RTL_COND(rtl_counters_cond)
1950 {
1951         void __iomem *ioaddr = tp->mmio_addr;
1952
1953         return RTL_R32(CounterAddrLow) & CounterDump;
1954 }
1955
1956 static void rtl8169_update_counters(struct net_device *dev)
1957 {
1958         struct rtl8169_private *tp = netdev_priv(dev);
1959         void __iomem *ioaddr = tp->mmio_addr;
1960         struct device *d = &tp->pci_dev->dev;
1961         struct rtl8169_counters *counters;
1962         dma_addr_t paddr;
1963         u32 cmd;
1964
1965         /*
1966          * Some chips are unable to dump tally counters when the receiver
1967          * is disabled.
1968          */
1969         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1970                 return;
1971
1972         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1973         if (!counters)
1974                 return;
1975
1976         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1977         cmd = (u64)paddr & DMA_BIT_MASK(32);
1978         RTL_W32(CounterAddrLow, cmd);
1979         RTL_W32(CounterAddrLow, cmd | CounterDump);
1980
1981         if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
1982                 memcpy(&tp->counters, counters, sizeof(*counters));
1983
1984         RTL_W32(CounterAddrLow, 0);
1985         RTL_W32(CounterAddrHigh, 0);
1986
1987         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1988 }
1989
1990 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1991                                       struct ethtool_stats *stats, u64 *data)
1992 {
1993         struct rtl8169_private *tp = netdev_priv(dev);
1994
1995         ASSERT_RTNL();
1996
1997         rtl8169_update_counters(dev);
1998
1999         data[0] = le64_to_cpu(tp->counters.tx_packets);
2000         data[1] = le64_to_cpu(tp->counters.rx_packets);
2001         data[2] = le64_to_cpu(tp->counters.tx_errors);
2002         data[3] = le32_to_cpu(tp->counters.rx_errors);
2003         data[4] = le16_to_cpu(tp->counters.rx_missed);
2004         data[5] = le16_to_cpu(tp->counters.align_errors);
2005         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2006         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2007         data[8] = le64_to_cpu(tp->counters.rx_unicast);
2008         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2009         data[10] = le32_to_cpu(tp->counters.rx_multicast);
2010         data[11] = le16_to_cpu(tp->counters.tx_aborted);
2011         data[12] = le16_to_cpu(tp->counters.tx_underun);
2012 }
2013
2014 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2015 {
2016         switch(stringset) {
2017         case ETH_SS_STATS:
2018                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2019                 break;
2020         }
2021 }
2022
2023 static const struct ethtool_ops rtl8169_ethtool_ops = {
2024         .get_drvinfo            = rtl8169_get_drvinfo,
2025         .get_regs_len           = rtl8169_get_regs_len,
2026         .get_link               = ethtool_op_get_link,
2027         .get_settings           = rtl8169_get_settings,
2028         .set_settings           = rtl8169_set_settings,
2029         .get_msglevel           = rtl8169_get_msglevel,
2030         .set_msglevel           = rtl8169_set_msglevel,
2031         .get_regs               = rtl8169_get_regs,
2032         .get_wol                = rtl8169_get_wol,
2033         .set_wol                = rtl8169_set_wol,
2034         .get_strings            = rtl8169_get_strings,
2035         .get_sset_count         = rtl8169_get_sset_count,
2036         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2037         .get_ts_info            = ethtool_op_get_ts_info,
2038 };
2039
2040 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2041                                     struct net_device *dev, u8 default_version)
2042 {
2043         void __iomem *ioaddr = tp->mmio_addr;
2044         /*
2045          * The driver currently handles the 8168Bf and the 8168Be identically
2046          * but they can be identified more specifically through the test below
2047          * if needed:
2048          *
2049          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2050          *
2051          * Same thing for the 8101Eb and the 8101Ec:
2052          *
2053          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2054          */
2055         static const struct rtl_mac_info {
2056                 u32 mask;
2057                 u32 val;
2058                 int mac_version;
2059         } mac_info[] = {
2060                 /* 8168G family. */
2061                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2062                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2063                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2064                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2065
2066                 /* 8168F family. */
2067                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2068                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2069                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2070
2071                 /* 8168E family. */
2072                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2073                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2074                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2075                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2076
2077                 /* 8168D family. */
2078                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2079                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2080                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2081
2082                 /* 8168DP family. */
2083                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2084                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2085                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2086
2087                 /* 8168C family. */
2088                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2089                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2090                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2091                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2092                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2093                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2094                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2095                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2096                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2097
2098                 /* 8168B family. */
2099                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2100                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2101                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2102                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2103
2104                 /* 8101 family. */
2105                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2106                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2107                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2108                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2109                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2110                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2111                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2112                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2113                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2114                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2115                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2116                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2117                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2118                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2119                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2120                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2121                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2122                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2123                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2124                 /* FIXME: where did these entries come from ? -- FR */
2125                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2126                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2127
2128                 /* 8110 family. */
2129                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2130                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2131                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2132                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2133                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2134                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2135
2136                 /* Catch-all */
2137                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2138         };
2139         const struct rtl_mac_info *p = mac_info;
2140         u32 reg;
2141
2142         reg = RTL_R32(TxConfig);
2143         while ((reg & p->mask) != p->val)
2144                 p++;
2145         tp->mac_version = p->mac_version;
2146
2147         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2148                 netif_notice(tp, probe, dev,
2149                              "unknown MAC, using family default\n");
2150                 tp->mac_version = default_version;
2151         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2152                 tp->mac_version = tp->mii.supports_gmii ?
2153                                   RTL_GIGA_MAC_VER_42 :
2154                                   RTL_GIGA_MAC_VER_43;
2155         }
2156 }
2157
2158 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2159 {
2160         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2161 }
2162
2163 struct phy_reg {
2164         u16 reg;
2165         u16 val;
2166 };
2167
2168 static void rtl_writephy_batch(struct rtl8169_private *tp,
2169                                const struct phy_reg *regs, int len)
2170 {
2171         while (len-- > 0) {
2172                 rtl_writephy(tp, regs->reg, regs->val);
2173                 regs++;
2174         }
2175 }
2176
2177 #define PHY_READ                0x00000000
2178 #define PHY_DATA_OR             0x10000000
2179 #define PHY_DATA_AND            0x20000000
2180 #define PHY_BJMPN               0x30000000
2181 #define PHY_MDIO_CHG            0x40000000
2182 #define PHY_CLEAR_READCOUNT     0x70000000
2183 #define PHY_WRITE               0x80000000
2184 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2185 #define PHY_COMP_EQ_SKIPN       0xa0000000
2186 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2187 #define PHY_WRITE_PREVIOUS      0xc0000000
2188 #define PHY_SKIPN               0xd0000000
2189 #define PHY_DELAY_MS            0xe0000000
2190
2191 struct fw_info {
2192         u32     magic;
2193         char    version[RTL_VER_SIZE];
2194         __le32  fw_start;
2195         __le32  fw_len;
2196         u8      chksum;
2197 } __packed;
2198
2199 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2200
2201 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2202 {
2203         const struct firmware *fw = rtl_fw->fw;
2204         struct fw_info *fw_info = (struct fw_info *)fw->data;
2205         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2206         char *version = rtl_fw->version;
2207         bool rc = false;
2208
2209         if (fw->size < FW_OPCODE_SIZE)
2210                 goto out;
2211
2212         if (!fw_info->magic) {
2213                 size_t i, size, start;
2214                 u8 checksum = 0;
2215
2216                 if (fw->size < sizeof(*fw_info))
2217                         goto out;
2218
2219                 for (i = 0; i < fw->size; i++)
2220                         checksum += fw->data[i];
2221                 if (checksum != 0)
2222                         goto out;
2223
2224                 start = le32_to_cpu(fw_info->fw_start);
2225                 if (start > fw->size)
2226                         goto out;
2227
2228                 size = le32_to_cpu(fw_info->fw_len);
2229                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2230                         goto out;
2231
2232                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2233
2234                 pa->code = (__le32 *)(fw->data + start);
2235                 pa->size = size;
2236         } else {
2237                 if (fw->size % FW_OPCODE_SIZE)
2238                         goto out;
2239
2240                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2241
2242                 pa->code = (__le32 *)fw->data;
2243                 pa->size = fw->size / FW_OPCODE_SIZE;
2244         }
2245         version[RTL_VER_SIZE - 1] = 0;
2246
2247         rc = true;
2248 out:
2249         return rc;
2250 }
2251
2252 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2253                            struct rtl_fw_phy_action *pa)
2254 {
2255         bool rc = false;
2256         size_t index;
2257
2258         for (index = 0; index < pa->size; index++) {
2259                 u32 action = le32_to_cpu(pa->code[index]);
2260                 u32 regno = (action & 0x0fff0000) >> 16;
2261
2262                 switch(action & 0xf0000000) {
2263                 case PHY_READ:
2264                 case PHY_DATA_OR:
2265                 case PHY_DATA_AND:
2266                 case PHY_MDIO_CHG:
2267                 case PHY_CLEAR_READCOUNT:
2268                 case PHY_WRITE:
2269                 case PHY_WRITE_PREVIOUS:
2270                 case PHY_DELAY_MS:
2271                         break;
2272
2273                 case PHY_BJMPN:
2274                         if (regno > index) {
2275                                 netif_err(tp, ifup, tp->dev,
2276                                           "Out of range of firmware\n");
2277                                 goto out;
2278                         }
2279                         break;
2280                 case PHY_READCOUNT_EQ_SKIP:
2281                         if (index + 2 >= pa->size) {
2282                                 netif_err(tp, ifup, tp->dev,
2283                                           "Out of range of firmware\n");
2284                                 goto out;
2285                         }
2286                         break;
2287                 case PHY_COMP_EQ_SKIPN:
2288                 case PHY_COMP_NEQ_SKIPN:
2289                 case PHY_SKIPN:
2290                         if (index + 1 + regno >= pa->size) {
2291                                 netif_err(tp, ifup, tp->dev,
2292                                           "Out of range of firmware\n");
2293                                 goto out;
2294                         }
2295                         break;
2296
2297                 default:
2298                         netif_err(tp, ifup, tp->dev,
2299                                   "Invalid action 0x%08x\n", action);
2300                         goto out;
2301                 }
2302         }
2303         rc = true;
2304 out:
2305         return rc;
2306 }
2307
2308 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2309 {
2310         struct net_device *dev = tp->dev;
2311         int rc = -EINVAL;
2312
2313         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2314                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2315                 goto out;
2316         }
2317
2318         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2319                 rc = 0;
2320 out:
2321         return rc;
2322 }
2323
2324 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2325 {
2326         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2327         struct mdio_ops org, *ops = &tp->mdio_ops;
2328         u32 predata, count;
2329         size_t index;
2330
2331         predata = count = 0;
2332         org.write = ops->write;
2333         org.read = ops->read;
2334
2335         for (index = 0; index < pa->size; ) {
2336                 u32 action = le32_to_cpu(pa->code[index]);
2337                 u32 data = action & 0x0000ffff;
2338                 u32 regno = (action & 0x0fff0000) >> 16;
2339
2340                 if (!action)
2341                         break;
2342
2343                 switch(action & 0xf0000000) {
2344                 case PHY_READ:
2345                         predata = rtl_readphy(tp, regno);
2346                         count++;
2347                         index++;
2348                         break;
2349                 case PHY_DATA_OR:
2350                         predata |= data;
2351                         index++;
2352                         break;
2353                 case PHY_DATA_AND:
2354                         predata &= data;
2355                         index++;
2356                         break;
2357                 case PHY_BJMPN:
2358                         index -= regno;
2359                         break;
2360                 case PHY_MDIO_CHG:
2361                         if (data == 0) {
2362                                 ops->write = org.write;
2363                                 ops->read = org.read;
2364                         } else if (data == 1) {
2365                                 ops->write = mac_mcu_write;
2366                                 ops->read = mac_mcu_read;
2367                         }
2368
2369                         index++;
2370                         break;
2371                 case PHY_CLEAR_READCOUNT:
2372                         count = 0;
2373                         index++;
2374                         break;
2375                 case PHY_WRITE:
2376                         rtl_writephy(tp, regno, data);
2377                         index++;
2378                         break;
2379                 case PHY_READCOUNT_EQ_SKIP:
2380                         index += (count == data) ? 2 : 1;
2381                         break;
2382                 case PHY_COMP_EQ_SKIPN:
2383                         if (predata == data)
2384                                 index += regno;
2385                         index++;
2386                         break;
2387                 case PHY_COMP_NEQ_SKIPN:
2388                         if (predata != data)
2389                                 index += regno;
2390                         index++;
2391                         break;
2392                 case PHY_WRITE_PREVIOUS:
2393                         rtl_writephy(tp, regno, predata);
2394                         index++;
2395                         break;
2396                 case PHY_SKIPN:
2397                         index += regno + 1;
2398                         break;
2399                 case PHY_DELAY_MS:
2400                         mdelay(data);
2401                         index++;
2402                         break;
2403
2404                 default:
2405                         BUG();
2406                 }
2407         }
2408
2409         ops->write = org.write;
2410         ops->read = org.read;
2411 }
2412
2413 static void rtl_release_firmware(struct rtl8169_private *tp)
2414 {
2415         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2416                 release_firmware(tp->rtl_fw->fw);
2417                 kfree(tp->rtl_fw);
2418         }
2419         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2420 }
2421
2422 static void rtl_apply_firmware(struct rtl8169_private *tp)
2423 {
2424         struct rtl_fw *rtl_fw = tp->rtl_fw;
2425
2426         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2427         if (!IS_ERR_OR_NULL(rtl_fw))
2428                 rtl_phy_write_fw(tp, rtl_fw);
2429 }
2430
2431 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2432 {
2433         if (rtl_readphy(tp, reg) != val)
2434                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2435         else
2436                 rtl_apply_firmware(tp);
2437 }
2438
2439 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2440 {
2441         static const struct phy_reg phy_reg_init[] = {
2442                 { 0x1f, 0x0001 },
2443                 { 0x06, 0x006e },
2444                 { 0x08, 0x0708 },
2445                 { 0x15, 0x4000 },
2446                 { 0x18, 0x65c7 },
2447
2448                 { 0x1f, 0x0001 },
2449                 { 0x03, 0x00a1 },
2450                 { 0x02, 0x0008 },
2451                 { 0x01, 0x0120 },
2452                 { 0x00, 0x1000 },
2453                 { 0x04, 0x0800 },
2454                 { 0x04, 0x0000 },
2455
2456                 { 0x03, 0xff41 },
2457                 { 0x02, 0xdf60 },
2458                 { 0x01, 0x0140 },
2459                 { 0x00, 0x0077 },
2460                 { 0x04, 0x7800 },
2461                 { 0x04, 0x7000 },
2462
2463                 { 0x03, 0x802f },
2464                 { 0x02, 0x4f02 },
2465                 { 0x01, 0x0409 },
2466                 { 0x00, 0xf0f9 },
2467                 { 0x04, 0x9800 },
2468                 { 0x04, 0x9000 },
2469
2470                 { 0x03, 0xdf01 },
2471                 { 0x02, 0xdf20 },
2472                 { 0x01, 0xff95 },
2473                 { 0x00, 0xba00 },
2474                 { 0x04, 0xa800 },
2475                 { 0x04, 0xa000 },
2476
2477                 { 0x03, 0xff41 },
2478                 { 0x02, 0xdf20 },
2479                 { 0x01, 0x0140 },
2480                 { 0x00, 0x00bb },
2481                 { 0x04, 0xb800 },
2482                 { 0x04, 0xb000 },
2483
2484                 { 0x03, 0xdf41 },
2485                 { 0x02, 0xdc60 },
2486                 { 0x01, 0x6340 },
2487                 { 0x00, 0x007d },
2488                 { 0x04, 0xd800 },
2489                 { 0x04, 0xd000 },
2490
2491                 { 0x03, 0xdf01 },
2492                 { 0x02, 0xdf20 },
2493                 { 0x01, 0x100a },
2494                 { 0x00, 0xa0ff },
2495                 { 0x04, 0xf800 },
2496                 { 0x04, 0xf000 },
2497
2498                 { 0x1f, 0x0000 },
2499                 { 0x0b, 0x0000 },
2500                 { 0x00, 0x9200 }
2501         };
2502
2503         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2504 }
2505
2506 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2507 {
2508         static const struct phy_reg phy_reg_init[] = {
2509                 { 0x1f, 0x0002 },
2510                 { 0x01, 0x90d0 },
2511                 { 0x1f, 0x0000 }
2512         };
2513
2514         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2515 }
2516
2517 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2518 {
2519         struct pci_dev *pdev = tp->pci_dev;
2520
2521         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2522             (pdev->subsystem_device != 0xe000))
2523                 return;
2524
2525         rtl_writephy(tp, 0x1f, 0x0001);
2526         rtl_writephy(tp, 0x10, 0xf01b);
2527         rtl_writephy(tp, 0x1f, 0x0000);
2528 }
2529
2530 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2531 {
2532         static const struct phy_reg phy_reg_init[] = {
2533                 { 0x1f, 0x0001 },
2534                 { 0x04, 0x0000 },
2535                 { 0x03, 0x00a1 },
2536                 { 0x02, 0x0008 },
2537                 { 0x01, 0x0120 },
2538                 { 0x00, 0x1000 },
2539                 { 0x04, 0x0800 },
2540                 { 0x04, 0x9000 },
2541                 { 0x03, 0x802f },
2542                 { 0x02, 0x4f02 },
2543                 { 0x01, 0x0409 },
2544                 { 0x00, 0xf099 },
2545                 { 0x04, 0x9800 },
2546                 { 0x04, 0xa000 },
2547                 { 0x03, 0xdf01 },
2548                 { 0x02, 0xdf20 },
2549                 { 0x01, 0xff95 },
2550                 { 0x00, 0xba00 },
2551                 { 0x04, 0xa800 },
2552                 { 0x04, 0xf000 },
2553                 { 0x03, 0xdf01 },
2554                 { 0x02, 0xdf20 },
2555                 { 0x01, 0x101a },
2556                 { 0x00, 0xa0ff },
2557                 { 0x04, 0xf800 },
2558                 { 0x04, 0x0000 },
2559                 { 0x1f, 0x0000 },
2560
2561                 { 0x1f, 0x0001 },
2562                 { 0x10, 0xf41b },
2563                 { 0x14, 0xfb54 },
2564                 { 0x18, 0xf5c7 },
2565                 { 0x1f, 0x0000 },
2566
2567                 { 0x1f, 0x0001 },
2568                 { 0x17, 0x0cc0 },
2569                 { 0x1f, 0x0000 }
2570         };
2571
2572         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2573
2574         rtl8169scd_hw_phy_config_quirk(tp);
2575 }
2576
2577 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2578 {
2579         static const struct phy_reg phy_reg_init[] = {
2580                 { 0x1f, 0x0001 },
2581                 { 0x04, 0x0000 },
2582                 { 0x03, 0x00a1 },
2583                 { 0x02, 0x0008 },
2584                 { 0x01, 0x0120 },
2585                 { 0x00, 0x1000 },
2586                 { 0x04, 0x0800 },
2587                 { 0x04, 0x9000 },
2588                 { 0x03, 0x802f },
2589                 { 0x02, 0x4f02 },
2590                 { 0x01, 0x0409 },
2591                 { 0x00, 0xf099 },
2592                 { 0x04, 0x9800 },
2593                 { 0x04, 0xa000 },
2594                 { 0x03, 0xdf01 },
2595                 { 0x02, 0xdf20 },
2596                 { 0x01, 0xff95 },
2597                 { 0x00, 0xba00 },
2598                 { 0x04, 0xa800 },
2599                 { 0x04, 0xf000 },
2600                 { 0x03, 0xdf01 },
2601                 { 0x02, 0xdf20 },
2602                 { 0x01, 0x101a },
2603                 { 0x00, 0xa0ff },
2604                 { 0x04, 0xf800 },
2605                 { 0x04, 0x0000 },
2606                 { 0x1f, 0x0000 },
2607
2608                 { 0x1f, 0x0001 },
2609                 { 0x0b, 0x8480 },
2610                 { 0x1f, 0x0000 },
2611
2612                 { 0x1f, 0x0001 },
2613                 { 0x18, 0x67c7 },
2614                 { 0x04, 0x2000 },
2615                 { 0x03, 0x002f },
2616                 { 0x02, 0x4360 },
2617                 { 0x01, 0x0109 },
2618                 { 0x00, 0x3022 },
2619                 { 0x04, 0x2800 },
2620                 { 0x1f, 0x0000 },
2621
2622                 { 0x1f, 0x0001 },
2623                 { 0x17, 0x0cc0 },
2624                 { 0x1f, 0x0000 }
2625         };
2626
2627         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2628 }
2629
2630 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2631 {
2632         static const struct phy_reg phy_reg_init[] = {
2633                 { 0x10, 0xf41b },
2634                 { 0x1f, 0x0000 }
2635         };
2636
2637         rtl_writephy(tp, 0x1f, 0x0001);
2638         rtl_patchphy(tp, 0x16, 1 << 0);
2639
2640         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2641 }
2642
2643 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2644 {
2645         static const struct phy_reg phy_reg_init[] = {
2646                 { 0x1f, 0x0001 },
2647                 { 0x10, 0xf41b },
2648                 { 0x1f, 0x0000 }
2649         };
2650
2651         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2652 }
2653
2654 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2655 {
2656         static const struct phy_reg phy_reg_init[] = {
2657                 { 0x1f, 0x0000 },
2658                 { 0x1d, 0x0f00 },
2659                 { 0x1f, 0x0002 },
2660                 { 0x0c, 0x1ec8 },
2661                 { 0x1f, 0x0000 }
2662         };
2663
2664         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2665 }
2666
2667 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2668 {
2669         static const struct phy_reg phy_reg_init[] = {
2670                 { 0x1f, 0x0001 },
2671                 { 0x1d, 0x3d98 },
2672                 { 0x1f, 0x0000 }
2673         };
2674
2675         rtl_writephy(tp, 0x1f, 0x0000);
2676         rtl_patchphy(tp, 0x14, 1 << 5);
2677         rtl_patchphy(tp, 0x0d, 1 << 5);
2678
2679         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2680 }
2681
2682 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2683 {
2684         static const struct phy_reg phy_reg_init[] = {
2685                 { 0x1f, 0x0001 },
2686                 { 0x12, 0x2300 },
2687                 { 0x1f, 0x0002 },
2688                 { 0x00, 0x88d4 },
2689                 { 0x01, 0x82b1 },
2690                 { 0x03, 0x7002 },
2691                 { 0x08, 0x9e30 },
2692                 { 0x09, 0x01f0 },
2693                 { 0x0a, 0x5500 },
2694                 { 0x0c, 0x00c8 },
2695                 { 0x1f, 0x0003 },
2696                 { 0x12, 0xc096 },
2697                 { 0x16, 0x000a },
2698                 { 0x1f, 0x0000 },
2699                 { 0x1f, 0x0000 },
2700                 { 0x09, 0x2000 },
2701                 { 0x09, 0x0000 }
2702         };
2703
2704         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2705
2706         rtl_patchphy(tp, 0x14, 1 << 5);
2707         rtl_patchphy(tp, 0x0d, 1 << 5);
2708         rtl_writephy(tp, 0x1f, 0x0000);
2709 }
2710
2711 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2712 {
2713         static const struct phy_reg phy_reg_init[] = {
2714                 { 0x1f, 0x0001 },
2715                 { 0x12, 0x2300 },
2716                 { 0x03, 0x802f },
2717                 { 0x02, 0x4f02 },
2718                 { 0x01, 0x0409 },
2719                 { 0x00, 0xf099 },
2720                 { 0x04, 0x9800 },
2721                 { 0x04, 0x9000 },
2722                 { 0x1d, 0x3d98 },
2723                 { 0x1f, 0x0002 },
2724                 { 0x0c, 0x7eb8 },
2725                 { 0x06, 0x0761 },
2726                 { 0x1f, 0x0003 },
2727                 { 0x16, 0x0f0a },
2728                 { 0x1f, 0x0000 }
2729         };
2730
2731         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2732
2733         rtl_patchphy(tp, 0x16, 1 << 0);
2734         rtl_patchphy(tp, 0x14, 1 << 5);
2735         rtl_patchphy(tp, 0x0d, 1 << 5);
2736         rtl_writephy(tp, 0x1f, 0x0000);
2737 }
2738
2739 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2740 {
2741         static const struct phy_reg phy_reg_init[] = {
2742                 { 0x1f, 0x0001 },
2743                 { 0x12, 0x2300 },
2744                 { 0x1d, 0x3d98 },
2745                 { 0x1f, 0x0002 },
2746                 { 0x0c, 0x7eb8 },
2747                 { 0x06, 0x5461 },
2748                 { 0x1f, 0x0003 },
2749                 { 0x16, 0x0f0a },
2750                 { 0x1f, 0x0000 }
2751         };
2752
2753         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2754
2755         rtl_patchphy(tp, 0x16, 1 << 0);
2756         rtl_patchphy(tp, 0x14, 1 << 5);
2757         rtl_patchphy(tp, 0x0d, 1 << 5);
2758         rtl_writephy(tp, 0x1f, 0x0000);
2759 }
2760
2761 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2762 {
2763         rtl8168c_3_hw_phy_config(tp);
2764 }
2765
2766 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2767 {
2768         static const struct phy_reg phy_reg_init_0[] = {
2769                 /* Channel Estimation */
2770                 { 0x1f, 0x0001 },
2771                 { 0x06, 0x4064 },
2772                 { 0x07, 0x2863 },
2773                 { 0x08, 0x059c },
2774                 { 0x09, 0x26b4 },
2775                 { 0x0a, 0x6a19 },
2776                 { 0x0b, 0xdcc8 },
2777                 { 0x10, 0xf06d },
2778                 { 0x14, 0x7f68 },
2779                 { 0x18, 0x7fd9 },
2780                 { 0x1c, 0xf0ff },
2781                 { 0x1d, 0x3d9c },
2782                 { 0x1f, 0x0003 },
2783                 { 0x12, 0xf49f },
2784                 { 0x13, 0x070b },
2785                 { 0x1a, 0x05ad },
2786                 { 0x14, 0x94c0 },
2787
2788                 /*
2789                  * Tx Error Issue
2790                  * Enhance line driver power
2791                  */
2792                 { 0x1f, 0x0002 },
2793                 { 0x06, 0x5561 },
2794                 { 0x1f, 0x0005 },
2795                 { 0x05, 0x8332 },
2796                 { 0x06, 0x5561 },
2797
2798                 /*
2799                  * Can not link to 1Gbps with bad cable
2800                  * Decrease SNR threshold form 21.07dB to 19.04dB
2801                  */
2802                 { 0x1f, 0x0001 },
2803                 { 0x17, 0x0cc0 },
2804
2805                 { 0x1f, 0x0000 },
2806                 { 0x0d, 0xf880 }
2807         };
2808
2809         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2810
2811         /*
2812          * Rx Error Issue
2813          * Fine Tune Switching regulator parameter
2814          */
2815         rtl_writephy(tp, 0x1f, 0x0002);
2816         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2817         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2818
2819         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2820                 static const struct phy_reg phy_reg_init[] = {
2821                         { 0x1f, 0x0002 },
2822                         { 0x05, 0x669a },
2823                         { 0x1f, 0x0005 },
2824                         { 0x05, 0x8330 },
2825                         { 0x06, 0x669a },
2826                         { 0x1f, 0x0002 }
2827                 };
2828                 int val;
2829
2830                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2831
2832                 val = rtl_readphy(tp, 0x0d);
2833
2834                 if ((val & 0x00ff) != 0x006c) {
2835                         static const u32 set[] = {
2836                                 0x0065, 0x0066, 0x0067, 0x0068,
2837                                 0x0069, 0x006a, 0x006b, 0x006c
2838                         };
2839                         int i;
2840
2841                         rtl_writephy(tp, 0x1f, 0x0002);
2842
2843                         val &= 0xff00;
2844                         for (i = 0; i < ARRAY_SIZE(set); i++)
2845                                 rtl_writephy(tp, 0x0d, val | set[i]);
2846                 }
2847         } else {
2848                 static const struct phy_reg phy_reg_init[] = {
2849                         { 0x1f, 0x0002 },
2850                         { 0x05, 0x6662 },
2851                         { 0x1f, 0x0005 },
2852                         { 0x05, 0x8330 },
2853                         { 0x06, 0x6662 }
2854                 };
2855
2856                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857         }
2858
2859         /* RSET couple improve */
2860         rtl_writephy(tp, 0x1f, 0x0002);
2861         rtl_patchphy(tp, 0x0d, 0x0300);
2862         rtl_patchphy(tp, 0x0f, 0x0010);
2863
2864         /* Fine tune PLL performance */
2865         rtl_writephy(tp, 0x1f, 0x0002);
2866         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2867         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2868
2869         rtl_writephy(tp, 0x1f, 0x0005);
2870         rtl_writephy(tp, 0x05, 0x001b);
2871
2872         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2873
2874         rtl_writephy(tp, 0x1f, 0x0000);
2875 }
2876
2877 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2878 {
2879         static const struct phy_reg phy_reg_init_0[] = {
2880                 /* Channel Estimation */
2881                 { 0x1f, 0x0001 },
2882                 { 0x06, 0x4064 },
2883                 { 0x07, 0x2863 },
2884                 { 0x08, 0x059c },
2885                 { 0x09, 0x26b4 },
2886                 { 0x0a, 0x6a19 },
2887                 { 0x0b, 0xdcc8 },
2888                 { 0x10, 0xf06d },
2889                 { 0x14, 0x7f68 },
2890                 { 0x18, 0x7fd9 },
2891                 { 0x1c, 0xf0ff },
2892                 { 0x1d, 0x3d9c },
2893                 { 0x1f, 0x0003 },
2894                 { 0x12, 0xf49f },
2895                 { 0x13, 0x070b },
2896                 { 0x1a, 0x05ad },
2897                 { 0x14, 0x94c0 },
2898
2899                 /*
2900                  * Tx Error Issue
2901                  * Enhance line driver power
2902                  */
2903                 { 0x1f, 0x0002 },
2904                 { 0x06, 0x5561 },
2905                 { 0x1f, 0x0005 },
2906                 { 0x05, 0x8332 },
2907                 { 0x06, 0x5561 },
2908
2909                 /*
2910                  * Can not link to 1Gbps with bad cable
2911                  * Decrease SNR threshold form 21.07dB to 19.04dB
2912                  */
2913                 { 0x1f, 0x0001 },
2914                 { 0x17, 0x0cc0 },
2915
2916                 { 0x1f, 0x0000 },
2917                 { 0x0d, 0xf880 }
2918         };
2919
2920         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2921
2922         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2923                 static const struct phy_reg phy_reg_init[] = {
2924                         { 0x1f, 0x0002 },
2925                         { 0x05, 0x669a },
2926                         { 0x1f, 0x0005 },
2927                         { 0x05, 0x8330 },
2928                         { 0x06, 0x669a },
2929
2930                         { 0x1f, 0x0002 }
2931                 };
2932                 int val;
2933
2934                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2935
2936                 val = rtl_readphy(tp, 0x0d);
2937                 if ((val & 0x00ff) != 0x006c) {
2938                         static const u32 set[] = {
2939                                 0x0065, 0x0066, 0x0067, 0x0068,
2940                                 0x0069, 0x006a, 0x006b, 0x006c
2941                         };
2942                         int i;
2943
2944                         rtl_writephy(tp, 0x1f, 0x0002);
2945
2946                         val &= 0xff00;
2947                         for (i = 0; i < ARRAY_SIZE(set); i++)
2948                                 rtl_writephy(tp, 0x0d, val | set[i]);
2949                 }
2950         } else {
2951                 static const struct phy_reg phy_reg_init[] = {
2952                         { 0x1f, 0x0002 },
2953                         { 0x05, 0x2642 },
2954                         { 0x1f, 0x0005 },
2955                         { 0x05, 0x8330 },
2956                         { 0x06, 0x2642 }
2957                 };
2958
2959                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2960         }
2961
2962         /* Fine tune PLL performance */
2963         rtl_writephy(tp, 0x1f, 0x0002);
2964         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2965         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2966
2967         /* Switching regulator Slew rate */
2968         rtl_writephy(tp, 0x1f, 0x0002);
2969         rtl_patchphy(tp, 0x0f, 0x0017);
2970
2971         rtl_writephy(tp, 0x1f, 0x0005);
2972         rtl_writephy(tp, 0x05, 0x001b);
2973
2974         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2975
2976         rtl_writephy(tp, 0x1f, 0x0000);
2977 }
2978
2979 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2980 {
2981         static const struct phy_reg phy_reg_init[] = {
2982                 { 0x1f, 0x0002 },
2983                 { 0x10, 0x0008 },
2984                 { 0x0d, 0x006c },
2985
2986                 { 0x1f, 0x0000 },
2987                 { 0x0d, 0xf880 },
2988
2989                 { 0x1f, 0x0001 },
2990                 { 0x17, 0x0cc0 },
2991
2992                 { 0x1f, 0x0001 },
2993                 { 0x0b, 0xa4d8 },
2994                 { 0x09, 0x281c },
2995                 { 0x07, 0x2883 },
2996                 { 0x0a, 0x6b35 },
2997                 { 0x1d, 0x3da4 },
2998                 { 0x1c, 0xeffd },
2999                 { 0x14, 0x7f52 },
3000                 { 0x18, 0x7fc6 },
3001                 { 0x08, 0x0601 },
3002                 { 0x06, 0x4063 },
3003                 { 0x10, 0xf074 },
3004                 { 0x1f, 0x0003 },
3005                 { 0x13, 0x0789 },
3006                 { 0x12, 0xf4bd },
3007                 { 0x1a, 0x04fd },
3008                 { 0x14, 0x84b0 },
3009                 { 0x1f, 0x0000 },
3010                 { 0x00, 0x9200 },
3011
3012                 { 0x1f, 0x0005 },
3013                 { 0x01, 0x0340 },
3014                 { 0x1f, 0x0001 },
3015                 { 0x04, 0x4000 },
3016                 { 0x03, 0x1d21 },
3017                 { 0x02, 0x0c32 },
3018                 { 0x01, 0x0200 },
3019                 { 0x00, 0x5554 },
3020                 { 0x04, 0x4800 },
3021                 { 0x04, 0x4000 },
3022                 { 0x04, 0xf000 },
3023                 { 0x03, 0xdf01 },
3024                 { 0x02, 0xdf20 },
3025                 { 0x01, 0x101a },
3026                 { 0x00, 0xa0ff },
3027                 { 0x04, 0xf800 },
3028                 { 0x04, 0xf000 },
3029                 { 0x1f, 0x0000 },
3030
3031                 { 0x1f, 0x0007 },
3032                 { 0x1e, 0x0023 },
3033                 { 0x16, 0x0000 },
3034                 { 0x1f, 0x0000 }
3035         };
3036
3037         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3038 }
3039
3040 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3041 {
3042         static const struct phy_reg phy_reg_init[] = {
3043                 { 0x1f, 0x0001 },
3044                 { 0x17, 0x0cc0 },
3045
3046                 { 0x1f, 0x0007 },
3047                 { 0x1e, 0x002d },
3048                 { 0x18, 0x0040 },
3049                 { 0x1f, 0x0000 }
3050         };
3051
3052         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3053         rtl_patchphy(tp, 0x0d, 1 << 5);
3054 }
3055
3056 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3057 {
3058         static const struct phy_reg phy_reg_init[] = {
3059                 /* Enable Delay cap */
3060                 { 0x1f, 0x0005 },
3061                 { 0x05, 0x8b80 },
3062                 { 0x06, 0xc896 },
3063                 { 0x1f, 0x0000 },
3064
3065                 /* Channel estimation fine tune */
3066                 { 0x1f, 0x0001 },
3067                 { 0x0b, 0x6c20 },
3068                 { 0x07, 0x2872 },
3069                 { 0x1c, 0xefff },
3070                 { 0x1f, 0x0003 },
3071                 { 0x14, 0x6420 },
3072                 { 0x1f, 0x0000 },
3073
3074                 /* Update PFM & 10M TX idle timer */
3075                 { 0x1f, 0x0007 },
3076                 { 0x1e, 0x002f },
3077                 { 0x15, 0x1919 },
3078                 { 0x1f, 0x0000 },
3079
3080                 { 0x1f, 0x0007 },
3081                 { 0x1e, 0x00ac },
3082                 { 0x18, 0x0006 },
3083                 { 0x1f, 0x0000 }
3084         };
3085
3086         rtl_apply_firmware(tp);
3087
3088         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3089
3090         /* DCO enable for 10M IDLE Power */
3091         rtl_writephy(tp, 0x1f, 0x0007);
3092         rtl_writephy(tp, 0x1e, 0x0023);
3093         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3094         rtl_writephy(tp, 0x1f, 0x0000);
3095
3096         /* For impedance matching */
3097         rtl_writephy(tp, 0x1f, 0x0002);
3098         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
3099         rtl_writephy(tp, 0x1f, 0x0000);
3100
3101         /* PHY auto speed down */
3102         rtl_writephy(tp, 0x1f, 0x0007);
3103         rtl_writephy(tp, 0x1e, 0x002d);
3104         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
3105         rtl_writephy(tp, 0x1f, 0x0000);
3106         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3107
3108         rtl_writephy(tp, 0x1f, 0x0005);
3109         rtl_writephy(tp, 0x05, 0x8b86);
3110         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3111         rtl_writephy(tp, 0x1f, 0x0000);
3112
3113         rtl_writephy(tp, 0x1f, 0x0005);
3114         rtl_writephy(tp, 0x05, 0x8b85);
3115         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3116         rtl_writephy(tp, 0x1f, 0x0007);
3117         rtl_writephy(tp, 0x1e, 0x0020);
3118         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
3119         rtl_writephy(tp, 0x1f, 0x0006);
3120         rtl_writephy(tp, 0x00, 0x5a00);
3121         rtl_writephy(tp, 0x1f, 0x0000);
3122         rtl_writephy(tp, 0x0d, 0x0007);
3123         rtl_writephy(tp, 0x0e, 0x003c);
3124         rtl_writephy(tp, 0x0d, 0x4007);
3125         rtl_writephy(tp, 0x0e, 0x0000);
3126         rtl_writephy(tp, 0x0d, 0x0000);
3127 }
3128
3129 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3130 {
3131         const u16 w[] = {
3132                 addr[0] | (addr[1] << 8),
3133                 addr[2] | (addr[3] << 8),
3134                 addr[4] | (addr[5] << 8)
3135         };
3136         const struct exgmac_reg e[] = {
3137                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3138                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3139                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3140                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3141         };
3142
3143         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3144 }
3145
3146 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3147 {
3148         static const struct phy_reg phy_reg_init[] = {
3149                 /* Enable Delay cap */
3150                 { 0x1f, 0x0004 },
3151                 { 0x1f, 0x0007 },
3152                 { 0x1e, 0x00ac },
3153                 { 0x18, 0x0006 },
3154                 { 0x1f, 0x0002 },
3155                 { 0x1f, 0x0000 },
3156                 { 0x1f, 0x0000 },
3157
3158                 /* Channel estimation fine tune */
3159                 { 0x1f, 0x0003 },
3160                 { 0x09, 0xa20f },
3161                 { 0x1f, 0x0000 },
3162                 { 0x1f, 0x0000 },
3163
3164                 /* Green Setting */
3165                 { 0x1f, 0x0005 },
3166                 { 0x05, 0x8b5b },
3167                 { 0x06, 0x9222 },
3168                 { 0x05, 0x8b6d },
3169                 { 0x06, 0x8000 },
3170                 { 0x05, 0x8b76 },
3171                 { 0x06, 0x8000 },
3172                 { 0x1f, 0x0000 }
3173         };
3174
3175         rtl_apply_firmware(tp);
3176
3177         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3178
3179         /* For 4-corner performance improve */
3180         rtl_writephy(tp, 0x1f, 0x0005);
3181         rtl_writephy(tp, 0x05, 0x8b80);
3182         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
3183         rtl_writephy(tp, 0x1f, 0x0000);
3184
3185         /* PHY auto speed down */
3186         rtl_writephy(tp, 0x1f, 0x0004);
3187         rtl_writephy(tp, 0x1f, 0x0007);
3188         rtl_writephy(tp, 0x1e, 0x002d);
3189         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3190         rtl_writephy(tp, 0x1f, 0x0002);
3191         rtl_writephy(tp, 0x1f, 0x0000);
3192         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3193
3194         /* improve 10M EEE waveform */
3195         rtl_writephy(tp, 0x1f, 0x0005);
3196         rtl_writephy(tp, 0x05, 0x8b86);
3197         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3198         rtl_writephy(tp, 0x1f, 0x0000);
3199
3200         /* Improve 2-pair detection performance */
3201         rtl_writephy(tp, 0x1f, 0x0005);
3202         rtl_writephy(tp, 0x05, 0x8b85);
3203         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3204         rtl_writephy(tp, 0x1f, 0x0000);
3205
3206         /* EEE setting */
3207         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3208         rtl_writephy(tp, 0x1f, 0x0005);
3209         rtl_writephy(tp, 0x05, 0x8b85);
3210         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3211         rtl_writephy(tp, 0x1f, 0x0004);
3212         rtl_writephy(tp, 0x1f, 0x0007);
3213         rtl_writephy(tp, 0x1e, 0x0020);
3214         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3215         rtl_writephy(tp, 0x1f, 0x0002);
3216         rtl_writephy(tp, 0x1f, 0x0000);
3217         rtl_writephy(tp, 0x0d, 0x0007);
3218         rtl_writephy(tp, 0x0e, 0x003c);
3219         rtl_writephy(tp, 0x0d, 0x4007);
3220         rtl_writephy(tp, 0x0e, 0x0000);
3221         rtl_writephy(tp, 0x0d, 0x0000);
3222
3223         /* Green feature */
3224         rtl_writephy(tp, 0x1f, 0x0003);
3225         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3226         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3227         rtl_writephy(tp, 0x1f, 0x0000);
3228
3229         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3230         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3231 }
3232
3233 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3234 {
3235         /* For 4-corner performance improve */
3236         rtl_writephy(tp, 0x1f, 0x0005);
3237         rtl_writephy(tp, 0x05, 0x8b80);
3238         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3239         rtl_writephy(tp, 0x1f, 0x0000);
3240
3241         /* PHY auto speed down */
3242         rtl_writephy(tp, 0x1f, 0x0007);
3243         rtl_writephy(tp, 0x1e, 0x002d);
3244         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3245         rtl_writephy(tp, 0x1f, 0x0000);
3246         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3247
3248         /* Improve 10M EEE waveform */
3249         rtl_writephy(tp, 0x1f, 0x0005);
3250         rtl_writephy(tp, 0x05, 0x8b86);
3251         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3252         rtl_writephy(tp, 0x1f, 0x0000);
3253 }
3254
3255 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3256 {
3257         static const struct phy_reg phy_reg_init[] = {
3258                 /* Channel estimation fine tune */
3259                 { 0x1f, 0x0003 },
3260                 { 0x09, 0xa20f },
3261                 { 0x1f, 0x0000 },
3262
3263                 /* Modify green table for giga & fnet */
3264                 { 0x1f, 0x0005 },
3265                 { 0x05, 0x8b55 },
3266                 { 0x06, 0x0000 },
3267                 { 0x05, 0x8b5e },
3268                 { 0x06, 0x0000 },
3269                 { 0x05, 0x8b67 },
3270                 { 0x06, 0x0000 },
3271                 { 0x05, 0x8b70 },
3272                 { 0x06, 0x0000 },
3273                 { 0x1f, 0x0000 },
3274                 { 0x1f, 0x0007 },
3275                 { 0x1e, 0x0078 },
3276                 { 0x17, 0x0000 },
3277                 { 0x19, 0x00fb },
3278                 { 0x1f, 0x0000 },
3279
3280                 /* Modify green table for 10M */
3281                 { 0x1f, 0x0005 },
3282                 { 0x05, 0x8b79 },
3283                 { 0x06, 0xaa00 },
3284                 { 0x1f, 0x0000 },
3285
3286                 /* Disable hiimpedance detection (RTCT) */
3287                 { 0x1f, 0x0003 },
3288                 { 0x01, 0x328a },
3289                 { 0x1f, 0x0000 }
3290         };
3291
3292         rtl_apply_firmware(tp);
3293
3294         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3295
3296         rtl8168f_hw_phy_config(tp);
3297
3298         /* Improve 2-pair detection performance */
3299         rtl_writephy(tp, 0x1f, 0x0005);
3300         rtl_writephy(tp, 0x05, 0x8b85);
3301         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3302         rtl_writephy(tp, 0x1f, 0x0000);
3303 }
3304
3305 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3306 {
3307         rtl_apply_firmware(tp);
3308
3309         rtl8168f_hw_phy_config(tp);
3310 }
3311
3312 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3313 {
3314         static const struct phy_reg phy_reg_init[] = {
3315                 /* Channel estimation fine tune */
3316                 { 0x1f, 0x0003 },
3317                 { 0x09, 0xa20f },
3318                 { 0x1f, 0x0000 },
3319
3320                 /* Modify green table for giga & fnet */
3321                 { 0x1f, 0x0005 },
3322                 { 0x05, 0x8b55 },
3323                 { 0x06, 0x0000 },
3324                 { 0x05, 0x8b5e },
3325                 { 0x06, 0x0000 },
3326                 { 0x05, 0x8b67 },
3327                 { 0x06, 0x0000 },
3328                 { 0x05, 0x8b70 },
3329                 { 0x06, 0x0000 },
3330                 { 0x1f, 0x0000 },
3331                 { 0x1f, 0x0007 },
3332                 { 0x1e, 0x0078 },
3333                 { 0x17, 0x0000 },
3334                 { 0x19, 0x00aa },
3335                 { 0x1f, 0x0000 },
3336
3337                 /* Modify green table for 10M */
3338                 { 0x1f, 0x0005 },
3339                 { 0x05, 0x8b79 },
3340                 { 0x06, 0xaa00 },
3341                 { 0x1f, 0x0000 },
3342
3343                 /* Disable hiimpedance detection (RTCT) */
3344                 { 0x1f, 0x0003 },
3345                 { 0x01, 0x328a },
3346                 { 0x1f, 0x0000 }
3347         };
3348
3349
3350         rtl_apply_firmware(tp);
3351
3352         rtl8168f_hw_phy_config(tp);
3353
3354         /* Improve 2-pair detection performance */
3355         rtl_writephy(tp, 0x1f, 0x0005);
3356         rtl_writephy(tp, 0x05, 0x8b85);
3357         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3358         rtl_writephy(tp, 0x1f, 0x0000);
3359
3360         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3361
3362         /* Modify green table for giga */
3363         rtl_writephy(tp, 0x1f, 0x0005);
3364         rtl_writephy(tp, 0x05, 0x8b54);
3365         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3366         rtl_writephy(tp, 0x05, 0x8b5d);
3367         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0800);
3368         rtl_writephy(tp, 0x05, 0x8a7c);
3369         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3370         rtl_writephy(tp, 0x05, 0x8a7f);
3371         rtl_w1w0_phy(tp, 0x06, 0x0100, 0x0000);
3372         rtl_writephy(tp, 0x05, 0x8a82);
3373         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3374         rtl_writephy(tp, 0x05, 0x8a85);
3375         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3376         rtl_writephy(tp, 0x05, 0x8a88);
3377         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
3378         rtl_writephy(tp, 0x1f, 0x0000);
3379
3380         /* uc same-seed solution */
3381         rtl_writephy(tp, 0x1f, 0x0005);
3382         rtl_writephy(tp, 0x05, 0x8b85);
3383         rtl_w1w0_phy(tp, 0x06, 0x8000, 0x0000);
3384         rtl_writephy(tp, 0x1f, 0x0000);
3385
3386         /* eee setting */
3387         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3388         rtl_writephy(tp, 0x1f, 0x0005);
3389         rtl_writephy(tp, 0x05, 0x8b85);
3390         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
3391         rtl_writephy(tp, 0x1f, 0x0004);
3392         rtl_writephy(tp, 0x1f, 0x0007);
3393         rtl_writephy(tp, 0x1e, 0x0020);
3394         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
3395         rtl_writephy(tp, 0x1f, 0x0000);
3396         rtl_writephy(tp, 0x0d, 0x0007);
3397         rtl_writephy(tp, 0x0e, 0x003c);
3398         rtl_writephy(tp, 0x0d, 0x4007);
3399         rtl_writephy(tp, 0x0e, 0x0000);
3400         rtl_writephy(tp, 0x0d, 0x0000);
3401
3402         /* Green feature */
3403         rtl_writephy(tp, 0x1f, 0x0003);
3404         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
3405         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
3406         rtl_writephy(tp, 0x1f, 0x0000);
3407 }
3408
3409 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3410 {
3411         rtl_apply_firmware(tp);
3412
3413         rtl_writephy(tp, 0x1f, 0x0a46);
3414         if (rtl_readphy(tp, 0x10) & 0x0100) {
3415                 rtl_writephy(tp, 0x1f, 0x0bcc);
3416                 rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
3417         } else {
3418                 rtl_writephy(tp, 0x1f, 0x0bcc);
3419                 rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
3420         }
3421
3422         rtl_writephy(tp, 0x1f, 0x0a46);
3423         if (rtl_readphy(tp, 0x13) & 0x0100) {
3424                 rtl_writephy(tp, 0x1f, 0x0c41);
3425                 rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
3426         } else {
3427                 rtl_writephy(tp, 0x1f, 0x0c41);
3428                 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
3429         }
3430
3431         /* Enable PHY auto speed down */
3432         rtl_writephy(tp, 0x1f, 0x0a44);
3433         rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
3434
3435         rtl_writephy(tp, 0x1f, 0x0bcc);
3436         rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
3437         rtl_writephy(tp, 0x1f, 0x0a44);
3438         rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
3439         rtl_writephy(tp, 0x1f, 0x0a43);
3440         rtl_writephy(tp, 0x13, 0x8084);
3441         rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
3442         rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
3443
3444         /* EEE auto-fallback function */
3445         rtl_writephy(tp, 0x1f, 0x0a4b);
3446         rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
3447
3448         /* Enable UC LPF tune function */
3449         rtl_writephy(tp, 0x1f, 0x0a43);
3450         rtl_writephy(tp, 0x13, 0x8012);
3451         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3452
3453         rtl_writephy(tp, 0x1f, 0x0c42);
3454         rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
3455
3456         /* Improve SWR Efficiency */
3457         rtl_writephy(tp, 0x1f, 0x0bcd);
3458         rtl_writephy(tp, 0x14, 0x5065);
3459         rtl_writephy(tp, 0x14, 0xd065);
3460         rtl_writephy(tp, 0x1f, 0x0bc8);
3461         rtl_writephy(tp, 0x11, 0x5655);
3462         rtl_writephy(tp, 0x1f, 0x0bcd);
3463         rtl_writephy(tp, 0x14, 0x1065);
3464         rtl_writephy(tp, 0x14, 0x9065);
3465         rtl_writephy(tp, 0x14, 0x1065);
3466
3467         rtl_writephy(tp, 0x1f, 0x0000);
3468 }
3469
3470 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3471 {
3472         rtl_apply_firmware(tp);
3473 }
3474
3475 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3476 {
3477         static const struct phy_reg phy_reg_init[] = {
3478                 { 0x1f, 0x0003 },
3479                 { 0x08, 0x441d },
3480                 { 0x01, 0x9100 },
3481                 { 0x1f, 0x0000 }
3482         };
3483
3484         rtl_writephy(tp, 0x1f, 0x0000);
3485         rtl_patchphy(tp, 0x11, 1 << 12);
3486         rtl_patchphy(tp, 0x19, 1 << 13);
3487         rtl_patchphy(tp, 0x10, 1 << 15);
3488
3489         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3490 }
3491
3492 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3493 {
3494         static const struct phy_reg phy_reg_init[] = {
3495                 { 0x1f, 0x0005 },
3496                 { 0x1a, 0x0000 },
3497                 { 0x1f, 0x0000 },
3498
3499                 { 0x1f, 0x0004 },
3500                 { 0x1c, 0x0000 },
3501                 { 0x1f, 0x0000 },
3502
3503                 { 0x1f, 0x0001 },
3504                 { 0x15, 0x7701 },
3505                 { 0x1f, 0x0000 }
3506         };
3507
3508         /* Disable ALDPS before ram code */
3509         rtl_writephy(tp, 0x1f, 0x0000);
3510         rtl_writephy(tp, 0x18, 0x0310);
3511         msleep(100);
3512
3513         rtl_apply_firmware(tp);
3514
3515         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3516 }
3517
3518 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3519 {
3520         /* Disable ALDPS before setting firmware */
3521         rtl_writephy(tp, 0x1f, 0x0000);
3522         rtl_writephy(tp, 0x18, 0x0310);
3523         msleep(20);
3524
3525         rtl_apply_firmware(tp);
3526
3527         /* EEE setting */
3528         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3529         rtl_writephy(tp, 0x1f, 0x0004);
3530         rtl_writephy(tp, 0x10, 0x401f);
3531         rtl_writephy(tp, 0x19, 0x7030);
3532         rtl_writephy(tp, 0x1f, 0x0000);
3533 }
3534
3535 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3536 {
3537         static const struct phy_reg phy_reg_init[] = {
3538                 { 0x1f, 0x0004 },
3539                 { 0x10, 0xc07f },
3540                 { 0x19, 0x7030 },
3541                 { 0x1f, 0x0000 }
3542         };
3543
3544         /* Disable ALDPS before ram code */
3545         rtl_writephy(tp, 0x1f, 0x0000);
3546         rtl_writephy(tp, 0x18, 0x0310);
3547         msleep(100);
3548
3549         rtl_apply_firmware(tp);
3550
3551         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3552         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3553
3554         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3555 }
3556
3557 static void rtl_hw_phy_config(struct net_device *dev)
3558 {
3559         struct rtl8169_private *tp = netdev_priv(dev);
3560
3561         rtl8169_print_mac_version(tp);
3562
3563         switch (tp->mac_version) {
3564         case RTL_GIGA_MAC_VER_01:
3565                 break;
3566         case RTL_GIGA_MAC_VER_02:
3567         case RTL_GIGA_MAC_VER_03:
3568                 rtl8169s_hw_phy_config(tp);
3569                 break;
3570         case RTL_GIGA_MAC_VER_04:
3571                 rtl8169sb_hw_phy_config(tp);
3572                 break;
3573         case RTL_GIGA_MAC_VER_05:
3574                 rtl8169scd_hw_phy_config(tp);
3575                 break;
3576         case RTL_GIGA_MAC_VER_06:
3577                 rtl8169sce_hw_phy_config(tp);
3578                 break;
3579         case RTL_GIGA_MAC_VER_07:
3580         case RTL_GIGA_MAC_VER_08:
3581         case RTL_GIGA_MAC_VER_09:
3582                 rtl8102e_hw_phy_config(tp);
3583                 break;
3584         case RTL_GIGA_MAC_VER_11:
3585                 rtl8168bb_hw_phy_config(tp);
3586                 break;
3587         case RTL_GIGA_MAC_VER_12:
3588                 rtl8168bef_hw_phy_config(tp);
3589                 break;
3590         case RTL_GIGA_MAC_VER_17:
3591                 rtl8168bef_hw_phy_config(tp);
3592                 break;
3593         case RTL_GIGA_MAC_VER_18:
3594                 rtl8168cp_1_hw_phy_config(tp);
3595                 break;
3596         case RTL_GIGA_MAC_VER_19:
3597                 rtl8168c_1_hw_phy_config(tp);
3598                 break;
3599         case RTL_GIGA_MAC_VER_20:
3600                 rtl8168c_2_hw_phy_config(tp);
3601                 break;
3602         case RTL_GIGA_MAC_VER_21:
3603                 rtl8168c_3_hw_phy_config(tp);
3604                 break;
3605         case RTL_GIGA_MAC_VER_22:
3606                 rtl8168c_4_hw_phy_config(tp);
3607                 break;
3608         case RTL_GIGA_MAC_VER_23:
3609         case RTL_GIGA_MAC_VER_24:
3610                 rtl8168cp_2_hw_phy_config(tp);
3611                 break;
3612         case RTL_GIGA_MAC_VER_25:
3613                 rtl8168d_1_hw_phy_config(tp);
3614                 break;
3615         case RTL_GIGA_MAC_VER_26:
3616                 rtl8168d_2_hw_phy_config(tp);
3617                 break;
3618         case RTL_GIGA_MAC_VER_27:
3619                 rtl8168d_3_hw_phy_config(tp);
3620                 break;
3621         case RTL_GIGA_MAC_VER_28:
3622                 rtl8168d_4_hw_phy_config(tp);
3623                 break;
3624         case RTL_GIGA_MAC_VER_29:
3625         case RTL_GIGA_MAC_VER_30:
3626                 rtl8105e_hw_phy_config(tp);
3627                 break;
3628         case RTL_GIGA_MAC_VER_31:
3629                 /* None. */
3630                 break;
3631         case RTL_GIGA_MAC_VER_32:
3632         case RTL_GIGA_MAC_VER_33:
3633                 rtl8168e_1_hw_phy_config(tp);
3634                 break;
3635         case RTL_GIGA_MAC_VER_34:
3636                 rtl8168e_2_hw_phy_config(tp);
3637                 break;
3638         case RTL_GIGA_MAC_VER_35:
3639                 rtl8168f_1_hw_phy_config(tp);
3640                 break;
3641         case RTL_GIGA_MAC_VER_36:
3642                 rtl8168f_2_hw_phy_config(tp);
3643                 break;
3644
3645         case RTL_GIGA_MAC_VER_37:
3646                 rtl8402_hw_phy_config(tp);
3647                 break;
3648
3649         case RTL_GIGA_MAC_VER_38:
3650                 rtl8411_hw_phy_config(tp);
3651                 break;
3652
3653         case RTL_GIGA_MAC_VER_39:
3654                 rtl8106e_hw_phy_config(tp);
3655                 break;
3656
3657         case RTL_GIGA_MAC_VER_40:
3658                 rtl8168g_1_hw_phy_config(tp);
3659                 break;
3660         case RTL_GIGA_MAC_VER_42:
3661         case RTL_GIGA_MAC_VER_43:
3662         case RTL_GIGA_MAC_VER_44:
3663                 rtl8168g_2_hw_phy_config(tp);
3664                 break;
3665
3666         case RTL_GIGA_MAC_VER_41:
3667         default:
3668                 break;
3669         }
3670 }
3671
3672 static void rtl_phy_work(struct rtl8169_private *tp)
3673 {
3674         struct timer_list *timer = &tp->timer;
3675         void __iomem *ioaddr = tp->mmio_addr;
3676         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3677
3678         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3679
3680         if (tp->phy_reset_pending(tp)) {
3681                 /*
3682                  * A busy loop could burn quite a few cycles on nowadays CPU.
3683                  * Let's delay the execution of the timer for a few ticks.
3684                  */
3685                 timeout = HZ/10;
3686                 goto out_mod_timer;
3687         }
3688
3689         if (tp->link_ok(ioaddr))
3690                 return;
3691
3692         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
3693
3694         tp->phy_reset_enable(tp);
3695
3696 out_mod_timer:
3697         mod_timer(timer, jiffies + timeout);
3698 }
3699
3700 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3701 {
3702         if (!test_and_set_bit(flag, tp->wk.flags))
3703                 schedule_work(&tp->wk.work);
3704 }
3705
3706 static void rtl8169_phy_timer(unsigned long __opaque)
3707 {
3708         struct net_device *dev = (struct net_device *)__opaque;
3709         struct rtl8169_private *tp = netdev_priv(dev);
3710
3711         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
3712 }
3713
3714 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3715                                   void __iomem *ioaddr)
3716 {
3717         iounmap(ioaddr);
3718         pci_release_regions(pdev);
3719         pci_clear_mwi(pdev);
3720         pci_disable_device(pdev);
3721         free_netdev(dev);
3722 }
3723
3724 DECLARE_RTL_COND(rtl_phy_reset_cond)
3725 {
3726         return tp->phy_reset_pending(tp);
3727 }
3728
3729 static void rtl8169_phy_reset(struct net_device *dev,
3730                               struct rtl8169_private *tp)
3731 {
3732         tp->phy_reset_enable(tp);
3733         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
3734 }
3735
3736 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3737 {
3738         void __iomem *ioaddr = tp->mmio_addr;
3739
3740         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3741             (RTL_R8(PHYstatus) & TBI_Enable);
3742 }
3743
3744 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3745 {
3746         void __iomem *ioaddr = tp->mmio_addr;
3747
3748         rtl_hw_phy_config(dev);
3749
3750         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3751                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3752                 RTL_W8(0x82, 0x01);
3753         }
3754
3755         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3756
3757         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3758                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3759
3760         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3761                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3762                 RTL_W8(0x82, 0x01);
3763                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3764                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3765         }
3766
3767         rtl8169_phy_reset(dev, tp);
3768
3769         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3770                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3771                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3772                           (tp->mii.supports_gmii ?
3773                            ADVERTISED_1000baseT_Half |
3774                            ADVERTISED_1000baseT_Full : 0));
3775
3776         if (rtl_tbi_enabled(tp))
3777                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3778 }
3779
3780 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3781 {
3782         void __iomem *ioaddr = tp->mmio_addr;
3783
3784         rtl_lock_work(tp);
3785
3786         RTL_W8(Cfg9346, Cfg9346_Unlock);
3787
3788         RTL_W32(MAC4, addr[4] | addr[5] << 8);
3789         RTL_R32(MAC4);
3790
3791         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3792         RTL_R32(MAC0);
3793
3794         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3795                 rtl_rar_exgmac_set(tp, addr);
3796
3797         RTL_W8(Cfg9346, Cfg9346_Lock);
3798
3799         rtl_unlock_work(tp);
3800 }
3801
3802 static int rtl_set_mac_address(struct net_device *dev, void *p)
3803 {
3804         struct rtl8169_private *tp = netdev_priv(dev);
3805         struct sockaddr *addr = p;
3806
3807         if (!is_valid_ether_addr(addr->sa_data))
3808                 return -EADDRNOTAVAIL;
3809
3810         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3811
3812         rtl_rar_set(tp, dev->dev_addr);
3813
3814         return 0;
3815 }
3816
3817 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3818 {
3819         struct rtl8169_private *tp = netdev_priv(dev);
3820         struct mii_ioctl_data *data = if_mii(ifr);
3821
3822         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3823 }
3824
3825 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3826                           struct mii_ioctl_data *data, int cmd)
3827 {
3828         switch (cmd) {
3829         case SIOCGMIIPHY:
3830                 data->phy_id = 32; /* Internal PHY */
3831                 return 0;
3832
3833         case SIOCGMIIREG:
3834                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3835                 return 0;
3836
3837         case SIOCSMIIREG:
3838                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3839                 return 0;
3840         }
3841         return -EOPNOTSUPP;
3842 }
3843
3844 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3845 {
3846         return -EOPNOTSUPP;
3847 }
3848
3849 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3850 {
3851         if (tp->features & RTL_FEATURE_MSI) {
3852                 pci_disable_msi(pdev);
3853                 tp->features &= ~RTL_FEATURE_MSI;
3854         }
3855 }
3856
3857 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
3858 {
3859         struct mdio_ops *ops = &tp->mdio_ops;
3860
3861         switch (tp->mac_version) {
3862         case RTL_GIGA_MAC_VER_27:
3863                 ops->write      = r8168dp_1_mdio_write;
3864                 ops->read       = r8168dp_1_mdio_read;
3865                 break;
3866         case RTL_GIGA_MAC_VER_28:
3867         case RTL_GIGA_MAC_VER_31:
3868                 ops->write      = r8168dp_2_mdio_write;
3869                 ops->read       = r8168dp_2_mdio_read;
3870                 break;
3871         case RTL_GIGA_MAC_VER_40:
3872         case RTL_GIGA_MAC_VER_41:
3873         case RTL_GIGA_MAC_VER_42:
3874         case RTL_GIGA_MAC_VER_43:
3875         case RTL_GIGA_MAC_VER_44:
3876                 ops->write      = r8168g_mdio_write;
3877                 ops->read       = r8168g_mdio_read;
3878                 break;
3879         default:
3880                 ops->write      = r8169_mdio_write;
3881                 ops->read       = r8169_mdio_read;
3882                 break;
3883         }
3884 }
3885
3886 static void rtl_speed_down(struct rtl8169_private *tp)
3887 {
3888         u32 adv;
3889         int lpa;
3890
3891         rtl_writephy(tp, 0x1f, 0x0000);
3892         lpa = rtl_readphy(tp, MII_LPA);
3893
3894         if (lpa & (LPA_10HALF | LPA_10FULL))
3895                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
3896         else if (lpa & (LPA_100HALF | LPA_100FULL))
3897                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3898                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3899         else
3900                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3901                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3902                       (tp->mii.supports_gmii ?
3903                        ADVERTISED_1000baseT_Half |
3904                        ADVERTISED_1000baseT_Full : 0);
3905
3906         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3907                           adv);
3908 }
3909
3910 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3911 {
3912         void __iomem *ioaddr = tp->mmio_addr;
3913
3914         switch (tp->mac_version) {
3915         case RTL_GIGA_MAC_VER_25:
3916         case RTL_GIGA_MAC_VER_26:
3917         case RTL_GIGA_MAC_VER_29:
3918         case RTL_GIGA_MAC_VER_30:
3919         case RTL_GIGA_MAC_VER_32:
3920         case RTL_GIGA_MAC_VER_33:
3921         case RTL_GIGA_MAC_VER_34:
3922         case RTL_GIGA_MAC_VER_37:
3923         case RTL_GIGA_MAC_VER_38:
3924         case RTL_GIGA_MAC_VER_39:
3925         case RTL_GIGA_MAC_VER_40:
3926         case RTL_GIGA_MAC_VER_41:
3927         case RTL_GIGA_MAC_VER_42:
3928         case RTL_GIGA_MAC_VER_43:
3929         case RTL_GIGA_MAC_VER_44:
3930                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3931                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3932                 break;
3933         default:
3934                 break;
3935         }
3936 }
3937
3938 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3939 {
3940         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3941                 return false;
3942
3943         rtl_speed_down(tp);
3944         rtl_wol_suspend_quirk(tp);
3945
3946         return true;
3947 }
3948
3949 static void r810x_phy_power_down(struct rtl8169_private *tp)
3950 {
3951         rtl_writephy(tp, 0x1f, 0x0000);
3952         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3953 }
3954
3955 static void r810x_phy_power_up(struct rtl8169_private *tp)
3956 {
3957         rtl_writephy(tp, 0x1f, 0x0000);
3958         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3959 }
3960
3961 static void r810x_pll_power_down(struct rtl8169_private *tp)
3962 {
3963         void __iomem *ioaddr = tp->mmio_addr;
3964
3965         if (rtl_wol_pll_power_down(tp))
3966                 return;
3967
3968         r810x_phy_power_down(tp);
3969
3970         switch (tp->mac_version) {
3971         case RTL_GIGA_MAC_VER_07:
3972         case RTL_GIGA_MAC_VER_08:
3973         case RTL_GIGA_MAC_VER_09:
3974         case RTL_GIGA_MAC_VER_10:
3975         case RTL_GIGA_MAC_VER_13:
3976         case RTL_GIGA_MAC_VER_16:
3977                 break;
3978         default:
3979                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3980                 break;
3981         }
3982 }
3983
3984 static void r810x_pll_power_up(struct rtl8169_private *tp)
3985 {
3986         void __iomem *ioaddr = tp->mmio_addr;
3987
3988         r810x_phy_power_up(tp);
3989
3990         switch (tp->mac_version) {
3991         case RTL_GIGA_MAC_VER_07:
3992         case RTL_GIGA_MAC_VER_08:
3993         case RTL_GIGA_MAC_VER_09:
3994         case RTL_GIGA_MAC_VER_10:
3995         case RTL_GIGA_MAC_VER_13:
3996         case RTL_GIGA_MAC_VER_16:
3997                 break;
3998         default:
3999                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4000                 break;
4001         }
4002 }
4003
4004 static void r8168_phy_power_up(struct rtl8169_private *tp)
4005 {
4006         rtl_writephy(tp, 0x1f, 0x0000);
4007         switch (tp->mac_version) {
4008         case RTL_GIGA_MAC_VER_11:
4009         case RTL_GIGA_MAC_VER_12:
4010         case RTL_GIGA_MAC_VER_17:
4011         case RTL_GIGA_MAC_VER_18:
4012         case RTL_GIGA_MAC_VER_19:
4013         case RTL_GIGA_MAC_VER_20:
4014         case RTL_GIGA_MAC_VER_21:
4015         case RTL_GIGA_MAC_VER_22:
4016         case RTL_GIGA_MAC_VER_23:
4017         case RTL_GIGA_MAC_VER_24:
4018         case RTL_GIGA_MAC_VER_25:
4019         case RTL_GIGA_MAC_VER_26:
4020         case RTL_GIGA_MAC_VER_27:
4021         case RTL_GIGA_MAC_VER_28:
4022         case RTL_GIGA_MAC_VER_31:
4023                 rtl_writephy(tp, 0x0e, 0x0000);
4024                 break;
4025         default:
4026                 break;
4027         }
4028         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4029 }
4030
4031 static void r8168_phy_power_down(struct rtl8169_private *tp)
4032 {
4033         rtl_writephy(tp, 0x1f, 0x0000);
4034         switch (tp->mac_version) {
4035         case RTL_GIGA_MAC_VER_32:
4036         case RTL_GIGA_MAC_VER_33:
4037         case RTL_GIGA_MAC_VER_40:
4038         case RTL_GIGA_MAC_VER_41:
4039                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4040                 break;
4041
4042         case RTL_GIGA_MAC_VER_11:
4043         case RTL_GIGA_MAC_VER_12:
4044         case RTL_GIGA_MAC_VER_17:
4045         case RTL_GIGA_MAC_VER_18:
4046         case RTL_GIGA_MAC_VER_19:
4047         case RTL_GIGA_MAC_VER_20:
4048         case RTL_GIGA_MAC_VER_21:
4049         case RTL_GIGA_MAC_VER_22:
4050         case RTL_GIGA_MAC_VER_23:
4051         case RTL_GIGA_MAC_VER_24:
4052         case RTL_GIGA_MAC_VER_25:
4053         case RTL_GIGA_MAC_VER_26:
4054         case RTL_GIGA_MAC_VER_27:
4055         case RTL_GIGA_MAC_VER_28:
4056         case RTL_GIGA_MAC_VER_31:
4057                 rtl_writephy(tp, 0x0e, 0x0200);
4058         default:
4059                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4060                 break;
4061         }
4062 }
4063
4064 static void r8168_pll_power_down(struct rtl8169_private *tp)
4065 {
4066         void __iomem *ioaddr = tp->mmio_addr;
4067
4068         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4069              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4070              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4071             r8168dp_check_dash(tp)) {
4072                 return;
4073         }
4074
4075         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4076              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4077             (RTL_R16(CPlusCmd) & ASF)) {
4078                 return;
4079         }
4080
4081         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4082             tp->mac_version == RTL_GIGA_MAC_VER_33)
4083                 rtl_ephy_write(tp, 0x19, 0xff64);
4084
4085         if (rtl_wol_pll_power_down(tp))
4086                 return;
4087
4088         r8168_phy_power_down(tp);
4089
4090         switch (tp->mac_version) {
4091         case RTL_GIGA_MAC_VER_25:
4092         case RTL_GIGA_MAC_VER_26:
4093         case RTL_GIGA_MAC_VER_27:
4094         case RTL_GIGA_MAC_VER_28:
4095         case RTL_GIGA_MAC_VER_31:
4096         case RTL_GIGA_MAC_VER_32:
4097         case RTL_GIGA_MAC_VER_33:
4098                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4099                 break;
4100         case RTL_GIGA_MAC_VER_40:
4101         case RTL_GIGA_MAC_VER_41:
4102                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4103                              0xfc000000, ERIAR_EXGMAC);
4104                 break;
4105         }
4106 }
4107
4108 static void r8168_pll_power_up(struct rtl8169_private *tp)
4109 {
4110         void __iomem *ioaddr = tp->mmio_addr;
4111
4112         switch (tp->mac_version) {
4113         case RTL_GIGA_MAC_VER_25:
4114         case RTL_GIGA_MAC_VER_26:
4115         case RTL_GIGA_MAC_VER_27:
4116         case RTL_GIGA_MAC_VER_28:
4117         case RTL_GIGA_MAC_VER_31:
4118         case RTL_GIGA_MAC_VER_32:
4119         case RTL_GIGA_MAC_VER_33:
4120                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4121                 break;
4122         case RTL_GIGA_MAC_VER_40:
4123         case RTL_GIGA_MAC_VER_41:
4124                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4125                              0x00000000, ERIAR_EXGMAC);
4126                 break;
4127         }
4128
4129         r8168_phy_power_up(tp);
4130 }
4131
4132 static void rtl_generic_op(struct rtl8169_private *tp,
4133                            void (*op)(struct rtl8169_private *))
4134 {
4135         if (op)
4136                 op(tp);
4137 }
4138
4139 static void rtl_pll_power_down(struct rtl8169_private *tp)
4140 {
4141         rtl_generic_op(tp, tp->pll_power_ops.down);
4142 }
4143
4144 static void rtl_pll_power_up(struct rtl8169_private *tp)
4145 {
4146         rtl_generic_op(tp, tp->pll_power_ops.up);
4147 }
4148
4149 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4150 {
4151         struct pll_power_ops *ops = &tp->pll_power_ops;
4152
4153         switch (tp->mac_version) {
4154         case RTL_GIGA_MAC_VER_07:
4155         case RTL_GIGA_MAC_VER_08:
4156         case RTL_GIGA_MAC_VER_09:
4157         case RTL_GIGA_MAC_VER_10:
4158         case RTL_GIGA_MAC_VER_16:
4159         case RTL_GIGA_MAC_VER_29:
4160         case RTL_GIGA_MAC_VER_30:
4161         case RTL_GIGA_MAC_VER_37:
4162         case RTL_GIGA_MAC_VER_39:
4163         case RTL_GIGA_MAC_VER_43:
4164                 ops->down       = r810x_pll_power_down;
4165                 ops->up         = r810x_pll_power_up;
4166                 break;
4167
4168         case RTL_GIGA_MAC_VER_11:
4169         case RTL_GIGA_MAC_VER_12:
4170         case RTL_GIGA_MAC_VER_17:
4171         case RTL_GIGA_MAC_VER_18:
4172         case RTL_GIGA_MAC_VER_19:
4173         case RTL_GIGA_MAC_VER_20:
4174         case RTL_GIGA_MAC_VER_21:
4175         case RTL_GIGA_MAC_VER_22:
4176         case RTL_GIGA_MAC_VER_23:
4177         case RTL_GIGA_MAC_VER_24:
4178         case RTL_GIGA_MAC_VER_25:
4179         case RTL_GIGA_MAC_VER_26:
4180         case RTL_GIGA_MAC_VER_27:
4181         case RTL_GIGA_MAC_VER_28:
4182         case RTL_GIGA_MAC_VER_31:
4183         case RTL_GIGA_MAC_VER_32:
4184         case RTL_GIGA_MAC_VER_33:
4185         case RTL_GIGA_MAC_VER_34:
4186         case RTL_GIGA_MAC_VER_35:
4187         case RTL_GIGA_MAC_VER_36:
4188         case RTL_GIGA_MAC_VER_38:
4189         case RTL_GIGA_MAC_VER_40:
4190         case RTL_GIGA_MAC_VER_41:
4191         case RTL_GIGA_MAC_VER_42:
4192         case RTL_GIGA_MAC_VER_44:
4193                 ops->down       = r8168_pll_power_down;
4194                 ops->up         = r8168_pll_power_up;
4195                 break;
4196
4197         default:
4198                 ops->down       = NULL;
4199                 ops->up         = NULL;
4200                 break;
4201         }
4202 }
4203
4204 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4205 {
4206         void __iomem *ioaddr = tp->mmio_addr;
4207
4208         switch (tp->mac_version) {
4209         case RTL_GIGA_MAC_VER_01:
4210         case RTL_GIGA_MAC_VER_02:
4211         case RTL_GIGA_MAC_VER_03:
4212         case RTL_GIGA_MAC_VER_04:
4213         case RTL_GIGA_MAC_VER_05:
4214         case RTL_GIGA_MAC_VER_06:
4215         case RTL_GIGA_MAC_VER_10:
4216         case RTL_GIGA_MAC_VER_11:
4217         case RTL_GIGA_MAC_VER_12:
4218         case RTL_GIGA_MAC_VER_13:
4219         case RTL_GIGA_MAC_VER_14:
4220         case RTL_GIGA_MAC_VER_15:
4221         case RTL_GIGA_MAC_VER_16:
4222         case RTL_GIGA_MAC_VER_17:
4223                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4224                 break;
4225         case RTL_GIGA_MAC_VER_18:
4226         case RTL_GIGA_MAC_VER_19:
4227         case RTL_GIGA_MAC_VER_20:
4228         case RTL_GIGA_MAC_VER_21:
4229         case RTL_GIGA_MAC_VER_22:
4230         case RTL_GIGA_MAC_VER_23:
4231         case RTL_GIGA_MAC_VER_24:
4232         case RTL_GIGA_MAC_VER_34:
4233                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4234                 break;
4235         case RTL_GIGA_MAC_VER_40:
4236         case RTL_GIGA_MAC_VER_41:
4237         case RTL_GIGA_MAC_VER_42:
4238         case RTL_GIGA_MAC_VER_43:
4239         case RTL_GIGA_MAC_VER_44:
4240                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4241                 break;
4242         default:
4243                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4244                 break;
4245         }
4246 }
4247
4248 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4249 {
4250         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4251 }
4252
4253 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4254 {
4255         void __iomem *ioaddr = tp->mmio_addr;
4256
4257         RTL_W8(Cfg9346, Cfg9346_Unlock);
4258         rtl_generic_op(tp, tp->jumbo_ops.enable);
4259         RTL_W8(Cfg9346, Cfg9346_Lock);
4260 }
4261
4262 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4263 {
4264         void __iomem *ioaddr = tp->mmio_addr;
4265
4266         RTL_W8(Cfg9346, Cfg9346_Unlock);
4267         rtl_generic_op(tp, tp->jumbo_ops.disable);
4268         RTL_W8(Cfg9346, Cfg9346_Lock);
4269 }
4270
4271 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4272 {
4273         void __iomem *ioaddr = tp->mmio_addr;
4274
4275         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4276         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4277         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4278 }
4279
4280 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4281 {
4282         void __iomem *ioaddr = tp->mmio_addr;
4283
4284         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4285         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4286         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4287 }
4288
4289 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4290 {
4291         void __iomem *ioaddr = tp->mmio_addr;
4292
4293         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4294 }
4295
4296 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4297 {
4298         void __iomem *ioaddr = tp->mmio_addr;
4299
4300         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4301 }
4302
4303 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4304 {
4305         void __iomem *ioaddr = tp->mmio_addr;
4306
4307         RTL_W8(MaxTxPacketSize, 0x3f);
4308         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4309         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4310         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4311 }
4312
4313 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4314 {
4315         void __iomem *ioaddr = tp->mmio_addr;
4316
4317         RTL_W8(MaxTxPacketSize, 0x0c);
4318         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4319         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4320         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4321 }
4322
4323 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4324 {
4325         rtl_tx_performance_tweak(tp->pci_dev,
4326                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4327 }
4328
4329 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4330 {
4331         rtl_tx_performance_tweak(tp->pci_dev,
4332                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4333 }
4334
4335 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4336 {
4337         void __iomem *ioaddr = tp->mmio_addr;
4338
4339         r8168b_0_hw_jumbo_enable(tp);
4340
4341         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4342 }
4343
4344 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4345 {
4346         void __iomem *ioaddr = tp->mmio_addr;
4347
4348         r8168b_0_hw_jumbo_disable(tp);
4349
4350         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4351 }
4352
4353 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4354 {
4355         struct jumbo_ops *ops = &tp->jumbo_ops;
4356
4357         switch (tp->mac_version) {
4358         case RTL_GIGA_MAC_VER_11:
4359                 ops->disable    = r8168b_0_hw_jumbo_disable;
4360                 ops->enable     = r8168b_0_hw_jumbo_enable;
4361                 break;
4362         case RTL_GIGA_MAC_VER_12:
4363         case RTL_GIGA_MAC_VER_17:
4364                 ops->disable    = r8168b_1_hw_jumbo_disable;
4365                 ops->enable     = r8168b_1_hw_jumbo_enable;
4366                 break;
4367         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4368         case RTL_GIGA_MAC_VER_19:
4369         case RTL_GIGA_MAC_VER_20:
4370         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4371         case RTL_GIGA_MAC_VER_22:
4372         case RTL_GIGA_MAC_VER_23:
4373         case RTL_GIGA_MAC_VER_24:
4374         case RTL_GIGA_MAC_VER_25:
4375         case RTL_GIGA_MAC_VER_26:
4376                 ops->disable    = r8168c_hw_jumbo_disable;
4377                 ops->enable     = r8168c_hw_jumbo_enable;
4378                 break;
4379         case RTL_GIGA_MAC_VER_27:
4380         case RTL_GIGA_MAC_VER_28:
4381                 ops->disable    = r8168dp_hw_jumbo_disable;
4382                 ops->enable     = r8168dp_hw_jumbo_enable;
4383                 break;
4384         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4385         case RTL_GIGA_MAC_VER_32:
4386         case RTL_GIGA_MAC_VER_33:
4387         case RTL_GIGA_MAC_VER_34:
4388                 ops->disable    = r8168e_hw_jumbo_disable;
4389                 ops->enable     = r8168e_hw_jumbo_enable;
4390                 break;
4391
4392         /*
4393          * No action needed for jumbo frames with 8169.
4394          * No jumbo for 810x at all.
4395          */
4396         case RTL_GIGA_MAC_VER_40:
4397         case RTL_GIGA_MAC_VER_41:
4398         case RTL_GIGA_MAC_VER_42:
4399         case RTL_GIGA_MAC_VER_43:
4400         case RTL_GIGA_MAC_VER_44:
4401         default:
4402                 ops->disable    = NULL;
4403                 ops->enable     = NULL;
4404                 break;
4405         }
4406 }
4407
4408 DECLARE_RTL_COND(rtl_chipcmd_cond)
4409 {
4410         void __iomem *ioaddr = tp->mmio_addr;
4411
4412         return RTL_R8(ChipCmd) & CmdReset;
4413 }
4414
4415 static void rtl_hw_reset(struct rtl8169_private *tp)
4416 {
4417         void __iomem *ioaddr = tp->mmio_addr;
4418
4419         RTL_W8(ChipCmd, CmdReset);
4420
4421         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4422 }
4423
4424 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4425 {
4426         struct rtl_fw *rtl_fw;
4427         const char *name;
4428         int rc = -ENOMEM;
4429
4430         name = rtl_lookup_firmware_name(tp);
4431         if (!name)
4432                 goto out_no_firmware;
4433
4434         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4435         if (!rtl_fw)
4436                 goto err_warn;
4437
4438         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4439         if (rc < 0)
4440                 goto err_free;
4441
4442         rc = rtl_check_firmware(tp, rtl_fw);
4443         if (rc < 0)
4444                 goto err_release_firmware;
4445
4446         tp->rtl_fw = rtl_fw;
4447 out:
4448         return;
4449
4450 err_release_firmware:
4451         release_firmware(rtl_fw->fw);
4452 err_free:
4453         kfree(rtl_fw);
4454 err_warn:
4455         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4456                    name, rc);
4457 out_no_firmware:
4458         tp->rtl_fw = NULL;
4459         goto out;
4460 }
4461
4462 static void rtl_request_firmware(struct rtl8169_private *tp)
4463 {
4464         if (IS_ERR(tp->rtl_fw))
4465                 rtl_request_uncached_firmware(tp);
4466 }
4467
4468 static void rtl_rx_close(struct rtl8169_private *tp)
4469 {
4470         void __iomem *ioaddr = tp->mmio_addr;
4471
4472         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4473 }
4474
4475 DECLARE_RTL_COND(rtl_npq_cond)
4476 {
4477         void __iomem *ioaddr = tp->mmio_addr;
4478
4479         return RTL_R8(TxPoll) & NPQ;
4480 }
4481
4482 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4483 {
4484         void __iomem *ioaddr = tp->mmio_addr;
4485
4486         return RTL_R32(TxConfig) & TXCFG_EMPTY;
4487 }
4488
4489 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4490 {
4491         void __iomem *ioaddr = tp->mmio_addr;
4492
4493         /* Disable interrupts */
4494         rtl8169_irq_mask_and_ack(tp);
4495
4496         rtl_rx_close(tp);
4497
4498         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4499             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4500             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4501                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4502         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4503                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4504                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
4505                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
4506                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
4507                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
4508                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
4509                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
4510                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
4511                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
4512                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4513                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4514         } else {
4515                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4516                 udelay(100);
4517         }
4518
4519         rtl_hw_reset(tp);
4520 }
4521
4522 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4523 {
4524         void __iomem *ioaddr = tp->mmio_addr;
4525
4526         /* Set DMA burst size and Interframe Gap Time */
4527         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4528                 (InterFrameGap << TxInterFrameGapShift));
4529 }
4530
4531 static void rtl_hw_start(struct net_device *dev)
4532 {
4533         struct rtl8169_private *tp = netdev_priv(dev);
4534
4535         tp->hw_start(dev);
4536
4537         rtl_irq_enable_all(tp);
4538 }
4539
4540 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4541                                          void __iomem *ioaddr)
4542 {
4543         /*
4544          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4545          * register to be written before TxDescAddrLow to work.
4546          * Switching from MMIO to I/O access fixes the issue as well.
4547          */
4548         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4549         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4550         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4551         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4552 }
4553
4554 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4555 {
4556         u16 cmd;
4557
4558         cmd = RTL_R16(CPlusCmd);
4559         RTL_W16(CPlusCmd, cmd);
4560         return cmd;
4561 }
4562
4563 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4564 {
4565         /* Low hurts. Let's disable the filtering. */
4566         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4567 }
4568
4569 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4570 {
4571         static const struct rtl_cfg2_info {
4572                 u32 mac_version;
4573                 u32 clk;
4574                 u32 val;
4575         } cfg2_info [] = {
4576                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4577                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4578                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4579                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4580         };
4581         const struct rtl_cfg2_info *p = cfg2_info;
4582         unsigned int i;
4583         u32 clk;
4584
4585         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4586         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4587                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4588                         RTL_W32(0x7c, p->val);
4589                         break;
4590                 }
4591         }
4592 }
4593
4594 static void rtl_set_rx_mode(struct net_device *dev)
4595 {
4596         struct rtl8169_private *tp = netdev_priv(dev);
4597         void __iomem *ioaddr = tp->mmio_addr;
4598         u32 mc_filter[2];       /* Multicast hash filter */
4599         int rx_mode;
4600         u32 tmp = 0;
4601
4602         if (dev->flags & IFF_PROMISC) {
4603                 /* Unconditionally log net taps. */
4604                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4605                 rx_mode =
4606                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4607                     AcceptAllPhys;
4608                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4609         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4610                    (dev->flags & IFF_ALLMULTI)) {
4611                 /* Too many to filter perfectly -- accept all multicasts. */
4612                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4613                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4614         } else {
4615                 struct netdev_hw_addr *ha;
4616
4617                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4618                 mc_filter[1] = mc_filter[0] = 0;
4619                 netdev_for_each_mc_addr(ha, dev) {
4620                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4621                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4622                         rx_mode |= AcceptMulticast;
4623                 }
4624         }
4625
4626         if (dev->features & NETIF_F_RXALL)
4627                 rx_mode |= (AcceptErr | AcceptRunt);
4628
4629         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4630
4631         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4632                 u32 data = mc_filter[0];
4633
4634                 mc_filter[0] = swab32(mc_filter[1]);
4635                 mc_filter[1] = swab32(data);
4636         }
4637
4638         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4639                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4640
4641         RTL_W32(MAR0 + 4, mc_filter[1]);
4642         RTL_W32(MAR0 + 0, mc_filter[0]);
4643
4644         RTL_W32(RxConfig, tmp);
4645 }
4646
4647 static void rtl_hw_start_8169(struct net_device *dev)
4648 {
4649         struct rtl8169_private *tp = netdev_priv(dev);
4650         void __iomem *ioaddr = tp->mmio_addr;
4651         struct pci_dev *pdev = tp->pci_dev;
4652
4653         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4654                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4655                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4656         }
4657
4658         RTL_W8(Cfg9346, Cfg9346_Unlock);
4659         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4660             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4661             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4662             tp->mac_version == RTL_GIGA_MAC_VER_04)
4663                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4664
4665         rtl_init_rxcfg(tp);
4666
4667         RTL_W8(EarlyTxThres, NoEarlyTx);
4668
4669         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4670
4671         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4672             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4673             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4674             tp->mac_version == RTL_GIGA_MAC_VER_04)
4675                 rtl_set_rx_tx_config_registers(tp);
4676
4677         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4678
4679         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4680             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4681                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4682                         "Bit-3 and bit-14 MUST be 1\n");
4683                 tp->cp_cmd |= (1 << 14);
4684         }
4685
4686         RTL_W16(CPlusCmd, tp->cp_cmd);
4687
4688         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4689
4690         /*
4691          * Undocumented corner. Supposedly:
4692          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4693          */
4694         RTL_W16(IntrMitigate, 0x0000);
4695
4696         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4697
4698         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4699             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4700             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4701             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4702                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4703                 rtl_set_rx_tx_config_registers(tp);
4704         }
4705
4706         RTL_W8(Cfg9346, Cfg9346_Lock);
4707
4708         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4709         RTL_R8(IntrMask);
4710
4711         RTL_W32(RxMissed, 0);
4712
4713         rtl_set_rx_mode(dev);
4714
4715         /* no early-rx interrupts */
4716         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4717 }
4718
4719 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4720 {
4721         if (tp->csi_ops.write)
4722                 tp->csi_ops.write(tp, addr, value);
4723 }
4724
4725 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4726 {
4727         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
4728 }
4729
4730 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
4731 {
4732         u32 csi;
4733
4734         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4735         rtl_csi_write(tp, 0x070c, csi | bits);
4736 }
4737
4738 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
4739 {
4740         rtl_csi_access_enable(tp, 0x17000000);
4741 }
4742
4743 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
4744 {
4745         rtl_csi_access_enable(tp, 0x27000000);
4746 }
4747
4748 DECLARE_RTL_COND(rtl_csiar_cond)
4749 {
4750         void __iomem *ioaddr = tp->mmio_addr;
4751
4752         return RTL_R32(CSIAR) & CSIAR_FLAG;
4753 }
4754
4755 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
4756 {
4757         void __iomem *ioaddr = tp->mmio_addr;
4758
4759         RTL_W32(CSIDR, value);
4760         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4761                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4762
4763         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4764 }
4765
4766 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
4767 {
4768         void __iomem *ioaddr = tp->mmio_addr;
4769
4770         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
4771                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4772
4773         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4774                 RTL_R32(CSIDR) : ~0;
4775 }
4776
4777 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
4778 {
4779         void __iomem *ioaddr = tp->mmio_addr;
4780
4781         RTL_W32(CSIDR, value);
4782         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4783                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4784                 CSIAR_FUNC_NIC);
4785
4786         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4787 }
4788
4789 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
4790 {
4791         void __iomem *ioaddr = tp->mmio_addr;
4792
4793         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
4794                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4795
4796         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4797                 RTL_R32(CSIDR) : ~0;
4798 }
4799
4800 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
4801 {
4802         void __iomem *ioaddr = tp->mmio_addr;
4803
4804         RTL_W32(CSIDR, value);
4805         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4806                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
4807                 CSIAR_FUNC_NIC2);
4808
4809         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4810 }
4811
4812 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
4813 {
4814         void __iomem *ioaddr = tp->mmio_addr;
4815
4816         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
4817                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
4818
4819         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4820                 RTL_R32(CSIDR) : ~0;
4821 }
4822
4823 static void rtl_init_csi_ops(struct rtl8169_private *tp)
4824 {
4825         struct csi_ops *ops = &tp->csi_ops;
4826
4827         switch (tp->mac_version) {
4828         case RTL_GIGA_MAC_VER_01:
4829         case RTL_GIGA_MAC_VER_02:
4830         case RTL_GIGA_MAC_VER_03:
4831         case RTL_GIGA_MAC_VER_04:
4832         case RTL_GIGA_MAC_VER_05:
4833         case RTL_GIGA_MAC_VER_06:
4834         case RTL_GIGA_MAC_VER_10:
4835         case RTL_GIGA_MAC_VER_11:
4836         case RTL_GIGA_MAC_VER_12:
4837         case RTL_GIGA_MAC_VER_13:
4838         case RTL_GIGA_MAC_VER_14:
4839         case RTL_GIGA_MAC_VER_15:
4840         case RTL_GIGA_MAC_VER_16:
4841         case RTL_GIGA_MAC_VER_17:
4842                 ops->write      = NULL;
4843                 ops->read       = NULL;
4844                 break;
4845
4846         case RTL_GIGA_MAC_VER_37:
4847         case RTL_GIGA_MAC_VER_38:
4848                 ops->write      = r8402_csi_write;
4849                 ops->read       = r8402_csi_read;
4850                 break;
4851
4852         case RTL_GIGA_MAC_VER_44:
4853                 ops->write      = r8411_csi_write;
4854                 ops->read       = r8411_csi_read;
4855                 break;
4856
4857         default:
4858                 ops->write      = r8169_csi_write;
4859                 ops->read       = r8169_csi_read;
4860                 break;
4861         }
4862 }
4863
4864 struct ephy_info {
4865         unsigned int offset;
4866         u16 mask;
4867         u16 bits;
4868 };
4869
4870 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4871                           int len)
4872 {
4873         u16 w;
4874
4875         while (len-- > 0) {
4876                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4877                 rtl_ephy_write(tp, e->offset, w);
4878                 e++;
4879         }
4880 }
4881
4882 static void rtl_disable_clock_request(struct pci_dev *pdev)
4883 {
4884         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
4885                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4886 }
4887
4888 static void rtl_enable_clock_request(struct pci_dev *pdev)
4889 {
4890         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
4891                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4892 }
4893
4894 #define R8168_CPCMD_QUIRK_MASK (\
4895         EnableBist | \
4896         Mac_dbgo_oe | \
4897         Force_half_dup | \
4898         Force_rxflow_en | \
4899         Force_txflow_en | \
4900         Cxpl_dbg_sel | \
4901         ASF | \
4902         PktCntrDisable | \
4903         Mac_dbgo_sel)
4904
4905 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4906 {
4907         void __iomem *ioaddr = tp->mmio_addr;
4908         struct pci_dev *pdev = tp->pci_dev;
4909
4910         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4911
4912         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4913
4914         if (tp->dev->mtu <= ETH_DATA_LEN) {
4915                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
4916                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4917         }
4918 }
4919
4920 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4921 {
4922         void __iomem *ioaddr = tp->mmio_addr;
4923
4924         rtl_hw_start_8168bb(tp);
4925
4926         RTL_W8(MaxTxPacketSize, TxPacketMax);
4927
4928         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4929 }
4930
4931 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4932 {
4933         void __iomem *ioaddr = tp->mmio_addr;
4934         struct pci_dev *pdev = tp->pci_dev;
4935
4936         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4937
4938         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4939
4940         if (tp->dev->mtu <= ETH_DATA_LEN)
4941                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4942
4943         rtl_disable_clock_request(pdev);
4944
4945         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4946 }
4947
4948 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4949 {
4950         static const struct ephy_info e_info_8168cp[] = {
4951                 { 0x01, 0,      0x0001 },
4952                 { 0x02, 0x0800, 0x1000 },
4953                 { 0x03, 0,      0x0042 },
4954                 { 0x06, 0x0080, 0x0000 },
4955                 { 0x07, 0,      0x2000 }
4956         };
4957
4958         rtl_csi_access_enable_2(tp);
4959
4960         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4961
4962         __rtl_hw_start_8168cp(tp);
4963 }
4964
4965 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4966 {
4967         void __iomem *ioaddr = tp->mmio_addr;
4968         struct pci_dev *pdev = tp->pci_dev;
4969
4970         rtl_csi_access_enable_2(tp);
4971
4972         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4973
4974         if (tp->dev->mtu <= ETH_DATA_LEN)
4975                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4976
4977         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4978 }
4979
4980 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4981 {
4982         void __iomem *ioaddr = tp->mmio_addr;
4983         struct pci_dev *pdev = tp->pci_dev;
4984
4985         rtl_csi_access_enable_2(tp);
4986
4987         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4988
4989         /* Magic. */
4990         RTL_W8(DBG_REG, 0x20);
4991
4992         RTL_W8(MaxTxPacketSize, TxPacketMax);
4993
4994         if (tp->dev->mtu <= ETH_DATA_LEN)
4995                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4996
4997         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4998 }
4999
5000 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5001 {
5002         void __iomem *ioaddr = tp->mmio_addr;
5003         static const struct ephy_info e_info_8168c_1[] = {
5004                 { 0x02, 0x0800, 0x1000 },
5005                 { 0x03, 0,      0x0002 },
5006                 { 0x06, 0x0080, 0x0000 }
5007         };
5008
5009         rtl_csi_access_enable_2(tp);
5010
5011         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5012
5013         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5014
5015         __rtl_hw_start_8168cp(tp);
5016 }
5017
5018 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5019 {
5020         static const struct ephy_info e_info_8168c_2[] = {
5021                 { 0x01, 0,      0x0001 },
5022                 { 0x03, 0x0400, 0x0220 }
5023         };
5024
5025         rtl_csi_access_enable_2(tp);
5026
5027         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5028
5029         __rtl_hw_start_8168cp(tp);
5030 }
5031
5032 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5033 {
5034         rtl_hw_start_8168c_2(tp);
5035 }
5036
5037 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5038 {
5039         rtl_csi_access_enable_2(tp);
5040
5041         __rtl_hw_start_8168cp(tp);
5042 }
5043
5044 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5045 {
5046         void __iomem *ioaddr = tp->mmio_addr;
5047         struct pci_dev *pdev = tp->pci_dev;
5048
5049         rtl_csi_access_enable_2(tp);
5050
5051         rtl_disable_clock_request(pdev);
5052
5053         RTL_W8(MaxTxPacketSize, TxPacketMax);
5054
5055         if (tp->dev->mtu <= ETH_DATA_LEN)
5056                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5057
5058         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5059 }
5060
5061 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5062 {
5063         void __iomem *ioaddr = tp->mmio_addr;
5064         struct pci_dev *pdev = tp->pci_dev;
5065
5066         rtl_csi_access_enable_1(tp);
5067
5068         if (tp->dev->mtu <= ETH_DATA_LEN)
5069                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5070
5071         RTL_W8(MaxTxPacketSize, TxPacketMax);
5072
5073         rtl_disable_clock_request(pdev);
5074 }
5075
5076 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5077 {
5078         void __iomem *ioaddr = tp->mmio_addr;
5079         struct pci_dev *pdev = tp->pci_dev;
5080         static const struct ephy_info e_info_8168d_4[] = {
5081                 { 0x0b, ~0,     0x48 },
5082                 { 0x19, 0x20,   0x50 },
5083                 { 0x0c, ~0,     0x20 }
5084         };
5085         int i;
5086
5087         rtl_csi_access_enable_1(tp);
5088
5089         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5090
5091         RTL_W8(MaxTxPacketSize, TxPacketMax);
5092
5093         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5094                 const struct ephy_info *e = e_info_8168d_4 + i;
5095                 u16 w;
5096
5097                 w = rtl_ephy_read(tp, e->offset);
5098                 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5099         }
5100
5101         rtl_enable_clock_request(pdev);
5102 }
5103
5104 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5105 {
5106         void __iomem *ioaddr = tp->mmio_addr;
5107         struct pci_dev *pdev = tp->pci_dev;
5108         static const struct ephy_info e_info_8168e_1[] = {
5109                 { 0x00, 0x0200, 0x0100 },
5110                 { 0x00, 0x0000, 0x0004 },
5111                 { 0x06, 0x0002, 0x0001 },
5112                 { 0x06, 0x0000, 0x0030 },
5113                 { 0x07, 0x0000, 0x2000 },
5114                 { 0x00, 0x0000, 0x0020 },
5115                 { 0x03, 0x5800, 0x2000 },
5116                 { 0x03, 0x0000, 0x0001 },
5117                 { 0x01, 0x0800, 0x1000 },
5118                 { 0x07, 0x0000, 0x4000 },
5119                 { 0x1e, 0x0000, 0x2000 },
5120                 { 0x19, 0xffff, 0xfe6c },
5121                 { 0x0a, 0x0000, 0x0040 }
5122         };
5123
5124         rtl_csi_access_enable_2(tp);
5125
5126         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5127
5128         if (tp->dev->mtu <= ETH_DATA_LEN)
5129                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5130
5131         RTL_W8(MaxTxPacketSize, TxPacketMax);
5132
5133         rtl_disable_clock_request(pdev);
5134
5135         /* Reset tx FIFO pointer */
5136         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5137         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5138
5139         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5140 }
5141
5142 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5143 {
5144         void __iomem *ioaddr = tp->mmio_addr;
5145         struct pci_dev *pdev = tp->pci_dev;
5146         static const struct ephy_info e_info_8168e_2[] = {
5147                 { 0x09, 0x0000, 0x0080 },
5148                 { 0x19, 0x0000, 0x0224 }
5149         };
5150
5151         rtl_csi_access_enable_1(tp);
5152
5153         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5154
5155         if (tp->dev->mtu <= ETH_DATA_LEN)
5156                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5157
5158         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5159         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5160         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5161         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5162         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5163         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5164         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5165         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5166
5167         RTL_W8(MaxTxPacketSize, EarlySize);
5168
5169         rtl_disable_clock_request(pdev);
5170
5171         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5172         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5173
5174         /* Adjust EEE LED frequency */
5175         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5176
5177         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5178         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5179         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5180 }
5181
5182 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5183 {
5184         void __iomem *ioaddr = tp->mmio_addr;
5185         struct pci_dev *pdev = tp->pci_dev;
5186
5187         rtl_csi_access_enable_2(tp);
5188
5189         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5190
5191         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5192         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5193         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5194         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5195         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5196         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5197         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5198         rtl_w1w0_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5199         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5200         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5201
5202         RTL_W8(MaxTxPacketSize, EarlySize);
5203
5204         rtl_disable_clock_request(pdev);
5205
5206         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5207         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5208         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5209         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5210         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5211 }
5212
5213 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5214 {
5215         void __iomem *ioaddr = tp->mmio_addr;
5216         static const struct ephy_info e_info_8168f_1[] = {
5217                 { 0x06, 0x00c0, 0x0020 },
5218                 { 0x08, 0x0001, 0x0002 },
5219                 { 0x09, 0x0000, 0x0080 },
5220                 { 0x19, 0x0000, 0x0224 }
5221         };
5222
5223         rtl_hw_start_8168f(tp);
5224
5225         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5226
5227         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5228
5229         /* Adjust EEE LED frequency */
5230         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5231 }
5232
5233 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5234 {
5235         static const struct ephy_info e_info_8168f_1[] = {
5236                 { 0x06, 0x00c0, 0x0020 },
5237                 { 0x0f, 0xffff, 0x5200 },
5238                 { 0x1e, 0x0000, 0x4000 },
5239                 { 0x19, 0x0000, 0x0224 }
5240         };
5241
5242         rtl_hw_start_8168f(tp);
5243
5244         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5245
5246         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5247 }
5248
5249 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5250 {
5251         void __iomem *ioaddr = tp->mmio_addr;
5252         struct pci_dev *pdev = tp->pci_dev;
5253
5254         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5255
5256         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5257         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5258         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5259         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5260
5261         rtl_csi_access_enable_1(tp);
5262
5263         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5264
5265         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5266         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5267         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5268
5269         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5270         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5271         RTL_W8(MaxTxPacketSize, EarlySize);
5272
5273         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5274         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5275
5276         /* Adjust EEE LED frequency */
5277         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5278
5279         rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5280         rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5281 }
5282
5283 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5284 {
5285         void __iomem *ioaddr = tp->mmio_addr;
5286         static const struct ephy_info e_info_8168g_2[] = {
5287                 { 0x00, 0x0000, 0x0008 },
5288                 { 0x0c, 0x3df0, 0x0200 },
5289                 { 0x19, 0xffff, 0xfc00 },
5290                 { 0x1e, 0xffff, 0x20eb }
5291         };
5292
5293         rtl_hw_start_8168g_1(tp);
5294
5295         /* disable aspm and clock request before access ephy */
5296         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5297         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5298         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5299 }
5300
5301 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5302 {
5303         void __iomem *ioaddr = tp->mmio_addr;
5304         static const struct ephy_info e_info_8411_2[] = {
5305                 { 0x00, 0x0000, 0x0008 },
5306                 { 0x0c, 0x3df0, 0x0200 },
5307                 { 0x0f, 0xffff, 0x5200 },
5308                 { 0x19, 0x0020, 0x0000 },
5309                 { 0x1e, 0x0000, 0x2000 }
5310         };
5311
5312         rtl_hw_start_8168g_1(tp);
5313
5314         /* disable aspm and clock request before access ephy */
5315         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5316         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5317         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5318 }
5319
5320 static void rtl_hw_start_8168(struct net_device *dev)
5321 {
5322         struct rtl8169_private *tp = netdev_priv(dev);
5323         void __iomem *ioaddr = tp->mmio_addr;
5324
5325         RTL_W8(Cfg9346, Cfg9346_Unlock);
5326
5327         RTL_W8(MaxTxPacketSize, TxPacketMax);
5328
5329         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5330
5331         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
5332
5333         RTL_W16(CPlusCmd, tp->cp_cmd);
5334
5335         RTL_W16(IntrMitigate, 0x5151);
5336
5337         /* Work around for RxFIFO overflow. */
5338         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5339                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5340                 tp->event_slow &= ~RxOverflow;
5341         }
5342
5343         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5344
5345         rtl_set_rx_tx_config_registers(tp);
5346
5347         RTL_R8(IntrMask);
5348
5349         switch (tp->mac_version) {
5350         case RTL_GIGA_MAC_VER_11:
5351                 rtl_hw_start_8168bb(tp);
5352                 break;
5353
5354         case RTL_GIGA_MAC_VER_12:
5355         case RTL_GIGA_MAC_VER_17:
5356                 rtl_hw_start_8168bef(tp);
5357                 break;
5358
5359         case RTL_GIGA_MAC_VER_18:
5360                 rtl_hw_start_8168cp_1(tp);
5361                 break;
5362
5363         case RTL_GIGA_MAC_VER_19:
5364                 rtl_hw_start_8168c_1(tp);
5365                 break;
5366
5367         case RTL_GIGA_MAC_VER_20:
5368                 rtl_hw_start_8168c_2(tp);
5369                 break;
5370
5371         case RTL_GIGA_MAC_VER_21:
5372                 rtl_hw_start_8168c_3(tp);
5373                 break;
5374
5375         case RTL_GIGA_MAC_VER_22:
5376                 rtl_hw_start_8168c_4(tp);
5377                 break;
5378
5379         case RTL_GIGA_MAC_VER_23:
5380                 rtl_hw_start_8168cp_2(tp);
5381                 break;
5382
5383         case RTL_GIGA_MAC_VER_24:
5384                 rtl_hw_start_8168cp_3(tp);
5385                 break;
5386
5387         case RTL_GIGA_MAC_VER_25:
5388         case RTL_GIGA_MAC_VER_26:
5389         case RTL_GIGA_MAC_VER_27:
5390                 rtl_hw_start_8168d(tp);
5391                 break;
5392
5393         case RTL_GIGA_MAC_VER_28:
5394                 rtl_hw_start_8168d_4(tp);
5395                 break;
5396
5397         case RTL_GIGA_MAC_VER_31:
5398                 rtl_hw_start_8168dp(tp);
5399                 break;
5400
5401         case RTL_GIGA_MAC_VER_32:
5402         case RTL_GIGA_MAC_VER_33:
5403                 rtl_hw_start_8168e_1(tp);
5404                 break;
5405         case RTL_GIGA_MAC_VER_34:
5406                 rtl_hw_start_8168e_2(tp);
5407                 break;
5408
5409         case RTL_GIGA_MAC_VER_35:
5410         case RTL_GIGA_MAC_VER_36:
5411                 rtl_hw_start_8168f_1(tp);
5412                 break;
5413
5414         case RTL_GIGA_MAC_VER_38:
5415                 rtl_hw_start_8411(tp);
5416                 break;
5417
5418         case RTL_GIGA_MAC_VER_40:
5419         case RTL_GIGA_MAC_VER_41:
5420                 rtl_hw_start_8168g_1(tp);
5421                 break;
5422         case RTL_GIGA_MAC_VER_42:
5423                 rtl_hw_start_8168g_2(tp);
5424                 break;
5425
5426         case RTL_GIGA_MAC_VER_44:
5427                 rtl_hw_start_8411_2(tp);
5428                 break;
5429
5430         default:
5431                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
5432                         dev->name, tp->mac_version);
5433                 break;
5434         }
5435
5436         RTL_W8(Cfg9346, Cfg9346_Lock);
5437
5438         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5439
5440         rtl_set_rx_mode(dev);
5441
5442         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
5443 }
5444
5445 #define R810X_CPCMD_QUIRK_MASK (\
5446         EnableBist | \
5447         Mac_dbgo_oe | \
5448         Force_half_dup | \
5449         Force_rxflow_en | \
5450         Force_txflow_en | \
5451         Cxpl_dbg_sel | \
5452         ASF | \
5453         PktCntrDisable | \
5454         Mac_dbgo_sel)
5455
5456 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5457 {
5458         void __iomem *ioaddr = tp->mmio_addr;
5459         struct pci_dev *pdev = tp->pci_dev;
5460         static const struct ephy_info e_info_8102e_1[] = {
5461                 { 0x01, 0, 0x6e65 },
5462                 { 0x02, 0, 0x091f },
5463                 { 0x03, 0, 0xc2f9 },
5464                 { 0x06, 0, 0xafb5 },
5465                 { 0x07, 0, 0x0e00 },
5466                 { 0x19, 0, 0xec80 },
5467                 { 0x01, 0, 0x2e65 },
5468                 { 0x01, 0, 0x6e65 }
5469         };
5470         u8 cfg1;
5471
5472         rtl_csi_access_enable_2(tp);
5473
5474         RTL_W8(DBG_REG, FIX_NAK_1);
5475
5476         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5477
5478         RTL_W8(Config1,
5479                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5480         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5481
5482         cfg1 = RTL_R8(Config1);
5483         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5484                 RTL_W8(Config1, cfg1 & ~LEDS0);
5485
5486         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5487 }
5488
5489 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5490 {
5491         void __iomem *ioaddr = tp->mmio_addr;
5492         struct pci_dev *pdev = tp->pci_dev;
5493
5494         rtl_csi_access_enable_2(tp);
5495
5496         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5497
5498         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5499         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5500 }
5501
5502 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5503 {
5504         rtl_hw_start_8102e_2(tp);
5505
5506         rtl_ephy_write(tp, 0x03, 0xc2f9);
5507 }
5508
5509 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5510 {
5511         void __iomem *ioaddr = tp->mmio_addr;
5512         static const struct ephy_info e_info_8105e_1[] = {
5513                 { 0x07, 0, 0x4000 },
5514                 { 0x19, 0, 0x0200 },
5515                 { 0x19, 0, 0x0020 },
5516                 { 0x1e, 0, 0x2000 },
5517                 { 0x03, 0, 0x0001 },
5518                 { 0x19, 0, 0x0100 },
5519                 { 0x19, 0, 0x0004 },
5520                 { 0x0a, 0, 0x0020 }
5521         };
5522
5523         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5524         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5525
5526         /* Disable Early Tally Counter */
5527         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5528
5529         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5530         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5531
5532         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5533 }
5534
5535 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5536 {
5537         rtl_hw_start_8105e_1(tp);
5538         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5539 }
5540
5541 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5542 {
5543         void __iomem *ioaddr = tp->mmio_addr;
5544         static const struct ephy_info e_info_8402[] = {
5545                 { 0x19, 0xffff, 0xff64 },
5546                 { 0x1e, 0, 0x4000 }
5547         };
5548
5549         rtl_csi_access_enable_2(tp);
5550
5551         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5552         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5553
5554         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5555         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5556
5557         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5558
5559         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5560
5561         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5562         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5563         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5564         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5565         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5566         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5567         rtl_w1w0_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5568 }
5569
5570 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5571 {
5572         void __iomem *ioaddr = tp->mmio_addr;
5573
5574         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5575         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5576
5577         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5578         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5579         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
5580 }
5581
5582 static void rtl_hw_start_8101(struct net_device *dev)
5583 {
5584         struct rtl8169_private *tp = netdev_priv(dev);
5585         void __iomem *ioaddr = tp->mmio_addr;
5586         struct pci_dev *pdev = tp->pci_dev;
5587
5588         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5589                 tp->event_slow &= ~RxFIFOOver;
5590
5591         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5592             tp->mac_version == RTL_GIGA_MAC_VER_16)
5593                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
5594                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5595
5596         RTL_W8(Cfg9346, Cfg9346_Unlock);
5597
5598         RTL_W8(MaxTxPacketSize, TxPacketMax);
5599
5600         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5601
5602         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5603         RTL_W16(CPlusCmd, tp->cp_cmd);
5604
5605         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5606
5607         rtl_set_rx_tx_config_registers(tp);
5608
5609         switch (tp->mac_version) {
5610         case RTL_GIGA_MAC_VER_07:
5611                 rtl_hw_start_8102e_1(tp);
5612                 break;
5613
5614         case RTL_GIGA_MAC_VER_08:
5615                 rtl_hw_start_8102e_3(tp);
5616                 break;
5617
5618         case RTL_GIGA_MAC_VER_09:
5619                 rtl_hw_start_8102e_2(tp);
5620                 break;
5621
5622         case RTL_GIGA_MAC_VER_29:
5623                 rtl_hw_start_8105e_1(tp);
5624                 break;
5625         case RTL_GIGA_MAC_VER_30:
5626                 rtl_hw_start_8105e_2(tp);
5627                 break;
5628
5629         case RTL_GIGA_MAC_VER_37:
5630                 rtl_hw_start_8402(tp);
5631                 break;
5632
5633         case RTL_GIGA_MAC_VER_39:
5634                 rtl_hw_start_8106(tp);
5635                 break;
5636         case RTL_GIGA_MAC_VER_43:
5637                 rtl_hw_start_8168g_2(tp);
5638                 break;
5639         }
5640
5641         RTL_W8(Cfg9346, Cfg9346_Lock);
5642
5643         RTL_W16(IntrMitigate, 0x0000);
5644
5645         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5646
5647         rtl_set_rx_mode(dev);
5648
5649         RTL_R8(IntrMask);
5650
5651         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5652 }
5653
5654 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5655 {
5656         struct rtl8169_private *tp = netdev_priv(dev);
5657
5658         if (new_mtu < ETH_ZLEN ||
5659             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5660                 return -EINVAL;
5661
5662         if (new_mtu > ETH_DATA_LEN)
5663                 rtl_hw_jumbo_enable(tp);
5664         else
5665                 rtl_hw_jumbo_disable(tp);
5666
5667         dev->mtu = new_mtu;
5668         netdev_update_features(dev);
5669
5670         return 0;
5671 }
5672
5673 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5674 {
5675         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5676         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5677 }
5678
5679 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5680                                      void **data_buff, struct RxDesc *desc)
5681 {
5682         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5683                          DMA_FROM_DEVICE);
5684
5685         kfree(*data_buff);
5686         *data_buff = NULL;
5687         rtl8169_make_unusable_by_asic(desc);
5688 }
5689
5690 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5691 {
5692         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5693
5694         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5695 }
5696
5697 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5698                                        u32 rx_buf_sz)
5699 {
5700         desc->addr = cpu_to_le64(mapping);
5701         wmb();
5702         rtl8169_mark_to_asic(desc, rx_buf_sz);
5703 }
5704
5705 static inline void *rtl8169_align(void *data)
5706 {
5707         return (void *)ALIGN((long)data, 16);
5708 }
5709
5710 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5711                                              struct RxDesc *desc)
5712 {
5713         void *data;
5714         dma_addr_t mapping;
5715         struct device *d = &tp->pci_dev->dev;
5716         struct net_device *dev = tp->dev;
5717         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5718
5719         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5720         if (!data)
5721                 return NULL;
5722
5723         if (rtl8169_align(data) != data) {
5724                 kfree(data);
5725                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5726                 if (!data)
5727                         return NULL;
5728         }
5729
5730         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5731                                  DMA_FROM_DEVICE);
5732         if (unlikely(dma_mapping_error(d, mapping))) {
5733                 if (net_ratelimit())
5734                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5735                 goto err_out;
5736         }
5737
5738         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5739         return data;
5740
5741 err_out:
5742         kfree(data);
5743         return NULL;
5744 }
5745
5746 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5747 {
5748         unsigned int i;
5749
5750         for (i = 0; i < NUM_RX_DESC; i++) {
5751                 if (tp->Rx_databuff[i]) {
5752                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5753                                             tp->RxDescArray + i);
5754                 }
5755         }
5756 }
5757
5758 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5759 {
5760         desc->opts1 |= cpu_to_le32(RingEnd);
5761 }
5762
5763 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5764 {
5765         unsigned int i;
5766
5767         for (i = 0; i < NUM_RX_DESC; i++) {
5768                 void *data;
5769
5770                 if (tp->Rx_databuff[i])
5771                         continue;
5772
5773                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5774                 if (!data) {
5775                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5776                         goto err_out;
5777                 }
5778                 tp->Rx_databuff[i] = data;
5779         }
5780
5781         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5782         return 0;
5783
5784 err_out:
5785         rtl8169_rx_clear(tp);
5786         return -ENOMEM;
5787 }
5788
5789 static int rtl8169_init_ring(struct net_device *dev)
5790 {
5791         struct rtl8169_private *tp = netdev_priv(dev);
5792
5793         rtl8169_init_ring_indexes(tp);
5794
5795         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5796         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5797
5798         return rtl8169_rx_fill(tp);
5799 }
5800
5801 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5802                                  struct TxDesc *desc)
5803 {
5804         unsigned int len = tx_skb->len;
5805
5806         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5807
5808         desc->opts1 = 0x00;
5809         desc->opts2 = 0x00;
5810         desc->addr = 0x00;
5811         tx_skb->len = 0;
5812 }
5813
5814 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5815                                    unsigned int n)
5816 {
5817         unsigned int i;
5818
5819         for (i = 0; i < n; i++) {
5820                 unsigned int entry = (start + i) % NUM_TX_DESC;
5821                 struct ring_info *tx_skb = tp->tx_skb + entry;
5822                 unsigned int len = tx_skb->len;
5823
5824                 if (len) {
5825                         struct sk_buff *skb = tx_skb->skb;
5826
5827                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5828                                              tp->TxDescArray + entry);
5829                         if (skb) {
5830                                 tp->dev->stats.tx_dropped++;
5831                                 dev_kfree_skb(skb);
5832                                 tx_skb->skb = NULL;
5833                         }
5834                 }
5835         }
5836 }
5837
5838 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5839 {
5840         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5841         tp->cur_tx = tp->dirty_tx = 0;
5842 }
5843
5844 static void rtl_reset_work(struct rtl8169_private *tp)
5845 {
5846         struct net_device *dev = tp->dev;
5847         int i;
5848
5849         napi_disable(&tp->napi);
5850         netif_stop_queue(dev);
5851         synchronize_sched();
5852
5853         rtl8169_hw_reset(tp);
5854
5855         for (i = 0; i < NUM_RX_DESC; i++)
5856                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5857
5858         rtl8169_tx_clear(tp);
5859         rtl8169_init_ring_indexes(tp);
5860
5861         napi_enable(&tp->napi);
5862         rtl_hw_start(dev);
5863         netif_wake_queue(dev);
5864         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5865 }
5866
5867 static void rtl8169_tx_timeout(struct net_device *dev)
5868 {
5869         struct rtl8169_private *tp = netdev_priv(dev);
5870
5871         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5872 }
5873
5874 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5875                               u32 *opts)
5876 {
5877         struct skb_shared_info *info = skb_shinfo(skb);
5878         unsigned int cur_frag, entry;
5879         struct TxDesc * uninitialized_var(txd);
5880         struct device *d = &tp->pci_dev->dev;
5881
5882         entry = tp->cur_tx;
5883         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5884                 const skb_frag_t *frag = info->frags + cur_frag;
5885                 dma_addr_t mapping;
5886                 u32 status, len;
5887                 void *addr;
5888
5889                 entry = (entry + 1) % NUM_TX_DESC;
5890
5891                 txd = tp->TxDescArray + entry;
5892                 len = skb_frag_size(frag);
5893                 addr = skb_frag_address(frag);
5894                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5895                 if (unlikely(dma_mapping_error(d, mapping))) {
5896                         if (net_ratelimit())
5897                                 netif_err(tp, drv, tp->dev,
5898                                           "Failed to map TX fragments DMA!\n");
5899                         goto err_out;
5900                 }
5901
5902                 /* Anti gcc 2.95.3 bugware (sic) */
5903                 status = opts[0] | len |
5904                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5905
5906                 txd->opts1 = cpu_to_le32(status);
5907                 txd->opts2 = cpu_to_le32(opts[1]);
5908                 txd->addr = cpu_to_le64(mapping);
5909
5910                 tp->tx_skb[entry].len = len;
5911         }
5912
5913         if (cur_frag) {
5914                 tp->tx_skb[entry].skb = skb;
5915                 txd->opts1 |= cpu_to_le32(LastFrag);
5916         }
5917
5918         return cur_frag;
5919
5920 err_out:
5921         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5922         return -EIO;
5923 }
5924
5925 static bool rtl_skb_pad(struct sk_buff *skb)
5926 {
5927         if (skb_padto(skb, ETH_ZLEN))
5928                 return false;
5929         skb_put(skb, ETH_ZLEN - skb->len);
5930         return true;
5931 }
5932
5933 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5934 {
5935         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5936 }
5937
5938 static inline bool rtl8169_tso_csum(struct rtl8169_private *tp,
5939                                     struct sk_buff *skb, u32 *opts)
5940 {
5941         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5942         u32 mss = skb_shinfo(skb)->gso_size;
5943         int offset = info->opts_offset;
5944
5945         if (mss) {
5946                 opts[0] |= TD_LSO;
5947                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5948         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5949                 const struct iphdr *ip = ip_hdr(skb);
5950
5951                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5952                         return skb_checksum_help(skb) == 0 && rtl_skb_pad(skb);
5953
5954                 if (ip->protocol == IPPROTO_TCP)
5955                         opts[offset] |= info->checksum.tcp;
5956                 else if (ip->protocol == IPPROTO_UDP)
5957                         opts[offset] |= info->checksum.udp;
5958                 else
5959                         WARN_ON_ONCE(1);
5960         } else {
5961                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5962                         return rtl_skb_pad(skb);
5963         }
5964         return true;
5965 }
5966
5967 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5968                                       struct net_device *dev)
5969 {
5970         struct rtl8169_private *tp = netdev_priv(dev);
5971         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5972         struct TxDesc *txd = tp->TxDescArray + entry;
5973         void __iomem *ioaddr = tp->mmio_addr;
5974         struct device *d = &tp->pci_dev->dev;
5975         dma_addr_t mapping;
5976         u32 status, len;
5977         u32 opts[2];
5978         int frags;
5979
5980         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
5981                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5982                 goto err_stop_0;
5983         }
5984
5985         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5986                 goto err_stop_0;
5987
5988         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5989         opts[0] = DescOwn;
5990
5991         if (!rtl8169_tso_csum(tp, skb, opts))
5992                 goto err_update_stats;
5993
5994         len = skb_headlen(skb);
5995         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5996         if (unlikely(dma_mapping_error(d, mapping))) {
5997                 if (net_ratelimit())
5998                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5999                 goto err_dma_0;
6000         }
6001
6002         tp->tx_skb[entry].len = len;
6003         txd->addr = cpu_to_le64(mapping);
6004
6005         frags = rtl8169_xmit_frags(tp, skb, opts);
6006         if (frags < 0)
6007                 goto err_dma_1;
6008         else if (frags)
6009                 opts[0] |= FirstFrag;
6010         else {
6011                 opts[0] |= FirstFrag | LastFrag;
6012                 tp->tx_skb[entry].skb = skb;
6013         }
6014
6015         txd->opts2 = cpu_to_le32(opts[1]);
6016
6017         skb_tx_timestamp(skb);
6018
6019         wmb();
6020
6021         /* Anti gcc 2.95.3 bugware (sic) */
6022         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6023         txd->opts1 = cpu_to_le32(status);
6024
6025         tp->cur_tx += frags + 1;
6026
6027         wmb();
6028
6029         RTL_W8(TxPoll, NPQ);
6030
6031         mmiowb();
6032
6033         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6034                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6035                  * not miss a ring update when it notices a stopped queue.
6036                  */
6037                 smp_wmb();
6038                 netif_stop_queue(dev);
6039                 /* Sync with rtl_tx:
6040                  * - publish queue status and cur_tx ring index (write barrier)
6041                  * - refresh dirty_tx ring index (read barrier).
6042                  * May the current thread have a pessimistic view of the ring
6043                  * status and forget to wake up queue, a racing rtl_tx thread
6044                  * can't.
6045                  */
6046                 smp_mb();
6047                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6048                         netif_wake_queue(dev);
6049         }
6050
6051         return NETDEV_TX_OK;
6052
6053 err_dma_1:
6054         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6055 err_dma_0:
6056         dev_kfree_skb(skb);
6057 err_update_stats:
6058         dev->stats.tx_dropped++;
6059         return NETDEV_TX_OK;
6060
6061 err_stop_0:
6062         netif_stop_queue(dev);
6063         dev->stats.tx_dropped++;
6064         return NETDEV_TX_BUSY;
6065 }
6066
6067 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6068 {
6069         struct rtl8169_private *tp = netdev_priv(dev);
6070         struct pci_dev *pdev = tp->pci_dev;
6071         u16 pci_status, pci_cmd;
6072
6073         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6074         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6075
6076         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6077                   pci_cmd, pci_status);
6078
6079         /*
6080          * The recovery sequence below admits a very elaborated explanation:
6081          * - it seems to work;
6082          * - I did not see what else could be done;
6083          * - it makes iop3xx happy.
6084          *
6085          * Feel free to adjust to your needs.
6086          */
6087         if (pdev->broken_parity_status)
6088                 pci_cmd &= ~PCI_COMMAND_PARITY;
6089         else
6090                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6091
6092         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6093
6094         pci_write_config_word(pdev, PCI_STATUS,
6095                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6096                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6097                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6098
6099         /* The infamous DAC f*ckup only happens at boot time */
6100         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6101                 void __iomem *ioaddr = tp->mmio_addr;
6102
6103                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6104                 tp->cp_cmd &= ~PCIDAC;
6105                 RTL_W16(CPlusCmd, tp->cp_cmd);
6106                 dev->features &= ~NETIF_F_HIGHDMA;
6107         }
6108
6109         rtl8169_hw_reset(tp);
6110
6111         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6112 }
6113
6114 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6115 {
6116         unsigned int dirty_tx, tx_left;
6117
6118         dirty_tx = tp->dirty_tx;
6119         smp_rmb();
6120         tx_left = tp->cur_tx - dirty_tx;
6121
6122         while (tx_left > 0) {
6123                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6124                 struct ring_info *tx_skb = tp->tx_skb + entry;
6125                 u32 status;
6126
6127                 rmb();
6128                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6129                 if (status & DescOwn)
6130                         break;
6131
6132                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6133                                      tp->TxDescArray + entry);
6134                 if (status & LastFrag) {
6135                         u64_stats_update_begin(&tp->tx_stats.syncp);
6136                         tp->tx_stats.packets++;
6137                         tp->tx_stats.bytes += tx_skb->skb->len;
6138                         u64_stats_update_end(&tp->tx_stats.syncp);
6139                         dev_kfree_skb(tx_skb->skb);
6140                         tx_skb->skb = NULL;
6141                 }
6142                 dirty_tx++;
6143                 tx_left--;
6144         }
6145
6146         if (tp->dirty_tx != dirty_tx) {
6147                 tp->dirty_tx = dirty_tx;
6148                 /* Sync with rtl8169_start_xmit:
6149                  * - publish dirty_tx ring index (write barrier)
6150                  * - refresh cur_tx ring index and queue status (read barrier)
6151                  * May the current thread miss the stopped queue condition,
6152                  * a racing xmit thread can only have a right view of the
6153                  * ring status.
6154                  */
6155                 smp_mb();
6156                 if (netif_queue_stopped(dev) &&
6157                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6158                         netif_wake_queue(dev);
6159                 }
6160                 /*
6161                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6162                  * too close. Let's kick an extra TxPoll request when a burst
6163                  * of start_xmit activity is detected (if it is not detected,
6164                  * it is slow enough). -- FR
6165                  */
6166                 if (tp->cur_tx != dirty_tx) {
6167                         void __iomem *ioaddr = tp->mmio_addr;
6168
6169                         RTL_W8(TxPoll, NPQ);
6170                 }
6171         }
6172 }
6173
6174 static inline int rtl8169_fragmented_frame(u32 status)
6175 {
6176         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6177 }
6178
6179 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6180 {
6181         u32 status = opts1 & RxProtoMask;
6182
6183         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6184             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6185                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6186         else
6187                 skb_checksum_none_assert(skb);
6188 }
6189
6190 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6191                                            struct rtl8169_private *tp,
6192                                            int pkt_size,
6193                                            dma_addr_t addr)
6194 {
6195         struct sk_buff *skb;
6196         struct device *d = &tp->pci_dev->dev;
6197
6198         data = rtl8169_align(data);
6199         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6200         prefetch(data);
6201         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
6202         if (skb)
6203                 memcpy(skb->data, data, pkt_size);
6204         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6205
6206         return skb;
6207 }
6208
6209 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6210 {
6211         unsigned int cur_rx, rx_left;
6212         unsigned int count;
6213
6214         cur_rx = tp->cur_rx;
6215
6216         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6217                 unsigned int entry = cur_rx % NUM_RX_DESC;
6218                 struct RxDesc *desc = tp->RxDescArray + entry;
6219                 u32 status;
6220
6221                 rmb();
6222                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
6223
6224                 if (status & DescOwn)
6225                         break;
6226                 if (unlikely(status & RxRES)) {
6227                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6228                                    status);
6229                         dev->stats.rx_errors++;
6230                         if (status & (RxRWT | RxRUNT))
6231                                 dev->stats.rx_length_errors++;
6232                         if (status & RxCRC)
6233                                 dev->stats.rx_crc_errors++;
6234                         if (status & RxFOVF) {
6235                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6236                                 dev->stats.rx_fifo_errors++;
6237                         }
6238                         if ((status & (RxRUNT | RxCRC)) &&
6239                             !(status & (RxRWT | RxFOVF)) &&
6240                             (dev->features & NETIF_F_RXALL))
6241                                 goto process_pkt;
6242                 } else {
6243                         struct sk_buff *skb;
6244                         dma_addr_t addr;
6245                         int pkt_size;
6246
6247 process_pkt:
6248                         addr = le64_to_cpu(desc->addr);
6249                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6250                                 pkt_size = (status & 0x00003fff) - 4;
6251                         else
6252                                 pkt_size = status & 0x00003fff;
6253
6254                         /*
6255                          * The driver does not support incoming fragmented
6256                          * frames. They are seen as a symptom of over-mtu
6257                          * sized frames.
6258                          */
6259                         if (unlikely(rtl8169_fragmented_frame(status))) {
6260                                 dev->stats.rx_dropped++;
6261                                 dev->stats.rx_length_errors++;
6262                                 goto release_descriptor;
6263                         }
6264
6265                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6266                                                   tp, pkt_size, addr);
6267                         if (!skb) {
6268                                 dev->stats.rx_dropped++;
6269                                 goto release_descriptor;
6270                         }
6271
6272                         rtl8169_rx_csum(skb, status);
6273                         skb_put(skb, pkt_size);
6274                         skb->protocol = eth_type_trans(skb, dev);
6275
6276                         rtl8169_rx_vlan_tag(desc, skb);
6277
6278                         napi_gro_receive(&tp->napi, skb);
6279
6280                         u64_stats_update_begin(&tp->rx_stats.syncp);
6281                         tp->rx_stats.packets++;
6282                         tp->rx_stats.bytes += pkt_size;
6283                         u64_stats_update_end(&tp->rx_stats.syncp);
6284                 }
6285 release_descriptor:
6286                 desc->opts2 = 0;
6287                 wmb();
6288                 rtl8169_mark_to_asic(desc, rx_buf_sz);
6289         }
6290
6291         count = cur_rx - tp->cur_rx;
6292         tp->cur_rx = cur_rx;
6293
6294         return count;
6295 }
6296
6297 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6298 {
6299         struct net_device *dev = dev_instance;
6300         struct rtl8169_private *tp = netdev_priv(dev);
6301         int handled = 0;
6302         u16 status;
6303
6304         status = rtl_get_events(tp);
6305         if (status && status != 0xffff) {
6306                 status &= RTL_EVENT_NAPI | tp->event_slow;
6307                 if (status) {
6308                         handled = 1;
6309
6310                         rtl_irq_disable(tp);
6311                         napi_schedule(&tp->napi);
6312                 }
6313         }
6314         return IRQ_RETVAL(handled);
6315 }
6316
6317 /*
6318  * Workqueue context.
6319  */
6320 static void rtl_slow_event_work(struct rtl8169_private *tp)
6321 {
6322         struct net_device *dev = tp->dev;
6323         u16 status;
6324
6325         status = rtl_get_events(tp) & tp->event_slow;
6326         rtl_ack_events(tp, status);
6327
6328         if (unlikely(status & RxFIFOOver)) {
6329                 switch (tp->mac_version) {
6330                 /* Work around for rx fifo overflow */
6331                 case RTL_GIGA_MAC_VER_11:
6332                         netif_stop_queue(dev);
6333                         /* XXX - Hack alert. See rtl_task(). */
6334                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6335                 default:
6336                         break;
6337                 }
6338         }
6339
6340         if (unlikely(status & SYSErr))
6341                 rtl8169_pcierr_interrupt(dev);
6342
6343         if (status & LinkChg)
6344                 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
6345
6346         rtl_irq_enable_all(tp);
6347 }
6348
6349 static void rtl_task(struct work_struct *work)
6350 {
6351         static const struct {
6352                 int bitnr;
6353                 void (*action)(struct rtl8169_private *);
6354         } rtl_work[] = {
6355                 /* XXX - keep rtl_slow_event_work() as first element. */
6356                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6357                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6358                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
6359         };
6360         struct rtl8169_private *tp =
6361                 container_of(work, struct rtl8169_private, wk.work);
6362         struct net_device *dev = tp->dev;
6363         int i;
6364
6365         rtl_lock_work(tp);
6366
6367         if (!netif_running(dev) ||
6368             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6369                 goto out_unlock;
6370
6371         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6372                 bool pending;
6373
6374                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6375                 if (pending)
6376                         rtl_work[i].action(tp);
6377         }
6378
6379 out_unlock:
6380         rtl_unlock_work(tp);
6381 }
6382
6383 static int rtl8169_poll(struct napi_struct *napi, int budget)
6384 {
6385         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6386         struct net_device *dev = tp->dev;
6387         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6388         int work_done= 0;
6389         u16 status;
6390
6391         status = rtl_get_events(tp);
6392         rtl_ack_events(tp, status & ~tp->event_slow);
6393
6394         if (status & RTL_EVENT_NAPI_RX)
6395                 work_done = rtl_rx(dev, tp, (u32) budget);
6396
6397         if (status & RTL_EVENT_NAPI_TX)
6398                 rtl_tx(dev, tp);
6399
6400         if (status & tp->event_slow) {
6401                 enable_mask &= ~tp->event_slow;
6402
6403                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6404         }
6405
6406         if (work_done < budget) {
6407                 napi_complete(napi);
6408
6409                 rtl_irq_enable(tp, enable_mask);
6410                 mmiowb();
6411         }
6412
6413         return work_done;
6414 }
6415
6416 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
6417 {
6418         struct rtl8169_private *tp = netdev_priv(dev);
6419
6420         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6421                 return;
6422
6423         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
6424         RTL_W32(RxMissed, 0);
6425 }
6426
6427 static void rtl8169_down(struct net_device *dev)
6428 {
6429         struct rtl8169_private *tp = netdev_priv(dev);
6430         void __iomem *ioaddr = tp->mmio_addr;
6431
6432         del_timer_sync(&tp->timer);
6433
6434         napi_disable(&tp->napi);
6435         netif_stop_queue(dev);
6436
6437         rtl8169_hw_reset(tp);
6438         /*
6439          * At this point device interrupts can not be enabled in any function,
6440          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6441          * and napi is disabled (rtl8169_poll).
6442          */
6443         rtl8169_rx_missed(dev, ioaddr);
6444
6445         /* Give a racing hard_start_xmit a few cycles to complete. */
6446         synchronize_sched();
6447
6448         rtl8169_tx_clear(tp);
6449
6450         rtl8169_rx_clear(tp);
6451
6452         rtl_pll_power_down(tp);
6453 }
6454
6455 static int rtl8169_close(struct net_device *dev)
6456 {
6457         struct rtl8169_private *tp = netdev_priv(dev);
6458         struct pci_dev *pdev = tp->pci_dev;
6459
6460         pm_runtime_get_sync(&pdev->dev);
6461
6462         /* Update counters before going down */
6463         rtl8169_update_counters(dev);
6464
6465         rtl_lock_work(tp);
6466         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6467
6468         rtl8169_down(dev);
6469         rtl_unlock_work(tp);
6470
6471         cancel_work_sync(&tp->wk.work);
6472
6473         free_irq(pdev->irq, dev);
6474
6475         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6476                           tp->RxPhyAddr);
6477         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6478                           tp->TxPhyAddr);
6479         tp->TxDescArray = NULL;
6480         tp->RxDescArray = NULL;
6481
6482         pm_runtime_put_sync(&pdev->dev);
6483
6484         return 0;
6485 }
6486
6487 #ifdef CONFIG_NET_POLL_CONTROLLER
6488 static void rtl8169_netpoll(struct net_device *dev)
6489 {
6490         struct rtl8169_private *tp = netdev_priv(dev);
6491
6492         rtl8169_interrupt(tp->pci_dev->irq, dev);
6493 }
6494 #endif
6495
6496 static int rtl_open(struct net_device *dev)
6497 {
6498         struct rtl8169_private *tp = netdev_priv(dev);
6499         void __iomem *ioaddr = tp->mmio_addr;
6500         struct pci_dev *pdev = tp->pci_dev;
6501         int retval = -ENOMEM;
6502
6503         pm_runtime_get_sync(&pdev->dev);
6504
6505         /*
6506          * Rx and Tx descriptors needs 256 bytes alignment.
6507          * dma_alloc_coherent provides more.
6508          */
6509         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6510                                              &tp->TxPhyAddr, GFP_KERNEL);
6511         if (!tp->TxDescArray)
6512                 goto err_pm_runtime_put;
6513
6514         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6515                                              &tp->RxPhyAddr, GFP_KERNEL);
6516         if (!tp->RxDescArray)
6517                 goto err_free_tx_0;
6518
6519         retval = rtl8169_init_ring(dev);
6520         if (retval < 0)
6521                 goto err_free_rx_1;
6522
6523         INIT_WORK(&tp->wk.work, rtl_task);
6524
6525         smp_mb();
6526
6527         rtl_request_firmware(tp);
6528
6529         retval = request_irq(pdev->irq, rtl8169_interrupt,
6530                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
6531                              dev->name, dev);
6532         if (retval < 0)
6533                 goto err_release_fw_2;
6534
6535         rtl_lock_work(tp);
6536
6537         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6538
6539         napi_enable(&tp->napi);
6540
6541         rtl8169_init_phy(dev, tp);
6542
6543         __rtl8169_set_features(dev, dev->features);
6544
6545         rtl_pll_power_up(tp);
6546
6547         rtl_hw_start(dev);
6548
6549         netif_start_queue(dev);
6550
6551         rtl_unlock_work(tp);
6552
6553         tp->saved_wolopts = 0;
6554         pm_runtime_put_noidle(&pdev->dev);
6555
6556         rtl8169_check_link_status(dev, tp, ioaddr);
6557 out:
6558         return retval;
6559
6560 err_release_fw_2:
6561         rtl_release_firmware(tp);
6562         rtl8169_rx_clear(tp);
6563 err_free_rx_1:
6564         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6565                           tp->RxPhyAddr);
6566         tp->RxDescArray = NULL;
6567 err_free_tx_0:
6568         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6569                           tp->TxPhyAddr);
6570         tp->TxDescArray = NULL;
6571 err_pm_runtime_put:
6572         pm_runtime_put_noidle(&pdev->dev);
6573         goto out;
6574 }
6575
6576 static struct rtnl_link_stats64 *
6577 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6578 {
6579         struct rtl8169_private *tp = netdev_priv(dev);
6580         void __iomem *ioaddr = tp->mmio_addr;
6581         unsigned int start;
6582
6583         if (netif_running(dev))
6584                 rtl8169_rx_missed(dev, ioaddr);
6585
6586         do {
6587                 start = u64_stats_fetch_begin_bh(&tp->rx_stats.syncp);
6588                 stats->rx_packets = tp->rx_stats.packets;
6589                 stats->rx_bytes = tp->rx_stats.bytes;
6590         } while (u64_stats_fetch_retry_bh(&tp->rx_stats.syncp, start));
6591
6592
6593         do {
6594                 start = u64_stats_fetch_begin_bh(&tp->tx_stats.syncp);
6595                 stats->tx_packets = tp->tx_stats.packets;
6596                 stats->tx_bytes = tp->tx_stats.bytes;
6597         } while (u64_stats_fetch_retry_bh(&tp->tx_stats.syncp, start));
6598
6599         stats->rx_dropped       = dev->stats.rx_dropped;
6600         stats->tx_dropped       = dev->stats.tx_dropped;
6601         stats->rx_length_errors = dev->stats.rx_length_errors;
6602         stats->rx_errors        = dev->stats.rx_errors;
6603         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6604         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6605         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6606
6607         return stats;
6608 }
6609
6610 static void rtl8169_net_suspend(struct net_device *dev)
6611 {
6612         struct rtl8169_private *tp = netdev_priv(dev);
6613
6614         if (!netif_running(dev))
6615                 return;
6616
6617         netif_device_detach(dev);
6618         netif_stop_queue(dev);
6619
6620         rtl_lock_work(tp);
6621         napi_disable(&tp->napi);
6622         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6623         rtl_unlock_work(tp);
6624
6625         rtl_pll_power_down(tp);
6626 }
6627
6628 #ifdef CONFIG_PM
6629
6630 static int rtl8169_suspend(struct device *device)
6631 {
6632         struct pci_dev *pdev = to_pci_dev(device);
6633         struct net_device *dev = pci_get_drvdata(pdev);
6634
6635         rtl8169_net_suspend(dev);
6636
6637         return 0;
6638 }
6639
6640 static void __rtl8169_resume(struct net_device *dev)
6641 {
6642         struct rtl8169_private *tp = netdev_priv(dev);
6643
6644         netif_device_attach(dev);
6645
6646         rtl_pll_power_up(tp);
6647
6648         rtl_lock_work(tp);
6649         napi_enable(&tp->napi);
6650         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6651         rtl_unlock_work(tp);
6652
6653         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6654 }
6655
6656 static int rtl8169_resume(struct device *device)
6657 {
6658         struct pci_dev *pdev = to_pci_dev(device);
6659         struct net_device *dev = pci_get_drvdata(pdev);
6660         struct rtl8169_private *tp = netdev_priv(dev);
6661
6662         rtl8169_init_phy(dev, tp);
6663
6664         if (netif_running(dev))
6665                 __rtl8169_resume(dev);
6666
6667         return 0;
6668 }
6669
6670 static int rtl8169_runtime_suspend(struct device *device)
6671 {
6672         struct pci_dev *pdev = to_pci_dev(device);
6673         struct net_device *dev = pci_get_drvdata(pdev);
6674         struct rtl8169_private *tp = netdev_priv(dev);
6675
6676         if (!tp->TxDescArray)
6677                 return 0;
6678
6679         rtl_lock_work(tp);
6680         tp->saved_wolopts = __rtl8169_get_wol(tp);
6681         __rtl8169_set_wol(tp, WAKE_ANY);
6682         rtl_unlock_work(tp);
6683
6684         rtl8169_net_suspend(dev);
6685
6686         return 0;
6687 }
6688
6689 static int rtl8169_runtime_resume(struct device *device)
6690 {
6691         struct pci_dev *pdev = to_pci_dev(device);
6692         struct net_device *dev = pci_get_drvdata(pdev);
6693         struct rtl8169_private *tp = netdev_priv(dev);
6694
6695         if (!tp->TxDescArray)
6696                 return 0;
6697
6698         rtl_lock_work(tp);
6699         __rtl8169_set_wol(tp, tp->saved_wolopts);
6700         tp->saved_wolopts = 0;
6701         rtl_unlock_work(tp);
6702
6703         rtl8169_init_phy(dev, tp);
6704
6705         __rtl8169_resume(dev);
6706
6707         return 0;
6708 }
6709
6710 static int rtl8169_runtime_idle(struct device *device)
6711 {
6712         struct pci_dev *pdev = to_pci_dev(device);
6713         struct net_device *dev = pci_get_drvdata(pdev);
6714         struct rtl8169_private *tp = netdev_priv(dev);
6715
6716         return tp->TxDescArray ? -EBUSY : 0;
6717 }
6718
6719 static const struct dev_pm_ops rtl8169_pm_ops = {
6720         .suspend                = rtl8169_suspend,
6721         .resume                 = rtl8169_resume,
6722         .freeze                 = rtl8169_suspend,
6723         .thaw                   = rtl8169_resume,
6724         .poweroff               = rtl8169_suspend,
6725         .restore                = rtl8169_resume,
6726         .runtime_suspend        = rtl8169_runtime_suspend,
6727         .runtime_resume         = rtl8169_runtime_resume,
6728         .runtime_idle           = rtl8169_runtime_idle,
6729 };
6730
6731 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6732
6733 #else /* !CONFIG_PM */
6734
6735 #define RTL8169_PM_OPS  NULL
6736
6737 #endif /* !CONFIG_PM */
6738
6739 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6740 {
6741         void __iomem *ioaddr = tp->mmio_addr;
6742
6743         /* WoL fails with 8168b when the receiver is disabled. */
6744         switch (tp->mac_version) {
6745         case RTL_GIGA_MAC_VER_11:
6746         case RTL_GIGA_MAC_VER_12:
6747         case RTL_GIGA_MAC_VER_17:
6748                 pci_clear_master(tp->pci_dev);
6749
6750                 RTL_W8(ChipCmd, CmdRxEnb);
6751                 /* PCI commit */
6752                 RTL_R8(ChipCmd);
6753                 break;
6754         default:
6755                 break;
6756         }
6757 }
6758
6759 static void rtl_shutdown(struct pci_dev *pdev)
6760 {
6761         struct net_device *dev = pci_get_drvdata(pdev);
6762         struct rtl8169_private *tp = netdev_priv(dev);
6763         struct device *d = &pdev->dev;
6764
6765         pm_runtime_get_sync(d);
6766
6767         rtl8169_net_suspend(dev);
6768
6769         /* Restore original MAC address */
6770         rtl_rar_set(tp, dev->perm_addr);
6771
6772         rtl8169_hw_reset(tp);
6773
6774         if (system_state == SYSTEM_POWER_OFF) {
6775                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6776                         rtl_wol_suspend_quirk(tp);
6777                         rtl_wol_shutdown_quirk(tp);
6778                 }
6779
6780                 pci_wake_from_d3(pdev, true);
6781                 pci_set_power_state(pdev, PCI_D3hot);
6782         }
6783
6784         pm_runtime_put_noidle(d);
6785 }
6786
6787 static void rtl_remove_one(struct pci_dev *pdev)
6788 {
6789         struct net_device *dev = pci_get_drvdata(pdev);
6790         struct rtl8169_private *tp = netdev_priv(dev);
6791
6792         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
6793             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
6794             tp->mac_version == RTL_GIGA_MAC_VER_31) {
6795                 rtl8168_driver_stop(tp);
6796         }
6797
6798         netif_napi_del(&tp->napi);
6799
6800         unregister_netdev(dev);
6801
6802         rtl_release_firmware(tp);
6803
6804         if (pci_dev_run_wake(pdev))
6805                 pm_runtime_get_noresume(&pdev->dev);
6806
6807         /* restore original MAC address */
6808         rtl_rar_set(tp, dev->perm_addr);
6809
6810         rtl_disable_msi(pdev, tp);
6811         rtl8169_release_board(pdev, dev, tp->mmio_addr);
6812         pci_set_drvdata(pdev, NULL);
6813 }
6814
6815 static const struct net_device_ops rtl_netdev_ops = {
6816         .ndo_open               = rtl_open,
6817         .ndo_stop               = rtl8169_close,
6818         .ndo_get_stats64        = rtl8169_get_stats64,
6819         .ndo_start_xmit         = rtl8169_start_xmit,
6820         .ndo_tx_timeout         = rtl8169_tx_timeout,
6821         .ndo_validate_addr      = eth_validate_addr,
6822         .ndo_change_mtu         = rtl8169_change_mtu,
6823         .ndo_fix_features       = rtl8169_fix_features,
6824         .ndo_set_features       = rtl8169_set_features,
6825         .ndo_set_mac_address    = rtl_set_mac_address,
6826         .ndo_do_ioctl           = rtl8169_ioctl,
6827         .ndo_set_rx_mode        = rtl_set_rx_mode,
6828 #ifdef CONFIG_NET_POLL_CONTROLLER
6829         .ndo_poll_controller    = rtl8169_netpoll,
6830 #endif
6831
6832 };
6833
6834 static const struct rtl_cfg_info {
6835         void (*hw_start)(struct net_device *);
6836         unsigned int region;
6837         unsigned int align;
6838         u16 event_slow;
6839         unsigned features;
6840         u8 default_ver;
6841 } rtl_cfg_infos [] = {
6842         [RTL_CFG_0] = {
6843                 .hw_start       = rtl_hw_start_8169,
6844                 .region         = 1,
6845                 .align          = 0,
6846                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6847                 .features       = RTL_FEATURE_GMII,
6848                 .default_ver    = RTL_GIGA_MAC_VER_01,
6849         },
6850         [RTL_CFG_1] = {
6851                 .hw_start       = rtl_hw_start_8168,
6852                 .region         = 2,
6853                 .align          = 8,
6854                 .event_slow     = SYSErr | LinkChg | RxOverflow,
6855                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
6856                 .default_ver    = RTL_GIGA_MAC_VER_11,
6857         },
6858         [RTL_CFG_2] = {
6859                 .hw_start       = rtl_hw_start_8101,
6860                 .region         = 2,
6861                 .align          = 8,
6862                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
6863                                   PCSTimeout,
6864                 .features       = RTL_FEATURE_MSI,
6865                 .default_ver    = RTL_GIGA_MAC_VER_13,
6866         }
6867 };
6868
6869 /* Cfg9346_Unlock assumed. */
6870 static unsigned rtl_try_msi(struct rtl8169_private *tp,
6871                             const struct rtl_cfg_info *cfg)
6872 {
6873         void __iomem *ioaddr = tp->mmio_addr;
6874         unsigned msi = 0;
6875         u8 cfg2;
6876
6877         cfg2 = RTL_R8(Config2) & ~MSIEnable;
6878         if (cfg->features & RTL_FEATURE_MSI) {
6879                 if (pci_enable_msi(tp->pci_dev)) {
6880                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
6881                 } else {
6882                         cfg2 |= MSIEnable;
6883                         msi = RTL_FEATURE_MSI;
6884                 }
6885         }
6886         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6887                 RTL_W8(Config2, cfg2);
6888         return msi;
6889 }
6890
6891 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6892 {
6893         void __iomem *ioaddr = tp->mmio_addr;
6894
6895         return RTL_R8(MCU) & LINK_LIST_RDY;
6896 }
6897
6898 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6899 {
6900         void __iomem *ioaddr = tp->mmio_addr;
6901
6902         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6903 }
6904
6905 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6906 {
6907         void __iomem *ioaddr = tp->mmio_addr;
6908         u32 data;
6909
6910         tp->ocp_base = OCP_STD_PHY_BASE;
6911
6912         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
6913
6914         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6915                 return;
6916
6917         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6918                 return;
6919
6920         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6921         msleep(1);
6922         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6923
6924         data = r8168_mac_ocp_read(tp, 0xe8de);
6925         data &= ~(1 << 14);
6926         r8168_mac_ocp_write(tp, 0xe8de, data);
6927
6928         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6929                 return;
6930
6931         data = r8168_mac_ocp_read(tp, 0xe8de);
6932         data |= (1 << 15);
6933         r8168_mac_ocp_write(tp, 0xe8de, data);
6934
6935         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6936                 return;
6937 }
6938
6939 static void rtl_hw_initialize(struct rtl8169_private *tp)
6940 {
6941         switch (tp->mac_version) {
6942         case RTL_GIGA_MAC_VER_40:
6943         case RTL_GIGA_MAC_VER_41:
6944         case RTL_GIGA_MAC_VER_42:
6945         case RTL_GIGA_MAC_VER_43:
6946         case RTL_GIGA_MAC_VER_44:
6947                 rtl_hw_init_8168g(tp);
6948                 break;
6949
6950         default:
6951                 break;
6952         }
6953 }
6954
6955 static int
6956 rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6957 {
6958         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6959         const unsigned int region = cfg->region;
6960         struct rtl8169_private *tp;
6961         struct mii_if_info *mii;
6962         struct net_device *dev;
6963         void __iomem *ioaddr;
6964         int chipset, i;
6965         int rc;
6966
6967         if (netif_msg_drv(&debug)) {
6968                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
6969                        MODULENAME, RTL8169_VERSION);
6970         }
6971
6972         dev = alloc_etherdev(sizeof (*tp));
6973         if (!dev) {
6974                 rc = -ENOMEM;
6975                 goto out;
6976         }
6977
6978         SET_NETDEV_DEV(dev, &pdev->dev);
6979         dev->netdev_ops = &rtl_netdev_ops;
6980         tp = netdev_priv(dev);
6981         tp->dev = dev;
6982         tp->pci_dev = pdev;
6983         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6984
6985         mii = &tp->mii;
6986         mii->dev = dev;
6987         mii->mdio_read = rtl_mdio_read;
6988         mii->mdio_write = rtl_mdio_write;
6989         mii->phy_id_mask = 0x1f;
6990         mii->reg_num_mask = 0x1f;
6991         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
6992
6993         /* disable ASPM completely as that cause random device stop working
6994          * problems as well as full system hangs for some PCIe devices users */
6995         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6996                                      PCIE_LINK_STATE_CLKPM);
6997
6998         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6999         rc = pci_enable_device(pdev);
7000         if (rc < 0) {
7001                 netif_err(tp, probe, dev, "enable failure\n");
7002                 goto err_out_free_dev_1;
7003         }
7004
7005         if (pci_set_mwi(pdev) < 0)
7006                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
7007
7008         /* make sure PCI base addr 1 is MMIO */
7009         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
7010                 netif_err(tp, probe, dev,
7011                           "region #%d not an MMIO resource, aborting\n",
7012                           region);
7013                 rc = -ENODEV;
7014                 goto err_out_mwi_2;
7015         }
7016
7017         /* check for weird/broken PCI region reporting */
7018         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7019                 netif_err(tp, probe, dev,
7020                           "Invalid PCI region size(s), aborting\n");
7021                 rc = -ENODEV;
7022                 goto err_out_mwi_2;
7023         }
7024
7025         rc = pci_request_regions(pdev, MODULENAME);
7026         if (rc < 0) {
7027                 netif_err(tp, probe, dev, "could not request regions\n");
7028                 goto err_out_mwi_2;
7029         }
7030
7031         tp->cp_cmd = RxChkSum;
7032
7033         if ((sizeof(dma_addr_t) > 4) &&
7034             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
7035                 tp->cp_cmd |= PCIDAC;
7036                 dev->features |= NETIF_F_HIGHDMA;
7037         } else {
7038                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7039                 if (rc < 0) {
7040                         netif_err(tp, probe, dev, "DMA configuration failed\n");
7041                         goto err_out_free_res_3;
7042                 }
7043         }
7044
7045         /* ioremap MMIO region */
7046         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
7047         if (!ioaddr) {
7048                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
7049                 rc = -EIO;
7050                 goto err_out_free_res_3;
7051         }
7052         tp->mmio_addr = ioaddr;
7053
7054         if (!pci_is_pcie(pdev))
7055                 netif_info(tp, probe, dev, "not PCI Express\n");
7056
7057         /* Identify chip attached to board */
7058         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
7059
7060         rtl_init_rxcfg(tp);
7061
7062         rtl_irq_disable(tp);
7063
7064         rtl_hw_initialize(tp);
7065
7066         rtl_hw_reset(tp);
7067
7068         rtl_ack_events(tp, 0xffff);
7069
7070         pci_set_master(pdev);
7071
7072         /*
7073          * Pretend we are using VLANs; This bypasses a nasty bug where
7074          * Interrupts stop flowing on high load on 8110SCd controllers.
7075          */
7076         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7077                 tp->cp_cmd |= RxVlan;
7078
7079         rtl_init_mdio_ops(tp);
7080         rtl_init_pll_power_ops(tp);
7081         rtl_init_jumbo_ops(tp);
7082         rtl_init_csi_ops(tp);
7083
7084         rtl8169_print_mac_version(tp);
7085
7086         chipset = tp->mac_version;
7087         tp->txd_version = rtl_chip_infos[chipset].txd_version;
7088
7089         RTL_W8(Cfg9346, Cfg9346_Unlock);
7090         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
7091         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
7092         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
7093                 tp->features |= RTL_FEATURE_WOL;
7094         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
7095                 tp->features |= RTL_FEATURE_WOL;
7096         tp->features |= rtl_try_msi(tp, cfg);
7097         RTL_W8(Cfg9346, Cfg9346_Lock);
7098
7099         if (rtl_tbi_enabled(tp)) {
7100                 tp->set_speed = rtl8169_set_speed_tbi;
7101                 tp->get_settings = rtl8169_gset_tbi;
7102                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
7103                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
7104                 tp->link_ok = rtl8169_tbi_link_ok;
7105                 tp->do_ioctl = rtl_tbi_ioctl;
7106         } else {
7107                 tp->set_speed = rtl8169_set_speed_xmii;
7108                 tp->get_settings = rtl8169_gset_xmii;
7109                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
7110                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
7111                 tp->link_ok = rtl8169_xmii_link_ok;
7112                 tp->do_ioctl = rtl_xmii_ioctl;
7113         }
7114
7115         mutex_init(&tp->wk.mutex);
7116
7117         /* Get MAC address */
7118         for (i = 0; i < ETH_ALEN; i++)
7119                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
7120
7121         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
7122         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7123
7124         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
7125
7126         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7127          * properly for all devices */
7128         dev->features |= NETIF_F_RXCSUM |
7129                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7130
7131         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7132                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7133                 NETIF_F_HW_VLAN_CTAG_RX;
7134         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7135                 NETIF_F_HIGHDMA;
7136
7137         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7138                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7139                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7140
7141         dev->hw_features |= NETIF_F_RXALL;
7142         dev->hw_features |= NETIF_F_RXFCS;
7143
7144         tp->hw_start = cfg->hw_start;
7145         tp->event_slow = cfg->event_slow;
7146
7147         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
7148                 ~(RxBOVF | RxFOVF) : ~0;
7149
7150         init_timer(&tp->timer);
7151         tp->timer.data = (unsigned long) dev;
7152         tp->timer.function = rtl8169_phy_timer;
7153
7154         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7155
7156         rc = register_netdev(dev);
7157         if (rc < 0)
7158                 goto err_out_msi_4;
7159
7160         pci_set_drvdata(pdev, dev);
7161
7162         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7163                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
7164                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
7165         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7166                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7167                            "tx checksumming: %s]\n",
7168                            rtl_chip_infos[chipset].jumbo_max,
7169                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
7170         }
7171
7172         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7173             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7174             tp->mac_version == RTL_GIGA_MAC_VER_31) {
7175                 rtl8168_driver_start(tp);
7176         }
7177
7178         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
7179
7180         if (pci_dev_run_wake(pdev))
7181                 pm_runtime_put_noidle(&pdev->dev);
7182
7183         netif_carrier_off(dev);
7184
7185 out:
7186         return rc;
7187
7188 err_out_msi_4:
7189         netif_napi_del(&tp->napi);
7190         rtl_disable_msi(pdev, tp);
7191         iounmap(ioaddr);
7192 err_out_free_res_3:
7193         pci_release_regions(pdev);
7194 err_out_mwi_2:
7195         pci_clear_mwi(pdev);
7196         pci_disable_device(pdev);
7197 err_out_free_dev_1:
7198         free_netdev(dev);
7199         goto out;
7200 }
7201
7202 static struct pci_driver rtl8169_pci_driver = {
7203         .name           = MODULENAME,
7204         .id_table       = rtl8169_pci_tbl,
7205         .probe          = rtl_init_one,
7206         .remove         = rtl_remove_one,
7207         .shutdown       = rtl_shutdown,
7208         .driver.pm      = RTL8169_PM_OPS,
7209 };
7210
7211 module_pci_driver(rtl8169_pci_driver);