2 * Copyright 2013 Red Hat Inc.
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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25 #include <subdev/bios.h>
26 #include <subdev/ltcg.h>
30 extern const u8 nvc0_pte_storage_type_map[256];
33 nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
35 struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb);
38 ltcg->tags_free(ltcg, &(*pmem)->tag);
40 nv50_ram_put(pfb, pmem);
44 nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
45 u32 memtype, struct nouveau_mem **pmem)
47 struct nouveau_mm *mm = &pfb->vram;
48 struct nouveau_mm_node *r;
49 struct nouveau_mem *mem;
50 int type = (memtype & 0x0ff);
51 int back = (memtype & 0x800);
52 const bool comp = nvc0_pte_storage_type_map[type] != type;
61 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
65 INIT_LIST_HEAD(&mem->regions);
68 mutex_lock(&pfb->base.mutex);
70 struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb);
72 /* compression only works with lpages */
73 if (align == (1 << (17 - 12))) {
75 ltcg->tags_alloc(ltcg, n, &mem->tag);
78 if (unlikely(!mem->tag))
79 type = nvc0_pte_storage_type_map[type];
85 ret = nouveau_mm_tail(mm, 1, size, ncmin, align, &r);
87 ret = nouveau_mm_head(mm, 1, size, ncmin, align, &r);
89 mutex_unlock(&pfb->base.mutex);
90 pfb->ram->put(pfb, &mem);
94 list_add_tail(&r->rl_entry, &mem->regions);
97 mutex_unlock(&pfb->base.mutex);
99 r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
100 mem->offset = (u64)r->offset << 12;
106 nvc0_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
107 struct nouveau_oclass *oclass, void *data, u32 size,
108 struct nouveau_object **pobject)
110 struct nouveau_fb *pfb = nouveau_fb(parent);
111 struct nouveau_bios *bios = nouveau_bios(pfb);
112 struct nouveau_ram *ram;
113 const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
114 const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
115 u32 parts = nv_rd32(pfb, 0x022438);
116 u32 pmask = nv_rd32(pfb, 0x022554);
117 u32 bsize = nv_rd32(pfb, 0x10f20c);
122 ret = nouveau_ram_create(parent, engine, oclass, &ram);
123 *pobject = nv_object(ram);
127 nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800));
128 nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask);
130 ram->type = nouveau_fb_bios_memtype(bios);
131 ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1;
133 /* read amount of vram attached to each memory controller */
134 for (part = 0; part < parts; part++) {
135 if (!(pmask & (1 << part))) {
136 u32 psize = nv_rd32(pfb, 0x11020c + (part * 0x1000));
137 if (psize != bsize) {
143 nv_debug(pfb, "%d: mem_amount 0x%08x\n", part, psize);
144 ram->size += (u64)psize << 20;
148 /* if all controllers have the same amount attached, there's no holes */
151 length = (ram->size >> 12) - rsvd_head - rsvd_tail;
152 ret = nouveau_mm_init(&pfb->vram, offset, length, 1);
154 /* otherwise, address lowest common amount from 0GiB */
155 ret = nouveau_mm_init(&pfb->vram, rsvd_head,
156 (bsize << 8) * parts, 1);
160 /* and the rest starting from (8GiB + common_size) */
161 offset = (0x0200000000ULL >> 12) + (bsize << 8);
162 length = (ram->size >> 12) - (bsize << 8) - rsvd_tail;
164 ret = nouveau_mm_init(&pfb->vram, offset, length, 0);
166 nouveau_mm_fini(&pfb->vram);
172 ram->get = nvc0_ram_get;
173 ram->put = nvc0_ram_put;
177 struct nouveau_oclass
180 .ofuncs = &(struct nouveau_ofuncs) {
181 .ctor = nvc0_ram_create,
182 .dtor = _nouveau_ram_dtor,
183 .init = _nouveau_ram_init,
184 .fini = _nouveau_ram_fini,