drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139
 140 /* helper to disable agp */
 141 /**
 142  * radeon_agp_disable - AGP disable helper function
 143  *
 144  * @rdev: radeon device pointer
 145  *
 146  * Removes AGP flags and changes the gart callbacks on AGP
 147  * cards when using the internal gart rather than AGP (all asics).
 148  */
 149 void radeon_agp_disable(struct radeon_device *rdev)
 150 {
 151         rdev->flags &= ~RADEON_IS_AGP;
 152         if (rdev->family >= CHIP_R600) {
 153                 DRM_INFO("Forcing AGP to PCIE mode\n");
 154                 rdev->flags |= RADEON_IS_PCIE;
 155         } else if (rdev->family >= CHIP_RV515 ||
 156                         rdev->family == CHIP_RV380 ||
 157                         rdev->family == CHIP_RV410 ||
 158                         rdev->family == CHIP_R423) {
 159                 DRM_INFO("Forcing AGP to PCIE mode\n");
 160                 rdev->flags |= RADEON_IS_PCIE;
 161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 162                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 163         } else {
 164                 DRM_INFO("Forcing AGP to PCI mode\n");
 165                 rdev->flags |= RADEON_IS_PCI;
 166                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 167                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 168         }
 169         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 170 }
 171
 172 /*
 173  * ASIC
 174  */
 175 static struct radeon_asic r100_asic = {
 176         .init = &r100_init,
 177         .fini = &r100_fini,
 178         .suspend = &r100_suspend,
 179         .resume = &r100_resume,
 180         .vga_set_state = &r100_vga_set_state,
 181         .asic_reset = &r100_asic_reset,
 182         .ioctl_wait_idle = NULL,
 183         .gui_idle = &r100_gui_idle,
 184         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 185         .gart = {
 186                 .tlb_flush = &r100_pci_gart_tlb_flush,
 187                 .set_page = &r100_pci_gart_set_page,
 188         },
 189         .ring = {
 190                 [RADEON_RING_TYPE_GFX_INDEX] = {
 191                         .ib_execute = &r100_ring_ib_execute,
 192                         .emit_fence = &r100_fence_ring_emit,
 193                         .emit_semaphore = &r100_semaphore_ring_emit,
 194                         .cs_parse = &r100_cs_parse,
 195                         .ring_start = &r100_ring_start,
 196                         .ring_test = &r100_ring_test,
 197                         .ib_test = &r100_ib_test,
 198                         .is_lockup = &r100_gpu_is_lockup,
 199                         .get_rptr = &radeon_ring_generic_get_rptr,
 200                         .get_wptr = &radeon_ring_generic_get_wptr,
 201                         .set_wptr = &radeon_ring_generic_set_wptr,
 202                 }
 203         },
 204         .irq = {
 205                 .set = &r100_irq_set,
 206                 .process = &r100_irq_process,
 207         },
 208         .display = {
 209                 .bandwidth_update = &r100_bandwidth_update,
 210                 .get_vblank_counter = &r100_get_vblank_counter,
 211                 .wait_for_vblank = &r100_wait_for_vblank,
 212                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 213                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 214         },
 215         .copy = {
 216                 .blit = &r100_copy_blit,
 217                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 218                 .dma = NULL,
 219                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 220                 .copy = &r100_copy_blit,
 221                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 222         },
 223         .surface = {
 224                 .set_reg = r100_set_surface_reg,
 225                 .clear_reg = r100_clear_surface_reg,
 226         },
 227         .hpd = {
 228                 .init = &r100_hpd_init,
 229                 .fini = &r100_hpd_fini,
 230                 .sense = &r100_hpd_sense,
 231                 .set_polarity = &r100_hpd_set_polarity,
 232         },
 233         .pm = {
 234                 .misc = &r100_pm_misc,
 235                 .prepare = &r100_pm_prepare,
 236                 .finish = &r100_pm_finish,
 237                 .init_profile = &r100_pm_init_profile,
 238                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 239                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 240                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 241                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 242                 .set_memory_clock = NULL,
 243                 .get_pcie_lanes = NULL,
 244                 .set_pcie_lanes = NULL,
 245                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 246         },
 247         .pflip = {
 248                 .pre_page_flip = &r100_pre_page_flip,
 249                 .page_flip = &r100_page_flip,
 250                 .post_page_flip = &r100_post_page_flip,
 251         },
 252 };
 253
 254 static struct radeon_asic r200_asic = {
 255         .init = &r100_init,
 256         .fini = &r100_fini,
 257         .suspend = &r100_suspend,
 258         .resume = &r100_resume,
 259         .vga_set_state = &r100_vga_set_state,
 260         .asic_reset = &r100_asic_reset,
 261         .ioctl_wait_idle = NULL,
 262         .gui_idle = &r100_gui_idle,
 263         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 264         .gart = {
 265                 .tlb_flush = &r100_pci_gart_tlb_flush,
 266                 .set_page = &r100_pci_gart_set_page,
 267         },
 268         .ring = {
 269                 [RADEON_RING_TYPE_GFX_INDEX] = {
 270                         .ib_execute = &r100_ring_ib_execute,
 271                         .emit_fence = &r100_fence_ring_emit,
 272                         .emit_semaphore = &r100_semaphore_ring_emit,
 273                         .cs_parse = &r100_cs_parse,
 274                         .ring_start = &r100_ring_start,
 275                         .ring_test = &r100_ring_test,
 276                         .ib_test = &r100_ib_test,
 277                         .is_lockup = &r100_gpu_is_lockup,
 278                         .get_rptr = &radeon_ring_generic_get_rptr,
 279                         .get_wptr = &radeon_ring_generic_get_wptr,
 280                         .set_wptr = &radeon_ring_generic_set_wptr,
 281                 }
 282         },
 283         .irq = {
 284                 .set = &r100_irq_set,
 285                 .process = &r100_irq_process,
 286         },
 287         .display = {
 288                 .bandwidth_update = &r100_bandwidth_update,
 289                 .get_vblank_counter = &r100_get_vblank_counter,
 290                 .wait_for_vblank = &r100_wait_for_vblank,
 291                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 292                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 293         },
 294         .copy = {
 295                 .blit = &r100_copy_blit,
 296                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 297                 .dma = &r200_copy_dma,
 298                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 299                 .copy = &r100_copy_blit,
 300                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 301         },
 302         .surface = {
 303                 .set_reg = r100_set_surface_reg,
 304                 .clear_reg = r100_clear_surface_reg,
 305         },
 306         .hpd = {
 307                 .init = &r100_hpd_init,
 308                 .fini = &r100_hpd_fini,
 309                 .sense = &r100_hpd_sense,
 310                 .set_polarity = &r100_hpd_set_polarity,
 311         },
 312         .pm = {
 313                 .misc = &r100_pm_misc,
 314                 .prepare = &r100_pm_prepare,
 315                 .finish = &r100_pm_finish,
 316                 .init_profile = &r100_pm_init_profile,
 317                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 318                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 319                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 320                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 321                 .set_memory_clock = NULL,
 322                 .get_pcie_lanes = NULL,
 323                 .set_pcie_lanes = NULL,
 324                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 325         },
 326         .pflip = {
 327                 .pre_page_flip = &r100_pre_page_flip,
 328                 .page_flip = &r100_page_flip,
 329                 .post_page_flip = &r100_post_page_flip,
 330         },
 331 };
 332
 333 static struct radeon_asic r300_asic = {
 334         .init = &r300_init,
 335         .fini = &r300_fini,
 336         .suspend = &r300_suspend,
 337         .resume = &r300_resume,
 338         .vga_set_state = &r100_vga_set_state,
 339         .asic_reset = &r300_asic_reset,
 340         .ioctl_wait_idle = NULL,
 341         .gui_idle = &r100_gui_idle,
 342         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 343         .gart = {
 344                 .tlb_flush = &r100_pci_gart_tlb_flush,
 345                 .set_page = &r100_pci_gart_set_page,
 346         },
 347         .ring = {
 348                 [RADEON_RING_TYPE_GFX_INDEX] = {
 349                         .ib_execute = &r100_ring_ib_execute,
 350                         .emit_fence = &r300_fence_ring_emit,
 351                         .emit_semaphore = &r100_semaphore_ring_emit,
 352                         .cs_parse = &r300_cs_parse,
 353                         .ring_start = &r300_ring_start,
 354                         .ring_test = &r100_ring_test,
 355                         .ib_test = &r100_ib_test,
 356                         .is_lockup = &r100_gpu_is_lockup,
 357                         .get_rptr = &radeon_ring_generic_get_rptr,
 358                         .get_wptr = &radeon_ring_generic_get_wptr,
 359                         .set_wptr = &radeon_ring_generic_set_wptr,
 360                 }
 361         },
 362         .irq = {
 363                 .set = &r100_irq_set,
 364                 .process = &r100_irq_process,
 365         },
 366         .display = {
 367                 .bandwidth_update = &r100_bandwidth_update,
 368                 .get_vblank_counter = &r100_get_vblank_counter,
 369                 .wait_for_vblank = &r100_wait_for_vblank,
 370                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 371                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 372         },
 373         .copy = {
 374                 .blit = &r100_copy_blit,
 375                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 376                 .dma = &r200_copy_dma,
 377                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 378                 .copy = &r100_copy_blit,
 379                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 380         },
 381         .surface = {
 382                 .set_reg = r100_set_surface_reg,
 383                 .clear_reg = r100_clear_surface_reg,
 384         },
 385         .hpd = {
 386                 .init = &r100_hpd_init,
 387                 .fini = &r100_hpd_fini,
 388                 .sense = &r100_hpd_sense,
 389                 .set_polarity = &r100_hpd_set_polarity,
 390         },
 391         .pm = {
 392                 .misc = &r100_pm_misc,
 393                 .prepare = &r100_pm_prepare,
 394                 .finish = &r100_pm_finish,
 395                 .init_profile = &r100_pm_init_profile,
 396                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 397                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 398                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 399                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 400                 .set_memory_clock = NULL,
 401                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 402                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 403                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 404         },
 405         .pflip = {
 406                 .pre_page_flip = &r100_pre_page_flip,
 407                 .page_flip = &r100_page_flip,
 408                 .post_page_flip = &r100_post_page_flip,
 409         },
 410 };
 411
 412 static struct radeon_asic r300_asic_pcie = {
 413         .init = &r300_init,
 414         .fini = &r300_fini,
 415         .suspend = &r300_suspend,
 416         .resume = &r300_resume,
 417         .vga_set_state = &r100_vga_set_state,
 418         .asic_reset = &r300_asic_reset,
 419         .ioctl_wait_idle = NULL,
 420         .gui_idle = &r100_gui_idle,
 421         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 422         .gart = {
 423                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 424                 .set_page = &rv370_pcie_gart_set_page,
 425         },
 426         .ring = {
 427                 [RADEON_RING_TYPE_GFX_INDEX] = {
 428                         .ib_execute = &r100_ring_ib_execute,
 429                         .emit_fence = &r300_fence_ring_emit,
 430                         .emit_semaphore = &r100_semaphore_ring_emit,
 431                         .cs_parse = &r300_cs_parse,
 432                         .ring_start = &r300_ring_start,
 433                         .ring_test = &r100_ring_test,
 434                         .ib_test = &r100_ib_test,
 435                         .is_lockup = &r100_gpu_is_lockup,
 436                         .get_rptr = &radeon_ring_generic_get_rptr,
 437                         .get_wptr = &radeon_ring_generic_get_wptr,
 438                         .set_wptr = &radeon_ring_generic_set_wptr,
 439                 }
 440         },
 441         .irq = {
 442                 .set = &r100_irq_set,
 443                 .process = &r100_irq_process,
 444         },
 445         .display = {
 446                 .bandwidth_update = &r100_bandwidth_update,
 447                 .get_vblank_counter = &r100_get_vblank_counter,
 448                 .wait_for_vblank = &r100_wait_for_vblank,
 449                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 450                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 451         },
 452         .copy = {
 453                 .blit = &r100_copy_blit,
 454                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 455                 .dma = &r200_copy_dma,
 456                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 457                 .copy = &r100_copy_blit,
 458                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 459         },
 460         .surface = {
 461                 .set_reg = r100_set_surface_reg,
 462                 .clear_reg = r100_clear_surface_reg,
 463         },
 464         .hpd = {
 465                 .init = &r100_hpd_init,
 466                 .fini = &r100_hpd_fini,
 467                 .sense = &r100_hpd_sense,
 468                 .set_polarity = &r100_hpd_set_polarity,
 469         },
 470         .pm = {
 471                 .misc = &r100_pm_misc,
 472                 .prepare = &r100_pm_prepare,
 473                 .finish = &r100_pm_finish,
 474                 .init_profile = &r100_pm_init_profile,
 475                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 476                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 477                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 478                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 479                 .set_memory_clock = NULL,
 480                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 481                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 482                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 483         },
 484         .pflip = {
 485                 .pre_page_flip = &r100_pre_page_flip,
 486                 .page_flip = &r100_page_flip,
 487                 .post_page_flip = &r100_post_page_flip,
 488         },
 489 };
 490
 491 static struct radeon_asic r420_asic = {
 492         .init = &r420_init,
 493         .fini = &r420_fini,
 494         .suspend = &r420_suspend,
 495         .resume = &r420_resume,
 496         .vga_set_state = &r100_vga_set_state,
 497         .asic_reset = &r300_asic_reset,
 498         .ioctl_wait_idle = NULL,
 499         .gui_idle = &r100_gui_idle,
 500         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 501         .gart = {
 502                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 503                 .set_page = &rv370_pcie_gart_set_page,
 504         },
 505         .ring = {
 506                 [RADEON_RING_TYPE_GFX_INDEX] = {
 507                         .ib_execute = &r100_ring_ib_execute,
 508                         .emit_fence = &r300_fence_ring_emit,
 509                         .emit_semaphore = &r100_semaphore_ring_emit,
 510                         .cs_parse = &r300_cs_parse,
 511                         .ring_start = &r300_ring_start,
 512                         .ring_test = &r100_ring_test,
 513                         .ib_test = &r100_ib_test,
 514                         .is_lockup = &r100_gpu_is_lockup,
 515                         .get_rptr = &radeon_ring_generic_get_rptr,
 516                         .get_wptr = &radeon_ring_generic_get_wptr,
 517                         .set_wptr = &radeon_ring_generic_set_wptr,
 518                 }
 519         },
 520         .irq = {
 521                 .set = &r100_irq_set,
 522                 .process = &r100_irq_process,
 523         },
 524         .display = {
 525                 .bandwidth_update = &r100_bandwidth_update,
 526                 .get_vblank_counter = &r100_get_vblank_counter,
 527                 .wait_for_vblank = &r100_wait_for_vblank,
 528                 .set_backlight_level = &atombios_set_backlight_level,
 529                 .get_backlight_level = &atombios_get_backlight_level,
 530         },
 531         .copy = {
 532                 .blit = &r100_copy_blit,
 533                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 534                 .dma = &r200_copy_dma,
 535                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 536                 .copy = &r100_copy_blit,
 537                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 538         },
 539         .surface = {
 540                 .set_reg = r100_set_surface_reg,
 541                 .clear_reg = r100_clear_surface_reg,
 542         },
 543         .hpd = {
 544                 .init = &r100_hpd_init,
 545                 .fini = &r100_hpd_fini,
 546                 .sense = &r100_hpd_sense,
 547                 .set_polarity = &r100_hpd_set_polarity,
 548         },
 549         .pm = {
 550                 .misc = &r100_pm_misc,
 551                 .prepare = &r100_pm_prepare,
 552                 .finish = &r100_pm_finish,
 553                 .init_profile = &r420_pm_init_profile,
 554                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 555                 .get_engine_clock = &radeon_atom_get_engine_clock,
 556                 .set_engine_clock = &radeon_atom_set_engine_clock,
 557                 .get_memory_clock = &radeon_atom_get_memory_clock,
 558                 .set_memory_clock = &radeon_atom_set_memory_clock,
 559                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 560                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 561                 .set_clock_gating = &radeon_atom_set_clock_gating,
 562         },
 563         .pflip = {
 564                 .pre_page_flip = &r100_pre_page_flip,
 565                 .page_flip = &r100_page_flip,
 566                 .post_page_flip = &r100_post_page_flip,
 567         },
 568 };
 569
 570 static struct radeon_asic rs400_asic = {
 571         .init = &rs400_init,
 572         .fini = &rs400_fini,
 573         .suspend = &rs400_suspend,
 574         .resume = &rs400_resume,
 575         .vga_set_state = &r100_vga_set_state,
 576         .asic_reset = &r300_asic_reset,
 577         .ioctl_wait_idle = NULL,
 578         .gui_idle = &r100_gui_idle,
 579         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 580         .gart = {
 581                 .tlb_flush = &rs400_gart_tlb_flush,
 582                 .set_page = &rs400_gart_set_page,
 583         },
 584         .ring = {
 585                 [RADEON_RING_TYPE_GFX_INDEX] = {
 586                         .ib_execute = &r100_ring_ib_execute,
 587                         .emit_fence = &r300_fence_ring_emit,
 588                         .emit_semaphore = &r100_semaphore_ring_emit,
 589                         .cs_parse = &r300_cs_parse,
 590                         .ring_start = &r300_ring_start,
 591                         .ring_test = &r100_ring_test,
 592                         .ib_test = &r100_ib_test,
 593                         .is_lockup = &r100_gpu_is_lockup,
 594                         .get_rptr = &radeon_ring_generic_get_rptr,
 595                         .get_wptr = &radeon_ring_generic_get_wptr,
 596                         .set_wptr = &radeon_ring_generic_set_wptr,
 597                 }
 598         },
 599         .irq = {
 600                 .set = &r100_irq_set,
 601                 .process = &r100_irq_process,
 602         },
 603         .display = {
 604                 .bandwidth_update = &r100_bandwidth_update,
 605                 .get_vblank_counter = &r100_get_vblank_counter,
 606                 .wait_for_vblank = &r100_wait_for_vblank,
 607                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 608                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 609         },
 610         .copy = {
 611                 .blit = &r100_copy_blit,
 612                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 613                 .dma = &r200_copy_dma,
 614                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 615                 .copy = &r100_copy_blit,
 616                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 617         },
 618         .surface = {
 619                 .set_reg = r100_set_surface_reg,
 620                 .clear_reg = r100_clear_surface_reg,
 621         },
 622         .hpd = {
 623                 .init = &r100_hpd_init,
 624                 .fini = &r100_hpd_fini,
 625                 .sense = &r100_hpd_sense,
 626                 .set_polarity = &r100_hpd_set_polarity,
 627         },
 628         .pm = {
 629                 .misc = &r100_pm_misc,
 630                 .prepare = &r100_pm_prepare,
 631                 .finish = &r100_pm_finish,
 632                 .init_profile = &r100_pm_init_profile,
 633                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 634                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 635                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 636                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 637                 .set_memory_clock = NULL,
 638                 .get_pcie_lanes = NULL,
 639                 .set_pcie_lanes = NULL,
 640                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 641         },
 642         .pflip = {
 643                 .pre_page_flip = &r100_pre_page_flip,
 644                 .page_flip = &r100_page_flip,
 645                 .post_page_flip = &r100_post_page_flip,
 646         },
 647 };
 648
 649 static struct radeon_asic rs600_asic = {
 650         .init = &rs600_init,
 651         .fini = &rs600_fini,
 652         .suspend = &rs600_suspend,
 653         .resume = &rs600_resume,
 654         .vga_set_state = &r100_vga_set_state,
 655         .asic_reset = &rs600_asic_reset,
 656         .ioctl_wait_idle = NULL,
 657         .gui_idle = &r100_gui_idle,
 658         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 659         .gart = {
 660                 .tlb_flush = &rs600_gart_tlb_flush,
 661                 .set_page = &rs600_gart_set_page,
 662         },
 663         .ring = {
 664                 [RADEON_RING_TYPE_GFX_INDEX] = {
 665                         .ib_execute = &r100_ring_ib_execute,
 666                         .emit_fence = &r300_fence_ring_emit,
 667                         .emit_semaphore = &r100_semaphore_ring_emit,
 668                         .cs_parse = &r300_cs_parse,
 669                         .ring_start = &r300_ring_start,
 670                         .ring_test = &r100_ring_test,
 671                         .ib_test = &r100_ib_test,
 672                         .is_lockup = &r100_gpu_is_lockup,
 673                         .get_rptr = &radeon_ring_generic_get_rptr,
 674                         .get_wptr = &radeon_ring_generic_get_wptr,
 675                         .set_wptr = &radeon_ring_generic_set_wptr,
 676                 }
 677         },
 678         .irq = {
 679                 .set = &rs600_irq_set,
 680                 .process = &rs600_irq_process,
 681         },
 682         .display = {
 683                 .bandwidth_update = &rs600_bandwidth_update,
 684                 .get_vblank_counter = &rs600_get_vblank_counter,
 685                 .wait_for_vblank = &avivo_wait_for_vblank,
 686                 .set_backlight_level = &atombios_set_backlight_level,
 687                 .get_backlight_level = &atombios_get_backlight_level,
 688                 .hdmi_enable = &r600_hdmi_enable,
 689                 .hdmi_setmode = &r600_hdmi_setmode,
 690         },
 691         .copy = {
 692                 .blit = &r100_copy_blit,
 693                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 694                 .dma = &r200_copy_dma,
 695                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 696                 .copy = &r100_copy_blit,
 697                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 698         },
 699         .surface = {
 700                 .set_reg = r100_set_surface_reg,
 701                 .clear_reg = r100_clear_surface_reg,
 702         },
 703         .hpd = {
 704                 .init = &rs600_hpd_init,
 705                 .fini = &rs600_hpd_fini,
 706                 .sense = &rs600_hpd_sense,
 707                 .set_polarity = &rs600_hpd_set_polarity,
 708         },
 709         .pm = {
 710                 .misc = &rs600_pm_misc,
 711                 .prepare = &rs600_pm_prepare,
 712                 .finish = &rs600_pm_finish,
 713                 .init_profile = &r420_pm_init_profile,
 714                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 715                 .get_engine_clock = &radeon_atom_get_engine_clock,
 716                 .set_engine_clock = &radeon_atom_set_engine_clock,
 717                 .get_memory_clock = &radeon_atom_get_memory_clock,
 718                 .set_memory_clock = &radeon_atom_set_memory_clock,
 719                 .get_pcie_lanes = NULL,
 720                 .set_pcie_lanes = NULL,
 721                 .set_clock_gating = &radeon_atom_set_clock_gating,
 722         },
 723         .pflip = {
 724                 .pre_page_flip = &rs600_pre_page_flip,
 725                 .page_flip = &rs600_page_flip,
 726                 .post_page_flip = &rs600_post_page_flip,
 727         },
 728 };
 729
 730 static struct radeon_asic rs690_asic = {
 731         .init = &rs690_init,
 732         .fini = &rs690_fini,
 733         .suspend = &rs690_suspend,
 734         .resume = &rs690_resume,
 735         .vga_set_state = &r100_vga_set_state,
 736         .asic_reset = &rs600_asic_reset,
 737         .ioctl_wait_idle = NULL,
 738         .gui_idle = &r100_gui_idle,
 739         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 740         .gart = {
 741                 .tlb_flush = &rs400_gart_tlb_flush,
 742                 .set_page = &rs400_gart_set_page,
 743         },
 744         .ring = {
 745                 [RADEON_RING_TYPE_GFX_INDEX] = {
 746                         .ib_execute = &r100_ring_ib_execute,
 747                         .emit_fence = &r300_fence_ring_emit,
 748                         .emit_semaphore = &r100_semaphore_ring_emit,
 749                         .cs_parse = &r300_cs_parse,
 750                         .ring_start = &r300_ring_start,
 751                         .ring_test = &r100_ring_test,
 752                         .ib_test = &r100_ib_test,
 753                         .is_lockup = &r100_gpu_is_lockup,
 754                         .get_rptr = &radeon_ring_generic_get_rptr,
 755                         .get_wptr = &radeon_ring_generic_get_wptr,
 756                         .set_wptr = &radeon_ring_generic_set_wptr,
 757                 }
 758         },
 759         .irq = {
 760                 .set = &rs600_irq_set,
 761                 .process = &rs600_irq_process,
 762         },
 763         .display = {
 764                 .get_vblank_counter = &rs600_get_vblank_counter,
 765                 .bandwidth_update = &rs690_bandwidth_update,
 766                 .wait_for_vblank = &avivo_wait_for_vblank,
 767                 .set_backlight_level = &atombios_set_backlight_level,
 768                 .get_backlight_level = &atombios_get_backlight_level,
 769                 .hdmi_enable = &r600_hdmi_enable,
 770                 .hdmi_setmode = &r600_hdmi_setmode,
 771         },
 772         .copy = {
 773                 .blit = &r100_copy_blit,
 774                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 775                 .dma = &r200_copy_dma,
 776                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 777                 .copy = &r200_copy_dma,
 778                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 779         },
 780         .surface = {
 781                 .set_reg = r100_set_surface_reg,
 782                 .clear_reg = r100_clear_surface_reg,
 783         },
 784         .hpd = {
 785                 .init = &rs600_hpd_init,
 786                 .fini = &rs600_hpd_fini,
 787                 .sense = &rs600_hpd_sense,
 788                 .set_polarity = &rs600_hpd_set_polarity,
 789         },
 790         .pm = {
 791                 .misc = &rs600_pm_misc,
 792                 .prepare = &rs600_pm_prepare,
 793                 .finish = &rs600_pm_finish,
 794                 .init_profile = &r420_pm_init_profile,
 795                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 796                 .get_engine_clock = &radeon_atom_get_engine_clock,
 797                 .set_engine_clock = &radeon_atom_set_engine_clock,
 798                 .get_memory_clock = &radeon_atom_get_memory_clock,
 799                 .set_memory_clock = &radeon_atom_set_memory_clock,
 800                 .get_pcie_lanes = NULL,
 801                 .set_pcie_lanes = NULL,
 802                 .set_clock_gating = &radeon_atom_set_clock_gating,
 803         },
 804         .pflip = {
 805                 .pre_page_flip = &rs600_pre_page_flip,
 806                 .page_flip = &rs600_page_flip,
 807                 .post_page_flip = &rs600_post_page_flip,
 808         },
 809 };
 810
 811 static struct radeon_asic rv515_asic = {
 812         .init = &rv515_init,
 813         .fini = &rv515_fini,
 814         .suspend = &rv515_suspend,
 815         .resume = &rv515_resume,
 816         .vga_set_state = &r100_vga_set_state,
 817         .asic_reset = &rs600_asic_reset,
 818         .ioctl_wait_idle = NULL,
 819         .gui_idle = &r100_gui_idle,
 820         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 821         .gart = {
 822                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 823                 .set_page = &rv370_pcie_gart_set_page,
 824         },
 825         .ring = {
 826                 [RADEON_RING_TYPE_GFX_INDEX] = {
 827                         .ib_execute = &r100_ring_ib_execute,
 828                         .emit_fence = &r300_fence_ring_emit,
 829                         .emit_semaphore = &r100_semaphore_ring_emit,
 830                         .cs_parse = &r300_cs_parse,
 831                         .ring_start = &rv515_ring_start,
 832                         .ring_test = &r100_ring_test,
 833                         .ib_test = &r100_ib_test,
 834                         .is_lockup = &r100_gpu_is_lockup,
 835                         .get_rptr = &radeon_ring_generic_get_rptr,
 836                         .get_wptr = &radeon_ring_generic_get_wptr,
 837                         .set_wptr = &radeon_ring_generic_set_wptr,
 838                 }
 839         },
 840         .irq = {
 841                 .set = &rs600_irq_set,
 842                 .process = &rs600_irq_process,
 843         },
 844         .display = {
 845                 .get_vblank_counter = &rs600_get_vblank_counter,
 846                 .bandwidth_update = &rv515_bandwidth_update,
 847                 .wait_for_vblank = &avivo_wait_for_vblank,
 848                 .set_backlight_level = &atombios_set_backlight_level,
 849                 .get_backlight_level = &atombios_get_backlight_level,
 850         },
 851         .copy = {
 852                 .blit = &r100_copy_blit,
 853                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 854                 .dma = &r200_copy_dma,
 855                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 856                 .copy = &r100_copy_blit,
 857                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 858         },
 859         .surface = {
 860                 .set_reg = r100_set_surface_reg,
 861                 .clear_reg = r100_clear_surface_reg,
 862         },
 863         .hpd = {
 864                 .init = &rs600_hpd_init,
 865                 .fini = &rs600_hpd_fini,
 866                 .sense = &rs600_hpd_sense,
 867                 .set_polarity = &rs600_hpd_set_polarity,
 868         },
 869         .pm = {
 870                 .misc = &rs600_pm_misc,
 871                 .prepare = &rs600_pm_prepare,
 872                 .finish = &rs600_pm_finish,
 873                 .init_profile = &r420_pm_init_profile,
 874                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 875                 .get_engine_clock = &radeon_atom_get_engine_clock,
 876                 .set_engine_clock = &radeon_atom_set_engine_clock,
 877                 .get_memory_clock = &radeon_atom_get_memory_clock,
 878                 .set_memory_clock = &radeon_atom_set_memory_clock,
 879                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 880                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 881                 .set_clock_gating = &radeon_atom_set_clock_gating,
 882         },
 883         .pflip = {
 884                 .pre_page_flip = &rs600_pre_page_flip,
 885                 .page_flip = &rs600_page_flip,
 886                 .post_page_flip = &rs600_post_page_flip,
 887         },
 888 };
 889
 890 static struct radeon_asic r520_asic = {
 891         .init = &r520_init,
 892         .fini = &rv515_fini,
 893         .suspend = &rv515_suspend,
 894         .resume = &r520_resume,
 895         .vga_set_state = &r100_vga_set_state,
 896         .asic_reset = &rs600_asic_reset,
 897         .ioctl_wait_idle = NULL,
 898         .gui_idle = &r100_gui_idle,
 899         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 900         .gart = {
 901                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 902                 .set_page = &rv370_pcie_gart_set_page,
 903         },
 904         .ring = {
 905                 [RADEON_RING_TYPE_GFX_INDEX] = {
 906                         .ib_execute = &r100_ring_ib_execute,
 907                         .emit_fence = &r300_fence_ring_emit,
 908                         .emit_semaphore = &r100_semaphore_ring_emit,
 909                         .cs_parse = &r300_cs_parse,
 910                         .ring_start = &rv515_ring_start,
 911                         .ring_test = &r100_ring_test,
 912                         .ib_test = &r100_ib_test,
 913                         .is_lockup = &r100_gpu_is_lockup,
 914                         .get_rptr = &radeon_ring_generic_get_rptr,
 915                         .get_wptr = &radeon_ring_generic_get_wptr,
 916                         .set_wptr = &radeon_ring_generic_set_wptr,
 917                 }
 918         },
 919         .irq = {
 920                 .set = &rs600_irq_set,
 921                 .process = &rs600_irq_process,
 922         },
 923         .display = {
 924                 .bandwidth_update = &rv515_bandwidth_update,
 925                 .get_vblank_counter = &rs600_get_vblank_counter,
 926                 .wait_for_vblank = &avivo_wait_for_vblank,
 927                 .set_backlight_level = &atombios_set_backlight_level,
 928                 .get_backlight_level = &atombios_get_backlight_level,
 929         },
 930         .copy = {
 931                 .blit = &r100_copy_blit,
 932                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 933                 .dma = &r200_copy_dma,
 934                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 935                 .copy = &r100_copy_blit,
 936                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 937         },
 938         .surface = {
 939                 .set_reg = r100_set_surface_reg,
 940                 .clear_reg = r100_clear_surface_reg,
 941         },
 942         .hpd = {
 943                 .init = &rs600_hpd_init,
 944                 .fini = &rs600_hpd_fini,
 945                 .sense = &rs600_hpd_sense,
 946                 .set_polarity = &rs600_hpd_set_polarity,
 947         },
 948         .pm = {
 949                 .misc = &rs600_pm_misc,
 950                 .prepare = &rs600_pm_prepare,
 951                 .finish = &rs600_pm_finish,
 952                 .init_profile = &r420_pm_init_profile,
 953                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 954                 .get_engine_clock = &radeon_atom_get_engine_clock,
 955                 .set_engine_clock = &radeon_atom_set_engine_clock,
 956                 .get_memory_clock = &radeon_atom_get_memory_clock,
 957                 .set_memory_clock = &radeon_atom_set_memory_clock,
 958                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 959                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 960                 .set_clock_gating = &radeon_atom_set_clock_gating,
 961         },
 962         .pflip = {
 963                 .pre_page_flip = &rs600_pre_page_flip,
 964                 .page_flip = &rs600_page_flip,
 965                 .post_page_flip = &rs600_post_page_flip,
 966         },
 967 };
 968
 969 static struct radeon_asic r600_asic = {
 970         .init = &r600_init,
 971         .fini = &r600_fini,
 972         .suspend = &r600_suspend,
 973         .resume = &r600_resume,
 974         .vga_set_state = &r600_vga_set_state,
 975         .asic_reset = &r600_asic_reset,
 976         .ioctl_wait_idle = r600_ioctl_wait_idle,
 977         .gui_idle = &r600_gui_idle,
 978         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 979         .get_xclk = &r600_get_xclk,
 980         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 981         .gart = {
 982                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 983                 .set_page = &rs600_gart_set_page,
 984         },
 985         .ring = {
 986                 [RADEON_RING_TYPE_GFX_INDEX] = {
 987                         .ib_execute = &r600_ring_ib_execute,
 988                         .emit_fence = &r600_fence_ring_emit,
 989                         .emit_semaphore = &r600_semaphore_ring_emit,
 990                         .cs_parse = &r600_cs_parse,
 991                         .ring_test = &r600_ring_test,
 992                         .ib_test = &r600_ib_test,
 993                         .is_lockup = &r600_gfx_is_lockup,
 994                         .get_rptr = &radeon_ring_generic_get_rptr,
 995                         .get_wptr = &radeon_ring_generic_get_wptr,
 996                         .set_wptr = &radeon_ring_generic_set_wptr,
 997                 },
 998                 [R600_RING_TYPE_DMA_INDEX] = {
 999                         .ib_execute = &r600_dma_ring_ib_execute,
1000                         .emit_fence = &r600_dma_fence_ring_emit,
1001                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1002                         .cs_parse = &r600_dma_cs_parse,
1003                         .ring_test = &r600_dma_ring_test,
1004                         .ib_test = &r600_dma_ib_test,
1005                         .is_lockup = &r600_dma_is_lockup,
1006                         .get_rptr = &radeon_ring_generic_get_rptr,
1007                         .get_wptr = &radeon_ring_generic_get_wptr,
1008                         .set_wptr = &radeon_ring_generic_set_wptr,
1009                 }
1010         },
1011         .irq = {
1012                 .set = &r600_irq_set,
1013                 .process = &r600_irq_process,
1014         },
1015         .display = {
1016                 .bandwidth_update = &rv515_bandwidth_update,
1017                 .get_vblank_counter = &rs600_get_vblank_counter,
1018                 .wait_for_vblank = &avivo_wait_for_vblank,
1019                 .set_backlight_level = &atombios_set_backlight_level,
1020                 .get_backlight_level = &atombios_get_backlight_level,
1021                 .hdmi_enable = &r600_hdmi_enable,
1022                 .hdmi_setmode = &r600_hdmi_setmode,
1023         },
1024         .copy = {
1025                 .blit = &r600_copy_blit,
1026                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1027                 .dma = &r600_copy_dma,
1028                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1029                 .copy = &r600_copy_dma,
1030                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1031         },
1032         .surface = {
1033                 .set_reg = r600_set_surface_reg,
1034                 .clear_reg = r600_clear_surface_reg,
1035         },
1036         .hpd = {
1037                 .init = &r600_hpd_init,
1038                 .fini = &r600_hpd_fini,
1039                 .sense = &r600_hpd_sense,
1040                 .set_polarity = &r600_hpd_set_polarity,
1041         },
1042         .pm = {
1043                 .misc = &r600_pm_misc,
1044                 .prepare = &rs600_pm_prepare,
1045                 .finish = &rs600_pm_finish,
1046                 .init_profile = &r600_pm_init_profile,
1047                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1048                 .get_engine_clock = &radeon_atom_get_engine_clock,
1049                 .set_engine_clock = &radeon_atom_set_engine_clock,
1050                 .get_memory_clock = &radeon_atom_get_memory_clock,
1051                 .set_memory_clock = &radeon_atom_set_memory_clock,
1052                 .get_pcie_lanes = &r600_get_pcie_lanes,
1053                 .set_pcie_lanes = &r600_set_pcie_lanes,
1054                 .set_clock_gating = NULL,
1055                 .get_temperature = &rv6xx_get_temp,
1056         },
1057         .pflip = {
1058                 .pre_page_flip = &rs600_pre_page_flip,
1059                 .page_flip = &rs600_page_flip,
1060                 .post_page_flip = &rs600_post_page_flip,
1061         },
1062 };
1063
1064 static struct radeon_asic rv6xx_asic = {
1065         .init = &r600_init,
1066         .fini = &r600_fini,
1067         .suspend = &r600_suspend,
1068         .resume = &r600_resume,
1069         .vga_set_state = &r600_vga_set_state,
1070         .asic_reset = &r600_asic_reset,
1071         .ioctl_wait_idle = r600_ioctl_wait_idle,
1072         .gui_idle = &r600_gui_idle,
1073         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1074         .get_xclk = &r600_get_xclk,
1075         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1076         .gart = {
1077                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078                 .set_page = &rs600_gart_set_page,
1079         },
1080         .ring = {
1081                 [RADEON_RING_TYPE_GFX_INDEX] = {
1082                         .ib_execute = &r600_ring_ib_execute,
1083                         .emit_fence = &r600_fence_ring_emit,
1084                         .emit_semaphore = &r600_semaphore_ring_emit,
1085                         .cs_parse = &r600_cs_parse,
1086                         .ring_test = &r600_ring_test,
1087                         .ib_test = &r600_ib_test,
1088                         .is_lockup = &r600_gfx_is_lockup,
1089                         .get_rptr = &radeon_ring_generic_get_rptr,
1090                         .get_wptr = &radeon_ring_generic_get_wptr,
1091                         .set_wptr = &radeon_ring_generic_set_wptr,
1092                 },
1093                 [R600_RING_TYPE_DMA_INDEX] = {
1094                         .ib_execute = &r600_dma_ring_ib_execute,
1095                         .emit_fence = &r600_dma_fence_ring_emit,
1096                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097                         .cs_parse = &r600_dma_cs_parse,
1098                         .ring_test = &r600_dma_ring_test,
1099                         .ib_test = &r600_dma_ib_test,
1100                         .is_lockup = &r600_dma_is_lockup,
1101                         .get_rptr = &radeon_ring_generic_get_rptr,
1102                         .get_wptr = &radeon_ring_generic_get_wptr,
1103                         .set_wptr = &radeon_ring_generic_set_wptr,
1104                 }
1105         },
1106         .irq = {
1107                 .set = &r600_irq_set,
1108                 .process = &r600_irq_process,
1109         },
1110         .display = {
1111                 .bandwidth_update = &rv515_bandwidth_update,
1112                 .get_vblank_counter = &rs600_get_vblank_counter,
1113                 .wait_for_vblank = &avivo_wait_for_vblank,
1114                 .set_backlight_level = &atombios_set_backlight_level,
1115                 .get_backlight_level = &atombios_get_backlight_level,
1116         },
1117         .copy = {
1118                 .blit = &r600_copy_blit,
1119                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1120                 .dma = &r600_copy_dma,
1121                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1122                 .copy = &r600_copy_dma,
1123                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1124         },
1125         .surface = {
1126                 .set_reg = r600_set_surface_reg,
1127                 .clear_reg = r600_clear_surface_reg,
1128         },
1129         .hpd = {
1130                 .init = &r600_hpd_init,
1131                 .fini = &r600_hpd_fini,
1132                 .sense = &r600_hpd_sense,
1133                 .set_polarity = &r600_hpd_set_polarity,
1134         },
1135         .pm = {
1136                 .misc = &r600_pm_misc,
1137                 .prepare = &rs600_pm_prepare,
1138                 .finish = &rs600_pm_finish,
1139                 .init_profile = &r600_pm_init_profile,
1140                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1141                 .get_engine_clock = &radeon_atom_get_engine_clock,
1142                 .set_engine_clock = &radeon_atom_set_engine_clock,
1143                 .get_memory_clock = &radeon_atom_get_memory_clock,
1144                 .set_memory_clock = &radeon_atom_set_memory_clock,
1145                 .get_pcie_lanes = &r600_get_pcie_lanes,
1146                 .set_pcie_lanes = &r600_set_pcie_lanes,
1147                 .set_clock_gating = NULL,
1148                 .get_temperature = &rv6xx_get_temp,
1149         },
1150         .dpm = {
1151                 .init = &rv6xx_dpm_init,
1152                 .setup_asic = &rv6xx_setup_asic,
1153                 .enable = &rv6xx_dpm_enable,
1154                 .disable = &rv6xx_dpm_disable,
1155                 .set_power_state = &rv6xx_dpm_set_power_state,
1156                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1157                 .fini = &rv6xx_dpm_fini,
1158                 .get_sclk = &rv6xx_dpm_get_sclk,
1159                 .get_mclk = &rv6xx_dpm_get_mclk,
1160                 .print_power_state = &rv6xx_dpm_print_power_state,
1161         },
1162         .pflip = {
1163                 .pre_page_flip = &rs600_pre_page_flip,
1164                 .page_flip = &rs600_page_flip,
1165                 .post_page_flip = &rs600_post_page_flip,
1166         },
1167 };
1168
1169 static struct radeon_asic rs780_asic = {
1170         .init = &r600_init,
1171         .fini = &r600_fini,
1172         .suspend = &r600_suspend,
1173         .resume = &r600_resume,
1174         .vga_set_state = &r600_vga_set_state,
1175         .asic_reset = &r600_asic_reset,
1176         .ioctl_wait_idle = r600_ioctl_wait_idle,
1177         .gui_idle = &r600_gui_idle,
1178         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1179         .get_xclk = &r600_get_xclk,
1180         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1181         .gart = {
1182                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1183                 .set_page = &rs600_gart_set_page,
1184         },
1185         .ring = {
1186                 [RADEON_RING_TYPE_GFX_INDEX] = {
1187                         .ib_execute = &r600_ring_ib_execute,
1188                         .emit_fence = &r600_fence_ring_emit,
1189                         .emit_semaphore = &r600_semaphore_ring_emit,
1190                         .cs_parse = &r600_cs_parse,
1191                         .ring_test = &r600_ring_test,
1192                         .ib_test = &r600_ib_test,
1193                         .is_lockup = &r600_gfx_is_lockup,
1194                         .get_rptr = &radeon_ring_generic_get_rptr,
1195                         .get_wptr = &radeon_ring_generic_get_wptr,
1196                         .set_wptr = &radeon_ring_generic_set_wptr,
1197                 },
1198                 [R600_RING_TYPE_DMA_INDEX] = {
1199                         .ib_execute = &r600_dma_ring_ib_execute,
1200                         .emit_fence = &r600_dma_fence_ring_emit,
1201                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1202                         .cs_parse = &r600_dma_cs_parse,
1203                         .ring_test = &r600_dma_ring_test,
1204                         .ib_test = &r600_dma_ib_test,
1205                         .is_lockup = &r600_dma_is_lockup,
1206                         .get_rptr = &radeon_ring_generic_get_rptr,
1207                         .get_wptr = &radeon_ring_generic_get_wptr,
1208                         .set_wptr = &radeon_ring_generic_set_wptr,
1209                 }
1210         },
1211         .irq = {
1212                 .set = &r600_irq_set,
1213                 .process = &r600_irq_process,
1214         },
1215         .display = {
1216                 .bandwidth_update = &rs690_bandwidth_update,
1217                 .get_vblank_counter = &rs600_get_vblank_counter,
1218                 .wait_for_vblank = &avivo_wait_for_vblank,
1219                 .set_backlight_level = &atombios_set_backlight_level,
1220                 .get_backlight_level = &atombios_get_backlight_level,
1221                 .hdmi_enable = &r600_hdmi_enable,
1222                 .hdmi_setmode = &r600_hdmi_setmode,
1223         },
1224         .copy = {
1225                 .blit = &r600_copy_blit,
1226                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1227                 .dma = &r600_copy_dma,
1228                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1229                 .copy = &r600_copy_dma,
1230                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1231         },
1232         .surface = {
1233                 .set_reg = r600_set_surface_reg,
1234                 .clear_reg = r600_clear_surface_reg,
1235         },
1236         .hpd = {
1237                 .init = &r600_hpd_init,
1238                 .fini = &r600_hpd_fini,
1239                 .sense = &r600_hpd_sense,
1240                 .set_polarity = &r600_hpd_set_polarity,
1241         },
1242         .pm = {
1243                 .misc = &r600_pm_misc,
1244                 .prepare = &rs600_pm_prepare,
1245                 .finish = &rs600_pm_finish,
1246                 .init_profile = &rs780_pm_init_profile,
1247                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1248                 .get_engine_clock = &radeon_atom_get_engine_clock,
1249                 .set_engine_clock = &radeon_atom_set_engine_clock,
1250                 .get_memory_clock = NULL,
1251                 .set_memory_clock = NULL,
1252                 .get_pcie_lanes = NULL,
1253                 .set_pcie_lanes = NULL,
1254                 .set_clock_gating = NULL,
1255                 .get_temperature = &rv6xx_get_temp,
1256         },
1257         .dpm = {
1258                 .init = &rs780_dpm_init,
1259                 .setup_asic = &rs780_dpm_setup_asic,
1260                 .enable = &rs780_dpm_enable,
1261                 .disable = &rs780_dpm_disable,
1262                 .set_power_state = &rs780_dpm_set_power_state,
1263                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1264                 .fini = &rs780_dpm_fini,
1265                 .get_sclk = &rs780_dpm_get_sclk,
1266                 .get_mclk = &rs780_dpm_get_mclk,
1267                 .print_power_state = &rs780_dpm_print_power_state,
1268         },
1269         .pflip = {
1270                 .pre_page_flip = &rs600_pre_page_flip,
1271                 .page_flip = &rs600_page_flip,
1272                 .post_page_flip = &rs600_post_page_flip,
1273         },
1274 };
1275
1276 static struct radeon_asic rv770_asic = {
1277         .init = &rv770_init,
1278         .fini = &rv770_fini,
1279         .suspend = &rv770_suspend,
1280         .resume = &rv770_resume,
1281         .asic_reset = &r600_asic_reset,
1282         .vga_set_state = &r600_vga_set_state,
1283         .ioctl_wait_idle = r600_ioctl_wait_idle,
1284         .gui_idle = &r600_gui_idle,
1285         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1286         .get_xclk = &rv770_get_xclk,
1287         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1288         .gart = {
1289                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1290                 .set_page = &rs600_gart_set_page,
1291         },
1292         .ring = {
1293                 [RADEON_RING_TYPE_GFX_INDEX] = {
1294                         .ib_execute = &r600_ring_ib_execute,
1295                         .emit_fence = &r600_fence_ring_emit,
1296                         .emit_semaphore = &r600_semaphore_ring_emit,
1297                         .cs_parse = &r600_cs_parse,
1298                         .ring_test = &r600_ring_test,
1299                         .ib_test = &r600_ib_test,
1300                         .is_lockup = &r600_gfx_is_lockup,
1301                         .get_rptr = &radeon_ring_generic_get_rptr,
1302                         .get_wptr = &radeon_ring_generic_get_wptr,
1303                         .set_wptr = &radeon_ring_generic_set_wptr,
1304                 },
1305                 [R600_RING_TYPE_DMA_INDEX] = {
1306                         .ib_execute = &r600_dma_ring_ib_execute,
1307                         .emit_fence = &r600_dma_fence_ring_emit,
1308                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1309                         .cs_parse = &r600_dma_cs_parse,
1310                         .ring_test = &r600_dma_ring_test,
1311                         .ib_test = &r600_dma_ib_test,
1312                         .is_lockup = &r600_dma_is_lockup,
1313                         .get_rptr = &radeon_ring_generic_get_rptr,
1314                         .get_wptr = &radeon_ring_generic_get_wptr,
1315                         .set_wptr = &radeon_ring_generic_set_wptr,
1316                 },
1317                 [R600_RING_TYPE_UVD_INDEX] = {
1318                         .ib_execute = &r600_uvd_ib_execute,
1319                         .emit_fence = &r600_uvd_fence_emit,
1320                         .emit_semaphore = &r600_uvd_semaphore_emit,
1321                         .cs_parse = &radeon_uvd_cs_parse,
1322                         .ring_test = &r600_uvd_ring_test,
1323                         .ib_test = &r600_uvd_ib_test,
1324                         .is_lockup = &radeon_ring_test_lockup,
1325                         .get_rptr = &radeon_ring_generic_get_rptr,
1326                         .get_wptr = &radeon_ring_generic_get_wptr,
1327                         .set_wptr = &radeon_ring_generic_set_wptr,
1328                 }
1329         },
1330         .irq = {
1331                 .set = &r600_irq_set,
1332                 .process = &r600_irq_process,
1333         },
1334         .display = {
1335                 .bandwidth_update = &rv515_bandwidth_update,
1336                 .get_vblank_counter = &rs600_get_vblank_counter,
1337                 .wait_for_vblank = &avivo_wait_for_vblank,
1338                 .set_backlight_level = &atombios_set_backlight_level,
1339                 .get_backlight_level = &atombios_get_backlight_level,
1340                 .hdmi_enable = &r600_hdmi_enable,
1341                 .hdmi_setmode = &r600_hdmi_setmode,
1342         },
1343         .copy = {
1344                 .blit = &r600_copy_blit,
1345                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1346                 .dma = &rv770_copy_dma,
1347                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1348                 .copy = &rv770_copy_dma,
1349                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1350         },
1351         .surface = {
1352                 .set_reg = r600_set_surface_reg,
1353                 .clear_reg = r600_clear_surface_reg,
1354         },
1355         .hpd = {
1356                 .init = &r600_hpd_init,
1357                 .fini = &r600_hpd_fini,
1358                 .sense = &r600_hpd_sense,
1359                 .set_polarity = &r600_hpd_set_polarity,
1360         },
1361         .pm = {
1362                 .misc = &rv770_pm_misc,
1363                 .prepare = &rs600_pm_prepare,
1364                 .finish = &rs600_pm_finish,
1365                 .init_profile = &r600_pm_init_profile,
1366                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1367                 .get_engine_clock = &radeon_atom_get_engine_clock,
1368                 .set_engine_clock = &radeon_atom_set_engine_clock,
1369                 .get_memory_clock = &radeon_atom_get_memory_clock,
1370                 .set_memory_clock = &radeon_atom_set_memory_clock,
1371                 .get_pcie_lanes = &r600_get_pcie_lanes,
1372                 .set_pcie_lanes = &r600_set_pcie_lanes,
1373                 .set_clock_gating = &radeon_atom_set_clock_gating,
1374                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1375                 .get_temperature = &rv770_get_temp,
1376         },
1377         .dpm = {
1378                 .init = &rv770_dpm_init,
1379                 .setup_asic = &rv770_dpm_setup_asic,
1380                 .enable = &rv770_dpm_enable,
1381                 .disable = &rv770_dpm_disable,
1382                 .set_power_state = &rv770_dpm_set_power_state,
1383                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1384                 .fini = &rv770_dpm_fini,
1385                 .get_sclk = &rv770_dpm_get_sclk,
1386                 .get_mclk = &rv770_dpm_get_mclk,
1387                 .print_power_state = &rv770_dpm_print_power_state,
1388         },
1389         .pflip = {
1390                 .pre_page_flip = &rs600_pre_page_flip,
1391                 .page_flip = &rv770_page_flip,
1392                 .post_page_flip = &rs600_post_page_flip,
1393         },
1394 };
1395
1396 static struct radeon_asic evergreen_asic = {
1397         .init = &evergreen_init,
1398         .fini = &evergreen_fini,
1399         .suspend = &evergreen_suspend,
1400         .resume = &evergreen_resume,
1401         .asic_reset = &evergreen_asic_reset,
1402         .vga_set_state = &r600_vga_set_state,
1403         .ioctl_wait_idle = r600_ioctl_wait_idle,
1404         .gui_idle = &r600_gui_idle,
1405         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1406         .get_xclk = &rv770_get_xclk,
1407         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1408         .gart = {
1409                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1410                 .set_page = &rs600_gart_set_page,
1411         },
1412         .ring = {
1413                 [RADEON_RING_TYPE_GFX_INDEX] = {
1414                         .ib_execute = &evergreen_ring_ib_execute,
1415                         .emit_fence = &r600_fence_ring_emit,
1416                         .emit_semaphore = &r600_semaphore_ring_emit,
1417                         .cs_parse = &evergreen_cs_parse,
1418                         .ring_test = &r600_ring_test,
1419                         .ib_test = &r600_ib_test,
1420                         .is_lockup = &evergreen_gfx_is_lockup,
1421                         .get_rptr = &radeon_ring_generic_get_rptr,
1422                         .get_wptr = &radeon_ring_generic_get_wptr,
1423                         .set_wptr = &radeon_ring_generic_set_wptr,
1424                 },
1425                 [R600_RING_TYPE_DMA_INDEX] = {
1426                         .ib_execute = &evergreen_dma_ring_ib_execute,
1427                         .emit_fence = &evergreen_dma_fence_ring_emit,
1428                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1429                         .cs_parse = &evergreen_dma_cs_parse,
1430                         .ring_test = &r600_dma_ring_test,
1431                         .ib_test = &r600_dma_ib_test,
1432                         .is_lockup = &evergreen_dma_is_lockup,
1433                         .get_rptr = &radeon_ring_generic_get_rptr,
1434                         .get_wptr = &radeon_ring_generic_get_wptr,
1435                         .set_wptr = &radeon_ring_generic_set_wptr,
1436                 },
1437                 [R600_RING_TYPE_UVD_INDEX] = {
1438                         .ib_execute = &r600_uvd_ib_execute,
1439                         .emit_fence = &r600_uvd_fence_emit,
1440                         .emit_semaphore = &r600_uvd_semaphore_emit,
1441                         .cs_parse = &radeon_uvd_cs_parse,
1442                         .ring_test = &r600_uvd_ring_test,
1443                         .ib_test = &r600_uvd_ib_test,
1444                         .is_lockup = &radeon_ring_test_lockup,
1445                         .get_rptr = &radeon_ring_generic_get_rptr,
1446                         .get_wptr = &radeon_ring_generic_get_wptr,
1447                         .set_wptr = &radeon_ring_generic_set_wptr,
1448                 }
1449         },
1450         .irq = {
1451                 .set = &evergreen_irq_set,
1452                 .process = &evergreen_irq_process,
1453         },
1454         .display = {
1455                 .bandwidth_update = &evergreen_bandwidth_update,
1456                 .get_vblank_counter = &evergreen_get_vblank_counter,
1457                 .wait_for_vblank = &dce4_wait_for_vblank,
1458                 .set_backlight_level = &atombios_set_backlight_level,
1459                 .get_backlight_level = &atombios_get_backlight_level,
1460                 .hdmi_enable = &evergreen_hdmi_enable,
1461                 .hdmi_setmode = &evergreen_hdmi_setmode,
1462         },
1463         .copy = {
1464                 .blit = &r600_copy_blit,
1465                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1466                 .dma = &evergreen_copy_dma,
1467                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1468                 .copy = &evergreen_copy_dma,
1469                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1470         },
1471         .surface = {
1472                 .set_reg = r600_set_surface_reg,
1473                 .clear_reg = r600_clear_surface_reg,
1474         },
1475         .hpd = {
1476                 .init = &evergreen_hpd_init,
1477                 .fini = &evergreen_hpd_fini,
1478                 .sense = &evergreen_hpd_sense,
1479                 .set_polarity = &evergreen_hpd_set_polarity,
1480         },
1481         .pm = {
1482                 .misc = &evergreen_pm_misc,
1483                 .prepare = &evergreen_pm_prepare,
1484                 .finish = &evergreen_pm_finish,
1485                 .init_profile = &r600_pm_init_profile,
1486                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1487                 .get_engine_clock = &radeon_atom_get_engine_clock,
1488                 .set_engine_clock = &radeon_atom_set_engine_clock,
1489                 .get_memory_clock = &radeon_atom_get_memory_clock,
1490                 .set_memory_clock = &radeon_atom_set_memory_clock,
1491                 .get_pcie_lanes = &r600_get_pcie_lanes,
1492                 .set_pcie_lanes = &r600_set_pcie_lanes,
1493                 .set_clock_gating = NULL,
1494                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1495                 .get_temperature = &evergreen_get_temp,
1496         },
1497         .dpm = {
1498                 .init = &cypress_dpm_init,
1499                 .setup_asic = &cypress_dpm_setup_asic,
1500                 .enable = &cypress_dpm_enable,
1501                 .disable = &cypress_dpm_disable,
1502                 .set_power_state = &cypress_dpm_set_power_state,
1503                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1504                 .fini = &cypress_dpm_fini,
1505                 .get_sclk = &rv770_dpm_get_sclk,
1506                 .get_mclk = &rv770_dpm_get_mclk,
1507                 .print_power_state = &rv770_dpm_print_power_state,
1508         },
1509         .pflip = {
1510                 .pre_page_flip = &evergreen_pre_page_flip,
1511                 .page_flip = &evergreen_page_flip,
1512                 .post_page_flip = &evergreen_post_page_flip,
1513         },
1514 };
1515
1516 static struct radeon_asic sumo_asic = {
1517         .init = &evergreen_init,
1518         .fini = &evergreen_fini,
1519         .suspend = &evergreen_suspend,
1520         .resume = &evergreen_resume,
1521         .asic_reset = &evergreen_asic_reset,
1522         .vga_set_state = &r600_vga_set_state,
1523         .ioctl_wait_idle = r600_ioctl_wait_idle,
1524         .gui_idle = &r600_gui_idle,
1525         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1526         .get_xclk = &r600_get_xclk,
1527         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1528         .gart = {
1529                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1530                 .set_page = &rs600_gart_set_page,
1531         },
1532         .ring = {
1533                 [RADEON_RING_TYPE_GFX_INDEX] = {
1534                         .ib_execute = &evergreen_ring_ib_execute,
1535                         .emit_fence = &r600_fence_ring_emit,
1536                         .emit_semaphore = &r600_semaphore_ring_emit,
1537                         .cs_parse = &evergreen_cs_parse,
1538                         .ring_test = &r600_ring_test,
1539                         .ib_test = &r600_ib_test,
1540                         .is_lockup = &evergreen_gfx_is_lockup,
1541                         .get_rptr = &radeon_ring_generic_get_rptr,
1542                         .get_wptr = &radeon_ring_generic_get_wptr,
1543                         .set_wptr = &radeon_ring_generic_set_wptr,
1544                 },
1545                 [R600_RING_TYPE_DMA_INDEX] = {
1546                         .ib_execute = &evergreen_dma_ring_ib_execute,
1547                         .emit_fence = &evergreen_dma_fence_ring_emit,
1548                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1549                         .cs_parse = &evergreen_dma_cs_parse,
1550                         .ring_test = &r600_dma_ring_test,
1551                         .ib_test = &r600_dma_ib_test,
1552                         .is_lockup = &evergreen_dma_is_lockup,
1553                         .get_rptr = &radeon_ring_generic_get_rptr,
1554                         .get_wptr = &radeon_ring_generic_get_wptr,
1555                         .set_wptr = &radeon_ring_generic_set_wptr,
1556                 },
1557                 [R600_RING_TYPE_UVD_INDEX] = {
1558                         .ib_execute = &r600_uvd_ib_execute,
1559                         .emit_fence = &r600_uvd_fence_emit,
1560                         .emit_semaphore = &r600_uvd_semaphore_emit,
1561                         .cs_parse = &radeon_uvd_cs_parse,
1562                         .ring_test = &r600_uvd_ring_test,
1563                         .ib_test = &r600_uvd_ib_test,
1564                         .is_lockup = &radeon_ring_test_lockup,
1565                         .get_rptr = &radeon_ring_generic_get_rptr,
1566                         .get_wptr = &radeon_ring_generic_get_wptr,
1567                         .set_wptr = &radeon_ring_generic_set_wptr,
1568                 }
1569         },
1570         .irq = {
1571                 .set = &evergreen_irq_set,
1572                 .process = &evergreen_irq_process,
1573         },
1574         .display = {
1575                 .bandwidth_update = &evergreen_bandwidth_update,
1576                 .get_vblank_counter = &evergreen_get_vblank_counter,
1577                 .wait_for_vblank = &dce4_wait_for_vblank,
1578                 .set_backlight_level = &atombios_set_backlight_level,
1579                 .get_backlight_level = &atombios_get_backlight_level,
1580                 .hdmi_enable = &evergreen_hdmi_enable,
1581                 .hdmi_setmode = &evergreen_hdmi_setmode,
1582         },
1583         .copy = {
1584                 .blit = &r600_copy_blit,
1585                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1586                 .dma = &evergreen_copy_dma,
1587                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1588                 .copy = &evergreen_copy_dma,
1589                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1590         },
1591         .surface = {
1592                 .set_reg = r600_set_surface_reg,
1593                 .clear_reg = r600_clear_surface_reg,
1594         },
1595         .hpd = {
1596                 .init = &evergreen_hpd_init,
1597                 .fini = &evergreen_hpd_fini,
1598                 .sense = &evergreen_hpd_sense,
1599                 .set_polarity = &evergreen_hpd_set_polarity,
1600         },
1601         .pm = {
1602                 .misc = &evergreen_pm_misc,
1603                 .prepare = &evergreen_pm_prepare,
1604                 .finish = &evergreen_pm_finish,
1605                 .init_profile = &sumo_pm_init_profile,
1606                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1607                 .get_engine_clock = &radeon_atom_get_engine_clock,
1608                 .set_engine_clock = &radeon_atom_set_engine_clock,
1609                 .get_memory_clock = NULL,
1610                 .set_memory_clock = NULL,
1611                 .get_pcie_lanes = NULL,
1612                 .set_pcie_lanes = NULL,
1613                 .set_clock_gating = NULL,
1614                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1615                 .get_temperature = &sumo_get_temp,
1616         },
1617         .dpm = {
1618                 .init = &sumo_dpm_init,
1619                 .setup_asic = &sumo_dpm_setup_asic,
1620                 .enable = &sumo_dpm_enable,
1621                 .disable = &sumo_dpm_disable,
1622                 .set_power_state = &sumo_dpm_set_power_state,
1623                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1624                 .fini = &sumo_dpm_fini,
1625                 .get_sclk = &sumo_dpm_get_sclk,
1626                 .get_mclk = &sumo_dpm_get_mclk,
1627                 .print_power_state = &sumo_dpm_print_power_state,
1628         },
1629         .pflip = {
1630                 .pre_page_flip = &evergreen_pre_page_flip,
1631                 .page_flip = &evergreen_page_flip,
1632                 .post_page_flip = &evergreen_post_page_flip,
1633         },
1634 };
1635
1636 static struct radeon_asic btc_asic = {
1637         .init = &evergreen_init,
1638         .fini = &evergreen_fini,
1639         .suspend = &evergreen_suspend,
1640         .resume = &evergreen_resume,
1641         .asic_reset = &evergreen_asic_reset,
1642         .vga_set_state = &r600_vga_set_state,
1643         .ioctl_wait_idle = r600_ioctl_wait_idle,
1644         .gui_idle = &r600_gui_idle,
1645         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1646         .get_xclk = &rv770_get_xclk,
1647         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1648         .gart = {
1649                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1650                 .set_page = &rs600_gart_set_page,
1651         },
1652         .ring = {
1653                 [RADEON_RING_TYPE_GFX_INDEX] = {
1654                         .ib_execute = &evergreen_ring_ib_execute,
1655                         .emit_fence = &r600_fence_ring_emit,
1656                         .emit_semaphore = &r600_semaphore_ring_emit,
1657                         .cs_parse = &evergreen_cs_parse,
1658                         .ring_test = &r600_ring_test,
1659                         .ib_test = &r600_ib_test,
1660                         .is_lockup = &evergreen_gfx_is_lockup,
1661                         .get_rptr = &radeon_ring_generic_get_rptr,
1662                         .get_wptr = &radeon_ring_generic_get_wptr,
1663                         .set_wptr = &radeon_ring_generic_set_wptr,
1664                 },
1665                 [R600_RING_TYPE_DMA_INDEX] = {
1666                         .ib_execute = &evergreen_dma_ring_ib_execute,
1667                         .emit_fence = &evergreen_dma_fence_ring_emit,
1668                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1669                         .cs_parse = &evergreen_dma_cs_parse,
1670                         .ring_test = &r600_dma_ring_test,
1671                         .ib_test = &r600_dma_ib_test,
1672                         .is_lockup = &evergreen_dma_is_lockup,
1673                         .get_rptr = &radeon_ring_generic_get_rptr,
1674                         .get_wptr = &radeon_ring_generic_get_wptr,
1675                         .set_wptr = &radeon_ring_generic_set_wptr,
1676                 },
1677                 [R600_RING_TYPE_UVD_INDEX] = {
1678                         .ib_execute = &r600_uvd_ib_execute,
1679                         .emit_fence = &r600_uvd_fence_emit,
1680                         .emit_semaphore = &r600_uvd_semaphore_emit,
1681                         .cs_parse = &radeon_uvd_cs_parse,
1682                         .ring_test = &r600_uvd_ring_test,
1683                         .ib_test = &r600_uvd_ib_test,
1684                         .is_lockup = &radeon_ring_test_lockup,
1685                         .get_rptr = &radeon_ring_generic_get_rptr,
1686                         .get_wptr = &radeon_ring_generic_get_wptr,
1687                         .set_wptr = &radeon_ring_generic_set_wptr,
1688                 }
1689         },
1690         .irq = {
1691                 .set = &evergreen_irq_set,
1692                 .process = &evergreen_irq_process,
1693         },
1694         .display = {
1695                 .bandwidth_update = &evergreen_bandwidth_update,
1696                 .get_vblank_counter = &evergreen_get_vblank_counter,
1697                 .wait_for_vblank = &dce4_wait_for_vblank,
1698                 .set_backlight_level = &atombios_set_backlight_level,
1699                 .get_backlight_level = &atombios_get_backlight_level,
1700                 .hdmi_enable = &evergreen_hdmi_enable,
1701                 .hdmi_setmode = &evergreen_hdmi_setmode,
1702         },
1703         .copy = {
1704                 .blit = &r600_copy_blit,
1705                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1706                 .dma = &evergreen_copy_dma,
1707                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1708                 .copy = &evergreen_copy_dma,
1709                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1710         },
1711         .surface = {
1712                 .set_reg = r600_set_surface_reg,
1713                 .clear_reg = r600_clear_surface_reg,
1714         },
1715         .hpd = {
1716                 .init = &evergreen_hpd_init,
1717                 .fini = &evergreen_hpd_fini,
1718                 .sense = &evergreen_hpd_sense,
1719                 .set_polarity = &evergreen_hpd_set_polarity,
1720         },
1721         .pm = {
1722                 .misc = &evergreen_pm_misc,
1723                 .prepare = &evergreen_pm_prepare,
1724                 .finish = &evergreen_pm_finish,
1725                 .init_profile = &btc_pm_init_profile,
1726                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1727                 .get_engine_clock = &radeon_atom_get_engine_clock,
1728                 .set_engine_clock = &radeon_atom_set_engine_clock,
1729                 .get_memory_clock = &radeon_atom_get_memory_clock,
1730                 .set_memory_clock = &radeon_atom_set_memory_clock,
1731                 .get_pcie_lanes = &r600_get_pcie_lanes,
1732                 .set_pcie_lanes = &r600_set_pcie_lanes,
1733                 .set_clock_gating = NULL,
1734                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1735                 .get_temperature = &evergreen_get_temp,
1736         },
1737         .dpm = {
1738                 .init = &btc_dpm_init,
1739                 .setup_asic = &btc_dpm_setup_asic,
1740                 .enable = &btc_dpm_enable,
1741                 .disable = &btc_dpm_disable,
1742                 .set_power_state = &btc_dpm_set_power_state,
1743                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1744                 .fini = &btc_dpm_fini,
1745                 .get_sclk = &rv770_dpm_get_sclk,
1746                 .get_mclk = &rv770_dpm_get_mclk,
1747                 .print_power_state = &rv770_dpm_print_power_state,
1748         },
1749         .pflip = {
1750                 .pre_page_flip = &evergreen_pre_page_flip,
1751                 .page_flip = &evergreen_page_flip,
1752                 .post_page_flip = &evergreen_post_page_flip,
1753         },
1754 };
1755
1756 static struct radeon_asic cayman_asic = {
1757         .init = &cayman_init,
1758         .fini = &cayman_fini,
1759         .suspend = &cayman_suspend,
1760         .resume = &cayman_resume,
1761         .asic_reset = &cayman_asic_reset,
1762         .vga_set_state = &r600_vga_set_state,
1763         .ioctl_wait_idle = r600_ioctl_wait_idle,
1764         .gui_idle = &r600_gui_idle,
1765         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1766         .get_xclk = &rv770_get_xclk,
1767         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1768         .gart = {
1769                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1770                 .set_page = &rs600_gart_set_page,
1771         },
1772         .vm = {
1773                 .init = &cayman_vm_init,
1774                 .fini = &cayman_vm_fini,
1775                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1776                 .set_page = &cayman_vm_set_page,
1777         },
1778         .ring = {
1779                 [RADEON_RING_TYPE_GFX_INDEX] = {
1780                         .ib_execute = &cayman_ring_ib_execute,
1781                         .ib_parse = &evergreen_ib_parse,
1782                         .emit_fence = &cayman_fence_ring_emit,
1783                         .emit_semaphore = &r600_semaphore_ring_emit,
1784                         .cs_parse = &evergreen_cs_parse,
1785                         .ring_test = &r600_ring_test,
1786                         .ib_test = &r600_ib_test,
1787                         .is_lockup = &cayman_gfx_is_lockup,
1788                         .vm_flush = &cayman_vm_flush,
1789                         .get_rptr = &radeon_ring_generic_get_rptr,
1790                         .get_wptr = &radeon_ring_generic_get_wptr,
1791                         .set_wptr = &radeon_ring_generic_set_wptr,
1792                 },
1793                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1794                         .ib_execute = &cayman_ring_ib_execute,
1795                         .ib_parse = &evergreen_ib_parse,
1796                         .emit_fence = &cayman_fence_ring_emit,
1797                         .emit_semaphore = &r600_semaphore_ring_emit,
1798                         .cs_parse = &evergreen_cs_parse,
1799                         .ring_test = &r600_ring_test,
1800                         .ib_test = &r600_ib_test,
1801                         .is_lockup = &cayman_gfx_is_lockup,
1802                         .vm_flush = &cayman_vm_flush,
1803                         .get_rptr = &radeon_ring_generic_get_rptr,
1804                         .get_wptr = &radeon_ring_generic_get_wptr,
1805                         .set_wptr = &radeon_ring_generic_set_wptr,
1806                 },
1807                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1808                         .ib_execute = &cayman_ring_ib_execute,
1809                         .ib_parse = &evergreen_ib_parse,
1810                         .emit_fence = &cayman_fence_ring_emit,
1811                         .emit_semaphore = &r600_semaphore_ring_emit,
1812                         .cs_parse = &evergreen_cs_parse,
1813                         .ring_test = &r600_ring_test,
1814                         .ib_test = &r600_ib_test,
1815                         .is_lockup = &cayman_gfx_is_lockup,
1816                         .vm_flush = &cayman_vm_flush,
1817                         .get_rptr = &radeon_ring_generic_get_rptr,
1818                         .get_wptr = &radeon_ring_generic_get_wptr,
1819                         .set_wptr = &radeon_ring_generic_set_wptr,
1820                 },
1821                 [R600_RING_TYPE_DMA_INDEX] = {
1822                         .ib_execute = &cayman_dma_ring_ib_execute,
1823                         .ib_parse = &evergreen_dma_ib_parse,
1824                         .emit_fence = &evergreen_dma_fence_ring_emit,
1825                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1826                         .cs_parse = &evergreen_dma_cs_parse,
1827                         .ring_test = &r600_dma_ring_test,
1828                         .ib_test = &r600_dma_ib_test,
1829                         .is_lockup = &cayman_dma_is_lockup,
1830                         .vm_flush = &cayman_dma_vm_flush,
1831                         .get_rptr = &radeon_ring_generic_get_rptr,
1832                         .get_wptr = &radeon_ring_generic_get_wptr,
1833                         .set_wptr = &radeon_ring_generic_set_wptr,
1834                 },
1835                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1836                         .ib_execute = &cayman_dma_ring_ib_execute,
1837                         .ib_parse = &evergreen_dma_ib_parse,
1838                         .emit_fence = &evergreen_dma_fence_ring_emit,
1839                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1840                         .cs_parse = &evergreen_dma_cs_parse,
1841                         .ring_test = &r600_dma_ring_test,
1842                         .ib_test = &r600_dma_ib_test,
1843                         .is_lockup = &cayman_dma_is_lockup,
1844                         .vm_flush = &cayman_dma_vm_flush,
1845                         .get_rptr = &radeon_ring_generic_get_rptr,
1846                         .get_wptr = &radeon_ring_generic_get_wptr,
1847                         .set_wptr = &radeon_ring_generic_set_wptr,
1848                 },
1849                 [R600_RING_TYPE_UVD_INDEX] = {
1850                         .ib_execute = &r600_uvd_ib_execute,
1851                         .emit_fence = &r600_uvd_fence_emit,
1852                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1853                         .cs_parse = &radeon_uvd_cs_parse,
1854                         .ring_test = &r600_uvd_ring_test,
1855                         .ib_test = &r600_uvd_ib_test,
1856                         .is_lockup = &radeon_ring_test_lockup,
1857                         .get_rptr = &radeon_ring_generic_get_rptr,
1858                         .get_wptr = &radeon_ring_generic_get_wptr,
1859                         .set_wptr = &radeon_ring_generic_set_wptr,
1860                 }
1861         },
1862         .irq = {
1863                 .set = &evergreen_irq_set,
1864                 .process = &evergreen_irq_process,
1865         },
1866         .display = {
1867                 .bandwidth_update = &evergreen_bandwidth_update,
1868                 .get_vblank_counter = &evergreen_get_vblank_counter,
1869                 .wait_for_vblank = &dce4_wait_for_vblank,
1870                 .set_backlight_level = &atombios_set_backlight_level,
1871                 .get_backlight_level = &atombios_get_backlight_level,
1872                 .hdmi_enable = &evergreen_hdmi_enable,
1873                 .hdmi_setmode = &evergreen_hdmi_setmode,
1874         },
1875         .copy = {
1876                 .blit = &r600_copy_blit,
1877                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1878                 .dma = &evergreen_copy_dma,
1879                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1880                 .copy = &evergreen_copy_dma,
1881                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1882         },
1883         .surface = {
1884                 .set_reg = r600_set_surface_reg,
1885                 .clear_reg = r600_clear_surface_reg,
1886         },
1887         .hpd = {
1888                 .init = &evergreen_hpd_init,
1889                 .fini = &evergreen_hpd_fini,
1890                 .sense = &evergreen_hpd_sense,
1891                 .set_polarity = &evergreen_hpd_set_polarity,
1892         },
1893         .pm = {
1894                 .misc = &evergreen_pm_misc,
1895                 .prepare = &evergreen_pm_prepare,
1896                 .finish = &evergreen_pm_finish,
1897                 .init_profile = &btc_pm_init_profile,
1898                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1899                 .get_engine_clock = &radeon_atom_get_engine_clock,
1900                 .set_engine_clock = &radeon_atom_set_engine_clock,
1901                 .get_memory_clock = &radeon_atom_get_memory_clock,
1902                 .set_memory_clock = &radeon_atom_set_memory_clock,
1903                 .get_pcie_lanes = &r600_get_pcie_lanes,
1904                 .set_pcie_lanes = &r600_set_pcie_lanes,
1905                 .set_clock_gating = NULL,
1906                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1907                 .get_temperature = &evergreen_get_temp,
1908         },
1909         .pflip = {
1910                 .pre_page_flip = &evergreen_pre_page_flip,
1911                 .page_flip = &evergreen_page_flip,
1912                 .post_page_flip = &evergreen_post_page_flip,
1913         },
1914 };
1915
1916 static struct radeon_asic trinity_asic = {
1917         .init = &cayman_init,
1918         .fini = &cayman_fini,
1919         .suspend = &cayman_suspend,
1920         .resume = &cayman_resume,
1921         .asic_reset = &cayman_asic_reset,
1922         .vga_set_state = &r600_vga_set_state,
1923         .ioctl_wait_idle = r600_ioctl_wait_idle,
1924         .gui_idle = &r600_gui_idle,
1925         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1926         .get_xclk = &r600_get_xclk,
1927         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1928         .gart = {
1929                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1930                 .set_page = &rs600_gart_set_page,
1931         },
1932         .vm = {
1933                 .init = &cayman_vm_init,
1934                 .fini = &cayman_vm_fini,
1935                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1936                 .set_page = &cayman_vm_set_page,
1937         },
1938         .ring = {
1939                 [RADEON_RING_TYPE_GFX_INDEX] = {
1940                         .ib_execute = &cayman_ring_ib_execute,
1941                         .ib_parse = &evergreen_ib_parse,
1942                         .emit_fence = &cayman_fence_ring_emit,
1943                         .emit_semaphore = &r600_semaphore_ring_emit,
1944                         .cs_parse = &evergreen_cs_parse,
1945                         .ring_test = &r600_ring_test,
1946                         .ib_test = &r600_ib_test,
1947                         .is_lockup = &cayman_gfx_is_lockup,
1948                         .vm_flush = &cayman_vm_flush,
1949                         .get_rptr = &radeon_ring_generic_get_rptr,
1950                         .get_wptr = &radeon_ring_generic_get_wptr,
1951                         .set_wptr = &radeon_ring_generic_set_wptr,
1952                 },
1953                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1954                         .ib_execute = &cayman_ring_ib_execute,
1955                         .ib_parse = &evergreen_ib_parse,
1956                         .emit_fence = &cayman_fence_ring_emit,
1957                         .emit_semaphore = &r600_semaphore_ring_emit,
1958                         .cs_parse = &evergreen_cs_parse,
1959                         .ring_test = &r600_ring_test,
1960                         .ib_test = &r600_ib_test,
1961                         .is_lockup = &cayman_gfx_is_lockup,
1962                         .vm_flush = &cayman_vm_flush,
1963                         .get_rptr = &radeon_ring_generic_get_rptr,
1964                         .get_wptr = &radeon_ring_generic_get_wptr,
1965                         .set_wptr = &radeon_ring_generic_set_wptr,
1966                 },
1967                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1968                         .ib_execute = &cayman_ring_ib_execute,
1969                         .ib_parse = &evergreen_ib_parse,
1970                         .emit_fence = &cayman_fence_ring_emit,
1971                         .emit_semaphore = &r600_semaphore_ring_emit,
1972                         .cs_parse = &evergreen_cs_parse,
1973                         .ring_test = &r600_ring_test,
1974                         .ib_test = &r600_ib_test,
1975                         .is_lockup = &cayman_gfx_is_lockup,
1976                         .vm_flush = &cayman_vm_flush,
1977                         .get_rptr = &radeon_ring_generic_get_rptr,
1978                         .get_wptr = &radeon_ring_generic_get_wptr,
1979                         .set_wptr = &radeon_ring_generic_set_wptr,
1980                 },
1981                 [R600_RING_TYPE_DMA_INDEX] = {
1982                         .ib_execute = &cayman_dma_ring_ib_execute,
1983                         .ib_parse = &evergreen_dma_ib_parse,
1984                         .emit_fence = &evergreen_dma_fence_ring_emit,
1985                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1986                         .cs_parse = &evergreen_dma_cs_parse,
1987                         .ring_test = &r600_dma_ring_test,
1988                         .ib_test = &r600_dma_ib_test,
1989                         .is_lockup = &cayman_dma_is_lockup,
1990                         .vm_flush = &cayman_dma_vm_flush,
1991                         .get_rptr = &radeon_ring_generic_get_rptr,
1992                         .get_wptr = &radeon_ring_generic_get_wptr,
1993                         .set_wptr = &radeon_ring_generic_set_wptr,
1994                 },
1995                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1996                         .ib_execute = &cayman_dma_ring_ib_execute,
1997                         .ib_parse = &evergreen_dma_ib_parse,
1998                         .emit_fence = &evergreen_dma_fence_ring_emit,
1999                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2000                         .cs_parse = &evergreen_dma_cs_parse,
2001                         .ring_test = &r600_dma_ring_test,
2002                         .ib_test = &r600_dma_ib_test,
2003                         .is_lockup = &cayman_dma_is_lockup,
2004                         .vm_flush = &cayman_dma_vm_flush,
2005                         .get_rptr = &radeon_ring_generic_get_rptr,
2006                         .get_wptr = &radeon_ring_generic_get_wptr,
2007                         .set_wptr = &radeon_ring_generic_set_wptr,
2008                 },
2009                 [R600_RING_TYPE_UVD_INDEX] = {
2010                         .ib_execute = &r600_uvd_ib_execute,
2011                         .emit_fence = &r600_uvd_fence_emit,
2012                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2013                         .cs_parse = &radeon_uvd_cs_parse,
2014                         .ring_test = &r600_uvd_ring_test,
2015                         .ib_test = &r600_uvd_ib_test,
2016                         .is_lockup = &radeon_ring_test_lockup,
2017                         .get_rptr = &radeon_ring_generic_get_rptr,
2018                         .get_wptr = &radeon_ring_generic_get_wptr,
2019                         .set_wptr = &radeon_ring_generic_set_wptr,
2020                 }
2021         },
2022         .irq = {
2023                 .set = &evergreen_irq_set,
2024                 .process = &evergreen_irq_process,
2025         },
2026         .display = {
2027                 .bandwidth_update = &dce6_bandwidth_update,
2028                 .get_vblank_counter = &evergreen_get_vblank_counter,
2029                 .wait_for_vblank = &dce4_wait_for_vblank,
2030                 .set_backlight_level = &atombios_set_backlight_level,
2031                 .get_backlight_level = &atombios_get_backlight_level,
2032         },
2033         .copy = {
2034                 .blit = &r600_copy_blit,
2035                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2036                 .dma = &evergreen_copy_dma,
2037                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2038                 .copy = &evergreen_copy_dma,
2039                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2040         },
2041         .surface = {
2042                 .set_reg = r600_set_surface_reg,
2043                 .clear_reg = r600_clear_surface_reg,
2044         },
2045         .hpd = {
2046                 .init = &evergreen_hpd_init,
2047                 .fini = &evergreen_hpd_fini,
2048                 .sense = &evergreen_hpd_sense,
2049                 .set_polarity = &evergreen_hpd_set_polarity,
2050         },
2051         .pm = {
2052                 .misc = &evergreen_pm_misc,
2053                 .prepare = &evergreen_pm_prepare,
2054                 .finish = &evergreen_pm_finish,
2055                 .init_profile = &sumo_pm_init_profile,
2056                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2057                 .get_engine_clock = &radeon_atom_get_engine_clock,
2058                 .set_engine_clock = &radeon_atom_set_engine_clock,
2059                 .get_memory_clock = NULL,
2060                 .set_memory_clock = NULL,
2061                 .get_pcie_lanes = NULL,
2062                 .set_pcie_lanes = NULL,
2063                 .set_clock_gating = NULL,
2064                 .set_uvd_clocks = &sumo_set_uvd_clocks,
2065                 .get_temperature = &tn_get_temp,
2066         },
2067         .pflip = {
2068                 .pre_page_flip = &evergreen_pre_page_flip,
2069                 .page_flip = &evergreen_page_flip,
2070                 .post_page_flip = &evergreen_post_page_flip,
2071         },
2072 };
2073
2074 static struct radeon_asic si_asic = {
2075         .init = &si_init,
2076         .fini = &si_fini,
2077         .suspend = &si_suspend,
2078         .resume = &si_resume,
2079         .asic_reset = &si_asic_reset,
2080         .vga_set_state = &r600_vga_set_state,
2081         .ioctl_wait_idle = r600_ioctl_wait_idle,
2082         .gui_idle = &r600_gui_idle,
2083         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2084         .get_xclk = &si_get_xclk,
2085         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
2086         .gart = {
2087                 .tlb_flush = &si_pcie_gart_tlb_flush,
2088                 .set_page = &rs600_gart_set_page,
2089         },
2090         .vm = {
2091                 .init = &si_vm_init,
2092                 .fini = &si_vm_fini,
2093                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2094                 .set_page = &si_vm_set_page,
2095         },
2096         .ring = {
2097                 [RADEON_RING_TYPE_GFX_INDEX] = {
2098                         .ib_execute = &si_ring_ib_execute,
2099                         .ib_parse = &si_ib_parse,
2100                         .emit_fence = &si_fence_ring_emit,
2101                         .emit_semaphore = &r600_semaphore_ring_emit,
2102                         .cs_parse = NULL,
2103                         .ring_test = &r600_ring_test,
2104                         .ib_test = &r600_ib_test,
2105                         .is_lockup = &si_gfx_is_lockup,
2106                         .vm_flush = &si_vm_flush,
2107                         .get_rptr = &radeon_ring_generic_get_rptr,
2108                         .get_wptr = &radeon_ring_generic_get_wptr,
2109                         .set_wptr = &radeon_ring_generic_set_wptr,
2110                 },
2111                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2112                         .ib_execute = &si_ring_ib_execute,
2113                         .ib_parse = &si_ib_parse,
2114                         .emit_fence = &si_fence_ring_emit,
2115                         .emit_semaphore = &r600_semaphore_ring_emit,
2116                         .cs_parse = NULL,
2117                         .ring_test = &r600_ring_test,
2118                         .ib_test = &r600_ib_test,
2119                         .is_lockup = &si_gfx_is_lockup,
2120                         .vm_flush = &si_vm_flush,
2121                         .get_rptr = &radeon_ring_generic_get_rptr,
2122                         .get_wptr = &radeon_ring_generic_get_wptr,
2123                         .set_wptr = &radeon_ring_generic_set_wptr,
2124                 },
2125                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2126                         .ib_execute = &si_ring_ib_execute,
2127                         .ib_parse = &si_ib_parse,
2128                         .emit_fence = &si_fence_ring_emit,
2129                         .emit_semaphore = &r600_semaphore_ring_emit,
2130                         .cs_parse = NULL,
2131                         .ring_test = &r600_ring_test,
2132                         .ib_test = &r600_ib_test,
2133                         .is_lockup = &si_gfx_is_lockup,
2134                         .vm_flush = &si_vm_flush,
2135                         .get_rptr = &radeon_ring_generic_get_rptr,
2136                         .get_wptr = &radeon_ring_generic_get_wptr,
2137                         .set_wptr = &radeon_ring_generic_set_wptr,
2138                 },
2139                 [R600_RING_TYPE_DMA_INDEX] = {
2140                         .ib_execute = &cayman_dma_ring_ib_execute,
2141                         .ib_parse = &evergreen_dma_ib_parse,
2142                         .emit_fence = &evergreen_dma_fence_ring_emit,
2143                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2144                         .cs_parse = NULL,
2145                         .ring_test = &r600_dma_ring_test,
2146                         .ib_test = &r600_dma_ib_test,
2147                         .is_lockup = &si_dma_is_lockup,
2148                         .vm_flush = &si_dma_vm_flush,
2149                         .get_rptr = &radeon_ring_generic_get_rptr,
2150                         .get_wptr = &radeon_ring_generic_get_wptr,
2151                         .set_wptr = &radeon_ring_generic_set_wptr,
2152                 },
2153                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2154                         .ib_execute = &cayman_dma_ring_ib_execute,
2155                         .ib_parse = &evergreen_dma_ib_parse,
2156                         .emit_fence = &evergreen_dma_fence_ring_emit,
2157                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2158                         .cs_parse = NULL,
2159                         .ring_test = &r600_dma_ring_test,
2160                         .ib_test = &r600_dma_ib_test,
2161                         .is_lockup = &si_dma_is_lockup,
2162                         .vm_flush = &si_dma_vm_flush,
2163                         .get_rptr = &radeon_ring_generic_get_rptr,
2164                         .get_wptr = &radeon_ring_generic_get_wptr,
2165                         .set_wptr = &radeon_ring_generic_set_wptr,
2166                 },
2167                 [R600_RING_TYPE_UVD_INDEX] = {
2168                         .ib_execute = &r600_uvd_ib_execute,
2169                         .emit_fence = &r600_uvd_fence_emit,
2170                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2171                         .cs_parse = &radeon_uvd_cs_parse,
2172                         .ring_test = &r600_uvd_ring_test,
2173                         .ib_test = &r600_uvd_ib_test,
2174                         .is_lockup = &radeon_ring_test_lockup,
2175                         .get_rptr = &radeon_ring_generic_get_rptr,
2176                         .get_wptr = &radeon_ring_generic_get_wptr,
2177                         .set_wptr = &radeon_ring_generic_set_wptr,
2178                 }
2179         },
2180         .irq = {
2181                 .set = &si_irq_set,
2182                 .process = &si_irq_process,
2183         },
2184         .display = {
2185                 .bandwidth_update = &dce6_bandwidth_update,
2186                 .get_vblank_counter = &evergreen_get_vblank_counter,
2187                 .wait_for_vblank = &dce4_wait_for_vblank,
2188                 .set_backlight_level = &atombios_set_backlight_level,
2189                 .get_backlight_level = &atombios_get_backlight_level,
2190         },
2191         .copy = {
2192                 .blit = NULL,
2193                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2194                 .dma = &si_copy_dma,
2195                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2196                 .copy = &si_copy_dma,
2197                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2198         },
2199         .surface = {
2200                 .set_reg = r600_set_surface_reg,
2201                 .clear_reg = r600_clear_surface_reg,
2202         },
2203         .hpd = {
2204                 .init = &evergreen_hpd_init,
2205                 .fini = &evergreen_hpd_fini,
2206                 .sense = &evergreen_hpd_sense,
2207                 .set_polarity = &evergreen_hpd_set_polarity,
2208         },
2209         .pm = {
2210                 .misc = &evergreen_pm_misc,
2211                 .prepare = &evergreen_pm_prepare,
2212                 .finish = &evergreen_pm_finish,
2213                 .init_profile = &sumo_pm_init_profile,
2214                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2215                 .get_engine_clock = &radeon_atom_get_engine_clock,
2216                 .set_engine_clock = &radeon_atom_set_engine_clock,
2217                 .get_memory_clock = &radeon_atom_get_memory_clock,
2218                 .set_memory_clock = &radeon_atom_set_memory_clock,
2219                 .get_pcie_lanes = &r600_get_pcie_lanes,
2220                 .set_pcie_lanes = &r600_set_pcie_lanes,
2221                 .set_clock_gating = NULL,
2222                 .set_uvd_clocks = &si_set_uvd_clocks,
2223                 .get_temperature = &si_get_temp,
2224         },
2225         .pflip = {
2226                 .pre_page_flip = &evergreen_pre_page_flip,
2227                 .page_flip = &evergreen_page_flip,
2228                 .post_page_flip = &evergreen_post_page_flip,
2229         },
2230 };
2231
2232 static struct radeon_asic ci_asic = {
2233         .init = &cik_init,
2234         .fini = &cik_fini,
2235         .suspend = &cik_suspend,
2236         .resume = &cik_resume,
2237         .asic_reset = &cik_asic_reset,
2238         .vga_set_state = &r600_vga_set_state,
2239         .ioctl_wait_idle = NULL,
2240         .gui_idle = &r600_gui_idle,
2241         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2242         .get_xclk = &cik_get_xclk,
2243         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2244         .gart = {
2245                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2246                 .set_page = &rs600_gart_set_page,
2247         },
2248         .vm = {
2249                 .init = &cik_vm_init,
2250                 .fini = &cik_vm_fini,
2251                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2252                 .set_page = &cik_vm_set_page,
2253         },
2254         .ring = {
2255                 [RADEON_RING_TYPE_GFX_INDEX] = {
2256                         .ib_execute = &cik_ring_ib_execute,
2257                         .ib_parse = &cik_ib_parse,
2258                         .emit_fence = &cik_fence_gfx_ring_emit,
2259                         .emit_semaphore = &cik_semaphore_ring_emit,
2260                         .cs_parse = NULL,
2261                         .ring_test = &cik_ring_test,
2262                         .ib_test = &cik_ib_test,
2263                         .is_lockup = &cik_gfx_is_lockup,
2264                         .vm_flush = &cik_vm_flush,
2265                         .get_rptr = &radeon_ring_generic_get_rptr,
2266                         .get_wptr = &radeon_ring_generic_get_wptr,
2267                         .set_wptr = &radeon_ring_generic_set_wptr,
2268                 },
2269                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2270                         .ib_execute = &cik_ring_ib_execute,
2271                         .ib_parse = &cik_ib_parse,
2272                         .emit_fence = &cik_fence_compute_ring_emit,
2273                         .emit_semaphore = &cik_semaphore_ring_emit,
2274                         .cs_parse = NULL,
2275                         .ring_test = &cik_ring_test,
2276                         .ib_test = &cik_ib_test,
2277                         .is_lockup = &cik_gfx_is_lockup,
2278                         .vm_flush = &cik_vm_flush,
2279                         .get_rptr = &cik_compute_ring_get_rptr,
2280                         .get_wptr = &cik_compute_ring_get_wptr,
2281                         .set_wptr = &cik_compute_ring_set_wptr,
2282                 },
2283                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2284                         .ib_execute = &cik_ring_ib_execute,
2285                         .ib_parse = &cik_ib_parse,
2286                         .emit_fence = &cik_fence_compute_ring_emit,
2287                         .emit_semaphore = &cik_semaphore_ring_emit,
2288                         .cs_parse = NULL,
2289                         .ring_test = &cik_ring_test,
2290                         .ib_test = &cik_ib_test,
2291                         .is_lockup = &cik_gfx_is_lockup,
2292                         .vm_flush = &cik_vm_flush,
2293                         .get_rptr = &cik_compute_ring_get_rptr,
2294                         .get_wptr = &cik_compute_ring_get_wptr,
2295                         .set_wptr = &cik_compute_ring_set_wptr,
2296                 },
2297                 [R600_RING_TYPE_DMA_INDEX] = {
2298                         .ib_execute = &cik_sdma_ring_ib_execute,
2299                         .ib_parse = &cik_ib_parse,
2300                         .emit_fence = &cik_sdma_fence_ring_emit,
2301                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2302                         .cs_parse = NULL,
2303                         .ring_test = &cik_sdma_ring_test,
2304                         .ib_test = &cik_sdma_ib_test,
2305                         .is_lockup = &cik_sdma_is_lockup,
2306                         .vm_flush = &cik_dma_vm_flush,
2307                         .get_rptr = &radeon_ring_generic_get_rptr,
2308                         .get_wptr = &radeon_ring_generic_get_wptr,
2309                         .set_wptr = &radeon_ring_generic_set_wptr,
2310                 },
2311                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2312                         .ib_execute = &cik_sdma_ring_ib_execute,
2313                         .ib_parse = &cik_ib_parse,
2314                         .emit_fence = &cik_sdma_fence_ring_emit,
2315                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2316                         .cs_parse = NULL,
2317                         .ring_test = &cik_sdma_ring_test,
2318                         .ib_test = &cik_sdma_ib_test,
2319                         .is_lockup = &cik_sdma_is_lockup,
2320                         .vm_flush = &cik_dma_vm_flush,
2321                         .get_rptr = &radeon_ring_generic_get_rptr,
2322                         .get_wptr = &radeon_ring_generic_get_wptr,
2323                         .set_wptr = &radeon_ring_generic_set_wptr,
2324                 },
2325                 [R600_RING_TYPE_UVD_INDEX] = {
2326                         .ib_execute = &r600_uvd_ib_execute,
2327                         .emit_fence = &r600_uvd_fence_emit,
2328                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2329                         .cs_parse = &radeon_uvd_cs_parse,
2330                         .ring_test = &r600_uvd_ring_test,
2331                         .ib_test = &r600_uvd_ib_test,
2332                         .is_lockup = &radeon_ring_test_lockup,
2333                         .get_rptr = &radeon_ring_generic_get_rptr,
2334                         .get_wptr = &radeon_ring_generic_get_wptr,
2335                         .set_wptr = &radeon_ring_generic_set_wptr,
2336                 }
2337         },
2338         .irq = {
2339                 .set = &cik_irq_set,
2340                 .process = &cik_irq_process,
2341         },
2342         .display = {
2343                 .bandwidth_update = &dce8_bandwidth_update,
2344                 .get_vblank_counter = &evergreen_get_vblank_counter,
2345                 .wait_for_vblank = &dce4_wait_for_vblank,
2346         },
2347         .copy = {
2348                 .blit = NULL,
2349                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2350                 .dma = &cik_copy_dma,
2351                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2352                 .copy = &cik_copy_dma,
2353                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2354         },
2355         .surface = {
2356                 .set_reg = r600_set_surface_reg,
2357                 .clear_reg = r600_clear_surface_reg,
2358         },
2359         .hpd = {
2360                 .init = &evergreen_hpd_init,
2361                 .fini = &evergreen_hpd_fini,
2362                 .sense = &evergreen_hpd_sense,
2363                 .set_polarity = &evergreen_hpd_set_polarity,
2364         },
2365         .pm = {
2366                 .misc = &evergreen_pm_misc,
2367                 .prepare = &evergreen_pm_prepare,
2368                 .finish = &evergreen_pm_finish,
2369                 .init_profile = &sumo_pm_init_profile,
2370                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2371                 .get_engine_clock = &radeon_atom_get_engine_clock,
2372                 .set_engine_clock = &radeon_atom_set_engine_clock,
2373                 .get_memory_clock = &radeon_atom_get_memory_clock,
2374                 .set_memory_clock = &radeon_atom_set_memory_clock,
2375                 .get_pcie_lanes = NULL,
2376                 .set_pcie_lanes = NULL,
2377                 .set_clock_gating = NULL,
2378                 .set_uvd_clocks = &cik_set_uvd_clocks,
2379         },
2380         .pflip = {
2381                 .pre_page_flip = &evergreen_pre_page_flip,
2382                 .page_flip = &evergreen_page_flip,
2383                 .post_page_flip = &evergreen_post_page_flip,
2384         },
2385 };
2386
2387 static struct radeon_asic kv_asic = {
2388         .init = &cik_init,
2389         .fini = &cik_fini,
2390         .suspend = &cik_suspend,
2391         .resume = &cik_resume,
2392         .asic_reset = &cik_asic_reset,
2393         .vga_set_state = &r600_vga_set_state,
2394         .ioctl_wait_idle = NULL,
2395         .gui_idle = &r600_gui_idle,
2396         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2397         .get_xclk = &cik_get_xclk,
2398         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2399         .gart = {
2400                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2401                 .set_page = &rs600_gart_set_page,
2402         },
2403         .vm = {
2404                 .init = &cik_vm_init,
2405                 .fini = &cik_vm_fini,
2406                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2407                 .set_page = &cik_vm_set_page,
2408         },
2409         .ring = {
2410                 [RADEON_RING_TYPE_GFX_INDEX] = {
2411                         .ib_execute = &cik_ring_ib_execute,
2412                         .ib_parse = &cik_ib_parse,
2413                         .emit_fence = &cik_fence_gfx_ring_emit,
2414                         .emit_semaphore = &cik_semaphore_ring_emit,
2415                         .cs_parse = NULL,
2416                         .ring_test = &cik_ring_test,
2417                         .ib_test = &cik_ib_test,
2418                         .is_lockup = &cik_gfx_is_lockup,
2419                         .vm_flush = &cik_vm_flush,
2420                         .get_rptr = &radeon_ring_generic_get_rptr,
2421                         .get_wptr = &radeon_ring_generic_get_wptr,
2422                         .set_wptr = &radeon_ring_generic_set_wptr,
2423                 },
2424                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2425                         .ib_execute = &cik_ring_ib_execute,
2426                         .ib_parse = &cik_ib_parse,
2427                         .emit_fence = &cik_fence_compute_ring_emit,
2428                         .emit_semaphore = &cik_semaphore_ring_emit,
2429                         .cs_parse = NULL,
2430                         .ring_test = &cik_ring_test,
2431                         .ib_test = &cik_ib_test,
2432                         .is_lockup = &cik_gfx_is_lockup,
2433                         .vm_flush = &cik_vm_flush,
2434                         .get_rptr = &cik_compute_ring_get_rptr,
2435                         .get_wptr = &cik_compute_ring_get_wptr,
2436                         .set_wptr = &cik_compute_ring_set_wptr,
2437                 },
2438                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2439                         .ib_execute = &cik_ring_ib_execute,
2440                         .ib_parse = &cik_ib_parse,
2441                         .emit_fence = &cik_fence_compute_ring_emit,
2442                         .emit_semaphore = &cik_semaphore_ring_emit,
2443                         .cs_parse = NULL,
2444                         .ring_test = &cik_ring_test,
2445                         .ib_test = &cik_ib_test,
2446                         .is_lockup = &cik_gfx_is_lockup,
2447                         .vm_flush = &cik_vm_flush,
2448                         .get_rptr = &cik_compute_ring_get_rptr,
2449                         .get_wptr = &cik_compute_ring_get_wptr,
2450                         .set_wptr = &cik_compute_ring_set_wptr,
2451                 },
2452                 [R600_RING_TYPE_DMA_INDEX] = {
2453                         .ib_execute = &cik_sdma_ring_ib_execute,
2454                         .ib_parse = &cik_ib_parse,
2455                         .emit_fence = &cik_sdma_fence_ring_emit,
2456                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2457                         .cs_parse = NULL,
2458                         .ring_test = &cik_sdma_ring_test,
2459                         .ib_test = &cik_sdma_ib_test,
2460                         .is_lockup = &cik_sdma_is_lockup,
2461                         .vm_flush = &cik_dma_vm_flush,
2462                         .get_rptr = &radeon_ring_generic_get_rptr,
2463                         .get_wptr = &radeon_ring_generic_get_wptr,
2464                         .set_wptr = &radeon_ring_generic_set_wptr,
2465                 },
2466                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2467                         .ib_execute = &cik_sdma_ring_ib_execute,
2468                         .ib_parse = &cik_ib_parse,
2469                         .emit_fence = &cik_sdma_fence_ring_emit,
2470                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2471                         .cs_parse = NULL,
2472                         .ring_test = &cik_sdma_ring_test,
2473                         .ib_test = &cik_sdma_ib_test,
2474                         .is_lockup = &cik_sdma_is_lockup,
2475                         .vm_flush = &cik_dma_vm_flush,
2476                         .get_rptr = &radeon_ring_generic_get_rptr,
2477                         .get_wptr = &radeon_ring_generic_get_wptr,
2478                         .set_wptr = &radeon_ring_generic_set_wptr,
2479                 },
2480                 [R600_RING_TYPE_UVD_INDEX] = {
2481                         .ib_execute = &r600_uvd_ib_execute,
2482                         .emit_fence = &r600_uvd_fence_emit,
2483                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2484                         .cs_parse = &radeon_uvd_cs_parse,
2485                         .ring_test = &r600_uvd_ring_test,
2486                         .ib_test = &r600_uvd_ib_test,
2487                         .is_lockup = &radeon_ring_test_lockup,
2488                         .get_rptr = &radeon_ring_generic_get_rptr,
2489                         .get_wptr = &radeon_ring_generic_get_wptr,
2490                         .set_wptr = &radeon_ring_generic_set_wptr,
2491                 }
2492         },
2493         .irq = {
2494                 .set = &cik_irq_set,
2495                 .process = &cik_irq_process,
2496         },
2497         .display = {
2498                 .bandwidth_update = &dce8_bandwidth_update,
2499                 .get_vblank_counter = &evergreen_get_vblank_counter,
2500                 .wait_for_vblank = &dce4_wait_for_vblank,
2501         },
2502         .copy = {
2503                 .blit = NULL,
2504                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2505                 .dma = &cik_copy_dma,
2506                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2507                 .copy = &cik_copy_dma,
2508                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2509         },
2510         .surface = {
2511                 .set_reg = r600_set_surface_reg,
2512                 .clear_reg = r600_clear_surface_reg,
2513         },
2514         .hpd = {
2515                 .init = &evergreen_hpd_init,
2516                 .fini = &evergreen_hpd_fini,
2517                 .sense = &evergreen_hpd_sense,
2518                 .set_polarity = &evergreen_hpd_set_polarity,
2519         },
2520         .pm = {
2521                 .misc = &evergreen_pm_misc,
2522                 .prepare = &evergreen_pm_prepare,
2523                 .finish = &evergreen_pm_finish,
2524                 .init_profile = &sumo_pm_init_profile,
2525                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2526                 .get_engine_clock = &radeon_atom_get_engine_clock,
2527                 .set_engine_clock = &radeon_atom_set_engine_clock,
2528                 .get_memory_clock = &radeon_atom_get_memory_clock,
2529                 .set_memory_clock = &radeon_atom_set_memory_clock,
2530                 .get_pcie_lanes = NULL,
2531                 .set_pcie_lanes = NULL,
2532                 .set_clock_gating = NULL,
2533                 .set_uvd_clocks = &cik_set_uvd_clocks,
2534         },
2535         .pflip = {
2536                 .pre_page_flip = &evergreen_pre_page_flip,
2537                 .page_flip = &evergreen_page_flip,
2538                 .post_page_flip = &evergreen_post_page_flip,
2539         },
2540 };
2541
2542 /**
2543  * radeon_asic_init - register asic specific callbacks
2544  *
2545  * @rdev: radeon device pointer
2546  *
2547  * Registers the appropriate asic specific callbacks for each
2548  * chip family.  Also sets other asics specific info like the number
2549  * of crtcs and the register aperture accessors (all asics).
2550  * Returns 0 for success.
2551  */
2552 int radeon_asic_init(struct radeon_device *rdev)
2553 {
2554         radeon_register_accessor_init(rdev);
2555
2556         /* set the number of crtcs */
2557         if (rdev->flags & RADEON_SINGLE_CRTC)
2558                 rdev->num_crtc = 1;
2559         else
2560                 rdev->num_crtc = 2;
2561
2562         rdev->has_uvd = false;
2563
2564         switch (rdev->family) {
2565         case CHIP_R100:
2566         case CHIP_RV100:
2567         case CHIP_RS100:
2568         case CHIP_RV200:
2569         case CHIP_RS200:
2570                 rdev->asic = &r100_asic;
2571                 break;
2572         case CHIP_R200:
2573         case CHIP_RV250:
2574         case CHIP_RS300:
2575         case CHIP_RV280:
2576                 rdev->asic = &r200_asic;
2577                 break;
2578         case CHIP_R300:
2579         case CHIP_R350:
2580         case CHIP_RV350:
2581         case CHIP_RV380:
2582                 if (rdev->flags & RADEON_IS_PCIE)
2583                         rdev->asic = &r300_asic_pcie;
2584                 else
2585                         rdev->asic = &r300_asic;
2586                 break;
2587         case CHIP_R420:
2588         case CHIP_R423:
2589         case CHIP_RV410:
2590                 rdev->asic = &r420_asic;
2591                 /* handle macs */
2592                 if (rdev->bios == NULL) {
2593                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2594                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2595                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2596                         rdev->asic->pm.set_memory_clock = NULL;
2597                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2598                 }
2599                 break;
2600         case CHIP_RS400:
2601         case CHIP_RS480:
2602                 rdev->asic = &rs400_asic;
2603                 break;
2604         case CHIP_RS600:
2605                 rdev->asic = &rs600_asic;
2606                 break;
2607         case CHIP_RS690:
2608         case CHIP_RS740:
2609                 rdev->asic = &rs690_asic;
2610                 break;
2611         case CHIP_RV515:
2612                 rdev->asic = &rv515_asic;
2613                 break;
2614         case CHIP_R520:
2615         case CHIP_RV530:
2616         case CHIP_RV560:
2617         case CHIP_RV570:
2618         case CHIP_R580:
2619                 rdev->asic = &r520_asic;
2620                 break;
2621         case CHIP_R600:
2622                 rdev->asic = &r600_asic;
2623                 break;
2624         case CHIP_RV610:
2625         case CHIP_RV630:
2626         case CHIP_RV620:
2627         case CHIP_RV635:
2628         case CHIP_RV670:
2629                 rdev->asic = &rv6xx_asic;
2630                 rdev->has_uvd = true;
2631                 break;
2632         case CHIP_RS780:
2633         case CHIP_RS880:
2634                 rdev->asic = &rs780_asic;
2635                 rdev->has_uvd = true;
2636                 break;
2637         case CHIP_RV770:
2638         case CHIP_RV730:
2639         case CHIP_RV710:
2640         case CHIP_RV740:
2641                 rdev->asic = &rv770_asic;
2642                 rdev->has_uvd = true;
2643                 break;
2644         case CHIP_CEDAR:
2645         case CHIP_REDWOOD:
2646         case CHIP_JUNIPER:
2647         case CHIP_CYPRESS:
2648         case CHIP_HEMLOCK:
2649                 /* set num crtcs */
2650                 if (rdev->family == CHIP_CEDAR)
2651                         rdev->num_crtc = 4;
2652                 else
2653                         rdev->num_crtc = 6;
2654                 rdev->asic = &evergreen_asic;
2655                 rdev->has_uvd = true;
2656                 break;
2657         case CHIP_PALM:
2658         case CHIP_SUMO:
2659         case CHIP_SUMO2:
2660                 rdev->asic = &sumo_asic;
2661                 rdev->has_uvd = true;
2662                 break;
2663         case CHIP_BARTS:
2664         case CHIP_TURKS:
2665         case CHIP_CAICOS:
2666                 /* set num crtcs */
2667                 if (rdev->family == CHIP_CAICOS)
2668                         rdev->num_crtc = 4;
2669                 else
2670                         rdev->num_crtc = 6;
2671                 rdev->asic = &btc_asic;
2672                 rdev->has_uvd = true;
2673                 break;
2674         case CHIP_CAYMAN:
2675                 rdev->asic = &cayman_asic;
2676                 /* set num crtcs */
2677                 rdev->num_crtc = 6;
2678                 rdev->has_uvd = true;
2679                 break;
2680         case CHIP_ARUBA:
2681                 rdev->asic = &trinity_asic;
2682                 /* set num crtcs */
2683                 rdev->num_crtc = 4;
2684                 rdev->has_uvd = true;
2685                 break;
2686         case CHIP_TAHITI:
2687         case CHIP_PITCAIRN:
2688         case CHIP_VERDE:
2689         case CHIP_OLAND:
2690         case CHIP_HAINAN:
2691                 rdev->asic = &si_asic;
2692                 /* set num crtcs */
2693                 if (rdev->family == CHIP_HAINAN)
2694                         rdev->num_crtc = 0;
2695                 else if (rdev->family == CHIP_OLAND)
2696                         rdev->num_crtc = 2;
2697                 else
2698                         rdev->num_crtc = 6;
2699                 if (rdev->family == CHIP_HAINAN)
2700                         rdev->has_uvd = false;
2701                 else
2702                         rdev->has_uvd = true;
2703                 break;
2704         case CHIP_BONAIRE:
2705                 rdev->asic = &ci_asic;
2706                 rdev->num_crtc = 6;
2707                 break;
2708         case CHIP_KAVERI:
2709         case CHIP_KABINI:
2710                 rdev->asic = &kv_asic;
2711                 /* set num crtcs */
2712                 if (rdev->family == CHIP_KAVERI)
2713                         rdev->num_crtc = 4;
2714                 else
2715                         rdev->num_crtc = 2;
2716                 break;
2717         default:
2718                 /* FIXME: not supported yet */
2719                 return -EINVAL;
2720         }
2721
2722         if (rdev->flags & RADEON_IS_IGP) {
2723                 rdev->asic->pm.get_memory_clock = NULL;
2724                 rdev->asic->pm.set_memory_clock = NULL;
2725         }
2726
2727         return 0;
2728 }
2729