2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <drm/i915_drm.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_dp_helper.h>
37 * _wait_for - magic (register) wait macro
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
44 #define _wait_for(COND, MS, W) ({ \
45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
48 if (time_after(jiffies, timeout__)) { \
53 if (W && drm_can_sleep()) { \
62 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
63 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
67 #define KHz(x) (1000*x)
68 #define MHz(x) KHz(1000*x)
71 * Display related stuff
74 /* store information about an Ixxx DVO */
75 /* The i830->i865 use multiple DVOs with multiple i2cs */
76 /* the i915, i945 have a single sDVO i2c bus - which is different */
78 /* maximum connectors per crtcs in the mode set */
79 #define INTELFB_CONN_LIMIT 4
81 #define INTEL_I2C_BUS_DVO 1
82 #define INTEL_I2C_BUS_SDVO 2
84 /* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86 #define INTEL_OUTPUT_UNUSED 0
87 #define INTEL_OUTPUT_ANALOG 1
88 #define INTEL_OUTPUT_DVO 2
89 #define INTEL_OUTPUT_SDVO 3
90 #define INTEL_OUTPUT_LVDS 4
91 #define INTEL_OUTPUT_TVOUT 5
92 #define INTEL_OUTPUT_HDMI 6
93 #define INTEL_OUTPUT_DISPLAYPORT 7
94 #define INTEL_OUTPUT_EDP 8
95 #define INTEL_OUTPUT_UNKNOWN 9
97 #define INTEL_DVO_CHIP_NONE 0
98 #define INTEL_DVO_CHIP_LVDS 1
99 #define INTEL_DVO_CHIP_TMDS 2
100 #define INTEL_DVO_CHIP_TVOUT 4
102 struct intel_framebuffer {
103 struct drm_framebuffer base;
104 struct drm_i915_gem_object *obj;
108 struct drm_fb_helper helper;
109 struct intel_framebuffer ifb;
110 struct list_head fbdev_list;
111 struct drm_display_mode *our_mode;
114 struct intel_encoder {
115 struct drm_encoder base;
117 * The new crtc this encoder will be driven from. Only differs from
118 * base->crtc while a modeset is in progress.
120 struct intel_crtc *new_crtc;
125 * Intel hw has only one MUX where encoders could be clone, hence a
126 * simple flag is enough to compute the possible_clones mask.
129 bool connectors_active;
130 void (*hot_plug)(struct intel_encoder *);
131 bool (*compute_config)(struct intel_encoder *,
132 struct intel_crtc_config *);
133 void (*pre_pll_enable)(struct intel_encoder *);
134 void (*pre_enable)(struct intel_encoder *);
135 void (*enable)(struct intel_encoder *);
136 void (*mode_set)(struct intel_encoder *intel_encoder);
137 void (*disable)(struct intel_encoder *);
138 void (*post_disable)(struct intel_encoder *);
139 /* Read out the current hw state of this connector, returning true if
140 * the encoder is active. If the encoder is enabled it also set the pipe
141 * it is connected to in the pipe parameter. */
142 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
144 enum hpd_pin hpd_pin;
148 struct drm_display_mode *fixed_mode;
152 struct intel_connector {
153 struct drm_connector base;
155 * The fixed encoder this connector is connected to.
157 struct intel_encoder *encoder;
160 * The new encoder this connector will be driven. Only differs from
161 * encoder while a modeset is in progress.
163 struct intel_encoder *new_encoder;
165 /* Reads out the current hw, returning true if the connector is enabled
166 * and active (i.e. dpms ON state). */
167 bool (*get_hw_state)(struct intel_connector *);
169 /* Panel info for eDP and LVDS */
170 struct intel_panel panel;
172 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
175 /* since POLL and HPD connectors may use the same HPD line keep the native
176 state of connector->polled in case hotplug storm detection changes it */
180 typedef struct dpll {
192 struct intel_crtc_config {
193 struct drm_display_mode requested_mode;
194 struct drm_display_mode adjusted_mode;
195 /* This flag must be set by the encoder's compute_config callback if it
196 * changes the crtc timings in the mode to prevent the crtc fixup from
197 * overwriting them. Currently only lvds needs that. */
199 /* Whether to set up the PCH/FDI. Note that we never allow sharing
200 * between pch encoders and cpu encoders. */
201 bool has_pch_encoder;
203 /* CPU Transcoder for the pipe. Currently this can only differ from the
204 * pipe on Haswell (where we have a special eDP transcoder). */
205 enum transcoder cpu_transcoder;
208 * Use reduced/limited/broadcast rbg range, compressing from the full
209 * range fed into the crtcs.
211 bool limited_color_range;
213 /* DP has a bunch of special case unfortunately, so mark the pipe
218 /* Controls for the clock computation, to override various stages. */
221 /* Settings for the intel dpll used on pretty much everything but
226 struct intel_link_m_n dp_m_n;
228 * This is currently used by DP and HDMI encoders since those can have a
229 * target pixel clock != the port link clock (which is currently stored
230 * in adjusted_mode->clock).
232 int pixel_target_clock;
233 /* Used by SDVO (and if we ever fix it, HDMI). */
234 unsigned pixel_multiplier;
238 struct drm_crtc base;
241 u8 lut_r[256], lut_g[256], lut_b[256];
243 * Whether the crtc and the connected output pipeline is active. Implies
244 * that crtc->enabled is set, i.e. the current mode configuration has
245 * some outputs connected to this crtc.
249 bool primary_disabled; /* is the crtc obscured by a plane? */
251 struct intel_overlay *overlay;
252 struct intel_unpin_work *unpin_work;
255 atomic_t unpin_work_count;
257 /* Display surface base address adjustement for pageflips. Note that on
258 * gen4+ this only adjusts up to a tile, offsets within a tile are
259 * handled in the hw itself (with the TILEOFF register). */
260 unsigned long dspaddr_offset;
262 struct drm_i915_gem_object *cursor_bo;
263 uint32_t cursor_addr;
264 int16_t cursor_x, cursor_y;
265 int16_t cursor_width, cursor_height;
268 struct intel_crtc_config config;
270 /* We can share PLLs across outputs if the timings match */
271 struct intel_pch_pll *pch_pll;
272 uint32_t ddi_pll_sel;
274 /* reset counter value when the last flip was submitted */
275 unsigned int reset_counter;
277 /* Access to these should be protected by dev_priv->irq_lock. */
278 bool cpu_fifo_underrun_disabled;
279 bool pch_fifo_underrun_disabled;
283 struct drm_plane base;
286 struct drm_i915_gem_object *obj;
289 u32 lut_r[1024], lut_g[1024], lut_b[1024];
291 unsigned int crtc_w, crtc_h;
292 uint32_t src_x, src_y;
293 uint32_t src_w, src_h;
294 void (*update_plane)(struct drm_plane *plane,
295 struct drm_framebuffer *fb,
296 struct drm_i915_gem_object *obj,
297 int crtc_x, int crtc_y,
298 unsigned int crtc_w, unsigned int crtc_h,
299 uint32_t x, uint32_t y,
300 uint32_t src_w, uint32_t src_h);
301 void (*disable_plane)(struct drm_plane *plane);
302 int (*update_colorkey)(struct drm_plane *plane,
303 struct drm_intel_sprite_colorkey *key);
304 void (*get_colorkey)(struct drm_plane *plane,
305 struct drm_intel_sprite_colorkey *key);
308 struct intel_watermark_params {
309 unsigned long fifo_size;
310 unsigned long max_wm;
311 unsigned long default_wm;
312 unsigned long guard_size;
313 unsigned long cacheline_size;
316 struct cxsr_latency {
319 unsigned long fsb_freq;
320 unsigned long mem_freq;
321 unsigned long display_sr;
322 unsigned long display_hpll_disable;
323 unsigned long cursor_sr;
324 unsigned long cursor_hpll_disable;
327 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
328 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
329 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
330 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
331 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
333 #define DIP_HEADER_SIZE 5
335 #define DIP_TYPE_AVI 0x82
336 #define DIP_VERSION_AVI 0x2
337 #define DIP_LEN_AVI 13
338 #define DIP_AVI_PR_1 0
339 #define DIP_AVI_PR_2 1
340 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
341 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
342 #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
344 #define DIP_TYPE_SPD 0x83
345 #define DIP_VERSION_SPD 0x1
346 #define DIP_LEN_SPD 25
347 #define DIP_SPD_UNKNOWN 0
348 #define DIP_SPD_DSTB 0x1
349 #define DIP_SPD_DVDP 0x2
350 #define DIP_SPD_DVHS 0x3
351 #define DIP_SPD_HDDVR 0x4
352 #define DIP_SPD_DVC 0x5
353 #define DIP_SPD_DSC 0x6
354 #define DIP_SPD_VCD 0x7
355 #define DIP_SPD_GAME 0x8
356 #define DIP_SPD_PC 0x9
357 #define DIP_SPD_BD 0xa
358 #define DIP_SPD_SCD 0xb
360 struct dip_infoframe {
361 uint8_t type; /* HB0 */
362 uint8_t ver; /* HB1 */
363 uint8_t len; /* HB2 - body len, not including checksum */
364 uint8_t ecc; /* Header ECC */
365 uint8_t checksum; /* PB0 */
368 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
370 /* PB2 - C 7:6, M 5:4, R 3:0 */
372 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
376 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
379 uint16_t top_bar_end;
380 uint16_t bottom_bar_start;
381 uint16_t left_bar_end;
382 uint16_t right_bar_start;
383 } __attribute__ ((packed)) avi;
388 } __attribute__ ((packed)) spd;
390 } __attribute__ ((packed)) body;
391 } __attribute__((packed));
396 uint32_t color_range;
397 bool color_range_auto;
400 enum hdmi_force_audio force_audio;
401 bool rgb_quant_range_selectable;
402 void (*write_infoframe)(struct drm_encoder *encoder,
403 struct dip_infoframe *frame);
404 void (*set_infoframes)(struct drm_encoder *encoder,
405 struct drm_display_mode *adjusted_mode);
408 #define DP_MAX_DOWNSTREAM_PORTS 0x10
409 #define DP_LINK_CONFIGURATION_SIZE 9
413 uint32_t aux_ch_ctl_reg;
415 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
417 enum hdmi_force_audio force_audio;
418 uint32_t color_range;
419 bool color_range_auto;
422 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
423 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
424 struct i2c_adapter adapter;
425 struct i2c_algo_dp_aux_data algo;
427 uint8_t train_set[4];
428 int panel_power_up_delay;
429 int panel_power_down_delay;
430 int panel_power_cycle_delay;
431 int backlight_on_delay;
432 int backlight_off_delay;
433 struct delayed_work panel_vdd_work;
435 struct intel_connector *attached_connector;
438 struct intel_digital_port {
439 struct intel_encoder base;
443 struct intel_hdmi hdmi;
447 vlv_dport_to_channel(struct intel_digital_port *dport)
449 switch (dport->port) {
459 static inline struct drm_crtc *
460 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
462 struct drm_i915_private *dev_priv = dev->dev_private;
463 return dev_priv->pipe_to_crtc_mapping[pipe];
466 static inline struct drm_crtc *
467 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
469 struct drm_i915_private *dev_priv = dev->dev_private;
470 return dev_priv->plane_to_crtc_mapping[plane];
473 struct intel_unpin_work {
474 struct work_struct work;
475 struct drm_crtc *crtc;
476 struct drm_i915_gem_object *old_fb_obj;
477 struct drm_i915_gem_object *pending_flip_obj;
478 struct drm_pending_vblank_event *event;
480 #define INTEL_FLIP_INACTIVE 0
481 #define INTEL_FLIP_PENDING 1
482 #define INTEL_FLIP_COMPLETE 2
483 bool enable_stall_check;
486 struct intel_fbc_work {
487 struct delayed_work work;
488 struct drm_crtc *crtc;
489 struct drm_framebuffer *fb;
493 int intel_pch_rawclk(struct drm_device *dev);
495 int intel_connector_update_modes(struct drm_connector *connector,
497 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
499 extern void intel_attach_force_audio_property(struct drm_connector *connector);
500 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
502 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
503 extern void intel_crt_init(struct drm_device *dev);
504 extern void intel_hdmi_init(struct drm_device *dev,
505 int hdmi_reg, enum port port);
506 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
507 struct intel_connector *intel_connector);
508 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
509 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
510 struct intel_crtc_config *pipe_config);
511 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
512 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
514 extern void intel_dvo_init(struct drm_device *dev);
515 extern void intel_tv_init(struct drm_device *dev);
516 extern void intel_mark_busy(struct drm_device *dev);
517 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
518 extern void intel_mark_idle(struct drm_device *dev);
519 extern bool intel_lvds_init(struct drm_device *dev);
520 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
521 extern void intel_dp_init(struct drm_device *dev, int output_reg,
523 extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
524 struct intel_connector *intel_connector);
525 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
526 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
527 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
528 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
529 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
530 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
531 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
532 struct intel_crtc_config *pipe_config);
533 extern bool intel_dpd_is_edp(struct drm_device *dev);
534 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
535 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
536 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
537 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
538 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
539 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
540 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
541 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
542 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
546 extern int intel_panel_init(struct intel_panel *panel,
547 struct drm_display_mode *fixed_mode);
548 extern void intel_panel_fini(struct intel_panel *panel);
550 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
551 struct drm_display_mode *adjusted_mode);
552 extern void intel_pch_panel_fitting(struct drm_device *dev,
554 const struct drm_display_mode *mode,
555 struct drm_display_mode *adjusted_mode);
556 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
557 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
558 extern int intel_panel_setup_backlight(struct drm_connector *connector);
559 extern void intel_panel_enable_backlight(struct drm_device *dev,
561 extern void intel_panel_disable_backlight(struct drm_device *dev);
562 extern void intel_panel_destroy_backlight(struct drm_device *dev);
563 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
565 struct intel_set_config {
566 struct drm_encoder **save_connector_encoders;
567 struct drm_crtc **save_encoder_crtcs;
573 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
574 int x, int y, struct drm_framebuffer *old_fb);
575 extern void intel_modeset_disable(struct drm_device *dev);
576 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
577 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
578 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
579 extern void intel_encoder_destroy(struct drm_encoder *encoder);
580 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
581 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
582 extern void intel_connector_dpms(struct drm_connector *, int mode);
583 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
584 extern void intel_modeset_check_state(struct drm_device *dev);
585 extern void intel_plane_restore(struct drm_plane *plane);
588 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
590 return to_intel_connector(connector)->encoder;
593 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
595 struct intel_digital_port *intel_dig_port =
596 container_of(encoder, struct intel_digital_port, base.base);
597 return &intel_dig_port->dp;
600 static inline struct intel_digital_port *
601 enc_to_dig_port(struct drm_encoder *encoder)
603 return container_of(encoder, struct intel_digital_port, base.base);
606 static inline struct intel_digital_port *
607 dp_to_dig_port(struct intel_dp *intel_dp)
609 return container_of(intel_dp, struct intel_digital_port, dp);
612 static inline struct intel_digital_port *
613 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
615 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
618 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
619 struct intel_digital_port *port);
621 extern void intel_connector_attach_encoder(struct intel_connector *connector,
622 struct intel_encoder *encoder);
623 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
625 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
626 struct drm_crtc *crtc);
627 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
628 struct drm_file *file_priv);
629 extern enum transcoder
630 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
632 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
633 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
634 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
635 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
637 struct intel_load_detect_pipe {
638 struct drm_framebuffer *release_fb;
639 bool load_detect_temp;
642 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
643 struct drm_display_mode *mode,
644 struct intel_load_detect_pipe *old);
645 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
646 struct intel_load_detect_pipe *old);
648 extern void intelfb_restore(void);
649 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
650 u16 blue, int regno);
651 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
652 u16 *blue, int regno);
653 extern void intel_enable_clock_gating(struct drm_device *dev);
655 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
656 struct drm_i915_gem_object *obj,
657 struct intel_ring_buffer *pipelined);
658 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
660 extern int intel_framebuffer_init(struct drm_device *dev,
661 struct intel_framebuffer *ifb,
662 struct drm_mode_fb_cmd2 *mode_cmd,
663 struct drm_i915_gem_object *obj);
664 extern int intel_fbdev_init(struct drm_device *dev);
665 extern void intel_fbdev_initial_config(struct drm_device *dev);
666 extern void intel_fbdev_fini(struct drm_device *dev);
667 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
668 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
669 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
670 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
672 extern void intel_setup_overlay(struct drm_device *dev);
673 extern void intel_cleanup_overlay(struct drm_device *dev);
674 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
675 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
676 struct drm_file *file_priv);
677 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
678 struct drm_file *file_priv);
680 extern void intel_fb_output_poll_changed(struct drm_device *dev);
681 extern void intel_fb_restore_mode(struct drm_device *dev);
683 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
685 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
686 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
688 extern void intel_init_clock_gating(struct drm_device *dev);
689 extern void intel_write_eld(struct drm_encoder *encoder,
690 struct drm_display_mode *mode);
691 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
692 extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
693 struct intel_link_m_n *m_n);
694 extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
695 struct intel_link_m_n *m_n);
696 extern void intel_prepare_ddi(struct drm_device *dev);
697 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
698 extern void intel_ddi_init(struct drm_device *dev, enum port port);
700 /* For use by IVB LP watermark workaround in intel_sprite.c */
701 extern void intel_update_watermarks(struct drm_device *dev);
702 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
703 uint32_t sprite_width,
705 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
706 struct drm_display_mode *mode);
708 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
709 unsigned int tiling_mode,
713 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
714 struct drm_file *file_priv);
715 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
716 struct drm_file *file_priv);
718 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
719 extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
722 /* Power-related functions, located in intel_pm.c */
723 extern void intel_init_pm(struct drm_device *dev);
725 extern bool intel_fbc_enabled(struct drm_device *dev);
726 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
727 extern void intel_update_fbc(struct drm_device *dev);
729 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
730 extern void intel_gpu_ips_teardown(void);
732 extern bool intel_using_power_well(struct drm_device *dev);
733 extern void intel_init_power_well(struct drm_device *dev);
734 extern void intel_set_power_well(struct drm_device *dev, bool enable);
735 extern void intel_enable_gt_powersave(struct drm_device *dev);
736 extern void intel_disable_gt_powersave(struct drm_device *dev);
737 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
738 extern void ironlake_teardown_rc6(struct drm_device *dev);
740 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
742 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
743 extern void intel_ddi_pll_init(struct drm_device *dev);
744 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
745 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
746 enum transcoder cpu_transcoder);
747 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
748 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
749 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
750 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
751 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
752 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
753 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
755 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
756 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
758 extern void intel_display_handle_reset(struct drm_device *dev);
759 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
762 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
763 enum transcoder pch_transcoder,
766 #endif /* __INTEL_DRV_H__ */