2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
85 * Returns true on success, false on failure.
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
98 intel_pch_rawclk(struct drm_device *dev)
100 struct drm_i915_private *dev_priv = dev->dev_private;
102 WARN_ON(!HAS_PCH_SPLIT(dev));
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
130 static inline u32 /* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device *dev)
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
140 static const intel_limit_t intel_limits_i8xx_dvo = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
151 .find_pll = intel_find_best_PLL,
154 static const intel_limit_t intel_limits_i8xx_lvds = {
155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
168 static const intel_limit_t intel_limits_i9xx_sdvo = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
179 .find_pll = intel_find_best_PLL,
182 static const intel_limit_t intel_limits_i9xx_lvds = {
183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
193 .find_pll = intel_find_best_PLL,
197 static const intel_limit_t intel_limits_g4x_sdvo = {
198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
210 .find_pll = intel_g4x_find_best_PLL,
213 static const intel_limit_t intel_limits_g4x_hdmi = {
214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
224 .find_pll = intel_g4x_find_best_PLL,
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
239 .find_pll = intel_g4x_find_best_PLL,
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
254 .find_pll = intel_g4x_find_best_PLL,
257 static const intel_limit_t intel_limits_g4x_display_port = {
258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 10, .p2_fast = 10 },
268 .find_pll = intel_find_pll_g4x_dp,
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_find_best_PLL,
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_find_best_PLL,
301 /* Ironlake / Sandybridge
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
306 static const intel_limit_t intel_limits_ironlake_dac = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
317 .find_pll = intel_g4x_find_best_PLL,
320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
360 .find_pll = intel_g4x_find_best_PLL,
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 .find_pll = intel_g4x_find_best_PLL,
377 static const intel_limit_t intel_limits_ironlake_display_port = {
378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
387 .p2_slow = 10, .p2_fast = 10 },
388 .find_pll = intel_find_pll_ironlake_dp,
391 static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 1, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
405 static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
419 static const intel_limit_t intel_limits_vlv_dp = {
420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
422 .n = { .min = 1, .max = 7 },
423 .m = { .min = 22, .max = 450 },
424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 1, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
450 return I915_READ(DPIO_DATA);
453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
471 static void vlv_init_dpio(struct drm_device *dev)
473 struct drm_i915_private *dev_priv = dev->dev_private;
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
485 struct drm_device *dev = crtc->dev;
486 const intel_limit_t *limit;
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
489 if (intel_is_dual_link_lvds(dev)) {
490 if (refclk == 100000)
491 limit = &intel_limits_ironlake_dual_lvds_100m;
493 limit = &intel_limits_ironlake_dual_lvds;
495 if (refclk == 100000)
496 limit = &intel_limits_ironlake_single_lvds_100m;
498 limit = &intel_limits_ironlake_single_lvds;
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
502 limit = &intel_limits_ironlake_display_port;
504 limit = &intel_limits_ironlake_dac;
509 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
511 struct drm_device *dev = crtc->dev;
512 const intel_limit_t *limit;
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
515 if (intel_is_dual_link_lvds(dev))
516 limit = &intel_limits_g4x_dual_channel_lvds;
518 limit = &intel_limits_g4x_single_channel_lvds;
519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
521 limit = &intel_limits_g4x_hdmi;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523 limit = &intel_limits_g4x_sdvo;
524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525 limit = &intel_limits_g4x_display_port;
526 } else /* The option is for other outputs */
527 limit = &intel_limits_i9xx_sdvo;
532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
537 if (HAS_PCH_SPLIT(dev))
538 limit = intel_ironlake_limit(crtc, refclk);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc);
541 } else if (IS_PINEVIEW(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_pineview_lvds;
545 limit = &intel_limits_pineview_sdvo;
546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
552 limit = &intel_limits_vlv_dp;
553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
557 limit = &intel_limits_i9xx_sdvo;
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
560 limit = &intel_limits_i8xx_lvds;
562 limit = &intel_limits_i8xx_dvo;
567 /* m1 is reserved as 0 in Pineview, n is a ring counter */
568 static void pineview_clock(int refclk, intel_clock_t *clock)
570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
576 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
589 * Returns whether any output on the specified pipe is of the specified type
591 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
593 struct drm_device *dev = crtc->dev;
594 struct intel_encoder *encoder;
596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
603 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
609 static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
614 INTELPllInvalid("p1 out of range\n");
615 if (clock->p < limit->p.min || limit->p.max < clock->p)
616 INTELPllInvalid("p out of range\n");
617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
618 INTELPllInvalid("m2 out of range\n");
619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
620 INTELPllInvalid("m1 out of range\n");
621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
622 INTELPllInvalid("m1 <= m2\n");
623 if (clock->m < limit->m.min || limit->m.max < clock->m)
624 INTELPllInvalid("m out of range\n");
625 if (clock->n < limit->n.min || limit->n.max < clock->n)
626 INTELPllInvalid("n out of range\n");
627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
633 INTELPllInvalid("dot out of range\n");
639 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
644 struct drm_device *dev = crtc->dev;
648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
657 clock.p2 = limit->p2.p2_slow;
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
662 clock.p2 = limit->p2.p2_fast;
665 memset(best_clock, 0, sizeof(*best_clock));
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
680 intel_clock(dev, refclk, &clock);
681 if (!intel_PLL_is_valid(dev, limit,
685 clock.p != match_clock->p)
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
698 return (err != target);
702 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
706 struct drm_device *dev = crtc->dev;
710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (HAS_PCH_SPLIT(dev))
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
724 clock.p2 = limit->p2.p2_slow;
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
729 clock.p2 = limit->p2.p2_fast;
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736 /* based on hardware requirement, prefere larger m1,m2 */
737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
745 intel_clock(dev, refclk, &clock);
746 if (!intel_PLL_is_valid(dev, limit,
750 clock.p != match_clock->p)
753 this_err = abs(clock.dot - target);
754 if (this_err < err_most) {
768 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
772 struct drm_device *dev = crtc->dev;
775 if (target < 200000) {
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
793 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
795 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
800 if (target < 200000) {
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
821 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
832 dotclk = target * 1000;
835 fastclk = dotclk / (2*100);
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
863 if (absppm < bestppm - 10) {
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
889 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
895 return intel_crtc->config.cpu_transcoder;
898 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
903 frame = I915_READ(frame_reg);
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
910 * intel_wait_for_vblank - wait for vblank on a given pipe
912 * @pipe: pipe to wait for
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
917 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 int pipestat_reg = PIPESTAT(pipe);
922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
943 /* Wait for vblank interrupt bit to set */
944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
947 DRM_DEBUG_KMS("vblank wait timed out\n");
951 * intel_wait_for_pipe_off - wait for pipe to turn off
953 * @pipe: pipe to wait for
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
960 * wait for the pipe register state bit to turn off
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
967 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 if (INTEL_INFO(dev)->gen >= 4) {
974 int reg = PIPECONF(cpu_transcoder);
976 /* Wait for the Pipe State to go off */
977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
979 WARN(1, "pipe_off wait timed out\n");
981 u32 last_line, line_mask;
982 int reg = PIPEDSL(pipe);
983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
986 line_mask = DSL_LINEMASK_GEN2;
988 line_mask = DSL_LINEMASK_GEN3;
990 /* Wait for the display line to settle */
992 last_line = I915_READ(reg) & line_mask;
994 } while (((I915_READ(reg) & line_mask) != last_line) &&
995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
997 WARN(1, "pipe_off wait timed out\n");
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1006 * Returns true if @port is connected, false otherwise.
1008 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1016 bit = SDE_PORTB_HOTPLUG;
1019 bit = SDE_PORTC_HOTPLUG;
1022 bit = SDE_PORTD_HOTPLUG;
1028 switch(port->port) {
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1043 return I915_READ(SDEISR) & bit;
1046 static const char *state_string(bool enabled)
1048 return enabled ? "on" : "off";
1051 /* Only for pre-ILK configs */
1052 static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1066 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1070 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %c: %08x\n",
1101 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %c: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 pipe_name(crtc->pipe),
1112 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1115 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1138 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1155 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1169 if (HAS_DDI(dev_priv->dev))
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191 int pp_reg, lvds_reg;
1193 enum pipe panel_pipe = PIPE_A;
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1200 pp_reg = PP_CONTROL;
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
1217 void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1230 if (!intel_using_power_well(dev_priv->dev) &&
1231 cpu_transcoder != TRANSCODER_EDP) {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1269 /* Planes are fixed to pipes on ILK+ */
1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
1291 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1306 sprite_name(pipe, i), pipe_name(pipe));
1310 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1326 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1341 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
1344 if ((val & DP_PORT_EN) == 0)
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1359 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1362 if ((val & SDVO_ENABLE) == 0)
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1375 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1378 if ((val & LVDS_PORT_EN) == 0)
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1391 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1406 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, int reg, u32 port_sel)
1409 u32 val = I915_READ(reg);
1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1412 reg, pipe_name(pipe));
1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
1416 "IBX PCH dp port still using transcoder B\n");
1419 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1422 u32 val = I915_READ(reg);
1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1425 reg, pipe_name(pipe));
1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1428 && (val & SDVO_PIPE_B_SELECT),
1429 "IBX PCH hdmi port still using transcoder B\n");
1432 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1443 val = I915_READ(reg);
1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
1449 val = I915_READ(reg);
1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1468 * Note! This is for pre-ILK only.
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1472 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1477 assert_pipe_disabled(dev_priv, pipe);
1479 /* No really, not for ILK+ */
1480 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1482 /* PLL is protected by panel, make sure we can write it */
1483 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1484 assert_panel_unlocked(dev_priv, pipe);
1487 val = I915_READ(reg);
1488 val |= DPLL_VCO_ENABLE;
1490 /* We do this three times for luck */
1491 I915_WRITE(reg, val);
1493 udelay(150); /* wait for warmup */
1494 I915_WRITE(reg, val);
1496 udelay(150); /* wait for warmup */
1497 I915_WRITE(reg, val);
1499 udelay(150); /* wait for warmup */
1503 * intel_disable_pll - disable a PLL
1504 * @dev_priv: i915 private structure
1505 * @pipe: pipe PLL to disable
1507 * Disable the PLL for @pipe, making sure the pipe is off first.
1509 * Note! This is for pre-ILK only.
1511 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1516 /* Don't disable pipe A or pipe A PLLs if needed */
1517 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1520 /* Make sure the pipe isn't still relying on us */
1521 assert_pipe_disabled(dev_priv, pipe);
1524 val = I915_READ(reg);
1525 val &= ~DPLL_VCO_ENABLE;
1526 I915_WRITE(reg, val);
1532 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1533 enum intel_sbi_destination destination)
1537 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1539 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1541 DRM_ERROR("timeout waiting for SBI to become ready\n");
1545 I915_WRITE(SBI_ADDR, (reg << 16));
1546 I915_WRITE(SBI_DATA, value);
1548 if (destination == SBI_ICLK)
1549 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1551 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1552 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1554 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1556 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1562 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1563 enum intel_sbi_destination destination)
1566 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1568 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1570 DRM_ERROR("timeout waiting for SBI to become ready\n");
1574 I915_WRITE(SBI_ADDR, (reg << 16));
1576 if (destination == SBI_ICLK)
1577 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1579 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1580 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1582 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1584 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1588 return I915_READ(SBI_DATA);
1592 * ironlake_enable_pch_pll - enable PCH PLL
1593 * @dev_priv: i915 private structure
1594 * @pipe: pipe PLL to enable
1596 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1597 * drives the transcoder clock.
1599 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1601 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1602 struct intel_pch_pll *pll;
1606 /* PCH PLLs only available on ILK, SNB and IVB */
1607 BUG_ON(dev_priv->info->gen < 5);
1608 pll = intel_crtc->pch_pll;
1612 if (WARN_ON(pll->refcount == 0))
1615 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1616 pll->pll_reg, pll->active, pll->on,
1617 intel_crtc->base.base.id);
1619 /* PCH refclock must be enabled first */
1620 assert_pch_refclk_enabled(dev_priv);
1622 if (pll->active++ && pll->on) {
1623 assert_pch_pll_enabled(dev_priv, pll, NULL);
1627 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1630 val = I915_READ(reg);
1631 val |= DPLL_VCO_ENABLE;
1632 I915_WRITE(reg, val);
1639 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1641 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1642 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1646 /* PCH only available on ILK+ */
1647 BUG_ON(dev_priv->info->gen < 5);
1651 if (WARN_ON(pll->refcount == 0))
1654 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1655 pll->pll_reg, pll->active, pll->on,
1656 intel_crtc->base.base.id);
1658 if (WARN_ON(pll->active == 0)) {
1659 assert_pch_pll_disabled(dev_priv, pll, NULL);
1663 if (--pll->active) {
1664 assert_pch_pll_enabled(dev_priv, pll, NULL);
1668 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1670 /* Make sure transcoder isn't still depending on us */
1671 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1674 val = I915_READ(reg);
1675 val &= ~DPLL_VCO_ENABLE;
1676 I915_WRITE(reg, val);
1683 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1686 struct drm_device *dev = dev_priv->dev;
1687 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1688 uint32_t reg, val, pipeconf_val;
1690 /* PCH only available on ILK+ */
1691 BUG_ON(dev_priv->info->gen < 5);
1693 /* Make sure PCH DPLL is enabled */
1694 assert_pch_pll_enabled(dev_priv,
1695 to_intel_crtc(crtc)->pch_pll,
1696 to_intel_crtc(crtc));
1698 /* FDI must be feeding us bits for PCH ports */
1699 assert_fdi_tx_enabled(dev_priv, pipe);
1700 assert_fdi_rx_enabled(dev_priv, pipe);
1702 if (HAS_PCH_CPT(dev)) {
1703 /* Workaround: Set the timing override bit before enabling the
1704 * pch transcoder. */
1705 reg = TRANS_CHICKEN2(pipe);
1706 val = I915_READ(reg);
1707 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1708 I915_WRITE(reg, val);
1711 reg = TRANSCONF(pipe);
1712 val = I915_READ(reg);
1713 pipeconf_val = I915_READ(PIPECONF(pipe));
1715 if (HAS_PCH_IBX(dev_priv->dev)) {
1717 * make the BPC in transcoder be consistent with
1718 * that in pipeconf reg.
1720 val &= ~PIPECONF_BPC_MASK;
1721 val |= pipeconf_val & PIPECONF_BPC_MASK;
1724 val &= ~TRANS_INTERLACE_MASK;
1725 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1726 if (HAS_PCH_IBX(dev_priv->dev) &&
1727 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1728 val |= TRANS_LEGACY_INTERLACED_ILK;
1730 val |= TRANS_INTERLACED;
1732 val |= TRANS_PROGRESSIVE;
1734 I915_WRITE(reg, val | TRANS_ENABLE);
1735 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1736 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1739 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1740 enum transcoder cpu_transcoder)
1742 u32 val, pipeconf_val;
1744 /* PCH only available on ILK+ */
1745 BUG_ON(dev_priv->info->gen < 5);
1747 /* FDI must be feeding us bits for PCH ports */
1748 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1749 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1751 /* Workaround: set timing override bit. */
1752 val = I915_READ(_TRANSA_CHICKEN2);
1753 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1754 I915_WRITE(_TRANSA_CHICKEN2, val);
1757 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1759 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1760 PIPECONF_INTERLACED_ILK)
1761 val |= TRANS_INTERLACED;
1763 val |= TRANS_PROGRESSIVE;
1765 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1766 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1767 DRM_ERROR("Failed to enable PCH transcoder\n");
1770 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1773 struct drm_device *dev = dev_priv->dev;
1776 /* FDI relies on the transcoder */
1777 assert_fdi_tx_disabled(dev_priv, pipe);
1778 assert_fdi_rx_disabled(dev_priv, pipe);
1780 /* Ports must be off as well */
1781 assert_pch_ports_disabled(dev_priv, pipe);
1783 reg = TRANSCONF(pipe);
1784 val = I915_READ(reg);
1785 val &= ~TRANS_ENABLE;
1786 I915_WRITE(reg, val);
1787 /* wait for PCH transcoder off, transcoder state */
1788 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1789 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1791 if (!HAS_PCH_IBX(dev)) {
1792 /* Workaround: Clear the timing override chicken bit again. */
1793 reg = TRANS_CHICKEN2(pipe);
1794 val = I915_READ(reg);
1795 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1796 I915_WRITE(reg, val);
1800 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1804 val = I915_READ(_TRANSACONF);
1805 val &= ~TRANS_ENABLE;
1806 I915_WRITE(_TRANSACONF, val);
1807 /* wait for PCH transcoder off, transcoder state */
1808 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1809 DRM_ERROR("Failed to disable PCH transcoder\n");
1811 /* Workaround: clear timing override bit. */
1812 val = I915_READ(_TRANSA_CHICKEN2);
1813 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1814 I915_WRITE(_TRANSA_CHICKEN2, val);
1818 * intel_enable_pipe - enable a pipe, asserting requirements
1819 * @dev_priv: i915 private structure
1820 * @pipe: pipe to enable
1821 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1823 * Enable @pipe, making sure that various hardware specific requirements
1824 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1826 * @pipe should be %PIPE_A or %PIPE_B.
1828 * Will wait until the pipe is actually running (i.e. first vblank) before
1831 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1836 enum pipe pch_transcoder;
1840 assert_planes_disabled(dev_priv, pipe);
1841 assert_sprites_disabled(dev_priv, pipe);
1843 if (HAS_PCH_LPT(dev_priv->dev))
1844 pch_transcoder = TRANSCODER_A;
1846 pch_transcoder = pipe;
1849 * A pipe without a PLL won't actually be able to drive bits from
1850 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1853 if (!HAS_PCH_SPLIT(dev_priv->dev))
1854 assert_pll_enabled(dev_priv, pipe);
1857 /* if driving the PCH, we need FDI enabled */
1858 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1859 assert_fdi_tx_pll_enabled(dev_priv,
1860 (enum pipe) cpu_transcoder);
1862 /* FIXME: assert CPU port conditions for SNB+ */
1865 reg = PIPECONF(cpu_transcoder);
1866 val = I915_READ(reg);
1867 if (val & PIPECONF_ENABLE)
1870 I915_WRITE(reg, val | PIPECONF_ENABLE);
1871 intel_wait_for_vblank(dev_priv->dev, pipe);
1875 * intel_disable_pipe - disable a pipe, asserting requirements
1876 * @dev_priv: i915 private structure
1877 * @pipe: pipe to disable
1879 * Disable @pipe, making sure that various hardware specific requirements
1880 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1882 * @pipe should be %PIPE_A or %PIPE_B.
1884 * Will wait until the pipe has shut down before returning.
1886 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1889 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1895 * Make sure planes won't keep trying to pump pixels to us,
1896 * or we might hang the display.
1898 assert_planes_disabled(dev_priv, pipe);
1899 assert_sprites_disabled(dev_priv, pipe);
1901 /* Don't disable pipe A or pipe A PLLs if needed */
1902 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1905 reg = PIPECONF(cpu_transcoder);
1906 val = I915_READ(reg);
1907 if ((val & PIPECONF_ENABLE) == 0)
1910 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1911 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1915 * Plane regs are double buffered, going from enabled->disabled needs a
1916 * trigger in order to latch. The display address reg provides this.
1918 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1921 if (dev_priv->info->gen >= 4)
1922 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1924 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1928 * intel_enable_plane - enable a display plane on a given pipe
1929 * @dev_priv: i915 private structure
1930 * @plane: plane to enable
1931 * @pipe: pipe being fed
1933 * Enable @plane on @pipe, making sure that @pipe is running first.
1935 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1936 enum plane plane, enum pipe pipe)
1941 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1942 assert_pipe_enabled(dev_priv, pipe);
1944 reg = DSPCNTR(plane);
1945 val = I915_READ(reg);
1946 if (val & DISPLAY_PLANE_ENABLE)
1949 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1950 intel_flush_display_plane(dev_priv, plane);
1951 intel_wait_for_vblank(dev_priv->dev, pipe);
1955 * intel_disable_plane - disable a display plane
1956 * @dev_priv: i915 private structure
1957 * @plane: plane to disable
1958 * @pipe: pipe consuming the data
1960 * Disable @plane; should be an independent operation.
1962 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1963 enum plane plane, enum pipe pipe)
1968 reg = DSPCNTR(plane);
1969 val = I915_READ(reg);
1970 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1973 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1974 intel_flush_display_plane(dev_priv, plane);
1975 intel_wait_for_vblank(dev_priv->dev, pipe);
1978 static bool need_vtd_wa(struct drm_device *dev)
1980 #ifdef CONFIG_INTEL_IOMMU
1981 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1988 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1989 struct drm_i915_gem_object *obj,
1990 struct intel_ring_buffer *pipelined)
1992 struct drm_i915_private *dev_priv = dev->dev_private;
1996 switch (obj->tiling_mode) {
1997 case I915_TILING_NONE:
1998 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1999 alignment = 128 * 1024;
2000 else if (INTEL_INFO(dev)->gen >= 4)
2001 alignment = 4 * 1024;
2003 alignment = 64 * 1024;
2006 /* pin() will align the object as required by fence */
2010 /* Despite that we check this in framebuffer_init userspace can
2011 * screw us over and change the tiling after the fact. Only
2012 * pinned buffers can't change their tiling. */
2013 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2019 /* Note that the w/a also requires 64 PTE of padding following the
2020 * bo. We currently fill all unused PTE with the shadow page and so
2021 * we should always have valid PTE following the scanout preventing
2024 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2025 alignment = 256 * 1024;
2027 dev_priv->mm.interruptible = false;
2028 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2030 goto err_interruptible;
2032 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2033 * fence, whereas 965+ only requires a fence if using
2034 * framebuffer compression. For simplicity, we always install
2035 * a fence as the cost is not that onerous.
2037 ret = i915_gem_object_get_fence(obj);
2041 i915_gem_object_pin_fence(obj);
2043 dev_priv->mm.interruptible = true;
2047 i915_gem_object_unpin(obj);
2049 dev_priv->mm.interruptible = true;
2053 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2055 i915_gem_object_unpin_fence(obj);
2056 i915_gem_object_unpin(obj);
2059 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2060 * is assumed to be a power-of-two. */
2061 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2062 unsigned int tiling_mode,
2066 if (tiling_mode != I915_TILING_NONE) {
2067 unsigned int tile_rows, tiles;
2072 tiles = *x / (512/cpp);
2075 return tile_rows * pitch * 8 + tiles * 4096;
2077 unsigned int offset;
2079 offset = *y * pitch + *x * cpp;
2081 *x = (offset & 4095) / cpp;
2082 return offset & -4096;
2086 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2089 struct drm_device *dev = crtc->dev;
2090 struct drm_i915_private *dev_priv = dev->dev_private;
2091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2092 struct intel_framebuffer *intel_fb;
2093 struct drm_i915_gem_object *obj;
2094 int plane = intel_crtc->plane;
2095 unsigned long linear_offset;
2104 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2108 intel_fb = to_intel_framebuffer(fb);
2109 obj = intel_fb->obj;
2111 reg = DSPCNTR(plane);
2112 dspcntr = I915_READ(reg);
2113 /* Mask out pixel format bits in case we change it */
2114 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2115 switch (fb->pixel_format) {
2117 dspcntr |= DISPPLANE_8BPP;
2119 case DRM_FORMAT_XRGB1555:
2120 case DRM_FORMAT_ARGB1555:
2121 dspcntr |= DISPPLANE_BGRX555;
2123 case DRM_FORMAT_RGB565:
2124 dspcntr |= DISPPLANE_BGRX565;
2126 case DRM_FORMAT_XRGB8888:
2127 case DRM_FORMAT_ARGB8888:
2128 dspcntr |= DISPPLANE_BGRX888;
2130 case DRM_FORMAT_XBGR8888:
2131 case DRM_FORMAT_ABGR8888:
2132 dspcntr |= DISPPLANE_RGBX888;
2134 case DRM_FORMAT_XRGB2101010:
2135 case DRM_FORMAT_ARGB2101010:
2136 dspcntr |= DISPPLANE_BGRX101010;
2138 case DRM_FORMAT_XBGR2101010:
2139 case DRM_FORMAT_ABGR2101010:
2140 dspcntr |= DISPPLANE_RGBX101010;
2146 if (INTEL_INFO(dev)->gen >= 4) {
2147 if (obj->tiling_mode != I915_TILING_NONE)
2148 dspcntr |= DISPPLANE_TILED;
2150 dspcntr &= ~DISPPLANE_TILED;
2153 I915_WRITE(reg, dspcntr);
2155 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2157 if (INTEL_INFO(dev)->gen >= 4) {
2158 intel_crtc->dspaddr_offset =
2159 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2160 fb->bits_per_pixel / 8,
2162 linear_offset -= intel_crtc->dspaddr_offset;
2164 intel_crtc->dspaddr_offset = linear_offset;
2167 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2168 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2169 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2170 if (INTEL_INFO(dev)->gen >= 4) {
2171 I915_MODIFY_DISPBASE(DSPSURF(plane),
2172 obj->gtt_offset + intel_crtc->dspaddr_offset);
2173 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2174 I915_WRITE(DSPLINOFF(plane), linear_offset);
2176 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2182 static int ironlake_update_plane(struct drm_crtc *crtc,
2183 struct drm_framebuffer *fb, int x, int y)
2185 struct drm_device *dev = crtc->dev;
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188 struct intel_framebuffer *intel_fb;
2189 struct drm_i915_gem_object *obj;
2190 int plane = intel_crtc->plane;
2191 unsigned long linear_offset;
2201 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2205 intel_fb = to_intel_framebuffer(fb);
2206 obj = intel_fb->obj;
2208 reg = DSPCNTR(plane);
2209 dspcntr = I915_READ(reg);
2210 /* Mask out pixel format bits in case we change it */
2211 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2212 switch (fb->pixel_format) {
2214 dspcntr |= DISPPLANE_8BPP;
2216 case DRM_FORMAT_RGB565:
2217 dspcntr |= DISPPLANE_BGRX565;
2219 case DRM_FORMAT_XRGB8888:
2220 case DRM_FORMAT_ARGB8888:
2221 dspcntr |= DISPPLANE_BGRX888;
2223 case DRM_FORMAT_XBGR8888:
2224 case DRM_FORMAT_ABGR8888:
2225 dspcntr |= DISPPLANE_RGBX888;
2227 case DRM_FORMAT_XRGB2101010:
2228 case DRM_FORMAT_ARGB2101010:
2229 dspcntr |= DISPPLANE_BGRX101010;
2231 case DRM_FORMAT_XBGR2101010:
2232 case DRM_FORMAT_ABGR2101010:
2233 dspcntr |= DISPPLANE_RGBX101010;
2239 if (obj->tiling_mode != I915_TILING_NONE)
2240 dspcntr |= DISPPLANE_TILED;
2242 dspcntr &= ~DISPPLANE_TILED;
2245 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2247 I915_WRITE(reg, dspcntr);
2249 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2250 intel_crtc->dspaddr_offset =
2251 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2252 fb->bits_per_pixel / 8,
2254 linear_offset -= intel_crtc->dspaddr_offset;
2256 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2257 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2258 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2259 I915_MODIFY_DISPBASE(DSPSURF(plane),
2260 obj->gtt_offset + intel_crtc->dspaddr_offset);
2261 if (IS_HASWELL(dev)) {
2262 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2264 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2265 I915_WRITE(DSPLINOFF(plane), linear_offset);
2272 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2274 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2275 int x, int y, enum mode_set_atomic state)
2277 struct drm_device *dev = crtc->dev;
2278 struct drm_i915_private *dev_priv = dev->dev_private;
2280 if (dev_priv->display.disable_fbc)
2281 dev_priv->display.disable_fbc(dev);
2282 intel_increase_pllclock(crtc);
2284 return dev_priv->display.update_plane(crtc, fb, x, y);
2287 void intel_display_handle_reset(struct drm_device *dev)
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct drm_crtc *crtc;
2293 * Flips in the rings have been nuked by the reset,
2294 * so complete all pending flips so that user space
2295 * will get its events and not get stuck.
2297 * Also update the base address of all primary
2298 * planes to the the last fb to make sure we're
2299 * showing the correct fb after a reset.
2301 * Need to make two loops over the crtcs so that we
2302 * don't try to grab a crtc mutex before the
2303 * pending_flip_queue really got woken up.
2306 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2308 enum plane plane = intel_crtc->plane;
2310 intel_prepare_page_flip(dev, plane);
2311 intel_finish_page_flip_plane(dev, plane);
2314 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2317 mutex_lock(&crtc->mutex);
2318 if (intel_crtc->active)
2319 dev_priv->display.update_plane(crtc, crtc->fb,
2321 mutex_unlock(&crtc->mutex);
2326 intel_finish_fb(struct drm_framebuffer *old_fb)
2328 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2329 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2330 bool was_interruptible = dev_priv->mm.interruptible;
2333 /* Big Hammer, we also need to ensure that any pending
2334 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2335 * current scanout is retired before unpinning the old
2338 * This should only fail upon a hung GPU, in which case we
2339 * can safely continue.
2341 dev_priv->mm.interruptible = false;
2342 ret = i915_gem_object_finish_gpu(obj);
2343 dev_priv->mm.interruptible = was_interruptible;
2348 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2350 struct drm_device *dev = crtc->dev;
2351 struct drm_i915_master_private *master_priv;
2352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2354 if (!dev->primary->master)
2357 master_priv = dev->primary->master->driver_priv;
2358 if (!master_priv->sarea_priv)
2361 switch (intel_crtc->pipe) {
2363 master_priv->sarea_priv->pipeA_x = x;
2364 master_priv->sarea_priv->pipeA_y = y;
2367 master_priv->sarea_priv->pipeB_x = x;
2368 master_priv->sarea_priv->pipeB_y = y;
2376 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2377 struct drm_framebuffer *fb)
2379 struct drm_device *dev = crtc->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2382 struct drm_framebuffer *old_fb;
2387 DRM_ERROR("No FB bound\n");
2391 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2392 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2393 plane_name(intel_crtc->plane),
2394 INTEL_INFO(dev)->num_pipes);
2398 mutex_lock(&dev->struct_mutex);
2399 ret = intel_pin_and_fence_fb_obj(dev,
2400 to_intel_framebuffer(fb)->obj,
2403 mutex_unlock(&dev->struct_mutex);
2404 DRM_ERROR("pin & fence failed\n");
2408 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2410 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2411 mutex_unlock(&dev->struct_mutex);
2412 DRM_ERROR("failed to update base address\n");
2422 intel_wait_for_vblank(dev, intel_crtc->pipe);
2423 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2426 intel_update_fbc(dev);
2427 mutex_unlock(&dev->struct_mutex);
2429 intel_crtc_update_sarea_pos(crtc, x, y);
2434 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2436 struct drm_device *dev = crtc->dev;
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2439 int pipe = intel_crtc->pipe;
2442 /* enable normal train */
2443 reg = FDI_TX_CTL(pipe);
2444 temp = I915_READ(reg);
2445 if (IS_IVYBRIDGE(dev)) {
2446 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2447 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2449 temp &= ~FDI_LINK_TRAIN_NONE;
2450 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2452 I915_WRITE(reg, temp);
2454 reg = FDI_RX_CTL(pipe);
2455 temp = I915_READ(reg);
2456 if (HAS_PCH_CPT(dev)) {
2457 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2458 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2460 temp &= ~FDI_LINK_TRAIN_NONE;
2461 temp |= FDI_LINK_TRAIN_NONE;
2463 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2465 /* wait one idle pattern time */
2469 /* IVB wants error correction enabled */
2470 if (IS_IVYBRIDGE(dev))
2471 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2472 FDI_FE_ERRC_ENABLE);
2475 static void ivb_modeset_global_resources(struct drm_device *dev)
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_crtc *pipe_B_crtc =
2479 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2480 struct intel_crtc *pipe_C_crtc =
2481 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2484 /* When everything is off disable fdi C so that we could enable fdi B
2485 * with all lanes. XXX: This misses the case where a pipe is not using
2486 * any pch resources and so doesn't need any fdi lanes. */
2487 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2488 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2489 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2491 temp = I915_READ(SOUTH_CHICKEN1);
2492 temp &= ~FDI_BC_BIFURCATION_SELECT;
2493 DRM_DEBUG_KMS("disabling fdi C rx\n");
2494 I915_WRITE(SOUTH_CHICKEN1, temp);
2498 /* The FDI link training functions for ILK/Ibexpeak. */
2499 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2501 struct drm_device *dev = crtc->dev;
2502 struct drm_i915_private *dev_priv = dev->dev_private;
2503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2504 int pipe = intel_crtc->pipe;
2505 int plane = intel_crtc->plane;
2506 u32 reg, temp, tries;
2508 /* FDI needs bits from pipe & plane first */
2509 assert_pipe_enabled(dev_priv, pipe);
2510 assert_plane_enabled(dev_priv, plane);
2512 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2514 reg = FDI_RX_IMR(pipe);
2515 temp = I915_READ(reg);
2516 temp &= ~FDI_RX_SYMBOL_LOCK;
2517 temp &= ~FDI_RX_BIT_LOCK;
2518 I915_WRITE(reg, temp);
2522 /* enable CPU FDI TX and PCH FDI RX */
2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
2526 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2527 temp &= ~FDI_LINK_TRAIN_NONE;
2528 temp |= FDI_LINK_TRAIN_PATTERN_1;
2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2531 reg = FDI_RX_CTL(pipe);
2532 temp = I915_READ(reg);
2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_1;
2535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2540 /* Ironlake workaround, enable clock pointer after FDI enable*/
2541 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2542 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2543 FDI_RX_PHASE_SYNC_POINTER_EN);
2545 reg = FDI_RX_IIR(pipe);
2546 for (tries = 0; tries < 5; tries++) {
2547 temp = I915_READ(reg);
2548 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2550 if ((temp & FDI_RX_BIT_LOCK)) {
2551 DRM_DEBUG_KMS("FDI train 1 done.\n");
2552 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2557 DRM_ERROR("FDI train 1 fail!\n");
2560 reg = FDI_TX_CTL(pipe);
2561 temp = I915_READ(reg);
2562 temp &= ~FDI_LINK_TRAIN_NONE;
2563 temp |= FDI_LINK_TRAIN_PATTERN_2;
2564 I915_WRITE(reg, temp);
2566 reg = FDI_RX_CTL(pipe);
2567 temp = I915_READ(reg);
2568 temp &= ~FDI_LINK_TRAIN_NONE;
2569 temp |= FDI_LINK_TRAIN_PATTERN_2;
2570 I915_WRITE(reg, temp);
2575 reg = FDI_RX_IIR(pipe);
2576 for (tries = 0; tries < 5; tries++) {
2577 temp = I915_READ(reg);
2578 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2580 if (temp & FDI_RX_SYMBOL_LOCK) {
2581 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2582 DRM_DEBUG_KMS("FDI train 2 done.\n");
2587 DRM_ERROR("FDI train 2 fail!\n");
2589 DRM_DEBUG_KMS("FDI train done\n");
2593 static const int snb_b_fdi_train_param[] = {
2594 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2595 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2596 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2597 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2600 /* The FDI link training functions for SNB/Cougarpoint. */
2601 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2603 struct drm_device *dev = crtc->dev;
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2606 int pipe = intel_crtc->pipe;
2607 u32 reg, temp, i, retry;
2609 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2611 reg = FDI_RX_IMR(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_RX_SYMBOL_LOCK;
2614 temp &= ~FDI_RX_BIT_LOCK;
2615 I915_WRITE(reg, temp);
2620 /* enable CPU FDI TX and PCH FDI RX */
2621 reg = FDI_TX_CTL(pipe);
2622 temp = I915_READ(reg);
2624 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2625 temp &= ~FDI_LINK_TRAIN_NONE;
2626 temp |= FDI_LINK_TRAIN_PATTERN_1;
2627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2630 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2632 I915_WRITE(FDI_RX_MISC(pipe),
2633 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2635 reg = FDI_RX_CTL(pipe);
2636 temp = I915_READ(reg);
2637 if (HAS_PCH_CPT(dev)) {
2638 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2639 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2641 temp &= ~FDI_LINK_TRAIN_NONE;
2642 temp |= FDI_LINK_TRAIN_PATTERN_1;
2644 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2649 for (i = 0; i < 4; i++) {
2650 reg = FDI_TX_CTL(pipe);
2651 temp = I915_READ(reg);
2652 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2653 temp |= snb_b_fdi_train_param[i];
2654 I915_WRITE(reg, temp);
2659 for (retry = 0; retry < 5; retry++) {
2660 reg = FDI_RX_IIR(pipe);
2661 temp = I915_READ(reg);
2662 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2663 if (temp & FDI_RX_BIT_LOCK) {
2664 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665 DRM_DEBUG_KMS("FDI train 1 done.\n");
2674 DRM_ERROR("FDI train 1 fail!\n");
2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_NONE;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2;
2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2686 I915_WRITE(reg, temp);
2688 reg = FDI_RX_CTL(pipe);
2689 temp = I915_READ(reg);
2690 if (HAS_PCH_CPT(dev)) {
2691 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2692 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2694 temp &= ~FDI_LINK_TRAIN_NONE;
2695 temp |= FDI_LINK_TRAIN_PATTERN_2;
2697 I915_WRITE(reg, temp);
2702 for (i = 0; i < 4; i++) {
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2706 temp |= snb_b_fdi_train_param[i];
2707 I915_WRITE(reg, temp);
2712 for (retry = 0; retry < 5; retry++) {
2713 reg = FDI_RX_IIR(pipe);
2714 temp = I915_READ(reg);
2715 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2716 if (temp & FDI_RX_SYMBOL_LOCK) {
2717 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2718 DRM_DEBUG_KMS("FDI train 2 done.\n");
2727 DRM_ERROR("FDI train 2 fail!\n");
2729 DRM_DEBUG_KMS("FDI train done.\n");
2732 /* Manual link training for Ivy Bridge A0 parts */
2733 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2735 struct drm_device *dev = crtc->dev;
2736 struct drm_i915_private *dev_priv = dev->dev_private;
2737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2738 int pipe = intel_crtc->pipe;
2741 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2743 reg = FDI_RX_IMR(pipe);
2744 temp = I915_READ(reg);
2745 temp &= ~FDI_RX_SYMBOL_LOCK;
2746 temp &= ~FDI_RX_BIT_LOCK;
2747 I915_WRITE(reg, temp);
2752 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2753 I915_READ(FDI_RX_IIR(pipe)));
2755 /* enable CPU FDI TX and PCH FDI RX */
2756 reg = FDI_TX_CTL(pipe);
2757 temp = I915_READ(reg);
2759 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2760 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2761 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2762 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2763 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2764 temp |= FDI_COMPOSITE_SYNC;
2765 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2767 I915_WRITE(FDI_RX_MISC(pipe),
2768 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 temp &= ~FDI_LINK_TRAIN_AUTO;
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775 temp |= FDI_COMPOSITE_SYNC;
2776 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2781 for (i = 0; i < 4; i++) {
2782 reg = FDI_TX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2785 temp |= snb_b_fdi_train_param[i];
2786 I915_WRITE(reg, temp);
2791 reg = FDI_RX_IIR(pipe);
2792 temp = I915_READ(reg);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2795 if (temp & FDI_RX_BIT_LOCK ||
2796 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2797 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2798 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2803 DRM_ERROR("FDI train 1 fail!\n");
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2809 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2810 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2811 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2812 I915_WRITE(reg, temp);
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2817 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2818 I915_WRITE(reg, temp);
2823 for (i = 0; i < 4; i++) {
2824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2827 temp |= snb_b_fdi_train_param[i];
2828 I915_WRITE(reg, temp);
2833 reg = FDI_RX_IIR(pipe);
2834 temp = I915_READ(reg);
2835 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2837 if (temp & FDI_RX_SYMBOL_LOCK) {
2838 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2839 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2844 DRM_ERROR("FDI train 2 fail!\n");
2846 DRM_DEBUG_KMS("FDI train done.\n");
2849 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2851 struct drm_device *dev = intel_crtc->base.dev;
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853 int pipe = intel_crtc->pipe;
2857 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2858 reg = FDI_RX_CTL(pipe);
2859 temp = I915_READ(reg);
2860 temp &= ~((0x7 << 19) | (0x7 << 16));
2861 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2862 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2863 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2868 /* Switch from Rawclk to PCDclk */
2869 temp = I915_READ(reg);
2870 I915_WRITE(reg, temp | FDI_PCDCLK);
2875 /* Enable CPU FDI TX PLL, always on for Ironlake */
2876 reg = FDI_TX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2879 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2886 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2888 struct drm_device *dev = intel_crtc->base.dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2890 int pipe = intel_crtc->pipe;
2893 /* Switch from PCDclk to Rawclk */
2894 reg = FDI_RX_CTL(pipe);
2895 temp = I915_READ(reg);
2896 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2898 /* Disable CPU FDI TX PLL */
2899 reg = FDI_TX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2906 reg = FDI_RX_CTL(pipe);
2907 temp = I915_READ(reg);
2908 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2910 /* Wait for the clocks to turn off. */
2915 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 int pipe = intel_crtc->pipe;
2923 /* disable CPU FDI tx and PCH FDI rx */
2924 reg = FDI_TX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2929 reg = FDI_RX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 temp &= ~(0x7 << 16);
2932 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2933 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2938 /* Ironlake workaround, disable clock pointer after downing FDI */
2939 if (HAS_PCH_IBX(dev)) {
2940 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2943 /* still set train pattern 1 */
2944 reg = FDI_TX_CTL(pipe);
2945 temp = I915_READ(reg);
2946 temp &= ~FDI_LINK_TRAIN_NONE;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1;
2948 I915_WRITE(reg, temp);
2950 reg = FDI_RX_CTL(pipe);
2951 temp = I915_READ(reg);
2952 if (HAS_PCH_CPT(dev)) {
2953 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2954 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2956 temp &= ~FDI_LINK_TRAIN_NONE;
2957 temp |= FDI_LINK_TRAIN_PATTERN_1;
2959 /* BPC in FDI rx is consistent with that in PIPECONF */
2960 temp &= ~(0x07 << 16);
2961 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2962 I915_WRITE(reg, temp);
2968 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2970 struct drm_device *dev = crtc->dev;
2971 struct drm_i915_private *dev_priv = dev->dev_private;
2972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2973 unsigned long flags;
2976 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2977 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2980 spin_lock_irqsave(&dev->event_lock, flags);
2981 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2982 spin_unlock_irqrestore(&dev->event_lock, flags);
2987 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2989 struct drm_device *dev = crtc->dev;
2990 struct drm_i915_private *dev_priv = dev->dev_private;
2992 if (crtc->fb == NULL)
2995 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2997 wait_event(dev_priv->pending_flip_queue,
2998 !intel_crtc_has_pending_flip(crtc));
3000 mutex_lock(&dev->struct_mutex);
3001 intel_finish_fb(crtc->fb);
3002 mutex_unlock(&dev->struct_mutex);
3005 /* Program iCLKIP clock to the desired frequency */
3006 static void lpt_program_iclkip(struct drm_crtc *crtc)
3008 struct drm_device *dev = crtc->dev;
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3013 mutex_lock(&dev_priv->dpio_lock);
3015 /* It is necessary to ungate the pixclk gate prior to programming
3016 * the divisors, and gate it back when it is done.
3018 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3020 /* Disable SSCCTL */
3021 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3022 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3026 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3027 if (crtc->mode.clock == 20000) {
3032 /* The iCLK virtual clock root frequency is in MHz,
3033 * but the crtc->mode.clock in in KHz. To get the divisors,
3034 * it is necessary to divide one by another, so we
3035 * convert the virtual clock precision to KHz here for higher
3038 u32 iclk_virtual_root_freq = 172800 * 1000;
3039 u32 iclk_pi_range = 64;
3040 u32 desired_divisor, msb_divisor_value, pi_value;
3042 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3043 msb_divisor_value = desired_divisor / iclk_pi_range;
3044 pi_value = desired_divisor % iclk_pi_range;
3047 divsel = msb_divisor_value - 2;
3048 phaseinc = pi_value;
3051 /* This should not happen with any sane values */
3052 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3053 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3054 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3055 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3057 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3064 /* Program SSCDIVINTPHASE6 */
3065 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3066 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3067 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3068 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3069 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3070 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3071 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3072 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3074 /* Program SSCAUXDIV */
3075 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3076 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3077 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3078 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3080 /* Enable modulator and associated divider */
3081 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3082 temp &= ~SBI_SSCCTL_DISABLE;
3083 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3085 /* Wait for initialization time */
3088 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3090 mutex_unlock(&dev_priv->dpio_lock);
3094 * Enable PCH resources required for PCH ports:
3096 * - FDI training & RX/TX
3097 * - update transcoder timings
3098 * - DP transcoding bits
3101 static void ironlake_pch_enable(struct drm_crtc *crtc)
3103 struct drm_device *dev = crtc->dev;
3104 struct drm_i915_private *dev_priv = dev->dev_private;
3105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3106 int pipe = intel_crtc->pipe;
3109 assert_transcoder_disabled(dev_priv, pipe);
3111 /* Write the TU size bits before fdi link training, so that error
3112 * detection works. */
3113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3116 /* For PCH output, training FDI link */
3117 dev_priv->display.fdi_link_train(crtc);
3119 /* XXX: pch pll's can be enabled any time before we enable the PCH
3120 * transcoder, and we actually should do this to not upset any PCH
3121 * transcoder that already use the clock when we share it.
3123 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3124 * unconditionally resets the pll - we need that to have the right LVDS
3125 * enable sequence. */
3126 ironlake_enable_pch_pll(intel_crtc);
3128 if (HAS_PCH_CPT(dev)) {
3131 temp = I915_READ(PCH_DPLL_SEL);
3135 temp |= TRANSA_DPLL_ENABLE;
3136 sel = TRANSA_DPLLB_SEL;
3139 temp |= TRANSB_DPLL_ENABLE;
3140 sel = TRANSB_DPLLB_SEL;
3143 temp |= TRANSC_DPLL_ENABLE;
3144 sel = TRANSC_DPLLB_SEL;
3147 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3151 I915_WRITE(PCH_DPLL_SEL, temp);
3154 /* set transcoder timing, panel must allow it */
3155 assert_panel_unlocked(dev_priv, pipe);
3156 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3157 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3158 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3160 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3161 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3162 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3163 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3165 intel_fdi_normal_train(crtc);
3167 /* For PCH DP, enable TRANS_DP_CTL */
3168 if (HAS_PCH_CPT(dev) &&
3169 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3170 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3171 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3172 reg = TRANS_DP_CTL(pipe);
3173 temp = I915_READ(reg);
3174 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3175 TRANS_DP_SYNC_MASK |
3177 temp |= (TRANS_DP_OUTPUT_ENABLE |
3178 TRANS_DP_ENH_FRAMING);
3179 temp |= bpc << 9; /* same format but at 11:9 */
3181 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3182 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3183 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3184 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3186 switch (intel_trans_dp_port_sel(crtc)) {
3188 temp |= TRANS_DP_PORT_SEL_B;
3191 temp |= TRANS_DP_PORT_SEL_C;
3194 temp |= TRANS_DP_PORT_SEL_D;
3200 I915_WRITE(reg, temp);
3203 ironlake_enable_pch_transcoder(dev_priv, pipe);
3206 static void lpt_pch_enable(struct drm_crtc *crtc)
3208 struct drm_device *dev = crtc->dev;
3209 struct drm_i915_private *dev_priv = dev->dev_private;
3210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3211 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3213 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3215 lpt_program_iclkip(crtc);
3217 /* Set transcoder timing. */
3218 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3219 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3220 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3222 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3223 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3224 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3225 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3227 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3230 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3232 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3237 if (pll->refcount == 0) {
3238 WARN(1, "bad PCH PLL refcount\n");
3243 intel_crtc->pch_pll = NULL;
3246 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3248 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3249 struct intel_pch_pll *pll;
3252 pll = intel_crtc->pch_pll;
3254 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3255 intel_crtc->base.base.id, pll->pll_reg);
3259 if (HAS_PCH_IBX(dev_priv->dev)) {
3260 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3261 i = intel_crtc->pipe;
3262 pll = &dev_priv->pch_plls[i];
3264 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3265 intel_crtc->base.base.id, pll->pll_reg);
3270 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3271 pll = &dev_priv->pch_plls[i];
3273 /* Only want to check enabled timings first */
3274 if (pll->refcount == 0)
3277 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3278 fp == I915_READ(pll->fp0_reg)) {
3279 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3280 intel_crtc->base.base.id,
3281 pll->pll_reg, pll->refcount, pll->active);
3287 /* Ok no matching timings, maybe there's a free one? */
3288 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3289 pll = &dev_priv->pch_plls[i];
3290 if (pll->refcount == 0) {
3291 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3292 intel_crtc->base.base.id, pll->pll_reg);
3300 intel_crtc->pch_pll = pll;
3302 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3303 prepare: /* separate function? */
3304 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3306 /* Wait for the clocks to stabilize before rewriting the regs */
3307 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3308 POSTING_READ(pll->pll_reg);
3311 I915_WRITE(pll->fp0_reg, fp);
3312 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3317 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3319 struct drm_i915_private *dev_priv = dev->dev_private;
3320 int dslreg = PIPEDSL(pipe);
3323 temp = I915_READ(dslreg);
3325 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3326 if (wait_for(I915_READ(dslreg) != temp, 5))
3327 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3331 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3333 struct drm_device *dev = crtc->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3336 struct intel_encoder *encoder;
3337 int pipe = intel_crtc->pipe;
3338 int plane = intel_crtc->plane;
3341 WARN_ON(!crtc->enabled);
3343 if (intel_crtc->active)
3346 intel_crtc->active = true;
3347 intel_update_watermarks(dev);
3349 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3350 temp = I915_READ(PCH_LVDS);
3351 if ((temp & LVDS_PORT_EN) == 0)
3352 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3356 if (intel_crtc->config.has_pch_encoder) {
3357 /* Note: FDI PLL enabling _must_ be done before we enable the
3358 * cpu pipes, hence this is separate from all the other fdi/pch
3360 ironlake_fdi_pll_enable(intel_crtc);
3362 assert_fdi_tx_disabled(dev_priv, pipe);
3363 assert_fdi_rx_disabled(dev_priv, pipe);
3366 for_each_encoder_on_crtc(dev, crtc, encoder)
3367 if (encoder->pre_enable)
3368 encoder->pre_enable(encoder);
3370 /* Enable panel fitting for LVDS */
3371 if (dev_priv->pch_pf_size &&
3372 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3373 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3374 /* Force use of hard-coded filter coefficients
3375 * as some pre-programmed values are broken,
3378 if (IS_IVYBRIDGE(dev))
3379 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3380 PF_PIPE_SEL_IVB(pipe));
3382 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3383 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3384 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3388 * On ILK+ LUT must be loaded before the pipe is running but with
3391 intel_crtc_load_lut(crtc);
3393 intel_enable_pipe(dev_priv, pipe,
3394 intel_crtc->config.has_pch_encoder);
3395 intel_enable_plane(dev_priv, plane, pipe);
3397 if (intel_crtc->config.has_pch_encoder)
3398 ironlake_pch_enable(crtc);
3400 mutex_lock(&dev->struct_mutex);
3401 intel_update_fbc(dev);
3402 mutex_unlock(&dev->struct_mutex);
3404 intel_crtc_update_cursor(crtc, true);
3406 for_each_encoder_on_crtc(dev, crtc, encoder)
3407 encoder->enable(encoder);
3409 if (HAS_PCH_CPT(dev))
3410 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3413 * There seems to be a race in PCH platform hw (at least on some
3414 * outputs) where an enabled pipe still completes any pageflip right
3415 * away (as if the pipe is off) instead of waiting for vblank. As soon
3416 * as the first vblank happend, everything works as expected. Hence just
3417 * wait for one vblank before returning to avoid strange things
3420 intel_wait_for_vblank(dev, intel_crtc->pipe);
3423 static void haswell_crtc_enable(struct drm_crtc *crtc)
3425 struct drm_device *dev = crtc->dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3428 struct intel_encoder *encoder;
3429 int pipe = intel_crtc->pipe;
3430 int plane = intel_crtc->plane;
3432 WARN_ON(!crtc->enabled);
3434 if (intel_crtc->active)
3437 intel_crtc->active = true;
3438 intel_update_watermarks(dev);
3440 if (intel_crtc->config.has_pch_encoder)
3441 dev_priv->display.fdi_link_train(crtc);
3443 for_each_encoder_on_crtc(dev, crtc, encoder)
3444 if (encoder->pre_enable)
3445 encoder->pre_enable(encoder);
3447 intel_ddi_enable_pipe_clock(intel_crtc);
3449 /* Enable panel fitting for eDP */
3450 if (dev_priv->pch_pf_size &&
3451 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3452 /* Force use of hard-coded filter coefficients
3453 * as some pre-programmed values are broken,
3456 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3457 PF_PIPE_SEL_IVB(pipe));
3458 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3459 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3463 * On ILK+ LUT must be loaded before the pipe is running but with
3466 intel_crtc_load_lut(crtc);
3468 intel_ddi_set_pipe_settings(crtc);
3469 intel_ddi_enable_transcoder_func(crtc);
3471 intel_enable_pipe(dev_priv, pipe,
3472 intel_crtc->config.has_pch_encoder);
3473 intel_enable_plane(dev_priv, plane, pipe);
3475 if (intel_crtc->config.has_pch_encoder)
3476 lpt_pch_enable(crtc);
3478 mutex_lock(&dev->struct_mutex);
3479 intel_update_fbc(dev);
3480 mutex_unlock(&dev->struct_mutex);
3482 intel_crtc_update_cursor(crtc, true);
3484 for_each_encoder_on_crtc(dev, crtc, encoder)
3485 encoder->enable(encoder);
3488 * There seems to be a race in PCH platform hw (at least on some
3489 * outputs) where an enabled pipe still completes any pageflip right
3490 * away (as if the pipe is off) instead of waiting for vblank. As soon
3491 * as the first vblank happend, everything works as expected. Hence just
3492 * wait for one vblank before returning to avoid strange things
3495 intel_wait_for_vblank(dev, intel_crtc->pipe);
3498 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3500 struct drm_device *dev = crtc->dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3503 struct intel_encoder *encoder;
3504 int pipe = intel_crtc->pipe;
3505 int plane = intel_crtc->plane;
3509 if (!intel_crtc->active)
3512 for_each_encoder_on_crtc(dev, crtc, encoder)
3513 encoder->disable(encoder);
3515 intel_crtc_wait_for_pending_flips(crtc);
3516 drm_vblank_off(dev, pipe);
3517 intel_crtc_update_cursor(crtc, false);
3519 intel_disable_plane(dev_priv, plane, pipe);
3521 if (dev_priv->cfb_plane == plane)
3522 intel_disable_fbc(dev);
3524 intel_disable_pipe(dev_priv, pipe);
3527 I915_WRITE(PF_CTL(pipe), 0);
3528 I915_WRITE(PF_WIN_SZ(pipe), 0);
3530 for_each_encoder_on_crtc(dev, crtc, encoder)
3531 if (encoder->post_disable)
3532 encoder->post_disable(encoder);
3534 ironlake_fdi_disable(crtc);
3536 ironlake_disable_pch_transcoder(dev_priv, pipe);
3538 if (HAS_PCH_CPT(dev)) {
3539 /* disable TRANS_DP_CTL */
3540 reg = TRANS_DP_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3543 temp |= TRANS_DP_PORT_SEL_NONE;
3544 I915_WRITE(reg, temp);
3546 /* disable DPLL_SEL */
3547 temp = I915_READ(PCH_DPLL_SEL);
3550 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3553 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3556 /* C shares PLL A or B */
3557 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3562 I915_WRITE(PCH_DPLL_SEL, temp);
3565 /* disable PCH DPLL */
3566 intel_disable_pch_pll(intel_crtc);
3568 ironlake_fdi_pll_disable(intel_crtc);
3570 intel_crtc->active = false;
3571 intel_update_watermarks(dev);
3573 mutex_lock(&dev->struct_mutex);
3574 intel_update_fbc(dev);
3575 mutex_unlock(&dev->struct_mutex);
3578 static void haswell_crtc_disable(struct drm_crtc *crtc)
3580 struct drm_device *dev = crtc->dev;
3581 struct drm_i915_private *dev_priv = dev->dev_private;
3582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3583 struct intel_encoder *encoder;
3584 int pipe = intel_crtc->pipe;
3585 int plane = intel_crtc->plane;
3586 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3588 if (!intel_crtc->active)
3591 for_each_encoder_on_crtc(dev, crtc, encoder)
3592 encoder->disable(encoder);
3594 intel_crtc_wait_for_pending_flips(crtc);
3595 drm_vblank_off(dev, pipe);
3596 intel_crtc_update_cursor(crtc, false);
3598 intel_disable_plane(dev_priv, plane, pipe);
3600 if (dev_priv->cfb_plane == plane)
3601 intel_disable_fbc(dev);
3603 intel_disable_pipe(dev_priv, pipe);
3605 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3607 /* XXX: Once we have proper panel fitter state tracking implemented with
3608 * hardware state read/check support we should switch to only disable
3609 * the panel fitter when we know it's used. */
3610 if (intel_using_power_well(dev)) {
3611 I915_WRITE(PF_CTL(pipe), 0);
3612 I915_WRITE(PF_WIN_SZ(pipe), 0);
3615 intel_ddi_disable_pipe_clock(intel_crtc);
3617 for_each_encoder_on_crtc(dev, crtc, encoder)
3618 if (encoder->post_disable)
3619 encoder->post_disable(encoder);
3621 if (intel_crtc->config.has_pch_encoder) {
3622 lpt_disable_pch_transcoder(dev_priv);
3623 intel_ddi_fdi_disable(crtc);
3626 intel_crtc->active = false;
3627 intel_update_watermarks(dev);
3629 mutex_lock(&dev->struct_mutex);
3630 intel_update_fbc(dev);
3631 mutex_unlock(&dev->struct_mutex);
3634 static void ironlake_crtc_off(struct drm_crtc *crtc)
3636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3637 intel_put_pch_pll(intel_crtc);
3640 static void haswell_crtc_off(struct drm_crtc *crtc)
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3645 * start using it. */
3646 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3648 intel_ddi_put_crtc_pll(crtc);
3651 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3653 if (!enable && intel_crtc->overlay) {
3654 struct drm_device *dev = intel_crtc->base.dev;
3655 struct drm_i915_private *dev_priv = dev->dev_private;
3657 mutex_lock(&dev->struct_mutex);
3658 dev_priv->mm.interruptible = false;
3659 (void) intel_overlay_switch_off(intel_crtc->overlay);
3660 dev_priv->mm.interruptible = true;
3661 mutex_unlock(&dev->struct_mutex);
3664 /* Let userspace switch the overlay on again. In most cases userspace
3665 * has to recompute where to put it anyway.
3670 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3671 * cursor plane briefly if not already running after enabling the display
3673 * This workaround avoids occasional blank screens when self refresh is
3677 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3679 u32 cntl = I915_READ(CURCNTR(pipe));
3681 if ((cntl & CURSOR_MODE) == 0) {
3682 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3684 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3685 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3686 intel_wait_for_vblank(dev_priv->dev, pipe);
3687 I915_WRITE(CURCNTR(pipe), cntl);
3688 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3689 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3693 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3695 struct drm_device *dev = crtc->dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3698 struct intel_encoder *encoder;
3699 int pipe = intel_crtc->pipe;
3700 int plane = intel_crtc->plane;
3702 WARN_ON(!crtc->enabled);
3704 if (intel_crtc->active)
3707 intel_crtc->active = true;
3708 intel_update_watermarks(dev);
3710 intel_enable_pll(dev_priv, pipe);
3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 if (encoder->pre_enable)
3714 encoder->pre_enable(encoder);
3716 intel_enable_pipe(dev_priv, pipe, false);
3717 intel_enable_plane(dev_priv, plane, pipe);
3719 g4x_fixup_plane(dev_priv, pipe);
3721 intel_crtc_load_lut(crtc);
3722 intel_update_fbc(dev);
3724 /* Give the overlay scaler a chance to enable if it's on this pipe */
3725 intel_crtc_dpms_overlay(intel_crtc, true);
3726 intel_crtc_update_cursor(crtc, true);
3728 for_each_encoder_on_crtc(dev, crtc, encoder)
3729 encoder->enable(encoder);
3732 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3734 struct drm_device *dev = crtc->base.dev;
3735 struct drm_i915_private *dev_priv = dev->dev_private;
3737 uint32_t pctl = I915_READ(PFIT_CONTROL);
3739 assert_pipe_disabled(dev_priv, crtc->pipe);
3741 if (INTEL_INFO(dev)->gen >= 4)
3742 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3746 if (pipe == crtc->pipe) {
3747 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3748 I915_WRITE(PFIT_CONTROL, 0);
3752 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3757 struct intel_encoder *encoder;
3758 int pipe = intel_crtc->pipe;
3759 int plane = intel_crtc->plane;
3761 if (!intel_crtc->active)
3764 for_each_encoder_on_crtc(dev, crtc, encoder)
3765 encoder->disable(encoder);
3767 /* Give the overlay scaler a chance to disable if it's on this pipe */
3768 intel_crtc_wait_for_pending_flips(crtc);
3769 drm_vblank_off(dev, pipe);
3770 intel_crtc_dpms_overlay(intel_crtc, false);
3771 intel_crtc_update_cursor(crtc, false);
3773 if (dev_priv->cfb_plane == plane)
3774 intel_disable_fbc(dev);
3776 intel_disable_plane(dev_priv, plane, pipe);
3777 intel_disable_pipe(dev_priv, pipe);
3779 i9xx_pfit_disable(intel_crtc);
3781 intel_disable_pll(dev_priv, pipe);
3783 intel_crtc->active = false;
3784 intel_update_fbc(dev);
3785 intel_update_watermarks(dev);
3788 static void i9xx_crtc_off(struct drm_crtc *crtc)
3792 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_master_private *master_priv;
3797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798 int pipe = intel_crtc->pipe;
3800 if (!dev->primary->master)
3803 master_priv = dev->primary->master->driver_priv;
3804 if (!master_priv->sarea_priv)
3809 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3810 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3813 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3814 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3817 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3823 * Sets the power management mode of the pipe and plane.
3825 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3827 struct drm_device *dev = crtc->dev;
3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 struct intel_encoder *intel_encoder;
3830 bool enable = false;
3832 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3833 enable |= intel_encoder->connectors_active;
3836 dev_priv->display.crtc_enable(crtc);
3838 dev_priv->display.crtc_disable(crtc);
3840 intel_crtc_update_sarea(crtc, enable);
3843 static void intel_crtc_disable(struct drm_crtc *crtc)
3845 struct drm_device *dev = crtc->dev;
3846 struct drm_connector *connector;
3847 struct drm_i915_private *dev_priv = dev->dev_private;
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3850 /* crtc should still be enabled when we disable it. */
3851 WARN_ON(!crtc->enabled);
3853 intel_crtc->eld_vld = false;
3854 dev_priv->display.crtc_disable(crtc);
3855 intel_crtc_update_sarea(crtc, false);
3856 dev_priv->display.off(crtc);
3858 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3859 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3862 mutex_lock(&dev->struct_mutex);
3863 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3864 mutex_unlock(&dev->struct_mutex);
3868 /* Update computed state. */
3869 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3870 if (!connector->encoder || !connector->encoder->crtc)
3873 if (connector->encoder->crtc != crtc)
3876 connector->dpms = DRM_MODE_DPMS_OFF;
3877 to_intel_encoder(connector->encoder)->connectors_active = false;
3881 void intel_modeset_disable(struct drm_device *dev)
3883 struct drm_crtc *crtc;
3885 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3887 intel_crtc_disable(crtc);
3891 void intel_encoder_destroy(struct drm_encoder *encoder)
3893 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3895 drm_encoder_cleanup(encoder);
3896 kfree(intel_encoder);
3899 /* Simple dpms helper for encodres with just one connector, no cloning and only
3900 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3901 * state of the entire output pipe. */
3902 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3904 if (mode == DRM_MODE_DPMS_ON) {
3905 encoder->connectors_active = true;
3907 intel_crtc_update_dpms(encoder->base.crtc);
3909 encoder->connectors_active = false;
3911 intel_crtc_update_dpms(encoder->base.crtc);
3915 /* Cross check the actual hw state with our own modeset state tracking (and it's
3916 * internal consistency). */
3917 static void intel_connector_check_state(struct intel_connector *connector)
3919 if (connector->get_hw_state(connector)) {
3920 struct intel_encoder *encoder = connector->encoder;
3921 struct drm_crtc *crtc;
3922 bool encoder_enabled;
3925 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3926 connector->base.base.id,
3927 drm_get_connector_name(&connector->base));
3929 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3930 "wrong connector dpms state\n");
3931 WARN(connector->base.encoder != &encoder->base,
3932 "active connector not linked to encoder\n");
3933 WARN(!encoder->connectors_active,
3934 "encoder->connectors_active not set\n");
3936 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3937 WARN(!encoder_enabled, "encoder not enabled\n");
3938 if (WARN_ON(!encoder->base.crtc))
3941 crtc = encoder->base.crtc;
3943 WARN(!crtc->enabled, "crtc not enabled\n");
3944 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3945 WARN(pipe != to_intel_crtc(crtc)->pipe,
3946 "encoder active on the wrong pipe\n");
3950 /* Even simpler default implementation, if there's really no special case to
3952 void intel_connector_dpms(struct drm_connector *connector, int mode)
3954 struct intel_encoder *encoder = intel_attached_encoder(connector);
3956 /* All the simple cases only support two dpms states. */
3957 if (mode != DRM_MODE_DPMS_ON)
3958 mode = DRM_MODE_DPMS_OFF;
3960 if (mode == connector->dpms)
3963 connector->dpms = mode;
3965 /* Only need to change hw state when actually enabled */
3966 if (encoder->base.crtc)
3967 intel_encoder_dpms(encoder, mode);
3969 WARN_ON(encoder->connectors_active != false);
3971 intel_modeset_check_state(connector->dev);
3974 /* Simple connector->get_hw_state implementation for encoders that support only
3975 * one connector and no cloning and hence the encoder state determines the state
3976 * of the connector. */
3977 bool intel_connector_get_hw_state(struct intel_connector *connector)
3980 struct intel_encoder *encoder = connector->encoder;
3982 return encoder->get_hw_state(encoder, &pipe);
3985 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3986 struct intel_crtc_config *pipe_config)
3988 struct drm_device *dev = crtc->dev;
3989 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3991 if (HAS_PCH_SPLIT(dev)) {
3992 /* FDI link clock is fixed at 2.7G */
3993 if (pipe_config->requested_mode.clock * 3
3994 > IRONLAKE_FDI_FREQ * 4)
3998 /* All interlaced capable intel hw wants timings in frames. Note though
3999 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4000 * timings, so we need to be careful not to clobber these.*/
4001 if (!pipe_config->timings_set)
4002 drm_mode_set_crtcinfo(adjusted_mode, 0);
4004 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4005 * with a hsync front porch of 0.
4007 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4008 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4011 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4012 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4013 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4014 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4016 pipe_config->pipe_bpp = 8*3;
4022 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4024 return 400000; /* FIXME */
4027 static int i945_get_display_clock_speed(struct drm_device *dev)
4032 static int i915_get_display_clock_speed(struct drm_device *dev)
4037 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4042 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4046 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4048 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4051 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4052 case GC_DISPLAY_CLOCK_333_MHZ:
4055 case GC_DISPLAY_CLOCK_190_200_MHZ:
4061 static int i865_get_display_clock_speed(struct drm_device *dev)
4066 static int i855_get_display_clock_speed(struct drm_device *dev)
4069 /* Assume that the hardware is in the high speed state. This
4070 * should be the default.
4072 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4073 case GC_CLOCK_133_200:
4074 case GC_CLOCK_100_200:
4076 case GC_CLOCK_166_250:
4078 case GC_CLOCK_100_133:
4082 /* Shouldn't happen */
4086 static int i830_get_display_clock_speed(struct drm_device *dev)
4092 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4094 while (*num > 0xffffff || *den > 0xffffff) {
4101 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4102 int pixel_clock, int link_clock,
4103 struct intel_link_m_n *m_n)
4106 m_n->gmch_m = bits_per_pixel * pixel_clock;
4107 m_n->gmch_n = link_clock * nlanes * 8;
4108 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4109 m_n->link_m = pixel_clock;
4110 m_n->link_n = link_clock;
4111 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4114 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4116 if (i915_panel_use_ssc >= 0)
4117 return i915_panel_use_ssc != 0;
4118 return dev_priv->lvds_use_ssc
4119 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4122 static int vlv_get_refclk(struct drm_crtc *crtc)
4124 struct drm_device *dev = crtc->dev;
4125 struct drm_i915_private *dev_priv = dev->dev_private;
4126 int refclk = 27000; /* for DP & HDMI */
4128 return 100000; /* only one validated so far */
4130 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4132 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4133 if (intel_panel_use_ssc(dev_priv))
4137 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4144 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4146 struct drm_device *dev = crtc->dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4150 if (IS_VALLEYVIEW(dev)) {
4151 refclk = vlv_get_refclk(crtc);
4152 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4153 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4154 refclk = dev_priv->lvds_ssc_freq * 1000;
4155 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4157 } else if (!IS_GEN2(dev)) {
4166 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4168 unsigned dotclock = crtc->config.adjusted_mode.clock;
4169 struct dpll *clock = &crtc->config.dpll;
4171 /* SDVO TV has fixed PLL values depend on its clock range,
4172 this mirrors vbios setting. */
4173 if (dotclock >= 100000 && dotclock < 140500) {
4179 } else if (dotclock >= 140500 && dotclock <= 200000) {
4187 crtc->config.clock_set = true;
4190 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4191 intel_clock_t *reduced_clock)
4193 struct drm_device *dev = crtc->base.dev;
4194 struct drm_i915_private *dev_priv = dev->dev_private;
4195 int pipe = crtc->pipe;
4197 struct dpll *clock = &crtc->config.dpll;
4199 if (IS_PINEVIEW(dev)) {
4200 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4202 fp2 = (1 << reduced_clock->n) << 16 |
4203 reduced_clock->m1 << 8 | reduced_clock->m2;
4205 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4207 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4211 I915_WRITE(FP0(pipe), fp);
4213 crtc->lowfreq_avail = false;
4214 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4215 reduced_clock && i915_powersave) {
4216 I915_WRITE(FP1(pipe), fp2);
4217 crtc->lowfreq_avail = true;
4219 I915_WRITE(FP1(pipe), fp);
4223 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4225 if (crtc->config.has_pch_encoder)
4226 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4228 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4231 static void vlv_update_pll(struct intel_crtc *crtc)
4233 struct drm_device *dev = crtc->base.dev;
4234 struct drm_i915_private *dev_priv = dev->dev_private;
4235 int pipe = crtc->pipe;
4236 u32 dpll, mdiv, pdiv;
4237 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4241 mutex_lock(&dev_priv->dpio_lock);
4243 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4244 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4246 dpll = DPLL_VGA_MODE_DIS;
4247 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4248 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4249 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4251 I915_WRITE(DPLL(pipe), dpll);
4252 POSTING_READ(DPLL(pipe));
4254 bestn = crtc->config.dpll.n;
4255 bestm1 = crtc->config.dpll.m1;
4256 bestm2 = crtc->config.dpll.m2;
4257 bestp1 = crtc->config.dpll.p1;
4258 bestp2 = crtc->config.dpll.p2;
4261 * In Valleyview PLL and program lane counter registers are exposed
4262 * through DPIO interface
4264 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4265 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4266 mdiv |= ((bestn << DPIO_N_SHIFT));
4267 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4268 mdiv |= (1 << DPIO_K_SHIFT);
4269 mdiv |= DPIO_ENABLE_CALIBRATION;
4270 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4272 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4274 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4275 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4276 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4277 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4278 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4280 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4282 dpll |= DPLL_VCO_ENABLE;
4283 I915_WRITE(DPLL(pipe), dpll);
4284 POSTING_READ(DPLL(pipe));
4285 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4286 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4288 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4290 if (crtc->config.has_dp_encoder)
4291 intel_dp_set_m_n(crtc);
4293 I915_WRITE(DPLL(pipe), dpll);
4295 /* Wait for the clocks to stabilize. */
4296 POSTING_READ(DPLL(pipe));
4302 if (crtc->config.pixel_multiplier > 1) {
4303 temp = (crtc->config.pixel_multiplier - 1)
4304 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4307 I915_WRITE(DPLL_MD(pipe), temp);
4308 POSTING_READ(DPLL_MD(pipe));
4310 /* Now program lane control registers */
4311 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4312 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
4316 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4319 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
4323 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4326 mutex_unlock(&dev_priv->dpio_lock);
4329 static void i9xx_update_pll(struct intel_crtc *crtc,
4330 intel_clock_t *reduced_clock,
4333 struct drm_device *dev = crtc->base.dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 struct intel_encoder *encoder;
4336 int pipe = crtc->pipe;
4339 struct dpll *clock = &crtc->config.dpll;
4341 i9xx_update_pll_dividers(crtc, reduced_clock);
4343 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4344 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4346 dpll = DPLL_VGA_MODE_DIS;
4348 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4349 dpll |= DPLLB_MODE_LVDS;
4351 dpll |= DPLLB_MODE_DAC_SERIAL;
4354 if ((crtc->config.pixel_multiplier > 1) &&
4355 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4356 dpll |= (crtc->config.pixel_multiplier - 1)
4357 << SDVO_MULTIPLIER_SHIFT_HIRES;
4359 dpll |= DPLL_DVO_HIGH_SPEED;
4361 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4362 dpll |= DPLL_DVO_HIGH_SPEED;
4364 /* compute bitmask from p1 value */
4365 if (IS_PINEVIEW(dev))
4366 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4368 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4369 if (IS_G4X(dev) && reduced_clock)
4370 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4372 switch (clock->p2) {
4374 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4377 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4380 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4383 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4386 if (INTEL_INFO(dev)->gen >= 4)
4387 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4389 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4390 dpll |= PLL_REF_INPUT_TVCLKINBC;
4391 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4392 /* XXX: just matching BIOS for now */
4393 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4395 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4396 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4397 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4399 dpll |= PLL_REF_INPUT_DREFCLK;
4401 dpll |= DPLL_VCO_ENABLE;
4402 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4403 POSTING_READ(DPLL(pipe));
4406 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4407 if (encoder->pre_pll_enable)
4408 encoder->pre_pll_enable(encoder);
4410 if (crtc->config.has_dp_encoder)
4411 intel_dp_set_m_n(crtc);
4413 I915_WRITE(DPLL(pipe), dpll);
4415 /* Wait for the clocks to stabilize. */
4416 POSTING_READ(DPLL(pipe));
4419 if (INTEL_INFO(dev)->gen >= 4) {
4423 if (crtc->config.pixel_multiplier > 1) {
4424 temp = (crtc->config.pixel_multiplier - 1)
4425 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4428 I915_WRITE(DPLL_MD(pipe), temp);
4430 /* The pixel multiplier can only be updated once the
4431 * DPLL is enabled and the clocks are stable.
4433 * So write it again.
4435 I915_WRITE(DPLL(pipe), dpll);
4439 static void i8xx_update_pll(struct intel_crtc *crtc,
4440 struct drm_display_mode *adjusted_mode,
4441 intel_clock_t *reduced_clock,
4444 struct drm_device *dev = crtc->base.dev;
4445 struct drm_i915_private *dev_priv = dev->dev_private;
4446 struct intel_encoder *encoder;
4447 int pipe = crtc->pipe;
4449 struct dpll *clock = &crtc->config.dpll;
4451 i9xx_update_pll_dividers(crtc, reduced_clock);
4453 dpll = DPLL_VGA_MODE_DIS;
4455 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4456 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4459 dpll |= PLL_P1_DIVIDE_BY_TWO;
4461 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4463 dpll |= PLL_P2_DIVIDE_BY_4;
4466 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4467 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4468 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4470 dpll |= PLL_REF_INPUT_DREFCLK;
4472 dpll |= DPLL_VCO_ENABLE;
4473 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4474 POSTING_READ(DPLL(pipe));
4477 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4478 if (encoder->pre_pll_enable)
4479 encoder->pre_pll_enable(encoder);
4481 I915_WRITE(DPLL(pipe), dpll);
4483 /* Wait for the clocks to stabilize. */
4484 POSTING_READ(DPLL(pipe));
4487 /* The pixel multiplier can only be updated once the
4488 * DPLL is enabled and the clocks are stable.
4490 * So write it again.
4492 I915_WRITE(DPLL(pipe), dpll);
4495 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4496 struct drm_display_mode *mode,
4497 struct drm_display_mode *adjusted_mode)
4499 struct drm_device *dev = intel_crtc->base.dev;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 enum pipe pipe = intel_crtc->pipe;
4502 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4503 uint32_t vsyncshift;
4505 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4506 /* the chip adds 2 halflines automatically */
4507 adjusted_mode->crtc_vtotal -= 1;
4508 adjusted_mode->crtc_vblank_end -= 1;
4509 vsyncshift = adjusted_mode->crtc_hsync_start
4510 - adjusted_mode->crtc_htotal / 2;
4515 if (INTEL_INFO(dev)->gen > 3)
4516 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4518 I915_WRITE(HTOTAL(cpu_transcoder),
4519 (adjusted_mode->crtc_hdisplay - 1) |
4520 ((adjusted_mode->crtc_htotal - 1) << 16));
4521 I915_WRITE(HBLANK(cpu_transcoder),
4522 (adjusted_mode->crtc_hblank_start - 1) |
4523 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4524 I915_WRITE(HSYNC(cpu_transcoder),
4525 (adjusted_mode->crtc_hsync_start - 1) |
4526 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4528 I915_WRITE(VTOTAL(cpu_transcoder),
4529 (adjusted_mode->crtc_vdisplay - 1) |
4530 ((adjusted_mode->crtc_vtotal - 1) << 16));
4531 I915_WRITE(VBLANK(cpu_transcoder),
4532 (adjusted_mode->crtc_vblank_start - 1) |
4533 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4534 I915_WRITE(VSYNC(cpu_transcoder),
4535 (adjusted_mode->crtc_vsync_start - 1) |
4536 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4538 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4539 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4540 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4542 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4543 (pipe == PIPE_B || pipe == PIPE_C))
4544 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4546 /* pipesrc controls the size that is scaled from, which should
4547 * always be the user's requested size.
4549 I915_WRITE(PIPESRC(pipe),
4550 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4553 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4555 struct drm_device *dev = intel_crtc->base.dev;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4559 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4561 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4562 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4565 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4568 if (intel_crtc->config.requested_mode.clock >
4569 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4570 pipeconf |= PIPECONF_DOUBLE_WIDE;
4572 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4575 /* default to 8bpc */
4576 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4577 if (intel_crtc->config.has_dp_encoder) {
4578 if (intel_crtc->config.dither) {
4579 pipeconf |= PIPECONF_6BPC |
4580 PIPECONF_DITHER_EN |
4581 PIPECONF_DITHER_TYPE_SP;
4585 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4586 INTEL_OUTPUT_EDP)) {
4587 if (intel_crtc->config.dither) {
4588 pipeconf |= PIPECONF_6BPC |
4590 I965_PIPECONF_ACTIVE;
4594 if (HAS_PIPE_CXSR(dev)) {
4595 if (intel_crtc->lowfreq_avail) {
4596 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4597 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4599 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4600 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4604 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4605 if (!IS_GEN2(dev) &&
4606 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4607 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4609 pipeconf |= PIPECONF_PROGRESSIVE;
4611 if (IS_VALLEYVIEW(dev)) {
4612 if (intel_crtc->config.limited_color_range)
4613 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4615 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4618 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4619 POSTING_READ(PIPECONF(intel_crtc->pipe));
4622 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4624 struct drm_framebuffer *fb)
4626 struct drm_device *dev = crtc->dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4629 struct drm_display_mode *adjusted_mode =
4630 &intel_crtc->config.adjusted_mode;
4631 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4632 int pipe = intel_crtc->pipe;
4633 int plane = intel_crtc->plane;
4634 int refclk, num_connectors = 0;
4635 intel_clock_t clock, reduced_clock;
4637 bool ok, has_reduced_clock = false, is_sdvo = false;
4638 bool is_lvds = false, is_tv = false;
4639 struct intel_encoder *encoder;
4640 const intel_limit_t *limit;
4643 for_each_encoder_on_crtc(dev, crtc, encoder) {
4644 switch (encoder->type) {
4645 case INTEL_OUTPUT_LVDS:
4648 case INTEL_OUTPUT_SDVO:
4649 case INTEL_OUTPUT_HDMI:
4651 if (encoder->needs_tv_clock)
4654 case INTEL_OUTPUT_TVOUT:
4662 refclk = i9xx_get_refclk(crtc, num_connectors);
4665 * Returns a set of divisors for the desired target clock with the given
4666 * refclk, or FALSE. The returned values represent the clock equation:
4667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4669 limit = intel_limit(crtc, refclk);
4670 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4673 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4677 /* Ensure that the cursor is valid for the new mode before changing... */
4678 intel_crtc_update_cursor(crtc, true);
4680 if (is_lvds && dev_priv->lvds_downclock_avail) {
4682 * Ensure we match the reduced clock's P to the target clock.
4683 * If the clocks don't match, we can't switch the display clock
4684 * by using the FP0/FP1. In such case we will disable the LVDS
4685 * downclock feature.
4687 has_reduced_clock = limit->find_pll(limit, crtc,
4688 dev_priv->lvds_downclock,
4693 /* Compat-code for transition, will disappear. */
4694 if (!intel_crtc->config.clock_set) {
4695 intel_crtc->config.dpll.n = clock.n;
4696 intel_crtc->config.dpll.m1 = clock.m1;
4697 intel_crtc->config.dpll.m2 = clock.m2;
4698 intel_crtc->config.dpll.p1 = clock.p1;
4699 intel_crtc->config.dpll.p2 = clock.p2;
4702 if (is_sdvo && is_tv)
4703 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4706 i8xx_update_pll(intel_crtc, adjusted_mode,
4707 has_reduced_clock ? &reduced_clock : NULL,
4709 else if (IS_VALLEYVIEW(dev))
4710 vlv_update_pll(intel_crtc);
4712 i9xx_update_pll(intel_crtc,
4713 has_reduced_clock ? &reduced_clock : NULL,
4716 /* Set up the display plane register */
4717 dspcntr = DISPPLANE_GAMMA_ENABLE;
4719 if (!IS_VALLEYVIEW(dev)) {
4721 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4723 dspcntr |= DISPPLANE_SEL_PIPE_B;
4726 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4727 drm_mode_debug_printmodeline(mode);
4729 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4731 /* pipesrc and dspsize control the size that is scaled from,
4732 * which should always be the user's requested size.
4734 I915_WRITE(DSPSIZE(plane),
4735 ((mode->vdisplay - 1) << 16) |
4736 (mode->hdisplay - 1));
4737 I915_WRITE(DSPPOS(plane), 0);
4739 i9xx_set_pipeconf(intel_crtc);
4741 I915_WRITE(DSPCNTR(plane), dspcntr);
4742 POSTING_READ(DSPCNTR(plane));
4744 ret = intel_pipe_set_base(crtc, x, y, fb);
4746 intel_update_watermarks(dev);
4751 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4752 struct intel_crtc_config *pipe_config)
4754 struct drm_device *dev = crtc->base.dev;
4755 struct drm_i915_private *dev_priv = dev->dev_private;
4758 tmp = I915_READ(PIPECONF(crtc->pipe));
4759 if (!(tmp & PIPECONF_ENABLE))
4765 static void ironlake_init_pch_refclk(struct drm_device *dev)
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 struct drm_mode_config *mode_config = &dev->mode_config;
4769 struct intel_encoder *encoder;
4771 bool has_lvds = false;
4772 bool has_cpu_edp = false;
4773 bool has_pch_edp = false;
4774 bool has_panel = false;
4775 bool has_ck505 = false;
4776 bool can_ssc = false;
4778 /* We need to take the global config into account */
4779 list_for_each_entry(encoder, &mode_config->encoder_list,
4781 switch (encoder->type) {
4782 case INTEL_OUTPUT_LVDS:
4786 case INTEL_OUTPUT_EDP:
4788 if (intel_encoder_is_pch_edp(&encoder->base))
4796 if (HAS_PCH_IBX(dev)) {
4797 has_ck505 = dev_priv->display_clock_mode;
4798 can_ssc = has_ck505;
4804 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4805 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4808 /* Ironlake: try to setup display ref clock before DPLL
4809 * enabling. This is only under driver's control after
4810 * PCH B stepping, previous chipset stepping should be
4811 * ignoring this setting.
4813 val = I915_READ(PCH_DREF_CONTROL);
4815 /* As we must carefully and slowly disable/enable each source in turn,
4816 * compute the final state we want first and check if we need to
4817 * make any changes at all.
4820 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4822 final |= DREF_NONSPREAD_CK505_ENABLE;
4824 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4826 final &= ~DREF_SSC_SOURCE_MASK;
4827 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4828 final &= ~DREF_SSC1_ENABLE;
4831 final |= DREF_SSC_SOURCE_ENABLE;
4833 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4834 final |= DREF_SSC1_ENABLE;
4837 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4838 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4840 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4842 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4844 final |= DREF_SSC_SOURCE_DISABLE;
4845 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4851 /* Always enable nonspread source */
4852 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4855 val |= DREF_NONSPREAD_CK505_ENABLE;
4857 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4860 val &= ~DREF_SSC_SOURCE_MASK;
4861 val |= DREF_SSC_SOURCE_ENABLE;
4863 /* SSC must be turned on before enabling the CPU output */
4864 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4865 DRM_DEBUG_KMS("Using SSC on panel\n");
4866 val |= DREF_SSC1_ENABLE;
4868 val &= ~DREF_SSC1_ENABLE;
4870 /* Get SSC going before enabling the outputs */
4871 I915_WRITE(PCH_DREF_CONTROL, val);
4872 POSTING_READ(PCH_DREF_CONTROL);
4875 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4877 /* Enable CPU source on CPU attached eDP */
4879 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4880 DRM_DEBUG_KMS("Using SSC on eDP\n");
4881 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4884 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4886 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4888 I915_WRITE(PCH_DREF_CONTROL, val);
4889 POSTING_READ(PCH_DREF_CONTROL);
4892 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4894 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4896 /* Turn off CPU output */
4897 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4899 I915_WRITE(PCH_DREF_CONTROL, val);
4900 POSTING_READ(PCH_DREF_CONTROL);
4903 /* Turn off the SSC source */
4904 val &= ~DREF_SSC_SOURCE_MASK;
4905 val |= DREF_SSC_SOURCE_DISABLE;
4908 val &= ~DREF_SSC1_ENABLE;
4910 I915_WRITE(PCH_DREF_CONTROL, val);
4911 POSTING_READ(PCH_DREF_CONTROL);
4915 BUG_ON(val != final);
4918 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4919 static void lpt_init_pch_refclk(struct drm_device *dev)
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct drm_mode_config *mode_config = &dev->mode_config;
4923 struct intel_encoder *encoder;
4924 bool has_vga = false;
4925 bool is_sdv = false;
4928 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4929 switch (encoder->type) {
4930 case INTEL_OUTPUT_ANALOG:
4939 mutex_lock(&dev_priv->dpio_lock);
4941 /* XXX: Rip out SDV support once Haswell ships for real. */
4942 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4945 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4946 tmp &= ~SBI_SSCCTL_DISABLE;
4947 tmp |= SBI_SSCCTL_PATHALT;
4948 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4952 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4953 tmp &= ~SBI_SSCCTL_PATHALT;
4954 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4957 tmp = I915_READ(SOUTH_CHICKEN2);
4958 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4959 I915_WRITE(SOUTH_CHICKEN2, tmp);
4961 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4962 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4963 DRM_ERROR("FDI mPHY reset assert timeout\n");
4965 tmp = I915_READ(SOUTH_CHICKEN2);
4966 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4967 I915_WRITE(SOUTH_CHICKEN2, tmp);
4969 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4970 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4972 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4975 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4976 tmp &= ~(0xFF << 24);
4977 tmp |= (0x12 << 24);
4978 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4981 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4983 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4986 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4988 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4990 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4992 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4995 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4996 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4997 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4999 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5000 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5001 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5003 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5005 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5007 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5009 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5012 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5013 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5014 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5016 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5017 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5018 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5021 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5024 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5026 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5029 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5032 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5035 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5037 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5040 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5042 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5043 tmp &= ~(0xFF << 16);
5044 tmp |= (0x1C << 16);
5045 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5047 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5048 tmp &= ~(0xFF << 16);
5049 tmp |= (0x1C << 16);
5050 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5053 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5055 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5057 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5059 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5061 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5062 tmp &= ~(0xF << 28);
5064 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5066 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5067 tmp &= ~(0xF << 28);
5069 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5072 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5073 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5074 tmp |= SBI_DBUFF0_ENABLE;
5075 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5077 mutex_unlock(&dev_priv->dpio_lock);
5081 * Initialize reference clocks when the driver loads
5083 void intel_init_pch_refclk(struct drm_device *dev)
5085 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5086 ironlake_init_pch_refclk(dev);
5087 else if (HAS_PCH_LPT(dev))
5088 lpt_init_pch_refclk(dev);
5091 static int ironlake_get_refclk(struct drm_crtc *crtc)
5093 struct drm_device *dev = crtc->dev;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 struct intel_encoder *encoder;
5096 struct intel_encoder *edp_encoder = NULL;
5097 int num_connectors = 0;
5098 bool is_lvds = false;
5100 for_each_encoder_on_crtc(dev, crtc, encoder) {
5101 switch (encoder->type) {
5102 case INTEL_OUTPUT_LVDS:
5105 case INTEL_OUTPUT_EDP:
5106 edp_encoder = encoder;
5112 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5113 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5114 dev_priv->lvds_ssc_freq);
5115 return dev_priv->lvds_ssc_freq * 1000;
5121 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5122 struct drm_display_mode *adjusted_mode,
5125 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5127 int pipe = intel_crtc->pipe;
5130 val = I915_READ(PIPECONF(pipe));
5132 val &= ~PIPECONF_BPC_MASK;
5133 switch (intel_crtc->config.pipe_bpp) {
5135 val |= PIPECONF_6BPC;
5138 val |= PIPECONF_8BPC;
5141 val |= PIPECONF_10BPC;
5144 val |= PIPECONF_12BPC;
5147 /* Case prevented by intel_choose_pipe_bpp_dither. */
5151 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5153 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5155 val &= ~PIPECONF_INTERLACE_MASK;
5156 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5157 val |= PIPECONF_INTERLACED_ILK;
5159 val |= PIPECONF_PROGRESSIVE;
5161 if (intel_crtc->config.limited_color_range)
5162 val |= PIPECONF_COLOR_RANGE_SELECT;
5164 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5166 I915_WRITE(PIPECONF(pipe), val);
5167 POSTING_READ(PIPECONF(pipe));
5171 * Set up the pipe CSC unit.
5173 * Currently only full range RGB to limited range RGB conversion
5174 * is supported, but eventually this should handle various
5175 * RGB<->YCbCr scenarios as well.
5177 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5179 struct drm_device *dev = crtc->dev;
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5182 int pipe = intel_crtc->pipe;
5183 uint16_t coeff = 0x7800; /* 1.0 */
5186 * TODO: Check what kind of values actually come out of the pipe
5187 * with these coeff/postoff values and adjust to get the best
5188 * accuracy. Perhaps we even need to take the bpc value into
5192 if (intel_crtc->config.limited_color_range)
5193 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5196 * GY/GU and RY/RU should be the other way around according
5197 * to BSpec, but reality doesn't agree. Just set them up in
5198 * a way that results in the correct picture.
5200 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5201 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5203 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5204 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5206 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5207 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5209 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5210 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5211 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5213 if (INTEL_INFO(dev)->gen > 6) {
5214 uint16_t postoff = 0;
5216 if (intel_crtc->config.limited_color_range)
5217 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5219 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5220 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5221 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5223 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5225 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5227 if (intel_crtc->config.limited_color_range)
5228 mode |= CSC_BLACK_SCREEN_OFFSET;
5230 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5234 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5235 struct drm_display_mode *adjusted_mode,
5238 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5240 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5243 val = I915_READ(PIPECONF(cpu_transcoder));
5245 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5247 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5249 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5250 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5251 val |= PIPECONF_INTERLACED_ILK;
5253 val |= PIPECONF_PROGRESSIVE;
5255 I915_WRITE(PIPECONF(cpu_transcoder), val);
5256 POSTING_READ(PIPECONF(cpu_transcoder));
5259 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5260 struct drm_display_mode *adjusted_mode,
5261 intel_clock_t *clock,
5262 bool *has_reduced_clock,
5263 intel_clock_t *reduced_clock)
5265 struct drm_device *dev = crtc->dev;
5266 struct drm_i915_private *dev_priv = dev->dev_private;
5267 struct intel_encoder *intel_encoder;
5269 const intel_limit_t *limit;
5270 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5272 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5273 switch (intel_encoder->type) {
5274 case INTEL_OUTPUT_LVDS:
5277 case INTEL_OUTPUT_SDVO:
5278 case INTEL_OUTPUT_HDMI:
5280 if (intel_encoder->needs_tv_clock)
5283 case INTEL_OUTPUT_TVOUT:
5289 refclk = ironlake_get_refclk(crtc);
5292 * Returns a set of divisors for the desired target clock with the given
5293 * refclk, or FALSE. The returned values represent the clock equation:
5294 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5296 limit = intel_limit(crtc, refclk);
5297 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5302 if (is_lvds && dev_priv->lvds_downclock_avail) {
5304 * Ensure we match the reduced clock's P to the target clock.
5305 * If the clocks don't match, we can't switch the display clock
5306 * by using the FP0/FP1. In such case we will disable the LVDS
5307 * downclock feature.
5309 *has_reduced_clock = limit->find_pll(limit, crtc,
5310 dev_priv->lvds_downclock,
5316 if (is_sdvo && is_tv)
5317 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5322 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5327 temp = I915_READ(SOUTH_CHICKEN1);
5328 if (temp & FDI_BC_BIFURCATION_SELECT)
5331 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5332 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5334 temp |= FDI_BC_BIFURCATION_SELECT;
5335 DRM_DEBUG_KMS("enabling fdi C rx\n");
5336 I915_WRITE(SOUTH_CHICKEN1, temp);
5337 POSTING_READ(SOUTH_CHICKEN1);
5340 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5342 struct drm_device *dev = intel_crtc->base.dev;
5343 struct drm_i915_private *dev_priv = dev->dev_private;
5344 struct intel_crtc *pipe_B_crtc =
5345 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5347 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5348 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5349 if (intel_crtc->fdi_lanes > 4) {
5350 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5351 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5352 /* Clamp lanes to avoid programming the hw with bogus values. */
5353 intel_crtc->fdi_lanes = 4;
5358 if (INTEL_INFO(dev)->num_pipes == 2)
5361 switch (intel_crtc->pipe) {
5365 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5366 intel_crtc->fdi_lanes > 2) {
5367 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5368 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5369 /* Clamp lanes to avoid programming the hw with bogus values. */
5370 intel_crtc->fdi_lanes = 2;
5375 if (intel_crtc->fdi_lanes > 2)
5376 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5378 cpt_enable_fdi_bc_bifurcation(dev);
5382 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5383 if (intel_crtc->fdi_lanes > 2) {
5384 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5385 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5386 /* Clamp lanes to avoid programming the hw with bogus values. */
5387 intel_crtc->fdi_lanes = 2;
5392 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5396 cpt_enable_fdi_bc_bifurcation(dev);
5404 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5407 * Account for spread spectrum to avoid
5408 * oversubscribing the link. Max center spread
5409 * is 2.5%; use 5% for safety's sake.
5411 u32 bps = target_clock * bpp * 21 / 20;
5412 return bps / (link_bw * 8) + 1;
5415 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5416 struct intel_link_m_n *m_n)
5418 struct drm_device *dev = crtc->base.dev;
5419 struct drm_i915_private *dev_priv = dev->dev_private;
5420 int pipe = crtc->pipe;
5422 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5423 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5424 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5425 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5428 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5429 struct intel_link_m_n *m_n)
5431 struct drm_device *dev = crtc->base.dev;
5432 struct drm_i915_private *dev_priv = dev->dev_private;
5433 int pipe = crtc->pipe;
5434 enum transcoder transcoder = crtc->config.cpu_transcoder;
5436 if (INTEL_INFO(dev)->gen >= 5) {
5437 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5438 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5439 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5440 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5442 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5443 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5444 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5445 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5449 static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5451 struct drm_device *dev = crtc->dev;
5452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5453 struct drm_display_mode *adjusted_mode =
5454 &intel_crtc->config.adjusted_mode;
5455 struct intel_link_m_n m_n = {0};
5456 int target_clock, lane, link_bw;
5458 /* FDI is a binary signal running at ~2.7GHz, encoding
5459 * each output octet as 10 bits. The actual frequency
5460 * is stored as a divider into a 100MHz clock, and the
5461 * mode pixel clock is stored in units of 1KHz.
5462 * Hence the bw of each lane in terms of the mode signal
5465 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5467 if (intel_crtc->config.pixel_target_clock)
5468 target_clock = intel_crtc->config.pixel_target_clock;
5470 target_clock = adjusted_mode->clock;
5472 lane = ironlake_get_lanes_required(target_clock, link_bw,
5473 intel_crtc->config.pipe_bpp);
5475 intel_crtc->fdi_lanes = lane;
5477 if (intel_crtc->config.pixel_multiplier > 1)
5478 link_bw *= intel_crtc->config.pixel_multiplier;
5479 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5482 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5485 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5486 intel_clock_t *clock, u32 *fp,
5487 intel_clock_t *reduced_clock, u32 *fp2)
5489 struct drm_crtc *crtc = &intel_crtc->base;
5490 struct drm_device *dev = crtc->dev;
5491 struct drm_i915_private *dev_priv = dev->dev_private;
5492 struct intel_encoder *intel_encoder;
5494 int factor, num_connectors = 0;
5495 bool is_lvds = false, is_sdvo = false, is_tv = false;
5497 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5498 switch (intel_encoder->type) {
5499 case INTEL_OUTPUT_LVDS:
5502 case INTEL_OUTPUT_SDVO:
5503 case INTEL_OUTPUT_HDMI:
5505 if (intel_encoder->needs_tv_clock)
5508 case INTEL_OUTPUT_TVOUT:
5516 /* Enable autotuning of the PLL clock (if permissible) */
5519 if ((intel_panel_use_ssc(dev_priv) &&
5520 dev_priv->lvds_ssc_freq == 100) ||
5521 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5523 } else if (is_sdvo && is_tv)
5526 if (clock->m < factor * clock->n)
5529 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5535 dpll |= DPLLB_MODE_LVDS;
5537 dpll |= DPLLB_MODE_DAC_SERIAL;
5539 if (intel_crtc->config.pixel_multiplier > 1) {
5540 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5541 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5543 dpll |= DPLL_DVO_HIGH_SPEED;
5545 if (intel_crtc->config.has_dp_encoder &&
5546 intel_crtc->config.has_pch_encoder)
5547 dpll |= DPLL_DVO_HIGH_SPEED;
5549 /* compute bitmask from p1 value */
5550 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5554 switch (clock->p2) {
5556 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5559 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5562 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5565 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5569 if (is_sdvo && is_tv)
5570 dpll |= PLL_REF_INPUT_TVCLKINBC;
5572 /* XXX: just matching BIOS for now */
5573 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5575 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5576 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5578 dpll |= PLL_REF_INPUT_DREFCLK;
5583 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5585 struct drm_framebuffer *fb)
5587 struct drm_device *dev = crtc->dev;
5588 struct drm_i915_private *dev_priv = dev->dev_private;
5589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5590 struct drm_display_mode *adjusted_mode =
5591 &intel_crtc->config.adjusted_mode;
5592 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5593 int pipe = intel_crtc->pipe;
5594 int plane = intel_crtc->plane;
5595 int num_connectors = 0;
5596 intel_clock_t clock, reduced_clock;
5597 u32 dpll, fp = 0, fp2 = 0;
5598 bool ok, has_reduced_clock = false;
5599 bool is_lvds = false;
5600 struct intel_encoder *encoder;
5602 bool dither, fdi_config_ok;
5604 for_each_encoder_on_crtc(dev, crtc, encoder) {
5605 switch (encoder->type) {
5606 case INTEL_OUTPUT_LVDS:
5614 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5615 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5617 intel_crtc->config.cpu_transcoder = pipe;
5619 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5620 &has_reduced_clock, &reduced_clock);
5622 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5625 /* Compat-code for transition, will disappear. */
5626 if (!intel_crtc->config.clock_set) {
5627 intel_crtc->config.dpll.n = clock.n;
5628 intel_crtc->config.dpll.m1 = clock.m1;
5629 intel_crtc->config.dpll.m2 = clock.m2;
5630 intel_crtc->config.dpll.p1 = clock.p1;
5631 intel_crtc->config.dpll.p2 = clock.p2;
5634 /* Ensure that the cursor is valid for the new mode before changing... */
5635 intel_crtc_update_cursor(crtc, true);
5637 /* determine panel color depth */
5638 dither = intel_crtc->config.dither;
5639 if (is_lvds && dev_priv->lvds_dither)
5642 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5643 if (has_reduced_clock)
5644 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5647 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5648 has_reduced_clock ? &fp2 : NULL);
5650 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5651 drm_mode_debug_printmodeline(mode);
5653 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5654 if (intel_crtc->config.has_pch_encoder) {
5655 struct intel_pch_pll *pll;
5657 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5659 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5664 intel_put_pch_pll(intel_crtc);
5666 if (intel_crtc->config.has_dp_encoder)
5667 intel_dp_set_m_n(intel_crtc);
5669 for_each_encoder_on_crtc(dev, crtc, encoder)
5670 if (encoder->pre_pll_enable)
5671 encoder->pre_pll_enable(encoder);
5673 if (intel_crtc->pch_pll) {
5674 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5676 /* Wait for the clocks to stabilize. */
5677 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5680 /* The pixel multiplier can only be updated once the
5681 * DPLL is enabled and the clocks are stable.
5683 * So write it again.
5685 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5688 intel_crtc->lowfreq_avail = false;
5689 if (intel_crtc->pch_pll) {
5690 if (is_lvds && has_reduced_clock && i915_powersave) {
5691 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5692 intel_crtc->lowfreq_avail = true;
5694 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5698 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5700 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5701 * ironlake_check_fdi_lanes. */
5702 intel_crtc->fdi_lanes = 0;
5703 if (intel_crtc->config.has_pch_encoder)
5704 ironlake_fdi_set_m_n(crtc);
5706 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5708 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5710 /* Set up the display plane register */
5711 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5712 POSTING_READ(DSPCNTR(plane));
5714 ret = intel_pipe_set_base(crtc, x, y, fb);
5716 intel_update_watermarks(dev);
5718 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5720 return fdi_config_ok ? ret : -EINVAL;
5723 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5724 struct intel_crtc_config *pipe_config)
5726 struct drm_device *dev = crtc->base.dev;
5727 struct drm_i915_private *dev_priv = dev->dev_private;
5730 tmp = I915_READ(PIPECONF(crtc->pipe));
5731 if (!(tmp & PIPECONF_ENABLE))
5734 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5735 pipe_config->has_pch_encoder = true;
5740 static void haswell_modeset_global_resources(struct drm_device *dev)
5742 struct drm_i915_private *dev_priv = dev->dev_private;
5743 bool enable = false;
5744 struct intel_crtc *crtc;
5745 struct intel_encoder *encoder;
5747 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5748 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5750 /* XXX: Should check for edp transcoder here, but thanks to init
5751 * sequence that's not yet available. Just in case desktop eDP
5752 * on PORT D is possible on haswell, too. */
5755 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5757 if (encoder->type != INTEL_OUTPUT_EDP &&
5758 encoder->connectors_active)
5762 /* Even the eDP panel fitter is outside the always-on well. */
5763 if (dev_priv->pch_pf_size)
5766 intel_set_power_well(dev, enable);
5769 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5771 struct drm_framebuffer *fb)
5773 struct drm_device *dev = crtc->dev;
5774 struct drm_i915_private *dev_priv = dev->dev_private;
5775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5776 struct drm_display_mode *adjusted_mode =
5777 &intel_crtc->config.adjusted_mode;
5778 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5779 int pipe = intel_crtc->pipe;
5780 int plane = intel_crtc->plane;
5781 int num_connectors = 0;
5782 bool is_cpu_edp = false;
5783 struct intel_encoder *encoder;
5787 for_each_encoder_on_crtc(dev, crtc, encoder) {
5788 switch (encoder->type) {
5789 case INTEL_OUTPUT_EDP:
5790 if (!intel_encoder_is_pch_edp(&encoder->base))
5799 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5801 intel_crtc->config.cpu_transcoder = pipe;
5803 /* We are not sure yet this won't happen. */
5804 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5805 INTEL_PCH_TYPE(dev));
5807 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5808 num_connectors, pipe_name(pipe));
5810 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5811 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5813 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5815 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5818 /* Ensure that the cursor is valid for the new mode before changing... */
5819 intel_crtc_update_cursor(crtc, true);
5821 /* determine panel color depth */
5822 dither = intel_crtc->config.dither;
5824 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5825 drm_mode_debug_printmodeline(mode);
5827 if (intel_crtc->config.has_dp_encoder)
5828 intel_dp_set_m_n(intel_crtc);
5830 intel_crtc->lowfreq_avail = false;
5832 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5834 if (intel_crtc->config.has_pch_encoder)
5835 ironlake_fdi_set_m_n(crtc);
5837 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5839 intel_set_pipe_csc(crtc);
5841 /* Set up the display plane register */
5842 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5843 POSTING_READ(DSPCNTR(plane));
5845 ret = intel_pipe_set_base(crtc, x, y, fb);
5847 intel_update_watermarks(dev);
5849 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5854 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5855 struct intel_crtc_config *pipe_config)
5857 struct drm_device *dev = crtc->base.dev;
5858 struct drm_i915_private *dev_priv = dev->dev_private;
5861 tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder));
5862 if (!(tmp & PIPECONF_ENABLE))
5866 * aswell has only FDI/PCH transcoder A. It is which is connected to
5867 * DDI E. So just check whether this pipe is wired to DDI E and whether
5868 * the PCH transcoder is on.
5870 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5871 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5872 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5873 pipe_config->has_pch_encoder = true;
5879 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5881 struct drm_framebuffer *fb)
5883 struct drm_device *dev = crtc->dev;
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885 struct drm_encoder_helper_funcs *encoder_funcs;
5886 struct intel_encoder *encoder;
5887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5888 struct drm_display_mode *adjusted_mode =
5889 &intel_crtc->config.adjusted_mode;
5890 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5891 int pipe = intel_crtc->pipe;
5894 drm_vblank_pre_modeset(dev, pipe);
5896 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5898 drm_vblank_post_modeset(dev, pipe);
5903 for_each_encoder_on_crtc(dev, crtc, encoder) {
5904 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5905 encoder->base.base.id,
5906 drm_get_encoder_name(&encoder->base),
5907 mode->base.id, mode->name);
5908 if (encoder->mode_set) {
5909 encoder->mode_set(encoder);
5911 encoder_funcs = encoder->base.helper_private;
5912 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5919 static bool intel_eld_uptodate(struct drm_connector *connector,
5920 int reg_eldv, uint32_t bits_eldv,
5921 int reg_elda, uint32_t bits_elda,
5924 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5925 uint8_t *eld = connector->eld;
5928 i = I915_READ(reg_eldv);
5937 i = I915_READ(reg_elda);
5939 I915_WRITE(reg_elda, i);
5941 for (i = 0; i < eld[2]; i++)
5942 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5948 static void g4x_write_eld(struct drm_connector *connector,
5949 struct drm_crtc *crtc)
5951 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5952 uint8_t *eld = connector->eld;
5957 i = I915_READ(G4X_AUD_VID_DID);
5959 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5960 eldv = G4X_ELDV_DEVCL_DEVBLC;
5962 eldv = G4X_ELDV_DEVCTG;
5964 if (intel_eld_uptodate(connector,
5965 G4X_AUD_CNTL_ST, eldv,
5966 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5967 G4X_HDMIW_HDMIEDID))
5970 i = I915_READ(G4X_AUD_CNTL_ST);
5971 i &= ~(eldv | G4X_ELD_ADDR);
5972 len = (i >> 9) & 0x1f; /* ELD buffer size */
5973 I915_WRITE(G4X_AUD_CNTL_ST, i);
5978 len = min_t(uint8_t, eld[2], len);
5979 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5980 for (i = 0; i < len; i++)
5981 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5983 i = I915_READ(G4X_AUD_CNTL_ST);
5985 I915_WRITE(G4X_AUD_CNTL_ST, i);
5988 static void haswell_write_eld(struct drm_connector *connector,
5989 struct drm_crtc *crtc)
5991 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5992 uint8_t *eld = connector->eld;
5993 struct drm_device *dev = crtc->dev;
5994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5998 int pipe = to_intel_crtc(crtc)->pipe;
6001 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6002 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6003 int aud_config = HSW_AUD_CFG(pipe);
6004 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6007 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6009 /* Audio output enable */
6010 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6011 tmp = I915_READ(aud_cntrl_st2);
6012 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6013 I915_WRITE(aud_cntrl_st2, tmp);
6015 /* Wait for 1 vertical blank */
6016 intel_wait_for_vblank(dev, pipe);
6018 /* Set ELD valid state */
6019 tmp = I915_READ(aud_cntrl_st2);
6020 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6021 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6022 I915_WRITE(aud_cntrl_st2, tmp);
6023 tmp = I915_READ(aud_cntrl_st2);
6024 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6026 /* Enable HDMI mode */
6027 tmp = I915_READ(aud_config);
6028 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6029 /* clear N_programing_enable and N_value_index */
6030 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6031 I915_WRITE(aud_config, tmp);
6033 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6035 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6036 intel_crtc->eld_vld = true;
6038 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6039 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6040 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6041 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6043 I915_WRITE(aud_config, 0);
6045 if (intel_eld_uptodate(connector,
6046 aud_cntrl_st2, eldv,
6047 aud_cntl_st, IBX_ELD_ADDRESS,
6051 i = I915_READ(aud_cntrl_st2);
6053 I915_WRITE(aud_cntrl_st2, i);
6058 i = I915_READ(aud_cntl_st);
6059 i &= ~IBX_ELD_ADDRESS;
6060 I915_WRITE(aud_cntl_st, i);
6061 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6062 DRM_DEBUG_DRIVER("port num:%d\n", i);
6064 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6065 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6066 for (i = 0; i < len; i++)
6067 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6069 i = I915_READ(aud_cntrl_st2);
6071 I915_WRITE(aud_cntrl_st2, i);
6075 static void ironlake_write_eld(struct drm_connector *connector,
6076 struct drm_crtc *crtc)
6078 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6079 uint8_t *eld = connector->eld;
6087 int pipe = to_intel_crtc(crtc)->pipe;
6089 if (HAS_PCH_IBX(connector->dev)) {
6090 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6091 aud_config = IBX_AUD_CFG(pipe);
6092 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6093 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6095 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6096 aud_config = CPT_AUD_CFG(pipe);
6097 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6098 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6101 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6103 i = I915_READ(aud_cntl_st);
6104 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6106 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6107 /* operate blindly on all ports */
6108 eldv = IBX_ELD_VALIDB;
6109 eldv |= IBX_ELD_VALIDB << 4;
6110 eldv |= IBX_ELD_VALIDB << 8;
6112 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6113 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6116 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6117 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6118 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6119 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6121 I915_WRITE(aud_config, 0);
6123 if (intel_eld_uptodate(connector,
6124 aud_cntrl_st2, eldv,
6125 aud_cntl_st, IBX_ELD_ADDRESS,
6129 i = I915_READ(aud_cntrl_st2);
6131 I915_WRITE(aud_cntrl_st2, i);
6136 i = I915_READ(aud_cntl_st);
6137 i &= ~IBX_ELD_ADDRESS;
6138 I915_WRITE(aud_cntl_st, i);
6140 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6141 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6142 for (i = 0; i < len; i++)
6143 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6145 i = I915_READ(aud_cntrl_st2);
6147 I915_WRITE(aud_cntrl_st2, i);
6150 void intel_write_eld(struct drm_encoder *encoder,
6151 struct drm_display_mode *mode)
6153 struct drm_crtc *crtc = encoder->crtc;
6154 struct drm_connector *connector;
6155 struct drm_device *dev = encoder->dev;
6156 struct drm_i915_private *dev_priv = dev->dev_private;
6158 connector = drm_select_eld(encoder, mode);
6162 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6164 drm_get_connector_name(connector),
6165 connector->encoder->base.id,
6166 drm_get_encoder_name(connector->encoder));
6168 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6170 if (dev_priv->display.write_eld)
6171 dev_priv->display.write_eld(connector, crtc);
6174 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6175 void intel_crtc_load_lut(struct drm_crtc *crtc)
6177 struct drm_device *dev = crtc->dev;
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 int palreg = PALETTE(intel_crtc->pipe);
6183 /* The clocks have to be on to load the palette. */
6184 if (!crtc->enabled || !intel_crtc->active)
6187 /* use legacy palette for Ironlake */
6188 if (HAS_PCH_SPLIT(dev))
6189 palreg = LGC_PALETTE(intel_crtc->pipe);
6191 for (i = 0; i < 256; i++) {
6192 I915_WRITE(palreg + 4 * i,
6193 (intel_crtc->lut_r[i] << 16) |
6194 (intel_crtc->lut_g[i] << 8) |
6195 intel_crtc->lut_b[i]);
6199 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6201 struct drm_device *dev = crtc->dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6204 bool visible = base != 0;
6207 if (intel_crtc->cursor_visible == visible)
6210 cntl = I915_READ(_CURACNTR);
6212 /* On these chipsets we can only modify the base whilst
6213 * the cursor is disabled.
6215 I915_WRITE(_CURABASE, base);
6217 cntl &= ~(CURSOR_FORMAT_MASK);
6218 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6219 cntl |= CURSOR_ENABLE |
6220 CURSOR_GAMMA_ENABLE |
6223 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6224 I915_WRITE(_CURACNTR, cntl);
6226 intel_crtc->cursor_visible = visible;
6229 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6231 struct drm_device *dev = crtc->dev;
6232 struct drm_i915_private *dev_priv = dev->dev_private;
6233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6234 int pipe = intel_crtc->pipe;
6235 bool visible = base != 0;
6237 if (intel_crtc->cursor_visible != visible) {
6238 uint32_t cntl = I915_READ(CURCNTR(pipe));
6240 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6241 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6242 cntl |= pipe << 28; /* Connect to correct pipe */
6244 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6245 cntl |= CURSOR_MODE_DISABLE;
6247 I915_WRITE(CURCNTR(pipe), cntl);
6249 intel_crtc->cursor_visible = visible;
6251 /* and commit changes on next vblank */
6252 I915_WRITE(CURBASE(pipe), base);
6255 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6257 struct drm_device *dev = crtc->dev;
6258 struct drm_i915_private *dev_priv = dev->dev_private;
6259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6260 int pipe = intel_crtc->pipe;
6261 bool visible = base != 0;
6263 if (intel_crtc->cursor_visible != visible) {
6264 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6266 cntl &= ~CURSOR_MODE;
6267 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6269 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6270 cntl |= CURSOR_MODE_DISABLE;
6272 if (IS_HASWELL(dev))
6273 cntl |= CURSOR_PIPE_CSC_ENABLE;
6274 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6276 intel_crtc->cursor_visible = visible;
6278 /* and commit changes on next vblank */
6279 I915_WRITE(CURBASE_IVB(pipe), base);
6282 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6283 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6286 struct drm_device *dev = crtc->dev;
6287 struct drm_i915_private *dev_priv = dev->dev_private;
6288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6289 int pipe = intel_crtc->pipe;
6290 int x = intel_crtc->cursor_x;
6291 int y = intel_crtc->cursor_y;
6297 if (on && crtc->enabled && crtc->fb) {
6298 base = intel_crtc->cursor_addr;
6299 if (x > (int) crtc->fb->width)
6302 if (y > (int) crtc->fb->height)
6308 if (x + intel_crtc->cursor_width < 0)
6311 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6314 pos |= x << CURSOR_X_SHIFT;
6317 if (y + intel_crtc->cursor_height < 0)
6320 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6323 pos |= y << CURSOR_Y_SHIFT;
6325 visible = base != 0;
6326 if (!visible && !intel_crtc->cursor_visible)
6329 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6330 I915_WRITE(CURPOS_IVB(pipe), pos);
6331 ivb_update_cursor(crtc, base);
6333 I915_WRITE(CURPOS(pipe), pos);
6334 if (IS_845G(dev) || IS_I865G(dev))
6335 i845_update_cursor(crtc, base);
6337 i9xx_update_cursor(crtc, base);
6341 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6342 struct drm_file *file,
6344 uint32_t width, uint32_t height)
6346 struct drm_device *dev = crtc->dev;
6347 struct drm_i915_private *dev_priv = dev->dev_private;
6348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6349 struct drm_i915_gem_object *obj;
6353 /* if we want to turn off the cursor ignore width and height */
6355 DRM_DEBUG_KMS("cursor off\n");
6358 mutex_lock(&dev->struct_mutex);
6362 /* Currently we only support 64x64 cursors */
6363 if (width != 64 || height != 64) {
6364 DRM_ERROR("we currently only support 64x64 cursors\n");
6368 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6369 if (&obj->base == NULL)
6372 if (obj->base.size < width * height * 4) {
6373 DRM_ERROR("buffer is to small\n");
6378 /* we only need to pin inside GTT if cursor is non-phy */
6379 mutex_lock(&dev->struct_mutex);
6380 if (!dev_priv->info->cursor_needs_physical) {
6383 if (obj->tiling_mode) {
6384 DRM_ERROR("cursor cannot be tiled\n");
6389 /* Note that the w/a also requires 2 PTE of padding following
6390 * the bo. We currently fill all unused PTE with the shadow
6391 * page and so we should always have valid PTE following the
6392 * cursor preventing the VT-d warning.
6395 if (need_vtd_wa(dev))
6396 alignment = 64*1024;
6398 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6400 DRM_ERROR("failed to move cursor bo into the GTT\n");
6404 ret = i915_gem_object_put_fence(obj);
6406 DRM_ERROR("failed to release fence for cursor");
6410 addr = obj->gtt_offset;
6412 int align = IS_I830(dev) ? 16 * 1024 : 256;
6413 ret = i915_gem_attach_phys_object(dev, obj,
6414 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6417 DRM_ERROR("failed to attach phys object\n");
6420 addr = obj->phys_obj->handle->busaddr;
6424 I915_WRITE(CURSIZE, (height << 12) | width);
6427 if (intel_crtc->cursor_bo) {
6428 if (dev_priv->info->cursor_needs_physical) {
6429 if (intel_crtc->cursor_bo != obj)
6430 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6432 i915_gem_object_unpin(intel_crtc->cursor_bo);
6433 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6436 mutex_unlock(&dev->struct_mutex);
6438 intel_crtc->cursor_addr = addr;
6439 intel_crtc->cursor_bo = obj;
6440 intel_crtc->cursor_width = width;
6441 intel_crtc->cursor_height = height;
6443 intel_crtc_update_cursor(crtc, true);
6447 i915_gem_object_unpin(obj);
6449 mutex_unlock(&dev->struct_mutex);
6451 drm_gem_object_unreference_unlocked(&obj->base);
6455 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6459 intel_crtc->cursor_x = x;
6460 intel_crtc->cursor_y = y;
6462 intel_crtc_update_cursor(crtc, true);
6467 /** Sets the color ramps on behalf of RandR */
6468 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6469 u16 blue, int regno)
6471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6473 intel_crtc->lut_r[regno] = red >> 8;
6474 intel_crtc->lut_g[regno] = green >> 8;
6475 intel_crtc->lut_b[regno] = blue >> 8;
6478 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6479 u16 *blue, int regno)
6481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6483 *red = intel_crtc->lut_r[regno] << 8;
6484 *green = intel_crtc->lut_g[regno] << 8;
6485 *blue = intel_crtc->lut_b[regno] << 8;
6488 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6489 u16 *blue, uint32_t start, uint32_t size)
6491 int end = (start + size > 256) ? 256 : start + size, i;
6492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6494 for (i = start; i < end; i++) {
6495 intel_crtc->lut_r[i] = red[i] >> 8;
6496 intel_crtc->lut_g[i] = green[i] >> 8;
6497 intel_crtc->lut_b[i] = blue[i] >> 8;
6500 intel_crtc_load_lut(crtc);
6503 /* VESA 640x480x72Hz mode to set on the pipe */
6504 static struct drm_display_mode load_detect_mode = {
6505 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6506 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6509 static struct drm_framebuffer *
6510 intel_framebuffer_create(struct drm_device *dev,
6511 struct drm_mode_fb_cmd2 *mode_cmd,
6512 struct drm_i915_gem_object *obj)
6514 struct intel_framebuffer *intel_fb;
6517 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6519 drm_gem_object_unreference_unlocked(&obj->base);
6520 return ERR_PTR(-ENOMEM);
6523 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6525 drm_gem_object_unreference_unlocked(&obj->base);
6527 return ERR_PTR(ret);
6530 return &intel_fb->base;
6534 intel_framebuffer_pitch_for_width(int width, int bpp)
6536 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6537 return ALIGN(pitch, 64);
6541 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6543 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6544 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6547 static struct drm_framebuffer *
6548 intel_framebuffer_create_for_mode(struct drm_device *dev,
6549 struct drm_display_mode *mode,
6552 struct drm_i915_gem_object *obj;
6553 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6555 obj = i915_gem_alloc_object(dev,
6556 intel_framebuffer_size_for_mode(mode, bpp));
6558 return ERR_PTR(-ENOMEM);
6560 mode_cmd.width = mode->hdisplay;
6561 mode_cmd.height = mode->vdisplay;
6562 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6564 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6566 return intel_framebuffer_create(dev, &mode_cmd, obj);
6569 static struct drm_framebuffer *
6570 mode_fits_in_fbdev(struct drm_device *dev,
6571 struct drm_display_mode *mode)
6573 struct drm_i915_private *dev_priv = dev->dev_private;
6574 struct drm_i915_gem_object *obj;
6575 struct drm_framebuffer *fb;
6577 if (dev_priv->fbdev == NULL)
6580 obj = dev_priv->fbdev->ifb.obj;
6584 fb = &dev_priv->fbdev->ifb.base;
6585 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6586 fb->bits_per_pixel))
6589 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6595 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6596 struct drm_display_mode *mode,
6597 struct intel_load_detect_pipe *old)
6599 struct intel_crtc *intel_crtc;
6600 struct intel_encoder *intel_encoder =
6601 intel_attached_encoder(connector);
6602 struct drm_crtc *possible_crtc;
6603 struct drm_encoder *encoder = &intel_encoder->base;
6604 struct drm_crtc *crtc = NULL;
6605 struct drm_device *dev = encoder->dev;
6606 struct drm_framebuffer *fb;
6609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6610 connector->base.id, drm_get_connector_name(connector),
6611 encoder->base.id, drm_get_encoder_name(encoder));
6614 * Algorithm gets a little messy:
6616 * - if the connector already has an assigned crtc, use it (but make
6617 * sure it's on first)
6619 * - try to find the first unused crtc that can drive this connector,
6620 * and use that if we find one
6623 /* See if we already have a CRTC for this connector */
6624 if (encoder->crtc) {
6625 crtc = encoder->crtc;
6627 mutex_lock(&crtc->mutex);
6629 old->dpms_mode = connector->dpms;
6630 old->load_detect_temp = false;
6632 /* Make sure the crtc and connector are running */
6633 if (connector->dpms != DRM_MODE_DPMS_ON)
6634 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6639 /* Find an unused one (if possible) */
6640 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6642 if (!(encoder->possible_crtcs & (1 << i)))
6644 if (!possible_crtc->enabled) {
6645 crtc = possible_crtc;
6651 * If we didn't find an unused CRTC, don't use any.
6654 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6658 mutex_lock(&crtc->mutex);
6659 intel_encoder->new_crtc = to_intel_crtc(crtc);
6660 to_intel_connector(connector)->new_encoder = intel_encoder;
6662 intel_crtc = to_intel_crtc(crtc);
6663 old->dpms_mode = connector->dpms;
6664 old->load_detect_temp = true;
6665 old->release_fb = NULL;
6668 mode = &load_detect_mode;
6670 /* We need a framebuffer large enough to accommodate all accesses
6671 * that the plane may generate whilst we perform load detection.
6672 * We can not rely on the fbcon either being present (we get called
6673 * during its initialisation to detect all boot displays, or it may
6674 * not even exist) or that it is large enough to satisfy the
6677 fb = mode_fits_in_fbdev(dev, mode);
6679 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6680 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6681 old->release_fb = fb;
6683 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6685 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6686 mutex_unlock(&crtc->mutex);
6690 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6691 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6692 if (old->release_fb)
6693 old->release_fb->funcs->destroy(old->release_fb);
6694 mutex_unlock(&crtc->mutex);
6698 /* let the connector get through one full cycle before testing */
6699 intel_wait_for_vblank(dev, intel_crtc->pipe);
6703 void intel_release_load_detect_pipe(struct drm_connector *connector,
6704 struct intel_load_detect_pipe *old)
6706 struct intel_encoder *intel_encoder =
6707 intel_attached_encoder(connector);
6708 struct drm_encoder *encoder = &intel_encoder->base;
6709 struct drm_crtc *crtc = encoder->crtc;
6711 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6712 connector->base.id, drm_get_connector_name(connector),
6713 encoder->base.id, drm_get_encoder_name(encoder));
6715 if (old->load_detect_temp) {
6716 to_intel_connector(connector)->new_encoder = NULL;
6717 intel_encoder->new_crtc = NULL;
6718 intel_set_mode(crtc, NULL, 0, 0, NULL);
6720 if (old->release_fb) {
6721 drm_framebuffer_unregister_private(old->release_fb);
6722 drm_framebuffer_unreference(old->release_fb);
6725 mutex_unlock(&crtc->mutex);
6729 /* Switch crtc and encoder back off if necessary */
6730 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6731 connector->funcs->dpms(connector, old->dpms_mode);
6733 mutex_unlock(&crtc->mutex);
6736 /* Returns the clock of the currently programmed mode of the given pipe. */
6737 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6739 struct drm_i915_private *dev_priv = dev->dev_private;
6740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6741 int pipe = intel_crtc->pipe;
6742 u32 dpll = I915_READ(DPLL(pipe));
6744 intel_clock_t clock;
6746 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6747 fp = I915_READ(FP0(pipe));
6749 fp = I915_READ(FP1(pipe));
6751 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6752 if (IS_PINEVIEW(dev)) {
6753 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6754 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6756 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6757 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6760 if (!IS_GEN2(dev)) {
6761 if (IS_PINEVIEW(dev))
6762 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6763 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6765 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6766 DPLL_FPA01_P1_POST_DIV_SHIFT);
6768 switch (dpll & DPLL_MODE_MASK) {
6769 case DPLLB_MODE_DAC_SERIAL:
6770 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6773 case DPLLB_MODE_LVDS:
6774 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6778 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6779 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6783 /* XXX: Handle the 100Mhz refclk */
6784 intel_clock(dev, 96000, &clock);
6786 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6789 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6790 DPLL_FPA01_P1_POST_DIV_SHIFT);
6793 if ((dpll & PLL_REF_INPUT_MASK) ==
6794 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6795 /* XXX: might not be 66MHz */
6796 intel_clock(dev, 66000, &clock);
6798 intel_clock(dev, 48000, &clock);
6800 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6803 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6804 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6806 if (dpll & PLL_P2_DIVIDE_BY_4)
6811 intel_clock(dev, 48000, &clock);
6815 /* XXX: It would be nice to validate the clocks, but we can't reuse
6816 * i830PllIsValid() because it relies on the xf86_config connector
6817 * configuration being accurate, which it isn't necessarily.
6823 /** Returns the currently programmed mode of the given pipe. */
6824 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6825 struct drm_crtc *crtc)
6827 struct drm_i915_private *dev_priv = dev->dev_private;
6828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6829 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6830 struct drm_display_mode *mode;
6831 int htot = I915_READ(HTOTAL(cpu_transcoder));
6832 int hsync = I915_READ(HSYNC(cpu_transcoder));
6833 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6834 int vsync = I915_READ(VSYNC(cpu_transcoder));
6836 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6840 mode->clock = intel_crtc_clock_get(dev, crtc);
6841 mode->hdisplay = (htot & 0xffff) + 1;
6842 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6843 mode->hsync_start = (hsync & 0xffff) + 1;
6844 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6845 mode->vdisplay = (vtot & 0xffff) + 1;
6846 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6847 mode->vsync_start = (vsync & 0xffff) + 1;
6848 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6850 drm_mode_set_name(mode);
6855 static void intel_increase_pllclock(struct drm_crtc *crtc)
6857 struct drm_device *dev = crtc->dev;
6858 drm_i915_private_t *dev_priv = dev->dev_private;
6859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6860 int pipe = intel_crtc->pipe;
6861 int dpll_reg = DPLL(pipe);
6864 if (HAS_PCH_SPLIT(dev))
6867 if (!dev_priv->lvds_downclock_avail)
6870 dpll = I915_READ(dpll_reg);
6871 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6872 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6874 assert_panel_unlocked(dev_priv, pipe);
6876 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6877 I915_WRITE(dpll_reg, dpll);
6878 intel_wait_for_vblank(dev, pipe);
6880 dpll = I915_READ(dpll_reg);
6881 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6882 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6886 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6888 struct drm_device *dev = crtc->dev;
6889 drm_i915_private_t *dev_priv = dev->dev_private;
6890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6892 if (HAS_PCH_SPLIT(dev))
6895 if (!dev_priv->lvds_downclock_avail)
6899 * Since this is called by a timer, we should never get here in
6902 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6903 int pipe = intel_crtc->pipe;
6904 int dpll_reg = DPLL(pipe);
6907 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6909 assert_panel_unlocked(dev_priv, pipe);
6911 dpll = I915_READ(dpll_reg);
6912 dpll |= DISPLAY_RATE_SELECT_FPA1;
6913 I915_WRITE(dpll_reg, dpll);
6914 intel_wait_for_vblank(dev, pipe);
6915 dpll = I915_READ(dpll_reg);
6916 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6917 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6922 void intel_mark_busy(struct drm_device *dev)
6924 i915_update_gfx_val(dev->dev_private);
6927 void intel_mark_idle(struct drm_device *dev)
6929 struct drm_crtc *crtc;
6931 if (!i915_powersave)
6934 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6938 intel_decrease_pllclock(crtc);
6942 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6944 struct drm_device *dev = obj->base.dev;
6945 struct drm_crtc *crtc;
6947 if (!i915_powersave)
6950 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6954 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6955 intel_increase_pllclock(crtc);
6959 static void intel_crtc_destroy(struct drm_crtc *crtc)
6961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6962 struct drm_device *dev = crtc->dev;
6963 struct intel_unpin_work *work;
6964 unsigned long flags;
6966 spin_lock_irqsave(&dev->event_lock, flags);
6967 work = intel_crtc->unpin_work;
6968 intel_crtc->unpin_work = NULL;
6969 spin_unlock_irqrestore(&dev->event_lock, flags);
6972 cancel_work_sync(&work->work);
6976 drm_crtc_cleanup(crtc);
6981 static void intel_unpin_work_fn(struct work_struct *__work)
6983 struct intel_unpin_work *work =
6984 container_of(__work, struct intel_unpin_work, work);
6985 struct drm_device *dev = work->crtc->dev;
6987 mutex_lock(&dev->struct_mutex);
6988 intel_unpin_fb_obj(work->old_fb_obj);
6989 drm_gem_object_unreference(&work->pending_flip_obj->base);
6990 drm_gem_object_unreference(&work->old_fb_obj->base);
6992 intel_update_fbc(dev);
6993 mutex_unlock(&dev->struct_mutex);
6995 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6996 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7001 static void do_intel_finish_page_flip(struct drm_device *dev,
7002 struct drm_crtc *crtc)
7004 drm_i915_private_t *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006 struct intel_unpin_work *work;
7007 unsigned long flags;
7009 /* Ignore early vblank irqs */
7010 if (intel_crtc == NULL)
7013 spin_lock_irqsave(&dev->event_lock, flags);
7014 work = intel_crtc->unpin_work;
7016 /* Ensure we don't miss a work->pending update ... */
7019 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7020 spin_unlock_irqrestore(&dev->event_lock, flags);
7024 /* and that the unpin work is consistent wrt ->pending. */
7027 intel_crtc->unpin_work = NULL;
7030 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7032 drm_vblank_put(dev, intel_crtc->pipe);
7034 spin_unlock_irqrestore(&dev->event_lock, flags);
7036 wake_up_all(&dev_priv->pending_flip_queue);
7038 queue_work(dev_priv->wq, &work->work);
7040 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7043 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7045 drm_i915_private_t *dev_priv = dev->dev_private;
7046 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7048 do_intel_finish_page_flip(dev, crtc);
7051 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7053 drm_i915_private_t *dev_priv = dev->dev_private;
7054 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7056 do_intel_finish_page_flip(dev, crtc);
7059 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7061 drm_i915_private_t *dev_priv = dev->dev_private;
7062 struct intel_crtc *intel_crtc =
7063 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7064 unsigned long flags;
7066 /* NB: An MMIO update of the plane base pointer will also
7067 * generate a page-flip completion irq, i.e. every modeset
7068 * is also accompanied by a spurious intel_prepare_page_flip().
7070 spin_lock_irqsave(&dev->event_lock, flags);
7071 if (intel_crtc->unpin_work)
7072 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7073 spin_unlock_irqrestore(&dev->event_lock, flags);
7076 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7078 /* Ensure that the work item is consistent when activating it ... */
7080 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7081 /* and that it is marked active as soon as the irq could fire. */
7085 static int intel_gen2_queue_flip(struct drm_device *dev,
7086 struct drm_crtc *crtc,
7087 struct drm_framebuffer *fb,
7088 struct drm_i915_gem_object *obj)
7090 struct drm_i915_private *dev_priv = dev->dev_private;
7091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7093 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7096 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7100 ret = intel_ring_begin(ring, 6);
7104 /* Can't queue multiple flips, so wait for the previous
7105 * one to finish before executing the next.
7107 if (intel_crtc->plane)
7108 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7110 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7111 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7112 intel_ring_emit(ring, MI_NOOP);
7113 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7114 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7115 intel_ring_emit(ring, fb->pitches[0]);
7116 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7117 intel_ring_emit(ring, 0); /* aux display base address, unused */
7119 intel_mark_page_flip_active(intel_crtc);
7120 intel_ring_advance(ring);
7124 intel_unpin_fb_obj(obj);
7129 static int intel_gen3_queue_flip(struct drm_device *dev,
7130 struct drm_crtc *crtc,
7131 struct drm_framebuffer *fb,
7132 struct drm_i915_gem_object *obj)
7134 struct drm_i915_private *dev_priv = dev->dev_private;
7135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7137 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7140 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7144 ret = intel_ring_begin(ring, 6);
7148 if (intel_crtc->plane)
7149 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7151 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7152 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7153 intel_ring_emit(ring, MI_NOOP);
7154 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7155 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7156 intel_ring_emit(ring, fb->pitches[0]);
7157 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7158 intel_ring_emit(ring, MI_NOOP);
7160 intel_mark_page_flip_active(intel_crtc);
7161 intel_ring_advance(ring);
7165 intel_unpin_fb_obj(obj);
7170 static int intel_gen4_queue_flip(struct drm_device *dev,
7171 struct drm_crtc *crtc,
7172 struct drm_framebuffer *fb,
7173 struct drm_i915_gem_object *obj)
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7177 uint32_t pf, pipesrc;
7178 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7181 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7185 ret = intel_ring_begin(ring, 4);
7189 /* i965+ uses the linear or tiled offsets from the
7190 * Display Registers (which do not change across a page-flip)
7191 * so we need only reprogram the base address.
7193 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7194 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7195 intel_ring_emit(ring, fb->pitches[0]);
7196 intel_ring_emit(ring,
7197 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7200 /* XXX Enabling the panel-fitter across page-flip is so far
7201 * untested on non-native modes, so ignore it for now.
7202 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7205 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7206 intel_ring_emit(ring, pf | pipesrc);
7208 intel_mark_page_flip_active(intel_crtc);
7209 intel_ring_advance(ring);
7213 intel_unpin_fb_obj(obj);
7218 static int intel_gen6_queue_flip(struct drm_device *dev,
7219 struct drm_crtc *crtc,
7220 struct drm_framebuffer *fb,
7221 struct drm_i915_gem_object *obj)
7223 struct drm_i915_private *dev_priv = dev->dev_private;
7224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7225 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7226 uint32_t pf, pipesrc;
7229 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7233 ret = intel_ring_begin(ring, 4);
7237 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7238 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7239 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7240 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7242 /* Contrary to the suggestions in the documentation,
7243 * "Enable Panel Fitter" does not seem to be required when page
7244 * flipping with a non-native mode, and worse causes a normal
7246 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7249 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7250 intel_ring_emit(ring, pf | pipesrc);
7252 intel_mark_page_flip_active(intel_crtc);
7253 intel_ring_advance(ring);
7257 intel_unpin_fb_obj(obj);
7263 * On gen7 we currently use the blit ring because (in early silicon at least)
7264 * the render ring doesn't give us interrpts for page flip completion, which
7265 * means clients will hang after the first flip is queued. Fortunately the
7266 * blit ring generates interrupts properly, so use it instead.
7268 static int intel_gen7_queue_flip(struct drm_device *dev,
7269 struct drm_crtc *crtc,
7270 struct drm_framebuffer *fb,
7271 struct drm_i915_gem_object *obj)
7273 struct drm_i915_private *dev_priv = dev->dev_private;
7274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7275 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7276 uint32_t plane_bit = 0;
7279 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7283 switch(intel_crtc->plane) {
7285 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7288 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7291 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7294 WARN_ONCE(1, "unknown plane in flip command\n");
7299 ret = intel_ring_begin(ring, 4);
7303 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7304 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7305 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7306 intel_ring_emit(ring, (MI_NOOP));
7308 intel_mark_page_flip_active(intel_crtc);
7309 intel_ring_advance(ring);
7313 intel_unpin_fb_obj(obj);
7318 static int intel_default_queue_flip(struct drm_device *dev,
7319 struct drm_crtc *crtc,
7320 struct drm_framebuffer *fb,
7321 struct drm_i915_gem_object *obj)
7326 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7327 struct drm_framebuffer *fb,
7328 struct drm_pending_vblank_event *event)
7330 struct drm_device *dev = crtc->dev;
7331 struct drm_i915_private *dev_priv = dev->dev_private;
7332 struct drm_framebuffer *old_fb = crtc->fb;
7333 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7335 struct intel_unpin_work *work;
7336 unsigned long flags;
7339 /* Can't change pixel format via MI display flips. */
7340 if (fb->pixel_format != crtc->fb->pixel_format)
7344 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7345 * Note that pitch changes could also affect these register.
7347 if (INTEL_INFO(dev)->gen > 3 &&
7348 (fb->offsets[0] != crtc->fb->offsets[0] ||
7349 fb->pitches[0] != crtc->fb->pitches[0]))
7352 work = kzalloc(sizeof *work, GFP_KERNEL);
7356 work->event = event;
7358 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7359 INIT_WORK(&work->work, intel_unpin_work_fn);
7361 ret = drm_vblank_get(dev, intel_crtc->pipe);
7365 /* We borrow the event spin lock for protecting unpin_work */
7366 spin_lock_irqsave(&dev->event_lock, flags);
7367 if (intel_crtc->unpin_work) {
7368 spin_unlock_irqrestore(&dev->event_lock, flags);
7370 drm_vblank_put(dev, intel_crtc->pipe);
7372 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7375 intel_crtc->unpin_work = work;
7376 spin_unlock_irqrestore(&dev->event_lock, flags);
7378 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7379 flush_workqueue(dev_priv->wq);
7381 ret = i915_mutex_lock_interruptible(dev);
7385 /* Reference the objects for the scheduled work. */
7386 drm_gem_object_reference(&work->old_fb_obj->base);
7387 drm_gem_object_reference(&obj->base);
7391 work->pending_flip_obj = obj;
7393 work->enable_stall_check = true;
7395 atomic_inc(&intel_crtc->unpin_work_count);
7396 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7398 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7400 goto cleanup_pending;
7402 intel_disable_fbc(dev);
7403 intel_mark_fb_busy(obj);
7404 mutex_unlock(&dev->struct_mutex);
7406 trace_i915_flip_request(intel_crtc->plane, obj);
7411 atomic_dec(&intel_crtc->unpin_work_count);
7413 drm_gem_object_unreference(&work->old_fb_obj->base);
7414 drm_gem_object_unreference(&obj->base);
7415 mutex_unlock(&dev->struct_mutex);
7418 spin_lock_irqsave(&dev->event_lock, flags);
7419 intel_crtc->unpin_work = NULL;
7420 spin_unlock_irqrestore(&dev->event_lock, flags);
7422 drm_vblank_put(dev, intel_crtc->pipe);
7429 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7430 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7431 .load_lut = intel_crtc_load_lut,
7434 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7436 struct intel_encoder *other_encoder;
7437 struct drm_crtc *crtc = &encoder->new_crtc->base;
7442 list_for_each_entry(other_encoder,
7443 &crtc->dev->mode_config.encoder_list,
7446 if (&other_encoder->new_crtc->base != crtc ||
7447 encoder == other_encoder)
7456 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7457 struct drm_crtc *crtc)
7459 struct drm_device *dev;
7460 struct drm_crtc *tmp;
7463 WARN(!crtc, "checking null crtc?\n");
7467 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7473 if (encoder->possible_crtcs & crtc_mask)
7479 * intel_modeset_update_staged_output_state
7481 * Updates the staged output configuration state, e.g. after we've read out the
7484 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7486 struct intel_encoder *encoder;
7487 struct intel_connector *connector;
7489 list_for_each_entry(connector, &dev->mode_config.connector_list,
7491 connector->new_encoder =
7492 to_intel_encoder(connector->base.encoder);
7495 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7498 to_intel_crtc(encoder->base.crtc);
7503 * intel_modeset_commit_output_state
7505 * This function copies the stage display pipe configuration to the real one.
7507 static void intel_modeset_commit_output_state(struct drm_device *dev)
7509 struct intel_encoder *encoder;
7510 struct intel_connector *connector;
7512 list_for_each_entry(connector, &dev->mode_config.connector_list,
7514 connector->base.encoder = &connector->new_encoder->base;
7517 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7519 encoder->base.crtc = &encoder->new_crtc->base;
7524 pipe_config_set_bpp(struct drm_crtc *crtc,
7525 struct drm_framebuffer *fb,
7526 struct intel_crtc_config *pipe_config)
7528 struct drm_device *dev = crtc->dev;
7529 struct drm_connector *connector;
7532 switch (fb->pixel_format) {
7534 bpp = 8*3; /* since we go through a colormap */
7536 case DRM_FORMAT_XRGB1555:
7537 case DRM_FORMAT_ARGB1555:
7538 /* checked in intel_framebuffer_init already */
7539 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7541 case DRM_FORMAT_RGB565:
7542 bpp = 6*3; /* min is 18bpp */
7544 case DRM_FORMAT_XBGR8888:
7545 case DRM_FORMAT_ABGR8888:
7546 /* checked in intel_framebuffer_init already */
7547 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7549 case DRM_FORMAT_XRGB8888:
7550 case DRM_FORMAT_ARGB8888:
7553 case DRM_FORMAT_XRGB2101010:
7554 case DRM_FORMAT_ARGB2101010:
7555 case DRM_FORMAT_XBGR2101010:
7556 case DRM_FORMAT_ABGR2101010:
7557 /* checked in intel_framebuffer_init already */
7558 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7562 /* TODO: gen4+ supports 16 bpc floating point, too. */
7564 DRM_DEBUG_KMS("unsupported depth\n");
7568 pipe_config->pipe_bpp = bpp;
7570 /* Clamp display bpp to EDID value */
7571 list_for_each_entry(connector, &dev->mode_config.connector_list,
7573 if (connector->encoder && connector->encoder->crtc != crtc)
7576 /* Don't use an invalid EDID bpc value */
7577 if (connector->display_info.bpc &&
7578 connector->display_info.bpc * 3 < bpp) {
7579 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7580 bpp, connector->display_info.bpc*3);
7581 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7588 static struct intel_crtc_config *
7589 intel_modeset_pipe_config(struct drm_crtc *crtc,
7590 struct drm_framebuffer *fb,
7591 struct drm_display_mode *mode)
7593 struct drm_device *dev = crtc->dev;
7594 struct drm_encoder_helper_funcs *encoder_funcs;
7595 struct intel_encoder *encoder;
7596 struct intel_crtc_config *pipe_config;
7599 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7601 return ERR_PTR(-ENOMEM);
7603 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7604 drm_mode_copy(&pipe_config->requested_mode, mode);
7606 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7610 /* Pass our mode to the connectors and the CRTC to give them a chance to
7611 * adjust it according to limitations or connector properties, and also
7612 * a chance to reject the mode entirely.
7614 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7617 if (&encoder->new_crtc->base != crtc)
7620 if (encoder->compute_config) {
7621 if (!(encoder->compute_config(encoder, pipe_config))) {
7622 DRM_DEBUG_KMS("Encoder config failure\n");
7629 encoder_funcs = encoder->base.helper_private;
7630 if (!(encoder_funcs->mode_fixup(&encoder->base,
7631 &pipe_config->requested_mode,
7632 &pipe_config->adjusted_mode))) {
7633 DRM_DEBUG_KMS("Encoder fixup failed\n");
7638 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7639 DRM_DEBUG_KMS("CRTC fixup failed\n");
7642 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7644 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7645 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7646 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7651 return ERR_PTR(-EINVAL);
7654 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7655 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7657 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7658 unsigned *prepare_pipes, unsigned *disable_pipes)
7660 struct intel_crtc *intel_crtc;
7661 struct drm_device *dev = crtc->dev;
7662 struct intel_encoder *encoder;
7663 struct intel_connector *connector;
7664 struct drm_crtc *tmp_crtc;
7666 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7668 /* Check which crtcs have changed outputs connected to them, these need
7669 * to be part of the prepare_pipes mask. We don't (yet) support global
7670 * modeset across multiple crtcs, so modeset_pipes will only have one
7671 * bit set at most. */
7672 list_for_each_entry(connector, &dev->mode_config.connector_list,
7674 if (connector->base.encoder == &connector->new_encoder->base)
7677 if (connector->base.encoder) {
7678 tmp_crtc = connector->base.encoder->crtc;
7680 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7683 if (connector->new_encoder)
7685 1 << connector->new_encoder->new_crtc->pipe;
7688 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7690 if (encoder->base.crtc == &encoder->new_crtc->base)
7693 if (encoder->base.crtc) {
7694 tmp_crtc = encoder->base.crtc;
7696 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7699 if (encoder->new_crtc)
7700 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7703 /* Check for any pipes that will be fully disabled ... */
7704 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7708 /* Don't try to disable disabled crtcs. */
7709 if (!intel_crtc->base.enabled)
7712 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7714 if (encoder->new_crtc == intel_crtc)
7719 *disable_pipes |= 1 << intel_crtc->pipe;
7723 /* set_mode is also used to update properties on life display pipes. */
7724 intel_crtc = to_intel_crtc(crtc);
7726 *prepare_pipes |= 1 << intel_crtc->pipe;
7729 * For simplicity do a full modeset on any pipe where the output routing
7730 * changed. We could be more clever, but that would require us to be
7731 * more careful with calling the relevant encoder->mode_set functions.
7734 *modeset_pipes = *prepare_pipes;
7736 /* ... and mask these out. */
7737 *modeset_pipes &= ~(*disable_pipes);
7738 *prepare_pipes &= ~(*disable_pipes);
7741 * HACK: We don't (yet) fully support global modesets. intel_set_config
7742 * obies this rule, but the modeset restore mode of
7743 * intel_modeset_setup_hw_state does not.
7745 *modeset_pipes &= 1 << intel_crtc->pipe;
7746 *prepare_pipes &= 1 << intel_crtc->pipe;
7748 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7749 *modeset_pipes, *prepare_pipes, *disable_pipes);
7752 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7754 struct drm_encoder *encoder;
7755 struct drm_device *dev = crtc->dev;
7757 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7758 if (encoder->crtc == crtc)
7765 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7767 struct intel_encoder *intel_encoder;
7768 struct intel_crtc *intel_crtc;
7769 struct drm_connector *connector;
7771 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7773 if (!intel_encoder->base.crtc)
7776 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7778 if (prepare_pipes & (1 << intel_crtc->pipe))
7779 intel_encoder->connectors_active = false;
7782 intel_modeset_commit_output_state(dev);
7784 /* Update computed state. */
7785 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7787 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7790 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7791 if (!connector->encoder || !connector->encoder->crtc)
7794 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7796 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7797 struct drm_property *dpms_property =
7798 dev->mode_config.dpms_property;
7800 connector->dpms = DRM_MODE_DPMS_ON;
7801 drm_object_property_set_value(&connector->base,
7805 intel_encoder = to_intel_encoder(connector->encoder);
7806 intel_encoder->connectors_active = true;
7812 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7813 list_for_each_entry((intel_crtc), \
7814 &(dev)->mode_config.crtc_list, \
7816 if (mask & (1 <<(intel_crtc)->pipe)) \
7819 intel_pipe_config_compare(struct intel_crtc_config *current_config,
7820 struct intel_crtc_config *pipe_config)
7822 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7823 DRM_ERROR("mismatch in has_pch_encoder "
7824 "(expected %i, found %i)\n",
7825 current_config->has_pch_encoder,
7826 pipe_config->has_pch_encoder);
7834 intel_modeset_check_state(struct drm_device *dev)
7836 drm_i915_private_t *dev_priv = dev->dev_private;
7837 struct intel_crtc *crtc;
7838 struct intel_encoder *encoder;
7839 struct intel_connector *connector;
7840 struct intel_crtc_config pipe_config;
7842 list_for_each_entry(connector, &dev->mode_config.connector_list,
7844 /* This also checks the encoder/connector hw state with the
7845 * ->get_hw_state callbacks. */
7846 intel_connector_check_state(connector);
7848 WARN(&connector->new_encoder->base != connector->base.encoder,
7849 "connector's staged encoder doesn't match current encoder\n");
7852 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7854 bool enabled = false;
7855 bool active = false;
7856 enum pipe pipe, tracked_pipe;
7858 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7859 encoder->base.base.id,
7860 drm_get_encoder_name(&encoder->base));
7862 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7863 "encoder's stage crtc doesn't match current crtc\n");
7864 WARN(encoder->connectors_active && !encoder->base.crtc,
7865 "encoder's active_connectors set, but no crtc\n");
7867 list_for_each_entry(connector, &dev->mode_config.connector_list,
7869 if (connector->base.encoder != &encoder->base)
7872 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7875 WARN(!!encoder->base.crtc != enabled,
7876 "encoder's enabled state mismatch "
7877 "(expected %i, found %i)\n",
7878 !!encoder->base.crtc, enabled);
7879 WARN(active && !encoder->base.crtc,
7880 "active encoder with no crtc\n");
7882 WARN(encoder->connectors_active != active,
7883 "encoder's computed active state doesn't match tracked active state "
7884 "(expected %i, found %i)\n", active, encoder->connectors_active);
7886 active = encoder->get_hw_state(encoder, &pipe);
7887 WARN(active != encoder->connectors_active,
7888 "encoder's hw state doesn't match sw tracking "
7889 "(expected %i, found %i)\n",
7890 encoder->connectors_active, active);
7892 if (!encoder->base.crtc)
7895 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7896 WARN(active && pipe != tracked_pipe,
7897 "active encoder's pipe doesn't match"
7898 "(expected %i, found %i)\n",
7899 tracked_pipe, pipe);
7903 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7905 bool enabled = false;
7906 bool active = false;
7908 DRM_DEBUG_KMS("[CRTC:%d]\n",
7909 crtc->base.base.id);
7911 WARN(crtc->active && !crtc->base.enabled,
7912 "active crtc, but not enabled in sw tracking\n");
7914 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7916 if (encoder->base.crtc != &crtc->base)
7919 if (encoder->connectors_active)
7922 WARN(active != crtc->active,
7923 "crtc's computed active state doesn't match tracked active state "
7924 "(expected %i, found %i)\n", active, crtc->active);
7925 WARN(enabled != crtc->base.enabled,
7926 "crtc's computed enabled state doesn't match tracked enabled state "
7927 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7929 memset(&pipe_config, 0, sizeof(pipe_config));
7930 active = dev_priv->display.get_pipe_config(crtc,
7932 WARN(crtc->active != active,
7933 "crtc active state doesn't match with hw state "
7934 "(expected %i, found %i)\n", crtc->active, active);
7937 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7938 "pipe state doesn't match!\n");
7942 static int __intel_set_mode(struct drm_crtc *crtc,
7943 struct drm_display_mode *mode,
7944 int x, int y, struct drm_framebuffer *fb)
7946 struct drm_device *dev = crtc->dev;
7947 drm_i915_private_t *dev_priv = dev->dev_private;
7948 struct drm_display_mode *saved_mode, *saved_hwmode;
7949 struct intel_crtc_config *pipe_config = NULL;
7950 struct intel_crtc *intel_crtc;
7951 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7954 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7957 saved_hwmode = saved_mode + 1;
7959 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7960 &prepare_pipes, &disable_pipes);
7962 *saved_hwmode = crtc->hwmode;
7963 *saved_mode = crtc->mode;
7965 /* Hack: Because we don't (yet) support global modeset on multiple
7966 * crtcs, we don't keep track of the new mode for more than one crtc.
7967 * Hence simply check whether any bit is set in modeset_pipes in all the
7968 * pieces of code that are not yet converted to deal with mutliple crtcs
7969 * changing their mode at the same time. */
7970 if (modeset_pipes) {
7971 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
7972 if (IS_ERR(pipe_config)) {
7973 ret = PTR_ERR(pipe_config);
7980 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7981 intel_crtc_disable(&intel_crtc->base);
7983 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7984 if (intel_crtc->base.enabled)
7985 dev_priv->display.crtc_disable(&intel_crtc->base);
7988 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7989 * to set it here already despite that we pass it down the callchain.
7991 if (modeset_pipes) {
7992 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
7994 /* mode_set/enable/disable functions rely on a correct pipe
7996 to_intel_crtc(crtc)->config = *pipe_config;
7997 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8000 /* Only after disabling all output pipelines that will be changed can we
8001 * update the the output configuration. */
8002 intel_modeset_update_state(dev, prepare_pipes);
8004 if (dev_priv->display.modeset_global_resources)
8005 dev_priv->display.modeset_global_resources(dev);
8007 /* Set up the DPLL and any encoders state that needs to adjust or depend
8010 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8011 ret = intel_crtc_mode_set(&intel_crtc->base,
8017 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8018 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8019 dev_priv->display.crtc_enable(&intel_crtc->base);
8021 if (modeset_pipes) {
8022 /* Store real post-adjustment hardware mode. */
8023 crtc->hwmode = pipe_config->adjusted_mode;
8025 /* Calculate and store various constants which
8026 * are later needed by vblank and swap-completion
8027 * timestamping. They are derived from true hwmode.
8029 drm_calc_timestamping_constants(crtc);
8032 /* FIXME: add subpixel order */
8034 if (ret && crtc->enabled) {
8035 crtc->hwmode = *saved_hwmode;
8036 crtc->mode = *saved_mode;
8045 int intel_set_mode(struct drm_crtc *crtc,
8046 struct drm_display_mode *mode,
8047 int x, int y, struct drm_framebuffer *fb)
8051 ret = __intel_set_mode(crtc, mode, x, y, fb);
8054 intel_modeset_check_state(crtc->dev);
8059 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8061 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8064 #undef for_each_intel_crtc_masked
8066 static void intel_set_config_free(struct intel_set_config *config)
8071 kfree(config->save_connector_encoders);
8072 kfree(config->save_encoder_crtcs);
8076 static int intel_set_config_save_state(struct drm_device *dev,
8077 struct intel_set_config *config)
8079 struct drm_encoder *encoder;
8080 struct drm_connector *connector;
8083 config->save_encoder_crtcs =
8084 kcalloc(dev->mode_config.num_encoder,
8085 sizeof(struct drm_crtc *), GFP_KERNEL);
8086 if (!config->save_encoder_crtcs)
8089 config->save_connector_encoders =
8090 kcalloc(dev->mode_config.num_connector,
8091 sizeof(struct drm_encoder *), GFP_KERNEL);
8092 if (!config->save_connector_encoders)
8095 /* Copy data. Note that driver private data is not affected.
8096 * Should anything bad happen only the expected state is
8097 * restored, not the drivers personal bookkeeping.
8100 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8101 config->save_encoder_crtcs[count++] = encoder->crtc;
8105 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8106 config->save_connector_encoders[count++] = connector->encoder;
8112 static void intel_set_config_restore_state(struct drm_device *dev,
8113 struct intel_set_config *config)
8115 struct intel_encoder *encoder;
8116 struct intel_connector *connector;
8120 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8122 to_intel_crtc(config->save_encoder_crtcs[count++]);
8126 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8127 connector->new_encoder =
8128 to_intel_encoder(config->save_connector_encoders[count++]);
8133 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8134 struct intel_set_config *config)
8137 /* We should be able to check here if the fb has the same properties
8138 * and then just flip_or_move it */
8139 if (set->crtc->fb != set->fb) {
8140 /* If we have no fb then treat it as a full mode set */
8141 if (set->crtc->fb == NULL) {
8142 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8143 config->mode_changed = true;
8144 } else if (set->fb == NULL) {
8145 config->mode_changed = true;
8146 } else if (set->fb->pixel_format !=
8147 set->crtc->fb->pixel_format) {
8148 config->mode_changed = true;
8150 config->fb_changed = true;
8153 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8154 config->fb_changed = true;
8156 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8157 DRM_DEBUG_KMS("modes are different, full mode set\n");
8158 drm_mode_debug_printmodeline(&set->crtc->mode);
8159 drm_mode_debug_printmodeline(set->mode);
8160 config->mode_changed = true;
8165 intel_modeset_stage_output_state(struct drm_device *dev,
8166 struct drm_mode_set *set,
8167 struct intel_set_config *config)
8169 struct drm_crtc *new_crtc;
8170 struct intel_connector *connector;
8171 struct intel_encoder *encoder;
8174 /* The upper layers ensure that we either disable a crtc or have a list
8175 * of connectors. For paranoia, double-check this. */
8176 WARN_ON(!set->fb && (set->num_connectors != 0));
8177 WARN_ON(set->fb && (set->num_connectors == 0));
8180 list_for_each_entry(connector, &dev->mode_config.connector_list,
8182 /* Otherwise traverse passed in connector list and get encoders
8184 for (ro = 0; ro < set->num_connectors; ro++) {
8185 if (set->connectors[ro] == &connector->base) {
8186 connector->new_encoder = connector->encoder;
8191 /* If we disable the crtc, disable all its connectors. Also, if
8192 * the connector is on the changing crtc but not on the new
8193 * connector list, disable it. */
8194 if ((!set->fb || ro == set->num_connectors) &&
8195 connector->base.encoder &&
8196 connector->base.encoder->crtc == set->crtc) {
8197 connector->new_encoder = NULL;
8199 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8200 connector->base.base.id,
8201 drm_get_connector_name(&connector->base));
8205 if (&connector->new_encoder->base != connector->base.encoder) {
8206 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8207 config->mode_changed = true;
8210 /* connector->new_encoder is now updated for all connectors. */
8212 /* Update crtc of enabled connectors. */
8214 list_for_each_entry(connector, &dev->mode_config.connector_list,
8216 if (!connector->new_encoder)
8219 new_crtc = connector->new_encoder->base.crtc;
8221 for (ro = 0; ro < set->num_connectors; ro++) {
8222 if (set->connectors[ro] == &connector->base)
8223 new_crtc = set->crtc;
8226 /* Make sure the new CRTC will work with the encoder */
8227 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8231 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8233 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8234 connector->base.base.id,
8235 drm_get_connector_name(&connector->base),
8239 /* Check for any encoders that needs to be disabled. */
8240 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8242 list_for_each_entry(connector,
8243 &dev->mode_config.connector_list,
8245 if (connector->new_encoder == encoder) {
8246 WARN_ON(!connector->new_encoder->new_crtc);
8251 encoder->new_crtc = NULL;
8253 /* Only now check for crtc changes so we don't miss encoders
8254 * that will be disabled. */
8255 if (&encoder->new_crtc->base != encoder->base.crtc) {
8256 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8257 config->mode_changed = true;
8260 /* Now we've also updated encoder->new_crtc for all encoders. */
8265 static int intel_crtc_set_config(struct drm_mode_set *set)
8267 struct drm_device *dev;
8268 struct drm_mode_set save_set;
8269 struct intel_set_config *config;
8274 BUG_ON(!set->crtc->helper_private);
8276 /* Enforce sane interface api - has been abused by the fb helper. */
8277 BUG_ON(!set->mode && set->fb);
8278 BUG_ON(set->fb && set->num_connectors == 0);
8281 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8282 set->crtc->base.id, set->fb->base.id,
8283 (int)set->num_connectors, set->x, set->y);
8285 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8288 dev = set->crtc->dev;
8291 config = kzalloc(sizeof(*config), GFP_KERNEL);
8295 ret = intel_set_config_save_state(dev, config);
8299 save_set.crtc = set->crtc;
8300 save_set.mode = &set->crtc->mode;
8301 save_set.x = set->crtc->x;
8302 save_set.y = set->crtc->y;
8303 save_set.fb = set->crtc->fb;
8305 /* Compute whether we need a full modeset, only an fb base update or no
8306 * change at all. In the future we might also check whether only the
8307 * mode changed, e.g. for LVDS where we only change the panel fitter in
8309 intel_set_config_compute_mode_changes(set, config);
8311 ret = intel_modeset_stage_output_state(dev, set, config);
8315 if (config->mode_changed) {
8317 DRM_DEBUG_KMS("attempting to set mode from"
8319 drm_mode_debug_printmodeline(set->mode);
8322 ret = intel_set_mode(set->crtc, set->mode,
8323 set->x, set->y, set->fb);
8325 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8326 set->crtc->base.id, ret);
8329 } else if (config->fb_changed) {
8330 intel_crtc_wait_for_pending_flips(set->crtc);
8332 ret = intel_pipe_set_base(set->crtc,
8333 set->x, set->y, set->fb);
8336 intel_set_config_free(config);
8341 intel_set_config_restore_state(dev, config);
8343 /* Try to restore the config */
8344 if (config->mode_changed &&
8345 intel_set_mode(save_set.crtc, save_set.mode,
8346 save_set.x, save_set.y, save_set.fb))
8347 DRM_ERROR("failed to restore config after modeset failure\n");
8350 intel_set_config_free(config);
8354 static const struct drm_crtc_funcs intel_crtc_funcs = {
8355 .cursor_set = intel_crtc_cursor_set,
8356 .cursor_move = intel_crtc_cursor_move,
8357 .gamma_set = intel_crtc_gamma_set,
8358 .set_config = intel_crtc_set_config,
8359 .destroy = intel_crtc_destroy,
8360 .page_flip = intel_crtc_page_flip,
8363 static void intel_cpu_pll_init(struct drm_device *dev)
8366 intel_ddi_pll_init(dev);
8369 static void intel_pch_pll_init(struct drm_device *dev)
8371 drm_i915_private_t *dev_priv = dev->dev_private;
8374 if (dev_priv->num_pch_pll == 0) {
8375 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8379 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8380 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8381 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8382 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8386 static void intel_crtc_init(struct drm_device *dev, int pipe)
8388 drm_i915_private_t *dev_priv = dev->dev_private;
8389 struct intel_crtc *intel_crtc;
8392 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8393 if (intel_crtc == NULL)
8396 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8398 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8399 for (i = 0; i < 256; i++) {
8400 intel_crtc->lut_r[i] = i;
8401 intel_crtc->lut_g[i] = i;
8402 intel_crtc->lut_b[i] = i;
8405 /* Swap pipes & planes for FBC on pre-965 */
8406 intel_crtc->pipe = pipe;
8407 intel_crtc->plane = pipe;
8408 intel_crtc->config.cpu_transcoder = pipe;
8409 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8410 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8411 intel_crtc->plane = !pipe;
8414 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8415 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8416 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8417 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8419 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8422 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8423 struct drm_file *file)
8425 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8426 struct drm_mode_object *drmmode_obj;
8427 struct intel_crtc *crtc;
8429 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8432 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8433 DRM_MODE_OBJECT_CRTC);
8436 DRM_ERROR("no such CRTC id\n");
8440 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8441 pipe_from_crtc_id->pipe = crtc->pipe;
8446 static int intel_encoder_clones(struct intel_encoder *encoder)
8448 struct drm_device *dev = encoder->base.dev;
8449 struct intel_encoder *source_encoder;
8453 list_for_each_entry(source_encoder,
8454 &dev->mode_config.encoder_list, base.head) {
8456 if (encoder == source_encoder)
8457 index_mask |= (1 << entry);
8459 /* Intel hw has only one MUX where enocoders could be cloned. */
8460 if (encoder->cloneable && source_encoder->cloneable)
8461 index_mask |= (1 << entry);
8469 static bool has_edp_a(struct drm_device *dev)
8471 struct drm_i915_private *dev_priv = dev->dev_private;
8473 if (!IS_MOBILE(dev))
8476 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8480 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8486 static void intel_setup_outputs(struct drm_device *dev)
8488 struct drm_i915_private *dev_priv = dev->dev_private;
8489 struct intel_encoder *encoder;
8490 bool dpd_is_edp = false;
8493 has_lvds = intel_lvds_init(dev);
8494 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8495 /* disable the panel fitter on everything but LVDS */
8496 I915_WRITE(PFIT_CONTROL, 0);
8500 intel_crt_init(dev);
8505 /* Haswell uses DDI functions to detect digital outputs */
8506 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8507 /* DDI A only supports eDP */
8509 intel_ddi_init(dev, PORT_A);
8511 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8513 found = I915_READ(SFUSE_STRAP);
8515 if (found & SFUSE_STRAP_DDIB_DETECTED)
8516 intel_ddi_init(dev, PORT_B);
8517 if (found & SFUSE_STRAP_DDIC_DETECTED)
8518 intel_ddi_init(dev, PORT_C);
8519 if (found & SFUSE_STRAP_DDID_DETECTED)
8520 intel_ddi_init(dev, PORT_D);
8521 } else if (HAS_PCH_SPLIT(dev)) {
8523 dpd_is_edp = intel_dpd_is_edp(dev);
8526 intel_dp_init(dev, DP_A, PORT_A);
8528 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8529 /* PCH SDVOB multiplex with HDMIB */
8530 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8532 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8533 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8534 intel_dp_init(dev, PCH_DP_B, PORT_B);
8537 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8538 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8540 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8541 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8543 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8544 intel_dp_init(dev, PCH_DP_C, PORT_C);
8546 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8547 intel_dp_init(dev, PCH_DP_D, PORT_D);
8548 } else if (IS_VALLEYVIEW(dev)) {
8549 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8550 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8551 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8553 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8554 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8556 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8557 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8559 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8562 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8563 DRM_DEBUG_KMS("probing SDVOB\n");
8564 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8565 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8566 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8567 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8570 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8571 DRM_DEBUG_KMS("probing DP_B\n");
8572 intel_dp_init(dev, DP_B, PORT_B);
8576 /* Before G4X SDVOC doesn't have its own detect register */
8578 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8579 DRM_DEBUG_KMS("probing SDVOC\n");
8580 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8583 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8585 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8586 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8587 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8589 if (SUPPORTS_INTEGRATED_DP(dev)) {
8590 DRM_DEBUG_KMS("probing DP_C\n");
8591 intel_dp_init(dev, DP_C, PORT_C);
8595 if (SUPPORTS_INTEGRATED_DP(dev) &&
8596 (I915_READ(DP_D) & DP_DETECTED)) {
8597 DRM_DEBUG_KMS("probing DP_D\n");
8598 intel_dp_init(dev, DP_D, PORT_D);
8600 } else if (IS_GEN2(dev))
8601 intel_dvo_init(dev);
8603 if (SUPPORTS_TV(dev))
8606 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8607 encoder->base.possible_crtcs = encoder->crtc_mask;
8608 encoder->base.possible_clones =
8609 intel_encoder_clones(encoder);
8612 intel_init_pch_refclk(dev);
8614 drm_helper_move_panel_connectors_to_head(dev);
8617 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8619 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8621 drm_framebuffer_cleanup(fb);
8622 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8627 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8628 struct drm_file *file,
8629 unsigned int *handle)
8631 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8632 struct drm_i915_gem_object *obj = intel_fb->obj;
8634 return drm_gem_handle_create(file, &obj->base, handle);
8637 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8638 .destroy = intel_user_framebuffer_destroy,
8639 .create_handle = intel_user_framebuffer_create_handle,
8642 int intel_framebuffer_init(struct drm_device *dev,
8643 struct intel_framebuffer *intel_fb,
8644 struct drm_mode_fb_cmd2 *mode_cmd,
8645 struct drm_i915_gem_object *obj)
8649 if (obj->tiling_mode == I915_TILING_Y) {
8650 DRM_DEBUG("hardware does not support tiling Y\n");
8654 if (mode_cmd->pitches[0] & 63) {
8655 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8656 mode_cmd->pitches[0]);
8660 /* FIXME <= Gen4 stride limits are bit unclear */
8661 if (mode_cmd->pitches[0] > 32768) {
8662 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8663 mode_cmd->pitches[0]);
8667 if (obj->tiling_mode != I915_TILING_NONE &&
8668 mode_cmd->pitches[0] != obj->stride) {
8669 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8670 mode_cmd->pitches[0], obj->stride);
8674 /* Reject formats not supported by any plane early. */
8675 switch (mode_cmd->pixel_format) {
8677 case DRM_FORMAT_RGB565:
8678 case DRM_FORMAT_XRGB8888:
8679 case DRM_FORMAT_ARGB8888:
8681 case DRM_FORMAT_XRGB1555:
8682 case DRM_FORMAT_ARGB1555:
8683 if (INTEL_INFO(dev)->gen > 3) {
8684 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8688 case DRM_FORMAT_XBGR8888:
8689 case DRM_FORMAT_ABGR8888:
8690 case DRM_FORMAT_XRGB2101010:
8691 case DRM_FORMAT_ARGB2101010:
8692 case DRM_FORMAT_XBGR2101010:
8693 case DRM_FORMAT_ABGR2101010:
8694 if (INTEL_INFO(dev)->gen < 4) {
8695 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8699 case DRM_FORMAT_YUYV:
8700 case DRM_FORMAT_UYVY:
8701 case DRM_FORMAT_YVYU:
8702 case DRM_FORMAT_VYUY:
8703 if (INTEL_INFO(dev)->gen < 5) {
8704 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8709 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8713 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8714 if (mode_cmd->offsets[0] != 0)
8717 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8718 intel_fb->obj = obj;
8720 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8722 DRM_ERROR("framebuffer init failed %d\n", ret);
8729 static struct drm_framebuffer *
8730 intel_user_framebuffer_create(struct drm_device *dev,
8731 struct drm_file *filp,
8732 struct drm_mode_fb_cmd2 *mode_cmd)
8734 struct drm_i915_gem_object *obj;
8736 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8737 mode_cmd->handles[0]));
8738 if (&obj->base == NULL)
8739 return ERR_PTR(-ENOENT);
8741 return intel_framebuffer_create(dev, mode_cmd, obj);
8744 static const struct drm_mode_config_funcs intel_mode_funcs = {
8745 .fb_create = intel_user_framebuffer_create,
8746 .output_poll_changed = intel_fb_output_poll_changed,
8749 /* Set up chip specific display functions */
8750 static void intel_init_display(struct drm_device *dev)
8752 struct drm_i915_private *dev_priv = dev->dev_private;
8755 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8756 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8757 dev_priv->display.crtc_enable = haswell_crtc_enable;
8758 dev_priv->display.crtc_disable = haswell_crtc_disable;
8759 dev_priv->display.off = haswell_crtc_off;
8760 dev_priv->display.update_plane = ironlake_update_plane;
8761 } else if (HAS_PCH_SPLIT(dev)) {
8762 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8763 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8764 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8765 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8766 dev_priv->display.off = ironlake_crtc_off;
8767 dev_priv->display.update_plane = ironlake_update_plane;
8769 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8770 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8771 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8772 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8773 dev_priv->display.off = i9xx_crtc_off;
8774 dev_priv->display.update_plane = i9xx_update_plane;
8777 /* Returns the core display clock speed */
8778 if (IS_VALLEYVIEW(dev))
8779 dev_priv->display.get_display_clock_speed =
8780 valleyview_get_display_clock_speed;
8781 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8782 dev_priv->display.get_display_clock_speed =
8783 i945_get_display_clock_speed;
8784 else if (IS_I915G(dev))
8785 dev_priv->display.get_display_clock_speed =
8786 i915_get_display_clock_speed;
8787 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8788 dev_priv->display.get_display_clock_speed =
8789 i9xx_misc_get_display_clock_speed;
8790 else if (IS_I915GM(dev))
8791 dev_priv->display.get_display_clock_speed =
8792 i915gm_get_display_clock_speed;
8793 else if (IS_I865G(dev))
8794 dev_priv->display.get_display_clock_speed =
8795 i865_get_display_clock_speed;
8796 else if (IS_I85X(dev))
8797 dev_priv->display.get_display_clock_speed =
8798 i855_get_display_clock_speed;
8800 dev_priv->display.get_display_clock_speed =
8801 i830_get_display_clock_speed;
8803 if (HAS_PCH_SPLIT(dev)) {
8805 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8806 dev_priv->display.write_eld = ironlake_write_eld;
8807 } else if (IS_GEN6(dev)) {
8808 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8809 dev_priv->display.write_eld = ironlake_write_eld;
8810 } else if (IS_IVYBRIDGE(dev)) {
8811 /* FIXME: detect B0+ stepping and use auto training */
8812 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8813 dev_priv->display.write_eld = ironlake_write_eld;
8814 dev_priv->display.modeset_global_resources =
8815 ivb_modeset_global_resources;
8816 } else if (IS_HASWELL(dev)) {
8817 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8818 dev_priv->display.write_eld = haswell_write_eld;
8819 dev_priv->display.modeset_global_resources =
8820 haswell_modeset_global_resources;
8822 } else if (IS_G4X(dev)) {
8823 dev_priv->display.write_eld = g4x_write_eld;
8826 /* Default just returns -ENODEV to indicate unsupported */
8827 dev_priv->display.queue_flip = intel_default_queue_flip;
8829 switch (INTEL_INFO(dev)->gen) {
8831 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8835 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8840 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8844 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8847 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8853 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8854 * resume, or other times. This quirk makes sure that's the case for
8857 static void quirk_pipea_force(struct drm_device *dev)
8859 struct drm_i915_private *dev_priv = dev->dev_private;
8861 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8862 DRM_INFO("applying pipe a force quirk\n");
8866 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8868 static void quirk_ssc_force_disable(struct drm_device *dev)
8870 struct drm_i915_private *dev_priv = dev->dev_private;
8871 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8872 DRM_INFO("applying lvds SSC disable quirk\n");
8876 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8879 static void quirk_invert_brightness(struct drm_device *dev)
8881 struct drm_i915_private *dev_priv = dev->dev_private;
8882 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8883 DRM_INFO("applying inverted panel brightness quirk\n");
8886 struct intel_quirk {
8888 int subsystem_vendor;
8889 int subsystem_device;
8890 void (*hook)(struct drm_device *dev);
8893 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8894 struct intel_dmi_quirk {
8895 void (*hook)(struct drm_device *dev);
8896 const struct dmi_system_id (*dmi_id_list)[];
8899 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8901 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8905 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8907 .dmi_id_list = &(const struct dmi_system_id[]) {
8909 .callback = intel_dmi_reverse_brightness,
8910 .ident = "NCR Corporation",
8911 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8912 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8915 { } /* terminating entry */
8917 .hook = quirk_invert_brightness,
8921 static struct intel_quirk intel_quirks[] = {
8922 /* HP Mini needs pipe A force quirk (LP: #322104) */
8923 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8925 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8926 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8928 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8929 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8931 /* 830/845 need to leave pipe A & dpll A up */
8932 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8933 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8935 /* Lenovo U160 cannot use SSC on LVDS */
8936 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8938 /* Sony Vaio Y cannot use SSC on LVDS */
8939 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8941 /* Acer Aspire 5734Z must invert backlight brightness */
8942 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8944 /* Acer/eMachines G725 */
8945 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8947 /* Acer/eMachines e725 */
8948 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8950 /* Acer/Packard Bell NCL20 */
8951 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8953 /* Acer Aspire 4736Z */
8954 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8957 static void intel_init_quirks(struct drm_device *dev)
8959 struct pci_dev *d = dev->pdev;
8962 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8963 struct intel_quirk *q = &intel_quirks[i];
8965 if (d->device == q->device &&
8966 (d->subsystem_vendor == q->subsystem_vendor ||
8967 q->subsystem_vendor == PCI_ANY_ID) &&
8968 (d->subsystem_device == q->subsystem_device ||
8969 q->subsystem_device == PCI_ANY_ID))
8972 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8973 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8974 intel_dmi_quirks[i].hook(dev);
8978 /* Disable the VGA plane that we never use */
8979 static void i915_disable_vga(struct drm_device *dev)
8981 struct drm_i915_private *dev_priv = dev->dev_private;
8983 u32 vga_reg = i915_vgacntrl_reg(dev);
8985 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8986 outb(SR01, VGA_SR_INDEX);
8987 sr1 = inb(VGA_SR_DATA);
8988 outb(sr1 | 1<<5, VGA_SR_DATA);
8989 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8992 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8993 POSTING_READ(vga_reg);
8996 void intel_modeset_init_hw(struct drm_device *dev)
8998 intel_init_power_well(dev);
9000 intel_prepare_ddi(dev);
9002 intel_init_clock_gating(dev);
9004 mutex_lock(&dev->struct_mutex);
9005 intel_enable_gt_powersave(dev);
9006 mutex_unlock(&dev->struct_mutex);
9009 void intel_modeset_init(struct drm_device *dev)
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9014 drm_mode_config_init(dev);
9016 dev->mode_config.min_width = 0;
9017 dev->mode_config.min_height = 0;
9019 dev->mode_config.preferred_depth = 24;
9020 dev->mode_config.prefer_shadow = 1;
9022 dev->mode_config.funcs = &intel_mode_funcs;
9024 intel_init_quirks(dev);
9028 if (INTEL_INFO(dev)->num_pipes == 0)
9031 intel_init_display(dev);
9034 dev->mode_config.max_width = 2048;
9035 dev->mode_config.max_height = 2048;
9036 } else if (IS_GEN3(dev)) {
9037 dev->mode_config.max_width = 4096;
9038 dev->mode_config.max_height = 4096;
9040 dev->mode_config.max_width = 8192;
9041 dev->mode_config.max_height = 8192;
9043 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9045 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9046 INTEL_INFO(dev)->num_pipes,
9047 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9049 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9050 intel_crtc_init(dev, i);
9051 for (j = 0; j < dev_priv->num_plane; j++) {
9052 ret = intel_plane_init(dev, i, j);
9054 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9055 pipe_name(i), sprite_name(i, j), ret);
9059 intel_cpu_pll_init(dev);
9060 intel_pch_pll_init(dev);
9062 /* Just disable it once at startup */
9063 i915_disable_vga(dev);
9064 intel_setup_outputs(dev);
9066 /* Just in case the BIOS is doing something questionable. */
9067 intel_disable_fbc(dev);
9071 intel_connector_break_all_links(struct intel_connector *connector)
9073 connector->base.dpms = DRM_MODE_DPMS_OFF;
9074 connector->base.encoder = NULL;
9075 connector->encoder->connectors_active = false;
9076 connector->encoder->base.crtc = NULL;
9079 static void intel_enable_pipe_a(struct drm_device *dev)
9081 struct intel_connector *connector;
9082 struct drm_connector *crt = NULL;
9083 struct intel_load_detect_pipe load_detect_temp;
9085 /* We can't just switch on the pipe A, we need to set things up with a
9086 * proper mode and output configuration. As a gross hack, enable pipe A
9087 * by enabling the load detect pipe once. */
9088 list_for_each_entry(connector,
9089 &dev->mode_config.connector_list,
9091 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9092 crt = &connector->base;
9100 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9101 intel_release_load_detect_pipe(crt, &load_detect_temp);
9107 intel_check_plane_mapping(struct intel_crtc *crtc)
9109 struct drm_device *dev = crtc->base.dev;
9110 struct drm_i915_private *dev_priv = dev->dev_private;
9113 if (INTEL_INFO(dev)->num_pipes == 1)
9116 reg = DSPCNTR(!crtc->plane);
9117 val = I915_READ(reg);
9119 if ((val & DISPLAY_PLANE_ENABLE) &&
9120 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9126 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9128 struct drm_device *dev = crtc->base.dev;
9129 struct drm_i915_private *dev_priv = dev->dev_private;
9132 /* Clear any frame start delays used for debugging left by the BIOS */
9133 reg = PIPECONF(crtc->config.cpu_transcoder);
9134 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9136 /* We need to sanitize the plane -> pipe mapping first because this will
9137 * disable the crtc (and hence change the state) if it is wrong. Note
9138 * that gen4+ has a fixed plane -> pipe mapping. */
9139 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9140 struct intel_connector *connector;
9143 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9144 crtc->base.base.id);
9146 /* Pipe has the wrong plane attached and the plane is active.
9147 * Temporarily change the plane mapping and disable everything
9149 plane = crtc->plane;
9150 crtc->plane = !plane;
9151 dev_priv->display.crtc_disable(&crtc->base);
9152 crtc->plane = plane;
9154 /* ... and break all links. */
9155 list_for_each_entry(connector, &dev->mode_config.connector_list,
9157 if (connector->encoder->base.crtc != &crtc->base)
9160 intel_connector_break_all_links(connector);
9163 WARN_ON(crtc->active);
9164 crtc->base.enabled = false;
9167 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9168 crtc->pipe == PIPE_A && !crtc->active) {
9169 /* BIOS forgot to enable pipe A, this mostly happens after
9170 * resume. Force-enable the pipe to fix this, the update_dpms
9171 * call below we restore the pipe to the right state, but leave
9172 * the required bits on. */
9173 intel_enable_pipe_a(dev);
9176 /* Adjust the state of the output pipe according to whether we
9177 * have active connectors/encoders. */
9178 intel_crtc_update_dpms(&crtc->base);
9180 if (crtc->active != crtc->base.enabled) {
9181 struct intel_encoder *encoder;
9183 /* This can happen either due to bugs in the get_hw_state
9184 * functions or because the pipe is force-enabled due to the
9186 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9188 crtc->base.enabled ? "enabled" : "disabled",
9189 crtc->active ? "enabled" : "disabled");
9191 crtc->base.enabled = crtc->active;
9193 /* Because we only establish the connector -> encoder ->
9194 * crtc links if something is active, this means the
9195 * crtc is now deactivated. Break the links. connector
9196 * -> encoder links are only establish when things are
9197 * actually up, hence no need to break them. */
9198 WARN_ON(crtc->active);
9200 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9201 WARN_ON(encoder->connectors_active);
9202 encoder->base.crtc = NULL;
9207 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9209 struct intel_connector *connector;
9210 struct drm_device *dev = encoder->base.dev;
9212 /* We need to check both for a crtc link (meaning that the
9213 * encoder is active and trying to read from a pipe) and the
9214 * pipe itself being active. */
9215 bool has_active_crtc = encoder->base.crtc &&
9216 to_intel_crtc(encoder->base.crtc)->active;
9218 if (encoder->connectors_active && !has_active_crtc) {
9219 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9220 encoder->base.base.id,
9221 drm_get_encoder_name(&encoder->base));
9223 /* Connector is active, but has no active pipe. This is
9224 * fallout from our resume register restoring. Disable
9225 * the encoder manually again. */
9226 if (encoder->base.crtc) {
9227 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9228 encoder->base.base.id,
9229 drm_get_encoder_name(&encoder->base));
9230 encoder->disable(encoder);
9233 /* Inconsistent output/port/pipe state happens presumably due to
9234 * a bug in one of the get_hw_state functions. Or someplace else
9235 * in our code, like the register restore mess on resume. Clamp
9236 * things to off as a safer default. */
9237 list_for_each_entry(connector,
9238 &dev->mode_config.connector_list,
9240 if (connector->encoder != encoder)
9243 intel_connector_break_all_links(connector);
9246 /* Enabled encoders without active connectors will be fixed in
9247 * the crtc fixup. */
9250 void i915_redisable_vga(struct drm_device *dev)
9252 struct drm_i915_private *dev_priv = dev->dev_private;
9253 u32 vga_reg = i915_vgacntrl_reg(dev);
9255 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9256 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9257 i915_disable_vga(dev);
9261 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9262 * and i915 state tracking structures. */
9263 void intel_modeset_setup_hw_state(struct drm_device *dev,
9266 struct drm_i915_private *dev_priv = dev->dev_private;
9269 struct drm_plane *plane;
9270 struct intel_crtc *crtc;
9271 struct intel_encoder *encoder;
9272 struct intel_connector *connector;
9275 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9277 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9278 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9279 case TRANS_DDI_EDP_INPUT_A_ON:
9280 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9283 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9286 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9290 /* A bogus value has been programmed, disable
9292 WARN(1, "Bogus eDP source %08x\n", tmp);
9293 intel_ddi_disable_transcoder_func(dev_priv,
9298 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9299 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9301 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9307 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9309 enum transcoder tmp = crtc->config.cpu_transcoder;
9310 memset(&crtc->config, 0, sizeof(crtc->config));
9311 crtc->config.cpu_transcoder = tmp;
9313 crtc->active = dev_priv->display.get_pipe_config(crtc,
9316 crtc->base.enabled = crtc->active;
9318 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9320 crtc->active ? "enabled" : "disabled");
9324 intel_ddi_setup_hw_pll_state(dev);
9326 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9330 if (encoder->get_hw_state(encoder, &pipe)) {
9331 encoder->base.crtc =
9332 dev_priv->pipe_to_crtc_mapping[pipe];
9334 encoder->base.crtc = NULL;
9337 encoder->connectors_active = false;
9338 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9339 encoder->base.base.id,
9340 drm_get_encoder_name(&encoder->base),
9341 encoder->base.crtc ? "enabled" : "disabled",
9345 list_for_each_entry(connector, &dev->mode_config.connector_list,
9347 if (connector->get_hw_state(connector)) {
9348 connector->base.dpms = DRM_MODE_DPMS_ON;
9349 connector->encoder->connectors_active = true;
9350 connector->base.encoder = &connector->encoder->base;
9352 connector->base.dpms = DRM_MODE_DPMS_OFF;
9353 connector->base.encoder = NULL;
9355 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9356 connector->base.base.id,
9357 drm_get_connector_name(&connector->base),
9358 connector->base.encoder ? "enabled" : "disabled");
9361 /* HW state is read out, now we need to sanitize this mess. */
9362 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9364 intel_sanitize_encoder(encoder);
9367 for_each_pipe(pipe) {
9368 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9369 intel_sanitize_crtc(crtc);
9372 if (force_restore) {
9374 * We need to use raw interfaces for restoring state to avoid
9375 * checking (bogus) intermediate states.
9377 for_each_pipe(pipe) {
9378 struct drm_crtc *crtc =
9379 dev_priv->pipe_to_crtc_mapping[pipe];
9381 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9384 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9385 intel_plane_restore(plane);
9387 i915_redisable_vga(dev);
9389 intel_modeset_update_staged_output_state(dev);
9392 intel_modeset_check_state(dev);
9394 drm_mode_config_reset(dev);
9397 void intel_modeset_gem_init(struct drm_device *dev)
9399 intel_modeset_init_hw(dev);
9401 intel_setup_overlay(dev);
9403 intel_modeset_setup_hw_state(dev, false);
9406 void intel_modeset_cleanup(struct drm_device *dev)
9408 struct drm_i915_private *dev_priv = dev->dev_private;
9409 struct drm_crtc *crtc;
9410 struct intel_crtc *intel_crtc;
9412 drm_kms_helper_poll_fini(dev);
9413 mutex_lock(&dev->struct_mutex);
9415 intel_unregister_dsm_handler();
9418 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9419 /* Skip inactive CRTCs */
9423 intel_crtc = to_intel_crtc(crtc);
9424 intel_increase_pllclock(crtc);
9427 intel_disable_fbc(dev);
9429 intel_disable_gt_powersave(dev);
9431 ironlake_teardown_rc6(dev);
9433 if (IS_VALLEYVIEW(dev))
9436 mutex_unlock(&dev->struct_mutex);
9438 /* Disable the irq before mode object teardown, for the irq might
9439 * enqueue unpin/hotplug work. */
9440 drm_irq_uninstall(dev);
9441 cancel_work_sync(&dev_priv->hotplug_work);
9442 cancel_work_sync(&dev_priv->rps.work);
9444 /* flush any delayed tasks or pending work */
9445 flush_scheduled_work();
9447 /* destroy backlight, if any, before the connectors */
9448 intel_panel_destroy_backlight(dev);
9450 drm_mode_config_cleanup(dev);
9452 intel_cleanup_overlay(dev);
9456 * Return which encoder is currently attached for connector.
9458 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9460 return &intel_attached_encoder(connector)->base;
9463 void intel_connector_attach_encoder(struct intel_connector *connector,
9464 struct intel_encoder *encoder)
9466 connector->encoder = encoder;
9467 drm_mode_connector_attach_encoder(&connector->base,
9472 * set vga decode state - true == enable VGA decode
9474 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9476 struct drm_i915_private *dev_priv = dev->dev_private;
9479 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9481 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9483 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9484 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9488 #ifdef CONFIG_DEBUG_FS
9489 #include <linux/seq_file.h>
9491 struct intel_display_error_state {
9492 struct intel_cursor_error_state {
9497 } cursor[I915_MAX_PIPES];
9499 struct intel_pipe_error_state {
9509 } pipe[I915_MAX_PIPES];
9511 struct intel_plane_error_state {
9519 } plane[I915_MAX_PIPES];
9522 struct intel_display_error_state *
9523 intel_display_capture_error_state(struct drm_device *dev)
9525 drm_i915_private_t *dev_priv = dev->dev_private;
9526 struct intel_display_error_state *error;
9527 enum transcoder cpu_transcoder;
9530 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9535 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9537 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9538 error->cursor[i].control = I915_READ(CURCNTR(i));
9539 error->cursor[i].position = I915_READ(CURPOS(i));
9540 error->cursor[i].base = I915_READ(CURBASE(i));
9542 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9543 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9544 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9547 error->plane[i].control = I915_READ(DSPCNTR(i));
9548 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9549 if (INTEL_INFO(dev)->gen <= 3) {
9550 error->plane[i].size = I915_READ(DSPSIZE(i));
9551 error->plane[i].pos = I915_READ(DSPPOS(i));
9553 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9554 error->plane[i].addr = I915_READ(DSPADDR(i));
9555 if (INTEL_INFO(dev)->gen >= 4) {
9556 error->plane[i].surface = I915_READ(DSPSURF(i));
9557 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9560 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9561 error->pipe[i].source = I915_READ(PIPESRC(i));
9562 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9563 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9564 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9565 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9566 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9567 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9574 intel_display_print_error_state(struct seq_file *m,
9575 struct drm_device *dev,
9576 struct intel_display_error_state *error)
9580 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9582 seq_printf(m, "Pipe [%d]:\n", i);
9583 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9584 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9585 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9586 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9587 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9588 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9589 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9590 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9592 seq_printf(m, "Plane [%d]:\n", i);
9593 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9594 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9595 if (INTEL_INFO(dev)->gen <= 3) {
9596 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9597 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9599 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9600 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9601 if (INTEL_INFO(dev)->gen >= 4) {
9602 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9603 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9606 seq_printf(m, "Cursor [%d]:\n", i);
9607 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9608 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9609 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);