arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21
  22 #include <linux/omap-dma.h>
  23 #include "l3_3xxx.h"
  24 #include "l4_3xxx.h"
  25 #include <linux/platform_data/asoc-ti-mcbsp.h>
  26 #include <linux/platform_data/spi-omap2-mcspi.h>
  27 #include <linux/platform_data/iommu-omap.h>
  28 #include <linux/platform_data/mailbox-omap.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "am35xx.h"
  32
  33 #include "soc.h"
  34 #include "omap_hwmod.h"
  35 #include "omap_hwmod_common_data.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "cm-regbits-34xx.h"
  38
  39 #include "i2c.h"
  40 #include "mmc.h"
  41 #include "wd_timer.h"
  42 #include "serial.h"
  43
  44 /*
  45  * OMAP3xxx hardware module integration data
  46  *
  47  * All of the data in this section should be autogeneratable from the
  48  * TI hardware database or other technical documentation.  Data that
  49  * is driver-specific or driver-kernel integration-specific belongs
  50  * elsewhere.
  51  */
  52
  53 /*
  54  * IP blocks
  55  */
  56
  57 /* L3 */
  58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  59         { .irq = 9 + OMAP_INTC_START, },
  60         { .irq = 10 + OMAP_INTC_START, },
  61         { .irq = -1 },
  62 };
  63
  64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  65         .name           = "l3_main",
  66         .class          = &l3_hwmod_class,
  67         .mpu_irqs       = omap3xxx_l3_main_irqs,
  68         .flags          = HWMOD_NO_IDLEST,
  69 };
  70
  71 /* L4 CORE */
  72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  73         .name           = "l4_core",
  74         .class          = &l4_hwmod_class,
  75         .flags          = HWMOD_NO_IDLEST,
  76 };
  77
  78 /* L4 PER */
  79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  80         .name           = "l4_per",
  81         .class          = &l4_hwmod_class,
  82         .flags          = HWMOD_NO_IDLEST,
  83 };
  84
  85 /* L4 WKUP */
  86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  87         .name           = "l4_wkup",
  88         .class          = &l4_hwmod_class,
  89         .flags          = HWMOD_NO_IDLEST,
  90 };
  91
  92 /* L4 SEC */
  93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  94         .name           = "l4_sec",
  95         .class          = &l4_hwmod_class,
  96         .flags          = HWMOD_NO_IDLEST,
  97 };
  98
  99 /* MPU */
 100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
 101         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 102         { .irq = -1 }
 103 };
 104
 105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 106         .name           = "mpu",
 107         .mpu_irqs       = omap3xxx_mpu_irqs,
 108         .class          = &mpu_hwmod_class,
 109         .main_clk       = "arm_fck",
 110 };
 111
 112 /* IVA2 (IVA2) */
 113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 114         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 115         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 116         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 117 };
 118
 119 static struct omap_hwmod omap3xxx_iva_hwmod = {
 120         .name           = "iva",
 121         .class          = &iva_hwmod_class,
 122         .clkdm_name     = "iva2_clkdm",
 123         .rst_lines      = omap3xxx_iva_resets,
 124         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 125         .main_clk       = "iva2_ck",
 126         .prcm = {
 127                 .omap2 = {
 128                         .module_offs = OMAP3430_IVA2_MOD,
 129                         .prcm_reg_id = 1,
 130                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 131                         .idlest_reg_id = 1,
 132                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 133                 }
 134         },
 135 };
 136
 137 /*
 138  * 'debugss' class
 139  * debug and emulation sub system
 140  */
 141
 142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 143         .name   = "debugss",
 144 };
 145
 146 /* debugss */
 147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 148         .name           = "debugss",
 149         .class          = &omap3xxx_debugss_hwmod_class,
 150         .clkdm_name     = "emu_clkdm",
 151         .main_clk       = "emu_src_ck",
 152         .flags          = HWMOD_NO_IDLEST,
 153 };
 154
 155 /* timer class */
 156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 157         .rev_offs       = 0x0000,
 158         .sysc_offs      = 0x0010,
 159         .syss_offs      = 0x0014,
 160         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 161                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 162                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 163                            SYSS_HAS_RESET_STATUS),
 164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 165         .clockact       = CLOCKACT_TEST_ICLK,
 166         .sysc_fields    = &omap_hwmod_sysc_type1,
 167 };
 168
 169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 170         .name = "timer",
 171         .sysc = &omap3xxx_timer_sysc,
 172 };
 173
 174 /* secure timers dev attribute */
 175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 176         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 177 };
 178
 179 /* always-on timers dev attribute */
 180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 181         .timer_capability       = OMAP_TIMER_ALWON,
 182 };
 183
 184 /* pwm timers dev attribute */
 185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 186         .timer_capability       = OMAP_TIMER_HAS_PWM,
 187 };
 188
 189 /* timers with DSP interrupt dev attribute */
 190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 191         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 192 };
 193
 194 /* pwm timers with DSP interrupt dev attribute */
 195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 196         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 197 };
 198
 199 /* timer1 */
 200 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 201         .name           = "timer1",
 202         .mpu_irqs       = omap2_timer1_mpu_irqs,
 203         .main_clk       = "gpt1_fck",
 204         .prcm           = {
 205                 .omap2 = {
 206                         .prcm_reg_id = 1,
 207                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 208                         .module_offs = WKUP_MOD,
 209                         .idlest_reg_id = 1,
 210                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 211                 },
 212         },
 213         .dev_attr       = &capability_alwon_dev_attr,
 214         .class          = &omap3xxx_timer_hwmod_class,
 215         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 216 };
 217
 218 /* timer2 */
 219 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 220         .name           = "timer2",
 221         .mpu_irqs       = omap2_timer2_mpu_irqs,
 222         .main_clk       = "gpt2_fck",
 223         .prcm           = {
 224                 .omap2 = {
 225                         .prcm_reg_id = 1,
 226                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 227                         .module_offs = OMAP3430_PER_MOD,
 228                         .idlest_reg_id = 1,
 229                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 230                 },
 231         },
 232         .class          = &omap3xxx_timer_hwmod_class,
 233         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 234 };
 235
 236 /* timer3 */
 237 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 238         .name           = "timer3",
 239         .mpu_irqs       = omap2_timer3_mpu_irqs,
 240         .main_clk       = "gpt3_fck",
 241         .prcm           = {
 242                 .omap2 = {
 243                         .prcm_reg_id = 1,
 244                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 245                         .module_offs = OMAP3430_PER_MOD,
 246                         .idlest_reg_id = 1,
 247                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 248                 },
 249         },
 250         .class          = &omap3xxx_timer_hwmod_class,
 251         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 252 };
 253
 254 /* timer4 */
 255 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 256         .name           = "timer4",
 257         .mpu_irqs       = omap2_timer4_mpu_irqs,
 258         .main_clk       = "gpt4_fck",
 259         .prcm           = {
 260                 .omap2 = {
 261                         .prcm_reg_id = 1,
 262                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 263                         .module_offs = OMAP3430_PER_MOD,
 264                         .idlest_reg_id = 1,
 265                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 266                 },
 267         },
 268         .class          = &omap3xxx_timer_hwmod_class,
 269         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 270 };
 271
 272 /* timer5 */
 273 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 274         .name           = "timer5",
 275         .mpu_irqs       = omap2_timer5_mpu_irqs,
 276         .main_clk       = "gpt5_fck",
 277         .prcm           = {
 278                 .omap2 = {
 279                         .prcm_reg_id = 1,
 280                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 281                         .module_offs = OMAP3430_PER_MOD,
 282                         .idlest_reg_id = 1,
 283                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 284                 },
 285         },
 286         .dev_attr       = &capability_dsp_dev_attr,
 287         .class          = &omap3xxx_timer_hwmod_class,
 288         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 289 };
 290
 291 /* timer6 */
 292 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 293         .name           = "timer6",
 294         .mpu_irqs       = omap2_timer6_mpu_irqs,
 295         .main_clk       = "gpt6_fck",
 296         .prcm           = {
 297                 .omap2 = {
 298                         .prcm_reg_id = 1,
 299                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 300                         .module_offs = OMAP3430_PER_MOD,
 301                         .idlest_reg_id = 1,
 302                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 303                 },
 304         },
 305         .dev_attr       = &capability_dsp_dev_attr,
 306         .class          = &omap3xxx_timer_hwmod_class,
 307         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 308 };
 309
 310 /* timer7 */
 311 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 312         .name           = "timer7",
 313         .mpu_irqs       = omap2_timer7_mpu_irqs,
 314         .main_clk       = "gpt7_fck",
 315         .prcm           = {
 316                 .omap2 = {
 317                         .prcm_reg_id = 1,
 318                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 319                         .module_offs = OMAP3430_PER_MOD,
 320                         .idlest_reg_id = 1,
 321                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 322                 },
 323         },
 324         .dev_attr       = &capability_dsp_dev_attr,
 325         .class          = &omap3xxx_timer_hwmod_class,
 326         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 327 };
 328
 329 /* timer8 */
 330 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 331         .name           = "timer8",
 332         .mpu_irqs       = omap2_timer8_mpu_irqs,
 333         .main_clk       = "gpt8_fck",
 334         .prcm           = {
 335                 .omap2 = {
 336                         .prcm_reg_id = 1,
 337                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 338                         .module_offs = OMAP3430_PER_MOD,
 339                         .idlest_reg_id = 1,
 340                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 341                 },
 342         },
 343         .dev_attr       = &capability_dsp_pwm_dev_attr,
 344         .class          = &omap3xxx_timer_hwmod_class,
 345         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 346 };
 347
 348 /* timer9 */
 349 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 350         .name           = "timer9",
 351         .mpu_irqs       = omap2_timer9_mpu_irqs,
 352         .main_clk       = "gpt9_fck",
 353         .prcm           = {
 354                 .omap2 = {
 355                         .prcm_reg_id = 1,
 356                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 357                         .module_offs = OMAP3430_PER_MOD,
 358                         .idlest_reg_id = 1,
 359                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 360                 },
 361         },
 362         .dev_attr       = &capability_pwm_dev_attr,
 363         .class          = &omap3xxx_timer_hwmod_class,
 364         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 365 };
 366
 367 /* timer10 */
 368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 369         .name           = "timer10",
 370         .mpu_irqs       = omap2_timer10_mpu_irqs,
 371         .main_clk       = "gpt10_fck",
 372         .prcm           = {
 373                 .omap2 = {
 374                         .prcm_reg_id = 1,
 375                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 376                         .module_offs = CORE_MOD,
 377                         .idlest_reg_id = 1,
 378                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 379                 },
 380         },
 381         .dev_attr       = &capability_pwm_dev_attr,
 382         .class          = &omap3xxx_timer_hwmod_class,
 383         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 384 };
 385
 386 /* timer11 */
 387 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 388         .name           = "timer11",
 389         .mpu_irqs       = omap2_timer11_mpu_irqs,
 390         .main_clk       = "gpt11_fck",
 391         .prcm           = {
 392                 .omap2 = {
 393                         .prcm_reg_id = 1,
 394                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 395                         .module_offs = CORE_MOD,
 396                         .idlest_reg_id = 1,
 397                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 398                 },
 399         },
 400         .dev_attr       = &capability_pwm_dev_attr,
 401         .class          = &omap3xxx_timer_hwmod_class,
 402         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 403 };
 404
 405 /* timer12 */
 406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 407         { .irq = 95 + OMAP_INTC_START, },
 408         { .irq = -1 },
 409 };
 410
 411 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 412         .name           = "timer12",
 413         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 414         .main_clk       = "gpt12_fck",
 415         .prcm           = {
 416                 .omap2 = {
 417                         .prcm_reg_id = 1,
 418                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 419                         .module_offs = WKUP_MOD,
 420                         .idlest_reg_id = 1,
 421                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 422                 },
 423         },
 424         .dev_attr       = &capability_secure_dev_attr,
 425         .class          = &omap3xxx_timer_hwmod_class,
 426         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 427 };
 428
 429 /*
 430  * 'wd_timer' class
 431  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 432  * overflow condition
 433  */
 434
 435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .syss_offs      = 0x0014,
 439         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 440                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 441                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 442                            SYSS_HAS_RESET_STATUS),
 443         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 444         .sysc_fields    = &omap_hwmod_sysc_type1,
 445 };
 446
 447 /* I2C common */
 448 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 449         .rev_offs       = 0x00,
 450         .sysc_offs      = 0x20,
 451         .syss_offs      = 0x10,
 452         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 453                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 454                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 455         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 456         .clockact       = CLOCKACT_TEST_ICLK,
 457         .sysc_fields    = &omap_hwmod_sysc_type1,
 458 };
 459
 460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 461         .name           = "wd_timer",
 462         .sysc           = &omap3xxx_wd_timer_sysc,
 463         .pre_shutdown   = &omap2_wd_timer_disable,
 464         .reset          = &omap2_wd_timer_reset,
 465 };
 466
 467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 468         .name           = "wd_timer2",
 469         .class          = &omap3xxx_wd_timer_hwmod_class,
 470         .main_clk       = "wdt2_fck",
 471         .prcm           = {
 472                 .omap2 = {
 473                         .prcm_reg_id = 1,
 474                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 475                         .module_offs = WKUP_MOD,
 476                         .idlest_reg_id = 1,
 477                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 478                 },
 479         },
 480         /*
 481          * XXX: Use software supervised mode, HW supervised smartidle seems to
 482          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 483          */
 484         .flags          = HWMOD_SWSUP_SIDLE,
 485 };
 486
 487 /* UART1 */
 488 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 489         .name           = "uart1",
 490         .mpu_irqs       = omap2_uart1_mpu_irqs,
 491         .sdma_reqs      = omap2_uart1_sdma_reqs,
 492         .main_clk       = "uart1_fck",
 493         .flags          = HWMOD_SWSUP_SIDLE_ACT,
 494         .prcm           = {
 495                 .omap2 = {
 496                         .module_offs = CORE_MOD,
 497                         .prcm_reg_id = 1,
 498                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 499                         .idlest_reg_id = 1,
 500                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 501                 },
 502         },
 503         .class          = &omap2_uart_class,
 504 };
 505
 506 /* UART2 */
 507 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 508         .name           = "uart2",
 509         .mpu_irqs       = omap2_uart2_mpu_irqs,
 510         .sdma_reqs      = omap2_uart2_sdma_reqs,
 511         .main_clk       = "uart2_fck",
 512         .flags          = HWMOD_SWSUP_SIDLE_ACT,
 513         .prcm           = {
 514                 .omap2 = {
 515                         .module_offs = CORE_MOD,
 516                         .prcm_reg_id = 1,
 517                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 518                         .idlest_reg_id = 1,
 519                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 520                 },
 521         },
 522         .class          = &omap2_uart_class,
 523 };
 524
 525 /* UART3 */
 526 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 527         .name           = "uart3",
 528         .mpu_irqs       = omap2_uart3_mpu_irqs,
 529         .sdma_reqs      = omap2_uart3_sdma_reqs,
 530         .main_clk       = "uart3_fck",
 531         .flags          = HWMOD_SWSUP_SIDLE_ACT,
 532         .prcm           = {
 533                 .omap2 = {
 534                         .module_offs = OMAP3430_PER_MOD,
 535                         .prcm_reg_id = 1,
 536                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 537                         .idlest_reg_id = 1,
 538                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 539                 },
 540         },
 541         .class          = &omap2_uart_class,
 542 };
 543
 544 /* UART4 */
 545 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 546         { .irq = 80 + OMAP_INTC_START, },
 547         { .irq = -1 },
 548 };
 549
 550 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 551         { .name = "rx", .dma_req = 82, },
 552         { .name = "tx", .dma_req = 81, },
 553         { .dma_req = -1 }
 554 };
 555
 556 static struct omap_hwmod omap36xx_uart4_hwmod = {
 557         .name           = "uart4",
 558         .mpu_irqs       = uart4_mpu_irqs,
 559         .sdma_reqs      = uart4_sdma_reqs,
 560         .main_clk       = "uart4_fck",
 561         .flags          = HWMOD_SWSUP_SIDLE_ACT,
 562         .prcm           = {
 563                 .omap2 = {
 564                         .module_offs = OMAP3430_PER_MOD,
 565                         .prcm_reg_id = 1,
 566                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 567                         .idlest_reg_id = 1,
 568                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 569                 },
 570         },
 571         .class          = &omap2_uart_class,
 572 };
 573
 574 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 575         { .irq = 84 + OMAP_INTC_START, },
 576         { .irq = -1 },
 577 };
 578
 579 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 580         { .name = "rx", .dma_req = 55, },
 581         { .name = "tx", .dma_req = 54, },
 582         { .dma_req = -1 }
 583 };
 584
 585 /*
 586  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 587  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 588  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 589  * should not be needed.  The functional clock structure of the AM35xx
 590  * UART4 is extremely unclear and opaque; it is unclear what the role
 591  * of uart1/2_fck is for the UART4.  Any clarification from either
 592  * empirical testing or the AM3505/3517 hardware designers would be
 593  * most welcome.
 594  */
 595 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 596         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 597 };
 598
 599 static struct omap_hwmod am35xx_uart4_hwmod = {
 600         .name           = "uart4",
 601         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 602         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 603         .main_clk       = "uart4_fck",
 604         .prcm           = {
 605                 .omap2 = {
 606                         .module_offs = CORE_MOD,
 607                         .prcm_reg_id = 1,
 608                         .module_bit = AM35XX_EN_UART4_SHIFT,
 609                         .idlest_reg_id = 1,
 610                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 611                 },
 612         },
 613         .opt_clks       = am35xx_uart4_opt_clks,
 614         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 615         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 616         .class          = &omap2_uart_class,
 617 };
 618
 619 static struct omap_hwmod_class i2c_class = {
 620         .name   = "i2c",
 621         .sysc   = &i2c_sysc,
 622         .rev    = OMAP_I2C_IP_VERSION_1,
 623         .reset  = &omap_i2c_reset,
 624 };
 625
 626 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 627         { .name = "dispc", .dma_req = 5 },
 628         { .name = "dsi1", .dma_req = 74 },
 629         { .dma_req = -1 }
 630 };
 631
 632 /* dss */
 633 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 634         /*
 635          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 636          * driver does not use these clocks.
 637          */
 638         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 639         { .role = "tv_clk", .clk = "dss_tv_fck" },
 640         /* required only on OMAP3430 */
 641         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 642 };
 643
 644 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 645         .name           = "dss_core",
 646         .class          = &omap2_dss_hwmod_class,
 647         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 648         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 649         .prcm           = {
 650                 .omap2 = {
 651                         .prcm_reg_id = 1,
 652                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 653                         .module_offs = OMAP3430_DSS_MOD,
 654                         .idlest_reg_id = 1,
 655                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 656                 },
 657         },
 658         .opt_clks       = dss_opt_clks,
 659         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 660         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 661 };
 662
 663 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 664         .name           = "dss_core",
 665         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 666         .class          = &omap2_dss_hwmod_class,
 667         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 668         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 669         .prcm           = {
 670                 .omap2 = {
 671                         .prcm_reg_id = 1,
 672                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 673                         .module_offs = OMAP3430_DSS_MOD,
 674                         .idlest_reg_id = 1,
 675                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 676                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 677                 },
 678         },
 679         .opt_clks       = dss_opt_clks,
 680         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 681 };
 682
 683 /*
 684  * 'dispc' class
 685  * display controller
 686  */
 687
 688 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 689         .rev_offs       = 0x0000,
 690         .sysc_offs      = 0x0010,
 691         .syss_offs      = 0x0014,
 692         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 693                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 694                            SYSC_HAS_ENAWAKEUP),
 695         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 696                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 697         .sysc_fields    = &omap_hwmod_sysc_type1,
 698 };
 699
 700 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 701         .name   = "dispc",
 702         .sysc   = &omap3_dispc_sysc,
 703 };
 704
 705 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 706         .name           = "dss_dispc",
 707         .class          = &omap3_dispc_hwmod_class,
 708         .mpu_irqs       = omap2_dispc_irqs,
 709         .main_clk       = "dss1_alwon_fck",
 710         .prcm           = {
 711                 .omap2 = {
 712                         .prcm_reg_id = 1,
 713                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 714                         .module_offs = OMAP3430_DSS_MOD,
 715                 },
 716         },
 717         .flags          = HWMOD_NO_IDLEST,
 718         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 719 };
 720
 721 /*
 722  * 'dsi' class
 723  * display serial interface controller
 724  */
 725
 726 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 727         .name = "dsi",
 728 };
 729
 730 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 731         { .irq = 25 + OMAP_INTC_START, },
 732         { .irq = -1 },
 733 };
 734
 735 /* dss_dsi1 */
 736 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 737         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 738 };
 739
 740 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 741         .name           = "dss_dsi1",
 742         .class          = &omap3xxx_dsi_hwmod_class,
 743         .mpu_irqs       = omap3xxx_dsi1_irqs,
 744         .main_clk       = "dss1_alwon_fck",
 745         .prcm           = {
 746                 .omap2 = {
 747                         .prcm_reg_id = 1,
 748                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 749                         .module_offs = OMAP3430_DSS_MOD,
 750                 },
 751         },
 752         .opt_clks       = dss_dsi1_opt_clks,
 753         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 754         .flags          = HWMOD_NO_IDLEST,
 755 };
 756
 757 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 758         { .role = "ick", .clk = "dss_ick" },
 759 };
 760
 761 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 762         .name           = "dss_rfbi",
 763         .class          = &omap2_rfbi_hwmod_class,
 764         .main_clk       = "dss1_alwon_fck",
 765         .prcm           = {
 766                 .omap2 = {
 767                         .prcm_reg_id = 1,
 768                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 769                         .module_offs = OMAP3430_DSS_MOD,
 770                 },
 771         },
 772         .opt_clks       = dss_rfbi_opt_clks,
 773         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 774         .flags          = HWMOD_NO_IDLEST,
 775 };
 776
 777 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 778         /* required only on OMAP3430 */
 779         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 780 };
 781
 782 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 783         .name           = "dss_venc",
 784         .class          = &omap2_venc_hwmod_class,
 785         .main_clk       = "dss_tv_fck",
 786         .prcm           = {
 787                 .omap2 = {
 788                         .prcm_reg_id = 1,
 789                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 790                         .module_offs = OMAP3430_DSS_MOD,
 791                 },
 792         },
 793         .opt_clks       = dss_venc_opt_clks,
 794         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 795         .flags          = HWMOD_NO_IDLEST,
 796 };
 797
 798 /* I2C1 */
 799 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 800         .fifo_depth     = 8, /* bytes */
 801         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_2,
 802 };
 803
 804 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 805         .name           = "i2c1",
 806         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 807         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 808         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 809         .main_clk       = "i2c1_fck",
 810         .prcm           = {
 811                 .omap2 = {
 812                         .module_offs = CORE_MOD,
 813                         .prcm_reg_id = 1,
 814                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 815                         .idlest_reg_id = 1,
 816                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 817                 },
 818         },
 819         .class          = &i2c_class,
 820         .dev_attr       = &i2c1_dev_attr,
 821 };
 822
 823 /* I2C2 */
 824 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 825         .fifo_depth     = 8, /* bytes */
 826         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 827 };
 828
 829 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 830         .name           = "i2c2",
 831         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 832         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 833         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 834         .main_clk       = "i2c2_fck",
 835         .prcm           = {
 836                 .omap2 = {
 837                         .module_offs = CORE_MOD,
 838                         .prcm_reg_id = 1,
 839                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 840                         .idlest_reg_id = 1,
 841                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 842                 },
 843         },
 844         .class          = &i2c_class,
 845         .dev_attr       = &i2c2_dev_attr,
 846 };
 847
 848 /* I2C3 */
 849 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 850         .fifo_depth     = 64, /* bytes */
 851         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 852 };
 853
 854 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 855         { .irq = 61 + OMAP_INTC_START, },
 856         { .irq = -1 },
 857 };
 858
 859 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 860         { .name = "tx", .dma_req = 25 },
 861         { .name = "rx", .dma_req = 26 },
 862         { .dma_req = -1 }
 863 };
 864
 865 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 866         .name           = "i2c3",
 867         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 868         .mpu_irqs       = i2c3_mpu_irqs,
 869         .sdma_reqs      = i2c3_sdma_reqs,
 870         .main_clk       = "i2c3_fck",
 871         .prcm           = {
 872                 .omap2 = {
 873                         .module_offs = CORE_MOD,
 874                         .prcm_reg_id = 1,
 875                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 876                         .idlest_reg_id = 1,
 877                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 878                 },
 879         },
 880         .class          = &i2c_class,
 881         .dev_attr       = &i2c3_dev_attr,
 882 };
 883
 884 /*
 885  * 'gpio' class
 886  * general purpose io module
 887  */
 888
 889 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 890         .rev_offs       = 0x0000,
 891         .sysc_offs      = 0x0010,
 892         .syss_offs      = 0x0014,
 893         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 894                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 895                            SYSS_HAS_RESET_STATUS),
 896         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 897         .sysc_fields    = &omap_hwmod_sysc_type1,
 898 };
 899
 900 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 901         .name = "gpio",
 902         .sysc = &omap3xxx_gpio_sysc,
 903         .rev = 1,
 904 };
 905
 906 /* gpio_dev_attr */
 907 static struct omap_gpio_dev_attr gpio_dev_attr = {
 908         .bank_width = 32,
 909         .dbck_flag = true,
 910 };
 911
 912 /* gpio1 */
 913 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 914         { .role = "dbclk", .clk = "gpio1_dbck", },
 915 };
 916
 917 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 918         .name           = "gpio1",
 919         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 920         .mpu_irqs       = omap2_gpio1_irqs,
 921         .main_clk       = "gpio1_ick",
 922         .opt_clks       = gpio1_opt_clks,
 923         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 924         .prcm           = {
 925                 .omap2 = {
 926                         .prcm_reg_id = 1,
 927                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 928                         .module_offs = WKUP_MOD,
 929                         .idlest_reg_id = 1,
 930                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 931                 },
 932         },
 933         .class          = &omap3xxx_gpio_hwmod_class,
 934         .dev_attr       = &gpio_dev_attr,
 935 };
 936
 937 /* gpio2 */
 938 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 939         { .role = "dbclk", .clk = "gpio2_dbck", },
 940 };
 941
 942 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 943         .name           = "gpio2",
 944         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 945         .mpu_irqs       = omap2_gpio2_irqs,
 946         .main_clk       = "gpio2_ick",
 947         .opt_clks       = gpio2_opt_clks,
 948         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 949         .prcm           = {
 950                 .omap2 = {
 951                         .prcm_reg_id = 1,
 952                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 953                         .module_offs = OMAP3430_PER_MOD,
 954                         .idlest_reg_id = 1,
 955                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 956                 },
 957         },
 958         .class          = &omap3xxx_gpio_hwmod_class,
 959         .dev_attr       = &gpio_dev_attr,
 960 };
 961
 962 /* gpio3 */
 963 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 964         { .role = "dbclk", .clk = "gpio3_dbck", },
 965 };
 966
 967 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 968         .name           = "gpio3",
 969         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 970         .mpu_irqs       = omap2_gpio3_irqs,
 971         .main_clk       = "gpio3_ick",
 972         .opt_clks       = gpio3_opt_clks,
 973         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 974         .prcm           = {
 975                 .omap2 = {
 976                         .prcm_reg_id = 1,
 977                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 978                         .module_offs = OMAP3430_PER_MOD,
 979                         .idlest_reg_id = 1,
 980                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 981                 },
 982         },
 983         .class          = &omap3xxx_gpio_hwmod_class,
 984         .dev_attr       = &gpio_dev_attr,
 985 };
 986
 987 /* gpio4 */
 988 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 989         { .role = "dbclk", .clk = "gpio4_dbck", },
 990 };
 991
 992 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 993         .name           = "gpio4",
 994         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 995         .mpu_irqs       = omap2_gpio4_irqs,
 996         .main_clk       = "gpio4_ick",
 997         .opt_clks       = gpio4_opt_clks,
 998         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 999         .prcm           = {
1000                 .omap2 = {
1001                         .prcm_reg_id = 1,
1002                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1003                         .module_offs = OMAP3430_PER_MOD,
1004                         .idlest_reg_id = 1,
1005                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1006                 },
1007         },
1008         .class          = &omap3xxx_gpio_hwmod_class,
1009         .dev_attr       = &gpio_dev_attr,
1010 };
1011
1012 /* gpio5 */
1013 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1014         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1015         { .irq = -1 },
1016 };
1017
1018 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1019         { .role = "dbclk", .clk = "gpio5_dbck", },
1020 };
1021
1022 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1023         .name           = "gpio5",
1024         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1025         .mpu_irqs       = omap3xxx_gpio5_irqs,
1026         .main_clk       = "gpio5_ick",
1027         .opt_clks       = gpio5_opt_clks,
1028         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1029         .prcm           = {
1030                 .omap2 = {
1031                         .prcm_reg_id = 1,
1032                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1033                         .module_offs = OMAP3430_PER_MOD,
1034                         .idlest_reg_id = 1,
1035                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1036                 },
1037         },
1038         .class          = &omap3xxx_gpio_hwmod_class,
1039         .dev_attr       = &gpio_dev_attr,
1040 };
1041
1042 /* gpio6 */
1043 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1044         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1045         { .irq = -1 },
1046 };
1047
1048 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1049         { .role = "dbclk", .clk = "gpio6_dbck", },
1050 };
1051
1052 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1053         .name           = "gpio6",
1054         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1055         .mpu_irqs       = omap3xxx_gpio6_irqs,
1056         .main_clk       = "gpio6_ick",
1057         .opt_clks       = gpio6_opt_clks,
1058         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1059         .prcm           = {
1060                 .omap2 = {
1061                         .prcm_reg_id = 1,
1062                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1063                         .module_offs = OMAP3430_PER_MOD,
1064                         .idlest_reg_id = 1,
1065                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1066                 },
1067         },
1068         .class          = &omap3xxx_gpio_hwmod_class,
1069         .dev_attr       = &gpio_dev_attr,
1070 };
1071
1072 /* dma attributes */
1073 static struct omap_dma_dev_attr dma_dev_attr = {
1074         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1075                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1076         .lch_count = 32,
1077 };
1078
1079 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1080         .rev_offs       = 0x0000,
1081         .sysc_offs      = 0x002c,
1082         .syss_offs      = 0x0028,
1083         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1084                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1085                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1086                            SYSS_HAS_RESET_STATUS),
1087         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1088                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1089         .sysc_fields    = &omap_hwmod_sysc_type1,
1090 };
1091
1092 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1093         .name = "dma",
1094         .sysc = &omap3xxx_dma_sysc,
1095 };
1096
1097 /* dma_system */
1098 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1099         .name           = "dma",
1100         .class          = &omap3xxx_dma_hwmod_class,
1101         .mpu_irqs       = omap2_dma_system_irqs,
1102         .main_clk       = "core_l3_ick",
1103         .prcm = {
1104                 .omap2 = {
1105                         .module_offs            = CORE_MOD,
1106                         .prcm_reg_id            = 1,
1107                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1108                         .idlest_reg_id          = 1,
1109                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1110                 },
1111         },
1112         .dev_attr       = &dma_dev_attr,
1113         .flags          = HWMOD_NO_IDLEST,
1114 };
1115
1116 /*
1117  * 'mcbsp' class
1118  * multi channel buffered serial port controller
1119  */
1120
1121 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1122         .sysc_offs      = 0x008c,
1123         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1124                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1125         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1126         .sysc_fields    = &omap_hwmod_sysc_type1,
1127         .clockact       = 0x2,
1128 };
1129
1130 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1131         .name = "mcbsp",
1132         .sysc = &omap3xxx_mcbsp_sysc,
1133         .rev  = MCBSP_CONFIG_TYPE3,
1134 };
1135
1136 /* McBSP functional clock mapping */
1137 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1138         { .role = "pad_fck", .clk = "mcbsp_clks" },
1139         { .role = "prcm_fck", .clk = "core_96m_fck" },
1140 };
1141
1142 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1143         { .role = "pad_fck", .clk = "mcbsp_clks" },
1144         { .role = "prcm_fck", .clk = "per_96m_fck" },
1145 };
1146
1147 /* mcbsp1 */
1148 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1149         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1150         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1151         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1152         { .irq = -1 },
1153 };
1154
1155 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1156         .name           = "mcbsp1",
1157         .class          = &omap3xxx_mcbsp_hwmod_class,
1158         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1159         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1160         .main_clk       = "mcbsp1_fck",
1161         .prcm           = {
1162                 .omap2 = {
1163                         .prcm_reg_id = 1,
1164                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1165                         .module_offs = CORE_MOD,
1166                         .idlest_reg_id = 1,
1167                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1168                 },
1169         },
1170         .opt_clks       = mcbsp15_opt_clks,
1171         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1172 };
1173
1174 /* mcbsp2 */
1175 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1176         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1177         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1178         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1179         { .irq = -1 },
1180 };
1181
1182 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1183         .sidetone       = "mcbsp2_sidetone",
1184 };
1185
1186 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1187         .name           = "mcbsp2",
1188         .class          = &omap3xxx_mcbsp_hwmod_class,
1189         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1190         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1191         .main_clk       = "mcbsp2_fck",
1192         .prcm           = {
1193                 .omap2 = {
1194                         .prcm_reg_id = 1,
1195                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1196                         .module_offs = OMAP3430_PER_MOD,
1197                         .idlest_reg_id = 1,
1198                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1199                 },
1200         },
1201         .opt_clks       = mcbsp234_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1203         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1204 };
1205
1206 /* mcbsp3 */
1207 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1208         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1209         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1210         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1211         { .irq = -1 },
1212 };
1213
1214 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1215         .sidetone       = "mcbsp3_sidetone",
1216 };
1217
1218 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1219         .name           = "mcbsp3",
1220         .class          = &omap3xxx_mcbsp_hwmod_class,
1221         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1222         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1223         .main_clk       = "mcbsp3_fck",
1224         .prcm           = {
1225                 .omap2 = {
1226                         .prcm_reg_id = 1,
1227                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1228                         .module_offs = OMAP3430_PER_MOD,
1229                         .idlest_reg_id = 1,
1230                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1231                 },
1232         },
1233         .opt_clks       = mcbsp234_opt_clks,
1234         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1235         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1236 };
1237
1238 /* mcbsp4 */
1239 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1240         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1241         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1242         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1243         { .irq = -1 },
1244 };
1245
1246 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1247         { .name = "rx", .dma_req = 20 },
1248         { .name = "tx", .dma_req = 19 },
1249         { .dma_req = -1 }
1250 };
1251
1252 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1253         .name           = "mcbsp4",
1254         .class          = &omap3xxx_mcbsp_hwmod_class,
1255         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1256         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1257         .main_clk       = "mcbsp4_fck",
1258         .prcm           = {
1259                 .omap2 = {
1260                         .prcm_reg_id = 1,
1261                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1262                         .module_offs = OMAP3430_PER_MOD,
1263                         .idlest_reg_id = 1,
1264                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1265                 },
1266         },
1267         .opt_clks       = mcbsp234_opt_clks,
1268         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1269 };
1270
1271 /* mcbsp5 */
1272 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1273         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1274         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1275         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1276         { .irq = -1 },
1277 };
1278
1279 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1280         { .name = "rx", .dma_req = 22 },
1281         { .name = "tx", .dma_req = 21 },
1282         { .dma_req = -1 }
1283 };
1284
1285 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1286         .name           = "mcbsp5",
1287         .class          = &omap3xxx_mcbsp_hwmod_class,
1288         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1289         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1290         .main_clk       = "mcbsp5_fck",
1291         .prcm           = {
1292                 .omap2 = {
1293                         .prcm_reg_id = 1,
1294                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1295                         .module_offs = CORE_MOD,
1296                         .idlest_reg_id = 1,
1297                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1298                 },
1299         },
1300         .opt_clks       = mcbsp15_opt_clks,
1301         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1302 };
1303
1304 /* 'mcbsp sidetone' class */
1305 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1306         .sysc_offs      = 0x0010,
1307         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1308         .sysc_fields    = &omap_hwmod_sysc_type1,
1309 };
1310
1311 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1312         .name = "mcbsp_sidetone",
1313         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1314 };
1315
1316 /* mcbsp2_sidetone */
1317 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1318         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1319         { .irq = -1 },
1320 };
1321
1322 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1323         .name           = "mcbsp2_sidetone",
1324         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1325         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1326         .main_clk       = "mcbsp2_fck",
1327         .prcm           = {
1328                 .omap2 = {
1329                         .prcm_reg_id = 1,
1330                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1331                         .module_offs = OMAP3430_PER_MOD,
1332                         .idlest_reg_id = 1,
1333                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1334                 },
1335         },
1336 };
1337
1338 /* mcbsp3_sidetone */
1339 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1340         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1341         { .irq = -1 },
1342 };
1343
1344 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1345         .name           = "mcbsp3_sidetone",
1346         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1347         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1348         .main_clk       = "mcbsp3_fck",
1349         .prcm           = {
1350                 .omap2 = {
1351                         .prcm_reg_id = 1,
1352                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1353                         .module_offs = OMAP3430_PER_MOD,
1354                         .idlest_reg_id = 1,
1355                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1356                 },
1357         },
1358 };
1359
1360 /* SR common */
1361 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1362         .clkact_shift   = 20,
1363 };
1364
1365 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1366         .sysc_offs      = 0x24,
1367         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1368         .clockact       = CLOCKACT_TEST_ICLK,
1369         .sysc_fields    = &omap34xx_sr_sysc_fields,
1370 };
1371
1372 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1373         .name = "smartreflex",
1374         .sysc = &omap34xx_sr_sysc,
1375         .rev  = 1,
1376 };
1377
1378 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1379         .sidle_shift    = 24,
1380         .enwkup_shift   = 26,
1381 };
1382
1383 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1384         .sysc_offs      = 0x38,
1385         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1386         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1387                         SYSC_NO_CACHE),
1388         .sysc_fields    = &omap36xx_sr_sysc_fields,
1389 };
1390
1391 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1392         .name = "smartreflex",
1393         .sysc = &omap36xx_sr_sysc,
1394         .rev  = 2,
1395 };
1396
1397 /* SR1 */
1398 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1399         .sensor_voltdm_name   = "mpu_iva",
1400 };
1401
1402 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1403         { .irq = 18 + OMAP_INTC_START, },
1404         { .irq = -1 },
1405 };
1406
1407 static struct omap_hwmod omap34xx_sr1_hwmod = {
1408         .name           = "smartreflex_mpu_iva",
1409         .class          = &omap34xx_smartreflex_hwmod_class,
1410         .main_clk       = "sr1_fck",
1411         .prcm           = {
1412                 .omap2 = {
1413                         .prcm_reg_id = 1,
1414                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1415                         .module_offs = WKUP_MOD,
1416                         .idlest_reg_id = 1,
1417                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1418                 },
1419         },
1420         .dev_attr       = &sr1_dev_attr,
1421         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1422         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1423 };
1424
1425 static struct omap_hwmod omap36xx_sr1_hwmod = {
1426         .name           = "smartreflex_mpu_iva",
1427         .class          = &omap36xx_smartreflex_hwmod_class,
1428         .main_clk       = "sr1_fck",
1429         .prcm           = {
1430                 .omap2 = {
1431                         .prcm_reg_id = 1,
1432                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1433                         .module_offs = WKUP_MOD,
1434                         .idlest_reg_id = 1,
1435                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1436                 },
1437         },
1438         .dev_attr       = &sr1_dev_attr,
1439         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1440 };
1441
1442 /* SR2 */
1443 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1444         .sensor_voltdm_name     = "core",
1445 };
1446
1447 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1448         { .irq = 19 + OMAP_INTC_START, },
1449         { .irq = -1 },
1450 };
1451
1452 static struct omap_hwmod omap34xx_sr2_hwmod = {
1453         .name           = "smartreflex_core",
1454         .class          = &omap34xx_smartreflex_hwmod_class,
1455         .main_clk       = "sr2_fck",
1456         .prcm           = {
1457                 .omap2 = {
1458                         .prcm_reg_id = 1,
1459                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1460                         .module_offs = WKUP_MOD,
1461                         .idlest_reg_id = 1,
1462                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1463                 },
1464         },
1465         .dev_attr       = &sr2_dev_attr,
1466         .mpu_irqs       = omap3_smartreflex_core_irqs,
1467         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1468 };
1469
1470 static struct omap_hwmod omap36xx_sr2_hwmod = {
1471         .name           = "smartreflex_core",
1472         .class          = &omap36xx_smartreflex_hwmod_class,
1473         .main_clk       = "sr2_fck",
1474         .prcm           = {
1475                 .omap2 = {
1476                         .prcm_reg_id = 1,
1477                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1478                         .module_offs = WKUP_MOD,
1479                         .idlest_reg_id = 1,
1480                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1481                 },
1482         },
1483         .dev_attr       = &sr2_dev_attr,
1484         .mpu_irqs       = omap3_smartreflex_core_irqs,
1485 };
1486
1487 /*
1488  * 'mailbox' class
1489  * mailbox module allowing communication between the on-chip processors
1490  * using a queued mailbox-interrupt mechanism.
1491  */
1492
1493 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1494         .rev_offs       = 0x000,
1495         .sysc_offs      = 0x010,
1496         .syss_offs      = 0x014,
1497         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1498                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1499         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1500         .sysc_fields    = &omap_hwmod_sysc_type1,
1501 };
1502
1503 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1504         .name = "mailbox",
1505         .sysc = &omap3xxx_mailbox_sysc,
1506 };
1507
1508 static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
1509         { .name = "dsp", .tx_id = 0, .rx_id = 1 },
1510 };
1511
1512 static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
1513         .num_users      = 2,
1514         .num_fifos      = 2,
1515         .info_cnt       = ARRAY_SIZE(omap3xxx_mailbox_info),
1516         .info           = omap3xxx_mailbox_info,
1517 };
1518
1519 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1520         { .irq = 26 + OMAP_INTC_START, },
1521         { .irq = -1 },
1522 };
1523
1524 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1525         .name           = "mailbox",
1526         .class          = &omap3xxx_mailbox_hwmod_class,
1527         .mpu_irqs       = omap3xxx_mailbox_irqs,
1528         .main_clk       = "mailboxes_ick",
1529         .prcm           = {
1530                 .omap2 = {
1531                         .prcm_reg_id = 1,
1532                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1533                         .module_offs = CORE_MOD,
1534                         .idlest_reg_id = 1,
1535                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1536                 },
1537         },
1538         .dev_attr       = &omap3xxx_mailbox_attrs,
1539 };
1540
1541 /*
1542  * 'mcspi' class
1543  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1544  * bus
1545  */
1546
1547 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1548         .rev_offs       = 0x0000,
1549         .sysc_offs      = 0x0010,
1550         .syss_offs      = 0x0014,
1551         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1552                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1553                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1554         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1555         .sysc_fields    = &omap_hwmod_sysc_type1,
1556 };
1557
1558 static struct omap_hwmod_class omap34xx_mcspi_class = {
1559         .name = "mcspi",
1560         .sysc = &omap34xx_mcspi_sysc,
1561         .rev = OMAP3_MCSPI_REV,
1562 };
1563
1564 /* mcspi1 */
1565 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1566         .num_chipselect = 4,
1567 };
1568
1569 static struct omap_hwmod omap34xx_mcspi1 = {
1570         .name           = "mcspi1",
1571         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1572         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1573         .main_clk       = "mcspi1_fck",
1574         .prcm           = {
1575                 .omap2 = {
1576                         .module_offs = CORE_MOD,
1577                         .prcm_reg_id = 1,
1578                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1579                         .idlest_reg_id = 1,
1580                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1581                 },
1582         },
1583         .class          = &omap34xx_mcspi_class,
1584         .dev_attr       = &omap_mcspi1_dev_attr,
1585 };
1586
1587 /* mcspi2 */
1588 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1589         .num_chipselect = 2,
1590 };
1591
1592 static struct omap_hwmod omap34xx_mcspi2 = {
1593         .name           = "mcspi2",
1594         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1595         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1596         .main_clk       = "mcspi2_fck",
1597         .prcm           = {
1598                 .omap2 = {
1599                         .module_offs = CORE_MOD,
1600                         .prcm_reg_id = 1,
1601                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1602                         .idlest_reg_id = 1,
1603                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1604                 },
1605         },
1606         .class          = &omap34xx_mcspi_class,
1607         .dev_attr       = &omap_mcspi2_dev_attr,
1608 };
1609
1610 /* mcspi3 */
1611 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1612         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1613         { .irq = -1 },
1614 };
1615
1616 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1617         { .name = "tx0", .dma_req = 15 },
1618         { .name = "rx0", .dma_req = 16 },
1619         { .name = "tx1", .dma_req = 23 },
1620         { .name = "rx1", .dma_req = 24 },
1621         { .dma_req = -1 }
1622 };
1623
1624 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1625         .num_chipselect = 2,
1626 };
1627
1628 static struct omap_hwmod omap34xx_mcspi3 = {
1629         .name           = "mcspi3",
1630         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1631         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1632         .main_clk       = "mcspi3_fck",
1633         .prcm           = {
1634                 .omap2 = {
1635                         .module_offs = CORE_MOD,
1636                         .prcm_reg_id = 1,
1637                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1638                         .idlest_reg_id = 1,
1639                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1640                 },
1641         },
1642         .class          = &omap34xx_mcspi_class,
1643         .dev_attr       = &omap_mcspi3_dev_attr,
1644 };
1645
1646 /* mcspi4 */
1647 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1648         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1649         { .irq = -1 },
1650 };
1651
1652 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1653         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1654         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1655         { .dma_req = -1 }
1656 };
1657
1658 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1659         .num_chipselect = 1,
1660 };
1661
1662 static struct omap_hwmod omap34xx_mcspi4 = {
1663         .name           = "mcspi4",
1664         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1665         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1666         .main_clk       = "mcspi4_fck",
1667         .prcm           = {
1668                 .omap2 = {
1669                         .module_offs = CORE_MOD,
1670                         .prcm_reg_id = 1,
1671                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1672                         .idlest_reg_id = 1,
1673                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1674                 },
1675         },
1676         .class          = &omap34xx_mcspi_class,
1677         .dev_attr       = &omap_mcspi4_dev_attr,
1678 };
1679
1680 /* usbhsotg */
1681 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1682         .rev_offs       = 0x0400,
1683         .sysc_offs      = 0x0404,
1684         .syss_offs      = 0x0408,
1685         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1686                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1687                           SYSC_HAS_AUTOIDLE),
1688         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1689                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1690         .sysc_fields    = &omap_hwmod_sysc_type1,
1691 };
1692
1693 static struct omap_hwmod_class usbotg_class = {
1694         .name = "usbotg",
1695         .sysc = &omap3xxx_usbhsotg_sysc,
1696 };
1697
1698 /* usb_otg_hs */
1699 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1700
1701         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1702         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1703         { .irq = -1 },
1704 };
1705
1706 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1707         .name           = "usb_otg_hs",
1708         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1709         .main_clk       = "hsotgusb_ick",
1710         .prcm           = {
1711                 .omap2 = {
1712                         .prcm_reg_id = 1,
1713                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1714                         .module_offs = CORE_MOD,
1715                         .idlest_reg_id = 1,
1716                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1717                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1718                 },
1719         },
1720         .class          = &usbotg_class,
1721
1722         /*
1723          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1724          * broken when autoidle is enabled
1725          * workaround is to disable the autoidle bit at module level.
1726          *
1727          * Enabling the device in any other MIDLEMODE setting but force-idle
1728          * causes core_pwrdm not enter idle states at least on OMAP3630.
1729          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1730          * signal when MIDLEMODE is set to force-idle.
1731          */
1732         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1733                                 | HWMOD_FORCE_MSTANDBY,
1734 };
1735
1736 /* usb_otg_hs */
1737 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1738         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1739         { .irq = -1 },
1740 };
1741
1742 static struct omap_hwmod_class am35xx_usbotg_class = {
1743         .name = "am35xx_usbotg",
1744 };
1745
1746 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1747         .name           = "am35x_otg_hs",
1748         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1749         .main_clk       = "hsotgusb_fck",
1750         .class          = &am35xx_usbotg_class,
1751         .flags          = HWMOD_NO_IDLEST,
1752 };
1753
1754 /* MMC/SD/SDIO common */
1755 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1756         .rev_offs       = 0x1fc,
1757         .sysc_offs      = 0x10,
1758         .syss_offs      = 0x14,
1759         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1760                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1761                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1762         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1763         .sysc_fields    = &omap_hwmod_sysc_type1,
1764 };
1765
1766 static struct omap_hwmod_class omap34xx_mmc_class = {
1767         .name = "mmc",
1768         .sysc = &omap34xx_mmc_sysc,
1769 };
1770
1771 /* MMC/SD/SDIO1 */
1772
1773 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1774         { .irq = 83 + OMAP_INTC_START, },
1775         { .irq = -1 },
1776 };
1777
1778 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1779         { .name = "tx", .dma_req = 61, },
1780         { .name = "rx", .dma_req = 62, },
1781         { .dma_req = -1 }
1782 };
1783
1784 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1785         { .role = "dbck", .clk = "omap_32k_fck", },
1786 };
1787
1788 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1789         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1790 };
1791
1792 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1793 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1794         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1795                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1796 };
1797
1798 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1799         .name           = "mmc1",
1800         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1801         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1802         .opt_clks       = omap34xx_mmc1_opt_clks,
1803         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1804         .main_clk       = "mmchs1_fck",
1805         .prcm           = {
1806                 .omap2 = {
1807                         .module_offs = CORE_MOD,
1808                         .prcm_reg_id = 1,
1809                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1810                         .idlest_reg_id = 1,
1811                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1812                 },
1813         },
1814         .dev_attr       = &mmc1_pre_es3_dev_attr,
1815         .class          = &omap34xx_mmc_class,
1816 };
1817
1818 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1819         .name           = "mmc1",
1820         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1821         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1822         .opt_clks       = omap34xx_mmc1_opt_clks,
1823         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1824         .main_clk       = "mmchs1_fck",
1825         .prcm           = {
1826                 .omap2 = {
1827                         .module_offs = CORE_MOD,
1828                         .prcm_reg_id = 1,
1829                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1830                         .idlest_reg_id = 1,
1831                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1832                 },
1833         },
1834         .dev_attr       = &mmc1_dev_attr,
1835         .class          = &omap34xx_mmc_class,
1836 };
1837
1838 /* MMC/SD/SDIO2 */
1839
1840 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1841         { .irq = 86 + OMAP_INTC_START, },
1842         { .irq = -1 },
1843 };
1844
1845 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1846         { .name = "tx", .dma_req = 47, },
1847         { .name = "rx", .dma_req = 48, },
1848         { .dma_req = -1 }
1849 };
1850
1851 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1852         { .role = "dbck", .clk = "omap_32k_fck", },
1853 };
1854
1855 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1856 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1857         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1858 };
1859
1860 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1861         .name           = "mmc2",
1862         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1863         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1864         .opt_clks       = omap34xx_mmc2_opt_clks,
1865         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1866         .main_clk       = "mmchs2_fck",
1867         .prcm           = {
1868                 .omap2 = {
1869                         .module_offs = CORE_MOD,
1870                         .prcm_reg_id = 1,
1871                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1872                         .idlest_reg_id = 1,
1873                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1874                 },
1875         },
1876         .dev_attr       = &mmc2_pre_es3_dev_attr,
1877         .class          = &omap34xx_mmc_class,
1878 };
1879
1880 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1881         .name           = "mmc2",
1882         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1883         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1884         .opt_clks       = omap34xx_mmc2_opt_clks,
1885         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1886         .main_clk       = "mmchs2_fck",
1887         .prcm           = {
1888                 .omap2 = {
1889                         .module_offs = CORE_MOD,
1890                         .prcm_reg_id = 1,
1891                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1892                         .idlest_reg_id = 1,
1893                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1894                 },
1895         },
1896         .class          = &omap34xx_mmc_class,
1897 };
1898
1899 /* MMC/SD/SDIO3 */
1900
1901 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1902         { .irq = 94 + OMAP_INTC_START, },
1903         { .irq = -1 },
1904 };
1905
1906 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1907         { .name = "tx", .dma_req = 77, },
1908         { .name = "rx", .dma_req = 78, },
1909         { .dma_req = -1 }
1910 };
1911
1912 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1913         { .role = "dbck", .clk = "omap_32k_fck", },
1914 };
1915
1916 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1917         .name           = "mmc3",
1918         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1919         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1920         .opt_clks       = omap34xx_mmc3_opt_clks,
1921         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1922         .main_clk       = "mmchs3_fck",
1923         .prcm           = {
1924                 .omap2 = {
1925                         .prcm_reg_id = 1,
1926                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1927                         .idlest_reg_id = 1,
1928                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1929                 },
1930         },
1931         .class          = &omap34xx_mmc_class,
1932 };
1933
1934 /*
1935  * 'usb_host_hs' class
1936  * high-speed multi-port usb host controller
1937  */
1938
1939 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1940         .rev_offs       = 0x0000,
1941         .sysc_offs      = 0x0010,
1942         .syss_offs      = 0x0014,
1943         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1944                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1945                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1946         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1947                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1948         .sysc_fields    = &omap_hwmod_sysc_type1,
1949 };
1950
1951 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1952         .name = "usb_host_hs",
1953         .sysc = &omap3xxx_usb_host_hs_sysc,
1954 };
1955
1956 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1957           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1958 };
1959
1960 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1961         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1962         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1963         { .irq = -1 },
1964 };
1965
1966 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1967         .name           = "usb_host_hs",
1968         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1969         .clkdm_name     = "l3_init_clkdm",
1970         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1971         .main_clk       = "usbhost_48m_fck",
1972         .prcm = {
1973                 .omap2 = {
1974                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1975                         .prcm_reg_id = 1,
1976                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1977                         .idlest_reg_id = 1,
1978                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1979                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1980                 },
1981         },
1982         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1983         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1984
1985         /*
1986          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1987          * id: i660
1988          *
1989          * Description:
1990          * In the following configuration :
1991          * - USBHOST module is set to smart-idle mode
1992          * - PRCM asserts idle_req to the USBHOST module ( This typically
1993          *   happens when the system is going to a low power mode : all ports
1994          *   have been suspended, the master part of the USBHOST module has
1995          *   entered the standby state, and SW has cut the functional clocks)
1996          * - an USBHOST interrupt occurs before the module is able to answer
1997          *   idle_ack, typically a remote wakeup IRQ.
1998          * Then the USB HOST module will enter a deadlock situation where it
1999          * is no more accessible nor functional.
2000          *
2001          * Workaround:
2002          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2003          */
2004
2005         /*
2006          * Errata: USB host EHCI may stall when entering smart-standby mode
2007          * Id: i571
2008          *
2009          * Description:
2010          * When the USBHOST module is set to smart-standby mode, and when it is
2011          * ready to enter the standby state (i.e. all ports are suspended and
2012          * all attached devices are in suspend mode), then it can wrongly assert
2013          * the Mstandby signal too early while there are still some residual OCP
2014          * transactions ongoing. If this condition occurs, the internal state
2015          * machine may go to an undefined state and the USB link may be stuck
2016          * upon the next resume.
2017          *
2018          * Workaround:
2019          * Don't use smart standby; use only force standby,
2020          * hence HWMOD_SWSUP_MSTANDBY
2021          */
2022
2023         /*
2024          * During system boot; If the hwmod framework resets the module
2025          * the module will have smart idle settings; which can lead to deadlock
2026          * (above Errata Id:i660); so, dont reset the module during boot;
2027          * Use HWMOD_INIT_NO_RESET.
2028          */
2029
2030         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2031                           HWMOD_INIT_NO_RESET,
2032 };
2033
2034 /*
2035  * 'usb_tll_hs' class
2036  * usb_tll_hs module is the adapter on the usb_host_hs ports
2037  */
2038 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2039         .rev_offs       = 0x0000,
2040         .sysc_offs      = 0x0010,
2041         .syss_offs      = 0x0014,
2042         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2043                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2044                            SYSC_HAS_AUTOIDLE),
2045         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2046         .sysc_fields    = &omap_hwmod_sysc_type1,
2047 };
2048
2049 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2050         .name = "usb_tll_hs",
2051         .sysc = &omap3xxx_usb_tll_hs_sysc,
2052 };
2053
2054 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2055         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2056         { .irq = -1 },
2057 };
2058
2059 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2060         .name           = "usb_tll_hs",
2061         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2062         .clkdm_name     = "l3_init_clkdm",
2063         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2064         .main_clk       = "usbtll_fck",
2065         .prcm = {
2066                 .omap2 = {
2067                         .module_offs = CORE_MOD,
2068                         .prcm_reg_id = 3,
2069                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2070                         .idlest_reg_id = 3,
2071                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2072                 },
2073         },
2074 };
2075
2076 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2077         .name           = "hdq1w",
2078         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2079         .main_clk       = "hdq_fck",
2080         .prcm           = {
2081                 .omap2 = {
2082                         .module_offs = CORE_MOD,
2083                         .prcm_reg_id = 1,
2084                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2085                         .idlest_reg_id = 1,
2086                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2087                 },
2088         },
2089         .class          = &omap2_hdq1w_class,
2090 };
2091
2092 /* SAD2D */
2093 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2094         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2095         { .name = "rst_modem_sw", .rst_shift = 1 },
2096 };
2097
2098 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2099         .name                   = "sad2d",
2100 };
2101
2102 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2103         .name           = "sad2d",
2104         .rst_lines      = omap3xxx_sad2d_resets,
2105         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2106         .main_clk       = "sad2d_ick",
2107         .prcm           = {
2108                 .omap2 = {
2109                         .module_offs = CORE_MOD,
2110                         .prcm_reg_id = 1,
2111                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2112                         .idlest_reg_id = 1,
2113                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2114                 },
2115         },
2116         .class          = &omap3xxx_sad2d_class,
2117 };
2118
2119 /*
2120  * '32K sync counter' class
2121  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2122  */
2123 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2124         .rev_offs       = 0x0000,
2125         .sysc_offs      = 0x0004,
2126         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2127         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2128         .sysc_fields    = &omap_hwmod_sysc_type1,
2129 };
2130
2131 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2132         .name   = "counter",
2133         .sysc   = &omap3xxx_counter_sysc,
2134 };
2135
2136 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2137         .name           = "counter_32k",
2138         .class          = &omap3xxx_counter_hwmod_class,
2139         .clkdm_name     = "wkup_clkdm",
2140         .flags          = HWMOD_SWSUP_SIDLE,
2141         .main_clk       = "wkup_32k_fck",
2142         .prcm           = {
2143                 .omap2  = {
2144                         .module_offs = WKUP_MOD,
2145                         .prcm_reg_id = 1,
2146                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2147                         .idlest_reg_id = 1,
2148                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2149                 },
2150         },
2151 };
2152
2153 /*
2154  * 'gpmc' class
2155  * general purpose memory controller
2156  */
2157
2158 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2159         .rev_offs       = 0x0000,
2160         .sysc_offs      = 0x0010,
2161         .syss_offs      = 0x0014,
2162         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2163                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2165         .sysc_fields    = &omap_hwmod_sysc_type1,
2166 };
2167
2168 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2169         .name   = "gpmc",
2170         .sysc   = &omap3xxx_gpmc_sysc,
2171 };
2172
2173 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2174         { .irq = 20 },
2175         { .irq = -1 }
2176 };
2177
2178 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2179         .name           = "gpmc",
2180         .class          = &omap3xxx_gpmc_hwmod_class,
2181         .clkdm_name     = "core_l3_clkdm",
2182         .mpu_irqs       = omap3xxx_gpmc_irqs,
2183         .main_clk       = "gpmc_fck",
2184         /*
2185          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2186          * block.  It is not being added due to any known bugs with
2187          * resetting the GPMC IP block, but rather because any timings
2188          * set by the bootloader are not being correctly programmed by
2189          * the kernel from the board file or DT data.
2190          * HWMOD_INIT_NO_RESET should be removed ASAP.
2191          */
2192         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2193                            HWMOD_NO_IDLEST),
2194 };
2195
2196 /*
2197  * interfaces
2198  */
2199
2200 /* L3 -> L4_CORE interface */
2201 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2202         .master = &omap3xxx_l3_main_hwmod,
2203         .slave  = &omap3xxx_l4_core_hwmod,
2204         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2205 };
2206
2207 /* L3 -> L4_PER interface */
2208 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2209         .master = &omap3xxx_l3_main_hwmod,
2210         .slave  = &omap3xxx_l4_per_hwmod,
2211         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2212 };
2213
2214 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2215         {
2216                 .pa_start       = 0x68000000,
2217                 .pa_end         = 0x6800ffff,
2218                 .flags          = ADDR_TYPE_RT,
2219         },
2220         { }
2221 };
2222
2223 /* MPU -> L3 interface */
2224 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2225         .master   = &omap3xxx_mpu_hwmod,
2226         .slave    = &omap3xxx_l3_main_hwmod,
2227         .addr     = omap3xxx_l3_main_addrs,
2228         .user   = OCP_USER_MPU,
2229 };
2230
2231 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2232         {
2233                 .pa_start       = 0x54000000,
2234                 .pa_end         = 0x547fffff,
2235                 .flags          = ADDR_TYPE_RT,
2236         },
2237         { }
2238 };
2239
2240 /* l3 -> debugss */
2241 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2242         .master         = &omap3xxx_l3_main_hwmod,
2243         .slave          = &omap3xxx_debugss_hwmod,
2244         .addr           = omap3xxx_l4_emu_addrs,
2245         .user           = OCP_USER_MPU,
2246 };
2247
2248 /* DSS -> l3 */
2249 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2250         .master         = &omap3430es1_dss_core_hwmod,
2251         .slave          = &omap3xxx_l3_main_hwmod,
2252         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2253 };
2254
2255 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2256         .master         = &omap3xxx_dss_core_hwmod,
2257         .slave          = &omap3xxx_l3_main_hwmod,
2258         .fw = {
2259                 .omap2 = {
2260                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2261                         .flags  = OMAP_FIREWALL_L3,
2262                 }
2263         },
2264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2265 };
2266
2267 /* l3_core -> usbhsotg interface */
2268 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2269         .master         = &omap3xxx_usbhsotg_hwmod,
2270         .slave          = &omap3xxx_l3_main_hwmod,
2271         .clk            = "core_l3_ick",
2272         .user           = OCP_USER_MPU,
2273 };
2274
2275 /* l3_core -> am35xx_usbhsotg interface */
2276 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2277         .master         = &am35xx_usbhsotg_hwmod,
2278         .slave          = &omap3xxx_l3_main_hwmod,
2279         .clk            = "hsotgusb_ick",
2280         .user           = OCP_USER_MPU,
2281 };
2282
2283 /* l3_core -> sad2d interface */
2284 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2285         .master         = &omap3xxx_sad2d_hwmod,
2286         .slave          = &omap3xxx_l3_main_hwmod,
2287         .clk            = "core_l3_ick",
2288         .user           = OCP_USER_MPU,
2289 };
2290
2291 /* L4_CORE -> L4_WKUP interface */
2292 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2293         .master = &omap3xxx_l4_core_hwmod,
2294         .slave  = &omap3xxx_l4_wkup_hwmod,
2295         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2296 };
2297
2298 /* L4 CORE -> MMC1 interface */
2299 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2300         .master         = &omap3xxx_l4_core_hwmod,
2301         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2302         .clk            = "mmchs1_ick",
2303         .addr           = omap2430_mmc1_addr_space,
2304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2305         .flags          = OMAP_FIREWALL_L4
2306 };
2307
2308 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2309         .master         = &omap3xxx_l4_core_hwmod,
2310         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2311         .clk            = "mmchs1_ick",
2312         .addr           = omap2430_mmc1_addr_space,
2313         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2314         .flags          = OMAP_FIREWALL_L4
2315 };
2316
2317 /* L4 CORE -> MMC2 interface */
2318 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2319         .master         = &omap3xxx_l4_core_hwmod,
2320         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2321         .clk            = "mmchs2_ick",
2322         .addr           = omap2430_mmc2_addr_space,
2323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2324         .flags          = OMAP_FIREWALL_L4
2325 };
2326
2327 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2328         .master         = &omap3xxx_l4_core_hwmod,
2329         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2330         .clk            = "mmchs2_ick",
2331         .addr           = omap2430_mmc2_addr_space,
2332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2333         .flags          = OMAP_FIREWALL_L4
2334 };
2335
2336 /* L4 CORE -> MMC3 interface */
2337 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2338         {
2339                 .pa_start       = 0x480ad000,
2340                 .pa_end         = 0x480ad1ff,
2341                 .flags          = ADDR_TYPE_RT,
2342         },
2343         { }
2344 };
2345
2346 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2347         .master         = &omap3xxx_l4_core_hwmod,
2348         .slave          = &omap3xxx_mmc3_hwmod,
2349         .clk            = "mmchs3_ick",
2350         .addr           = omap3xxx_mmc3_addr_space,
2351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2352         .flags          = OMAP_FIREWALL_L4
2353 };
2354
2355 /* L4 CORE -> UART1 interface */
2356 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2357         {
2358                 .pa_start       = OMAP3_UART1_BASE,
2359                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2360                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2361         },
2362         { }
2363 };
2364
2365 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2366         .master         = &omap3xxx_l4_core_hwmod,
2367         .slave          = &omap3xxx_uart1_hwmod,
2368         .clk            = "uart1_ick",
2369         .addr           = omap3xxx_uart1_addr_space,
2370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2371 };
2372
2373 /* L4 CORE -> UART2 interface */
2374 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2375         {
2376                 .pa_start       = OMAP3_UART2_BASE,
2377                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2378                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2379         },
2380         { }
2381 };
2382
2383 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2384         .master         = &omap3xxx_l4_core_hwmod,
2385         .slave          = &omap3xxx_uart2_hwmod,
2386         .clk            = "uart2_ick",
2387         .addr           = omap3xxx_uart2_addr_space,
2388         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2389 };
2390
2391 /* L4 PER -> UART3 interface */
2392 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2393         {
2394                 .pa_start       = OMAP3_UART3_BASE,
2395                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2396                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2397         },
2398         { }
2399 };
2400
2401 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2402         .master         = &omap3xxx_l4_per_hwmod,
2403         .slave          = &omap3xxx_uart3_hwmod,
2404         .clk            = "uart3_ick",
2405         .addr           = omap3xxx_uart3_addr_space,
2406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2407 };
2408
2409 /* L4 PER -> UART4 interface */
2410 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2411         {
2412                 .pa_start       = OMAP3_UART4_BASE,
2413                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2414                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2415         },
2416         { }
2417 };
2418
2419 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2420         .master         = &omap3xxx_l4_per_hwmod,
2421         .slave          = &omap36xx_uart4_hwmod,
2422         .clk            = "uart4_ick",
2423         .addr           = omap36xx_uart4_addr_space,
2424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2425 };
2426
2427 /* AM35xx: L4 CORE -> UART4 interface */
2428 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2429         {
2430                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2431                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2432                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2433         },
2434         { }
2435 };
2436
2437 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2438         .master         = &omap3xxx_l4_core_hwmod,
2439         .slave          = &am35xx_uart4_hwmod,
2440         .clk            = "uart4_ick",
2441         .addr           = am35xx_uart4_addr_space,
2442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2443 };
2444
2445 /* L4 CORE -> I2C1 interface */
2446 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2447         .master         = &omap3xxx_l4_core_hwmod,
2448         .slave          = &omap3xxx_i2c1_hwmod,
2449         .clk            = "i2c1_ick",
2450         .addr           = omap2_i2c1_addr_space,
2451         .fw = {
2452                 .omap2 = {
2453                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2454                         .l4_prot_group = 7,
2455                         .flags  = OMAP_FIREWALL_L4,
2456                 }
2457         },
2458         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2459 };
2460
2461 /* L4 CORE -> I2C2 interface */
2462 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2463         .master         = &omap3xxx_l4_core_hwmod,
2464         .slave          = &omap3xxx_i2c2_hwmod,
2465         .clk            = "i2c2_ick",
2466         .addr           = omap2_i2c2_addr_space,
2467         .fw = {
2468                 .omap2 = {
2469                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2470                         .l4_prot_group = 7,
2471                         .flags = OMAP_FIREWALL_L4,
2472                 }
2473         },
2474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2475 };
2476
2477 /* L4 CORE -> I2C3 interface */
2478 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2479         {
2480                 .pa_start       = 0x48060000,
2481                 .pa_end         = 0x48060000 + SZ_128 - 1,
2482                 .flags          = ADDR_TYPE_RT,
2483         },
2484         { }
2485 };
2486
2487 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2488         .master         = &omap3xxx_l4_core_hwmod,
2489         .slave          = &omap3xxx_i2c3_hwmod,
2490         .clk            = "i2c3_ick",
2491         .addr           = omap3xxx_i2c3_addr_space,
2492         .fw = {
2493                 .omap2 = {
2494                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2495                         .l4_prot_group = 7,
2496                         .flags = OMAP_FIREWALL_L4,
2497                 }
2498         },
2499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2500 };
2501
2502 /* L4 CORE -> SR1 interface */
2503 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2504         {
2505                 .pa_start       = OMAP34XX_SR1_BASE,
2506                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2507                 .flags          = ADDR_TYPE_RT,
2508         },
2509         { }
2510 };
2511
2512 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2513         .master         = &omap3xxx_l4_core_hwmod,
2514         .slave          = &omap34xx_sr1_hwmod,
2515         .clk            = "sr_l4_ick",
2516         .addr           = omap3_sr1_addr_space,
2517         .user           = OCP_USER_MPU,
2518 };
2519
2520 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2521         .master         = &omap3xxx_l4_core_hwmod,
2522         .slave          = &omap36xx_sr1_hwmod,
2523         .clk            = "sr_l4_ick",
2524         .addr           = omap3_sr1_addr_space,
2525         .user           = OCP_USER_MPU,
2526 };
2527
2528 /* L4 CORE -> SR1 interface */
2529 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2530         {
2531                 .pa_start       = OMAP34XX_SR2_BASE,
2532                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2533                 .flags          = ADDR_TYPE_RT,
2534         },
2535         { }
2536 };
2537
2538 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2539         .master         = &omap3xxx_l4_core_hwmod,
2540         .slave          = &omap34xx_sr2_hwmod,
2541         .clk            = "sr_l4_ick",
2542         .addr           = omap3_sr2_addr_space,
2543         .user           = OCP_USER_MPU,
2544 };
2545
2546 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2547         .master         = &omap3xxx_l4_core_hwmod,
2548         .slave          = &omap36xx_sr2_hwmod,
2549         .clk            = "sr_l4_ick",
2550         .addr           = omap3_sr2_addr_space,
2551         .user           = OCP_USER_MPU,
2552 };
2553
2554 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2555         {
2556                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2557                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2558                 .flags          = ADDR_TYPE_RT
2559         },
2560         { }
2561 };
2562
2563 /* l4_core -> usbhsotg  */
2564 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2565         .master         = &omap3xxx_l4_core_hwmod,
2566         .slave          = &omap3xxx_usbhsotg_hwmod,
2567         .clk            = "l4_ick",
2568         .addr           = omap3xxx_usbhsotg_addrs,
2569         .user           = OCP_USER_MPU,
2570 };
2571
2572 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2573         {
2574                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2575                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2576                 .flags          = ADDR_TYPE_RT
2577         },
2578         { }
2579 };
2580
2581 /* l4_core -> usbhsotg  */
2582 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2583         .master         = &omap3xxx_l4_core_hwmod,
2584         .slave          = &am35xx_usbhsotg_hwmod,
2585         .clk            = "hsotgusb_ick",
2586         .addr           = am35xx_usbhsotg_addrs,
2587         .user           = OCP_USER_MPU,
2588 };
2589
2590 /* L4_WKUP -> L4_SEC interface */
2591 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2592         .master = &omap3xxx_l4_wkup_hwmod,
2593         .slave  = &omap3xxx_l4_sec_hwmod,
2594         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2595 };
2596
2597 /* IVA2 <- L3 interface */
2598 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2599         .master         = &omap3xxx_l3_main_hwmod,
2600         .slave          = &omap3xxx_iva_hwmod,
2601         .clk            = "core_l3_ick",
2602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2603 };
2604
2605 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2606         {
2607                 .pa_start       = 0x48318000,
2608                 .pa_end         = 0x48318000 + SZ_1K - 1,
2609                 .flags          = ADDR_TYPE_RT
2610         },
2611         { }
2612 };
2613
2614 /* l4_wkup -> timer1 */
2615 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2616         .master         = &omap3xxx_l4_wkup_hwmod,
2617         .slave          = &omap3xxx_timer1_hwmod,
2618         .clk            = "gpt1_ick",
2619         .addr           = omap3xxx_timer1_addrs,
2620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2624         {
2625                 .pa_start       = 0x49032000,
2626                 .pa_end         = 0x49032000 + SZ_1K - 1,
2627                 .flags          = ADDR_TYPE_RT
2628         },
2629         { }
2630 };
2631
2632 /* l4_per -> timer2 */
2633 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2634         .master         = &omap3xxx_l4_per_hwmod,
2635         .slave          = &omap3xxx_timer2_hwmod,
2636         .clk            = "gpt2_ick",
2637         .addr           = omap3xxx_timer2_addrs,
2638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2639 };
2640
2641 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2642         {
2643                 .pa_start       = 0x49034000,
2644                 .pa_end         = 0x49034000 + SZ_1K - 1,
2645                 .flags          = ADDR_TYPE_RT
2646         },
2647         { }
2648 };
2649
2650 /* l4_per -> timer3 */
2651 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2652         .master         = &omap3xxx_l4_per_hwmod,
2653         .slave          = &omap3xxx_timer3_hwmod,
2654         .clk            = "gpt3_ick",
2655         .addr           = omap3xxx_timer3_addrs,
2656         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2657 };
2658
2659 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2660         {
2661                 .pa_start       = 0x49036000,
2662                 .pa_end         = 0x49036000 + SZ_1K - 1,
2663                 .flags          = ADDR_TYPE_RT
2664         },
2665         { }
2666 };
2667
2668 /* l4_per -> timer4 */
2669 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2670         .master         = &omap3xxx_l4_per_hwmod,
2671         .slave          = &omap3xxx_timer4_hwmod,
2672         .clk            = "gpt4_ick",
2673         .addr           = omap3xxx_timer4_addrs,
2674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2675 };
2676
2677 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2678         {
2679                 .pa_start       = 0x49038000,
2680                 .pa_end         = 0x49038000 + SZ_1K - 1,
2681                 .flags          = ADDR_TYPE_RT
2682         },
2683         { }
2684 };
2685
2686 /* l4_per -> timer5 */
2687 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2688         .master         = &omap3xxx_l4_per_hwmod,
2689         .slave          = &omap3xxx_timer5_hwmod,
2690         .clk            = "gpt5_ick",
2691         .addr           = omap3xxx_timer5_addrs,
2692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2693 };
2694
2695 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2696         {
2697                 .pa_start       = 0x4903A000,
2698                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2699                 .flags          = ADDR_TYPE_RT
2700         },
2701         { }
2702 };
2703
2704 /* l4_per -> timer6 */
2705 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2706         .master         = &omap3xxx_l4_per_hwmod,
2707         .slave          = &omap3xxx_timer6_hwmod,
2708         .clk            = "gpt6_ick",
2709         .addr           = omap3xxx_timer6_addrs,
2710         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2711 };
2712
2713 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2714         {
2715                 .pa_start       = 0x4903C000,
2716                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2717                 .flags          = ADDR_TYPE_RT
2718         },
2719         { }
2720 };
2721
2722 /* l4_per -> timer7 */
2723 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2724         .master         = &omap3xxx_l4_per_hwmod,
2725         .slave          = &omap3xxx_timer7_hwmod,
2726         .clk            = "gpt7_ick",
2727         .addr           = omap3xxx_timer7_addrs,
2728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2729 };
2730
2731 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2732         {
2733                 .pa_start       = 0x4903E000,
2734                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2735                 .flags          = ADDR_TYPE_RT
2736         },
2737         { }
2738 };
2739
2740 /* l4_per -> timer8 */
2741 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2742         .master         = &omap3xxx_l4_per_hwmod,
2743         .slave          = &omap3xxx_timer8_hwmod,
2744         .clk            = "gpt8_ick",
2745         .addr           = omap3xxx_timer8_addrs,
2746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2747 };
2748
2749 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2750         {
2751                 .pa_start       = 0x49040000,
2752                 .pa_end         = 0x49040000 + SZ_1K - 1,
2753                 .flags          = ADDR_TYPE_RT
2754         },
2755         { }
2756 };
2757
2758 /* l4_per -> timer9 */
2759 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2760         .master         = &omap3xxx_l4_per_hwmod,
2761         .slave          = &omap3xxx_timer9_hwmod,
2762         .clk            = "gpt9_ick",
2763         .addr           = omap3xxx_timer9_addrs,
2764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2765 };
2766
2767 /* l4_core -> timer10 */
2768 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2769         .master         = &omap3xxx_l4_core_hwmod,
2770         .slave          = &omap3xxx_timer10_hwmod,
2771         .clk            = "gpt10_ick",
2772         .addr           = omap2_timer10_addrs,
2773         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2774 };
2775
2776 /* l4_core -> timer11 */
2777 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2778         .master         = &omap3xxx_l4_core_hwmod,
2779         .slave          = &omap3xxx_timer11_hwmod,
2780         .clk            = "gpt11_ick",
2781         .addr           = omap2_timer11_addrs,
2782         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2783 };
2784
2785 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2786         {
2787                 .pa_start       = 0x48304000,
2788                 .pa_end         = 0x48304000 + SZ_1K - 1,
2789                 .flags          = ADDR_TYPE_RT
2790         },
2791         { }
2792 };
2793
2794 /* l4_core -> timer12 */
2795 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2796         .master         = &omap3xxx_l4_sec_hwmod,
2797         .slave          = &omap3xxx_timer12_hwmod,
2798         .clk            = "gpt12_ick",
2799         .addr           = omap3xxx_timer12_addrs,
2800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2801 };
2802
2803 /* l4_wkup -> wd_timer2 */
2804 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2805         {
2806                 .pa_start       = 0x48314000,
2807                 .pa_end         = 0x4831407f,
2808                 .flags          = ADDR_TYPE_RT
2809         },
2810         { }
2811 };
2812
2813 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2814         .master         = &omap3xxx_l4_wkup_hwmod,
2815         .slave          = &omap3xxx_wd_timer2_hwmod,
2816         .clk            = "wdt2_ick",
2817         .addr           = omap3xxx_wd_timer2_addrs,
2818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2819 };
2820
2821 /* l4_core -> dss */
2822 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2823         .master         = &omap3xxx_l4_core_hwmod,
2824         .slave          = &omap3430es1_dss_core_hwmod,
2825         .clk            = "dss_ick",
2826         .addr           = omap2_dss_addrs,
2827         .fw = {
2828                 .omap2 = {
2829                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2830                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2831                         .flags  = OMAP_FIREWALL_L4,
2832                 }
2833         },
2834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2835 };
2836
2837 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2838         .master         = &omap3xxx_l4_core_hwmod,
2839         .slave          = &omap3xxx_dss_core_hwmod,
2840         .clk            = "dss_ick",
2841         .addr           = omap2_dss_addrs,
2842         .fw = {
2843                 .omap2 = {
2844                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2845                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2846                         .flags  = OMAP_FIREWALL_L4,
2847                 }
2848         },
2849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2850 };
2851
2852 /* l4_core -> dss_dispc */
2853 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2854         .master         = &omap3xxx_l4_core_hwmod,
2855         .slave          = &omap3xxx_dss_dispc_hwmod,
2856         .clk            = "dss_ick",
2857         .addr           = omap2_dss_dispc_addrs,
2858         .fw = {
2859                 .omap2 = {
2860                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2861                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2862                         .flags  = OMAP_FIREWALL_L4,
2863                 }
2864         },
2865         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2866 };
2867
2868 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2869         {
2870                 .pa_start       = 0x4804FC00,
2871                 .pa_end         = 0x4804FFFF,
2872                 .flags          = ADDR_TYPE_RT
2873         },
2874         { }
2875 };
2876
2877 /* l4_core -> dss_dsi1 */
2878 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2879         .master         = &omap3xxx_l4_core_hwmod,
2880         .slave          = &omap3xxx_dss_dsi1_hwmod,
2881         .clk            = "dss_ick",
2882         .addr           = omap3xxx_dss_dsi1_addrs,
2883         .fw = {
2884                 .omap2 = {
2885                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2886                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2887                         .flags  = OMAP_FIREWALL_L4,
2888                 }
2889         },
2890         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2891 };
2892
2893 /* l4_core -> dss_rfbi */
2894 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2895         .master         = &omap3xxx_l4_core_hwmod,
2896         .slave          = &omap3xxx_dss_rfbi_hwmod,
2897         .clk            = "dss_ick",
2898         .addr           = omap2_dss_rfbi_addrs,
2899         .fw = {
2900                 .omap2 = {
2901                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2902                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2903                         .flags  = OMAP_FIREWALL_L4,
2904                 }
2905         },
2906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2907 };
2908
2909 /* l4_core -> dss_venc */
2910 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2911         .master         = &omap3xxx_l4_core_hwmod,
2912         .slave          = &omap3xxx_dss_venc_hwmod,
2913         .clk            = "dss_ick",
2914         .addr           = omap2_dss_venc_addrs,
2915         .fw = {
2916                 .omap2 = {
2917                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2918                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2919                         .flags  = OMAP_FIREWALL_L4,
2920                 }
2921         },
2922         .flags          = OCPIF_SWSUP_IDLE,
2923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2924 };
2925
2926 /* l4_wkup -> gpio1 */
2927 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2928         {
2929                 .pa_start       = 0x48310000,
2930                 .pa_end         = 0x483101ff,
2931                 .flags          = ADDR_TYPE_RT
2932         },
2933         { }
2934 };
2935
2936 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2937         .master         = &omap3xxx_l4_wkup_hwmod,
2938         .slave          = &omap3xxx_gpio1_hwmod,
2939         .addr           = omap3xxx_gpio1_addrs,
2940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2941 };
2942
2943 /* l4_per -> gpio2 */
2944 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2945         {
2946                 .pa_start       = 0x49050000,
2947                 .pa_end         = 0x490501ff,
2948                 .flags          = ADDR_TYPE_RT
2949         },
2950         { }
2951 };
2952
2953 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2954         .master         = &omap3xxx_l4_per_hwmod,
2955         .slave          = &omap3xxx_gpio2_hwmod,
2956         .addr           = omap3xxx_gpio2_addrs,
2957         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2958 };
2959
2960 /* l4_per -> gpio3 */
2961 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2962         {
2963                 .pa_start       = 0x49052000,
2964                 .pa_end         = 0x490521ff,
2965                 .flags          = ADDR_TYPE_RT
2966         },
2967         { }
2968 };
2969
2970 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2971         .master         = &omap3xxx_l4_per_hwmod,
2972         .slave          = &omap3xxx_gpio3_hwmod,
2973         .addr           = omap3xxx_gpio3_addrs,
2974         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2975 };
2976
2977 /*
2978  * 'mmu' class
2979  * The memory management unit performs virtual to physical address translation
2980  * for its requestors.
2981  */
2982
2983 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2984         .rev_offs       = 0x000,
2985         .sysc_offs      = 0x010,
2986         .syss_offs      = 0x014,
2987         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2988                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2989         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2990         .sysc_fields    = &omap_hwmod_sysc_type1,
2991 };
2992
2993 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2994         .name = "mmu",
2995         .sysc = &mmu_sysc,
2996 };
2997
2998 /* mmu isp */
2999
3000 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
3001         .da_start       = 0x0,
3002         .da_end         = 0xfffff000,
3003         .nr_tlb_entries = 8,
3004 };
3005
3006 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
3007 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
3008         { .irq = 24 },
3009         { .irq = -1 }
3010 };
3011
3012 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
3013         {
3014                 .pa_start       = 0x480bd400,
3015                 .pa_end         = 0x480bd47f,
3016                 .flags          = ADDR_TYPE_RT,
3017         },
3018         { }
3019 };
3020
3021 /* l4_core -> mmu isp */
3022 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3023         .master         = &omap3xxx_l4_core_hwmod,
3024         .slave          = &omap3xxx_mmu_isp_hwmod,
3025         .addr           = omap3xxx_mmu_isp_addrs,
3026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3027 };
3028
3029 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3030         .name           = "mmu_isp",
3031         .class          = &omap3xxx_mmu_hwmod_class,
3032         .mpu_irqs       = omap3xxx_mmu_isp_irqs,
3033         .main_clk       = "cam_ick",
3034         .dev_attr       = &mmu_isp_dev_attr,
3035         .flags          = HWMOD_NO_IDLEST,
3036 };
3037
3038 #ifdef CONFIG_OMAP_IOMMU_IVA2
3039
3040 /* mmu iva */
3041
3042 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3043         .da_start       = 0x11000000,
3044         .da_end         = 0xfffff000,
3045         .nr_tlb_entries = 32,
3046 };
3047
3048 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3049 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3050         { .irq = 28 },
3051         { .irq = -1 }
3052 };
3053
3054 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3055         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3056 };
3057
3058 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3059         {
3060                 .pa_start       = 0x5d000000,
3061                 .pa_end         = 0x5d00007f,
3062                 .flags          = ADDR_TYPE_RT,
3063         },
3064         { }
3065 };
3066
3067 /* l3_main -> iva mmu */
3068 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3069         .master         = &omap3xxx_l3_main_hwmod,
3070         .slave          = &omap3xxx_mmu_iva_hwmod,
3071         .addr           = omap3xxx_mmu_iva_addrs,
3072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3073 };
3074
3075 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3076         .name           = "mmu_iva",
3077         .class          = &omap3xxx_mmu_hwmod_class,
3078         .mpu_irqs       = omap3xxx_mmu_iva_irqs,
3079         .rst_lines      = omap3xxx_mmu_iva_resets,
3080         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3081         .main_clk       = "iva2_ck",
3082         .prcm = {
3083                 .omap2 = {
3084                         .module_offs = OMAP3430_IVA2_MOD,
3085                 },
3086         },
3087         .dev_attr       = &mmu_iva_dev_attr,
3088         .flags          = HWMOD_NO_IDLEST,
3089 };
3090
3091 #endif
3092
3093 /* l4_per -> gpio4 */
3094 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3095         {
3096                 .pa_start       = 0x49054000,
3097                 .pa_end         = 0x490541ff,
3098                 .flags          = ADDR_TYPE_RT
3099         },
3100         { }
3101 };
3102
3103 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3104         .master         = &omap3xxx_l4_per_hwmod,
3105         .slave          = &omap3xxx_gpio4_hwmod,
3106         .addr           = omap3xxx_gpio4_addrs,
3107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3108 };
3109
3110 /* l4_per -> gpio5 */
3111 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3112         {
3113                 .pa_start       = 0x49056000,
3114                 .pa_end         = 0x490561ff,
3115                 .flags          = ADDR_TYPE_RT
3116         },
3117         { }
3118 };
3119
3120 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3121         .master         = &omap3xxx_l4_per_hwmod,
3122         .slave          = &omap3xxx_gpio5_hwmod,
3123         .addr           = omap3xxx_gpio5_addrs,
3124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3125 };
3126
3127 /* l4_per -> gpio6 */
3128 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3129         {
3130                 .pa_start       = 0x49058000,
3131                 .pa_end         = 0x490581ff,
3132                 .flags          = ADDR_TYPE_RT
3133         },
3134         { }
3135 };
3136
3137 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3138         .master         = &omap3xxx_l4_per_hwmod,
3139         .slave          = &omap3xxx_gpio6_hwmod,
3140         .addr           = omap3xxx_gpio6_addrs,
3141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3142 };
3143
3144 /* dma_system -> L3 */
3145 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3146         .master         = &omap3xxx_dma_system_hwmod,
3147         .slave          = &omap3xxx_l3_main_hwmod,
3148         .clk            = "core_l3_ick",
3149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3150 };
3151
3152 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3153         {
3154                 .pa_start       = 0x48056000,
3155                 .pa_end         = 0x48056fff,
3156                 .flags          = ADDR_TYPE_RT
3157         },
3158         { }
3159 };
3160
3161 /* l4_cfg -> dma_system */
3162 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3163         .master         = &omap3xxx_l4_core_hwmod,
3164         .slave          = &omap3xxx_dma_system_hwmod,
3165         .clk            = "core_l4_ick",
3166         .addr           = omap3xxx_dma_system_addrs,
3167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3168 };
3169
3170 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3171         {
3172                 .name           = "mpu",
3173                 .pa_start       = 0x48074000,
3174                 .pa_end         = 0x480740ff,
3175                 .flags          = ADDR_TYPE_RT
3176         },
3177         { }
3178 };
3179
3180 /* l4_core -> mcbsp1 */
3181 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3182         .master         = &omap3xxx_l4_core_hwmod,
3183         .slave          = &omap3xxx_mcbsp1_hwmod,
3184         .clk            = "mcbsp1_ick",
3185         .addr           = omap3xxx_mcbsp1_addrs,
3186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3187 };
3188
3189 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3190         {
3191                 .name           = "mpu",
3192                 .pa_start       = 0x49022000,
3193                 .pa_end         = 0x490220ff,
3194                 .flags          = ADDR_TYPE_RT
3195         },
3196         { }
3197 };
3198
3199 /* l4_per -> mcbsp2 */
3200 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3201         .master         = &omap3xxx_l4_per_hwmod,
3202         .slave          = &omap3xxx_mcbsp2_hwmod,
3203         .clk            = "mcbsp2_ick",
3204         .addr           = omap3xxx_mcbsp2_addrs,
3205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3206 };
3207
3208 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3209         {
3210                 .name           = "mpu",
3211                 .pa_start       = 0x49024000,
3212                 .pa_end         = 0x490240ff,
3213                 .flags          = ADDR_TYPE_RT
3214         },
3215         { }
3216 };
3217
3218 /* l4_per -> mcbsp3 */
3219 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3220         .master         = &omap3xxx_l4_per_hwmod,
3221         .slave          = &omap3xxx_mcbsp3_hwmod,
3222         .clk            = "mcbsp3_ick",
3223         .addr           = omap3xxx_mcbsp3_addrs,
3224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3225 };
3226
3227 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3228         {
3229                 .name           = "mpu",
3230                 .pa_start       = 0x49026000,
3231                 .pa_end         = 0x490260ff,
3232                 .flags          = ADDR_TYPE_RT
3233         },
3234         { }
3235 };
3236
3237 /* l4_per -> mcbsp4 */
3238 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3239         .master         = &omap3xxx_l4_per_hwmod,
3240         .slave          = &omap3xxx_mcbsp4_hwmod,
3241         .clk            = "mcbsp4_ick",
3242         .addr           = omap3xxx_mcbsp4_addrs,
3243         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3244 };
3245
3246 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3247         {
3248                 .name           = "mpu",
3249                 .pa_start       = 0x48096000,
3250                 .pa_end         = 0x480960ff,
3251                 .flags          = ADDR_TYPE_RT
3252         },
3253         { }
3254 };
3255
3256 /* l4_core -> mcbsp5 */
3257 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3258         .master         = &omap3xxx_l4_core_hwmod,
3259         .slave          = &omap3xxx_mcbsp5_hwmod,
3260         .clk            = "mcbsp5_ick",
3261         .addr           = omap3xxx_mcbsp5_addrs,
3262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3263 };
3264
3265 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3266         {
3267                 .name           = "sidetone",
3268                 .pa_start       = 0x49028000,
3269                 .pa_end         = 0x490280ff,
3270                 .flags          = ADDR_TYPE_RT
3271         },
3272         { }
3273 };
3274
3275 /* l4_per -> mcbsp2_sidetone */
3276 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3277         .master         = &omap3xxx_l4_per_hwmod,
3278         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3279         .clk            = "mcbsp2_ick",
3280         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3281         .user           = OCP_USER_MPU,
3282 };
3283
3284 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3285         {
3286                 .name           = "sidetone",
3287                 .pa_start       = 0x4902A000,
3288                 .pa_end         = 0x4902A0ff,
3289                 .flags          = ADDR_TYPE_RT
3290         },
3291         { }
3292 };
3293
3294 /* l4_per -> mcbsp3_sidetone */
3295 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3296         .master         = &omap3xxx_l4_per_hwmod,
3297         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3298         .clk            = "mcbsp3_ick",
3299         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3300         .user           = OCP_USER_MPU,
3301 };
3302
3303 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3304         {
3305                 .pa_start       = 0x48094000,
3306                 .pa_end         = 0x480941ff,
3307                 .flags          = ADDR_TYPE_RT,
3308         },
3309         { }
3310 };
3311
3312 /* l4_core -> mailbox */
3313 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3314         .master         = &omap3xxx_l4_core_hwmod,
3315         .slave          = &omap3xxx_mailbox_hwmod,
3316         .addr           = omap3xxx_mailbox_addrs,
3317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3318 };
3319
3320 /* l4 core -> mcspi1 interface */
3321 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3322         .master         = &omap3xxx_l4_core_hwmod,
3323         .slave          = &omap34xx_mcspi1,
3324         .clk            = "mcspi1_ick",
3325         .addr           = omap2_mcspi1_addr_space,
3326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3327 };
3328
3329 /* l4 core -> mcspi2 interface */
3330 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3331         .master         = &omap3xxx_l4_core_hwmod,
3332         .slave          = &omap34xx_mcspi2,
3333         .clk            = "mcspi2_ick",
3334         .addr           = omap2_mcspi2_addr_space,
3335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3336 };
3337
3338 /* l4 core -> mcspi3 interface */
3339 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3340         .master         = &omap3xxx_l4_core_hwmod,
3341         .slave          = &omap34xx_mcspi3,
3342         .clk            = "mcspi3_ick",
3343         .addr           = omap2430_mcspi3_addr_space,
3344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3345 };
3346
3347 /* l4 core -> mcspi4 interface */
3348 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3349         {
3350                 .pa_start       = 0x480ba000,
3351                 .pa_end         = 0x480ba0ff,
3352                 .flags          = ADDR_TYPE_RT,
3353         },
3354         { }
3355 };
3356
3357 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3358         .master         = &omap3xxx_l4_core_hwmod,
3359         .slave          = &omap34xx_mcspi4,
3360         .clk            = "mcspi4_ick",
3361         .addr           = omap34xx_mcspi4_addr_space,
3362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3363 };
3364
3365 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3366         .master         = &omap3xxx_usb_host_hs_hwmod,
3367         .slave          = &omap3xxx_l3_main_hwmod,
3368         .clk            = "core_l3_ick",
3369         .user           = OCP_USER_MPU,
3370 };
3371
3372 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3373         {
3374                 .name           = "uhh",
3375                 .pa_start       = 0x48064000,
3376                 .pa_end         = 0x480643ff,
3377                 .flags          = ADDR_TYPE_RT
3378         },
3379         {
3380                 .name           = "ohci",
3381                 .pa_start       = 0x48064400,
3382                 .pa_end         = 0x480647ff,
3383         },
3384         {
3385                 .name           = "ehci",
3386                 .pa_start       = 0x48064800,
3387                 .pa_end         = 0x48064cff,
3388         },
3389         {}
3390 };
3391
3392 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3393         .master         = &omap3xxx_l4_core_hwmod,
3394         .slave          = &omap3xxx_usb_host_hs_hwmod,
3395         .clk            = "usbhost_ick",
3396         .addr           = omap3xxx_usb_host_hs_addrs,
3397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3398 };
3399
3400 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3401         {
3402                 .name           = "tll",
3403                 .pa_start       = 0x48062000,
3404                 .pa_end         = 0x48062fff,
3405                 .flags          = ADDR_TYPE_RT
3406         },
3407         {}
3408 };
3409
3410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3411         .master         = &omap3xxx_l4_core_hwmod,
3412         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3413         .clk            = "usbtll_ick",
3414         .addr           = omap3xxx_usb_tll_hs_addrs,
3415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3417
3418 /* l4_core -> hdq1w interface */
3419 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3420         .master         = &omap3xxx_l4_core_hwmod,
3421         .slave          = &omap3xxx_hdq1w_hwmod,
3422         .clk            = "hdq_ick",
3423         .addr           = omap2_hdq1w_addr_space,
3424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3425         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3426 };
3427
3428 /* l4_wkup -> 32ksync_counter */
3429 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3430         {
3431                 .pa_start       = 0x48320000,
3432                 .pa_end         = 0x4832001f,
3433                 .flags          = ADDR_TYPE_RT
3434         },
3435         { }
3436 };
3437
3438 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3439         {
3440                 .pa_start       = 0x6e000000,
3441                 .pa_end         = 0x6e000fff,
3442                 .flags          = ADDR_TYPE_RT
3443         },
3444         { }
3445 };
3446
3447 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3448         .master         = &omap3xxx_l4_wkup_hwmod,
3449         .slave          = &omap3xxx_counter_32k_hwmod,
3450         .clk            = "omap_32ksync_ick",
3451         .addr           = omap3xxx_counter_32k_addrs,
3452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3453 };
3454
3455 /* am35xx has Davinci MDIO & EMAC */
3456 static struct omap_hwmod_class am35xx_mdio_class = {
3457         .name = "davinci_mdio",
3458 };
3459
3460 static struct omap_hwmod am35xx_mdio_hwmod = {
3461         .name           = "davinci_mdio",
3462         .class          = &am35xx_mdio_class,
3463         .flags          = HWMOD_NO_IDLEST,
3464 };
3465
3466 /*
3467  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3468  * but this will probably require some additional hwmod core support,
3469  * so is left as a future to-do item.
3470  */
3471 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3472         .master         = &am35xx_mdio_hwmod,
3473         .slave          = &omap3xxx_l3_main_hwmod,
3474         .clk            = "emac_fck",
3475         .user           = OCP_USER_MPU,
3476 };
3477
3478 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3479         {
3480                 .pa_start       = AM35XX_IPSS_MDIO_BASE,
3481                 .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3482                 .flags          = ADDR_TYPE_RT,
3483         },
3484         { }
3485 };
3486
3487 /* l4_core -> davinci mdio  */
3488 /*
3489  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3490  * but this will probably require some additional hwmod core support,
3491  * so is left as a future to-do item.
3492  */
3493 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3494         .master         = &omap3xxx_l4_core_hwmod,
3495         .slave          = &am35xx_mdio_hwmod,
3496         .clk            = "emac_fck",
3497         .addr           = am35xx_mdio_addrs,
3498         .user           = OCP_USER_MPU,
3499 };
3500
3501 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3502         { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
3503         { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
3504         { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
3505         { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3506         { .irq = -1 },
3507 };
3508
3509 static struct omap_hwmod_class am35xx_emac_class = {
3510         .name = "davinci_emac",
3511 };
3512
3513 static struct omap_hwmod am35xx_emac_hwmod = {
3514         .name           = "davinci_emac",
3515         .mpu_irqs       = am35xx_emac_mpu_irqs,
3516         .class          = &am35xx_emac_class,
3517         /*
3518          * According to Mark Greer, the MPU will not return from WFI
3519          * when the EMAC signals an interrupt.
3520          * http://www.spinics.net/lists/arm-kernel/msg174734.html
3521          */
3522         .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3523 };
3524
3525 /* l3_core -> davinci emac interface */
3526 /*
3527  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3528  * but this will probably require some additional hwmod core support,
3529  * so is left as a future to-do item.
3530  */
3531 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3532         .master         = &am35xx_emac_hwmod,
3533         .slave          = &omap3xxx_l3_main_hwmod,
3534         .clk            = "emac_ick",
3535         .user           = OCP_USER_MPU,
3536 };
3537
3538 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3539         {
3540                 .pa_start       = AM35XX_IPSS_EMAC_BASE,
3541                 .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3542                 .flags          = ADDR_TYPE_RT,
3543         },
3544         { }
3545 };
3546
3547 /* l4_core -> davinci emac  */
3548 /*
3549  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3550  * but this will probably require some additional hwmod core support,
3551  * so is left as a future to-do item.
3552  */
3553 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3554         .master         = &omap3xxx_l4_core_hwmod,
3555         .slave          = &am35xx_emac_hwmod,
3556         .clk            = "emac_ick",
3557         .addr           = am35xx_emac_addrs,
3558         .user           = OCP_USER_MPU,
3559 };
3560
3561 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3562         .master         = &omap3xxx_l3_main_hwmod,
3563         .slave          = &omap3xxx_gpmc_hwmod,
3564         .clk            = "core_l3_ick",
3565         .addr           = omap3xxx_gpmc_addrs,
3566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3567 };
3568
3569 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3570 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3571         .sidle_shift    = 4,
3572         .srst_shift     = 1,
3573         .autoidle_shift = 0,
3574 };
3575
3576 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3577         .rev_offs       = 0x5c,
3578         .sysc_offs      = 0x60,
3579         .syss_offs      = 0x64,
3580         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3581                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3582         .sysc_fields    = &omap3_sham_sysc_fields,
3583 };
3584
3585 static struct omap_hwmod_class omap3xxx_sham_class = {
3586         .name   = "sham",
3587         .sysc   = &omap3_sham_sysc,
3588 };
3589
3590 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3591         { .irq = 49 + OMAP_INTC_START, },
3592         { .irq = -1 }
3593 };
3594
3595 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3596         { .name = "rx", .dma_req = 69, },
3597         { .dma_req = -1 }
3598 };
3599
3600 static struct omap_hwmod omap3xxx_sham_hwmod = {
3601         .name           = "sham",
3602         .mpu_irqs       = omap3_sham_mpu_irqs,
3603         .sdma_reqs      = omap3_sham_sdma_reqs,
3604         .main_clk       = "sha12_ick",
3605         .prcm           = {
3606                 .omap2 = {
3607                         .module_offs = CORE_MOD,
3608                         .prcm_reg_id = 1,
3609                         .module_bit = OMAP3430_EN_SHA12_SHIFT,
3610                         .idlest_reg_id = 1,
3611                         .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3612                 },
3613         },
3614         .class          = &omap3xxx_sham_class,
3615 };
3616
3617 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3618         {
3619                 .pa_start       = 0x480c3000,
3620                 .pa_end         = 0x480c3000 + 0x64 - 1,
3621                 .flags          = ADDR_TYPE_RT
3622         },
3623         { }
3624 };
3625
3626 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3627         .master         = &omap3xxx_l4_core_hwmod,
3628         .slave          = &omap3xxx_sham_hwmod,
3629         .clk            = "sha12_ick",
3630         .addr           = omap3xxx_sham_addrs,
3631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3632 };
3633
3634 /* l4_core -> AES */
3635 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3636         .sidle_shift    = 6,
3637         .srst_shift     = 1,
3638         .autoidle_shift = 0,
3639 };
3640
3641 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3642         .rev_offs       = 0x44,
3643         .sysc_offs      = 0x48,
3644         .syss_offs      = 0x4c,
3645         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3646                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3647         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3648         .sysc_fields    = &omap3xxx_aes_sysc_fields,
3649 };
3650
3651 static struct omap_hwmod_class omap3xxx_aes_class = {
3652         .name   = "aes",
3653         .sysc   = &omap3_aes_sysc,
3654 };
3655
3656 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3657         { .name = "tx", .dma_req = 65, },
3658         { .name = "rx", .dma_req = 66, },
3659         { .dma_req = -1 }
3660 };
3661
3662 static struct omap_hwmod omap3xxx_aes_hwmod = {
3663         .name           = "aes",
3664         .sdma_reqs      = omap3_aes_sdma_reqs,
3665         .main_clk       = "aes2_ick",
3666         .prcm           = {
3667                 .omap2 = {
3668                         .module_offs = CORE_MOD,
3669                         .prcm_reg_id = 1,
3670                         .module_bit = OMAP3430_EN_AES2_SHIFT,
3671                         .idlest_reg_id = 1,
3672                         .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3673                 },
3674         },
3675         .class          = &omap3xxx_aes_class,
3676 };
3677
3678 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3679         {
3680                 .pa_start       = 0x480c5000,
3681                 .pa_end         = 0x480c5000 + 0x50 - 1,
3682                 .flags          = ADDR_TYPE_RT
3683         },
3684         { }
3685 };
3686
3687 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3688         .master         = &omap3xxx_l4_core_hwmod,
3689         .slave          = &omap3xxx_aes_hwmod,
3690         .clk            = "aes2_ick",
3691         .addr           = omap3xxx_aes_addrs,
3692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3693 };
3694
3695 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3696         &omap3xxx_l3_main__l4_core,
3697         &omap3xxx_l3_main__l4_per,
3698         &omap3xxx_mpu__l3_main,
3699         &omap3xxx_l3_main__l4_debugss,
3700         &omap3xxx_l4_core__l4_wkup,
3701         &omap3xxx_l4_core__mmc3,
3702         &omap3_l4_core__uart1,
3703         &omap3_l4_core__uart2,
3704         &omap3_l4_per__uart3,
3705         &omap3_l4_core__i2c1,
3706         &omap3_l4_core__i2c2,
3707         &omap3_l4_core__i2c3,
3708         &omap3xxx_l4_wkup__l4_sec,
3709         &omap3xxx_l4_wkup__timer1,
3710         &omap3xxx_l4_per__timer2,
3711         &omap3xxx_l4_per__timer3,
3712         &omap3xxx_l4_per__timer4,
3713         &omap3xxx_l4_per__timer5,
3714         &omap3xxx_l4_per__timer6,
3715         &omap3xxx_l4_per__timer7,
3716         &omap3xxx_l4_per__timer8,
3717         &omap3xxx_l4_per__timer9,
3718         &omap3xxx_l4_core__timer10,
3719         &omap3xxx_l4_core__timer11,
3720         &omap3xxx_l4_wkup__wd_timer2,
3721         &omap3xxx_l4_wkup__gpio1,
3722         &omap3xxx_l4_per__gpio2,
3723         &omap3xxx_l4_per__gpio3,
3724         &omap3xxx_l4_per__gpio4,
3725         &omap3xxx_l4_per__gpio5,
3726         &omap3xxx_l4_per__gpio6,
3727         &omap3xxx_dma_system__l3,
3728         &omap3xxx_l4_core__dma_system,
3729         &omap3xxx_l4_core__mcbsp1,
3730         &omap3xxx_l4_per__mcbsp2,
3731         &omap3xxx_l4_per__mcbsp3,
3732         &omap3xxx_l4_per__mcbsp4,
3733         &omap3xxx_l4_core__mcbsp5,
3734         &omap3xxx_l4_per__mcbsp2_sidetone,
3735         &omap3xxx_l4_per__mcbsp3_sidetone,
3736         &omap34xx_l4_core__mcspi1,
3737         &omap34xx_l4_core__mcspi2,
3738         &omap34xx_l4_core__mcspi3,
3739         &omap34xx_l4_core__mcspi4,
3740         &omap3xxx_l4_wkup__counter_32k,
3741         &omap3xxx_l3_main__gpmc,
3742         NULL,
3743 };
3744
3745 /* GP-only hwmod links */
3746 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3747         &omap3xxx_l4_sec__timer12,
3748         &omap3xxx_l4_core__sham,
3749         &omap3xxx_l4_core__aes,
3750         NULL
3751 };
3752
3753 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3754         &omap3xxx_l4_sec__timer12,
3755         &omap3xxx_l4_core__sham,
3756         &omap3xxx_l4_core__aes,
3757         NULL
3758 };
3759
3760 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3761         &omap3xxx_l4_sec__timer12,
3762         /*
3763          * Apparently the SHA/MD5 and AES accelerator IP blocks are
3764          * only present on some AM35xx chips, and no one knows which
3765          * ones.  See
3766          * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3767          * if you need these IP blocks on an AM35xx, try uncommenting
3768          * the following lines.
3769          */
3770         /* &omap3xxx_l4_core__sham, */
3771         /* &omap3xxx_l4_core__aes, */
3772         NULL
3773 };
3774
3775 /* 3430ES1-only hwmod links */
3776 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3777         &omap3430es1_dss__l3,
3778         &omap3430es1_l4_core__dss,
3779         NULL
3780 };
3781
3782 /* 3430ES2+-only hwmod links */
3783 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3784         &omap3xxx_dss__l3,
3785         &omap3xxx_l4_core__dss,
3786         &omap3xxx_usbhsotg__l3,
3787         &omap3xxx_l4_core__usbhsotg,
3788         &omap3xxx_usb_host_hs__l3_main_2,
3789         &omap3xxx_l4_core__usb_host_hs,
3790         &omap3xxx_l4_core__usb_tll_hs,
3791         NULL
3792 };
3793
3794 /* <= 3430ES3-only hwmod links */
3795 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3796         &omap3xxx_l4_core__pre_es3_mmc1,
3797         &omap3xxx_l4_core__pre_es3_mmc2,
3798         NULL
3799 };
3800
3801 /* 3430ES3+-only hwmod links */
3802 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3803         &omap3xxx_l4_core__es3plus_mmc1,
3804         &omap3xxx_l4_core__es3plus_mmc2,
3805         NULL
3806 };
3807
3808 /* 34xx-only hwmod links (all ES revisions) */
3809 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3810         &omap3xxx_l3__iva,
3811         &omap34xx_l4_core__sr1,
3812         &omap34xx_l4_core__sr2,
3813         &omap3xxx_l4_core__mailbox,
3814         &omap3xxx_l4_core__hdq1w,
3815         &omap3xxx_sad2d__l3,
3816         &omap3xxx_l4_core__mmu_isp,
3817 #ifdef CONFIG_OMAP_IOMMU_IVA2
3818         &omap3xxx_l3_main__mmu_iva,
3819 #endif
3820         NULL
3821 };
3822
3823 /* 36xx-only hwmod links (all ES revisions) */
3824 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3825         &omap3xxx_l3__iva,
3826         &omap36xx_l4_per__uart4,
3827         &omap3xxx_dss__l3,
3828         &omap3xxx_l4_core__dss,
3829         &omap36xx_l4_core__sr1,
3830         &omap36xx_l4_core__sr2,
3831         &omap3xxx_usbhsotg__l3,
3832         &omap3xxx_l4_core__usbhsotg,
3833         &omap3xxx_l4_core__mailbox,
3834         &omap3xxx_usb_host_hs__l3_main_2,
3835         &omap3xxx_l4_core__usb_host_hs,
3836         &omap3xxx_l4_core__usb_tll_hs,
3837         &omap3xxx_l4_core__es3plus_mmc1,
3838         &omap3xxx_l4_core__es3plus_mmc2,
3839         &omap3xxx_l4_core__hdq1w,
3840         &omap3xxx_sad2d__l3,
3841         &omap3xxx_l4_core__mmu_isp,
3842 #ifdef CONFIG_OMAP_IOMMU_IVA2
3843         &omap3xxx_l3_main__mmu_iva,
3844 #endif
3845         NULL
3846 };
3847
3848 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3849         &omap3xxx_dss__l3,
3850         &omap3xxx_l4_core__dss,
3851         &am35xx_usbhsotg__l3,
3852         &am35xx_l4_core__usbhsotg,
3853         &am35xx_l4_core__uart4,
3854         &omap3xxx_usb_host_hs__l3_main_2,
3855         &omap3xxx_l4_core__usb_host_hs,
3856         &omap3xxx_l4_core__usb_tll_hs,
3857         &omap3xxx_l4_core__es3plus_mmc1,
3858         &omap3xxx_l4_core__es3plus_mmc2,
3859         &omap3xxx_l4_core__hdq1w,
3860         &am35xx_mdio__l3,
3861         &am35xx_l4_core__mdio,
3862         &am35xx_emac__l3,
3863         &am35xx_l4_core__emac,
3864         NULL
3865 };
3866
3867 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3868         &omap3xxx_l4_core__dss_dispc,
3869         &omap3xxx_l4_core__dss_dsi1,
3870         &omap3xxx_l4_core__dss_rfbi,
3871         &omap3xxx_l4_core__dss_venc,
3872         NULL
3873 };
3874
3875 int __init omap3xxx_hwmod_init(void)
3876 {
3877         int r;
3878         struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
3879         unsigned int rev;
3880
3881         omap_hwmod_init();
3882
3883         /* Register hwmod links common to all OMAP3 */
3884         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3885         if (r < 0)
3886                 return r;
3887
3888         rev = omap_rev();
3889
3890         /*
3891          * Register hwmod links common to individual OMAP3 families, all
3892          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3893          * All possible revisions should be included in this conditional.
3894          */
3895         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3896             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3897             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3898                 h = omap34xx_hwmod_ocp_ifs;
3899                 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3900         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3901                 h = am35xx_hwmod_ocp_ifs;
3902                 h_gp = am35xx_gp_hwmod_ocp_ifs;
3903         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3904                    rev == OMAP3630_REV_ES1_2) {
3905                 h = omap36xx_hwmod_ocp_ifs;
3906                 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3907         } else {
3908                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3909                 return -EINVAL;
3910         }
3911
3912         r = omap_hwmod_register_links(h);
3913         if (r < 0)
3914                 return r;
3915
3916         /* Register GP-only hwmod links. */
3917         if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3918                 r = omap_hwmod_register_links(h_gp);
3919                 if (r < 0)
3920                         return r;
3921         }
3922
3923
3924         /*
3925          * Register hwmod links specific to certain ES levels of a
3926          * particular family of silicon (e.g., 34xx ES1.0)
3927          */
3928         h = NULL;
3929         if (rev == OMAP3430_REV_ES1_0) {
3930                 h = omap3430es1_hwmod_ocp_ifs;
3931         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3932                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3933                    rev == OMAP3430_REV_ES3_1_2) {
3934                 h = omap3430es2plus_hwmod_ocp_ifs;
3935         }
3936
3937         if (h) {
3938                 r = omap_hwmod_register_links(h);
3939                 if (r < 0)
3940                         return r;
3941         }
3942
3943         h = NULL;
3944         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3945             rev == OMAP3430_REV_ES2_1) {
3946                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3947         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3948                    rev == OMAP3430_REV_ES3_1_2) {
3949                 h = omap3430_es3plus_hwmod_ocp_ifs;
3950         }
3951
3952         if (h)
3953                 r = omap_hwmod_register_links(h);
3954         if (r < 0)
3955                 return r;
3956
3957         /*
3958          * DSS code presumes that dss_core hwmod is handled first,
3959          * _before_ any other DSS related hwmods so register common
3960          * DSS hwmod links last to ensure that dss_core is already
3961          * registered.  Otherwise some change things may happen, for
3962          * ex. if dispc is handled before dss_core and DSS is enabled
3963          * in bootloader DISPC will be reset with outputs enabled
3964          * which sometimes leads to unrecoverable L3 error.  XXX The
3965          * long-term fix to this is to ensure hwmods are set up in
3966          * dependency order in the hwmod core code.
3967          */
3968         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3969
3970         return r;
3971 }