arch/arm/boot/dts/sun5i-a13.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         cpus {
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a8";
  22                 };
  23         };
  24
  25         memory {
  26                 reg = <0x40000000 0x20000000>;
  27         };
  28
  29         clocks {
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 ranges;
  33
  34                 /*
  35                  * This is a dummy clock, to be used as placeholder on
  36                  * other mux clocks when a specific parent clock is not
  37                  * yet implemented. It should be dropped when the driver
  38                  * is complete.
  39                  */
  40                 dummy: dummy {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <0>;
  44                 };
  45
  46                 osc24M: osc24M@01c20050 {
  47                         #clock-cells = <0>;
  48                         compatible = "allwinner,sun4i-osc-clk";
  49                         reg = <0x01c20050 0x4>;
  50                         clock-frequency = <24000000>;
  51                 };
  52
  53                 osc32k: osc32k {
  54                         #clock-cells = <0>;
  55                         compatible = "fixed-clock";
  56                         clock-frequency = <32768>;
  57                 };
  58
  59                 pll1: pll1@01c20000 {
  60                         #clock-cells = <0>;
  61                         compatible = "allwinner,sun4i-pll1-clk";
  62                         reg = <0x01c20000 0x4>;
  63                         clocks = <&osc24M>;
  64                 };
  65
  66                 /* dummy is 200M */
  67                 cpu: cpu@01c20054 {
  68                         #clock-cells = <0>;
  69                         compatible = "allwinner,sun4i-cpu-clk";
  70                         reg = <0x01c20054 0x4>;
  71                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  72                 };
  73
  74                 axi: axi@01c20054 {
  75                         #clock-cells = <0>;
  76                         compatible = "allwinner,sun4i-axi-clk";
  77                         reg = <0x01c20054 0x4>;
  78                         clocks = <&cpu>;
  79                 };
  80
  81                 axi_gates: axi_gates@01c2005c {
  82                         #clock-cells = <1>;
  83                         compatible = "allwinner,sun4i-axi-gates-clk";
  84                         reg = <0x01c2005c 0x4>;
  85                         clocks = <&axi>;
  86                         clock-output-names = "axi_dram";
  87                 };
  88
  89                 ahb: ahb@01c20054 {
  90                         #clock-cells = <0>;
  91                         compatible = "allwinner,sun4i-ahb-clk";
  92                         reg = <0x01c20054 0x4>;
  93                         clocks = <&axi>;
  94                 };
  95
  96                 ahb_gates: ahb_gates@01c20060 {
  97                         #clock-cells = <1>;
  98                         compatible = "allwinner,sun5i-a13-ahb-gates-clk";
  99                         reg = <0x01c20060 0x8>;
 100                         clocks = <&ahb>;
 101                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 102                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 103                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 104                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
 105                                 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
 106                                 "ahb_de_fe", "ahb_iep", "ahb_mali400";
 107                 };
 108
 109                 apb0: apb0@01c20054 {
 110                         #clock-cells = <0>;
 111                         compatible = "allwinner,sun4i-apb0-clk";
 112                         reg = <0x01c20054 0x4>;
 113                         clocks = <&ahb>;
 114                 };
 115
 116                 apb0_gates: apb0_gates@01c20068 {
 117                         #clock-cells = <1>;
 118                         compatible = "allwinner,sun5i-a13-apb0-gates-clk";
 119                         reg = <0x01c20068 0x4>;
 120                         clocks = <&apb0>;
 121                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
 122                 };
 123
 124                 /* dummy is pll6 */
 125                 apb1_mux: apb1_mux@01c20058 {
 126                         #clock-cells = <0>;
 127                         compatible = "allwinner,sun4i-apb1-mux-clk";
 128                         reg = <0x01c20058 0x4>;
 129                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 130                 };
 131
 132                 apb1: apb1@01c20058 {
 133                         #clock-cells = <0>;
 134                         compatible = "allwinner,sun4i-apb1-clk";
 135                         reg = <0x01c20058 0x4>;
 136                         clocks = <&apb1_mux>;
 137                 };
 138
 139                 apb1_gates: apb1_gates@01c2006c {
 140                         #clock-cells = <1>;
 141                         compatible = "allwinner,sun5i-a13-apb1-gates-clk";
 142                         reg = <0x01c2006c 0x4>;
 143                         clocks = <&apb1>;
 144                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 145                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
 146                 };
 147         };
 148
 149         soc@01c20000 {
 150                 compatible = "simple-bus";
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 reg = <0x01c20000 0x300000>;
 154                 ranges;
 155
 156                 intc: interrupt-controller@01c20400 {
 157                         compatible = "allwinner,sun4i-ic";
 158                         reg = <0x01c20400 0x400>;
 159                         interrupt-controller;
 160                         #interrupt-cells = <1>;
 161                 };
 162
 163                 pio: pinctrl@01c20800 {
 164                         compatible = "allwinner,sun5i-a13-pinctrl";
 165                         reg = <0x01c20800 0x400>;
 166                         clocks = <&apb0_gates 5>;
 167                         gpio-controller;
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         #gpio-cells = <3>;
 171
 172                         uart1_pins_a: uart1@0 {
 173                                 allwinner,pins = "PE10", "PE11";
 174                                 allwinner,function = "uart1";
 175                                 allwinner,drive = <0>;
 176                                 allwinner,pull = <0>;
 177                         };
 178
 179                         uart1_pins_b: uart1@1 {
 180                                 allwinner,pins = "PG3", "PG4";
 181                                 allwinner,function = "uart1";
 182                                 allwinner,drive = <0>;
 183                                 allwinner,pull = <0>;
 184                         };
 185                 };
 186
 187                 timer@01c20c00 {
 188                         compatible = "allwinner,sun4i-timer";
 189                         reg = <0x01c20c00 0x90>;
 190                         interrupts = <22>;
 191                         clocks = <&osc24M>;
 192                 };
 193
 194                 wdt: watchdog@01c20c90 {
 195                         compatible = "allwinner,sun4i-wdt";
 196                         reg = <0x01c20c90 0x10>;
 197                 };
 198
 199                 uart1: serial@01c28400 {
 200                         compatible = "snps,dw-apb-uart";
 201                         reg = <0x01c28400 0x400>;
 202                         interrupts = <2>;
 203                         reg-shift = <2>;
 204                         reg-io-width = <4>;
 205                         clocks = <&apb1_gates 17>;
 206                         status = "disabled";
 207                 };
 208
 209                 uart3: serial@01c28c00 {
 210                         compatible = "snps,dw-apb-uart";
 211                         reg = <0x01c28c00 0x400>;
 212                         interrupts = <4>;
 213                         reg-shift = <2>;
 214                         reg-io-width = <4>;
 215                         clocks = <&apb1_gates 19>;
 216                         status = "disabled";
 217                 };
 218         };
 219 };