2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
73 * Returns true on success, false on failure.
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
86 intel_pch_rawclk(struct drm_device *dev)
88 struct drm_i915_private *dev_priv = dev->dev_private;
90 WARN_ON(!HAS_PCH_SPLIT(dev));
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
109 static inline u32 /* units of 100MHz */
110 intel_fdi_link_freq(struct drm_device *dev)
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
130 .find_pll = intel_find_best_PLL,
133 static const intel_limit_t intel_limits_i8xx_lvds = {
134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
144 .find_pll = intel_find_best_PLL,
147 static const intel_limit_t intel_limits_i9xx_sdvo = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
158 .find_pll = intel_find_best_PLL,
161 static const intel_limit_t intel_limits_i9xx_lvds = {
162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
172 .find_pll = intel_find_best_PLL,
176 static const intel_limit_t intel_limits_g4x_sdvo = {
177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
189 .find_pll = intel_g4x_find_best_PLL,
192 static const intel_limit_t intel_limits_g4x_hdmi = {
193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
203 .find_pll = intel_g4x_find_best_PLL,
206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
218 .find_pll = intel_g4x_find_best_PLL,
221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
233 .find_pll = intel_g4x_find_best_PLL,
236 static const intel_limit_t intel_limits_pineview_sdvo = {
237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
239 /* Pineview's Ncounter is a ring counter */
240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
242 /* Pineview only has one combined m divider, which we treat as m2. */
243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 .find_pll = intel_find_best_PLL,
252 static const intel_limit_t intel_limits_pineview_lvds = {
253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
263 .find_pll = intel_find_best_PLL,
266 /* Ironlake / Sandybridge
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
271 static const intel_limit_t intel_limits_ironlake_dac = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
282 .find_pll = intel_g4x_find_best_PLL,
285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
296 .find_pll = intel_g4x_find_best_PLL,
299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 .find_pll = intel_g4x_find_best_PLL,
313 /* LVDS 100mhz refclk limits. */
314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
322 .p1 = { .min = 2, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
325 .find_pll = intel_g4x_find_best_PLL,
328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
336 .p1 = { .min = 2, .max = 6 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 .find_pll = intel_g4x_find_best_PLL,
342 static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
356 static const intel_limit_t intel_limits_vlv_hdmi = {
357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
370 static const intel_limit_t intel_limits_vlv_dp = {
371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
373 .n = { .min = 1, .max = 7 },
374 .m = { .min = 22, .max = 450 },
375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
378 .p1 = { .min = 1, .max = 3 },
379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
401 return I915_READ(DPIO_DATA);
404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
424 struct drm_device *dev = crtc->dev;
425 const intel_limit_t *limit;
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
428 if (intel_is_dual_link_lvds(dev)) {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_dual_lvds_100m;
432 limit = &intel_limits_ironlake_dual_lvds;
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_single_lvds_100m;
437 limit = &intel_limits_ironlake_single_lvds;
440 limit = &intel_limits_ironlake_dac;
445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
447 struct drm_device *dev = crtc->dev;
448 const intel_limit_t *limit;
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev))
452 limit = &intel_limits_g4x_dual_channel_lvds;
454 limit = &intel_limits_g4x_single_channel_lvds;
455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
457 limit = &intel_limits_g4x_hdmi;
458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
459 limit = &intel_limits_g4x_sdvo;
460 } else /* The option is for other outputs */
461 limit = &intel_limits_i9xx_sdvo;
466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
471 if (HAS_PCH_SPLIT(dev))
472 limit = intel_ironlake_limit(crtc, refclk);
473 else if (IS_G4X(dev)) {
474 limit = intel_g4x_limit(crtc);
475 } else if (IS_PINEVIEW(dev)) {
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
477 limit = &intel_limits_pineview_lvds;
479 limit = &intel_limits_pineview_sdvo;
480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
486 limit = &intel_limits_vlv_dp;
487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
491 limit = &intel_limits_i9xx_sdvo;
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
494 limit = &intel_limits_i8xx_lvds;
496 limit = &intel_limits_i8xx_dvo;
501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
502 static void pineview_clock(int refclk, intel_clock_t *clock)
504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
521 clock->m = i9xx_dpll_compute_m(clock);
522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
528 * Returns whether any output on the specified pipe is of the specified type
530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
532 struct drm_device *dev = crtc->dev;
533 struct intel_encoder *encoder;
535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
553 INTELPllInvalid("p1 out of range\n");
554 if (clock->p < limit->p.min || limit->p.max < clock->p)
555 INTELPllInvalid("p out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
561 INTELPllInvalid("m1 <= m2\n");
562 if (clock->m < limit->m.min || limit->m.max < clock->m)
563 INTELPllInvalid("m out of range\n");
564 if (clock->n < limit->n.min || limit->n.max < clock->n)
565 INTELPllInvalid("n out of range\n");
566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
567 INTELPllInvalid("vco out of range\n");
568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
572 INTELPllInvalid("dot out of range\n");
578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
583 struct drm_device *dev = crtc->dev;
587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
593 if (intel_is_dual_link_lvds(dev))
594 clock.p2 = limit->p2.p2_fast;
596 clock.p2 = limit->p2.p2_slow;
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
601 clock.p2 = limit->p2.p2_fast;
604 memset(best_clock, 0, sizeof(*best_clock));
606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
619 intel_clock(dev, refclk, &clock);
620 if (!intel_PLL_is_valid(dev, limit,
624 clock.p != match_clock->p)
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
637 return (err != target);
641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
645 struct drm_device *dev = crtc->dev;
649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
656 if (HAS_PCH_SPLIT(dev))
660 if (intel_is_dual_link_lvds(dev))
661 clock.p2 = limit->p2.p2_fast;
663 clock.p2 = limit->p2.p2_slow;
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
668 clock.p2 = limit->p2.p2_fast;
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
673 /* based on hardware requirement, prefer smaller n to precision */
674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
675 /* based on hardware requirement, prefere larger m1,m2 */
676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
684 intel_clock(dev, refclk, &clock);
685 if (!intel_PLL_is_valid(dev, limit,
689 this_err = abs(clock.dot - target);
690 if (this_err < err_most) {
704 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
715 dotclk = target * 1000;
718 fastclk = dotclk / (2*100);
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
746 if (absppm < bestppm - 10) {
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
772 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
778 return intel_crtc->config.cpu_transcoder;
781 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
786 frame = I915_READ(frame_reg);
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
793 * intel_wait_for_vblank - wait for vblank on a given pipe
795 * @pipe: pipe to wait for
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
800 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 int pipestat_reg = PIPESTAT(pipe);
805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
826 /* Wait for vblank interrupt bit to set */
827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
830 DRM_DEBUG_KMS("vblank wait timed out\n");
834 * intel_wait_for_pipe_off - wait for pipe to turn off
836 * @pipe: pipe to wait for
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
843 * wait for the pipe register state bit to turn off
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
850 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
852 struct drm_i915_private *dev_priv = dev->dev_private;
853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
856 if (INTEL_INFO(dev)->gen >= 4) {
857 int reg = PIPECONF(cpu_transcoder);
859 /* Wait for the Pipe State to go off */
860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
862 WARN(1, "pipe_off wait timed out\n");
864 u32 last_line, line_mask;
865 int reg = PIPEDSL(pipe);
866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
869 line_mask = DSL_LINEMASK_GEN2;
871 line_mask = DSL_LINEMASK_GEN3;
873 /* Wait for the display line to settle */
875 last_line = I915_READ(reg) & line_mask;
877 } while (((I915_READ(reg) & line_mask) != last_line) &&
878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
880 WARN(1, "pipe_off wait timed out\n");
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
889 * Returns true if @port is connected, false otherwise.
891 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
896 if (HAS_PCH_IBX(dev_priv->dev)) {
899 bit = SDE_PORTB_HOTPLUG;
902 bit = SDE_PORTC_HOTPLUG;
905 bit = SDE_PORTD_HOTPLUG;
913 bit = SDE_PORTB_HOTPLUG_CPT;
916 bit = SDE_PORTC_HOTPLUG_CPT;
919 bit = SDE_PORTD_HOTPLUG_CPT;
926 return I915_READ(SDEISR) & bit;
929 static const char *state_string(bool enabled)
931 return enabled ? "on" : "off";
934 /* Only for pre-ILK configs */
935 static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
949 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
950 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
953 static void assert_pch_pll(struct drm_i915_private *dev_priv,
954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
987 "PLL[%d] not %s on this transcoder %c: %08x\n",
988 pll->pll_reg == _PCH_DPLL_B,
990 pipe_name(crtc->pipe),
995 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
998 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1010 val = I915_READ(reg);
1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1021 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1024 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1038 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1041 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1052 if (HAS_DDI(dev_priv->dev))
1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1060 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1071 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1074 int pp_reg, lvds_reg;
1076 enum pipe panel_pipe = PIPE_A;
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1083 pp_reg = PP_CONTROL;
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
1100 void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1113 if (!intel_display_power_enabled(dev_priv->dev,
1114 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
1124 pipe_name(pipe), state_string(state), state_string(cur_state));
1127 static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
1142 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1145 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1152 /* Planes are fixed to pipes on ILK+ */
1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
1174 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
1193 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1209 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1216 reg = PCH_TRANSCONF(pipe);
1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1224 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
1227 if ((val & DP_PORT_EN) == 0)
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1242 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1245 if ((val & SDVO_ENABLE) == 0)
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1258 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1261 if ((val & LVDS_PORT_EN) == 0)
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1274 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1289 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, int reg, u32 port_sel)
1292 u32 val = I915_READ(reg);
1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1295 reg, pipe_name(pipe));
1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
1299 "IBX PCH dp port still using transcoder B\n");
1302 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1305 u32 val = I915_READ(reg);
1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1308 reg, pipe_name(pipe));
1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1311 && (val & SDVO_PIPE_B_SELECT),
1312 "IBX PCH hdmi port still using transcoder B\n");
1315 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1326 val = I915_READ(reg);
1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
1332 val = I915_READ(reg);
1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1351 * Note! This is for pre-ILK only.
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1355 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1360 assert_pipe_disabled(dev_priv, pipe);
1362 /* No really, not for ILK+ */
1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1382 udelay(150); /* wait for warmup */
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1392 * Note! This is for pre-ILK only.
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1415 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1445 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
1457 I915_WRITE(SBI_ADDR, (reg << 16));
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1471 return I915_READ(SBI_DATA);
1474 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1481 port_mask = DPLL_PORTC_READY_MASK;
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1489 * ironlake_enable_pch_pll - enable PCH PLL
1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1496 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1499 struct intel_pch_pll *pll;
1503 /* PCH PLLs only available on ILK, SNB and IVB */
1504 BUG_ON(dev_priv->info->gen < 5);
1505 pll = intel_crtc->pch_pll;
1509 if (WARN_ON(pll->refcount == 0))
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1519 if (pll->active++ && pll->on) {
1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1536 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
1548 if (WARN_ON(pll->refcount == 0))
1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
1555 if (WARN_ON(pll->active == 0)) {
1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
1560 if (--pll->active) {
1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1567 /* Make sure transcoder isn't still depending on us */
1568 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1583 struct drm_device *dev = dev_priv->dev;
1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585 uint32_t reg, val, pipeconf_val;
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1590 /* Make sure PCH DPLL is enabled */
1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
1608 reg = PCH_TRANSCONF(pipe);
1609 val = I915_READ(reg);
1610 pipeconf_val = I915_READ(PIPECONF(pipe));
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1627 val |= TRANS_INTERLACED;
1629 val |= TRANS_PROGRESSIVE;
1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637 enum transcoder cpu_transcoder)
1639 u32 val, pipeconf_val;
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1644 /* FDI must be feeding us bits for PCH ports */
1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
1658 val |= TRANS_INTERLACED;
1660 val |= TRANS_PROGRESSIVE;
1662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1670 struct drm_device *dev = dev_priv->dev;
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1680 reg = PCH_TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1701 val = I915_READ(LPT_TRANSCONF);
1702 val &= ~TRANS_ENABLE;
1703 I915_WRITE(LPT_TRANSCONF, val);
1704 /* wait for PCH transcoder off, transcoder state */
1705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711 I915_WRITE(_TRANSA_CHICKEN2, val);
1715 * intel_enable_pipe - enable a pipe, asserting requirements
1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1723 * @pipe should be %PIPE_A or %PIPE_B.
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1733 enum pipe pch_transcoder;
1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1740 if (HAS_PCH_LPT(dev_priv->dev))
1741 pch_transcoder = TRANSCODER_A;
1743 pch_transcoder = pipe;
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
1754 /* if driving the PCH, we need FDI enabled */
1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
1759 /* FIXME: assert CPU port conditions for SNB+ */
1762 reg = PIPECONF(cpu_transcoder);
1763 val = I915_READ(reg);
1764 if (val & PIPECONF_ENABLE)
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1772 * intel_disable_pipe - disable a pipe, asserting requirements
1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1779 * @pipe should be %PIPE_A or %PIPE_B.
1781 * Will wait until the pipe has shut down before returning.
1783 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1795 assert_planes_disabled(dev_priv, pipe);
1796 assert_sprites_disabled(dev_priv, pipe);
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1802 reg = PIPECONF(cpu_transcoder);
1803 val = I915_READ(reg);
1804 if ((val & PIPECONF_ENABLE) == 0)
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1815 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
1843 if (val & DISPLAY_PLANE_ENABLE)
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847 intel_flush_display_plane(dev_priv, plane);
1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1857 * Disable @plane; should be an independent operation.
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1875 static bool need_vtd_wa(struct drm_device *dev)
1877 #ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1885 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1886 struct drm_i915_gem_object *obj,
1887 struct intel_ring_buffer *pipelined)
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1893 switch (obj->tiling_mode) {
1894 case I915_TILING_NONE:
1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
1897 else if (INTEL_INFO(dev)->gen >= 4)
1898 alignment = 4 * 1024;
1900 alignment = 64 * 1024;
1903 /* pin() will align the object as required by fence */
1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1924 dev_priv->mm.interruptible = false;
1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1927 goto err_interruptible;
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1934 ret = i915_gem_object_get_fence(obj);
1938 i915_gem_object_pin_fence(obj);
1940 dev_priv->mm.interruptible = true;
1944 i915_gem_object_unpin(obj);
1946 dev_priv->mm.interruptible = true;
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
1958 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
1969 tiles = *x / (512/cpp);
1972 return tile_rows * pitch * 8 + tiles * 4096;
1974 unsigned int offset;
1976 offset = *y * pitch + *x * cpp;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1983 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
1990 struct drm_i915_gem_object *obj;
1991 int plane = intel_crtc->plane;
1992 unsigned long linear_offset;
2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2012 switch (fb->pixel_format) {
2014 dspcntr |= DISPPLANE_8BPP;
2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
2043 if (INTEL_INFO(dev)->gen >= 4) {
2044 if (obj->tiling_mode != I915_TILING_NONE)
2045 dspcntr |= DISPPLANE_TILED;
2047 dspcntr &= ~DISPPLANE_TILED;
2050 I915_WRITE(reg, dspcntr);
2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2059 linear_offset -= intel_crtc->dspaddr_offset;
2061 intel_crtc->dspaddr_offset = linear_offset;
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2067 if (INTEL_INFO(dev)->gen >= 4) {
2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2079 static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
2088 unsigned long linear_offset;
2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2109 switch (fb->pixel_format) {
2111 dspcntr |= DISPPLANE_8BPP;
2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2139 dspcntr &= ~DISPPLANE_TILED;
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2144 I915_WRITE(reg, dspcntr);
2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2147 intel_crtc->dspaddr_offset =
2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2151 linear_offset -= intel_crtc->dspaddr_offset;
2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
2179 intel_increase_pllclock(crtc);
2181 return dev_priv->display.update_plane(crtc, fb, x, y);
2184 void intel_display_handle_reset(struct drm_device *dev)
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2218 mutex_unlock(&crtc->mutex);
2223 intel_finish_fb(struct drm_framebuffer *old_fb)
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2245 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251 if (!dev->primary->master)
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2258 switch (intel_crtc->pipe) {
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2273 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2274 struct drm_framebuffer *fb)
2276 struct drm_device *dev = crtc->dev;
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279 struct drm_framebuffer *old_fb;
2284 DRM_ERROR("No FB bound\n");
2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
2295 mutex_lock(&dev->struct_mutex);
2296 ret = intel_pin_and_fence_fb_obj(dev,
2297 to_intel_framebuffer(fb)->obj,
2300 mutex_unlock(&dev->struct_mutex);
2301 DRM_ERROR("pin & fence failed\n");
2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2308 mutex_unlock(&dev->struct_mutex);
2309 DRM_ERROR("failed to update base address\n");
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2323 intel_update_fbc(dev);
2324 mutex_unlock(&dev->struct_mutex);
2326 intel_crtc_update_sarea_pos(crtc, x, y);
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
2342 if (IS_IVYBRIDGE(dev)) {
2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2349 I915_WRITE(reg, temp);
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2362 /* wait one idle pattern time */
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
2372 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2377 static void ivb_modeset_global_resources(struct drm_device *dev)
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
2410 int plane = intel_crtc->plane;
2411 u32 reg, temp, tries;
2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
2423 I915_WRITE(reg, temp);
2427 /* enable CPU FDI TX and PCH FDI RX */
2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
2450 reg = FDI_RX_IIR(pipe);
2451 for (tries = 0; tries < 5; tries++) {
2452 temp = I915_READ(reg);
2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2462 DRM_ERROR("FDI train 1 fail!\n");
2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 I915_WRITE(reg, temp);
2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
2475 I915_WRITE(reg, temp);
2480 reg = FDI_RX_IIR(pipe);
2481 for (tries = 0; tries < 5; tries++) {
2482 temp = I915_READ(reg);
2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2492 DRM_ERROR("FDI train 2 fail!\n");
2494 DRM_DEBUG_KMS("FDI train done\n");
2498 static const int snb_b_fdi_train_param[] = {
2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
2512 u32 reg, temp, i, retry;
2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
2520 I915_WRITE(reg, temp);
2525 /* enable CPU FDI TX and PCH FDI RX */
2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2554 for (i = 0; i < 4; i++) {
2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
2559 I915_WRITE(reg, temp);
2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579 DRM_ERROR("FDI train 1 fail!\n");
2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2591 I915_WRITE(reg, temp);
2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2602 I915_WRITE(reg, temp);
2607 for (i = 0; i < 4; i++) {
2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
2612 I915_WRITE(reg, temp);
2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632 DRM_ERROR("FDI train 2 fail!\n");
2634 DRM_DEBUG_KMS("FDI train done.\n");
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2660 /* enable CPU FDI TX and PCH FDI RX */
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2664 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2669 temp |= FDI_COMPOSITE_SYNC;
2670 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2672 I915_WRITE(FDI_RX_MISC(pipe),
2673 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_AUTO;
2678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2680 temp |= FDI_COMPOSITE_SYNC;
2681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2686 for (i = 0; i < 4; i++) {
2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700 if (temp & FDI_RX_BIT_LOCK ||
2701 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2703 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2708 DRM_ERROR("FDI train 1 fail!\n");
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717 I915_WRITE(reg, temp);
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723 I915_WRITE(reg, temp);
2728 for (i = 0; i < 4; i++) {
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= snb_b_fdi_train_param[i];
2733 I915_WRITE(reg, temp);
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2742 if (temp & FDI_RX_SYMBOL_LOCK) {
2743 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2744 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2749 DRM_ERROR("FDI train 2 fail!\n");
2751 DRM_DEBUG_KMS("FDI train done.\n");
2754 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2756 struct drm_device *dev = intel_crtc->base.dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 int pipe = intel_crtc->pipe;
2762 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2766 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2768 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2773 /* Switch from Rawclk to PCDclk */
2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp | FDI_PCDCLK);
2780 /* Enable CPU FDI TX PLL, always on for Ironlake */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2791 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2793 struct drm_device *dev = intel_crtc->base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 int pipe = intel_crtc->pipe;
2798 /* Switch from PCDclk to Rawclk */
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2803 /* Disable CPU FDI TX PLL */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2815 /* Wait for the clocks to turn off. */
2820 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2828 /* disable CPU FDI tx and PCH FDI rx */
2829 reg = FDI_TX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834 reg = FDI_RX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~(0x7 << 16);
2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2838 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2843 /* Ironlake workaround, disable clock pointer after downing FDI */
2844 if (HAS_PCH_IBX(dev)) {
2845 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2848 /* still set train pattern 1 */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_1;
2853 I915_WRITE(reg, temp);
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if (HAS_PCH_CPT(dev)) {
2858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1;
2864 /* BPC in FDI rx is consistent with that in PIPECONF */
2865 temp &= ~(0x07 << 16);
2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2867 I915_WRITE(reg, temp);
2873 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2875 struct drm_device *dev = crtc->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878 unsigned long flags;
2881 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2885 spin_lock_irqsave(&dev->event_lock, flags);
2886 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887 spin_unlock_irqrestore(&dev->event_lock, flags);
2892 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2894 struct drm_device *dev = crtc->dev;
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2897 if (crtc->fb == NULL)
2900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2902 wait_event(dev_priv->pending_flip_queue,
2903 !intel_crtc_has_pending_flip(crtc));
2905 mutex_lock(&dev->struct_mutex);
2906 intel_finish_fb(crtc->fb);
2907 mutex_unlock(&dev->struct_mutex);
2910 /* Program iCLKIP clock to the desired frequency */
2911 static void lpt_program_iclkip(struct drm_crtc *crtc)
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2918 mutex_lock(&dev_priv->dpio_lock);
2920 /* It is necessary to ungate the pixclk gate prior to programming
2921 * the divisors, and gate it back when it is done.
2923 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2925 /* Disable SSCCTL */
2926 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2927 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2932 if (crtc->mode.clock == 20000) {
2937 /* The iCLK virtual clock root frequency is in MHz,
2938 * but the crtc->mode.clock in in KHz. To get the divisors,
2939 * it is necessary to divide one by another, so we
2940 * convert the virtual clock precision to KHz here for higher
2943 u32 iclk_virtual_root_freq = 172800 * 1000;
2944 u32 iclk_pi_range = 64;
2945 u32 desired_divisor, msb_divisor_value, pi_value;
2947 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2948 msb_divisor_value = desired_divisor / iclk_pi_range;
2949 pi_value = desired_divisor % iclk_pi_range;
2952 divsel = msb_divisor_value - 2;
2953 phaseinc = pi_value;
2956 /* This should not happen with any sane values */
2957 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2958 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2959 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2960 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2962 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2969 /* Program SSCDIVINTPHASE6 */
2970 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2971 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2972 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2973 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2974 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2975 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2976 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2977 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2979 /* Program SSCAUXDIV */
2980 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2981 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2983 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2985 /* Enable modulator and associated divider */
2986 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2987 temp &= ~SBI_SSCCTL_DISABLE;
2988 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2990 /* Wait for initialization time */
2993 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2995 mutex_unlock(&dev_priv->dpio_lock);
2998 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2999 enum pipe pch_transcoder)
3001 struct drm_device *dev = crtc->base.dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3005 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3006 I915_READ(HTOTAL(cpu_transcoder)));
3007 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3008 I915_READ(HBLANK(cpu_transcoder)));
3009 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3010 I915_READ(HSYNC(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3013 I915_READ(VTOTAL(cpu_transcoder)));
3014 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3015 I915_READ(VBLANK(cpu_transcoder)));
3016 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3017 I915_READ(VSYNC(cpu_transcoder)));
3018 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3019 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023 * Enable PCH resources required for PCH ports:
3025 * - FDI training & RX/TX
3026 * - update transcoder timings
3027 * - DP transcoding bits
3030 static void ironlake_pch_enable(struct drm_crtc *crtc)
3032 struct drm_device *dev = crtc->dev;
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035 int pipe = intel_crtc->pipe;
3038 assert_pch_transcoder_disabled(dev_priv, pipe);
3040 /* Write the TU size bits before fdi link training, so that error
3041 * detection works. */
3042 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3043 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3045 /* For PCH output, training FDI link */
3046 dev_priv->display.fdi_link_train(crtc);
3048 /* XXX: pch pll's can be enabled any time before we enable the PCH
3049 * transcoder, and we actually should do this to not upset any PCH
3050 * transcoder that already use the clock when we share it.
3052 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3053 * unconditionally resets the pll - we need that to have the right LVDS
3054 * enable sequence. */
3055 ironlake_enable_pch_pll(intel_crtc);
3057 if (HAS_PCH_CPT(dev)) {
3060 temp = I915_READ(PCH_DPLL_SEL);
3064 temp |= TRANSA_DPLL_ENABLE;
3065 sel = TRANSA_DPLLB_SEL;
3068 temp |= TRANSB_DPLL_ENABLE;
3069 sel = TRANSB_DPLLB_SEL;
3072 temp |= TRANSC_DPLL_ENABLE;
3073 sel = TRANSC_DPLLB_SEL;
3076 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3080 I915_WRITE(PCH_DPLL_SEL, temp);
3083 /* set transcoder timing, panel must allow it */
3084 assert_panel_unlocked(dev_priv, pipe);
3085 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3087 intel_fdi_normal_train(crtc);
3089 /* For PCH DP, enable TRANS_DP_CTL */
3090 if (HAS_PCH_CPT(dev) &&
3091 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3092 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3093 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3094 reg = TRANS_DP_CTL(pipe);
3095 temp = I915_READ(reg);
3096 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3097 TRANS_DP_SYNC_MASK |
3099 temp |= (TRANS_DP_OUTPUT_ENABLE |
3100 TRANS_DP_ENH_FRAMING);
3101 temp |= bpc << 9; /* same format but at 11:9 */
3103 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3104 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3105 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3106 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3108 switch (intel_trans_dp_port_sel(crtc)) {
3110 temp |= TRANS_DP_PORT_SEL_B;
3113 temp |= TRANS_DP_PORT_SEL_C;
3116 temp |= TRANS_DP_PORT_SEL_D;
3122 I915_WRITE(reg, temp);
3125 ironlake_enable_pch_transcoder(dev_priv, pipe);
3128 static void lpt_pch_enable(struct drm_crtc *crtc)
3130 struct drm_device *dev = crtc->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3135 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3137 lpt_program_iclkip(crtc);
3139 /* Set transcoder timing. */
3140 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3142 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3145 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3147 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3152 if (pll->refcount == 0) {
3153 WARN(1, "bad PCH PLL refcount\n");
3158 intel_crtc->pch_pll = NULL;
3161 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3163 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3164 struct intel_pch_pll *pll;
3167 pll = intel_crtc->pch_pll;
3169 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3170 intel_crtc->base.base.id, pll->pll_reg);
3174 if (HAS_PCH_IBX(dev_priv->dev)) {
3175 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3176 i = intel_crtc->pipe;
3177 pll = &dev_priv->pch_plls[i];
3179 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3180 intel_crtc->base.base.id, pll->pll_reg);
3185 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186 pll = &dev_priv->pch_plls[i];
3188 /* Only want to check enabled timings first */
3189 if (pll->refcount == 0)
3192 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3193 fp == I915_READ(pll->fp0_reg)) {
3194 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3195 intel_crtc->base.base.id,
3196 pll->pll_reg, pll->refcount, pll->active);
3202 /* Ok no matching timings, maybe there's a free one? */
3203 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3204 pll = &dev_priv->pch_plls[i];
3205 if (pll->refcount == 0) {
3206 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3207 intel_crtc->base.base.id, pll->pll_reg);
3215 intel_crtc->pch_pll = pll;
3217 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3218 prepare: /* separate function? */
3219 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3221 /* Wait for the clocks to stabilize before rewriting the regs */
3222 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3223 POSTING_READ(pll->pll_reg);
3226 I915_WRITE(pll->fp0_reg, fp);
3227 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3232 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 int dslreg = PIPEDSL(pipe);
3238 temp = I915_READ(dslreg);
3240 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3241 if (wait_for(I915_READ(dslreg) != temp, 5))
3242 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3246 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3248 struct drm_device *dev = crtc->base.dev;
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 int pipe = crtc->pipe;
3252 if (crtc->config.pch_pfit.size) {
3253 /* Force use of hard-coded filter coefficients
3254 * as some pre-programmed values are broken,
3257 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3259 PF_PIPE_SEL_IVB(pipe));
3261 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3262 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3263 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3267 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3269 struct drm_device *dev = crtc->dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272 struct intel_encoder *encoder;
3273 int pipe = intel_crtc->pipe;
3274 int plane = intel_crtc->plane;
3277 WARN_ON(!crtc->enabled);
3279 if (intel_crtc->active)
3282 intel_crtc->active = true;
3284 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3285 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3287 intel_update_watermarks(dev);
3289 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3290 temp = I915_READ(PCH_LVDS);
3291 if ((temp & LVDS_PORT_EN) == 0)
3292 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3296 if (intel_crtc->config.has_pch_encoder) {
3297 /* Note: FDI PLL enabling _must_ be done before we enable the
3298 * cpu pipes, hence this is separate from all the other fdi/pch
3300 ironlake_fdi_pll_enable(intel_crtc);
3302 assert_fdi_tx_disabled(dev_priv, pipe);
3303 assert_fdi_rx_disabled(dev_priv, pipe);
3306 for_each_encoder_on_crtc(dev, crtc, encoder)
3307 if (encoder->pre_enable)
3308 encoder->pre_enable(encoder);
3310 /* Enable panel fitting for LVDS */
3311 ironlake_pfit_enable(intel_crtc);
3314 * On ILK+ LUT must be loaded before the pipe is running but with
3317 intel_crtc_load_lut(crtc);
3319 intel_enable_pipe(dev_priv, pipe,
3320 intel_crtc->config.has_pch_encoder);
3321 intel_enable_plane(dev_priv, plane, pipe);
3323 if (intel_crtc->config.has_pch_encoder)
3324 ironlake_pch_enable(crtc);
3326 mutex_lock(&dev->struct_mutex);
3327 intel_update_fbc(dev);
3328 mutex_unlock(&dev->struct_mutex);
3330 intel_crtc_update_cursor(crtc, true);
3332 for_each_encoder_on_crtc(dev, crtc, encoder)
3333 encoder->enable(encoder);
3335 if (HAS_PCH_CPT(dev))
3336 cpt_verify_modeset(dev, intel_crtc->pipe);
3339 * There seems to be a race in PCH platform hw (at least on some
3340 * outputs) where an enabled pipe still completes any pageflip right
3341 * away (as if the pipe is off) instead of waiting for vblank. As soon
3342 * as the first vblank happend, everything works as expected. Hence just
3343 * wait for one vblank before returning to avoid strange things
3346 intel_wait_for_vblank(dev, intel_crtc->pipe);
3349 static void haswell_crtc_enable(struct drm_crtc *crtc)
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 struct intel_encoder *encoder;
3355 int pipe = intel_crtc->pipe;
3356 int plane = intel_crtc->plane;
3358 WARN_ON(!crtc->enabled);
3360 if (intel_crtc->active)
3363 intel_crtc->active = true;
3365 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3366 if (intel_crtc->config.has_pch_encoder)
3367 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3369 intel_update_watermarks(dev);
3371 if (intel_crtc->config.has_pch_encoder)
3372 dev_priv->display.fdi_link_train(crtc);
3374 for_each_encoder_on_crtc(dev, crtc, encoder)
3375 if (encoder->pre_enable)
3376 encoder->pre_enable(encoder);
3378 intel_ddi_enable_pipe_clock(intel_crtc);
3380 /* Enable panel fitting for eDP */
3381 ironlake_pfit_enable(intel_crtc);
3384 * On ILK+ LUT must be loaded before the pipe is running but with
3387 intel_crtc_load_lut(crtc);
3389 intel_ddi_set_pipe_settings(crtc);
3390 intel_ddi_enable_transcoder_func(crtc);
3392 intel_enable_pipe(dev_priv, pipe,
3393 intel_crtc->config.has_pch_encoder);
3394 intel_enable_plane(dev_priv, plane, pipe);
3396 if (intel_crtc->config.has_pch_encoder)
3397 lpt_pch_enable(crtc);
3399 mutex_lock(&dev->struct_mutex);
3400 intel_update_fbc(dev);
3401 mutex_unlock(&dev->struct_mutex);
3403 intel_crtc_update_cursor(crtc, true);
3405 for_each_encoder_on_crtc(dev, crtc, encoder)
3406 encoder->enable(encoder);
3409 * There seems to be a race in PCH platform hw (at least on some
3410 * outputs) where an enabled pipe still completes any pageflip right
3411 * away (as if the pipe is off) instead of waiting for vblank. As soon
3412 * as the first vblank happend, everything works as expected. Hence just
3413 * wait for one vblank before returning to avoid strange things
3416 intel_wait_for_vblank(dev, intel_crtc->pipe);
3419 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3421 struct drm_device *dev = crtc->dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424 struct intel_encoder *encoder;
3425 int pipe = intel_crtc->pipe;
3426 int plane = intel_crtc->plane;
3430 if (!intel_crtc->active)
3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 encoder->disable(encoder);
3436 intel_crtc_wait_for_pending_flips(crtc);
3437 drm_vblank_off(dev, pipe);
3438 intel_crtc_update_cursor(crtc, false);
3440 intel_disable_plane(dev_priv, plane, pipe);
3442 if (dev_priv->cfb_plane == plane)
3443 intel_disable_fbc(dev);
3445 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3446 intel_disable_pipe(dev_priv, pipe);
3449 I915_WRITE(PF_CTL(pipe), 0);
3450 I915_WRITE(PF_WIN_SZ(pipe), 0);
3452 for_each_encoder_on_crtc(dev, crtc, encoder)
3453 if (encoder->post_disable)
3454 encoder->post_disable(encoder);
3456 ironlake_fdi_disable(crtc);
3458 ironlake_disable_pch_transcoder(dev_priv, pipe);
3459 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3461 if (HAS_PCH_CPT(dev)) {
3462 /* disable TRANS_DP_CTL */
3463 reg = TRANS_DP_CTL(pipe);
3464 temp = I915_READ(reg);
3465 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3466 temp |= TRANS_DP_PORT_SEL_NONE;
3467 I915_WRITE(reg, temp);
3469 /* disable DPLL_SEL */
3470 temp = I915_READ(PCH_DPLL_SEL);
3473 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3476 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3479 /* C shares PLL A or B */
3480 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3485 I915_WRITE(PCH_DPLL_SEL, temp);
3488 /* disable PCH DPLL */
3489 intel_disable_pch_pll(intel_crtc);
3491 ironlake_fdi_pll_disable(intel_crtc);
3493 intel_crtc->active = false;
3494 intel_update_watermarks(dev);
3496 mutex_lock(&dev->struct_mutex);
3497 intel_update_fbc(dev);
3498 mutex_unlock(&dev->struct_mutex);
3501 static void haswell_crtc_disable(struct drm_crtc *crtc)
3503 struct drm_device *dev = crtc->dev;
3504 struct drm_i915_private *dev_priv = dev->dev_private;
3505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3506 struct intel_encoder *encoder;
3507 int pipe = intel_crtc->pipe;
3508 int plane = intel_crtc->plane;
3509 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3511 if (!intel_crtc->active)
3514 for_each_encoder_on_crtc(dev, crtc, encoder)
3515 encoder->disable(encoder);
3517 intel_crtc_wait_for_pending_flips(crtc);
3518 drm_vblank_off(dev, pipe);
3519 intel_crtc_update_cursor(crtc, false);
3521 intel_disable_plane(dev_priv, plane, pipe);
3523 if (dev_priv->cfb_plane == plane)
3524 intel_disable_fbc(dev);
3526 if (intel_crtc->config.has_pch_encoder)
3527 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3528 intel_disable_pipe(dev_priv, pipe);
3530 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3532 /* XXX: Once we have proper panel fitter state tracking implemented with
3533 * hardware state read/check support we should switch to only disable
3534 * the panel fitter when we know it's used. */
3535 if (intel_display_power_enabled(dev,
3536 POWER_DOMAIN_PIPE_PANEL_FITTER(pipe))) {
3537 I915_WRITE(PF_CTL(pipe), 0);
3538 I915_WRITE(PF_WIN_SZ(pipe), 0);
3541 intel_ddi_disable_pipe_clock(intel_crtc);
3543 for_each_encoder_on_crtc(dev, crtc, encoder)
3544 if (encoder->post_disable)
3545 encoder->post_disable(encoder);
3547 if (intel_crtc->config.has_pch_encoder) {
3548 lpt_disable_pch_transcoder(dev_priv);
3549 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3550 intel_ddi_fdi_disable(crtc);
3553 intel_crtc->active = false;
3554 intel_update_watermarks(dev);
3556 mutex_lock(&dev->struct_mutex);
3557 intel_update_fbc(dev);
3558 mutex_unlock(&dev->struct_mutex);
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564 intel_put_pch_pll(intel_crtc);
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3572 * start using it. */
3573 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3575 intel_ddi_put_crtc_pll(crtc);
3578 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580 if (!enable && intel_crtc->overlay) {
3581 struct drm_device *dev = intel_crtc->base.dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3584 mutex_lock(&dev->struct_mutex);
3585 dev_priv->mm.interruptible = false;
3586 (void) intel_overlay_switch_off(intel_crtc->overlay);
3587 dev_priv->mm.interruptible = true;
3588 mutex_unlock(&dev->struct_mutex);
3591 /* Let userspace switch the overlay on again. In most cases userspace
3592 * has to recompute where to put it anyway.
3597 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3598 * cursor plane briefly if not already running after enabling the display
3600 * This workaround avoids occasional blank screens when self refresh is
3604 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3606 u32 cntl = I915_READ(CURCNTR(pipe));
3608 if ((cntl & CURSOR_MODE) == 0) {
3609 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3611 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3612 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3613 intel_wait_for_vblank(dev_priv->dev, pipe);
3614 I915_WRITE(CURCNTR(pipe), cntl);
3615 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3616 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3620 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3622 struct drm_device *dev = crtc->base.dev;
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 struct intel_crtc_config *pipe_config = &crtc->config;
3626 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3627 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3630 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3631 assert_pipe_disabled(dev_priv, crtc->pipe);
3634 * Enable automatic panel scaling so that non-native modes
3635 * fill the screen. The panel fitter should only be
3636 * adjusted whilst the pipe is disabled, according to
3637 * register description and PRM.
3639 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3640 pipe_config->gmch_pfit.control,
3641 pipe_config->gmch_pfit.pgm_ratios);
3643 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3644 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3646 /* Border color in case we don't scale up to the full screen. Black by
3647 * default, change to something else for debugging. */
3648 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3651 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 struct intel_encoder *encoder;
3657 int pipe = intel_crtc->pipe;
3658 int plane = intel_crtc->plane;
3660 WARN_ON(!crtc->enabled);
3662 if (intel_crtc->active)
3665 intel_crtc->active = true;
3666 intel_update_watermarks(dev);
3668 mutex_lock(&dev_priv->dpio_lock);
3670 for_each_encoder_on_crtc(dev, crtc, encoder)
3671 if (encoder->pre_pll_enable)
3672 encoder->pre_pll_enable(encoder);
3674 intel_enable_pll(dev_priv, pipe);
3676 for_each_encoder_on_crtc(dev, crtc, encoder)
3677 if (encoder->pre_enable)
3678 encoder->pre_enable(encoder);
3680 /* VLV wants encoder enabling _before_ the pipe is up. */
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 encoder->enable(encoder);
3684 /* Enable panel fitting for eDP */
3685 i9xx_pfit_enable(intel_crtc);
3687 intel_enable_pipe(dev_priv, pipe, false);
3688 intel_enable_plane(dev_priv, plane, pipe);
3690 intel_crtc_load_lut(crtc);
3691 intel_update_fbc(dev);
3693 /* Give the overlay scaler a chance to enable if it's on this pipe */
3694 intel_crtc_dpms_overlay(intel_crtc, true);
3695 intel_crtc_update_cursor(crtc, true);
3697 mutex_unlock(&dev_priv->dpio_lock);
3700 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3702 struct drm_device *dev = crtc->dev;
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705 struct intel_encoder *encoder;
3706 int pipe = intel_crtc->pipe;
3707 int plane = intel_crtc->plane;
3709 WARN_ON(!crtc->enabled);
3711 if (intel_crtc->active)
3714 intel_crtc->active = true;
3715 intel_update_watermarks(dev);
3717 intel_enable_pll(dev_priv, pipe);
3719 for_each_encoder_on_crtc(dev, crtc, encoder)
3720 if (encoder->pre_enable)
3721 encoder->pre_enable(encoder);
3723 /* Enable panel fitting for LVDS */
3724 i9xx_pfit_enable(intel_crtc);
3726 intel_enable_pipe(dev_priv, pipe, false);
3727 intel_enable_plane(dev_priv, plane, pipe);
3729 g4x_fixup_plane(dev_priv, pipe);
3731 intel_crtc_load_lut(crtc);
3732 intel_update_fbc(dev);
3734 /* Give the overlay scaler a chance to enable if it's on this pipe */
3735 intel_crtc_dpms_overlay(intel_crtc, true);
3736 intel_crtc_update_cursor(crtc, true);
3738 for_each_encoder_on_crtc(dev, crtc, encoder)
3739 encoder->enable(encoder);
3742 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3744 struct drm_device *dev = crtc->base.dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3747 uint32_t pctl = I915_READ(PFIT_CONTROL);
3749 assert_pipe_disabled(dev_priv, crtc->pipe);
3751 if (INTEL_INFO(dev)->gen >= 4)
3752 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3756 if (pipe == crtc->pipe) {
3757 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3758 I915_WRITE(PFIT_CONTROL, 0);
3762 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3764 struct drm_device *dev = crtc->dev;
3765 struct drm_i915_private *dev_priv = dev->dev_private;
3766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767 struct intel_encoder *encoder;
3768 int pipe = intel_crtc->pipe;
3769 int plane = intel_crtc->plane;
3771 if (!intel_crtc->active)
3774 for_each_encoder_on_crtc(dev, crtc, encoder)
3775 encoder->disable(encoder);
3777 /* Give the overlay scaler a chance to disable if it's on this pipe */
3778 intel_crtc_wait_for_pending_flips(crtc);
3779 drm_vblank_off(dev, pipe);
3780 intel_crtc_dpms_overlay(intel_crtc, false);
3781 intel_crtc_update_cursor(crtc, false);
3783 if (dev_priv->cfb_plane == plane)
3784 intel_disable_fbc(dev);
3786 intel_disable_plane(dev_priv, plane, pipe);
3787 intel_disable_pipe(dev_priv, pipe);
3789 i9xx_pfit_disable(intel_crtc);
3791 for_each_encoder_on_crtc(dev, crtc, encoder)
3792 if (encoder->post_disable)
3793 encoder->post_disable(encoder);
3795 intel_disable_pll(dev_priv, pipe);
3797 intel_crtc->active = false;
3798 intel_update_fbc(dev);
3799 intel_update_watermarks(dev);
3802 static void i9xx_crtc_off(struct drm_crtc *crtc)
3806 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3809 struct drm_device *dev = crtc->dev;
3810 struct drm_i915_master_private *master_priv;
3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3812 int pipe = intel_crtc->pipe;
3814 if (!dev->primary->master)
3817 master_priv = dev->primary->master->driver_priv;
3818 if (!master_priv->sarea_priv)
3823 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3824 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3827 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3828 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3831 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3837 * Sets the power management mode of the pipe and plane.
3839 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3841 struct drm_device *dev = crtc->dev;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843 struct intel_encoder *intel_encoder;
3844 bool enable = false;
3846 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3847 enable |= intel_encoder->connectors_active;
3850 dev_priv->display.crtc_enable(crtc);
3852 dev_priv->display.crtc_disable(crtc);
3854 intel_crtc_update_sarea(crtc, enable);
3857 static void intel_crtc_disable(struct drm_crtc *crtc)
3859 struct drm_device *dev = crtc->dev;
3860 struct drm_connector *connector;
3861 struct drm_i915_private *dev_priv = dev->dev_private;
3862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3864 /* crtc should still be enabled when we disable it. */
3865 WARN_ON(!crtc->enabled);
3867 dev_priv->display.crtc_disable(crtc);
3868 intel_crtc->eld_vld = false;
3869 intel_crtc_update_sarea(crtc, false);
3870 dev_priv->display.off(crtc);
3872 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3873 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3876 mutex_lock(&dev->struct_mutex);
3877 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3878 mutex_unlock(&dev->struct_mutex);
3882 /* Update computed state. */
3883 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3884 if (!connector->encoder || !connector->encoder->crtc)
3887 if (connector->encoder->crtc != crtc)
3890 connector->dpms = DRM_MODE_DPMS_OFF;
3891 to_intel_encoder(connector->encoder)->connectors_active = false;
3895 void intel_modeset_disable(struct drm_device *dev)
3897 struct drm_crtc *crtc;
3899 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3901 intel_crtc_disable(crtc);
3905 void intel_encoder_destroy(struct drm_encoder *encoder)
3907 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3909 drm_encoder_cleanup(encoder);
3910 kfree(intel_encoder);
3913 /* Simple dpms helper for encodres with just one connector, no cloning and only
3914 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3915 * state of the entire output pipe. */
3916 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3918 if (mode == DRM_MODE_DPMS_ON) {
3919 encoder->connectors_active = true;
3921 intel_crtc_update_dpms(encoder->base.crtc);
3923 encoder->connectors_active = false;
3925 intel_crtc_update_dpms(encoder->base.crtc);
3929 /* Cross check the actual hw state with our own modeset state tracking (and it's
3930 * internal consistency). */
3931 static void intel_connector_check_state(struct intel_connector *connector)
3933 if (connector->get_hw_state(connector)) {
3934 struct intel_encoder *encoder = connector->encoder;
3935 struct drm_crtc *crtc;
3936 bool encoder_enabled;
3939 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3940 connector->base.base.id,
3941 drm_get_connector_name(&connector->base));
3943 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3944 "wrong connector dpms state\n");
3945 WARN(connector->base.encoder != &encoder->base,
3946 "active connector not linked to encoder\n");
3947 WARN(!encoder->connectors_active,
3948 "encoder->connectors_active not set\n");
3950 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3951 WARN(!encoder_enabled, "encoder not enabled\n");
3952 if (WARN_ON(!encoder->base.crtc))
3955 crtc = encoder->base.crtc;
3957 WARN(!crtc->enabled, "crtc not enabled\n");
3958 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3959 WARN(pipe != to_intel_crtc(crtc)->pipe,
3960 "encoder active on the wrong pipe\n");
3964 /* Even simpler default implementation, if there's really no special case to
3966 void intel_connector_dpms(struct drm_connector *connector, int mode)
3968 struct intel_encoder *encoder = intel_attached_encoder(connector);
3970 /* All the simple cases only support two dpms states. */
3971 if (mode != DRM_MODE_DPMS_ON)
3972 mode = DRM_MODE_DPMS_OFF;
3974 if (mode == connector->dpms)
3977 connector->dpms = mode;
3979 /* Only need to change hw state when actually enabled */
3980 if (encoder->base.crtc)
3981 intel_encoder_dpms(encoder, mode);
3983 WARN_ON(encoder->connectors_active != false);
3985 intel_modeset_check_state(connector->dev);
3988 /* Simple connector->get_hw_state implementation for encoders that support only
3989 * one connector and no cloning and hence the encoder state determines the state
3990 * of the connector. */
3991 bool intel_connector_get_hw_state(struct intel_connector *connector)
3994 struct intel_encoder *encoder = connector->encoder;
3996 return encoder->get_hw_state(encoder, &pipe);
3999 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4000 struct intel_crtc_config *pipe_config)
4002 struct drm_i915_private *dev_priv = dev->dev_private;
4003 struct intel_crtc *pipe_B_crtc =
4004 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4006 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4007 pipe_name(pipe), pipe_config->fdi_lanes);
4008 if (pipe_config->fdi_lanes > 4) {
4009 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4010 pipe_name(pipe), pipe_config->fdi_lanes);
4014 if (IS_HASWELL(dev)) {
4015 if (pipe_config->fdi_lanes > 2) {
4016 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4017 pipe_config->fdi_lanes);
4024 if (INTEL_INFO(dev)->num_pipes == 2)
4027 /* Ivybridge 3 pipe is really complicated */
4032 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4033 pipe_config->fdi_lanes > 2) {
4034 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4035 pipe_name(pipe), pipe_config->fdi_lanes);
4040 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4041 pipe_B_crtc->config.fdi_lanes <= 2) {
4042 if (pipe_config->fdi_lanes > 2) {
4043 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4044 pipe_name(pipe), pipe_config->fdi_lanes);
4048 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4058 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4059 struct intel_crtc_config *pipe_config)
4061 struct drm_device *dev = intel_crtc->base.dev;
4062 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4063 int target_clock, lane, link_bw;
4064 bool setup_ok, needs_recompute = false;
4067 /* FDI is a binary signal running at ~2.7GHz, encoding
4068 * each output octet as 10 bits. The actual frequency
4069 * is stored as a divider into a 100MHz clock, and the
4070 * mode pixel clock is stored in units of 1KHz.
4071 * Hence the bw of each lane in terms of the mode signal
4074 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4076 if (pipe_config->pixel_target_clock)
4077 target_clock = pipe_config->pixel_target_clock;
4079 target_clock = adjusted_mode->clock;
4081 lane = ironlake_get_lanes_required(target_clock, link_bw,
4082 pipe_config->pipe_bpp);
4084 pipe_config->fdi_lanes = lane;
4086 if (pipe_config->pixel_multiplier > 1)
4087 link_bw *= pipe_config->pixel_multiplier;
4088 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4089 link_bw, &pipe_config->fdi_m_n);
4091 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4092 intel_crtc->pipe, pipe_config);
4093 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4094 pipe_config->pipe_bpp -= 2*3;
4095 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4096 pipe_config->pipe_bpp);
4097 needs_recompute = true;
4098 pipe_config->bw_constrained = true;
4103 if (needs_recompute)
4106 return setup_ok ? 0 : -EINVAL;
4109 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4110 struct intel_crtc_config *pipe_config)
4112 struct drm_device *dev = crtc->dev;
4113 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4115 if (HAS_PCH_SPLIT(dev)) {
4116 /* FDI link clock is fixed at 2.7G */
4117 if (pipe_config->requested_mode.clock * 3
4118 > IRONLAKE_FDI_FREQ * 4)
4122 /* All interlaced capable intel hw wants timings in frames. Note though
4123 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4124 * timings, so we need to be careful not to clobber these.*/
4125 if (!pipe_config->timings_set)
4126 drm_mode_set_crtcinfo(adjusted_mode, 0);
4128 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4129 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4131 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4132 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4135 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4136 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4137 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4138 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4140 pipe_config->pipe_bpp = 8*3;
4143 if (pipe_config->has_pch_encoder)
4144 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4149 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4151 return 400000; /* FIXME */
4154 static int i945_get_display_clock_speed(struct drm_device *dev)
4159 static int i915_get_display_clock_speed(struct drm_device *dev)
4164 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4169 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4173 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4175 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4178 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4179 case GC_DISPLAY_CLOCK_333_MHZ:
4182 case GC_DISPLAY_CLOCK_190_200_MHZ:
4188 static int i865_get_display_clock_speed(struct drm_device *dev)
4193 static int i855_get_display_clock_speed(struct drm_device *dev)
4196 /* Assume that the hardware is in the high speed state. This
4197 * should be the default.
4199 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4200 case GC_CLOCK_133_200:
4201 case GC_CLOCK_100_200:
4203 case GC_CLOCK_166_250:
4205 case GC_CLOCK_100_133:
4209 /* Shouldn't happen */
4213 static int i830_get_display_clock_speed(struct drm_device *dev)
4219 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4221 while (*num > 0xffffff || *den > 0xffffff) {
4228 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4229 int pixel_clock, int link_clock,
4230 struct intel_link_m_n *m_n)
4233 m_n->gmch_m = bits_per_pixel * pixel_clock;
4234 m_n->gmch_n = link_clock * nlanes * 8;
4235 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4236 m_n->link_m = pixel_clock;
4237 m_n->link_n = link_clock;
4238 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4241 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4243 if (i915_panel_use_ssc >= 0)
4244 return i915_panel_use_ssc != 0;
4245 return dev_priv->lvds_use_ssc
4246 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4249 static int vlv_get_refclk(struct drm_crtc *crtc)
4251 struct drm_device *dev = crtc->dev;
4252 struct drm_i915_private *dev_priv = dev->dev_private;
4253 int refclk = 27000; /* for DP & HDMI */
4255 return 100000; /* only one validated so far */
4257 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4259 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4260 if (intel_panel_use_ssc(dev_priv))
4264 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4271 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4273 struct drm_device *dev = crtc->dev;
4274 struct drm_i915_private *dev_priv = dev->dev_private;
4277 if (IS_VALLEYVIEW(dev)) {
4278 refclk = vlv_get_refclk(crtc);
4279 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4280 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4281 refclk = dev_priv->lvds_ssc_freq * 1000;
4282 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4284 } else if (!IS_GEN2(dev)) {
4293 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4295 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4298 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4300 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4303 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4304 intel_clock_t *reduced_clock)
4306 struct drm_device *dev = crtc->base.dev;
4307 struct drm_i915_private *dev_priv = dev->dev_private;
4308 int pipe = crtc->pipe;
4311 if (IS_PINEVIEW(dev)) {
4312 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4314 fp2 = pnv_dpll_compute_fp(reduced_clock);
4316 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4318 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4321 I915_WRITE(FP0(pipe), fp);
4323 crtc->lowfreq_avail = false;
4324 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4325 reduced_clock && i915_powersave) {
4326 I915_WRITE(FP1(pipe), fp2);
4327 crtc->lowfreq_avail = true;
4329 I915_WRITE(FP1(pipe), fp);
4333 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4338 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4339 * and set it to a reasonable value instead.
4341 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4342 reg_val &= 0xffffff00;
4343 reg_val |= 0x00000030;
4344 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4346 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4347 reg_val &= 0x8cffffff;
4348 reg_val = 0x8c000000;
4349 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4351 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4352 reg_val &= 0xffffff00;
4353 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4355 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4356 reg_val &= 0x00ffffff;
4357 reg_val |= 0xb0000000;
4358 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4361 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4362 struct intel_link_m_n *m_n)
4364 struct drm_device *dev = crtc->base.dev;
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 int pipe = crtc->pipe;
4368 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4369 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4370 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4371 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4374 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4375 struct intel_link_m_n *m_n)
4377 struct drm_device *dev = crtc->base.dev;
4378 struct drm_i915_private *dev_priv = dev->dev_private;
4379 int pipe = crtc->pipe;
4380 enum transcoder transcoder = crtc->config.cpu_transcoder;
4382 if (INTEL_INFO(dev)->gen >= 5) {
4383 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4384 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4385 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4386 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4388 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4389 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4390 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4391 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4395 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4397 if (crtc->config.has_pch_encoder)
4398 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4400 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4403 static void vlv_update_pll(struct intel_crtc *crtc)
4405 struct drm_device *dev = crtc->base.dev;
4406 struct drm_i915_private *dev_priv = dev->dev_private;
4407 struct drm_display_mode *adjusted_mode =
4408 &crtc->config.adjusted_mode;
4409 struct intel_encoder *encoder;
4410 int pipe = crtc->pipe;
4412 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4414 u32 coreclk, reg_val, dpll_md;
4416 mutex_lock(&dev_priv->dpio_lock);
4418 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4420 bestn = crtc->config.dpll.n;
4421 bestm1 = crtc->config.dpll.m1;
4422 bestm2 = crtc->config.dpll.m2;
4423 bestp1 = crtc->config.dpll.p1;
4424 bestp2 = crtc->config.dpll.p2;
4426 /* See eDP HDMI DPIO driver vbios notes doc */
4428 /* PLL B needs special handling */
4430 vlv_pllb_recal_opamp(dev_priv);
4432 /* Set up Tx target for periodic Rcomp update */
4433 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4435 /* Disable target IRef on PLL */
4436 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4437 reg_val &= 0x00ffffff;
4438 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4440 /* Disable fast lock */
4441 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4443 /* Set idtafcrecal before PLL is enabled */
4444 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4445 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4446 mdiv |= ((bestn << DPIO_N_SHIFT));
4447 mdiv |= (1 << DPIO_K_SHIFT);
4450 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4451 * but we don't support that).
4452 * Note: don't use the DAC post divider as it seems unstable.
4454 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4455 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4457 mdiv |= DPIO_ENABLE_CALIBRATION;
4458 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4460 /* Set HBR and RBR LPF coefficients */
4461 if (adjusted_mode->clock == 162000 ||
4462 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4463 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4466 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4469 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4470 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4471 /* Use SSC source */
4473 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4476 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4478 } else { /* HDMI or VGA */
4479 /* Use bend source */
4481 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4484 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4488 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4489 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4490 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4491 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4492 coreclk |= 0x01000000;
4493 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4495 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4497 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4498 if (encoder->pre_pll_enable)
4499 encoder->pre_pll_enable(encoder);
4501 /* Enable DPIO clock input */
4502 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4503 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4505 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4507 dpll |= DPLL_VCO_ENABLE;
4508 I915_WRITE(DPLL(pipe), dpll);
4509 POSTING_READ(DPLL(pipe));
4512 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4513 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4516 if (crtc->config.pixel_multiplier > 1) {
4517 dpll_md = (crtc->config.pixel_multiplier - 1)
4518 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4520 I915_WRITE(DPLL_MD(pipe), dpll_md);
4521 POSTING_READ(DPLL_MD(pipe));
4523 if (crtc->config.has_dp_encoder)
4524 intel_dp_set_m_n(crtc);
4526 mutex_unlock(&dev_priv->dpio_lock);
4529 static void i9xx_update_pll(struct intel_crtc *crtc,
4530 intel_clock_t *reduced_clock,
4533 struct drm_device *dev = crtc->base.dev;
4534 struct drm_i915_private *dev_priv = dev->dev_private;
4535 struct intel_encoder *encoder;
4536 int pipe = crtc->pipe;
4539 struct dpll *clock = &crtc->config.dpll;
4541 i9xx_update_pll_dividers(crtc, reduced_clock);
4543 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4544 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4546 dpll = DPLL_VGA_MODE_DIS;
4548 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4549 dpll |= DPLLB_MODE_LVDS;
4551 dpll |= DPLLB_MODE_DAC_SERIAL;
4553 if ((crtc->config.pixel_multiplier > 1) &&
4554 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4555 dpll |= (crtc->config.pixel_multiplier - 1)
4556 << SDVO_MULTIPLIER_SHIFT_HIRES;
4560 dpll |= DPLL_DVO_HIGH_SPEED;
4562 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4563 dpll |= DPLL_DVO_HIGH_SPEED;
4565 /* compute bitmask from p1 value */
4566 if (IS_PINEVIEW(dev))
4567 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4569 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4570 if (IS_G4X(dev) && reduced_clock)
4571 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4573 switch (clock->p2) {
4575 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4578 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4581 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4584 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4587 if (INTEL_INFO(dev)->gen >= 4)
4588 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4590 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4591 dpll |= PLL_REF_INPUT_TVCLKINBC;
4592 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4593 /* XXX: just matching BIOS for now */
4594 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4596 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4597 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4598 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4600 dpll |= PLL_REF_INPUT_DREFCLK;
4602 dpll |= DPLL_VCO_ENABLE;
4603 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4604 POSTING_READ(DPLL(pipe));
4607 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4608 if (encoder->pre_pll_enable)
4609 encoder->pre_pll_enable(encoder);
4611 if (crtc->config.has_dp_encoder)
4612 intel_dp_set_m_n(crtc);
4614 I915_WRITE(DPLL(pipe), dpll);
4616 /* Wait for the clocks to stabilize. */
4617 POSTING_READ(DPLL(pipe));
4620 if (INTEL_INFO(dev)->gen >= 4) {
4622 if (crtc->config.pixel_multiplier > 1) {
4623 dpll_md = (crtc->config.pixel_multiplier - 1)
4624 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4626 I915_WRITE(DPLL_MD(pipe), dpll_md);
4628 /* The pixel multiplier can only be updated once the
4629 * DPLL is enabled and the clocks are stable.
4631 * So write it again.
4633 I915_WRITE(DPLL(pipe), dpll);
4637 static void i8xx_update_pll(struct intel_crtc *crtc,
4638 struct drm_display_mode *adjusted_mode,
4639 intel_clock_t *reduced_clock,
4642 struct drm_device *dev = crtc->base.dev;
4643 struct drm_i915_private *dev_priv = dev->dev_private;
4644 struct intel_encoder *encoder;
4645 int pipe = crtc->pipe;
4647 struct dpll *clock = &crtc->config.dpll;
4649 i9xx_update_pll_dividers(crtc, reduced_clock);
4651 dpll = DPLL_VGA_MODE_DIS;
4653 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4654 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4657 dpll |= PLL_P1_DIVIDE_BY_TWO;
4659 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4661 dpll |= PLL_P2_DIVIDE_BY_4;
4664 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4665 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4666 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4668 dpll |= PLL_REF_INPUT_DREFCLK;
4670 dpll |= DPLL_VCO_ENABLE;
4671 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4672 POSTING_READ(DPLL(pipe));
4675 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4676 if (encoder->pre_pll_enable)
4677 encoder->pre_pll_enable(encoder);
4679 I915_WRITE(DPLL(pipe), dpll);
4681 /* Wait for the clocks to stabilize. */
4682 POSTING_READ(DPLL(pipe));
4685 /* The pixel multiplier can only be updated once the
4686 * DPLL is enabled and the clocks are stable.
4688 * So write it again.
4690 I915_WRITE(DPLL(pipe), dpll);
4693 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4694 struct drm_display_mode *mode,
4695 struct drm_display_mode *adjusted_mode)
4697 struct drm_device *dev = intel_crtc->base.dev;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 enum pipe pipe = intel_crtc->pipe;
4700 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4701 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4703 /* We need to be careful not to changed the adjusted mode, for otherwise
4704 * the hw state checker will get angry at the mismatch. */
4705 crtc_vtotal = adjusted_mode->crtc_vtotal;
4706 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4708 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4709 /* the chip adds 2 halflines automatically */
4711 crtc_vblank_end -= 1;
4712 vsyncshift = adjusted_mode->crtc_hsync_start
4713 - adjusted_mode->crtc_htotal / 2;
4718 if (INTEL_INFO(dev)->gen > 3)
4719 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4721 I915_WRITE(HTOTAL(cpu_transcoder),
4722 (adjusted_mode->crtc_hdisplay - 1) |
4723 ((adjusted_mode->crtc_htotal - 1) << 16));
4724 I915_WRITE(HBLANK(cpu_transcoder),
4725 (adjusted_mode->crtc_hblank_start - 1) |
4726 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4727 I915_WRITE(HSYNC(cpu_transcoder),
4728 (adjusted_mode->crtc_hsync_start - 1) |
4729 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4731 I915_WRITE(VTOTAL(cpu_transcoder),
4732 (adjusted_mode->crtc_vdisplay - 1) |
4733 ((crtc_vtotal - 1) << 16));
4734 I915_WRITE(VBLANK(cpu_transcoder),
4735 (adjusted_mode->crtc_vblank_start - 1) |
4736 ((crtc_vblank_end - 1) << 16));
4737 I915_WRITE(VSYNC(cpu_transcoder),
4738 (adjusted_mode->crtc_vsync_start - 1) |
4739 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4741 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4742 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4743 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4745 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4746 (pipe == PIPE_B || pipe == PIPE_C))
4747 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4749 /* pipesrc controls the size that is scaled from, which should
4750 * always be the user's requested size.
4752 I915_WRITE(PIPESRC(pipe),
4753 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4756 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4757 struct intel_crtc_config *pipe_config)
4759 struct drm_device *dev = crtc->base.dev;
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4764 tmp = I915_READ(HTOTAL(cpu_transcoder));
4765 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4766 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4767 tmp = I915_READ(HBLANK(cpu_transcoder));
4768 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4769 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4770 tmp = I915_READ(HSYNC(cpu_transcoder));
4771 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4772 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4774 tmp = I915_READ(VTOTAL(cpu_transcoder));
4775 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4776 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4777 tmp = I915_READ(VBLANK(cpu_transcoder));
4778 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4779 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4780 tmp = I915_READ(VSYNC(cpu_transcoder));
4781 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4782 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4784 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4785 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4786 pipe_config->adjusted_mode.crtc_vtotal += 1;
4787 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4790 tmp = I915_READ(PIPESRC(crtc->pipe));
4791 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4792 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4795 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4797 struct drm_device *dev = intel_crtc->base.dev;
4798 struct drm_i915_private *dev_priv = dev->dev_private;
4801 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4803 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4804 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4807 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4810 if (intel_crtc->config.requested_mode.clock >
4811 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4812 pipeconf |= PIPECONF_DOUBLE_WIDE;
4814 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4817 /* only g4x and later have fancy bpc/dither controls */
4818 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4819 pipeconf &= ~(PIPECONF_BPC_MASK |
4820 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4822 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4823 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4824 pipeconf |= PIPECONF_DITHER_EN |
4825 PIPECONF_DITHER_TYPE_SP;
4827 switch (intel_crtc->config.pipe_bpp) {
4829 pipeconf |= PIPECONF_6BPC;
4832 pipeconf |= PIPECONF_8BPC;
4835 pipeconf |= PIPECONF_10BPC;
4838 /* Case prevented by intel_choose_pipe_bpp_dither. */
4843 if (HAS_PIPE_CXSR(dev)) {
4844 if (intel_crtc->lowfreq_avail) {
4845 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4846 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4848 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4849 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4853 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4854 if (!IS_GEN2(dev) &&
4855 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4856 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4858 pipeconf |= PIPECONF_PROGRESSIVE;
4860 if (IS_VALLEYVIEW(dev)) {
4861 if (intel_crtc->config.limited_color_range)
4862 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4864 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4867 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4868 POSTING_READ(PIPECONF(intel_crtc->pipe));
4871 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4873 struct drm_framebuffer *fb)
4875 struct drm_device *dev = crtc->dev;
4876 struct drm_i915_private *dev_priv = dev->dev_private;
4877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4878 struct drm_display_mode *adjusted_mode =
4879 &intel_crtc->config.adjusted_mode;
4880 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4881 int pipe = intel_crtc->pipe;
4882 int plane = intel_crtc->plane;
4883 int refclk, num_connectors = 0;
4884 intel_clock_t clock, reduced_clock;
4886 bool ok, has_reduced_clock = false, is_sdvo = false;
4887 bool is_lvds = false, is_tv = false;
4888 struct intel_encoder *encoder;
4889 const intel_limit_t *limit;
4892 for_each_encoder_on_crtc(dev, crtc, encoder) {
4893 switch (encoder->type) {
4894 case INTEL_OUTPUT_LVDS:
4897 case INTEL_OUTPUT_SDVO:
4898 case INTEL_OUTPUT_HDMI:
4900 if (encoder->needs_tv_clock)
4903 case INTEL_OUTPUT_TVOUT:
4911 refclk = i9xx_get_refclk(crtc, num_connectors);
4914 * Returns a set of divisors for the desired target clock with the given
4915 * refclk, or FALSE. The returned values represent the clock equation:
4916 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4918 limit = intel_limit(crtc, refclk);
4919 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4922 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4926 /* Ensure that the cursor is valid for the new mode before changing... */
4927 intel_crtc_update_cursor(crtc, true);
4929 if (is_lvds && dev_priv->lvds_downclock_avail) {
4931 * Ensure we match the reduced clock's P to the target clock.
4932 * If the clocks don't match, we can't switch the display clock
4933 * by using the FP0/FP1. In such case we will disable the LVDS
4934 * downclock feature.
4936 has_reduced_clock = limit->find_pll(limit, crtc,
4937 dev_priv->lvds_downclock,
4942 /* Compat-code for transition, will disappear. */
4943 if (!intel_crtc->config.clock_set) {
4944 intel_crtc->config.dpll.n = clock.n;
4945 intel_crtc->config.dpll.m1 = clock.m1;
4946 intel_crtc->config.dpll.m2 = clock.m2;
4947 intel_crtc->config.dpll.p1 = clock.p1;
4948 intel_crtc->config.dpll.p2 = clock.p2;
4952 i8xx_update_pll(intel_crtc, adjusted_mode,
4953 has_reduced_clock ? &reduced_clock : NULL,
4955 else if (IS_VALLEYVIEW(dev))
4956 vlv_update_pll(intel_crtc);
4958 i9xx_update_pll(intel_crtc,
4959 has_reduced_clock ? &reduced_clock : NULL,
4962 /* Set up the display plane register */
4963 dspcntr = DISPPLANE_GAMMA_ENABLE;
4965 if (!IS_VALLEYVIEW(dev)) {
4967 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4969 dspcntr |= DISPPLANE_SEL_PIPE_B;
4972 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4973 drm_mode_debug_printmodeline(mode);
4975 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4977 /* pipesrc and dspsize control the size that is scaled from,
4978 * which should always be the user's requested size.
4980 I915_WRITE(DSPSIZE(plane),
4981 ((mode->vdisplay - 1) << 16) |
4982 (mode->hdisplay - 1));
4983 I915_WRITE(DSPPOS(plane), 0);
4985 i9xx_set_pipeconf(intel_crtc);
4987 I915_WRITE(DSPCNTR(plane), dspcntr);
4988 POSTING_READ(DSPCNTR(plane));
4990 ret = intel_pipe_set_base(crtc, x, y, fb);
4992 intel_update_watermarks(dev);
4997 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4998 struct intel_crtc_config *pipe_config)
5000 struct drm_device *dev = crtc->base.dev;
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5004 tmp = I915_READ(PIPECONF(crtc->pipe));
5005 if (!(tmp & PIPECONF_ENABLE))
5008 intel_get_pipe_timings(crtc, pipe_config);
5013 static void ironlake_init_pch_refclk(struct drm_device *dev)
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5016 struct drm_mode_config *mode_config = &dev->mode_config;
5017 struct intel_encoder *encoder;
5019 bool has_lvds = false;
5020 bool has_cpu_edp = false;
5021 bool has_panel = false;
5022 bool has_ck505 = false;
5023 bool can_ssc = false;
5025 /* We need to take the global config into account */
5026 list_for_each_entry(encoder, &mode_config->encoder_list,
5028 switch (encoder->type) {
5029 case INTEL_OUTPUT_LVDS:
5033 case INTEL_OUTPUT_EDP:
5035 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5041 if (HAS_PCH_IBX(dev)) {
5042 has_ck505 = dev_priv->display_clock_mode;
5043 can_ssc = has_ck505;
5049 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5050 has_panel, has_lvds, has_ck505);
5052 /* Ironlake: try to setup display ref clock before DPLL
5053 * enabling. This is only under driver's control after
5054 * PCH B stepping, previous chipset stepping should be
5055 * ignoring this setting.
5057 val = I915_READ(PCH_DREF_CONTROL);
5059 /* As we must carefully and slowly disable/enable each source in turn,
5060 * compute the final state we want first and check if we need to
5061 * make any changes at all.
5064 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5066 final |= DREF_NONSPREAD_CK505_ENABLE;
5068 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5070 final &= ~DREF_SSC_SOURCE_MASK;
5071 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5072 final &= ~DREF_SSC1_ENABLE;
5075 final |= DREF_SSC_SOURCE_ENABLE;
5077 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5078 final |= DREF_SSC1_ENABLE;
5081 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5082 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5084 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5086 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5088 final |= DREF_SSC_SOURCE_DISABLE;
5089 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5095 /* Always enable nonspread source */
5096 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5099 val |= DREF_NONSPREAD_CK505_ENABLE;
5101 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5104 val &= ~DREF_SSC_SOURCE_MASK;
5105 val |= DREF_SSC_SOURCE_ENABLE;
5107 /* SSC must be turned on before enabling the CPU output */
5108 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5109 DRM_DEBUG_KMS("Using SSC on panel\n");
5110 val |= DREF_SSC1_ENABLE;
5112 val &= ~DREF_SSC1_ENABLE;
5114 /* Get SSC going before enabling the outputs */
5115 I915_WRITE(PCH_DREF_CONTROL, val);
5116 POSTING_READ(PCH_DREF_CONTROL);
5119 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5121 /* Enable CPU source on CPU attached eDP */
5123 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5124 DRM_DEBUG_KMS("Using SSC on eDP\n");
5125 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5128 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5130 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5132 I915_WRITE(PCH_DREF_CONTROL, val);
5133 POSTING_READ(PCH_DREF_CONTROL);
5136 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5138 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5140 /* Turn off CPU output */
5141 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5143 I915_WRITE(PCH_DREF_CONTROL, val);
5144 POSTING_READ(PCH_DREF_CONTROL);
5147 /* Turn off the SSC source */
5148 val &= ~DREF_SSC_SOURCE_MASK;
5149 val |= DREF_SSC_SOURCE_DISABLE;
5152 val &= ~DREF_SSC1_ENABLE;
5154 I915_WRITE(PCH_DREF_CONTROL, val);
5155 POSTING_READ(PCH_DREF_CONTROL);
5159 BUG_ON(val != final);
5162 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5163 static void lpt_init_pch_refclk(struct drm_device *dev)
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 struct drm_mode_config *mode_config = &dev->mode_config;
5167 struct intel_encoder *encoder;
5168 bool has_vga = false;
5169 bool is_sdv = false;
5172 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5173 switch (encoder->type) {
5174 case INTEL_OUTPUT_ANALOG:
5183 mutex_lock(&dev_priv->dpio_lock);
5185 /* XXX: Rip out SDV support once Haswell ships for real. */
5186 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5189 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5190 tmp &= ~SBI_SSCCTL_DISABLE;
5191 tmp |= SBI_SSCCTL_PATHALT;
5192 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5196 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5197 tmp &= ~SBI_SSCCTL_PATHALT;
5198 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5201 tmp = I915_READ(SOUTH_CHICKEN2);
5202 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5203 I915_WRITE(SOUTH_CHICKEN2, tmp);
5205 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5206 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5207 DRM_ERROR("FDI mPHY reset assert timeout\n");
5209 tmp = I915_READ(SOUTH_CHICKEN2);
5210 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5211 I915_WRITE(SOUTH_CHICKEN2, tmp);
5213 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5214 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5216 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5219 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5220 tmp &= ~(0xFF << 24);
5221 tmp |= (0x12 << 24);
5222 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5225 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5227 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5230 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5232 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5234 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5236 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5239 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5240 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5241 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5243 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5244 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5245 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5247 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5249 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5251 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5253 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5256 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5257 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5258 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5260 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5261 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5262 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5265 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5268 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5270 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5273 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5276 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5279 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5281 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5284 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5286 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5287 tmp &= ~(0xFF << 16);
5288 tmp |= (0x1C << 16);
5289 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5291 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5292 tmp &= ~(0xFF << 16);
5293 tmp |= (0x1C << 16);
5294 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5297 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5299 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5301 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5303 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5305 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5306 tmp &= ~(0xF << 28);
5308 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5310 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5311 tmp &= ~(0xF << 28);
5313 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5316 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5317 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5318 tmp |= SBI_DBUFF0_ENABLE;
5319 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5321 mutex_unlock(&dev_priv->dpio_lock);
5325 * Initialize reference clocks when the driver loads
5327 void intel_init_pch_refclk(struct drm_device *dev)
5329 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5330 ironlake_init_pch_refclk(dev);
5331 else if (HAS_PCH_LPT(dev))
5332 lpt_init_pch_refclk(dev);
5335 static int ironlake_get_refclk(struct drm_crtc *crtc)
5337 struct drm_device *dev = crtc->dev;
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct intel_encoder *encoder;
5340 struct intel_encoder *edp_encoder = NULL;
5341 int num_connectors = 0;
5342 bool is_lvds = false;
5344 for_each_encoder_on_crtc(dev, crtc, encoder) {
5345 switch (encoder->type) {
5346 case INTEL_OUTPUT_LVDS:
5349 case INTEL_OUTPUT_EDP:
5350 edp_encoder = encoder;
5356 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5357 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5358 dev_priv->lvds_ssc_freq);
5359 return dev_priv->lvds_ssc_freq * 1000;
5365 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5367 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5369 int pipe = intel_crtc->pipe;
5372 val = I915_READ(PIPECONF(pipe));
5374 val &= ~PIPECONF_BPC_MASK;
5375 switch (intel_crtc->config.pipe_bpp) {
5377 val |= PIPECONF_6BPC;
5380 val |= PIPECONF_8BPC;
5383 val |= PIPECONF_10BPC;
5386 val |= PIPECONF_12BPC;
5389 /* Case prevented by intel_choose_pipe_bpp_dither. */
5393 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5394 if (intel_crtc->config.dither)
5395 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5397 val &= ~PIPECONF_INTERLACE_MASK;
5398 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5399 val |= PIPECONF_INTERLACED_ILK;
5401 val |= PIPECONF_PROGRESSIVE;
5403 if (intel_crtc->config.limited_color_range)
5404 val |= PIPECONF_COLOR_RANGE_SELECT;
5406 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5408 I915_WRITE(PIPECONF(pipe), val);
5409 POSTING_READ(PIPECONF(pipe));
5413 * Set up the pipe CSC unit.
5415 * Currently only full range RGB to limited range RGB conversion
5416 * is supported, but eventually this should handle various
5417 * RGB<->YCbCr scenarios as well.
5419 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5421 struct drm_device *dev = crtc->dev;
5422 struct drm_i915_private *dev_priv = dev->dev_private;
5423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5424 int pipe = intel_crtc->pipe;
5425 uint16_t coeff = 0x7800; /* 1.0 */
5428 * TODO: Check what kind of values actually come out of the pipe
5429 * with these coeff/postoff values and adjust to get the best
5430 * accuracy. Perhaps we even need to take the bpc value into
5434 if (intel_crtc->config.limited_color_range)
5435 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5438 * GY/GU and RY/RU should be the other way around according
5439 * to BSpec, but reality doesn't agree. Just set them up in
5440 * a way that results in the correct picture.
5442 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5443 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5445 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5446 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5448 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5449 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5451 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5452 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5453 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5455 if (INTEL_INFO(dev)->gen > 6) {
5456 uint16_t postoff = 0;
5458 if (intel_crtc->config.limited_color_range)
5459 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5461 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5462 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5463 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5465 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5467 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5469 if (intel_crtc->config.limited_color_range)
5470 mode |= CSC_BLACK_SCREEN_OFFSET;
5472 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5476 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5478 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5480 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5483 val = I915_READ(PIPECONF(cpu_transcoder));
5485 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5486 if (intel_crtc->config.dither)
5487 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5489 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5490 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5491 val |= PIPECONF_INTERLACED_ILK;
5493 val |= PIPECONF_PROGRESSIVE;
5495 I915_WRITE(PIPECONF(cpu_transcoder), val);
5496 POSTING_READ(PIPECONF(cpu_transcoder));
5499 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5500 struct drm_display_mode *adjusted_mode,
5501 intel_clock_t *clock,
5502 bool *has_reduced_clock,
5503 intel_clock_t *reduced_clock)
5505 struct drm_device *dev = crtc->dev;
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507 struct intel_encoder *intel_encoder;
5509 const intel_limit_t *limit;
5510 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5512 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5513 switch (intel_encoder->type) {
5514 case INTEL_OUTPUT_LVDS:
5517 case INTEL_OUTPUT_SDVO:
5518 case INTEL_OUTPUT_HDMI:
5520 if (intel_encoder->needs_tv_clock)
5523 case INTEL_OUTPUT_TVOUT:
5529 refclk = ironlake_get_refclk(crtc);
5532 * Returns a set of divisors for the desired target clock with the given
5533 * refclk, or FALSE. The returned values represent the clock equation:
5534 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5536 limit = intel_limit(crtc, refclk);
5537 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5542 if (is_lvds && dev_priv->lvds_downclock_avail) {
5544 * Ensure we match the reduced clock's P to the target clock.
5545 * If the clocks don't match, we can't switch the display clock
5546 * by using the FP0/FP1. In such case we will disable the LVDS
5547 * downclock feature.
5549 *has_reduced_clock = limit->find_pll(limit, crtc,
5550 dev_priv->lvds_downclock,
5559 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5561 struct drm_i915_private *dev_priv = dev->dev_private;
5564 temp = I915_READ(SOUTH_CHICKEN1);
5565 if (temp & FDI_BC_BIFURCATION_SELECT)
5568 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5569 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5571 temp |= FDI_BC_BIFURCATION_SELECT;
5572 DRM_DEBUG_KMS("enabling fdi C rx\n");
5573 I915_WRITE(SOUTH_CHICKEN1, temp);
5574 POSTING_READ(SOUTH_CHICKEN1);
5577 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5579 struct drm_device *dev = intel_crtc->base.dev;
5580 struct drm_i915_private *dev_priv = dev->dev_private;
5582 switch (intel_crtc->pipe) {
5586 if (intel_crtc->config.fdi_lanes > 2)
5587 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5589 cpt_enable_fdi_bc_bifurcation(dev);
5593 cpt_enable_fdi_bc_bifurcation(dev);
5601 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5604 * Account for spread spectrum to avoid
5605 * oversubscribing the link. Max center spread
5606 * is 2.5%; use 5% for safety's sake.
5608 u32 bps = target_clock * bpp * 21 / 20;
5609 return bps / (link_bw * 8) + 1;
5612 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5614 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5617 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5619 intel_clock_t *reduced_clock, u32 *fp2)
5621 struct drm_crtc *crtc = &intel_crtc->base;
5622 struct drm_device *dev = crtc->dev;
5623 struct drm_i915_private *dev_priv = dev->dev_private;
5624 struct intel_encoder *intel_encoder;
5626 int factor, num_connectors = 0;
5627 bool is_lvds = false, is_sdvo = false, is_tv = false;
5629 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5630 switch (intel_encoder->type) {
5631 case INTEL_OUTPUT_LVDS:
5634 case INTEL_OUTPUT_SDVO:
5635 case INTEL_OUTPUT_HDMI:
5637 if (intel_encoder->needs_tv_clock)
5640 case INTEL_OUTPUT_TVOUT:
5648 /* Enable autotuning of the PLL clock (if permissible) */
5651 if ((intel_panel_use_ssc(dev_priv) &&
5652 dev_priv->lvds_ssc_freq == 100) ||
5653 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5655 } else if (is_sdvo && is_tv)
5658 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5661 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5667 dpll |= DPLLB_MODE_LVDS;
5669 dpll |= DPLLB_MODE_DAC_SERIAL;
5671 if (intel_crtc->config.pixel_multiplier > 1) {
5672 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5673 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5677 dpll |= DPLL_DVO_HIGH_SPEED;
5678 if (intel_crtc->config.has_dp_encoder)
5679 dpll |= DPLL_DVO_HIGH_SPEED;
5681 /* compute bitmask from p1 value */
5682 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5684 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5686 switch (intel_crtc->config.dpll.p2) {
5688 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5691 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5694 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5697 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5701 if (is_sdvo && is_tv)
5702 dpll |= PLL_REF_INPUT_TVCLKINBC;
5704 /* XXX: just matching BIOS for now */
5705 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5707 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5708 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5710 dpll |= PLL_REF_INPUT_DREFCLK;
5715 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5717 struct drm_framebuffer *fb)
5719 struct drm_device *dev = crtc->dev;
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5722 struct drm_display_mode *adjusted_mode =
5723 &intel_crtc->config.adjusted_mode;
5724 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5725 int pipe = intel_crtc->pipe;
5726 int plane = intel_crtc->plane;
5727 int num_connectors = 0;
5728 intel_clock_t clock, reduced_clock;
5729 u32 dpll = 0, fp = 0, fp2 = 0;
5730 bool ok, has_reduced_clock = false;
5731 bool is_lvds = false;
5732 struct intel_encoder *encoder;
5735 for_each_encoder_on_crtc(dev, crtc, encoder) {
5736 switch (encoder->type) {
5737 case INTEL_OUTPUT_LVDS:
5745 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5746 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5748 intel_crtc->config.cpu_transcoder = pipe;
5750 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5751 &has_reduced_clock, &reduced_clock);
5753 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5756 /* Compat-code for transition, will disappear. */
5757 if (!intel_crtc->config.clock_set) {
5758 intel_crtc->config.dpll.n = clock.n;
5759 intel_crtc->config.dpll.m1 = clock.m1;
5760 intel_crtc->config.dpll.m2 = clock.m2;
5761 intel_crtc->config.dpll.p1 = clock.p1;
5762 intel_crtc->config.dpll.p2 = clock.p2;
5765 /* Ensure that the cursor is valid for the new mode before changing... */
5766 intel_crtc_update_cursor(crtc, true);
5768 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5769 drm_mode_debug_printmodeline(mode);
5771 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5772 if (intel_crtc->config.has_pch_encoder) {
5773 struct intel_pch_pll *pll;
5775 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5776 if (has_reduced_clock)
5777 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5779 dpll = ironlake_compute_dpll(intel_crtc,
5780 &fp, &reduced_clock,
5781 has_reduced_clock ? &fp2 : NULL);
5783 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5785 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5790 intel_put_pch_pll(intel_crtc);
5792 if (intel_crtc->config.has_dp_encoder)
5793 intel_dp_set_m_n(intel_crtc);
5795 for_each_encoder_on_crtc(dev, crtc, encoder)
5796 if (encoder->pre_pll_enable)
5797 encoder->pre_pll_enable(encoder);
5799 if (intel_crtc->pch_pll) {
5800 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5802 /* Wait for the clocks to stabilize. */
5803 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5806 /* The pixel multiplier can only be updated once the
5807 * DPLL is enabled and the clocks are stable.
5809 * So write it again.
5811 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5814 intel_crtc->lowfreq_avail = false;
5815 if (intel_crtc->pch_pll) {
5816 if (is_lvds && has_reduced_clock && i915_powersave) {
5817 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5818 intel_crtc->lowfreq_avail = true;
5820 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5824 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5826 if (intel_crtc->config.has_pch_encoder) {
5827 intel_cpu_transcoder_set_m_n(intel_crtc,
5828 &intel_crtc->config.fdi_m_n);
5831 if (IS_IVYBRIDGE(dev))
5832 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5834 ironlake_set_pipeconf(crtc);
5836 /* Set up the display plane register */
5837 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5838 POSTING_READ(DSPCNTR(plane));
5840 ret = intel_pipe_set_base(crtc, x, y, fb);
5842 intel_update_watermarks(dev);
5844 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5849 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5850 struct intel_crtc_config *pipe_config)
5852 struct drm_device *dev = crtc->base.dev;
5853 struct drm_i915_private *dev_priv = dev->dev_private;
5854 enum transcoder transcoder = pipe_config->cpu_transcoder;
5856 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5857 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5858 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5860 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5861 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5862 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5865 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5866 struct intel_crtc_config *pipe_config)
5868 struct drm_device *dev = crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5872 tmp = I915_READ(PIPECONF(crtc->pipe));
5873 if (!(tmp & PIPECONF_ENABLE))
5876 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5877 pipe_config->has_pch_encoder = true;
5879 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5880 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5881 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5883 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5886 intel_get_pipe_timings(crtc, pipe_config);
5891 static void haswell_modeset_global_resources(struct drm_device *dev)
5893 bool enable = false;
5894 struct intel_crtc *crtc;
5895 struct intel_encoder *encoder;
5897 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5898 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5900 /* XXX: Should check for edp transcoder here, but thanks to init
5901 * sequence that's not yet available. Just in case desktop eDP
5902 * on PORT D is possible on haswell, too. */
5903 /* Even the eDP panel fitter is outside the always-on well. */
5904 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5908 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5910 if (encoder->type != INTEL_OUTPUT_EDP &&
5911 encoder->connectors_active)
5915 intel_set_power_well(dev, enable);
5918 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5920 struct drm_framebuffer *fb)
5922 struct drm_device *dev = crtc->dev;
5923 struct drm_i915_private *dev_priv = dev->dev_private;
5924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5925 struct drm_display_mode *adjusted_mode =
5926 &intel_crtc->config.adjusted_mode;
5927 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5928 int pipe = intel_crtc->pipe;
5929 int plane = intel_crtc->plane;
5930 int num_connectors = 0;
5931 bool is_cpu_edp = false;
5932 struct intel_encoder *encoder;
5935 for_each_encoder_on_crtc(dev, crtc, encoder) {
5936 switch (encoder->type) {
5937 case INTEL_OUTPUT_EDP:
5938 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5947 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5949 intel_crtc->config.cpu_transcoder = pipe;
5951 /* We are not sure yet this won't happen. */
5952 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5953 INTEL_PCH_TYPE(dev));
5955 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5956 num_connectors, pipe_name(pipe));
5958 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5959 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5961 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5963 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5966 /* Ensure that the cursor is valid for the new mode before changing... */
5967 intel_crtc_update_cursor(crtc, true);
5969 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5970 drm_mode_debug_printmodeline(mode);
5972 if (intel_crtc->config.has_dp_encoder)
5973 intel_dp_set_m_n(intel_crtc);
5975 intel_crtc->lowfreq_avail = false;
5977 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5979 if (intel_crtc->config.has_pch_encoder) {
5980 intel_cpu_transcoder_set_m_n(intel_crtc,
5981 &intel_crtc->config.fdi_m_n);
5984 haswell_set_pipeconf(crtc);
5986 intel_set_pipe_csc(crtc);
5988 /* Set up the display plane register */
5989 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5990 POSTING_READ(DSPCNTR(plane));
5992 ret = intel_pipe_set_base(crtc, x, y, fb);
5994 intel_update_watermarks(dev);
5996 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6001 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6002 struct intel_crtc_config *pipe_config)
6004 struct drm_device *dev = crtc->base.dev;
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6006 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
6009 if (!intel_display_power_enabled(dev,
6010 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6013 tmp = I915_READ(PIPECONF(cpu_transcoder));
6014 if (!(tmp & PIPECONF_ENABLE))
6018 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6019 * DDI E. So just check whether this pipe is wired to DDI E and whether
6020 * the PCH transcoder is on.
6022 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6023 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6024 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6025 pipe_config->has_pch_encoder = true;
6027 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6028 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6029 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6031 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6034 intel_get_pipe_timings(crtc, pipe_config);
6039 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6041 struct drm_framebuffer *fb)
6043 struct drm_device *dev = crtc->dev;
6044 struct drm_i915_private *dev_priv = dev->dev_private;
6045 struct drm_encoder_helper_funcs *encoder_funcs;
6046 struct intel_encoder *encoder;
6047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6048 struct drm_display_mode *adjusted_mode =
6049 &intel_crtc->config.adjusted_mode;
6050 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6051 int pipe = intel_crtc->pipe;
6054 drm_vblank_pre_modeset(dev, pipe);
6056 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6058 drm_vblank_post_modeset(dev, pipe);
6063 for_each_encoder_on_crtc(dev, crtc, encoder) {
6064 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6065 encoder->base.base.id,
6066 drm_get_encoder_name(&encoder->base),
6067 mode->base.id, mode->name);
6068 if (encoder->mode_set) {
6069 encoder->mode_set(encoder);
6071 encoder_funcs = encoder->base.helper_private;
6072 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6079 static bool intel_eld_uptodate(struct drm_connector *connector,
6080 int reg_eldv, uint32_t bits_eldv,
6081 int reg_elda, uint32_t bits_elda,
6084 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6085 uint8_t *eld = connector->eld;
6088 i = I915_READ(reg_eldv);
6097 i = I915_READ(reg_elda);
6099 I915_WRITE(reg_elda, i);
6101 for (i = 0; i < eld[2]; i++)
6102 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6108 static void g4x_write_eld(struct drm_connector *connector,
6109 struct drm_crtc *crtc)
6111 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6112 uint8_t *eld = connector->eld;
6117 i = I915_READ(G4X_AUD_VID_DID);
6119 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6120 eldv = G4X_ELDV_DEVCL_DEVBLC;
6122 eldv = G4X_ELDV_DEVCTG;
6124 if (intel_eld_uptodate(connector,
6125 G4X_AUD_CNTL_ST, eldv,
6126 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6127 G4X_HDMIW_HDMIEDID))
6130 i = I915_READ(G4X_AUD_CNTL_ST);
6131 i &= ~(eldv | G4X_ELD_ADDR);
6132 len = (i >> 9) & 0x1f; /* ELD buffer size */
6133 I915_WRITE(G4X_AUD_CNTL_ST, i);
6138 len = min_t(uint8_t, eld[2], len);
6139 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6140 for (i = 0; i < len; i++)
6141 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6143 i = I915_READ(G4X_AUD_CNTL_ST);
6145 I915_WRITE(G4X_AUD_CNTL_ST, i);
6148 static void haswell_write_eld(struct drm_connector *connector,
6149 struct drm_crtc *crtc)
6151 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6152 uint8_t *eld = connector->eld;
6153 struct drm_device *dev = crtc->dev;
6154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6158 int pipe = to_intel_crtc(crtc)->pipe;
6161 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6162 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6163 int aud_config = HSW_AUD_CFG(pipe);
6164 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6167 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6169 /* Audio output enable */
6170 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6171 tmp = I915_READ(aud_cntrl_st2);
6172 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6173 I915_WRITE(aud_cntrl_st2, tmp);
6175 /* Wait for 1 vertical blank */
6176 intel_wait_for_vblank(dev, pipe);
6178 /* Set ELD valid state */
6179 tmp = I915_READ(aud_cntrl_st2);
6180 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6181 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6182 I915_WRITE(aud_cntrl_st2, tmp);
6183 tmp = I915_READ(aud_cntrl_st2);
6184 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6186 /* Enable HDMI mode */
6187 tmp = I915_READ(aud_config);
6188 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6189 /* clear N_programing_enable and N_value_index */
6190 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6191 I915_WRITE(aud_config, tmp);
6193 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6195 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6196 intel_crtc->eld_vld = true;
6198 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6199 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6200 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6201 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6203 I915_WRITE(aud_config, 0);
6205 if (intel_eld_uptodate(connector,
6206 aud_cntrl_st2, eldv,
6207 aud_cntl_st, IBX_ELD_ADDRESS,
6211 i = I915_READ(aud_cntrl_st2);
6213 I915_WRITE(aud_cntrl_st2, i);
6218 i = I915_READ(aud_cntl_st);
6219 i &= ~IBX_ELD_ADDRESS;
6220 I915_WRITE(aud_cntl_st, i);
6221 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6222 DRM_DEBUG_DRIVER("port num:%d\n", i);
6224 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6225 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6226 for (i = 0; i < len; i++)
6227 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6229 i = I915_READ(aud_cntrl_st2);
6231 I915_WRITE(aud_cntrl_st2, i);
6235 static void ironlake_write_eld(struct drm_connector *connector,
6236 struct drm_crtc *crtc)
6238 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6239 uint8_t *eld = connector->eld;
6247 int pipe = to_intel_crtc(crtc)->pipe;
6249 if (HAS_PCH_IBX(connector->dev)) {
6250 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6251 aud_config = IBX_AUD_CFG(pipe);
6252 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6253 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6255 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6256 aud_config = CPT_AUD_CFG(pipe);
6257 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6258 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6261 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6263 i = I915_READ(aud_cntl_st);
6264 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6266 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6267 /* operate blindly on all ports */
6268 eldv = IBX_ELD_VALIDB;
6269 eldv |= IBX_ELD_VALIDB << 4;
6270 eldv |= IBX_ELD_VALIDB << 8;
6272 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6273 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6276 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6277 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6278 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6279 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6281 I915_WRITE(aud_config, 0);
6283 if (intel_eld_uptodate(connector,
6284 aud_cntrl_st2, eldv,
6285 aud_cntl_st, IBX_ELD_ADDRESS,
6289 i = I915_READ(aud_cntrl_st2);
6291 I915_WRITE(aud_cntrl_st2, i);
6296 i = I915_READ(aud_cntl_st);
6297 i &= ~IBX_ELD_ADDRESS;
6298 I915_WRITE(aud_cntl_st, i);
6300 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6301 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6302 for (i = 0; i < len; i++)
6303 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6305 i = I915_READ(aud_cntrl_st2);
6307 I915_WRITE(aud_cntrl_st2, i);
6310 void intel_write_eld(struct drm_encoder *encoder,
6311 struct drm_display_mode *mode)
6313 struct drm_crtc *crtc = encoder->crtc;
6314 struct drm_connector *connector;
6315 struct drm_device *dev = encoder->dev;
6316 struct drm_i915_private *dev_priv = dev->dev_private;
6318 connector = drm_select_eld(encoder, mode);
6322 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6324 drm_get_connector_name(connector),
6325 connector->encoder->base.id,
6326 drm_get_encoder_name(connector->encoder));
6328 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6330 if (dev_priv->display.write_eld)
6331 dev_priv->display.write_eld(connector, crtc);
6334 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6335 void intel_crtc_load_lut(struct drm_crtc *crtc)
6337 struct drm_device *dev = crtc->dev;
6338 struct drm_i915_private *dev_priv = dev->dev_private;
6339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6340 int palreg = PALETTE(intel_crtc->pipe);
6343 /* The clocks have to be on to load the palette. */
6344 if (!crtc->enabled || !intel_crtc->active)
6347 /* use legacy palette for Ironlake */
6348 if (HAS_PCH_SPLIT(dev))
6349 palreg = LGC_PALETTE(intel_crtc->pipe);
6351 for (i = 0; i < 256; i++) {
6352 I915_WRITE(palreg + 4 * i,
6353 (intel_crtc->lut_r[i] << 16) |
6354 (intel_crtc->lut_g[i] << 8) |
6355 intel_crtc->lut_b[i]);
6359 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6361 struct drm_device *dev = crtc->dev;
6362 struct drm_i915_private *dev_priv = dev->dev_private;
6363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6364 bool visible = base != 0;
6367 if (intel_crtc->cursor_visible == visible)
6370 cntl = I915_READ(_CURACNTR);
6372 /* On these chipsets we can only modify the base whilst
6373 * the cursor is disabled.
6375 I915_WRITE(_CURABASE, base);
6377 cntl &= ~(CURSOR_FORMAT_MASK);
6378 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6379 cntl |= CURSOR_ENABLE |
6380 CURSOR_GAMMA_ENABLE |
6383 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6384 I915_WRITE(_CURACNTR, cntl);
6386 intel_crtc->cursor_visible = visible;
6389 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6391 struct drm_device *dev = crtc->dev;
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6394 int pipe = intel_crtc->pipe;
6395 bool visible = base != 0;
6397 if (intel_crtc->cursor_visible != visible) {
6398 uint32_t cntl = I915_READ(CURCNTR(pipe));
6400 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6401 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6402 cntl |= pipe << 28; /* Connect to correct pipe */
6404 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6405 cntl |= CURSOR_MODE_DISABLE;
6407 I915_WRITE(CURCNTR(pipe), cntl);
6409 intel_crtc->cursor_visible = visible;
6411 /* and commit changes on next vblank */
6412 I915_WRITE(CURBASE(pipe), base);
6415 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6417 struct drm_device *dev = crtc->dev;
6418 struct drm_i915_private *dev_priv = dev->dev_private;
6419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6420 int pipe = intel_crtc->pipe;
6421 bool visible = base != 0;
6423 if (intel_crtc->cursor_visible != visible) {
6424 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6426 cntl &= ~CURSOR_MODE;
6427 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6429 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6430 cntl |= CURSOR_MODE_DISABLE;
6432 if (IS_HASWELL(dev))
6433 cntl |= CURSOR_PIPE_CSC_ENABLE;
6434 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6436 intel_crtc->cursor_visible = visible;
6438 /* and commit changes on next vblank */
6439 I915_WRITE(CURBASE_IVB(pipe), base);
6442 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6443 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6446 struct drm_device *dev = crtc->dev;
6447 struct drm_i915_private *dev_priv = dev->dev_private;
6448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6449 int pipe = intel_crtc->pipe;
6450 int x = intel_crtc->cursor_x;
6451 int y = intel_crtc->cursor_y;
6457 if (on && crtc->enabled && crtc->fb) {
6458 base = intel_crtc->cursor_addr;
6459 if (x > (int) crtc->fb->width)
6462 if (y > (int) crtc->fb->height)
6468 if (x + intel_crtc->cursor_width < 0)
6471 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6474 pos |= x << CURSOR_X_SHIFT;
6477 if (y + intel_crtc->cursor_height < 0)
6480 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6483 pos |= y << CURSOR_Y_SHIFT;
6485 visible = base != 0;
6486 if (!visible && !intel_crtc->cursor_visible)
6489 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6490 I915_WRITE(CURPOS_IVB(pipe), pos);
6491 ivb_update_cursor(crtc, base);
6493 I915_WRITE(CURPOS(pipe), pos);
6494 if (IS_845G(dev) || IS_I865G(dev))
6495 i845_update_cursor(crtc, base);
6497 i9xx_update_cursor(crtc, base);
6501 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6502 struct drm_file *file,
6504 uint32_t width, uint32_t height)
6506 struct drm_device *dev = crtc->dev;
6507 struct drm_i915_private *dev_priv = dev->dev_private;
6508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6509 struct drm_i915_gem_object *obj;
6513 /* if we want to turn off the cursor ignore width and height */
6515 DRM_DEBUG_KMS("cursor off\n");
6518 mutex_lock(&dev->struct_mutex);
6522 /* Currently we only support 64x64 cursors */
6523 if (width != 64 || height != 64) {
6524 DRM_ERROR("we currently only support 64x64 cursors\n");
6528 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6529 if (&obj->base == NULL)
6532 if (obj->base.size < width * height * 4) {
6533 DRM_ERROR("buffer is to small\n");
6538 /* we only need to pin inside GTT if cursor is non-phy */
6539 mutex_lock(&dev->struct_mutex);
6540 if (!dev_priv->info->cursor_needs_physical) {
6543 if (obj->tiling_mode) {
6544 DRM_ERROR("cursor cannot be tiled\n");
6549 /* Note that the w/a also requires 2 PTE of padding following
6550 * the bo. We currently fill all unused PTE with the shadow
6551 * page and so we should always have valid PTE following the
6552 * cursor preventing the VT-d warning.
6555 if (need_vtd_wa(dev))
6556 alignment = 64*1024;
6558 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6560 DRM_ERROR("failed to move cursor bo into the GTT\n");
6564 ret = i915_gem_object_put_fence(obj);
6566 DRM_ERROR("failed to release fence for cursor");
6570 addr = obj->gtt_offset;
6572 int align = IS_I830(dev) ? 16 * 1024 : 256;
6573 ret = i915_gem_attach_phys_object(dev, obj,
6574 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6577 DRM_ERROR("failed to attach phys object\n");
6580 addr = obj->phys_obj->handle->busaddr;
6584 I915_WRITE(CURSIZE, (height << 12) | width);
6587 if (intel_crtc->cursor_bo) {
6588 if (dev_priv->info->cursor_needs_physical) {
6589 if (intel_crtc->cursor_bo != obj)
6590 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6592 i915_gem_object_unpin(intel_crtc->cursor_bo);
6593 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6596 mutex_unlock(&dev->struct_mutex);
6598 intel_crtc->cursor_addr = addr;
6599 intel_crtc->cursor_bo = obj;
6600 intel_crtc->cursor_width = width;
6601 intel_crtc->cursor_height = height;
6603 intel_crtc_update_cursor(crtc, true);
6607 i915_gem_object_unpin(obj);
6609 mutex_unlock(&dev->struct_mutex);
6611 drm_gem_object_unreference_unlocked(&obj->base);
6615 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6619 intel_crtc->cursor_x = x;
6620 intel_crtc->cursor_y = y;
6622 intel_crtc_update_cursor(crtc, true);
6627 /** Sets the color ramps on behalf of RandR */
6628 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6629 u16 blue, int regno)
6631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6633 intel_crtc->lut_r[regno] = red >> 8;
6634 intel_crtc->lut_g[regno] = green >> 8;
6635 intel_crtc->lut_b[regno] = blue >> 8;
6638 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6639 u16 *blue, int regno)
6641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6643 *red = intel_crtc->lut_r[regno] << 8;
6644 *green = intel_crtc->lut_g[regno] << 8;
6645 *blue = intel_crtc->lut_b[regno] << 8;
6648 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6649 u16 *blue, uint32_t start, uint32_t size)
6651 int end = (start + size > 256) ? 256 : start + size, i;
6652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654 for (i = start; i < end; i++) {
6655 intel_crtc->lut_r[i] = red[i] >> 8;
6656 intel_crtc->lut_g[i] = green[i] >> 8;
6657 intel_crtc->lut_b[i] = blue[i] >> 8;
6660 intel_crtc_load_lut(crtc);
6663 /* VESA 640x480x72Hz mode to set on the pipe */
6664 static struct drm_display_mode load_detect_mode = {
6665 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6666 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6669 static struct drm_framebuffer *
6670 intel_framebuffer_create(struct drm_device *dev,
6671 struct drm_mode_fb_cmd2 *mode_cmd,
6672 struct drm_i915_gem_object *obj)
6674 struct intel_framebuffer *intel_fb;
6677 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6679 drm_gem_object_unreference_unlocked(&obj->base);
6680 return ERR_PTR(-ENOMEM);
6683 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6685 drm_gem_object_unreference_unlocked(&obj->base);
6687 return ERR_PTR(ret);
6690 return &intel_fb->base;
6694 intel_framebuffer_pitch_for_width(int width, int bpp)
6696 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6697 return ALIGN(pitch, 64);
6701 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6703 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6704 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6707 static struct drm_framebuffer *
6708 intel_framebuffer_create_for_mode(struct drm_device *dev,
6709 struct drm_display_mode *mode,
6712 struct drm_i915_gem_object *obj;
6713 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6715 obj = i915_gem_alloc_object(dev,
6716 intel_framebuffer_size_for_mode(mode, bpp));
6718 return ERR_PTR(-ENOMEM);
6720 mode_cmd.width = mode->hdisplay;
6721 mode_cmd.height = mode->vdisplay;
6722 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6724 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6726 return intel_framebuffer_create(dev, &mode_cmd, obj);
6729 static struct drm_framebuffer *
6730 mode_fits_in_fbdev(struct drm_device *dev,
6731 struct drm_display_mode *mode)
6733 struct drm_i915_private *dev_priv = dev->dev_private;
6734 struct drm_i915_gem_object *obj;
6735 struct drm_framebuffer *fb;
6737 if (dev_priv->fbdev == NULL)
6740 obj = dev_priv->fbdev->ifb.obj;
6744 fb = &dev_priv->fbdev->ifb.base;
6745 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6746 fb->bits_per_pixel))
6749 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6755 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6756 struct drm_display_mode *mode,
6757 struct intel_load_detect_pipe *old)
6759 struct intel_crtc *intel_crtc;
6760 struct intel_encoder *intel_encoder =
6761 intel_attached_encoder(connector);
6762 struct drm_crtc *possible_crtc;
6763 struct drm_encoder *encoder = &intel_encoder->base;
6764 struct drm_crtc *crtc = NULL;
6765 struct drm_device *dev = encoder->dev;
6766 struct drm_framebuffer *fb;
6769 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6770 connector->base.id, drm_get_connector_name(connector),
6771 encoder->base.id, drm_get_encoder_name(encoder));
6774 * Algorithm gets a little messy:
6776 * - if the connector already has an assigned crtc, use it (but make
6777 * sure it's on first)
6779 * - try to find the first unused crtc that can drive this connector,
6780 * and use that if we find one
6783 /* See if we already have a CRTC for this connector */
6784 if (encoder->crtc) {
6785 crtc = encoder->crtc;
6787 mutex_lock(&crtc->mutex);
6789 old->dpms_mode = connector->dpms;
6790 old->load_detect_temp = false;
6792 /* Make sure the crtc and connector are running */
6793 if (connector->dpms != DRM_MODE_DPMS_ON)
6794 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6799 /* Find an unused one (if possible) */
6800 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6802 if (!(encoder->possible_crtcs & (1 << i)))
6804 if (!possible_crtc->enabled) {
6805 crtc = possible_crtc;
6811 * If we didn't find an unused CRTC, don't use any.
6814 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6818 mutex_lock(&crtc->mutex);
6819 intel_encoder->new_crtc = to_intel_crtc(crtc);
6820 to_intel_connector(connector)->new_encoder = intel_encoder;
6822 intel_crtc = to_intel_crtc(crtc);
6823 old->dpms_mode = connector->dpms;
6824 old->load_detect_temp = true;
6825 old->release_fb = NULL;
6828 mode = &load_detect_mode;
6830 /* We need a framebuffer large enough to accommodate all accesses
6831 * that the plane may generate whilst we perform load detection.
6832 * We can not rely on the fbcon either being present (we get called
6833 * during its initialisation to detect all boot displays, or it may
6834 * not even exist) or that it is large enough to satisfy the
6837 fb = mode_fits_in_fbdev(dev, mode);
6839 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6840 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6841 old->release_fb = fb;
6843 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6845 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6846 mutex_unlock(&crtc->mutex);
6850 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6851 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6852 if (old->release_fb)
6853 old->release_fb->funcs->destroy(old->release_fb);
6854 mutex_unlock(&crtc->mutex);
6858 /* let the connector get through one full cycle before testing */
6859 intel_wait_for_vblank(dev, intel_crtc->pipe);
6863 void intel_release_load_detect_pipe(struct drm_connector *connector,
6864 struct intel_load_detect_pipe *old)
6866 struct intel_encoder *intel_encoder =
6867 intel_attached_encoder(connector);
6868 struct drm_encoder *encoder = &intel_encoder->base;
6869 struct drm_crtc *crtc = encoder->crtc;
6871 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6872 connector->base.id, drm_get_connector_name(connector),
6873 encoder->base.id, drm_get_encoder_name(encoder));
6875 if (old->load_detect_temp) {
6876 to_intel_connector(connector)->new_encoder = NULL;
6877 intel_encoder->new_crtc = NULL;
6878 intel_set_mode(crtc, NULL, 0, 0, NULL);
6880 if (old->release_fb) {
6881 drm_framebuffer_unregister_private(old->release_fb);
6882 drm_framebuffer_unreference(old->release_fb);
6885 mutex_unlock(&crtc->mutex);
6889 /* Switch crtc and encoder back off if necessary */
6890 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6891 connector->funcs->dpms(connector, old->dpms_mode);
6893 mutex_unlock(&crtc->mutex);
6896 /* Returns the clock of the currently programmed mode of the given pipe. */
6897 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6901 int pipe = intel_crtc->pipe;
6902 u32 dpll = I915_READ(DPLL(pipe));
6904 intel_clock_t clock;
6906 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6907 fp = I915_READ(FP0(pipe));
6909 fp = I915_READ(FP1(pipe));
6911 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6912 if (IS_PINEVIEW(dev)) {
6913 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6914 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6916 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6917 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6920 if (!IS_GEN2(dev)) {
6921 if (IS_PINEVIEW(dev))
6922 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6923 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6925 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6926 DPLL_FPA01_P1_POST_DIV_SHIFT);
6928 switch (dpll & DPLL_MODE_MASK) {
6929 case DPLLB_MODE_DAC_SERIAL:
6930 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6933 case DPLLB_MODE_LVDS:
6934 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6938 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6939 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6943 /* XXX: Handle the 100Mhz refclk */
6944 intel_clock(dev, 96000, &clock);
6946 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6949 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6950 DPLL_FPA01_P1_POST_DIV_SHIFT);
6953 if ((dpll & PLL_REF_INPUT_MASK) ==
6954 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6955 /* XXX: might not be 66MHz */
6956 intel_clock(dev, 66000, &clock);
6958 intel_clock(dev, 48000, &clock);
6960 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6963 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6964 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6966 if (dpll & PLL_P2_DIVIDE_BY_4)
6971 intel_clock(dev, 48000, &clock);
6975 /* XXX: It would be nice to validate the clocks, but we can't reuse
6976 * i830PllIsValid() because it relies on the xf86_config connector
6977 * configuration being accurate, which it isn't necessarily.
6983 /** Returns the currently programmed mode of the given pipe. */
6984 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6985 struct drm_crtc *crtc)
6987 struct drm_i915_private *dev_priv = dev->dev_private;
6988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6989 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6990 struct drm_display_mode *mode;
6991 int htot = I915_READ(HTOTAL(cpu_transcoder));
6992 int hsync = I915_READ(HSYNC(cpu_transcoder));
6993 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6994 int vsync = I915_READ(VSYNC(cpu_transcoder));
6996 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7000 mode->clock = intel_crtc_clock_get(dev, crtc);
7001 mode->hdisplay = (htot & 0xffff) + 1;
7002 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7003 mode->hsync_start = (hsync & 0xffff) + 1;
7004 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7005 mode->vdisplay = (vtot & 0xffff) + 1;
7006 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7007 mode->vsync_start = (vsync & 0xffff) + 1;
7008 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7010 drm_mode_set_name(mode);
7015 static void intel_increase_pllclock(struct drm_crtc *crtc)
7017 struct drm_device *dev = crtc->dev;
7018 drm_i915_private_t *dev_priv = dev->dev_private;
7019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7020 int pipe = intel_crtc->pipe;
7021 int dpll_reg = DPLL(pipe);
7024 if (HAS_PCH_SPLIT(dev))
7027 if (!dev_priv->lvds_downclock_avail)
7030 dpll = I915_READ(dpll_reg);
7031 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7032 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7034 assert_panel_unlocked(dev_priv, pipe);
7036 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7037 I915_WRITE(dpll_reg, dpll);
7038 intel_wait_for_vblank(dev, pipe);
7040 dpll = I915_READ(dpll_reg);
7041 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7042 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7046 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7048 struct drm_device *dev = crtc->dev;
7049 drm_i915_private_t *dev_priv = dev->dev_private;
7050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7052 if (HAS_PCH_SPLIT(dev))
7055 if (!dev_priv->lvds_downclock_avail)
7059 * Since this is called by a timer, we should never get here in
7062 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7063 int pipe = intel_crtc->pipe;
7064 int dpll_reg = DPLL(pipe);
7067 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7069 assert_panel_unlocked(dev_priv, pipe);
7071 dpll = I915_READ(dpll_reg);
7072 dpll |= DISPLAY_RATE_SELECT_FPA1;
7073 I915_WRITE(dpll_reg, dpll);
7074 intel_wait_for_vblank(dev, pipe);
7075 dpll = I915_READ(dpll_reg);
7076 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7077 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7082 void intel_mark_busy(struct drm_device *dev)
7084 i915_update_gfx_val(dev->dev_private);
7087 void intel_mark_idle(struct drm_device *dev)
7089 struct drm_crtc *crtc;
7091 if (!i915_powersave)
7094 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7098 intel_decrease_pllclock(crtc);
7102 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7104 struct drm_device *dev = obj->base.dev;
7105 struct drm_crtc *crtc;
7107 if (!i915_powersave)
7110 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7114 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7115 intel_increase_pllclock(crtc);
7119 static void intel_crtc_destroy(struct drm_crtc *crtc)
7121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7122 struct drm_device *dev = crtc->dev;
7123 struct intel_unpin_work *work;
7124 unsigned long flags;
7126 spin_lock_irqsave(&dev->event_lock, flags);
7127 work = intel_crtc->unpin_work;
7128 intel_crtc->unpin_work = NULL;
7129 spin_unlock_irqrestore(&dev->event_lock, flags);
7132 cancel_work_sync(&work->work);
7136 drm_crtc_cleanup(crtc);
7141 static void intel_unpin_work_fn(struct work_struct *__work)
7143 struct intel_unpin_work *work =
7144 container_of(__work, struct intel_unpin_work, work);
7145 struct drm_device *dev = work->crtc->dev;
7147 mutex_lock(&dev->struct_mutex);
7148 intel_unpin_fb_obj(work->old_fb_obj);
7149 drm_gem_object_unreference(&work->pending_flip_obj->base);
7150 drm_gem_object_unreference(&work->old_fb_obj->base);
7152 intel_update_fbc(dev);
7153 mutex_unlock(&dev->struct_mutex);
7155 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7156 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7161 static void do_intel_finish_page_flip(struct drm_device *dev,
7162 struct drm_crtc *crtc)
7164 drm_i915_private_t *dev_priv = dev->dev_private;
7165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7166 struct intel_unpin_work *work;
7167 unsigned long flags;
7169 /* Ignore early vblank irqs */
7170 if (intel_crtc == NULL)
7173 spin_lock_irqsave(&dev->event_lock, flags);
7174 work = intel_crtc->unpin_work;
7176 /* Ensure we don't miss a work->pending update ... */
7179 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7180 spin_unlock_irqrestore(&dev->event_lock, flags);
7184 /* and that the unpin work is consistent wrt ->pending. */
7187 intel_crtc->unpin_work = NULL;
7190 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7192 drm_vblank_put(dev, intel_crtc->pipe);
7194 spin_unlock_irqrestore(&dev->event_lock, flags);
7196 wake_up_all(&dev_priv->pending_flip_queue);
7198 queue_work(dev_priv->wq, &work->work);
7200 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7203 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7205 drm_i915_private_t *dev_priv = dev->dev_private;
7206 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7208 do_intel_finish_page_flip(dev, crtc);
7211 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7213 drm_i915_private_t *dev_priv = dev->dev_private;
7214 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7216 do_intel_finish_page_flip(dev, crtc);
7219 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7221 drm_i915_private_t *dev_priv = dev->dev_private;
7222 struct intel_crtc *intel_crtc =
7223 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7224 unsigned long flags;
7226 /* NB: An MMIO update of the plane base pointer will also
7227 * generate a page-flip completion irq, i.e. every modeset
7228 * is also accompanied by a spurious intel_prepare_page_flip().
7230 spin_lock_irqsave(&dev->event_lock, flags);
7231 if (intel_crtc->unpin_work)
7232 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7233 spin_unlock_irqrestore(&dev->event_lock, flags);
7236 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7238 /* Ensure that the work item is consistent when activating it ... */
7240 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7241 /* and that it is marked active as soon as the irq could fire. */
7245 static int intel_gen2_queue_flip(struct drm_device *dev,
7246 struct drm_crtc *crtc,
7247 struct drm_framebuffer *fb,
7248 struct drm_i915_gem_object *obj)
7250 struct drm_i915_private *dev_priv = dev->dev_private;
7251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7253 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7256 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7260 ret = intel_ring_begin(ring, 6);
7264 /* Can't queue multiple flips, so wait for the previous
7265 * one to finish before executing the next.
7267 if (intel_crtc->plane)
7268 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7270 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7271 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7272 intel_ring_emit(ring, MI_NOOP);
7273 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7274 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7275 intel_ring_emit(ring, fb->pitches[0]);
7276 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7277 intel_ring_emit(ring, 0); /* aux display base address, unused */
7279 intel_mark_page_flip_active(intel_crtc);
7280 intel_ring_advance(ring);
7284 intel_unpin_fb_obj(obj);
7289 static int intel_gen3_queue_flip(struct drm_device *dev,
7290 struct drm_crtc *crtc,
7291 struct drm_framebuffer *fb,
7292 struct drm_i915_gem_object *obj)
7294 struct drm_i915_private *dev_priv = dev->dev_private;
7295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7297 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7300 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7304 ret = intel_ring_begin(ring, 6);
7308 if (intel_crtc->plane)
7309 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7311 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7312 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7313 intel_ring_emit(ring, MI_NOOP);
7314 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7315 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7316 intel_ring_emit(ring, fb->pitches[0]);
7317 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7318 intel_ring_emit(ring, MI_NOOP);
7320 intel_mark_page_flip_active(intel_crtc);
7321 intel_ring_advance(ring);
7325 intel_unpin_fb_obj(obj);
7330 static int intel_gen4_queue_flip(struct drm_device *dev,
7331 struct drm_crtc *crtc,
7332 struct drm_framebuffer *fb,
7333 struct drm_i915_gem_object *obj)
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7337 uint32_t pf, pipesrc;
7338 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7341 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7345 ret = intel_ring_begin(ring, 4);
7349 /* i965+ uses the linear or tiled offsets from the
7350 * Display Registers (which do not change across a page-flip)
7351 * so we need only reprogram the base address.
7353 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7354 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7355 intel_ring_emit(ring, fb->pitches[0]);
7356 intel_ring_emit(ring,
7357 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7360 /* XXX Enabling the panel-fitter across page-flip is so far
7361 * untested on non-native modes, so ignore it for now.
7362 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7365 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7366 intel_ring_emit(ring, pf | pipesrc);
7368 intel_mark_page_flip_active(intel_crtc);
7369 intel_ring_advance(ring);
7373 intel_unpin_fb_obj(obj);
7378 static int intel_gen6_queue_flip(struct drm_device *dev,
7379 struct drm_crtc *crtc,
7380 struct drm_framebuffer *fb,
7381 struct drm_i915_gem_object *obj)
7383 struct drm_i915_private *dev_priv = dev->dev_private;
7384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7385 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7386 uint32_t pf, pipesrc;
7389 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7393 ret = intel_ring_begin(ring, 4);
7397 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7398 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7399 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7400 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7402 /* Contrary to the suggestions in the documentation,
7403 * "Enable Panel Fitter" does not seem to be required when page
7404 * flipping with a non-native mode, and worse causes a normal
7406 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7409 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7410 intel_ring_emit(ring, pf | pipesrc);
7412 intel_mark_page_flip_active(intel_crtc);
7413 intel_ring_advance(ring);
7417 intel_unpin_fb_obj(obj);
7423 * On gen7 we currently use the blit ring because (in early silicon at least)
7424 * the render ring doesn't give us interrpts for page flip completion, which
7425 * means clients will hang after the first flip is queued. Fortunately the
7426 * blit ring generates interrupts properly, so use it instead.
7428 static int intel_gen7_queue_flip(struct drm_device *dev,
7429 struct drm_crtc *crtc,
7430 struct drm_framebuffer *fb,
7431 struct drm_i915_gem_object *obj)
7433 struct drm_i915_private *dev_priv = dev->dev_private;
7434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7435 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7436 uint32_t plane_bit = 0;
7439 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7443 switch(intel_crtc->plane) {
7445 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7448 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7451 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7454 WARN_ONCE(1, "unknown plane in flip command\n");
7459 ret = intel_ring_begin(ring, 4);
7463 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7464 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7465 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7466 intel_ring_emit(ring, (MI_NOOP));
7468 intel_mark_page_flip_active(intel_crtc);
7469 intel_ring_advance(ring);
7473 intel_unpin_fb_obj(obj);
7478 static int intel_default_queue_flip(struct drm_device *dev,
7479 struct drm_crtc *crtc,
7480 struct drm_framebuffer *fb,
7481 struct drm_i915_gem_object *obj)
7486 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7487 struct drm_framebuffer *fb,
7488 struct drm_pending_vblank_event *event)
7490 struct drm_device *dev = crtc->dev;
7491 struct drm_i915_private *dev_priv = dev->dev_private;
7492 struct drm_framebuffer *old_fb = crtc->fb;
7493 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7495 struct intel_unpin_work *work;
7496 unsigned long flags;
7499 /* Can't change pixel format via MI display flips. */
7500 if (fb->pixel_format != crtc->fb->pixel_format)
7504 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7505 * Note that pitch changes could also affect these register.
7507 if (INTEL_INFO(dev)->gen > 3 &&
7508 (fb->offsets[0] != crtc->fb->offsets[0] ||
7509 fb->pitches[0] != crtc->fb->pitches[0]))
7512 work = kzalloc(sizeof *work, GFP_KERNEL);
7516 work->event = event;
7518 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7519 INIT_WORK(&work->work, intel_unpin_work_fn);
7521 ret = drm_vblank_get(dev, intel_crtc->pipe);
7525 /* We borrow the event spin lock for protecting unpin_work */
7526 spin_lock_irqsave(&dev->event_lock, flags);
7527 if (intel_crtc->unpin_work) {
7528 spin_unlock_irqrestore(&dev->event_lock, flags);
7530 drm_vblank_put(dev, intel_crtc->pipe);
7532 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7535 intel_crtc->unpin_work = work;
7536 spin_unlock_irqrestore(&dev->event_lock, flags);
7538 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7539 flush_workqueue(dev_priv->wq);
7541 ret = i915_mutex_lock_interruptible(dev);
7545 /* Reference the objects for the scheduled work. */
7546 drm_gem_object_reference(&work->old_fb_obj->base);
7547 drm_gem_object_reference(&obj->base);
7551 work->pending_flip_obj = obj;
7553 work->enable_stall_check = true;
7555 atomic_inc(&intel_crtc->unpin_work_count);
7556 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7558 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7560 goto cleanup_pending;
7562 intel_disable_fbc(dev);
7563 intel_mark_fb_busy(obj);
7564 mutex_unlock(&dev->struct_mutex);
7566 trace_i915_flip_request(intel_crtc->plane, obj);
7571 atomic_dec(&intel_crtc->unpin_work_count);
7573 drm_gem_object_unreference(&work->old_fb_obj->base);
7574 drm_gem_object_unreference(&obj->base);
7575 mutex_unlock(&dev->struct_mutex);
7578 spin_lock_irqsave(&dev->event_lock, flags);
7579 intel_crtc->unpin_work = NULL;
7580 spin_unlock_irqrestore(&dev->event_lock, flags);
7582 drm_vblank_put(dev, intel_crtc->pipe);
7589 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7590 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7591 .load_lut = intel_crtc_load_lut,
7594 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7596 struct intel_encoder *other_encoder;
7597 struct drm_crtc *crtc = &encoder->new_crtc->base;
7602 list_for_each_entry(other_encoder,
7603 &crtc->dev->mode_config.encoder_list,
7606 if (&other_encoder->new_crtc->base != crtc ||
7607 encoder == other_encoder)
7616 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7617 struct drm_crtc *crtc)
7619 struct drm_device *dev;
7620 struct drm_crtc *tmp;
7623 WARN(!crtc, "checking null crtc?\n");
7627 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7633 if (encoder->possible_crtcs & crtc_mask)
7639 * intel_modeset_update_staged_output_state
7641 * Updates the staged output configuration state, e.g. after we've read out the
7644 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7646 struct intel_encoder *encoder;
7647 struct intel_connector *connector;
7649 list_for_each_entry(connector, &dev->mode_config.connector_list,
7651 connector->new_encoder =
7652 to_intel_encoder(connector->base.encoder);
7655 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7658 to_intel_crtc(encoder->base.crtc);
7663 * intel_modeset_commit_output_state
7665 * This function copies the stage display pipe configuration to the real one.
7667 static void intel_modeset_commit_output_state(struct drm_device *dev)
7669 struct intel_encoder *encoder;
7670 struct intel_connector *connector;
7672 list_for_each_entry(connector, &dev->mode_config.connector_list,
7674 connector->base.encoder = &connector->new_encoder->base;
7677 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7679 encoder->base.crtc = &encoder->new_crtc->base;
7684 pipe_config_set_bpp(struct drm_crtc *crtc,
7685 struct drm_framebuffer *fb,
7686 struct intel_crtc_config *pipe_config)
7688 struct drm_device *dev = crtc->dev;
7689 struct drm_connector *connector;
7692 switch (fb->pixel_format) {
7694 bpp = 8*3; /* since we go through a colormap */
7696 case DRM_FORMAT_XRGB1555:
7697 case DRM_FORMAT_ARGB1555:
7698 /* checked in intel_framebuffer_init already */
7699 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7701 case DRM_FORMAT_RGB565:
7702 bpp = 6*3; /* min is 18bpp */
7704 case DRM_FORMAT_XBGR8888:
7705 case DRM_FORMAT_ABGR8888:
7706 /* checked in intel_framebuffer_init already */
7707 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7709 case DRM_FORMAT_XRGB8888:
7710 case DRM_FORMAT_ARGB8888:
7713 case DRM_FORMAT_XRGB2101010:
7714 case DRM_FORMAT_ARGB2101010:
7715 case DRM_FORMAT_XBGR2101010:
7716 case DRM_FORMAT_ABGR2101010:
7717 /* checked in intel_framebuffer_init already */
7718 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7722 /* TODO: gen4+ supports 16 bpc floating point, too. */
7724 DRM_DEBUG_KMS("unsupported depth\n");
7728 pipe_config->pipe_bpp = bpp;
7730 /* Clamp display bpp to EDID value */
7731 list_for_each_entry(connector, &dev->mode_config.connector_list,
7733 if (connector->encoder && connector->encoder->crtc != crtc)
7736 /* Don't use an invalid EDID bpc value */
7737 if (connector->display_info.bpc &&
7738 connector->display_info.bpc * 3 < bpp) {
7739 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7740 bpp, connector->display_info.bpc*3);
7741 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7744 /* Clamp bpp to 8 on screens without EDID 1.4 */
7745 if (connector->display_info.bpc == 0 && bpp > 24) {
7746 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7748 pipe_config->pipe_bpp = 24;
7755 static struct intel_crtc_config *
7756 intel_modeset_pipe_config(struct drm_crtc *crtc,
7757 struct drm_framebuffer *fb,
7758 struct drm_display_mode *mode)
7760 struct drm_device *dev = crtc->dev;
7761 struct drm_encoder_helper_funcs *encoder_funcs;
7762 struct intel_encoder *encoder;
7763 struct intel_crtc_config *pipe_config;
7764 int plane_bpp, ret = -EINVAL;
7767 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7769 return ERR_PTR(-ENOMEM);
7771 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7772 drm_mode_copy(&pipe_config->requested_mode, mode);
7774 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7779 /* Pass our mode to the connectors and the CRTC to give them a chance to
7780 * adjust it according to limitations or connector properties, and also
7781 * a chance to reject the mode entirely.
7783 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7786 if (&encoder->new_crtc->base != crtc)
7789 if (encoder->compute_config) {
7790 if (!(encoder->compute_config(encoder, pipe_config))) {
7791 DRM_DEBUG_KMS("Encoder config failure\n");
7798 encoder_funcs = encoder->base.helper_private;
7799 if (!(encoder_funcs->mode_fixup(&encoder->base,
7800 &pipe_config->requested_mode,
7801 &pipe_config->adjusted_mode))) {
7802 DRM_DEBUG_KMS("Encoder fixup failed\n");
7807 ret = intel_crtc_compute_config(crtc, pipe_config);
7809 DRM_DEBUG_KMS("CRTC fixup failed\n");
7814 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7819 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7824 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7826 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7827 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7828 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7833 return ERR_PTR(ret);
7836 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7837 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7839 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7840 unsigned *prepare_pipes, unsigned *disable_pipes)
7842 struct intel_crtc *intel_crtc;
7843 struct drm_device *dev = crtc->dev;
7844 struct intel_encoder *encoder;
7845 struct intel_connector *connector;
7846 struct drm_crtc *tmp_crtc;
7848 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7850 /* Check which crtcs have changed outputs connected to them, these need
7851 * to be part of the prepare_pipes mask. We don't (yet) support global
7852 * modeset across multiple crtcs, so modeset_pipes will only have one
7853 * bit set at most. */
7854 list_for_each_entry(connector, &dev->mode_config.connector_list,
7856 if (connector->base.encoder == &connector->new_encoder->base)
7859 if (connector->base.encoder) {
7860 tmp_crtc = connector->base.encoder->crtc;
7862 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7865 if (connector->new_encoder)
7867 1 << connector->new_encoder->new_crtc->pipe;
7870 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7872 if (encoder->base.crtc == &encoder->new_crtc->base)
7875 if (encoder->base.crtc) {
7876 tmp_crtc = encoder->base.crtc;
7878 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7881 if (encoder->new_crtc)
7882 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7885 /* Check for any pipes that will be fully disabled ... */
7886 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7890 /* Don't try to disable disabled crtcs. */
7891 if (!intel_crtc->base.enabled)
7894 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7896 if (encoder->new_crtc == intel_crtc)
7901 *disable_pipes |= 1 << intel_crtc->pipe;
7905 /* set_mode is also used to update properties on life display pipes. */
7906 intel_crtc = to_intel_crtc(crtc);
7908 *prepare_pipes |= 1 << intel_crtc->pipe;
7911 * For simplicity do a full modeset on any pipe where the output routing
7912 * changed. We could be more clever, but that would require us to be
7913 * more careful with calling the relevant encoder->mode_set functions.
7916 *modeset_pipes = *prepare_pipes;
7918 /* ... and mask these out. */
7919 *modeset_pipes &= ~(*disable_pipes);
7920 *prepare_pipes &= ~(*disable_pipes);
7923 * HACK: We don't (yet) fully support global modesets. intel_set_config
7924 * obies this rule, but the modeset restore mode of
7925 * intel_modeset_setup_hw_state does not.
7927 *modeset_pipes &= 1 << intel_crtc->pipe;
7928 *prepare_pipes &= 1 << intel_crtc->pipe;
7930 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7931 *modeset_pipes, *prepare_pipes, *disable_pipes);
7934 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7936 struct drm_encoder *encoder;
7937 struct drm_device *dev = crtc->dev;
7939 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7940 if (encoder->crtc == crtc)
7947 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7949 struct intel_encoder *intel_encoder;
7950 struct intel_crtc *intel_crtc;
7951 struct drm_connector *connector;
7953 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7955 if (!intel_encoder->base.crtc)
7958 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7960 if (prepare_pipes & (1 << intel_crtc->pipe))
7961 intel_encoder->connectors_active = false;
7964 intel_modeset_commit_output_state(dev);
7966 /* Update computed state. */
7967 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7969 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7972 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7973 if (!connector->encoder || !connector->encoder->crtc)
7976 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7978 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7979 struct drm_property *dpms_property =
7980 dev->mode_config.dpms_property;
7982 connector->dpms = DRM_MODE_DPMS_ON;
7983 drm_object_property_set_value(&connector->base,
7987 intel_encoder = to_intel_encoder(connector->encoder);
7988 intel_encoder->connectors_active = true;
7994 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7995 list_for_each_entry((intel_crtc), \
7996 &(dev)->mode_config.crtc_list, \
7998 if (mask & (1 <<(intel_crtc)->pipe))
8001 intel_pipe_config_compare(struct intel_crtc_config *current_config,
8002 struct intel_crtc_config *pipe_config)
8004 #define PIPE_CONF_CHECK_I(name) \
8005 if (current_config->name != pipe_config->name) { \
8006 DRM_ERROR("mismatch in " #name " " \
8007 "(expected %i, found %i)\n", \
8008 current_config->name, \
8009 pipe_config->name); \
8013 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8014 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8015 DRM_ERROR("mismatch in " #name " " \
8016 "(expected %i, found %i)\n", \
8017 current_config->name & (mask), \
8018 pipe_config->name & (mask)); \
8022 PIPE_CONF_CHECK_I(has_pch_encoder);
8023 PIPE_CONF_CHECK_I(fdi_lanes);
8024 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8025 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8026 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8027 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8028 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8030 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8031 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8032 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8033 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8034 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8035 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8037 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8038 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8039 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8040 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8041 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8042 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8044 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8045 DRM_MODE_FLAG_INTERLACE);
8047 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8048 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8050 #undef PIPE_CONF_CHECK_I
8051 #undef PIPE_CONF_CHECK_FLAGS
8057 intel_modeset_check_state(struct drm_device *dev)
8059 drm_i915_private_t *dev_priv = dev->dev_private;
8060 struct intel_crtc *crtc;
8061 struct intel_encoder *encoder;
8062 struct intel_connector *connector;
8063 struct intel_crtc_config pipe_config;
8065 list_for_each_entry(connector, &dev->mode_config.connector_list,
8067 /* This also checks the encoder/connector hw state with the
8068 * ->get_hw_state callbacks. */
8069 intel_connector_check_state(connector);
8071 WARN(&connector->new_encoder->base != connector->base.encoder,
8072 "connector's staged encoder doesn't match current encoder\n");
8075 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8077 bool enabled = false;
8078 bool active = false;
8079 enum pipe pipe, tracked_pipe;
8081 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8082 encoder->base.base.id,
8083 drm_get_encoder_name(&encoder->base));
8085 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8086 "encoder's stage crtc doesn't match current crtc\n");
8087 WARN(encoder->connectors_active && !encoder->base.crtc,
8088 "encoder's active_connectors set, but no crtc\n");
8090 list_for_each_entry(connector, &dev->mode_config.connector_list,
8092 if (connector->base.encoder != &encoder->base)
8095 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8098 WARN(!!encoder->base.crtc != enabled,
8099 "encoder's enabled state mismatch "
8100 "(expected %i, found %i)\n",
8101 !!encoder->base.crtc, enabled);
8102 WARN(active && !encoder->base.crtc,
8103 "active encoder with no crtc\n");
8105 WARN(encoder->connectors_active != active,
8106 "encoder's computed active state doesn't match tracked active state "
8107 "(expected %i, found %i)\n", active, encoder->connectors_active);
8109 active = encoder->get_hw_state(encoder, &pipe);
8110 WARN(active != encoder->connectors_active,
8111 "encoder's hw state doesn't match sw tracking "
8112 "(expected %i, found %i)\n",
8113 encoder->connectors_active, active);
8115 if (!encoder->base.crtc)
8118 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8119 WARN(active && pipe != tracked_pipe,
8120 "active encoder's pipe doesn't match"
8121 "(expected %i, found %i)\n",
8122 tracked_pipe, pipe);
8126 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8128 bool enabled = false;
8129 bool active = false;
8131 DRM_DEBUG_KMS("[CRTC:%d]\n",
8132 crtc->base.base.id);
8134 WARN(crtc->active && !crtc->base.enabled,
8135 "active crtc, but not enabled in sw tracking\n");
8137 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8139 if (encoder->base.crtc != &crtc->base)
8142 if (encoder->connectors_active)
8145 WARN(active != crtc->active,
8146 "crtc's computed active state doesn't match tracked active state "
8147 "(expected %i, found %i)\n", active, crtc->active);
8148 WARN(enabled != crtc->base.enabled,
8149 "crtc's computed enabled state doesn't match tracked enabled state "
8150 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8152 memset(&pipe_config, 0, sizeof(pipe_config));
8153 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8154 active = dev_priv->display.get_pipe_config(crtc,
8156 WARN(crtc->active != active,
8157 "crtc active state doesn't match with hw state "
8158 "(expected %i, found %i)\n", crtc->active, active);
8161 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8162 "pipe state doesn't match!\n");
8166 static int __intel_set_mode(struct drm_crtc *crtc,
8167 struct drm_display_mode *mode,
8168 int x, int y, struct drm_framebuffer *fb)
8170 struct drm_device *dev = crtc->dev;
8171 drm_i915_private_t *dev_priv = dev->dev_private;
8172 struct drm_display_mode *saved_mode, *saved_hwmode;
8173 struct intel_crtc_config *pipe_config = NULL;
8174 struct intel_crtc *intel_crtc;
8175 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8178 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8181 saved_hwmode = saved_mode + 1;
8183 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8184 &prepare_pipes, &disable_pipes);
8186 *saved_hwmode = crtc->hwmode;
8187 *saved_mode = crtc->mode;
8189 /* Hack: Because we don't (yet) support global modeset on multiple
8190 * crtcs, we don't keep track of the new mode for more than one crtc.
8191 * Hence simply check whether any bit is set in modeset_pipes in all the
8192 * pieces of code that are not yet converted to deal with mutliple crtcs
8193 * changing their mode at the same time. */
8194 if (modeset_pipes) {
8195 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8196 if (IS_ERR(pipe_config)) {
8197 ret = PTR_ERR(pipe_config);
8204 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8205 intel_crtc_disable(&intel_crtc->base);
8207 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8208 if (intel_crtc->base.enabled)
8209 dev_priv->display.crtc_disable(&intel_crtc->base);
8212 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8213 * to set it here already despite that we pass it down the callchain.
8215 if (modeset_pipes) {
8216 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8218 /* mode_set/enable/disable functions rely on a correct pipe
8220 to_intel_crtc(crtc)->config = *pipe_config;
8221 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8224 /* Only after disabling all output pipelines that will be changed can we
8225 * update the the output configuration. */
8226 intel_modeset_update_state(dev, prepare_pipes);
8228 if (dev_priv->display.modeset_global_resources)
8229 dev_priv->display.modeset_global_resources(dev);
8231 /* Set up the DPLL and any encoders state that needs to adjust or depend
8234 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8235 ret = intel_crtc_mode_set(&intel_crtc->base,
8241 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8242 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8243 dev_priv->display.crtc_enable(&intel_crtc->base);
8245 if (modeset_pipes) {
8246 /* Store real post-adjustment hardware mode. */
8247 crtc->hwmode = pipe_config->adjusted_mode;
8249 /* Calculate and store various constants which
8250 * are later needed by vblank and swap-completion
8251 * timestamping. They are derived from true hwmode.
8253 drm_calc_timestamping_constants(crtc);
8256 /* FIXME: add subpixel order */
8258 if (ret && crtc->enabled) {
8259 crtc->hwmode = *saved_hwmode;
8260 crtc->mode = *saved_mode;
8269 int intel_set_mode(struct drm_crtc *crtc,
8270 struct drm_display_mode *mode,
8271 int x, int y, struct drm_framebuffer *fb)
8275 ret = __intel_set_mode(crtc, mode, x, y, fb);
8278 intel_modeset_check_state(crtc->dev);
8283 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8285 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8288 #undef for_each_intel_crtc_masked
8290 static void intel_set_config_free(struct intel_set_config *config)
8295 kfree(config->save_connector_encoders);
8296 kfree(config->save_encoder_crtcs);
8300 static int intel_set_config_save_state(struct drm_device *dev,
8301 struct intel_set_config *config)
8303 struct drm_encoder *encoder;
8304 struct drm_connector *connector;
8307 config->save_encoder_crtcs =
8308 kcalloc(dev->mode_config.num_encoder,
8309 sizeof(struct drm_crtc *), GFP_KERNEL);
8310 if (!config->save_encoder_crtcs)
8313 config->save_connector_encoders =
8314 kcalloc(dev->mode_config.num_connector,
8315 sizeof(struct drm_encoder *), GFP_KERNEL);
8316 if (!config->save_connector_encoders)
8319 /* Copy data. Note that driver private data is not affected.
8320 * Should anything bad happen only the expected state is
8321 * restored, not the drivers personal bookkeeping.
8324 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8325 config->save_encoder_crtcs[count++] = encoder->crtc;
8329 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8330 config->save_connector_encoders[count++] = connector->encoder;
8336 static void intel_set_config_restore_state(struct drm_device *dev,
8337 struct intel_set_config *config)
8339 struct intel_encoder *encoder;
8340 struct intel_connector *connector;
8344 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8346 to_intel_crtc(config->save_encoder_crtcs[count++]);
8350 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8351 connector->new_encoder =
8352 to_intel_encoder(config->save_connector_encoders[count++]);
8357 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8358 struct intel_set_config *config)
8361 /* We should be able to check here if the fb has the same properties
8362 * and then just flip_or_move it */
8363 if (set->crtc->fb != set->fb) {
8364 /* If we have no fb then treat it as a full mode set */
8365 if (set->crtc->fb == NULL) {
8366 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8367 config->mode_changed = true;
8368 } else if (set->fb == NULL) {
8369 config->mode_changed = true;
8370 } else if (set->fb->pixel_format !=
8371 set->crtc->fb->pixel_format) {
8372 config->mode_changed = true;
8374 config->fb_changed = true;
8377 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8378 config->fb_changed = true;
8380 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8381 DRM_DEBUG_KMS("modes are different, full mode set\n");
8382 drm_mode_debug_printmodeline(&set->crtc->mode);
8383 drm_mode_debug_printmodeline(set->mode);
8384 config->mode_changed = true;
8389 intel_modeset_stage_output_state(struct drm_device *dev,
8390 struct drm_mode_set *set,
8391 struct intel_set_config *config)
8393 struct drm_crtc *new_crtc;
8394 struct intel_connector *connector;
8395 struct intel_encoder *encoder;
8398 /* The upper layers ensure that we either disable a crtc or have a list
8399 * of connectors. For paranoia, double-check this. */
8400 WARN_ON(!set->fb && (set->num_connectors != 0));
8401 WARN_ON(set->fb && (set->num_connectors == 0));
8404 list_for_each_entry(connector, &dev->mode_config.connector_list,
8406 /* Otherwise traverse passed in connector list and get encoders
8408 for (ro = 0; ro < set->num_connectors; ro++) {
8409 if (set->connectors[ro] == &connector->base) {
8410 connector->new_encoder = connector->encoder;
8415 /* If we disable the crtc, disable all its connectors. Also, if
8416 * the connector is on the changing crtc but not on the new
8417 * connector list, disable it. */
8418 if ((!set->fb || ro == set->num_connectors) &&
8419 connector->base.encoder &&
8420 connector->base.encoder->crtc == set->crtc) {
8421 connector->new_encoder = NULL;
8423 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8424 connector->base.base.id,
8425 drm_get_connector_name(&connector->base));
8429 if (&connector->new_encoder->base != connector->base.encoder) {
8430 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8431 config->mode_changed = true;
8434 /* connector->new_encoder is now updated for all connectors. */
8436 /* Update crtc of enabled connectors. */
8438 list_for_each_entry(connector, &dev->mode_config.connector_list,
8440 if (!connector->new_encoder)
8443 new_crtc = connector->new_encoder->base.crtc;
8445 for (ro = 0; ro < set->num_connectors; ro++) {
8446 if (set->connectors[ro] == &connector->base)
8447 new_crtc = set->crtc;
8450 /* Make sure the new CRTC will work with the encoder */
8451 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8455 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8457 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8458 connector->base.base.id,
8459 drm_get_connector_name(&connector->base),
8463 /* Check for any encoders that needs to be disabled. */
8464 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8466 list_for_each_entry(connector,
8467 &dev->mode_config.connector_list,
8469 if (connector->new_encoder == encoder) {
8470 WARN_ON(!connector->new_encoder->new_crtc);
8475 encoder->new_crtc = NULL;
8477 /* Only now check for crtc changes so we don't miss encoders
8478 * that will be disabled. */
8479 if (&encoder->new_crtc->base != encoder->base.crtc) {
8480 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8481 config->mode_changed = true;
8484 /* Now we've also updated encoder->new_crtc for all encoders. */
8489 static int intel_crtc_set_config(struct drm_mode_set *set)
8491 struct drm_device *dev;
8492 struct drm_mode_set save_set;
8493 struct intel_set_config *config;
8498 BUG_ON(!set->crtc->helper_private);
8500 /* Enforce sane interface api - has been abused by the fb helper. */
8501 BUG_ON(!set->mode && set->fb);
8502 BUG_ON(set->fb && set->num_connectors == 0);
8505 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8506 set->crtc->base.id, set->fb->base.id,
8507 (int)set->num_connectors, set->x, set->y);
8509 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8512 dev = set->crtc->dev;
8515 config = kzalloc(sizeof(*config), GFP_KERNEL);
8519 ret = intel_set_config_save_state(dev, config);
8523 save_set.crtc = set->crtc;
8524 save_set.mode = &set->crtc->mode;
8525 save_set.x = set->crtc->x;
8526 save_set.y = set->crtc->y;
8527 save_set.fb = set->crtc->fb;
8529 /* Compute whether we need a full modeset, only an fb base update or no
8530 * change at all. In the future we might also check whether only the
8531 * mode changed, e.g. for LVDS where we only change the panel fitter in
8533 intel_set_config_compute_mode_changes(set, config);
8535 ret = intel_modeset_stage_output_state(dev, set, config);
8539 if (config->mode_changed) {
8541 DRM_DEBUG_KMS("attempting to set mode from"
8543 drm_mode_debug_printmodeline(set->mode);
8546 ret = intel_set_mode(set->crtc, set->mode,
8547 set->x, set->y, set->fb);
8549 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8550 set->crtc->base.id, ret);
8553 } else if (config->fb_changed) {
8554 intel_crtc_wait_for_pending_flips(set->crtc);
8556 ret = intel_pipe_set_base(set->crtc,
8557 set->x, set->y, set->fb);
8560 intel_set_config_free(config);
8565 intel_set_config_restore_state(dev, config);
8567 /* Try to restore the config */
8568 if (config->mode_changed &&
8569 intel_set_mode(save_set.crtc, save_set.mode,
8570 save_set.x, save_set.y, save_set.fb))
8571 DRM_ERROR("failed to restore config after modeset failure\n");
8574 intel_set_config_free(config);
8578 static const struct drm_crtc_funcs intel_crtc_funcs = {
8579 .cursor_set = intel_crtc_cursor_set,
8580 .cursor_move = intel_crtc_cursor_move,
8581 .gamma_set = intel_crtc_gamma_set,
8582 .set_config = intel_crtc_set_config,
8583 .destroy = intel_crtc_destroy,
8584 .page_flip = intel_crtc_page_flip,
8587 static void intel_cpu_pll_init(struct drm_device *dev)
8590 intel_ddi_pll_init(dev);
8593 static void intel_pch_pll_init(struct drm_device *dev)
8595 drm_i915_private_t *dev_priv = dev->dev_private;
8598 if (dev_priv->num_pch_pll == 0) {
8599 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8603 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8604 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8605 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8606 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8610 static void intel_crtc_init(struct drm_device *dev, int pipe)
8612 drm_i915_private_t *dev_priv = dev->dev_private;
8613 struct intel_crtc *intel_crtc;
8616 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8617 if (intel_crtc == NULL)
8620 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8622 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8623 for (i = 0; i < 256; i++) {
8624 intel_crtc->lut_r[i] = i;
8625 intel_crtc->lut_g[i] = i;
8626 intel_crtc->lut_b[i] = i;
8629 /* Swap pipes & planes for FBC on pre-965 */
8630 intel_crtc->pipe = pipe;
8631 intel_crtc->plane = pipe;
8632 intel_crtc->config.cpu_transcoder = pipe;
8633 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8634 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8635 intel_crtc->plane = !pipe;
8638 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8639 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8640 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8641 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8643 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8646 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8647 struct drm_file *file)
8649 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8650 struct drm_mode_object *drmmode_obj;
8651 struct intel_crtc *crtc;
8653 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8656 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8657 DRM_MODE_OBJECT_CRTC);
8660 DRM_ERROR("no such CRTC id\n");
8664 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8665 pipe_from_crtc_id->pipe = crtc->pipe;
8670 static int intel_encoder_clones(struct intel_encoder *encoder)
8672 struct drm_device *dev = encoder->base.dev;
8673 struct intel_encoder *source_encoder;
8677 list_for_each_entry(source_encoder,
8678 &dev->mode_config.encoder_list, base.head) {
8680 if (encoder == source_encoder)
8681 index_mask |= (1 << entry);
8683 /* Intel hw has only one MUX where enocoders could be cloned. */
8684 if (encoder->cloneable && source_encoder->cloneable)
8685 index_mask |= (1 << entry);
8693 static bool has_edp_a(struct drm_device *dev)
8695 struct drm_i915_private *dev_priv = dev->dev_private;
8697 if (!IS_MOBILE(dev))
8700 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8704 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8710 static void intel_setup_outputs(struct drm_device *dev)
8712 struct drm_i915_private *dev_priv = dev->dev_private;
8713 struct intel_encoder *encoder;
8714 bool dpd_is_edp = false;
8717 has_lvds = intel_lvds_init(dev);
8718 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8719 /* disable the panel fitter on everything but LVDS */
8720 I915_WRITE(PFIT_CONTROL, 0);
8724 intel_crt_init(dev);
8729 /* Haswell uses DDI functions to detect digital outputs */
8730 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8731 /* DDI A only supports eDP */
8733 intel_ddi_init(dev, PORT_A);
8735 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8737 found = I915_READ(SFUSE_STRAP);
8739 if (found & SFUSE_STRAP_DDIB_DETECTED)
8740 intel_ddi_init(dev, PORT_B);
8741 if (found & SFUSE_STRAP_DDIC_DETECTED)
8742 intel_ddi_init(dev, PORT_C);
8743 if (found & SFUSE_STRAP_DDID_DETECTED)
8744 intel_ddi_init(dev, PORT_D);
8745 } else if (HAS_PCH_SPLIT(dev)) {
8747 dpd_is_edp = intel_dpd_is_edp(dev);
8750 intel_dp_init(dev, DP_A, PORT_A);
8752 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8753 /* PCH SDVOB multiplex with HDMIB */
8754 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8756 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8757 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8758 intel_dp_init(dev, PCH_DP_B, PORT_B);
8761 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8762 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8764 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8765 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8767 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8768 intel_dp_init(dev, PCH_DP_C, PORT_C);
8770 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8771 intel_dp_init(dev, PCH_DP_D, PORT_D);
8772 } else if (IS_VALLEYVIEW(dev)) {
8773 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8774 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8775 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8777 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8778 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8780 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8781 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8783 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8786 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8787 DRM_DEBUG_KMS("probing SDVOB\n");
8788 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8789 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8790 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8791 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8794 if (!found && SUPPORTS_INTEGRATED_DP(dev))
8795 intel_dp_init(dev, DP_B, PORT_B);
8798 /* Before G4X SDVOC doesn't have its own detect register */
8800 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8801 DRM_DEBUG_KMS("probing SDVOC\n");
8802 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8805 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8807 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8808 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8809 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8811 if (SUPPORTS_INTEGRATED_DP(dev))
8812 intel_dp_init(dev, DP_C, PORT_C);
8815 if (SUPPORTS_INTEGRATED_DP(dev) &&
8816 (I915_READ(DP_D) & DP_DETECTED))
8817 intel_dp_init(dev, DP_D, PORT_D);
8818 } else if (IS_GEN2(dev))
8819 intel_dvo_init(dev);
8821 if (SUPPORTS_TV(dev))
8824 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8825 encoder->base.possible_crtcs = encoder->crtc_mask;
8826 encoder->base.possible_clones =
8827 intel_encoder_clones(encoder);
8830 intel_init_pch_refclk(dev);
8832 drm_helper_move_panel_connectors_to_head(dev);
8835 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8837 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8839 drm_framebuffer_cleanup(fb);
8840 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8845 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8846 struct drm_file *file,
8847 unsigned int *handle)
8849 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8850 struct drm_i915_gem_object *obj = intel_fb->obj;
8852 return drm_gem_handle_create(file, &obj->base, handle);
8855 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8856 .destroy = intel_user_framebuffer_destroy,
8857 .create_handle = intel_user_framebuffer_create_handle,
8860 int intel_framebuffer_init(struct drm_device *dev,
8861 struct intel_framebuffer *intel_fb,
8862 struct drm_mode_fb_cmd2 *mode_cmd,
8863 struct drm_i915_gem_object *obj)
8867 if (obj->tiling_mode == I915_TILING_Y) {
8868 DRM_DEBUG("hardware does not support tiling Y\n");
8872 if (mode_cmd->pitches[0] & 63) {
8873 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8874 mode_cmd->pitches[0]);
8878 /* FIXME <= Gen4 stride limits are bit unclear */
8879 if (mode_cmd->pitches[0] > 32768) {
8880 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8881 mode_cmd->pitches[0]);
8885 if (obj->tiling_mode != I915_TILING_NONE &&
8886 mode_cmd->pitches[0] != obj->stride) {
8887 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8888 mode_cmd->pitches[0], obj->stride);
8892 /* Reject formats not supported by any plane early. */
8893 switch (mode_cmd->pixel_format) {
8895 case DRM_FORMAT_RGB565:
8896 case DRM_FORMAT_XRGB8888:
8897 case DRM_FORMAT_ARGB8888:
8899 case DRM_FORMAT_XRGB1555:
8900 case DRM_FORMAT_ARGB1555:
8901 if (INTEL_INFO(dev)->gen > 3) {
8902 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8906 case DRM_FORMAT_XBGR8888:
8907 case DRM_FORMAT_ABGR8888:
8908 case DRM_FORMAT_XRGB2101010:
8909 case DRM_FORMAT_ARGB2101010:
8910 case DRM_FORMAT_XBGR2101010:
8911 case DRM_FORMAT_ABGR2101010:
8912 if (INTEL_INFO(dev)->gen < 4) {
8913 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8917 case DRM_FORMAT_YUYV:
8918 case DRM_FORMAT_UYVY:
8919 case DRM_FORMAT_YVYU:
8920 case DRM_FORMAT_VYUY:
8921 if (INTEL_INFO(dev)->gen < 5) {
8922 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8927 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8931 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8932 if (mode_cmd->offsets[0] != 0)
8935 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8936 intel_fb->obj = obj;
8938 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8940 DRM_ERROR("framebuffer init failed %d\n", ret);
8947 static struct drm_framebuffer *
8948 intel_user_framebuffer_create(struct drm_device *dev,
8949 struct drm_file *filp,
8950 struct drm_mode_fb_cmd2 *mode_cmd)
8952 struct drm_i915_gem_object *obj;
8954 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8955 mode_cmd->handles[0]));
8956 if (&obj->base == NULL)
8957 return ERR_PTR(-ENOENT);
8959 return intel_framebuffer_create(dev, mode_cmd, obj);
8962 static const struct drm_mode_config_funcs intel_mode_funcs = {
8963 .fb_create = intel_user_framebuffer_create,
8964 .output_poll_changed = intel_fb_output_poll_changed,
8967 /* Set up chip specific display functions */
8968 static void intel_init_display(struct drm_device *dev)
8970 struct drm_i915_private *dev_priv = dev->dev_private;
8973 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8974 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8975 dev_priv->display.crtc_enable = haswell_crtc_enable;
8976 dev_priv->display.crtc_disable = haswell_crtc_disable;
8977 dev_priv->display.off = haswell_crtc_off;
8978 dev_priv->display.update_plane = ironlake_update_plane;
8979 } else if (HAS_PCH_SPLIT(dev)) {
8980 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8981 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8982 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8983 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8984 dev_priv->display.off = ironlake_crtc_off;
8985 dev_priv->display.update_plane = ironlake_update_plane;
8986 } else if (IS_VALLEYVIEW(dev)) {
8987 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8988 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8989 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8990 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8991 dev_priv->display.off = i9xx_crtc_off;
8992 dev_priv->display.update_plane = i9xx_update_plane;
8994 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8995 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8996 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8997 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8998 dev_priv->display.off = i9xx_crtc_off;
8999 dev_priv->display.update_plane = i9xx_update_plane;
9002 /* Returns the core display clock speed */
9003 if (IS_VALLEYVIEW(dev))
9004 dev_priv->display.get_display_clock_speed =
9005 valleyview_get_display_clock_speed;
9006 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9007 dev_priv->display.get_display_clock_speed =
9008 i945_get_display_clock_speed;
9009 else if (IS_I915G(dev))
9010 dev_priv->display.get_display_clock_speed =
9011 i915_get_display_clock_speed;
9012 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9013 dev_priv->display.get_display_clock_speed =
9014 i9xx_misc_get_display_clock_speed;
9015 else if (IS_I915GM(dev))
9016 dev_priv->display.get_display_clock_speed =
9017 i915gm_get_display_clock_speed;
9018 else if (IS_I865G(dev))
9019 dev_priv->display.get_display_clock_speed =
9020 i865_get_display_clock_speed;
9021 else if (IS_I85X(dev))
9022 dev_priv->display.get_display_clock_speed =
9023 i855_get_display_clock_speed;
9025 dev_priv->display.get_display_clock_speed =
9026 i830_get_display_clock_speed;
9028 if (HAS_PCH_SPLIT(dev)) {
9030 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9031 dev_priv->display.write_eld = ironlake_write_eld;
9032 } else if (IS_GEN6(dev)) {
9033 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9034 dev_priv->display.write_eld = ironlake_write_eld;
9035 } else if (IS_IVYBRIDGE(dev)) {
9036 /* FIXME: detect B0+ stepping and use auto training */
9037 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9038 dev_priv->display.write_eld = ironlake_write_eld;
9039 dev_priv->display.modeset_global_resources =
9040 ivb_modeset_global_resources;
9041 } else if (IS_HASWELL(dev)) {
9042 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9043 dev_priv->display.write_eld = haswell_write_eld;
9044 dev_priv->display.modeset_global_resources =
9045 haswell_modeset_global_resources;
9047 } else if (IS_G4X(dev)) {
9048 dev_priv->display.write_eld = g4x_write_eld;
9051 /* Default just returns -ENODEV to indicate unsupported */
9052 dev_priv->display.queue_flip = intel_default_queue_flip;
9054 switch (INTEL_INFO(dev)->gen) {
9056 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9060 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9065 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9069 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9072 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9078 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9079 * resume, or other times. This quirk makes sure that's the case for
9082 static void quirk_pipea_force(struct drm_device *dev)
9084 struct drm_i915_private *dev_priv = dev->dev_private;
9086 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9087 DRM_INFO("applying pipe a force quirk\n");
9091 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9093 static void quirk_ssc_force_disable(struct drm_device *dev)
9095 struct drm_i915_private *dev_priv = dev->dev_private;
9096 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9097 DRM_INFO("applying lvds SSC disable quirk\n");
9101 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9104 static void quirk_invert_brightness(struct drm_device *dev)
9106 struct drm_i915_private *dev_priv = dev->dev_private;
9107 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9108 DRM_INFO("applying inverted panel brightness quirk\n");
9111 struct intel_quirk {
9113 int subsystem_vendor;
9114 int subsystem_device;
9115 void (*hook)(struct drm_device *dev);
9118 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9119 struct intel_dmi_quirk {
9120 void (*hook)(struct drm_device *dev);
9121 const struct dmi_system_id (*dmi_id_list)[];
9124 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9126 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9130 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9132 .dmi_id_list = &(const struct dmi_system_id[]) {
9134 .callback = intel_dmi_reverse_brightness,
9135 .ident = "NCR Corporation",
9136 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9137 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9140 { } /* terminating entry */
9142 .hook = quirk_invert_brightness,
9146 static struct intel_quirk intel_quirks[] = {
9147 /* HP Mini needs pipe A force quirk (LP: #322104) */
9148 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9150 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9151 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9153 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9154 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9156 /* 830/845 need to leave pipe A & dpll A up */
9157 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9158 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9160 /* Lenovo U160 cannot use SSC on LVDS */
9161 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9163 /* Sony Vaio Y cannot use SSC on LVDS */
9164 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9166 /* Acer Aspire 5734Z must invert backlight brightness */
9167 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9169 /* Acer/eMachines G725 */
9170 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9172 /* Acer/eMachines e725 */
9173 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9175 /* Acer/Packard Bell NCL20 */
9176 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9178 /* Acer Aspire 4736Z */
9179 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9182 static void intel_init_quirks(struct drm_device *dev)
9184 struct pci_dev *d = dev->pdev;
9187 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9188 struct intel_quirk *q = &intel_quirks[i];
9190 if (d->device == q->device &&
9191 (d->subsystem_vendor == q->subsystem_vendor ||
9192 q->subsystem_vendor == PCI_ANY_ID) &&
9193 (d->subsystem_device == q->subsystem_device ||
9194 q->subsystem_device == PCI_ANY_ID))
9197 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9198 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9199 intel_dmi_quirks[i].hook(dev);
9203 /* Disable the VGA plane that we never use */
9204 static void i915_disable_vga(struct drm_device *dev)
9206 struct drm_i915_private *dev_priv = dev->dev_private;
9208 u32 vga_reg = i915_vgacntrl_reg(dev);
9210 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9211 outb(SR01, VGA_SR_INDEX);
9212 sr1 = inb(VGA_SR_DATA);
9213 outb(sr1 | 1<<5, VGA_SR_DATA);
9214 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9217 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9218 POSTING_READ(vga_reg);
9221 void intel_modeset_init_hw(struct drm_device *dev)
9223 intel_init_power_well(dev);
9225 intel_prepare_ddi(dev);
9227 intel_init_clock_gating(dev);
9229 mutex_lock(&dev->struct_mutex);
9230 intel_enable_gt_powersave(dev);
9231 mutex_unlock(&dev->struct_mutex);
9234 void intel_modeset_suspend_hw(struct drm_device *dev)
9236 intel_suspend_hw(dev);
9239 void intel_modeset_init(struct drm_device *dev)
9241 struct drm_i915_private *dev_priv = dev->dev_private;
9244 drm_mode_config_init(dev);
9246 dev->mode_config.min_width = 0;
9247 dev->mode_config.min_height = 0;
9249 dev->mode_config.preferred_depth = 24;
9250 dev->mode_config.prefer_shadow = 1;
9252 dev->mode_config.funcs = &intel_mode_funcs;
9254 intel_init_quirks(dev);
9258 if (INTEL_INFO(dev)->num_pipes == 0)
9261 intel_init_display(dev);
9264 dev->mode_config.max_width = 2048;
9265 dev->mode_config.max_height = 2048;
9266 } else if (IS_GEN3(dev)) {
9267 dev->mode_config.max_width = 4096;
9268 dev->mode_config.max_height = 4096;
9270 dev->mode_config.max_width = 8192;
9271 dev->mode_config.max_height = 8192;
9273 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9275 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9276 INTEL_INFO(dev)->num_pipes,
9277 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9279 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9280 intel_crtc_init(dev, i);
9281 for (j = 0; j < dev_priv->num_plane; j++) {
9282 ret = intel_plane_init(dev, i, j);
9284 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9285 pipe_name(i), sprite_name(i, j), ret);
9289 intel_cpu_pll_init(dev);
9290 intel_pch_pll_init(dev);
9292 /* Just disable it once at startup */
9293 i915_disable_vga(dev);
9294 intel_setup_outputs(dev);
9296 /* Just in case the BIOS is doing something questionable. */
9297 intel_disable_fbc(dev);
9301 intel_connector_break_all_links(struct intel_connector *connector)
9303 connector->base.dpms = DRM_MODE_DPMS_OFF;
9304 connector->base.encoder = NULL;
9305 connector->encoder->connectors_active = false;
9306 connector->encoder->base.crtc = NULL;
9309 static void intel_enable_pipe_a(struct drm_device *dev)
9311 struct intel_connector *connector;
9312 struct drm_connector *crt = NULL;
9313 struct intel_load_detect_pipe load_detect_temp;
9315 /* We can't just switch on the pipe A, we need to set things up with a
9316 * proper mode and output configuration. As a gross hack, enable pipe A
9317 * by enabling the load detect pipe once. */
9318 list_for_each_entry(connector,
9319 &dev->mode_config.connector_list,
9321 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9322 crt = &connector->base;
9330 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9331 intel_release_load_detect_pipe(crt, &load_detect_temp);
9337 intel_check_plane_mapping(struct intel_crtc *crtc)
9339 struct drm_device *dev = crtc->base.dev;
9340 struct drm_i915_private *dev_priv = dev->dev_private;
9343 if (INTEL_INFO(dev)->num_pipes == 1)
9346 reg = DSPCNTR(!crtc->plane);
9347 val = I915_READ(reg);
9349 if ((val & DISPLAY_PLANE_ENABLE) &&
9350 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9356 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9358 struct drm_device *dev = crtc->base.dev;
9359 struct drm_i915_private *dev_priv = dev->dev_private;
9362 /* Clear any frame start delays used for debugging left by the BIOS */
9363 reg = PIPECONF(crtc->config.cpu_transcoder);
9364 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9366 /* We need to sanitize the plane -> pipe mapping first because this will
9367 * disable the crtc (and hence change the state) if it is wrong. Note
9368 * that gen4+ has a fixed plane -> pipe mapping. */
9369 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9370 struct intel_connector *connector;
9373 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9374 crtc->base.base.id);
9376 /* Pipe has the wrong plane attached and the plane is active.
9377 * Temporarily change the plane mapping and disable everything
9379 plane = crtc->plane;
9380 crtc->plane = !plane;
9381 dev_priv->display.crtc_disable(&crtc->base);
9382 crtc->plane = plane;
9384 /* ... and break all links. */
9385 list_for_each_entry(connector, &dev->mode_config.connector_list,
9387 if (connector->encoder->base.crtc != &crtc->base)
9390 intel_connector_break_all_links(connector);
9393 WARN_ON(crtc->active);
9394 crtc->base.enabled = false;
9397 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9398 crtc->pipe == PIPE_A && !crtc->active) {
9399 /* BIOS forgot to enable pipe A, this mostly happens after
9400 * resume. Force-enable the pipe to fix this, the update_dpms
9401 * call below we restore the pipe to the right state, but leave
9402 * the required bits on. */
9403 intel_enable_pipe_a(dev);
9406 /* Adjust the state of the output pipe according to whether we
9407 * have active connectors/encoders. */
9408 intel_crtc_update_dpms(&crtc->base);
9410 if (crtc->active != crtc->base.enabled) {
9411 struct intel_encoder *encoder;
9413 /* This can happen either due to bugs in the get_hw_state
9414 * functions or because the pipe is force-enabled due to the
9416 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9418 crtc->base.enabled ? "enabled" : "disabled",
9419 crtc->active ? "enabled" : "disabled");
9421 crtc->base.enabled = crtc->active;
9423 /* Because we only establish the connector -> encoder ->
9424 * crtc links if something is active, this means the
9425 * crtc is now deactivated. Break the links. connector
9426 * -> encoder links are only establish when things are
9427 * actually up, hence no need to break them. */
9428 WARN_ON(crtc->active);
9430 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9431 WARN_ON(encoder->connectors_active);
9432 encoder->base.crtc = NULL;
9437 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9439 struct intel_connector *connector;
9440 struct drm_device *dev = encoder->base.dev;
9442 /* We need to check both for a crtc link (meaning that the
9443 * encoder is active and trying to read from a pipe) and the
9444 * pipe itself being active. */
9445 bool has_active_crtc = encoder->base.crtc &&
9446 to_intel_crtc(encoder->base.crtc)->active;
9448 if (encoder->connectors_active && !has_active_crtc) {
9449 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9450 encoder->base.base.id,
9451 drm_get_encoder_name(&encoder->base));
9453 /* Connector is active, but has no active pipe. This is
9454 * fallout from our resume register restoring. Disable
9455 * the encoder manually again. */
9456 if (encoder->base.crtc) {
9457 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9458 encoder->base.base.id,
9459 drm_get_encoder_name(&encoder->base));
9460 encoder->disable(encoder);
9463 /* Inconsistent output/port/pipe state happens presumably due to
9464 * a bug in one of the get_hw_state functions. Or someplace else
9465 * in our code, like the register restore mess on resume. Clamp
9466 * things to off as a safer default. */
9467 list_for_each_entry(connector,
9468 &dev->mode_config.connector_list,
9470 if (connector->encoder != encoder)
9473 intel_connector_break_all_links(connector);
9476 /* Enabled encoders without active connectors will be fixed in
9477 * the crtc fixup. */
9480 void i915_redisable_vga(struct drm_device *dev)
9482 struct drm_i915_private *dev_priv = dev->dev_private;
9483 u32 vga_reg = i915_vgacntrl_reg(dev);
9485 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9486 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9487 i915_disable_vga(dev);
9491 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9492 * and i915 state tracking structures. */
9493 void intel_modeset_setup_hw_state(struct drm_device *dev,
9496 struct drm_i915_private *dev_priv = dev->dev_private;
9499 struct drm_plane *plane;
9500 struct intel_crtc *crtc;
9501 struct intel_encoder *encoder;
9502 struct intel_connector *connector;
9505 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9507 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9508 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9509 case TRANS_DDI_EDP_INPUT_A_ON:
9510 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9513 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9516 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9520 /* A bogus value has been programmed, disable
9522 WARN(1, "Bogus eDP source %08x\n", tmp);
9523 intel_ddi_disable_transcoder_func(dev_priv,
9528 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9529 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9531 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9537 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9539 enum transcoder tmp = crtc->config.cpu_transcoder;
9540 memset(&crtc->config, 0, sizeof(crtc->config));
9541 crtc->config.cpu_transcoder = tmp;
9543 crtc->active = dev_priv->display.get_pipe_config(crtc,
9546 crtc->base.enabled = crtc->active;
9548 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9550 crtc->active ? "enabled" : "disabled");
9554 intel_ddi_setup_hw_pll_state(dev);
9556 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9560 if (encoder->get_hw_state(encoder, &pipe)) {
9561 encoder->base.crtc =
9562 dev_priv->pipe_to_crtc_mapping[pipe];
9564 encoder->base.crtc = NULL;
9567 encoder->connectors_active = false;
9568 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9569 encoder->base.base.id,
9570 drm_get_encoder_name(&encoder->base),
9571 encoder->base.crtc ? "enabled" : "disabled",
9575 list_for_each_entry(connector, &dev->mode_config.connector_list,
9577 if (connector->get_hw_state(connector)) {
9578 connector->base.dpms = DRM_MODE_DPMS_ON;
9579 connector->encoder->connectors_active = true;
9580 connector->base.encoder = &connector->encoder->base;
9582 connector->base.dpms = DRM_MODE_DPMS_OFF;
9583 connector->base.encoder = NULL;
9585 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9586 connector->base.base.id,
9587 drm_get_connector_name(&connector->base),
9588 connector->base.encoder ? "enabled" : "disabled");
9591 /* HW state is read out, now we need to sanitize this mess. */
9592 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9594 intel_sanitize_encoder(encoder);
9597 for_each_pipe(pipe) {
9598 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9599 intel_sanitize_crtc(crtc);
9602 if (force_restore) {
9604 * We need to use raw interfaces for restoring state to avoid
9605 * checking (bogus) intermediate states.
9607 for_each_pipe(pipe) {
9608 struct drm_crtc *crtc =
9609 dev_priv->pipe_to_crtc_mapping[pipe];
9611 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9614 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9615 intel_plane_restore(plane);
9617 i915_redisable_vga(dev);
9619 intel_modeset_update_staged_output_state(dev);
9622 intel_modeset_check_state(dev);
9624 drm_mode_config_reset(dev);
9627 void intel_modeset_gem_init(struct drm_device *dev)
9629 intel_modeset_init_hw(dev);
9631 intel_setup_overlay(dev);
9633 intel_modeset_setup_hw_state(dev, false);
9636 void intel_modeset_cleanup(struct drm_device *dev)
9638 struct drm_i915_private *dev_priv = dev->dev_private;
9639 struct drm_crtc *crtc;
9640 struct intel_crtc *intel_crtc;
9643 * Interrupts and polling as the first thing to avoid creating havoc.
9644 * Too much stuff here (turning of rps, connectors, ...) would
9645 * experience fancy races otherwise.
9647 drm_irq_uninstall(dev);
9648 cancel_work_sync(&dev_priv->hotplug_work);
9650 * Due to the hpd irq storm handling the hotplug work can re-arm the
9651 * poll handlers. Hence disable polling after hpd handling is shut down.
9653 drm_kms_helper_poll_fini(dev);
9655 mutex_lock(&dev->struct_mutex);
9657 intel_unregister_dsm_handler();
9659 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9660 /* Skip inactive CRTCs */
9664 intel_crtc = to_intel_crtc(crtc);
9665 intel_increase_pllclock(crtc);
9668 intel_disable_fbc(dev);
9670 intel_disable_gt_powersave(dev);
9672 ironlake_teardown_rc6(dev);
9674 mutex_unlock(&dev->struct_mutex);
9676 /* flush any delayed tasks or pending work */
9677 flush_scheduled_work();
9679 /* destroy backlight, if any, before the connectors */
9680 intel_panel_destroy_backlight(dev);
9682 drm_mode_config_cleanup(dev);
9684 intel_cleanup_overlay(dev);
9688 * Return which encoder is currently attached for connector.
9690 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9692 return &intel_attached_encoder(connector)->base;
9695 void intel_connector_attach_encoder(struct intel_connector *connector,
9696 struct intel_encoder *encoder)
9698 connector->encoder = encoder;
9699 drm_mode_connector_attach_encoder(&connector->base,
9704 * set vga decode state - true == enable VGA decode
9706 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9708 struct drm_i915_private *dev_priv = dev->dev_private;
9711 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9713 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9715 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9716 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9720 #ifdef CONFIG_DEBUG_FS
9721 #include <linux/seq_file.h>
9723 struct intel_display_error_state {
9725 u32 power_well_driver;
9727 struct intel_cursor_error_state {
9732 } cursor[I915_MAX_PIPES];
9734 struct intel_pipe_error_state {
9735 enum transcoder cpu_transcoder;
9745 } pipe[I915_MAX_PIPES];
9747 struct intel_plane_error_state {
9755 } plane[I915_MAX_PIPES];
9758 struct intel_display_error_state *
9759 intel_display_capture_error_state(struct drm_device *dev)
9761 drm_i915_private_t *dev_priv = dev->dev_private;
9762 struct intel_display_error_state *error;
9763 enum transcoder cpu_transcoder;
9766 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9770 if (HAS_POWER_WELL(dev))
9771 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9774 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9775 error->pipe[i].cpu_transcoder = cpu_transcoder;
9777 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9778 error->cursor[i].control = I915_READ(CURCNTR(i));
9779 error->cursor[i].position = I915_READ(CURPOS(i));
9780 error->cursor[i].base = I915_READ(CURBASE(i));
9782 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9783 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9784 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9787 error->plane[i].control = I915_READ(DSPCNTR(i));
9788 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9789 if (INTEL_INFO(dev)->gen <= 3) {
9790 error->plane[i].size = I915_READ(DSPSIZE(i));
9791 error->plane[i].pos = I915_READ(DSPPOS(i));
9793 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9794 error->plane[i].addr = I915_READ(DSPADDR(i));
9795 if (INTEL_INFO(dev)->gen >= 4) {
9796 error->plane[i].surface = I915_READ(DSPSURF(i));
9797 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9800 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9801 error->pipe[i].source = I915_READ(PIPESRC(i));
9802 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9803 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9804 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9805 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9806 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9807 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9810 /* In the code above we read the registers without checking if the power
9811 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9812 * prevent the next I915_WRITE from detecting it and printing an error
9814 if (HAS_POWER_WELL(dev))
9815 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9821 intel_display_print_error_state(struct seq_file *m,
9822 struct drm_device *dev,
9823 struct intel_display_error_state *error)
9827 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9828 if (HAS_POWER_WELL(dev))
9829 seq_printf(m, "PWR_WELL_CTL2: %08x\n",
9830 error->power_well_driver);
9832 seq_printf(m, "Pipe [%d]:\n", i);
9833 seq_printf(m, " CPU transcoder: %c\n",
9834 transcoder_name(error->pipe[i].cpu_transcoder));
9835 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9836 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9837 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9838 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9839 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9840 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9841 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9842 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9844 seq_printf(m, "Plane [%d]:\n", i);
9845 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9846 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9847 if (INTEL_INFO(dev)->gen <= 3) {
9848 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9849 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9851 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9852 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9853 if (INTEL_INFO(dev)->gen >= 4) {
9854 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9855 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9858 seq_printf(m, "Cursor [%d]:\n", i);
9859 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9860 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9861 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);