drivers/gpu/drm/radeon/cik.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "cikd.h"
  32 #include "atom.h"
  33
  34 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  35 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  36
  37 /*
  38  * Core functions
  39  */
  40 /**
  41  * cik_tiling_mode_table_init - init the hw tiling table
  42  *
  43  * @rdev: radeon_device pointer
  44  *
  45  * Starting with SI, the tiling setup is done globally in a
  46  * set of 32 tiling modes.  Rather than selecting each set of
  47  * parameters per surface as on older asics, we just select
  48  * which index in the tiling table we want to use, and the
  49  * surface uses those parameters (CIK).
  50  */
  51 static void cik_tiling_mode_table_init(struct radeon_device *rdev)
  52 {
  53         const u32 num_tile_mode_states = 32;
  54         const u32 num_secondary_tile_mode_states = 16;
  55         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
  56         u32 num_pipe_configs;
  57         u32 num_rbs = rdev->config.cik.max_backends_per_se *
  58                 rdev->config.cik.max_shader_engines;
  59
  60         switch (rdev->config.cik.mem_row_size_in_kb) {
  61         case 1:
  62                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
  63                 break;
  64         case 2:
  65         default:
  66                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
  67                 break;
  68         case 4:
  69                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
  70                 break;
  71         }
  72
  73         num_pipe_configs = rdev->config.cik.max_tile_pipes;
  74         if (num_pipe_configs > 8)
  75                 num_pipe_configs = 8; /* ??? */
  76
  77         if (num_pipe_configs == 8) {
  78                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
  79                         switch (reg_offset) {
  80                         case 0:
  81                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  82                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
  83                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  84                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
  85                                 break;
  86                         case 1:
  87                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  88                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
  89                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  90                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
  91                                 break;
  92                         case 2:
  93                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  94                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
  95                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  96                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
  97                                 break;
  98                         case 3:
  99                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 100                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 101                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 102                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 103                                 break;
 104                         case 4:
 105                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 106                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 107                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 108                                                  TILE_SPLIT(split_equal_to_row_size));
 109                                 break;
 110                         case 5:
 111                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 112                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 113                                 break;
 114                         case 6:
 115                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 116                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 117                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 118                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 119                                 break;
 120                         case 7:
 121                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 122                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 123                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 124                                                  TILE_SPLIT(split_equal_to_row_size));
 125                                 break;
 126                         case 8:
 127                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 128                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
 129                                 break;
 130                         case 9:
 131                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 132                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 133                                 break;
 134                         case 10:
 135                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 136                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 137                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 138                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 139                                 break;
 140                         case 11:
 141                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 142                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 143                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 144                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 145                                 break;
 146                         case 12:
 147                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 148                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 149                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 150                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 151                                 break;
 152                         case 13:
 153                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 154                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 155                                 break;
 156                         case 14:
 157                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 158                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 159                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 160                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 161                                 break;
 162                         case 16:
 163                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 164                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 165                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 166                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 167                                 break;
 168                         case 17:
 169                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 170                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 171                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 172                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 173                                 break;
 174                         case 27:
 175                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 176                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 177                                 break;
 178                         case 28:
 179                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 180                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 181                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 182                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 183                                 break;
 184                         case 29:
 185                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 186                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 187                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 188                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 189                                 break;
 190                         case 30:
 191                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 192                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 193                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 194                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 195                                 break;
 196                         default:
 197                                 gb_tile_moden = 0;
 198                                 break;
 199                         }
 200                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 201                 }
 202                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
 203                         switch (reg_offset) {
 204                         case 0:
 205                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 206                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 207                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 208                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 209                                 break;
 210                         case 1:
 211                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 212                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 213                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 214                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 215                                 break;
 216                         case 2:
 217                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 218                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 219                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 220                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 221                                 break;
 222                         case 3:
 223                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 224                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 225                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 226                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 227                                 break;
 228                         case 4:
 229                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 230                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 231                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 232                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 233                                 break;
 234                         case 5:
 235                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 236                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 237                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 238                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 239                                 break;
 240                         case 6:
 241                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 242                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 243                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 244                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 245                                 break;
 246                         case 8:
 247                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 248                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
 249                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 250                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 251                                 break;
 252                         case 9:
 253                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 254                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 255                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 256                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 257                                 break;
 258                         case 10:
 259                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 260                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 261                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 262                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 263                                 break;
 264                         case 11:
 265                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 266                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 267                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 268                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 269                                 break;
 270                         case 12:
 271                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 272                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 273                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 274                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 275                                 break;
 276                         case 13:
 277                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 278                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 279                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 280                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 281                                 break;
 282                         case 14:
 283                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 284                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 285                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 286                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 287                                 break;
 288                         default:
 289                                 gb_tile_moden = 0;
 290                                 break;
 291                         }
 292                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 293                 }
 294         } else if (num_pipe_configs == 4) {
 295                 if (num_rbs == 4) {
 296                         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 297                                 switch (reg_offset) {
 298                                 case 0:
 299                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 300                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 301                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 302                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 303                                         break;
 304                                 case 1:
 305                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 306                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 307                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 308                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 309                                         break;
 310                                 case 2:
 311                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 312                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 313                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 314                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 315                                         break;
 316                                 case 3:
 317                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 318                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 319                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 320                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 321                                         break;
 322                                 case 4:
 323                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 324                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 325                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 326                                                          TILE_SPLIT(split_equal_to_row_size));
 327                                         break;
 328                                 case 5:
 329                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 330                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 331                                         break;
 332                                 case 6:
 333                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 334                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 335                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 336                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 337                                         break;
 338                                 case 7:
 339                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 340                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 341                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 342                                                          TILE_SPLIT(split_equal_to_row_size));
 343                                         break;
 344                                 case 8:
 345                                         gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 346                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16));
 347                                         break;
 348                                 case 9:
 349                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 350                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 351                                         break;
 352                                 case 10:
 353                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 354                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 355                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 356                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 357                                         break;
 358                                 case 11:
 359                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 360                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 361                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 362                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 363                                         break;
 364                                 case 12:
 365                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 366                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 367                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 368                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 369                                         break;
 370                                 case 13:
 371                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 372                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 373                                         break;
 374                                 case 14:
 375                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 376                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 377                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 378                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 379                                         break;
 380                                 case 16:
 381                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 382                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 383                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 384                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 385                                         break;
 386                                 case 17:
 387                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 388                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 389                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 390                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 391                                         break;
 392                                 case 27:
 393                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 394                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 395                                         break;
 396                                 case 28:
 397                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 398                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 399                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 400                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 401                                         break;
 402                                 case 29:
 403                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 404                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 405                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 406                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 407                                         break;
 408                                 case 30:
 409                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 410                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 411                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 412                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 413                                         break;
 414                                 default:
 415                                         gb_tile_moden = 0;
 416                                         break;
 417                                 }
 418                                 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 419                         }
 420                 } else if (num_rbs < 4) {
 421                         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 422                                 switch (reg_offset) {
 423                                 case 0:
 424                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 425                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 426                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 427                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 428                                         break;
 429                                 case 1:
 430                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 431                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 432                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 433                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 434                                         break;
 435                                 case 2:
 436                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 437                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 438                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 439                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 440                                         break;
 441                                 case 3:
 442                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 443                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 444                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 445                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 446                                         break;
 447                                 case 4:
 448                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 449                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 450                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 451                                                          TILE_SPLIT(split_equal_to_row_size));
 452                                         break;
 453                                 case 5:
 454                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 455                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 456                                         break;
 457                                 case 6:
 458                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 459                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 460                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 461                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 462                                         break;
 463                                 case 7:
 464                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 465                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 466                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 467                                                          TILE_SPLIT(split_equal_to_row_size));
 468                                         break;
 469                                 case 8:
 470                                         gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 471                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16));
 472                                         break;
 473                                 case 9:
 474                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 475                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 476                                         break;
 477                                 case 10:
 478                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 479                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 480                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 481                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 482                                         break;
 483                                 case 11:
 484                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 485                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 486                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 487                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 488                                         break;
 489                                 case 12:
 490                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 491                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 492                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 493                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 494                                         break;
 495                                 case 13:
 496                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 497                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 498                                         break;
 499                                 case 14:
 500                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 501                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 502                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 503                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 504                                         break;
 505                                 case 16:
 506                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 507                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 508                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 509                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 510                                         break;
 511                                 case 17:
 512                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 513                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 514                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 515                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 516                                         break;
 517                                 case 27:
 518                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 519                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 520                                         break;
 521                                 case 28:
 522                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 523                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 524                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 525                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 526                                         break;
 527                                 case 29:
 528                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 529                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 530                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 531                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 532                                         break;
 533                                 case 30:
 534                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 535                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 536                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 537                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 538                                         break;
 539                                 default:
 540                                         gb_tile_moden = 0;
 541                                         break;
 542                                 }
 543                                 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 544                         }
 545                 }
 546                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
 547                         switch (reg_offset) {
 548                         case 0:
 549                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 550                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 551                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 552                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 553                                 break;
 554                         case 1:
 555                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 556                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 557                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 558                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 559                                 break;
 560                         case 2:
 561                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 562                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 563                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 564                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 565                                 break;
 566                         case 3:
 567                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 568                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 569                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 570                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 571                                 break;
 572                         case 4:
 573                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 574                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 575                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 576                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 577                                 break;
 578                         case 5:
 579                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 580                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 581                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 582                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 583                                 break;
 584                         case 6:
 585                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 586                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 587                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 588                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 589                                 break;
 590                         case 8:
 591                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 592                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
 593                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 594                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 595                                 break;
 596                         case 9:
 597                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 598                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 599                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 600                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 601                                 break;
 602                         case 10:
 603                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 604                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 605                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 606                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 607                                 break;
 608                         case 11:
 609                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 610                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 611                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 612                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 613                                 break;
 614                         case 12:
 615                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 616                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 617                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 618                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 619                                 break;
 620                         case 13:
 621                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 622                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 623                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 624                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 625                                 break;
 626                         case 14:
 627                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 628                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 629                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 630                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 631                                 break;
 632                         default:
 633                                 gb_tile_moden = 0;
 634                                 break;
 635                         }
 636                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 637                 }
 638         } else if (num_pipe_configs == 2) {
 639                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 640                         switch (reg_offset) {
 641                         case 0:
 642                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 643                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 644                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 645                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 646                                 break;
 647                         case 1:
 648                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 649                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 650                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 651                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 652                                 break;
 653                         case 2:
 654                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 655                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 656                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 657                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 658                                 break;
 659                         case 3:
 660                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 661                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 662                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 663                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 664                                 break;
 665                         case 4:
 666                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 667                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 668                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 669                                                  TILE_SPLIT(split_equal_to_row_size));
 670                                 break;
 671                         case 5:
 672                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 673                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 674                                 break;
 675                         case 6:
 676                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 677                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 678                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 679                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 680                                 break;
 681                         case 7:
 682                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 683                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 684                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 685                                                  TILE_SPLIT(split_equal_to_row_size));
 686                                 break;
 687                         case 8:
 688                                 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
 689                                 break;
 690                         case 9:
 691                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 692                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 693                                 break;
 694                         case 10:
 695                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 696                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 697                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 698                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 699                                 break;
 700                         case 11:
 701                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 702                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 703                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 704                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 705                                 break;
 706                         case 12:
 707                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 708                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 709                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 710                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 711                                 break;
 712                         case 13:
 713                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 714                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 715                                 break;
 716                         case 14:
 717                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 718                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 719                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 720                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 721                                 break;
 722                         case 16:
 723                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 724                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 725                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 726                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 727                                 break;
 728                         case 17:
 729                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 730                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 731                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 732                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 733                                 break;
 734                         case 27:
 735                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 736                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 737                                 break;
 738                         case 28:
 739                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 740                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 741                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 742                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 743                                 break;
 744                         case 29:
 745                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 746                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 747                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 748                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 749                                 break;
 750                         case 30:
 751                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 752                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 753                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 754                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 755                                 break;
 756                         default:
 757                                 gb_tile_moden = 0;
 758                                 break;
 759                         }
 760                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 761                 }
 762                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
 763                         switch (reg_offset) {
 764                         case 0:
 765                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 766                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 767                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 768                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 769                                 break;
 770                         case 1:
 771                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 772                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 773                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 774                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 775                                 break;
 776                         case 2:
 777                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 778                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 779                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 780                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 781                                 break;
 782                         case 3:
 783                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 784                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 785                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 786                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 787                                 break;
 788                         case 4:
 789                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 790                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 791                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 792                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 793                                 break;
 794                         case 5:
 795                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 796                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 797                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 798                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 799                                 break;
 800                         case 6:
 801                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 802                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 803                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 804                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 805                                 break;
 806                         case 8:
 807                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
 808                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
 809                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 810                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 811                                 break;
 812                         case 9:
 813                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
 814                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 815                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 816                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 817                                 break;
 818                         case 10:
 819                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 820                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 821                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 822                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 823                                 break;
 824                         case 11:
 825                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 826                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 827                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 828                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 829                                 break;
 830                         case 12:
 831                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 832                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 833                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 834                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 835                                 break;
 836                         case 13:
 837                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 838                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 839                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 840                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 841                                 break;
 842                         case 14:
 843                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 844                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 845                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 846                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 847                                 break;
 848                         default:
 849                                 gb_tile_moden = 0;
 850                                 break;
 851                         }
 852                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 853                 }
 854         } else
 855                 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
 856 }
 857
 858 /**
 859  * cik_select_se_sh - select which SE, SH to address
 860  *
 861  * @rdev: radeon_device pointer
 862  * @se_num: shader engine to address
 863  * @sh_num: sh block to address
 864  *
 865  * Select which SE, SH combinations to address. Certain
 866  * registers are instanced per SE or SH.  0xffffffff means
 867  * broadcast to all SEs or SHs (CIK).
 868  */
 869 static void cik_select_se_sh(struct radeon_device *rdev,
 870                              u32 se_num, u32 sh_num)
 871 {
 872         u32 data = INSTANCE_BROADCAST_WRITES;
 873
 874         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
 875                 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
 876         else if (se_num == 0xffffffff)
 877                 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
 878         else if (sh_num == 0xffffffff)
 879                 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
 880         else
 881                 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
 882         WREG32(GRBM_GFX_INDEX, data);
 883 }
 884
 885 /**
 886  * cik_create_bitmask - create a bitmask
 887  *
 888  * @bit_width: length of the mask
 889  *
 890  * create a variable length bit mask (CIK).
 891  * Returns the bitmask.
 892  */
 893 static u32 cik_create_bitmask(u32 bit_width)
 894 {
 895         u32 i, mask = 0;
 896
 897         for (i = 0; i < bit_width; i++) {
 898                 mask <<= 1;
 899                 mask |= 1;
 900         }
 901         return mask;
 902 }
 903
 904 /**
 905  * cik_select_se_sh - select which SE, SH to address
 906  *
 907  * @rdev: radeon_device pointer
 908  * @max_rb_num: max RBs (render backends) for the asic
 909  * @se_num: number of SEs (shader engines) for the asic
 910  * @sh_per_se: number of SH blocks per SE for the asic
 911  *
 912  * Calculates the bitmask of disabled RBs (CIK).
 913  * Returns the disabled RB bitmask.
 914  */
 915 static u32 cik_get_rb_disabled(struct radeon_device *rdev,
 916                               u32 max_rb_num, u32 se_num,
 917                               u32 sh_per_se)
 918 {
 919         u32 data, mask;
 920
 921         data = RREG32(CC_RB_BACKEND_DISABLE);
 922         if (data & 1)
 923                 data &= BACKEND_DISABLE_MASK;
 924         else
 925                 data = 0;
 926         data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
 927
 928         data >>= BACKEND_DISABLE_SHIFT;
 929
 930         mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se);
 931
 932         return data & mask;
 933 }
 934
 935 /**
 936  * cik_setup_rb - setup the RBs on the asic
 937  *
 938  * @rdev: radeon_device pointer
 939  * @se_num: number of SEs (shader engines) for the asic
 940  * @sh_per_se: number of SH blocks per SE for the asic
 941  * @max_rb_num: max RBs (render backends) for the asic
 942  *
 943  * Configures per-SE/SH RB registers (CIK).
 944  */
 945 static void cik_setup_rb(struct radeon_device *rdev,
 946                          u32 se_num, u32 sh_per_se,
 947                          u32 max_rb_num)
 948 {
 949         int i, j;
 950         u32 data, mask;
 951         u32 disabled_rbs = 0;
 952         u32 enabled_rbs = 0;
 953
 954         for (i = 0; i < se_num; i++) {
 955                 for (j = 0; j < sh_per_se; j++) {
 956                         cik_select_se_sh(rdev, i, j);
 957                         data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
 958                         disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
 959                 }
 960         }
 961         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
 962
 963         mask = 1;
 964         for (i = 0; i < max_rb_num; i++) {
 965                 if (!(disabled_rbs & mask))
 966                         enabled_rbs |= mask;
 967                 mask <<= 1;
 968         }
 969
 970         for (i = 0; i < se_num; i++) {
 971                 cik_select_se_sh(rdev, i, 0xffffffff);
 972                 data = 0;
 973                 for (j = 0; j < sh_per_se; j++) {
 974                         switch (enabled_rbs & 3) {
 975                         case 1:
 976                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
 977                                 break;
 978                         case 2:
 979                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
 980                                 break;
 981                         case 3:
 982                         default:
 983                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
 984                                 break;
 985                         }
 986                         enabled_rbs >>= 2;
 987                 }
 988                 WREG32(PA_SC_RASTER_CONFIG, data);
 989         }
 990         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
 991 }
 992
 993 /**
 994  * cik_gpu_init - setup the 3D engine
 995  *
 996  * @rdev: radeon_device pointer
 997  *
 998  * Configures the 3D engine and tiling configuration
 999  * registers so that the 3D engine is usable.
1000  */
1001 static void cik_gpu_init(struct radeon_device *rdev)
1002 {
1003         u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
1004         u32 mc_shared_chmap, mc_arb_ramcfg;
1005         u32 hdp_host_path_cntl;
1006         u32 tmp;
1007         int i, j;
1008
1009         switch (rdev->family) {
1010         case CHIP_BONAIRE:
1011                 rdev->config.cik.max_shader_engines = 2;
1012                 rdev->config.cik.max_tile_pipes = 4;
1013                 rdev->config.cik.max_cu_per_sh = 7;
1014                 rdev->config.cik.max_sh_per_se = 1;
1015                 rdev->config.cik.max_backends_per_se = 2;
1016                 rdev->config.cik.max_texture_channel_caches = 4;
1017                 rdev->config.cik.max_gprs = 256;
1018                 rdev->config.cik.max_gs_threads = 32;
1019                 rdev->config.cik.max_hw_contexts = 8;
1020
1021                 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
1022                 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
1023                 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
1024                 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
1025                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
1026                 break;
1027         case CHIP_KAVERI:
1028                 /* TODO */
1029                 break;
1030         case CHIP_KABINI:
1031         default:
1032                 rdev->config.cik.max_shader_engines = 1;
1033                 rdev->config.cik.max_tile_pipes = 2;
1034                 rdev->config.cik.max_cu_per_sh = 2;
1035                 rdev->config.cik.max_sh_per_se = 1;
1036                 rdev->config.cik.max_backends_per_se = 1;
1037                 rdev->config.cik.max_texture_channel_caches = 2;
1038                 rdev->config.cik.max_gprs = 256;
1039                 rdev->config.cik.max_gs_threads = 16;
1040                 rdev->config.cik.max_hw_contexts = 8;
1041
1042                 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
1043                 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
1044                 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
1045                 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
1046                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
1047                 break;
1048         }
1049
1050         /* Initialize HDP */
1051         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1052                 WREG32((0x2c14 + j), 0x00000000);
1053                 WREG32((0x2c18 + j), 0x00000000);
1054                 WREG32((0x2c1c + j), 0x00000000);
1055                 WREG32((0x2c20 + j), 0x00000000);
1056                 WREG32((0x2c24 + j), 0x00000000);
1057         }
1058
1059         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1060
1061         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1062
1063         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1064         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1065
1066         rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
1067         rdev->config.cik.mem_max_burst_length_bytes = 256;
1068         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1069         rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1070         if (rdev->config.cik.mem_row_size_in_kb > 4)
1071                 rdev->config.cik.mem_row_size_in_kb = 4;
1072         /* XXX use MC settings? */
1073         rdev->config.cik.shader_engine_tile_size = 32;
1074         rdev->config.cik.num_gpus = 1;
1075         rdev->config.cik.multi_gpu_tile_size = 64;
1076
1077         /* fix up row size */
1078         gb_addr_config &= ~ROW_SIZE_MASK;
1079         switch (rdev->config.cik.mem_row_size_in_kb) {
1080         case 1:
1081         default:
1082                 gb_addr_config |= ROW_SIZE(0);
1083                 break;
1084         case 2:
1085                 gb_addr_config |= ROW_SIZE(1);
1086                 break;
1087         case 4:
1088                 gb_addr_config |= ROW_SIZE(2);
1089                 break;
1090         }
1091
1092         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1093          * not have bank info, so create a custom tiling dword.
1094          * bits 3:0   num_pipes
1095          * bits 7:4   num_banks
1096          * bits 11:8  group_size
1097          * bits 15:12 row_size
1098          */
1099         rdev->config.cik.tile_config = 0;
1100         switch (rdev->config.cik.num_tile_pipes) {
1101         case 1:
1102                 rdev->config.cik.tile_config |= (0 << 0);
1103                 break;
1104         case 2:
1105                 rdev->config.cik.tile_config |= (1 << 0);
1106                 break;
1107         case 4:
1108                 rdev->config.cik.tile_config |= (2 << 0);
1109                 break;
1110         case 8:
1111         default:
1112                 /* XXX what about 12? */
1113                 rdev->config.cik.tile_config |= (3 << 0);
1114                 break;
1115         }
1116         if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1117                 rdev->config.cik.tile_config |= 1 << 4;
1118         else
1119                 rdev->config.cik.tile_config |= 0 << 4;
1120         rdev->config.cik.tile_config |=
1121                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1122         rdev->config.cik.tile_config |=
1123                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1124
1125         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1126         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1127         WREG32(DMIF_ADDR_CALC, gb_addr_config);
1128
1129         cik_tiling_mode_table_init(rdev);
1130
1131         cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
1132                      rdev->config.cik.max_sh_per_se,
1133                      rdev->config.cik.max_backends_per_se);
1134
1135         /* set HW defaults for 3D engine */
1136         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1137
1138         WREG32(SX_DEBUG_1, 0x20);
1139
1140         WREG32(TA_CNTL_AUX, 0x00010000);
1141
1142         tmp = RREG32(SPI_CONFIG_CNTL);
1143         tmp |= 0x03000000;
1144         WREG32(SPI_CONFIG_CNTL, tmp);
1145
1146         WREG32(SQ_CONFIG, 1);
1147
1148         WREG32(DB_DEBUG, 0);
1149
1150         tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
1151         tmp |= 0x00000400;
1152         WREG32(DB_DEBUG2, tmp);
1153
1154         tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
1155         tmp |= 0x00020200;
1156         WREG32(DB_DEBUG3, tmp);
1157
1158         tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
1159         tmp |= 0x00018208;
1160         WREG32(CB_HW_CONTROL, tmp);
1161
1162         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1163
1164         WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
1165                                  SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
1166                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
1167                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
1168
1169         WREG32(VGT_NUM_INSTANCES, 1);
1170
1171         WREG32(CP_PERFMON_CNTL, 0);
1172
1173         WREG32(SQ_CONFIG, 0);
1174
1175         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1176                                           FORCE_EOV_MAX_REZ_CNT(255)));
1177
1178         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1179                AUTO_INVLD_EN(ES_AND_GS_AUTO));
1180
1181         WREG32(VGT_GS_VERTEX_REUSE, 16);
1182         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1183
1184         tmp = RREG32(HDP_MISC_CNTL);
1185         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1186         WREG32(HDP_MISC_CNTL, tmp);
1187
1188         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1189         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1190
1191         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1192         WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
1193
1194         udelay(50);
1195 }
1196
1197 /**
1198  * cik_gpu_is_lockup - check if the 3D engine is locked up
1199  *
1200  * @rdev: radeon_device pointer
1201  * @ring: radeon_ring structure holding ring information
1202  *
1203  * Check if the 3D engine is locked up (CIK).
1204  * Returns true if the engine is locked, false if not.
1205  */
1206 bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1207 {
1208         u32 srbm_status, srbm_status2;
1209         u32 grbm_status, grbm_status2;
1210         u32 grbm_status_se0, grbm_status_se1, grbm_status_se2, grbm_status_se3;
1211
1212         srbm_status = RREG32(SRBM_STATUS);
1213         srbm_status2 = RREG32(SRBM_STATUS2);
1214         grbm_status = RREG32(GRBM_STATUS);
1215         grbm_status2 = RREG32(GRBM_STATUS2);
1216         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1217         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1218         grbm_status_se2 = RREG32(GRBM_STATUS_SE2);
1219         grbm_status_se3 = RREG32(GRBM_STATUS_SE3);
1220         if (!(grbm_status & GUI_ACTIVE)) {
1221                 radeon_ring_lockup_update(ring);
1222                 return false;
1223         }
1224         /* force CP activities */
1225         radeon_ring_force_activity(rdev, ring);
1226         return radeon_ring_test_lockup(rdev, ring);
1227 }
1228
1229 /**
1230  * cik_gfx_gpu_soft_reset - soft reset the 3D engine and CPG
1231  *
1232  * @rdev: radeon_device pointer
1233  *
1234  * Soft reset the GFX engine and CPG blocks (CIK).
1235  * XXX: deal with reseting RLC and CPF
1236  * Returns 0 for success.
1237  */
1238 static int cik_gfx_gpu_soft_reset(struct radeon_device *rdev)
1239 {
1240         struct evergreen_mc_save save;
1241         u32 grbm_reset = 0;
1242
1243         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1244                 return 0;
1245
1246         dev_info(rdev->dev, "GPU GFX softreset \n");
1247         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1248                 RREG32(GRBM_STATUS));
1249         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
1250                 RREG32(GRBM_STATUS2));
1251         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1252                 RREG32(GRBM_STATUS_SE0));
1253         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1254                 RREG32(GRBM_STATUS_SE1));
1255         dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
1256                 RREG32(GRBM_STATUS_SE2));
1257         dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
1258                 RREG32(GRBM_STATUS_SE3));
1259         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1260                 RREG32(SRBM_STATUS));
1261         dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
1262                 RREG32(SRBM_STATUS2));
1263         evergreen_mc_stop(rdev, &save);
1264         if (radeon_mc_wait_for_idle(rdev)) {
1265                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1266         }
1267         /* Disable CP parsing/prefetching */
1268         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
1269
1270         /* reset all the gfx block and all CPG blocks */
1271         grbm_reset = SOFT_RESET_CPG | SOFT_RESET_GFX;
1272
1273         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1274         WREG32(GRBM_SOFT_RESET, grbm_reset);
1275         (void)RREG32(GRBM_SOFT_RESET);
1276         udelay(50);
1277         WREG32(GRBM_SOFT_RESET, 0);
1278         (void)RREG32(GRBM_SOFT_RESET);
1279         /* Wait a little for things to settle down */
1280         udelay(50);
1281         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1282                 RREG32(GRBM_STATUS));
1283         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
1284                 RREG32(GRBM_STATUS2));
1285         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1286                 RREG32(GRBM_STATUS_SE0));
1287         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1288                 RREG32(GRBM_STATUS_SE1));
1289         dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
1290                 RREG32(GRBM_STATUS_SE2));
1291         dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
1292                 RREG32(GRBM_STATUS_SE3));
1293         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1294                 RREG32(SRBM_STATUS));
1295         dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
1296                 RREG32(SRBM_STATUS2));
1297         evergreen_mc_resume(rdev, &save);
1298         return 0;
1299 }
1300
1301 /**
1302  * cik_compute_gpu_soft_reset - soft reset CPC
1303  *
1304  * @rdev: radeon_device pointer
1305  *
1306  * Soft reset the CPC blocks (CIK).
1307  * XXX: deal with reseting RLC and CPF
1308  * Returns 0 for success.
1309  */
1310 static int cik_compute_gpu_soft_reset(struct radeon_device *rdev)
1311 {
1312         struct evergreen_mc_save save;
1313         u32 grbm_reset = 0;
1314
1315         dev_info(rdev->dev, "GPU compute softreset \n");
1316         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1317                 RREG32(GRBM_STATUS));
1318         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
1319                 RREG32(GRBM_STATUS2));
1320         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1321                 RREG32(GRBM_STATUS_SE0));
1322         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1323                 RREG32(GRBM_STATUS_SE1));
1324         dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
1325                 RREG32(GRBM_STATUS_SE2));
1326         dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
1327                 RREG32(GRBM_STATUS_SE3));
1328         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1329                 RREG32(SRBM_STATUS));
1330         dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
1331                 RREG32(SRBM_STATUS2));
1332         evergreen_mc_stop(rdev, &save);
1333         if (radeon_mc_wait_for_idle(rdev)) {
1334                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1335         }
1336         /* Disable CP parsing/prefetching */
1337         WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
1338
1339         /* reset all the CPC blocks */
1340         grbm_reset = SOFT_RESET_CPG;
1341
1342         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1343         WREG32(GRBM_SOFT_RESET, grbm_reset);
1344         (void)RREG32(GRBM_SOFT_RESET);
1345         udelay(50);
1346         WREG32(GRBM_SOFT_RESET, 0);
1347         (void)RREG32(GRBM_SOFT_RESET);
1348         /* Wait a little for things to settle down */
1349         udelay(50);
1350         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1351                 RREG32(GRBM_STATUS));
1352         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
1353                 RREG32(GRBM_STATUS2));
1354         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1355                 RREG32(GRBM_STATUS_SE0));
1356         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1357                 RREG32(GRBM_STATUS_SE1));
1358         dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
1359                 RREG32(GRBM_STATUS_SE2));
1360         dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
1361                 RREG32(GRBM_STATUS_SE3));
1362         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1363                 RREG32(SRBM_STATUS));
1364         dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
1365                 RREG32(SRBM_STATUS2));
1366         evergreen_mc_resume(rdev, &save);
1367         return 0;
1368 }
1369
1370 /**
1371  * cik_asic_reset - soft reset compute and gfx
1372  *
1373  * @rdev: radeon_device pointer
1374  *
1375  * Soft reset the CPC blocks (CIK).
1376  * XXX: make this more fine grained and only reset
1377  * what is necessary.
1378  * Returns 0 for success.
1379  */
1380 int cik_asic_reset(struct radeon_device *rdev)
1381 {
1382         int r;
1383
1384         r = cik_compute_gpu_soft_reset(rdev);
1385         if (r)
1386                 dev_info(rdev->dev, "Compute reset failed!\n");
1387
1388         return cik_gfx_gpu_soft_reset(rdev);
1389 }