sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009-12 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM1811_JACKDET_MODE_NONE  0x0000
  42 #define WM1811_JACKDET_MODE_JACK  0x0100
  43 #define WM1811_JACKDET_MODE_MIC   0x0080
  44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
  45
  46 #define WM8994_NUM_DRC 3
  47 #define WM8994_NUM_EQ  3
  48
  49 static struct {
  50         unsigned int reg;
  51         unsigned int mask;
  52 } wm8994_vu_bits[] = {
  53         { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  54         { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  55         { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  56         { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  57         { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
  58         { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
  59         { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  60         { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  61         { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  62         { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  63
  64         { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
  65         { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
  66         { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
  67         { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
  68         { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
  69         { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
  70         { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
  71         { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
  72         { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
  73         { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  74         { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
  75         { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  76         { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
  77         { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
  78         { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
  79         { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
  80 };
  81
  82 static int wm8994_drc_base[] = {
  83         WM8994_AIF1_DRC1_1,
  84         WM8994_AIF1_DRC2_1,
  85         WM8994_AIF2_DRC_1,
  86 };
  87
  88 static int wm8994_retune_mobile_base[] = {
  89         WM8994_AIF1_DAC1_EQ_GAINS_1,
  90         WM8994_AIF1_DAC2_EQ_GAINS_1,
  91         WM8994_AIF2_EQ_GAINS_1,
  92 };
  93
  94 static const struct wm8958_micd_rate micdet_rates[] = {
  95         { 32768,       true,  1, 4 },
  96         { 32768,       false, 1, 1 },
  97         { 44100 * 256, true,  7, 10 },
  98         { 44100 * 256, false, 7, 10 },
  99 };
 100
 101 static const struct wm8958_micd_rate jackdet_rates[] = {
 102         { 32768,       true,  0, 1 },
 103         { 32768,       false, 0, 1 },
 104         { 44100 * 256, true,  10, 10 },
 105         { 44100 * 256, false, 7, 8 },
 106 };
 107
 108 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
 109 {
 110         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 111         struct wm8994 *control = wm8994->wm8994;
 112         int best, i, sysclk, val;
 113         bool idle;
 114         const struct wm8958_micd_rate *rates;
 115         int num_rates;
 116
 117         idle = !wm8994->jack_mic;
 118
 119         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
 120         if (sysclk & WM8994_SYSCLK_SRC)
 121                 sysclk = wm8994->aifclk[1];
 122         else
 123                 sysclk = wm8994->aifclk[0];
 124
 125         if (control->pdata.micd_rates) {
 126                 rates = control->pdata.micd_rates;
 127                 num_rates = control->pdata.num_micd_rates;
 128         } else if (wm8994->jackdet) {
 129                 rates = jackdet_rates;
 130                 num_rates = ARRAY_SIZE(jackdet_rates);
 131         } else {
 132                 rates = micdet_rates;
 133                 num_rates = ARRAY_SIZE(micdet_rates);
 134         }
 135
 136         best = 0;
 137         for (i = 0; i < num_rates; i++) {
 138                 if (rates[i].idle != idle)
 139                         continue;
 140                 if (abs(rates[i].sysclk - sysclk) <
 141                     abs(rates[best].sysclk - sysclk))
 142                         best = i;
 143                 else if (rates[best].idle != idle)
 144                         best = i;
 145         }
 146
 147         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 148                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 149
 150         dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
 151                 rates[best].start, rates[best].rate, sysclk,
 152                 idle ? "idle" : "active");
 153
 154         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
 155                             WM8958_MICD_BIAS_STARTTIME_MASK |
 156                             WM8958_MICD_RATE_MASK, val);
 157 }
 158
 159 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 160 {
 161         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 162         int rate;
 163         int reg1 = 0;
 164         int offset;
 165
 166         if (aif)
 167                 offset = 4;
 168         else
 169                 offset = 0;
 170
 171         switch (wm8994->sysclk[aif]) {
 172         case WM8994_SYSCLK_MCLK1:
 173                 rate = wm8994->mclk[0];
 174                 break;
 175
 176         case WM8994_SYSCLK_MCLK2:
 177                 reg1 |= 0x8;
 178                 rate = wm8994->mclk[1];
 179                 break;
 180
 181         case WM8994_SYSCLK_FLL1:
 182                 reg1 |= 0x10;
 183                 rate = wm8994->fll[0].out;
 184                 break;
 185
 186         case WM8994_SYSCLK_FLL2:
 187                 reg1 |= 0x18;
 188                 rate = wm8994->fll[1].out;
 189                 break;
 190
 191         default:
 192                 return -EINVAL;
 193         }
 194
 195         if (rate >= 13500000) {
 196                 rate /= 2;
 197                 reg1 |= WM8994_AIF1CLK_DIV;
 198
 199                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 200                         aif + 1, rate);
 201         }
 202
 203         wm8994->aifclk[aif] = rate;
 204
 205         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 206                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 207                             reg1);
 208
 209         return 0;
 210 }
 211
 212 static int configure_clock(struct snd_soc_codec *codec)
 213 {
 214         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 215         int change, new;
 216
 217         /* Bring up the AIF clocks first */
 218         configure_aif_clock(codec, 0);
 219         configure_aif_clock(codec, 1);
 220
 221         /* Then switch CLK_SYS over to the higher of them; a change
 222          * can only happen as a result of a clocking change which can
 223          * only be made outside of DAPM so we can safely redo the
 224          * clocking.
 225          */
 226
 227         /* If they're equal it doesn't matter which is used */
 228         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 229                 wm8958_micd_set_rate(codec);
 230                 return 0;
 231         }
 232
 233         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 234                 new = WM8994_SYSCLK_SRC;
 235         else
 236                 new = 0;
 237
 238         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 239                                      WM8994_SYSCLK_SRC, new);
 240         if (change)
 241                 snd_soc_dapm_sync(&codec->dapm);
 242
 243         wm8958_micd_set_rate(codec);
 244
 245         return 0;
 246 }
 247
 248 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 249                          struct snd_soc_dapm_widget *sink)
 250 {
 251         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 252         const char *clk;
 253
 254         /* Check what we're currently using for CLK_SYS */
 255         if (reg & WM8994_SYSCLK_SRC)
 256                 clk = "AIF2CLK";
 257         else
 258                 clk = "AIF1CLK";
 259
 260         return strcmp(source->name, clk) == 0;
 261 }
 262
 263 static const char *sidetone_hpf_text[] = {
 264         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 265 };
 266
 267 static const struct soc_enum sidetone_hpf =
 268         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 269
 270 static const char *adc_hpf_text[] = {
 271         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 272 };
 273
 274 static const struct soc_enum aif1adc1_hpf =
 275         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 276
 277 static const struct soc_enum aif1adc2_hpf =
 278         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 279
 280 static const struct soc_enum aif2adc_hpf =
 281         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 282
 283 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 284 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 285 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 286 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 287 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 288 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 289 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 290
 291 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 292         SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
 293                 snd_soc_get_volsw, wm8994_put_drc_sw)
 294
 295 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 296                              struct snd_ctl_elem_value *ucontrol)
 297 {
 298         struct soc_mixer_control *mc =
 299                 (struct soc_mixer_control *)kcontrol->private_value;
 300         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 301         int mask, ret;
 302
 303         /* Can't enable both ADC and DAC paths simultaneously */
 304         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 305                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 306                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 307         else
 308                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 309
 310         ret = snd_soc_read(codec, mc->reg);
 311         if (ret < 0)
 312                 return ret;
 313         if (ret & mask)
 314                 return -EINVAL;
 315
 316         return snd_soc_put_volsw(kcontrol, ucontrol);
 317 }
 318
 319 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 320 {
 321         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 322         struct wm8994 *control = wm8994->wm8994;
 323         struct wm8994_pdata *pdata = &control->pdata;
 324         int base = wm8994_drc_base[drc];
 325         int cfg = wm8994->drc_cfg[drc];
 326         int save, i;
 327
 328         /* Save any enables; the configuration should clear them. */
 329         save = snd_soc_read(codec, base);
 330         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 331                 WM8994_AIF1ADC1R_DRC_ENA;
 332
 333         for (i = 0; i < WM8994_DRC_REGS; i++)
 334                 snd_soc_update_bits(codec, base + i, 0xffff,
 335                                     pdata->drc_cfgs[cfg].regs[i]);
 336
 337         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 338                              WM8994_AIF1ADC1L_DRC_ENA |
 339                              WM8994_AIF1ADC1R_DRC_ENA, save);
 340 }
 341
 342 /* Icky as hell but saves code duplication */
 343 static int wm8994_get_drc(const char *name)
 344 {
 345         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 346                 return 0;
 347         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 348                 return 1;
 349         if (strcmp(name, "AIF2DRC Mode") == 0)
 350                 return 2;
 351         return -EINVAL;
 352 }
 353
 354 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 355                                struct snd_ctl_elem_value *ucontrol)
 356 {
 357         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 358         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 359         struct wm8994 *control = wm8994->wm8994;
 360         struct wm8994_pdata *pdata = &control->pdata;
 361         int drc = wm8994_get_drc(kcontrol->id.name);
 362         int value = ucontrol->value.integer.value[0];
 363
 364         if (drc < 0)
 365                 return drc;
 366
 367         if (value >= pdata->num_drc_cfgs)
 368                 return -EINVAL;
 369
 370         wm8994->drc_cfg[drc] = value;
 371
 372         wm8994_set_drc(codec, drc);
 373
 374         return 0;
 375 }
 376
 377 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 378                                struct snd_ctl_elem_value *ucontrol)
 379 {
 380         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 381         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 382         int drc = wm8994_get_drc(kcontrol->id.name);
 383
 384         if (drc < 0)
 385                 return drc;
 386         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 387
 388         return 0;
 389 }
 390
 391 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 392 {
 393         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 394         struct wm8994 *control = wm8994->wm8994;
 395         struct wm8994_pdata *pdata = &control->pdata;
 396         int base = wm8994_retune_mobile_base[block];
 397         int iface, best, best_val, save, i, cfg;
 398
 399         if (!pdata || !wm8994->num_retune_mobile_texts)
 400                 return;
 401
 402         switch (block) {
 403         case 0:
 404         case 1:
 405                 iface = 0;
 406                 break;
 407         case 2:
 408                 iface = 1;
 409                 break;
 410         default:
 411                 return;
 412         }
 413
 414         /* Find the version of the currently selected configuration
 415          * with the nearest sample rate. */
 416         cfg = wm8994->retune_mobile_cfg[block];
 417         best = 0;
 418         best_val = INT_MAX;
 419         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 420                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 421                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 422                     abs(pdata->retune_mobile_cfgs[i].rate
 423                         - wm8994->dac_rates[iface]) < best_val) {
 424                         best = i;
 425                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 426                                        - wm8994->dac_rates[iface]);
 427                 }
 428         }
 429
 430         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 431                 block,
 432                 pdata->retune_mobile_cfgs[best].name,
 433                 pdata->retune_mobile_cfgs[best].rate,
 434                 wm8994->dac_rates[iface]);
 435
 436         /* The EQ will be disabled while reconfiguring it, remember the
 437          * current configuration.
 438          */
 439         save = snd_soc_read(codec, base);
 440         save &= WM8994_AIF1DAC1_EQ_ENA;
 441
 442         for (i = 0; i < WM8994_EQ_REGS; i++)
 443                 snd_soc_update_bits(codec, base + i, 0xffff,
 444                                 pdata->retune_mobile_cfgs[best].regs[i]);
 445
 446         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 447 }
 448
 449 /* Icky as hell but saves code duplication */
 450 static int wm8994_get_retune_mobile_block(const char *name)
 451 {
 452         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 453                 return 0;
 454         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 455                 return 1;
 456         if (strcmp(name, "AIF2 EQ Mode") == 0)
 457                 return 2;
 458         return -EINVAL;
 459 }
 460
 461 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 462                                          struct snd_ctl_elem_value *ucontrol)
 463 {
 464         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 465         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 466         struct wm8994 *control = wm8994->wm8994;
 467         struct wm8994_pdata *pdata = &control->pdata;
 468         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 469         int value = ucontrol->value.integer.value[0];
 470
 471         if (block < 0)
 472                 return block;
 473
 474         if (value >= pdata->num_retune_mobile_cfgs)
 475                 return -EINVAL;
 476
 477         wm8994->retune_mobile_cfg[block] = value;
 478
 479         wm8994_set_retune_mobile(codec, block);
 480
 481         return 0;
 482 }
 483
 484 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 485                                          struct snd_ctl_elem_value *ucontrol)
 486 {
 487         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 488         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 489         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 490
 491         if (block < 0)
 492                 return block;
 493
 494         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 495
 496         return 0;
 497 }
 498
 499 static const char *aif_chan_src_text[] = {
 500         "Left", "Right"
 501 };
 502
 503 static const struct soc_enum aif1adcl_src =
 504         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 505
 506 static const struct soc_enum aif1adcr_src =
 507         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 508
 509 static const struct soc_enum aif2adcl_src =
 510         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 511
 512 static const struct soc_enum aif2adcr_src =
 513         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 514
 515 static const struct soc_enum aif1dacl_src =
 516         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 517
 518 static const struct soc_enum aif1dacr_src =
 519         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 520
 521 static const struct soc_enum aif2dacl_src =
 522         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 523
 524 static const struct soc_enum aif2dacr_src =
 525         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 526
 527 static const char *osr_text[] = {
 528         "Low Power", "High Performance",
 529 };
 530
 531 static const struct soc_enum dac_osr =
 532         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 533
 534 static const struct soc_enum adc_osr =
 535         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 536
 537 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 538 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 539                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 540                  1, 119, 0, digital_tlv),
 541 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 542                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 543                  1, 119, 0, digital_tlv),
 544 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 545                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 546                  1, 119, 0, digital_tlv),
 547
 548 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 549 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 550 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 551 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 552
 553 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 554 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 555 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 556 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 557
 558 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 559                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 560 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 561                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 562 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 563                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 564
 565 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 566 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 567
 568 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 569 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 570 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 571
 572 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 573 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 574 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 575
 576 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 577 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 578 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 579
 580 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 581 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 582 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 583
 584 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 585                5, 12, 0, st_tlv),
 586 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 587                0, 12, 0, st_tlv),
 588 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 589                5, 12, 0, st_tlv),
 590 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 591                0, 12, 0, st_tlv),
 592 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 593 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 594
 595 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 596 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 597
 598 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 599 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 600
 601 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 602 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 603
 604 SOC_ENUM("ADC OSR", adc_osr),
 605 SOC_ENUM("DAC OSR", dac_osr),
 606
 607 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 608                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 609 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 610              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 611
 612 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 613                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 614 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 615              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 616
 617 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 618                6, 1, 1, wm_hubs_spkmix_tlv),
 619 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 620                2, 1, 1, wm_hubs_spkmix_tlv),
 621
 622 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 623                6, 1, 1, wm_hubs_spkmix_tlv),
 624 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 625                2, 1, 1, wm_hubs_spkmix_tlv),
 626
 627 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 628                10, 15, 0, wm8994_3d_tlv),
 629 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 630            8, 1, 0),
 631 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 632                10, 15, 0, wm8994_3d_tlv),
 633 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 634            8, 1, 0),
 635 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 636                10, 15, 0, wm8994_3d_tlv),
 637 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 638            8, 1, 0),
 639 };
 640
 641 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 642 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 643                eq_tlv),
 644 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 649                eq_tlv),
 650 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 651                eq_tlv),
 652
 653 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 660                eq_tlv),
 661 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 662                eq_tlv),
 663
 664 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 665                eq_tlv),
 666 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 667                eq_tlv),
 668 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 669                eq_tlv),
 670 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 671                eq_tlv),
 672 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 673                eq_tlv),
 674 };
 675
 676 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
 677 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
 678                    WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 679                    WM8994_AIF1ADC1R_DRC_ENA),
 680 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
 681                    WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
 682                    WM8994_AIF1ADC2R_DRC_ENA),
 683 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
 684                    WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
 685                    WM8994_AIF2ADCR_DRC_ENA),
 686 };
 687
 688 static const char *wm8958_ng_text[] = {
 689         "30ms", "125ms", "250ms", "500ms",
 690 };
 691
 692 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 693         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 694                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 695
 696 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 697         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 698                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 699
 700 static const struct soc_enum wm8958_aif2dac_ng_hold =
 701         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 702                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 703
 704 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 705 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 706
 707 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 708            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 709 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 710 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 711                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 712                7, 1, ng_tlv),
 713
 714 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 715            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 716 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 717 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 718                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 719                7, 1, ng_tlv),
 720
 721 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 722            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 723 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 724 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 725                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 726                7, 1, ng_tlv),
 727 };
 728
 729 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 730 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 731                mixin_boost_tlv),
 732 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 733                mixin_boost_tlv),
 734 };
 735
 736 /* We run all mode setting through a function to enforce audio mode */
 737 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
 738 {
 739         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 740
 741         if (!wm8994->jackdet || !wm8994->micdet[0].jack)
 742                 return;
 743
 744         if (wm8994->active_refcount)
 745                 mode = WM1811_JACKDET_MODE_AUDIO;
 746
 747         if (mode == wm8994->jackdet_mode)
 748                 return;
 749
 750         wm8994->jackdet_mode = mode;
 751
 752         /* Always use audio mode to detect while the system is active */
 753         if (mode != WM1811_JACKDET_MODE_NONE)
 754                 mode = WM1811_JACKDET_MODE_AUDIO;
 755
 756         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 757                             WM1811_JACKDET_MODE_MASK, mode);
 758 }
 759
 760 static void active_reference(struct snd_soc_codec *codec)
 761 {
 762         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 763
 764         mutex_lock(&wm8994->accdet_lock);
 765
 766         wm8994->active_refcount++;
 767
 768         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
 769                 wm8994->active_refcount);
 770
 771         /* If we're using jack detection go into audio mode */
 772         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
 773
 774         mutex_unlock(&wm8994->accdet_lock);
 775 }
 776
 777 static void active_dereference(struct snd_soc_codec *codec)
 778 {
 779         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 780         u16 mode;
 781
 782         mutex_lock(&wm8994->accdet_lock);
 783
 784         wm8994->active_refcount--;
 785
 786         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
 787                 wm8994->active_refcount);
 788
 789         if (wm8994->active_refcount == 0) {
 790                 /* Go into appropriate detection only mode */
 791                 if (wm8994->jack_mic || wm8994->mic_detecting)
 792                         mode = WM1811_JACKDET_MODE_MIC;
 793                 else
 794                         mode = WM1811_JACKDET_MODE_JACK;
 795
 796                 wm1811_jackdet_set_mode(codec, mode);
 797         }
 798
 799         mutex_unlock(&wm8994->accdet_lock);
 800 }
 801
 802 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 803                          struct snd_kcontrol *kcontrol, int event)
 804 {
 805         struct snd_soc_codec *codec = w->codec;
 806         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 807
 808         switch (event) {
 809         case SND_SOC_DAPM_PRE_PMU:
 810                 return configure_clock(codec);
 811
 812         case SND_SOC_DAPM_POST_PMU:
 813                 /*
 814                  * JACKDET won't run until we start the clock and it
 815                  * only reports deltas, make sure we notify the state
 816                  * up the stack on startup.  Use a *very* generous
 817                  * timeout for paranoia, there's no urgency and we
 818                  * don't want false reports.
 819                  */
 820                 if (wm8994->jackdet && !wm8994->clk_has_run) {
 821                         schedule_delayed_work(&wm8994->jackdet_bootstrap,
 822                                               msecs_to_jiffies(1000));
 823                         wm8994->clk_has_run = true;
 824                 }
 825                 break;
 826
 827         case SND_SOC_DAPM_POST_PMD:
 828                 configure_clock(codec);
 829                 break;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static void vmid_reference(struct snd_soc_codec *codec)
 836 {
 837         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 838
 839         pm_runtime_get_sync(codec->dev);
 840
 841         wm8994->vmid_refcount++;
 842
 843         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 844                 wm8994->vmid_refcount);
 845
 846         if (wm8994->vmid_refcount == 1) {
 847                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 848                                     WM8994_LINEOUT1_DISCH |
 849                                     WM8994_LINEOUT2_DISCH, 0);
 850
 851                 wm_hubs_vmid_ena(codec);
 852
 853                 switch (wm8994->vmid_mode) {
 854                 default:
 855                         WARN_ON(NULL == "Invalid VMID mode");
 856                 case WM8994_VMID_NORMAL:
 857                         /* Startup bias, VMID ramp & buffer */
 858                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 859                                             WM8994_BIAS_SRC |
 860                                             WM8994_VMID_DISCH |
 861                                             WM8994_STARTUP_BIAS_ENA |
 862                                             WM8994_VMID_BUF_ENA |
 863                                             WM8994_VMID_RAMP_MASK,
 864                                             WM8994_BIAS_SRC |
 865                                             WM8994_STARTUP_BIAS_ENA |
 866                                             WM8994_VMID_BUF_ENA |
 867                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
 868
 869                         /* Main bias enable, VMID=2x40k */
 870                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 871                                             WM8994_BIAS_ENA |
 872                                             WM8994_VMID_SEL_MASK,
 873                                             WM8994_BIAS_ENA | 0x2);
 874
 875                         msleep(300);
 876
 877                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 878                                             WM8994_VMID_RAMP_MASK |
 879                                             WM8994_BIAS_SRC,
 880                                             0);
 881                         break;
 882
 883                 case WM8994_VMID_FORCE:
 884                         /* Startup bias, slow VMID ramp & buffer */
 885                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 886                                             WM8994_BIAS_SRC |
 887                                             WM8994_VMID_DISCH |
 888                                             WM8994_STARTUP_BIAS_ENA |
 889                                             WM8994_VMID_BUF_ENA |
 890                                             WM8994_VMID_RAMP_MASK,
 891                                             WM8994_BIAS_SRC |
 892                                             WM8994_STARTUP_BIAS_ENA |
 893                                             WM8994_VMID_BUF_ENA |
 894                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
 895
 896                         /* Main bias enable, VMID=2x40k */
 897                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 898                                             WM8994_BIAS_ENA |
 899                                             WM8994_VMID_SEL_MASK,
 900                                             WM8994_BIAS_ENA | 0x2);
 901
 902                         msleep(400);
 903
 904                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 905                                             WM8994_VMID_RAMP_MASK |
 906                                             WM8994_BIAS_SRC,
 907                                             0);
 908                         break;
 909                 }
 910         }
 911 }
 912
 913 static void vmid_dereference(struct snd_soc_codec *codec)
 914 {
 915         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 916
 917         wm8994->vmid_refcount--;
 918
 919         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 920                 wm8994->vmid_refcount);
 921
 922         if (wm8994->vmid_refcount == 0) {
 923                 if (wm8994->hubs.lineout1_se)
 924                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 925                                             WM8994_LINEOUT1N_ENA |
 926                                             WM8994_LINEOUT1P_ENA,
 927                                             WM8994_LINEOUT1N_ENA |
 928                                             WM8994_LINEOUT1P_ENA);
 929
 930                 if (wm8994->hubs.lineout2_se)
 931                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 932                                             WM8994_LINEOUT2N_ENA |
 933                                             WM8994_LINEOUT2P_ENA,
 934                                             WM8994_LINEOUT2N_ENA |
 935                                             WM8994_LINEOUT2P_ENA);
 936
 937                 /* Start discharging VMID */
 938                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 939                                     WM8994_BIAS_SRC |
 940                                     WM8994_VMID_DISCH,
 941                                     WM8994_BIAS_SRC |
 942                                     WM8994_VMID_DISCH);
 943
 944                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 945                                     WM8994_VMID_SEL_MASK, 0);
 946
 947                 msleep(400);
 948
 949                 /* Active discharge */
 950                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 951                                     WM8994_LINEOUT1_DISCH |
 952                                     WM8994_LINEOUT2_DISCH,
 953                                     WM8994_LINEOUT1_DISCH |
 954                                     WM8994_LINEOUT2_DISCH);
 955
 956                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 957                                     WM8994_LINEOUT1N_ENA |
 958                                     WM8994_LINEOUT1P_ENA |
 959                                     WM8994_LINEOUT2N_ENA |
 960                                     WM8994_LINEOUT2P_ENA, 0);
 961
 962                 /* Switch off startup biases */
 963                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 964                                     WM8994_BIAS_SRC |
 965                                     WM8994_STARTUP_BIAS_ENA |
 966                                     WM8994_VMID_BUF_ENA |
 967                                     WM8994_VMID_RAMP_MASK, 0);
 968
 969                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 970                                     WM8994_VMID_SEL_MASK, 0);
 971         }
 972
 973         pm_runtime_put(codec->dev);
 974 }
 975
 976 static int vmid_event(struct snd_soc_dapm_widget *w,
 977                       struct snd_kcontrol *kcontrol, int event)
 978 {
 979         struct snd_soc_codec *codec = w->codec;
 980
 981         switch (event) {
 982         case SND_SOC_DAPM_PRE_PMU:
 983                 vmid_reference(codec);
 984                 break;
 985
 986         case SND_SOC_DAPM_POST_PMD:
 987                 vmid_dereference(codec);
 988                 break;
 989         }
 990
 991         return 0;
 992 }
 993
 994 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
 995 {
 996         int source = 0;  /* GCC flow analysis can't track enable */
 997         int reg, reg_r;
 998
 999         /* We also need the same AIF source for L/R and only one path */
1000         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1001         switch (reg) {
1002         case WM8994_AIF2DACL_TO_DAC1L:
1003                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1004                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1005                 break;
1006         case WM8994_AIF1DAC2L_TO_DAC1L:
1007                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1008                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1009                 break;
1010         case WM8994_AIF1DAC1L_TO_DAC1L:
1011                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1012                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1013                 break;
1014         default:
1015                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1016                 return false;
1017         }
1018
1019         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1020         if (reg_r != reg) {
1021                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1022                 return false;
1023         }
1024
1025         /* Set the source up */
1026         snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1027                             WM8994_CP_DYN_SRC_SEL_MASK, source);
1028
1029         return true;
1030 }
1031
1032 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1033                       struct snd_kcontrol *kcontrol, int event)
1034 {
1035         struct snd_soc_codec *codec = w->codec;
1036         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1037         struct wm8994 *control = wm8994->wm8994;
1038         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1039         int i;
1040         int dac;
1041         int adc;
1042         int val;
1043
1044         switch (control->type) {
1045         case WM8994:
1046         case WM8958:
1047                 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1048                 break;
1049         default:
1050                 break;
1051         }
1052
1053         switch (event) {
1054         case SND_SOC_DAPM_PRE_PMU:
1055                 /* Don't enable timeslot 2 if not in use */
1056                 if (wm8994->channels[0] <= 2)
1057                         mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1058
1059                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1060                 if ((val & WM8994_AIF1ADCL_SRC) &&
1061                     (val & WM8994_AIF1ADCR_SRC))
1062                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1063                 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1064                          !(val & WM8994_AIF1ADCR_SRC))
1065                         adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1066                 else
1067                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1068                                 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1069
1070                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1071                 if ((val & WM8994_AIF1DACL_SRC) &&
1072                     (val & WM8994_AIF1DACR_SRC))
1073                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1074                 else if (!(val & WM8994_AIF1DACL_SRC) &&
1075                          !(val & WM8994_AIF1DACR_SRC))
1076                         dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1077                 else
1078                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1079                                 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1080
1081                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1082                                     mask, adc);
1083                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1084                                     mask, dac);
1085                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1086                                     WM8994_AIF1DSPCLK_ENA |
1087                                     WM8994_SYSDSPCLK_ENA,
1088                                     WM8994_AIF1DSPCLK_ENA |
1089                                     WM8994_SYSDSPCLK_ENA);
1090                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1091                                     WM8994_AIF1ADC1R_ENA |
1092                                     WM8994_AIF1ADC1L_ENA |
1093                                     WM8994_AIF1ADC2R_ENA |
1094                                     WM8994_AIF1ADC2L_ENA);
1095                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1096                                     WM8994_AIF1DAC1R_ENA |
1097                                     WM8994_AIF1DAC1L_ENA |
1098                                     WM8994_AIF1DAC2R_ENA |
1099                                     WM8994_AIF1DAC2L_ENA);
1100                 break;
1101
1102         case SND_SOC_DAPM_POST_PMU:
1103                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1104                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1105                                       snd_soc_read(codec,
1106                                                    wm8994_vu_bits[i].reg));
1107                 break;
1108
1109         case SND_SOC_DAPM_PRE_PMD:
1110         case SND_SOC_DAPM_POST_PMD:
1111                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1112                                     mask, 0);
1113                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1114                                     mask, 0);
1115
1116                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1117                 if (val & WM8994_AIF2DSPCLK_ENA)
1118                         val = WM8994_SYSDSPCLK_ENA;
1119                 else
1120                         val = 0;
1121                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1122                                     WM8994_SYSDSPCLK_ENA |
1123                                     WM8994_AIF1DSPCLK_ENA, val);
1124                 break;
1125         }
1126
1127         return 0;
1128 }
1129
1130 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1131                       struct snd_kcontrol *kcontrol, int event)
1132 {
1133         struct snd_soc_codec *codec = w->codec;
1134         int i;
1135         int dac;
1136         int adc;
1137         int val;
1138
1139         switch (event) {
1140         case SND_SOC_DAPM_PRE_PMU:
1141                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1142                 if ((val & WM8994_AIF2ADCL_SRC) &&
1143                     (val & WM8994_AIF2ADCR_SRC))
1144                         adc = WM8994_AIF2ADCR_ENA;
1145                 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1146                          !(val & WM8994_AIF2ADCR_SRC))
1147                         adc = WM8994_AIF2ADCL_ENA;
1148                 else
1149                         adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1150
1151
1152                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1153                 if ((val & WM8994_AIF2DACL_SRC) &&
1154                     (val & WM8994_AIF2DACR_SRC))
1155                         dac = WM8994_AIF2DACR_ENA;
1156                 else if (!(val & WM8994_AIF2DACL_SRC) &&
1157                          !(val & WM8994_AIF2DACR_SRC))
1158                         dac = WM8994_AIF2DACL_ENA;
1159                 else
1160                         dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1161
1162                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1163                                     WM8994_AIF2ADCL_ENA |
1164                                     WM8994_AIF2ADCR_ENA, adc);
1165                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1166                                     WM8994_AIF2DACL_ENA |
1167                                     WM8994_AIF2DACR_ENA, dac);
1168                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1169                                     WM8994_AIF2DSPCLK_ENA |
1170                                     WM8994_SYSDSPCLK_ENA,
1171                                     WM8994_AIF2DSPCLK_ENA |
1172                                     WM8994_SYSDSPCLK_ENA);
1173                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1174                                     WM8994_AIF2ADCL_ENA |
1175                                     WM8994_AIF2ADCR_ENA,
1176                                     WM8994_AIF2ADCL_ENA |
1177                                     WM8994_AIF2ADCR_ENA);
1178                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1179                                     WM8994_AIF2DACL_ENA |
1180                                     WM8994_AIF2DACR_ENA,
1181                                     WM8994_AIF2DACL_ENA |
1182                                     WM8994_AIF2DACR_ENA);
1183                 break;
1184
1185         case SND_SOC_DAPM_POST_PMU:
1186                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1187                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1188                                       snd_soc_read(codec,
1189                                                    wm8994_vu_bits[i].reg));
1190                 break;
1191
1192         case SND_SOC_DAPM_PRE_PMD:
1193         case SND_SOC_DAPM_POST_PMD:
1194                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1195                                     WM8994_AIF2DACL_ENA |
1196                                     WM8994_AIF2DACR_ENA, 0);
1197                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1198                                     WM8994_AIF2ADCL_ENA |
1199                                     WM8994_AIF2ADCR_ENA, 0);
1200
1201                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1202                 if (val & WM8994_AIF1DSPCLK_ENA)
1203                         val = WM8994_SYSDSPCLK_ENA;
1204                 else
1205                         val = 0;
1206                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1207                                     WM8994_SYSDSPCLK_ENA |
1208                                     WM8994_AIF2DSPCLK_ENA, val);
1209                 break;
1210         }
1211
1212         return 0;
1213 }
1214
1215 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1216                            struct snd_kcontrol *kcontrol, int event)
1217 {
1218         struct snd_soc_codec *codec = w->codec;
1219         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1220
1221         switch (event) {
1222         case SND_SOC_DAPM_PRE_PMU:
1223                 wm8994->aif1clk_enable = 1;
1224                 break;
1225         case SND_SOC_DAPM_POST_PMD:
1226                 wm8994->aif1clk_disable = 1;
1227                 break;
1228         }
1229
1230         return 0;
1231 }
1232
1233 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1234                            struct snd_kcontrol *kcontrol, int event)
1235 {
1236         struct snd_soc_codec *codec = w->codec;
1237         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1238
1239         switch (event) {
1240         case SND_SOC_DAPM_PRE_PMU:
1241                 wm8994->aif2clk_enable = 1;
1242                 break;
1243         case SND_SOC_DAPM_POST_PMD:
1244                 wm8994->aif2clk_disable = 1;
1245                 break;
1246         }
1247
1248         return 0;
1249 }
1250
1251 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1252                           struct snd_kcontrol *kcontrol, int event)
1253 {
1254         struct snd_soc_codec *codec = w->codec;
1255         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1256
1257         switch (event) {
1258         case SND_SOC_DAPM_PRE_PMU:
1259                 if (wm8994->aif1clk_enable) {
1260                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1261                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1262                                             WM8994_AIF1CLK_ENA_MASK,
1263                                             WM8994_AIF1CLK_ENA);
1264                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1265                         wm8994->aif1clk_enable = 0;
1266                 }
1267                 if (wm8994->aif2clk_enable) {
1268                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1269                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1270                                             WM8994_AIF2CLK_ENA_MASK,
1271                                             WM8994_AIF2CLK_ENA);
1272                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1273                         wm8994->aif2clk_enable = 0;
1274                 }
1275                 break;
1276         }
1277
1278         /* We may also have postponed startup of DSP, handle that. */
1279         wm8958_aif_ev(w, kcontrol, event);
1280
1281         return 0;
1282 }
1283
1284 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1285                            struct snd_kcontrol *kcontrol, int event)
1286 {
1287         struct snd_soc_codec *codec = w->codec;
1288         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1289
1290         switch (event) {
1291         case SND_SOC_DAPM_POST_PMD:
1292                 if (wm8994->aif1clk_disable) {
1293                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1294                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1295                                             WM8994_AIF1CLK_ENA_MASK, 0);
1296                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1297                         wm8994->aif1clk_disable = 0;
1298                 }
1299                 if (wm8994->aif2clk_disable) {
1300                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1301                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1302                                             WM8994_AIF2CLK_ENA_MASK, 0);
1303                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1304                         wm8994->aif2clk_disable = 0;
1305                 }
1306                 break;
1307         }
1308
1309         return 0;
1310 }
1311
1312 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1313                       struct snd_kcontrol *kcontrol, int event)
1314 {
1315         late_enable_ev(w, kcontrol, event);
1316         return 0;
1317 }
1318
1319 static int micbias_ev(struct snd_soc_dapm_widget *w,
1320                       struct snd_kcontrol *kcontrol, int event)
1321 {
1322         late_enable_ev(w, kcontrol, event);
1323         return 0;
1324 }
1325
1326 static int dac_ev(struct snd_soc_dapm_widget *w,
1327                   struct snd_kcontrol *kcontrol, int event)
1328 {
1329         struct snd_soc_codec *codec = w->codec;
1330         unsigned int mask = 1 << w->shift;
1331
1332         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1333                             mask, mask);
1334         return 0;
1335 }
1336
1337 static const char *adc_mux_text[] = {
1338         "ADC",
1339         "DMIC",
1340 };
1341
1342 static const struct soc_enum adc_enum =
1343         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1344
1345 static const struct snd_kcontrol_new adcl_mux =
1346         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1347
1348 static const struct snd_kcontrol_new adcr_mux =
1349         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1350
1351 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1352 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1353 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1354 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1355 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1356 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1357 };
1358
1359 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1360 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1361 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1362 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1363 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1364 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1365 };
1366
1367 /* Debugging; dump chip status after DAPM transitions */
1368 static int post_ev(struct snd_soc_dapm_widget *w,
1369             struct snd_kcontrol *kcontrol, int event)
1370 {
1371         struct snd_soc_codec *codec = w->codec;
1372         dev_dbg(codec->dev, "SRC status: %x\n",
1373                 snd_soc_read(codec,
1374                              WM8994_RATE_STATUS));
1375         return 0;
1376 }
1377
1378 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1379 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1380                 1, 1, 0),
1381 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1382                 0, 1, 0),
1383 };
1384
1385 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1386 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1387                 1, 1, 0),
1388 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1389                 0, 1, 0),
1390 };
1391
1392 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1393 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1394                 1, 1, 0),
1395 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1396                 0, 1, 0),
1397 };
1398
1399 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1400 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1401                 1, 1, 0),
1402 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1403                 0, 1, 0),
1404 };
1405
1406 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1407 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1408                 5, 1, 0),
1409 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1410                 4, 1, 0),
1411 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412                 2, 1, 0),
1413 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414                 1, 1, 0),
1415 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1416                 0, 1, 0),
1417 };
1418
1419 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1420 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1421                 5, 1, 0),
1422 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1423                 4, 1, 0),
1424 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425                 2, 1, 0),
1426 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427                 1, 1, 0),
1428 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1429                 0, 1, 0),
1430 };
1431
1432 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1433         SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1434                 snd_soc_get_volsw, wm8994_put_class_w)
1435
1436 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1437                               struct snd_ctl_elem_value *ucontrol)
1438 {
1439         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1440         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1441         struct snd_soc_codec *codec = w->codec;
1442         int ret;
1443
1444         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1445
1446         wm_hubs_update_class_w(codec);
1447
1448         return ret;
1449 }
1450
1451 static const struct snd_kcontrol_new dac1l_mix[] = {
1452 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1453                       5, 1, 0),
1454 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455                       4, 1, 0),
1456 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457                       2, 1, 0),
1458 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459                       1, 1, 0),
1460 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461                       0, 1, 0),
1462 };
1463
1464 static const struct snd_kcontrol_new dac1r_mix[] = {
1465 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1466                       5, 1, 0),
1467 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468                       4, 1, 0),
1469 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470                       2, 1, 0),
1471 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472                       1, 1, 0),
1473 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474                       0, 1, 0),
1475 };
1476
1477 static const char *sidetone_text[] = {
1478         "ADC/DMIC1", "DMIC2",
1479 };
1480
1481 static const struct soc_enum sidetone1_enum =
1482         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1483
1484 static const struct snd_kcontrol_new sidetone1_mux =
1485         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1486
1487 static const struct soc_enum sidetone2_enum =
1488         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1489
1490 static const struct snd_kcontrol_new sidetone2_mux =
1491         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1492
1493 static const char *aif1dac_text[] = {
1494         "AIF1DACDAT", "AIF3DACDAT",
1495 };
1496
1497 static const struct soc_enum aif1dac_enum =
1498         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1499
1500 static const struct snd_kcontrol_new aif1dac_mux =
1501         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1502
1503 static const char *aif2dac_text[] = {
1504         "AIF2DACDAT", "AIF3DACDAT",
1505 };
1506
1507 static const struct soc_enum aif2dac_enum =
1508         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1509
1510 static const struct snd_kcontrol_new aif2dac_mux =
1511         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1512
1513 static const char *aif2adc_text[] = {
1514         "AIF2ADCDAT", "AIF3DACDAT",
1515 };
1516
1517 static const struct soc_enum aif2adc_enum =
1518         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1519
1520 static const struct snd_kcontrol_new aif2adc_mux =
1521         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1522
1523 static const char *aif3adc_text[] = {
1524         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1525 };
1526
1527 static const struct soc_enum wm8994_aif3adc_enum =
1528         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1529
1530 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1531         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1532
1533 static const struct soc_enum wm8958_aif3adc_enum =
1534         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1535
1536 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1537         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1538
1539 static const char *mono_pcm_out_text[] = {
1540         "None", "AIF2ADCL", "AIF2ADCR",
1541 };
1542
1543 static const struct soc_enum mono_pcm_out_enum =
1544         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1545
1546 static const struct snd_kcontrol_new mono_pcm_out_mux =
1547         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1548
1549 static const char *aif2dac_src_text[] = {
1550         "AIF2", "AIF3",
1551 };
1552
1553 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1554 static const struct soc_enum aif2dacl_src_enum =
1555         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1556
1557 static const struct snd_kcontrol_new aif2dacl_src_mux =
1558         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1559
1560 static const struct soc_enum aif2dacr_src_enum =
1561         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1562
1563 static const struct snd_kcontrol_new aif2dacr_src_mux =
1564         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1565
1566 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1567 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1568         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1569 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1570         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1571
1572 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1573         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1574 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1575         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1576 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1577         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1578 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1579         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1580 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1581         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1582
1583 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1584                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1585                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1586 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1587                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1588                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1589 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1590                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1591 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1592                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1593
1594 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1595 };
1596
1597 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1598 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1599                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1600                     SND_SOC_DAPM_PRE_PMD),
1601 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1602                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1603                     SND_SOC_DAPM_PRE_PMD),
1604 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1605 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1606                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1607 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1608                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1609 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1610 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1611 };
1612
1613 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1614 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1615         dac_ev, SND_SOC_DAPM_PRE_PMU),
1616 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1617         dac_ev, SND_SOC_DAPM_PRE_PMU),
1618 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1619         dac_ev, SND_SOC_DAPM_PRE_PMU),
1620 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1621         dac_ev, SND_SOC_DAPM_PRE_PMU),
1622 };
1623
1624 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1625 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1626 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1627 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1628 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1629 };
1630
1631 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1632 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1633                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1634 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1635                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1636 };
1637
1638 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1639 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1640 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1641 };
1642
1643 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1644 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1645 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1646 SND_SOC_DAPM_INPUT("Clock"),
1647
1648 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1649                       SND_SOC_DAPM_PRE_PMU),
1650 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1651                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1652
1653 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1654                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1655                     SND_SOC_DAPM_PRE_PMD),
1656
1657 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1658 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1659 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1660
1661 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1662                      0, SND_SOC_NOPM, 9, 0),
1663 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1664                      0, SND_SOC_NOPM, 8, 0),
1665 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1666                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1667                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1668 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1669                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1670                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1671
1672 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1673                      0, SND_SOC_NOPM, 11, 0),
1674 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1675                      0, SND_SOC_NOPM, 10, 0),
1676 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1677                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1678                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1679 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1680                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1681                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1682
1683 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1684                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1685 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1686                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1687
1688 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1689                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1690 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1691                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1692
1693 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1694                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1695 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1696                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1697
1698 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1699 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1700
1701 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1702                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1703 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1704                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1705
1706 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1707                      SND_SOC_NOPM, 13, 0),
1708 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1709                      SND_SOC_NOPM, 12, 0),
1710 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1711                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1712                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1713 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1714                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1715                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1716
1717 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1718 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1719 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1720 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1721
1722 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1723 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1724 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1725
1726 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1727 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1728
1729 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1730
1731 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1732 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1733 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1734 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1735
1736 /* Power is done with the muxes since the ADC power also controls the
1737  * downsampling chain, the chip will automatically manage the analogue
1738  * specific portions.
1739  */
1740 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1741 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1742
1743 SND_SOC_DAPM_POST("Debug log", post_ev),
1744 };
1745
1746 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1747 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1748 };
1749
1750 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1751 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1752 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1753 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1754 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1755 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1756 };
1757
1758 static const struct snd_soc_dapm_route intercon[] = {
1759         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1760         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1761
1762         { "DSP1CLK", NULL, "CLK_SYS" },
1763         { "DSP2CLK", NULL, "CLK_SYS" },
1764         { "DSPINTCLK", NULL, "CLK_SYS" },
1765
1766         { "AIF1ADC1L", NULL, "AIF1CLK" },
1767         { "AIF1ADC1L", NULL, "DSP1CLK" },
1768         { "AIF1ADC1R", NULL, "AIF1CLK" },
1769         { "AIF1ADC1R", NULL, "DSP1CLK" },
1770         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1771
1772         { "AIF1DAC1L", NULL, "AIF1CLK" },
1773         { "AIF1DAC1L", NULL, "DSP1CLK" },
1774         { "AIF1DAC1R", NULL, "AIF1CLK" },
1775         { "AIF1DAC1R", NULL, "DSP1CLK" },
1776         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1777
1778         { "AIF1ADC2L", NULL, "AIF1CLK" },
1779         { "AIF1ADC2L", NULL, "DSP1CLK" },
1780         { "AIF1ADC2R", NULL, "AIF1CLK" },
1781         { "AIF1ADC2R", NULL, "DSP1CLK" },
1782         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1783
1784         { "AIF1DAC2L", NULL, "AIF1CLK" },
1785         { "AIF1DAC2L", NULL, "DSP1CLK" },
1786         { "AIF1DAC2R", NULL, "AIF1CLK" },
1787         { "AIF1DAC2R", NULL, "DSP1CLK" },
1788         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1789
1790         { "AIF2ADCL", NULL, "AIF2CLK" },
1791         { "AIF2ADCL", NULL, "DSP2CLK" },
1792         { "AIF2ADCR", NULL, "AIF2CLK" },
1793         { "AIF2ADCR", NULL, "DSP2CLK" },
1794         { "AIF2ADCR", NULL, "DSPINTCLK" },
1795
1796         { "AIF2DACL", NULL, "AIF2CLK" },
1797         { "AIF2DACL", NULL, "DSP2CLK" },
1798         { "AIF2DACR", NULL, "AIF2CLK" },
1799         { "AIF2DACR", NULL, "DSP2CLK" },
1800         { "AIF2DACR", NULL, "DSPINTCLK" },
1801
1802         { "DMIC1L", NULL, "DMIC1DAT" },
1803         { "DMIC1L", NULL, "CLK_SYS" },
1804         { "DMIC1R", NULL, "DMIC1DAT" },
1805         { "DMIC1R", NULL, "CLK_SYS" },
1806         { "DMIC2L", NULL, "DMIC2DAT" },
1807         { "DMIC2L", NULL, "CLK_SYS" },
1808         { "DMIC2R", NULL, "DMIC2DAT" },
1809         { "DMIC2R", NULL, "CLK_SYS" },
1810
1811         { "ADCL", NULL, "AIF1CLK" },
1812         { "ADCL", NULL, "DSP1CLK" },
1813         { "ADCL", NULL, "DSPINTCLK" },
1814
1815         { "ADCR", NULL, "AIF1CLK" },
1816         { "ADCR", NULL, "DSP1CLK" },
1817         { "ADCR", NULL, "DSPINTCLK" },
1818
1819         { "ADCL Mux", "ADC", "ADCL" },
1820         { "ADCL Mux", "DMIC", "DMIC1L" },
1821         { "ADCR Mux", "ADC", "ADCR" },
1822         { "ADCR Mux", "DMIC", "DMIC1R" },
1823
1824         { "DAC1L", NULL, "AIF1CLK" },
1825         { "DAC1L", NULL, "DSP1CLK" },
1826         { "DAC1L", NULL, "DSPINTCLK" },
1827
1828         { "DAC1R", NULL, "AIF1CLK" },
1829         { "DAC1R", NULL, "DSP1CLK" },
1830         { "DAC1R", NULL, "DSPINTCLK" },
1831
1832         { "DAC2L", NULL, "AIF2CLK" },
1833         { "DAC2L", NULL, "DSP2CLK" },
1834         { "DAC2L", NULL, "DSPINTCLK" },
1835
1836         { "DAC2R", NULL, "AIF2DACR" },
1837         { "DAC2R", NULL, "AIF2CLK" },
1838         { "DAC2R", NULL, "DSP2CLK" },
1839         { "DAC2R", NULL, "DSPINTCLK" },
1840
1841         { "TOCLK", NULL, "CLK_SYS" },
1842
1843         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1844         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1845         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1846
1847         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1848         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1849         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1850
1851         /* AIF1 outputs */
1852         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1853         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1854         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1855
1856         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1857         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1858         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1859
1860         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1861         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1862         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1863
1864         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1865         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1866         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1867
1868         /* Pin level routing for AIF3 */
1869         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1870         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1871         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1872         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1873
1874         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1875         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1876         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1877         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1878         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1879         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1880         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1881
1882         /* DAC1 inputs */
1883         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1884         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1885         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1886         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1887         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1888
1889         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1890         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1891         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1892         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1893         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1894
1895         /* DAC2/AIF2 outputs  */
1896         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1897         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1898         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1899         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1900         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1901         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1902
1903         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1904         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1905         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1906         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1907         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1908         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1909
1910         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1911         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1912         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1913         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1914
1915         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1916
1917         /* AIF3 output */
1918         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1919         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1920         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1921         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1922         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1923         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1924         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1925         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1926
1927         /* Sidetone */
1928         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1929         { "Left Sidetone", "DMIC2", "DMIC2L" },
1930         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1931         { "Right Sidetone", "DMIC2", "DMIC2R" },
1932
1933         /* Output stages */
1934         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1935         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1936
1937         { "SPKL", "DAC1 Switch", "DAC1L" },
1938         { "SPKL", "DAC2 Switch", "DAC2L" },
1939
1940         { "SPKR", "DAC1 Switch", "DAC1R" },
1941         { "SPKR", "DAC2 Switch", "DAC2R" },
1942
1943         { "Left Headphone Mux", "DAC", "DAC1L" },
1944         { "Right Headphone Mux", "DAC", "DAC1R" },
1945 };
1946
1947 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1948         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1949         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1950         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1951         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1952         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1953         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1954         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1955         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1956 };
1957
1958 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1959         { "DAC1L", NULL, "DAC1L Mixer" },
1960         { "DAC1R", NULL, "DAC1R Mixer" },
1961         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1962         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1963 };
1964
1965 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1966         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1967         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1968         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1969         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1970         { "MICBIAS1", NULL, "CLK_SYS" },
1971         { "MICBIAS1", NULL, "MICBIAS Supply" },
1972         { "MICBIAS2", NULL, "CLK_SYS" },
1973         { "MICBIAS2", NULL, "MICBIAS Supply" },
1974 };
1975
1976 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1977         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1978         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1979         { "MICBIAS1", NULL, "VMID" },
1980         { "MICBIAS2", NULL, "VMID" },
1981 };
1982
1983 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1984         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1985         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1986
1987         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1988         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1989         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1990         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1991
1992         { "AIF3DACDAT", NULL, "AIF3" },
1993         { "AIF3ADCDAT", NULL, "AIF3" },
1994
1995         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1996         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1997
1998         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1999 };
2000
2001 /* The size in bits of the FLL divide multiplied by 10
2002  * to allow rounding later */
2003 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2004
2005 struct fll_div {
2006         u16 outdiv;
2007         u16 n;
2008         u16 k;
2009         u16 clk_ref_div;
2010         u16 fll_fratio;
2011 };
2012
2013 static int wm8994_get_fll_config(struct fll_div *fll,
2014                                  int freq_in, int freq_out)
2015 {
2016         u64 Kpart;
2017         unsigned int K, Ndiv, Nmod;
2018
2019         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2020
2021         /* Scale the input frequency down to <= 13.5MHz */
2022         fll->clk_ref_div = 0;
2023         while (freq_in > 13500000) {
2024                 fll->clk_ref_div++;
2025                 freq_in /= 2;
2026
2027                 if (fll->clk_ref_div > 3)
2028                         return -EINVAL;
2029         }
2030         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2031
2032         /* Scale the output to give 90MHz<=Fvco<=100MHz */
2033         fll->outdiv = 3;
2034         while (freq_out * (fll->outdiv + 1) < 90000000) {
2035                 fll->outdiv++;
2036                 if (fll->outdiv > 63)
2037                         return -EINVAL;
2038         }
2039         freq_out *= fll->outdiv + 1;
2040         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2041
2042         if (freq_in > 1000000) {
2043                 fll->fll_fratio = 0;
2044         } else if (freq_in > 256000) {
2045                 fll->fll_fratio = 1;
2046                 freq_in *= 2;
2047         } else if (freq_in > 128000) {
2048                 fll->fll_fratio = 2;
2049                 freq_in *= 4;
2050         } else if (freq_in > 64000) {
2051                 fll->fll_fratio = 3;
2052                 freq_in *= 8;
2053         } else {
2054                 fll->fll_fratio = 4;
2055                 freq_in *= 16;
2056         }
2057         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2058
2059         /* Now, calculate N.K */
2060         Ndiv = freq_out / freq_in;
2061
2062         fll->n = Ndiv;
2063         Nmod = freq_out % freq_in;
2064         pr_debug("Nmod=%d\n", Nmod);
2065
2066         /* Calculate fractional part - scale up so we can round. */
2067         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2068
2069         do_div(Kpart, freq_in);
2070
2071         K = Kpart & 0xFFFFFFFF;
2072
2073         if ((K % 10) >= 5)
2074                 K += 5;
2075
2076         /* Move down to proper range now rounding is done */
2077         fll->k = K / 10;
2078
2079         pr_debug("N=%x K=%x\n", fll->n, fll->k);
2080
2081         return 0;
2082 }
2083
2084 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2085                           unsigned int freq_in, unsigned int freq_out)
2086 {
2087         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2088         struct wm8994 *control = wm8994->wm8994;
2089         int reg_offset, ret;
2090         struct fll_div fll;
2091         u16 reg, clk1, aif_reg, aif_src;
2092         unsigned long timeout;
2093         bool was_enabled;
2094
2095         switch (id) {
2096         case WM8994_FLL1:
2097                 reg_offset = 0;
2098                 id = 0;
2099                 aif_src = 0x10;
2100                 break;
2101         case WM8994_FLL2:
2102                 reg_offset = 0x20;
2103                 id = 1;
2104                 aif_src = 0x18;
2105                 break;
2106         default:
2107                 return -EINVAL;
2108         }
2109
2110         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2111         was_enabled = reg & WM8994_FLL1_ENA;
2112
2113         switch (src) {
2114         case 0:
2115                 /* Allow no source specification when stopping */
2116                 if (freq_out)
2117                         return -EINVAL;
2118                 src = wm8994->fll[id].src;
2119                 break;
2120         case WM8994_FLL_SRC_MCLK1:
2121         case WM8994_FLL_SRC_MCLK2:
2122         case WM8994_FLL_SRC_LRCLK:
2123         case WM8994_FLL_SRC_BCLK:
2124                 break;
2125         case WM8994_FLL_SRC_INTERNAL:
2126                 freq_in = 12000000;
2127                 freq_out = 12000000;
2128                 break;
2129         default:
2130                 return -EINVAL;
2131         }
2132
2133         /* Are we changing anything? */
2134         if (wm8994->fll[id].src == src &&
2135             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2136                 return 0;
2137
2138         /* If we're stopping the FLL redo the old config - no
2139          * registers will actually be written but we avoid GCC flow
2140          * analysis bugs spewing warnings.
2141          */
2142         if (freq_out)
2143                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2144         else
2145                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2146                                             wm8994->fll[id].out);
2147         if (ret < 0)
2148                 return ret;
2149
2150         /* Make sure that we're not providing SYSCLK right now */
2151         clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2152         if (clk1 & WM8994_SYSCLK_SRC)
2153                 aif_reg = WM8994_AIF2_CLOCKING_1;
2154         else
2155                 aif_reg = WM8994_AIF1_CLOCKING_1;
2156         reg = snd_soc_read(codec, aif_reg);
2157
2158         if ((reg & WM8994_AIF1CLK_ENA) &&
2159             (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2160                 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2161                         id + 1);
2162                 return -EBUSY;
2163         }
2164
2165         /* We always need to disable the FLL while reconfiguring */
2166         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2167                             WM8994_FLL1_ENA, 0);
2168
2169         if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2170             freq_in == freq_out && freq_out) {
2171                 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2172                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2173                                     WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2174                 goto out;
2175         }
2176
2177         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2178                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2179         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2180                             WM8994_FLL1_OUTDIV_MASK |
2181                             WM8994_FLL1_FRATIO_MASK, reg);
2182
2183         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2184                             WM8994_FLL1_K_MASK, fll.k);
2185
2186         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2187                             WM8994_FLL1_N_MASK,
2188                             fll.n << WM8994_FLL1_N_SHIFT);
2189
2190         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2191                             WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2192                             WM8994_FLL1_REFCLK_DIV_MASK |
2193                             WM8994_FLL1_REFCLK_SRC_MASK,
2194                             ((src == WM8994_FLL_SRC_INTERNAL)
2195                              << WM8994_FLL1_FRC_NCO_SHIFT) |
2196                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2197                             (src - 1));
2198
2199         /* Clear any pending completion from a previous failure */
2200         try_wait_for_completion(&wm8994->fll_locked[id]);
2201
2202         /* Enable (with fractional mode if required) */
2203         if (freq_out) {
2204                 /* Enable VMID if we need it */
2205                 if (!was_enabled) {
2206                         active_reference(codec);
2207
2208                         switch (control->type) {
2209                         case WM8994:
2210                                 vmid_reference(codec);
2211                                 break;
2212                         case WM8958:
2213                                 if (control->revision < 1)
2214                                         vmid_reference(codec);
2215                                 break;
2216                         default:
2217                                 break;
2218                         }
2219                 }
2220
2221                 reg = WM8994_FLL1_ENA;
2222
2223                 if (fll.k)
2224                         reg |= WM8994_FLL1_FRAC;
2225                 if (src == WM8994_FLL_SRC_INTERNAL)
2226                         reg |= WM8994_FLL1_OSC_ENA;
2227
2228                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2229                                     WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2230                                     WM8994_FLL1_FRAC, reg);
2231
2232                 if (wm8994->fll_locked_irq) {
2233                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2234                                                               msecs_to_jiffies(10));
2235                         if (timeout == 0)
2236                                 dev_warn(codec->dev,
2237                                          "Timed out waiting for FLL lock\n");
2238                 } else {
2239                         msleep(5);
2240                 }
2241         } else {
2242                 if (was_enabled) {
2243                         switch (control->type) {
2244                         case WM8994:
2245                                 vmid_dereference(codec);
2246                                 break;
2247                         case WM8958:
2248                                 if (control->revision < 1)
2249                                         vmid_dereference(codec);
2250                                 break;
2251                         default:
2252                                 break;
2253                         }
2254
2255                         active_dereference(codec);
2256                 }
2257         }
2258
2259 out:
2260         wm8994->fll[id].in = freq_in;
2261         wm8994->fll[id].out = freq_out;
2262         wm8994->fll[id].src = src;
2263
2264         configure_clock(codec);
2265
2266         /*
2267          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2268          * for detection.
2269          */
2270         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2271                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2272
2273                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2274                         & WM8994_AIF1CLK_RATE_MASK;
2275                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2276                         & WM8994_AIF1CLK_RATE_MASK;
2277
2278                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2279                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2280                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2281                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2282         } else if (wm8994->aifdiv[0]) {
2283                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2284                                     WM8994_AIF1CLK_RATE_MASK,
2285                                     wm8994->aifdiv[0]);
2286                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2287                                     WM8994_AIF2CLK_RATE_MASK,
2288                                     wm8994->aifdiv[1]);
2289
2290                 wm8994->aifdiv[0] = 0;
2291                 wm8994->aifdiv[1] = 0;
2292         }
2293
2294         return 0;
2295 }
2296
2297 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2298 {
2299         struct completion *completion = data;
2300
2301         complete(completion);
2302
2303         return IRQ_HANDLED;
2304 }
2305
2306 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2307
2308 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2309                           unsigned int freq_in, unsigned int freq_out)
2310 {
2311         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2312 }
2313
2314 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2315                 int clk_id, unsigned int freq, int dir)
2316 {
2317         struct snd_soc_codec *codec = dai->codec;
2318         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2319         int i;
2320
2321         switch (dai->id) {
2322         case 1:
2323         case 2:
2324                 break;
2325
2326         default:
2327                 /* AIF3 shares clocking with AIF1/2 */
2328                 return -EINVAL;
2329         }
2330
2331         switch (clk_id) {
2332         case WM8994_SYSCLK_MCLK1:
2333                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2334                 wm8994->mclk[0] = freq;
2335                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2336                         dai->id, freq);
2337                 break;
2338
2339         case WM8994_SYSCLK_MCLK2:
2340                 /* TODO: Set GPIO AF */
2341                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2342                 wm8994->mclk[1] = freq;
2343                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2344                         dai->id, freq);
2345                 break;
2346
2347         case WM8994_SYSCLK_FLL1:
2348                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2349                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2350                 break;
2351
2352         case WM8994_SYSCLK_FLL2:
2353                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2354                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2355                 break;
2356
2357         case WM8994_SYSCLK_OPCLK:
2358                 /* Special case - a division (times 10) is given and
2359                  * no effect on main clocking.
2360                  */
2361                 if (freq) {
2362                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2363                                 if (opclk_divs[i] == freq)
2364                                         break;
2365                         if (i == ARRAY_SIZE(opclk_divs))
2366                                 return -EINVAL;
2367                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2368                                             WM8994_OPCLK_DIV_MASK, i);
2369                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2370                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2371                 } else {
2372                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2373                                             WM8994_OPCLK_ENA, 0);
2374                 }
2375
2376         default:
2377                 return -EINVAL;
2378         }
2379
2380         configure_clock(codec);
2381
2382         /*
2383          * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2384          * for detection.
2385          */
2386         if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2387                 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2388
2389                 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2390                         & WM8994_AIF1CLK_RATE_MASK;
2391                 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2392                         & WM8994_AIF1CLK_RATE_MASK;
2393
2394                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2395                                     WM8994_AIF1CLK_RATE_MASK, 0x1);
2396                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2397                                     WM8994_AIF2CLK_RATE_MASK, 0x1);
2398         } else if (wm8994->aifdiv[0]) {
2399                 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2400                                     WM8994_AIF1CLK_RATE_MASK,
2401                                     wm8994->aifdiv[0]);
2402                 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2403                                     WM8994_AIF2CLK_RATE_MASK,
2404                                     wm8994->aifdiv[1]);
2405
2406                 wm8994->aifdiv[0] = 0;
2407                 wm8994->aifdiv[1] = 0;
2408         }
2409
2410         return 0;
2411 }
2412
2413 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2414                                  enum snd_soc_bias_level level)
2415 {
2416         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2417         struct wm8994 *control = wm8994->wm8994;
2418
2419         wm_hubs_set_bias_level(codec, level);
2420
2421         switch (level) {
2422         case SND_SOC_BIAS_ON:
2423                 break;
2424
2425         case SND_SOC_BIAS_PREPARE:
2426                 /* MICBIAS into regulating mode */
2427                 switch (control->type) {
2428                 case WM8958:
2429                 case WM1811:
2430                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2431                                             WM8958_MICB1_MODE, 0);
2432                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2433                                             WM8958_MICB2_MODE, 0);
2434                         break;
2435                 default:
2436                         break;
2437                 }
2438
2439                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2440                         active_reference(codec);
2441                 break;
2442
2443         case SND_SOC_BIAS_STANDBY:
2444                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2445                         switch (control->type) {
2446                         case WM8958:
2447                                 if (control->revision == 0) {
2448                                         /* Optimise performance for rev A */
2449                                         snd_soc_update_bits(codec,
2450                                                             WM8958_CHARGE_PUMP_2,
2451                                                             WM8958_CP_DISCH,
2452                                                             WM8958_CP_DISCH);
2453                                 }
2454                                 break;
2455
2456                         default:
2457                                 break;
2458                         }
2459
2460                         /* Discharge LINEOUT1 & 2 */
2461                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2462                                             WM8994_LINEOUT1_DISCH |
2463                                             WM8994_LINEOUT2_DISCH,
2464                                             WM8994_LINEOUT1_DISCH |
2465                                             WM8994_LINEOUT2_DISCH);
2466                 }
2467
2468                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2469                         active_dereference(codec);
2470
2471                 /* MICBIAS into bypass mode on newer devices */
2472                 switch (control->type) {
2473                 case WM8958:
2474                 case WM1811:
2475                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2476                                             WM8958_MICB1_MODE,
2477                                             WM8958_MICB1_MODE);
2478                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2479                                             WM8958_MICB2_MODE,
2480                                             WM8958_MICB2_MODE);
2481                         break;
2482                 default:
2483                         break;
2484                 }
2485                 break;
2486
2487         case SND_SOC_BIAS_OFF:
2488                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2489                         wm8994->cur_fw = NULL;
2490                 break;
2491         }
2492
2493         codec->dapm.bias_level = level;
2494
2495         return 0;
2496 }
2497
2498 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2499 {
2500         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2501
2502         switch (mode) {
2503         case WM8994_VMID_NORMAL:
2504                 if (wm8994->hubs.lineout1_se) {
2505                         snd_soc_dapm_disable_pin(&codec->dapm,
2506                                                  "LINEOUT1N Driver");
2507                         snd_soc_dapm_disable_pin(&codec->dapm,
2508                                                  "LINEOUT1P Driver");
2509                 }
2510                 if (wm8994->hubs.lineout2_se) {
2511                         snd_soc_dapm_disable_pin(&codec->dapm,
2512                                                  "LINEOUT2N Driver");
2513                         snd_soc_dapm_disable_pin(&codec->dapm,
2514                                                  "LINEOUT2P Driver");
2515                 }
2516
2517                 /* Do the sync with the old mode to allow it to clean up */
2518                 snd_soc_dapm_sync(&codec->dapm);
2519                 wm8994->vmid_mode = mode;
2520                 break;
2521
2522         case WM8994_VMID_FORCE:
2523                 if (wm8994->hubs.lineout1_se) {
2524                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2525                                                       "LINEOUT1N Driver");
2526                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2527                                                       "LINEOUT1P Driver");
2528                 }
2529                 if (wm8994->hubs.lineout2_se) {
2530                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2531                                                       "LINEOUT2N Driver");
2532                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2533                                                       "LINEOUT2P Driver");
2534                 }
2535
2536                 wm8994->vmid_mode = mode;
2537                 snd_soc_dapm_sync(&codec->dapm);
2538                 break;
2539
2540         default:
2541                 return -EINVAL;
2542         }
2543
2544         return 0;
2545 }
2546
2547 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2548 {
2549         struct snd_soc_codec *codec = dai->codec;
2550         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2551         struct wm8994 *control = wm8994->wm8994;
2552         int ms_reg;
2553         int aif1_reg;
2554         int ms = 0;
2555         int aif1 = 0;
2556
2557         switch (dai->id) {
2558         case 1:
2559                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2560                 aif1_reg = WM8994_AIF1_CONTROL_1;
2561                 break;
2562         case 2:
2563                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2564                 aif1_reg = WM8994_AIF2_CONTROL_1;
2565                 break;
2566         default:
2567                 return -EINVAL;
2568         }
2569
2570         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2571         case SND_SOC_DAIFMT_CBS_CFS:
2572                 break;
2573         case SND_SOC_DAIFMT_CBM_CFM:
2574                 ms = WM8994_AIF1_MSTR;
2575                 break;
2576         default:
2577                 return -EINVAL;
2578         }
2579
2580         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2581         case SND_SOC_DAIFMT_DSP_B:
2582                 aif1 |= WM8994_AIF1_LRCLK_INV;
2583         case SND_SOC_DAIFMT_DSP_A:
2584                 aif1 |= 0x18;
2585                 break;
2586         case SND_SOC_DAIFMT_I2S:
2587                 aif1 |= 0x10;
2588                 break;
2589         case SND_SOC_DAIFMT_RIGHT_J:
2590                 break;
2591         case SND_SOC_DAIFMT_LEFT_J:
2592                 aif1 |= 0x8;
2593                 break;
2594         default:
2595                 return -EINVAL;
2596         }
2597
2598         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2599         case SND_SOC_DAIFMT_DSP_A:
2600         case SND_SOC_DAIFMT_DSP_B:
2601                 /* frame inversion not valid for DSP modes */
2602                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2603                 case SND_SOC_DAIFMT_NB_NF:
2604                         break;
2605                 case SND_SOC_DAIFMT_IB_NF:
2606                         aif1 |= WM8994_AIF1_BCLK_INV;
2607                         break;
2608                 default:
2609                         return -EINVAL;
2610                 }
2611                 break;
2612
2613         case SND_SOC_DAIFMT_I2S:
2614         case SND_SOC_DAIFMT_RIGHT_J:
2615         case SND_SOC_DAIFMT_LEFT_J:
2616                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2617                 case SND_SOC_DAIFMT_NB_NF:
2618                         break;
2619                 case SND_SOC_DAIFMT_IB_IF:
2620                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2621                         break;
2622                 case SND_SOC_DAIFMT_IB_NF:
2623                         aif1 |= WM8994_AIF1_BCLK_INV;
2624                         break;
2625                 case SND_SOC_DAIFMT_NB_IF:
2626                         aif1 |= WM8994_AIF1_LRCLK_INV;
2627                         break;
2628                 default:
2629                         return -EINVAL;
2630                 }
2631                 break;
2632         default:
2633                 return -EINVAL;
2634         }
2635
2636         /* The AIF2 format configuration needs to be mirrored to AIF3
2637          * on WM8958 if it's in use so just do it all the time. */
2638         switch (control->type) {
2639         case WM1811:
2640         case WM8958:
2641                 if (dai->id == 2)
2642                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2643                                             WM8994_AIF1_LRCLK_INV |
2644                                             WM8958_AIF3_FMT_MASK, aif1);
2645                 break;
2646
2647         default:
2648                 break;
2649         }
2650
2651         snd_soc_update_bits(codec, aif1_reg,
2652                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2653                             WM8994_AIF1_FMT_MASK,
2654                             aif1);
2655         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2656                             ms);
2657
2658         return 0;
2659 }
2660
2661 static struct {
2662         int val, rate;
2663 } srs[] = {
2664         { 0,   8000 },
2665         { 1,  11025 },
2666         { 2,  12000 },
2667         { 3,  16000 },
2668         { 4,  22050 },
2669         { 5,  24000 },
2670         { 6,  32000 },
2671         { 7,  44100 },
2672         { 8,  48000 },
2673         { 9,  88200 },
2674         { 10, 96000 },
2675 };
2676
2677 static int fs_ratios[] = {
2678         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2679 };
2680
2681 static int bclk_divs[] = {
2682         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2683         640, 880, 960, 1280, 1760, 1920
2684 };
2685
2686 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2687                             struct snd_pcm_hw_params *params,
2688                             struct snd_soc_dai *dai)
2689 {
2690         struct snd_soc_codec *codec = dai->codec;
2691         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2692         struct wm8994 *control = wm8994->wm8994;
2693         struct wm8994_pdata *pdata = &control->pdata;
2694         int aif1_reg;
2695         int aif2_reg;
2696         int bclk_reg;
2697         int lrclk_reg;
2698         int rate_reg;
2699         int aif1 = 0;
2700         int aif2 = 0;
2701         int bclk = 0;
2702         int lrclk = 0;
2703         int rate_val = 0;
2704         int id = dai->id - 1;
2705
2706         int i, cur_val, best_val, bclk_rate, best;
2707
2708         switch (dai->id) {
2709         case 1:
2710                 aif1_reg = WM8994_AIF1_CONTROL_1;
2711                 aif2_reg = WM8994_AIF1_CONTROL_2;
2712                 bclk_reg = WM8994_AIF1_BCLK;
2713                 rate_reg = WM8994_AIF1_RATE;
2714                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2715                     wm8994->lrclk_shared[0]) {
2716                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2717                 } else {
2718                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2719                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2720                 }
2721                 break;
2722         case 2:
2723                 aif1_reg = WM8994_AIF2_CONTROL_1;
2724                 aif2_reg = WM8994_AIF2_CONTROL_2;
2725                 bclk_reg = WM8994_AIF2_BCLK;
2726                 rate_reg = WM8994_AIF2_RATE;
2727                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2728                     wm8994->lrclk_shared[1]) {
2729                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2730                 } else {
2731                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2732                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2733                 }
2734                 break;
2735         default:
2736                 return -EINVAL;
2737         }
2738
2739         bclk_rate = params_rate(params);
2740         switch (params_format(params)) {
2741         case SNDRV_PCM_FORMAT_S16_LE:
2742                 bclk_rate *= 16;
2743                 break;
2744         case SNDRV_PCM_FORMAT_S20_3LE:
2745                 bclk_rate *= 20;
2746                 aif1 |= 0x20;
2747                 break;
2748         case SNDRV_PCM_FORMAT_S24_LE:
2749                 bclk_rate *= 24;
2750                 aif1 |= 0x40;
2751                 break;
2752         case SNDRV_PCM_FORMAT_S32_LE:
2753                 bclk_rate *= 32;
2754                 aif1 |= 0x60;
2755                 break;
2756         default:
2757                 return -EINVAL;
2758         }
2759
2760         wm8994->channels[id] = params_channels(params);
2761         if (pdata->max_channels_clocked[id] &&
2762             wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2763                 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2764                         pdata->max_channels_clocked[id], wm8994->channels[id]);
2765                 wm8994->channels[id] = pdata->max_channels_clocked[id];
2766         }
2767
2768         switch (wm8994->channels[id]) {
2769         case 1:
2770         case 2:
2771                 bclk_rate *= 2;
2772                 break;
2773         default:
2774                 bclk_rate *= 4;
2775                 break;
2776         }
2777
2778         /* Try to find an appropriate sample rate; look for an exact match. */
2779         for (i = 0; i < ARRAY_SIZE(srs); i++)
2780                 if (srs[i].rate == params_rate(params))
2781                         break;
2782         if (i == ARRAY_SIZE(srs))
2783                 return -EINVAL;
2784         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2785
2786         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2787         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2788                 dai->id, wm8994->aifclk[id], bclk_rate);
2789
2790         if (wm8994->channels[id] == 1 &&
2791             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2792                 aif2 |= WM8994_AIF1_MONO;
2793
2794         if (wm8994->aifclk[id] == 0) {
2795                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2796                 return -EINVAL;
2797         }
2798
2799         /* AIFCLK/fs ratio; look for a close match in either direction */
2800         best = 0;
2801         best_val = abs((fs_ratios[0] * params_rate(params))
2802                        - wm8994->aifclk[id]);
2803         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2804                 cur_val = abs((fs_ratios[i] * params_rate(params))
2805                               - wm8994->aifclk[id]);
2806                 if (cur_val >= best_val)
2807                         continue;
2808                 best = i;
2809                 best_val = cur_val;
2810         }
2811         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2812                 dai->id, fs_ratios[best]);
2813         rate_val |= best;
2814
2815         /* We may not get quite the right frequency if using
2816          * approximate clocks so look for the closest match that is
2817          * higher than the target (we need to ensure that there enough
2818          * BCLKs to clock out the samples).
2819          */
2820         best = 0;
2821         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2822                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2823                 if (cur_val < 0) /* BCLK table is sorted */
2824                         break;
2825                 best = i;
2826         }
2827         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2828         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2829                 bclk_divs[best], bclk_rate);
2830         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2831
2832         lrclk = bclk_rate / params_rate(params);
2833         if (!lrclk) {
2834                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2835                         bclk_rate);
2836                 return -EINVAL;
2837         }
2838         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2839                 lrclk, bclk_rate / lrclk);
2840
2841         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2842         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2843         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2844         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2845                             lrclk);
2846         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2847                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2848
2849         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2850                 switch (dai->id) {
2851                 case 1:
2852                         wm8994->dac_rates[0] = params_rate(params);
2853                         wm8994_set_retune_mobile(codec, 0);
2854                         wm8994_set_retune_mobile(codec, 1);
2855                         break;
2856                 case 2:
2857                         wm8994->dac_rates[1] = params_rate(params);
2858                         wm8994_set_retune_mobile(codec, 2);
2859                         break;
2860                 }
2861         }
2862
2863         return 0;
2864 }
2865
2866 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2867                                  struct snd_pcm_hw_params *params,
2868                                  struct snd_soc_dai *dai)
2869 {
2870         struct snd_soc_codec *codec = dai->codec;
2871         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2872         struct wm8994 *control = wm8994->wm8994;
2873         int aif1_reg;
2874         int aif1 = 0;
2875
2876         switch (dai->id) {
2877         case 3:
2878                 switch (control->type) {
2879                 case WM1811:
2880                 case WM8958:
2881                         aif1_reg = WM8958_AIF3_CONTROL_1;
2882                         break;
2883                 default:
2884                         return 0;
2885                 }
2886                 break;
2887         default:
2888                 return 0;
2889         }
2890
2891         switch (params_format(params)) {
2892         case SNDRV_PCM_FORMAT_S16_LE:
2893                 break;
2894         case SNDRV_PCM_FORMAT_S20_3LE:
2895                 aif1 |= 0x20;
2896                 break;
2897         case SNDRV_PCM_FORMAT_S24_LE:
2898                 aif1 |= 0x40;
2899                 break;
2900         case SNDRV_PCM_FORMAT_S32_LE:
2901                 aif1 |= 0x60;
2902                 break;
2903         default:
2904                 return -EINVAL;
2905         }
2906
2907         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2908 }
2909
2910 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2911 {
2912         struct snd_soc_codec *codec = codec_dai->codec;
2913         int mute_reg;
2914         int reg;
2915
2916         switch (codec_dai->id) {
2917         case 1:
2918                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2919                 break;
2920         case 2:
2921                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2922                 break;
2923         default:
2924                 return -EINVAL;
2925         }
2926
2927         if (mute)
2928                 reg = WM8994_AIF1DAC1_MUTE;
2929         else
2930                 reg = 0;
2931
2932         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2933
2934         return 0;
2935 }
2936
2937 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2938 {
2939         struct snd_soc_codec *codec = codec_dai->codec;
2940         int reg, val, mask;
2941
2942         switch (codec_dai->id) {
2943         case 1:
2944                 reg = WM8994_AIF1_MASTER_SLAVE;
2945                 mask = WM8994_AIF1_TRI;
2946                 break;
2947         case 2:
2948                 reg = WM8994_AIF2_MASTER_SLAVE;
2949                 mask = WM8994_AIF2_TRI;
2950                 break;
2951         default:
2952                 return -EINVAL;
2953         }
2954
2955         if (tristate)
2956                 val = mask;
2957         else
2958                 val = 0;
2959
2960         return snd_soc_update_bits(codec, reg, mask, val);
2961 }
2962
2963 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2964 {
2965         struct snd_soc_codec *codec = dai->codec;
2966
2967         /* Disable the pulls on the AIF if we're using it to save power. */
2968         snd_soc_update_bits(codec, WM8994_GPIO_3,
2969                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2970         snd_soc_update_bits(codec, WM8994_GPIO_4,
2971                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2972         snd_soc_update_bits(codec, WM8994_GPIO_5,
2973                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2974
2975         return 0;
2976 }
2977
2978 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2979
2980 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2981                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2982
2983 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2984         .set_sysclk     = wm8994_set_dai_sysclk,
2985         .set_fmt        = wm8994_set_dai_fmt,
2986         .hw_params      = wm8994_hw_params,
2987         .digital_mute   = wm8994_aif_mute,
2988         .set_pll        = wm8994_set_fll,
2989         .set_tristate   = wm8994_set_tristate,
2990 };
2991
2992 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2993         .set_sysclk     = wm8994_set_dai_sysclk,
2994         .set_fmt        = wm8994_set_dai_fmt,
2995         .hw_params      = wm8994_hw_params,
2996         .digital_mute   = wm8994_aif_mute,
2997         .set_pll        = wm8994_set_fll,
2998         .set_tristate   = wm8994_set_tristate,
2999 };
3000
3001 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3002         .hw_params      = wm8994_aif3_hw_params,
3003 };
3004
3005 static struct snd_soc_dai_driver wm8994_dai[] = {
3006         {
3007                 .name = "wm8994-aif1",
3008                 .id = 1,
3009                 .playback = {
3010                         .stream_name = "AIF1 Playback",
3011                         .channels_min = 1,
3012                         .channels_max = 2,
3013                         .rates = WM8994_RATES,
3014                         .formats = WM8994_FORMATS,
3015                         .sig_bits = 24,
3016                 },
3017                 .capture = {
3018                         .stream_name = "AIF1 Capture",
3019                         .channels_min = 1,
3020                         .channels_max = 2,
3021                         .rates = WM8994_RATES,
3022                         .formats = WM8994_FORMATS,
3023                         .sig_bits = 24,
3024                  },
3025                 .ops = &wm8994_aif1_dai_ops,
3026         },
3027         {
3028                 .name = "wm8994-aif2",
3029                 .id = 2,
3030                 .playback = {
3031                         .stream_name = "AIF2 Playback",
3032                         .channels_min = 1,
3033                         .channels_max = 2,
3034                         .rates = WM8994_RATES,
3035                         .formats = WM8994_FORMATS,
3036                         .sig_bits = 24,
3037                 },
3038                 .capture = {
3039                         .stream_name = "AIF2 Capture",
3040                         .channels_min = 1,
3041                         .channels_max = 2,
3042                         .rates = WM8994_RATES,
3043                         .formats = WM8994_FORMATS,
3044                         .sig_bits = 24,
3045                 },
3046                 .probe = wm8994_aif2_probe,
3047                 .ops = &wm8994_aif2_dai_ops,
3048         },
3049         {
3050                 .name = "wm8994-aif3",
3051                 .id = 3,
3052                 .playback = {
3053                         .stream_name = "AIF3 Playback",
3054                         .channels_min = 1,
3055                         .channels_max = 2,
3056                         .rates = WM8994_RATES,
3057                         .formats = WM8994_FORMATS,
3058                         .sig_bits = 24,
3059                 },
3060                 .capture = {
3061                         .stream_name = "AIF3 Capture",
3062                         .channels_min = 1,
3063                         .channels_max = 2,
3064                         .rates = WM8994_RATES,
3065                         .formats = WM8994_FORMATS,
3066                         .sig_bits = 24,
3067                  },
3068                 .ops = &wm8994_aif3_dai_ops,
3069         }
3070 };
3071
3072 #ifdef CONFIG_PM
3073 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3074 {
3075         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3076         int i, ret;
3077
3078         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3079                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3080                        sizeof(struct wm8994_fll_config));
3081                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3082                 if (ret < 0)
3083                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3084                                  i + 1, ret);
3085         }
3086
3087         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3088
3089         return 0;
3090 }
3091
3092 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3093 {
3094         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3095         struct wm8994 *control = wm8994->wm8994;
3096         int i, ret;
3097         unsigned int val, mask;
3098
3099         if (control->revision < 4) {
3100                 /* force a HW read */
3101                 ret = regmap_read(control->regmap,
3102                                   WM8994_POWER_MANAGEMENT_5, &val);
3103
3104                 /* modify the cache only */
3105                 codec->cache_only = 1;
3106                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3107                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3108                 val &= mask;
3109                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3110                                     mask, val);
3111                 codec->cache_only = 0;
3112         }
3113
3114         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3115                 if (!wm8994->fll_suspend[i].out)
3116                         continue;
3117
3118                 ret = _wm8994_set_fll(codec, i + 1,
3119                                      wm8994->fll_suspend[i].src,
3120                                      wm8994->fll_suspend[i].in,
3121                                      wm8994->fll_suspend[i].out);
3122                 if (ret < 0)
3123                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3124                                  i + 1, ret);
3125         }
3126
3127         return 0;
3128 }
3129 #else
3130 #define wm8994_codec_suspend NULL
3131 #define wm8994_codec_resume NULL
3132 #endif
3133
3134 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3135 {
3136         struct snd_soc_codec *codec = wm8994->hubs.codec;
3137         struct wm8994 *control = wm8994->wm8994;
3138         struct wm8994_pdata *pdata = &control->pdata;
3139         struct snd_kcontrol_new controls[] = {
3140                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3141                              wm8994->retune_mobile_enum,
3142                              wm8994_get_retune_mobile_enum,
3143                              wm8994_put_retune_mobile_enum),
3144                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3145                              wm8994->retune_mobile_enum,
3146                              wm8994_get_retune_mobile_enum,
3147                              wm8994_put_retune_mobile_enum),
3148                 SOC_ENUM_EXT("AIF2 EQ Mode",
3149                              wm8994->retune_mobile_enum,
3150                              wm8994_get_retune_mobile_enum,
3151                              wm8994_put_retune_mobile_enum),
3152         };
3153         int ret, i, j;
3154         const char **t;
3155
3156         /* We need an array of texts for the enum API but the number
3157          * of texts is likely to be less than the number of
3158          * configurations due to the sample rate dependency of the
3159          * configurations. */
3160         wm8994->num_retune_mobile_texts = 0;
3161         wm8994->retune_mobile_texts = NULL;
3162         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3163                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3164                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
3165                                    wm8994->retune_mobile_texts[j]) == 0)
3166                                 break;
3167                 }
3168
3169                 if (j != wm8994->num_retune_mobile_texts)
3170                         continue;
3171
3172                 /* Expand the array... */
3173                 t = krealloc(wm8994->retune_mobile_texts,
3174                              sizeof(char *) *
3175                              (wm8994->num_retune_mobile_texts + 1),
3176                              GFP_KERNEL);
3177                 if (t == NULL)
3178                         continue;
3179
3180                 /* ...store the new entry... */
3181                 t[wm8994->num_retune_mobile_texts] =
3182                         pdata->retune_mobile_cfgs[i].name;
3183
3184                 /* ...and remember the new version. */
3185                 wm8994->num_retune_mobile_texts++;
3186                 wm8994->retune_mobile_texts = t;
3187         }
3188
3189         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3190                 wm8994->num_retune_mobile_texts);
3191
3192         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3193         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3194
3195         ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3196                                    ARRAY_SIZE(controls));
3197         if (ret != 0)
3198                 dev_err(wm8994->hubs.codec->dev,
3199                         "Failed to add ReTune Mobile controls: %d\n", ret);
3200 }
3201
3202 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3203 {
3204         struct snd_soc_codec *codec = wm8994->hubs.codec;
3205         struct wm8994 *control = wm8994->wm8994;
3206         struct wm8994_pdata *pdata = &control->pdata;
3207         int ret, i;
3208
3209         if (!pdata)
3210                 return;
3211
3212         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3213                                       pdata->lineout2_diff,
3214                                       pdata->lineout1fb,
3215                                       pdata->lineout2fb,
3216                                       pdata->jd_scthr,
3217                                       pdata->jd_thr,
3218                                       pdata->micb1_delay,
3219                                       pdata->micb2_delay,
3220                                       pdata->micbias1_lvl,
3221                                       pdata->micbias2_lvl);
3222
3223         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3224
3225         if (pdata->num_drc_cfgs) {
3226                 struct snd_kcontrol_new controls[] = {
3227                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3228                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3229                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3230                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3231                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3232                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3233                 };
3234
3235                 /* We need an array of texts for the enum API */
3236                 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3237                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3238                 if (!wm8994->drc_texts) {
3239                         dev_err(wm8994->hubs.codec->dev,
3240                                 "Failed to allocate %d DRC config texts\n",
3241                                 pdata->num_drc_cfgs);
3242                         return;
3243                 }
3244
3245                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3246                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3247
3248                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3249                 wm8994->drc_enum.texts = wm8994->drc_texts;
3250
3251                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3252                                            ARRAY_SIZE(controls));
3253                 for (i = 0; i < WM8994_NUM_DRC; i++)
3254                         wm8994_set_drc(codec, i);
3255         } else {
3256                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3257                                                  wm8994_drc_controls,
3258                                                  ARRAY_SIZE(wm8994_drc_controls));
3259         }
3260
3261         if (ret != 0)
3262                 dev_err(wm8994->hubs.codec->dev,
3263                         "Failed to add DRC mode controls: %d\n", ret);
3264
3265
3266         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3267                 pdata->num_retune_mobile_cfgs);
3268
3269         if (pdata->num_retune_mobile_cfgs)
3270                 wm8994_handle_retune_mobile_pdata(wm8994);
3271         else
3272                 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3273                                      ARRAY_SIZE(wm8994_eq_controls));
3274
3275         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3276                 if (pdata->micbias[i]) {
3277                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3278                                 pdata->micbias[i] & 0xffff);
3279                 }
3280         }
3281 }
3282
3283 /**
3284  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3285  *
3286  * @codec:   WM8994 codec
3287  * @jack:    jack to report detection events on
3288  * @micbias: microphone bias to detect on
3289  *
3290  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3291  * being used to bring out signals to the processor then only platform
3292  * data configuration is needed for WM8994 and processor GPIOs should
3293  * be configured using snd_soc_jack_add_gpios() instead.
3294  *
3295  * Configuration of detection levels is available via the micbias1_lvl
3296  * and micbias2_lvl platform data members.
3297  */
3298 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3299                       int micbias)
3300 {
3301         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3302         struct wm8994_micdet *micdet;
3303         struct wm8994 *control = wm8994->wm8994;
3304         int reg, ret;
3305
3306         if (control->type != WM8994) {
3307                 dev_warn(codec->dev, "Not a WM8994\n");
3308                 return -EINVAL;
3309         }
3310
3311         switch (micbias) {
3312         case 1:
3313                 micdet = &wm8994->micdet[0];
3314                 if (jack)
3315                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3316                                                             "MICBIAS1");
3317                 else
3318                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3319                                                        "MICBIAS1");
3320                 break;
3321         case 2:
3322                 micdet = &wm8994->micdet[1];
3323                 if (jack)
3324                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3325                                                             "MICBIAS1");
3326                 else
3327                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3328                                                        "MICBIAS1");
3329                 break;
3330         default:
3331                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3332                 return -EINVAL;
3333         }
3334
3335         if (ret != 0)
3336                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3337                          micbias, ret);
3338
3339         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3340                 micbias, jack);
3341
3342         /* Store the configuration */
3343         micdet->jack = jack;
3344         micdet->detecting = true;
3345
3346         /* If either of the jacks is set up then enable detection */
3347         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3348                 reg = WM8994_MICD_ENA;
3349         else
3350                 reg = 0;
3351
3352         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3353
3354         /* enable MICDET and MICSHRT deboune */
3355         snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3356                             WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3357                             WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3358                             WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3359
3360         snd_soc_dapm_sync(&codec->dapm);
3361
3362         return 0;
3363 }
3364 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3365
3366 static void wm8994_mic_work(struct work_struct *work)
3367 {
3368         struct wm8994_priv *priv = container_of(work,
3369                                                 struct wm8994_priv,
3370                                                 mic_work.work);
3371         struct regmap *regmap = priv->wm8994->regmap;
3372         struct device *dev = priv->wm8994->dev;
3373         unsigned int reg;
3374         int ret;
3375         int report;
3376
3377         pm_runtime_get_sync(dev);
3378
3379         ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3380         if (ret < 0) {
3381                 dev_err(dev, "Failed to read microphone status: %d\n",
3382                         ret);
3383                 pm_runtime_put(dev);
3384                 return;
3385         }
3386
3387         dev_dbg(dev, "Microphone status: %x\n", reg);
3388
3389         report = 0;
3390         if (reg & WM8994_MIC1_DET_STS) {
3391                 if (priv->micdet[0].detecting)
3392                         report = SND_JACK_HEADSET;
3393         }
3394         if (reg & WM8994_MIC1_SHRT_STS) {
3395                 if (priv->micdet[0].detecting)
3396                         report = SND_JACK_HEADPHONE;
3397                 else
3398                         report |= SND_JACK_BTN_0;
3399         }
3400         if (report)
3401                 priv->micdet[0].detecting = false;
3402         else
3403                 priv->micdet[0].detecting = true;
3404
3405         snd_soc_jack_report(priv->micdet[0].jack, report,
3406                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3407
3408         report = 0;
3409         if (reg & WM8994_MIC2_DET_STS) {
3410                 if (priv->micdet[1].detecting)
3411                         report = SND_JACK_HEADSET;
3412         }
3413         if (reg & WM8994_MIC2_SHRT_STS) {
3414                 if (priv->micdet[1].detecting)
3415                         report = SND_JACK_HEADPHONE;
3416                 else
3417                         report |= SND_JACK_BTN_0;
3418         }
3419         if (report)
3420                 priv->micdet[1].detecting = false;
3421         else
3422                 priv->micdet[1].detecting = true;
3423
3424         snd_soc_jack_report(priv->micdet[1].jack, report,
3425                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3426
3427         pm_runtime_put(dev);
3428 }
3429
3430 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3431 {
3432         struct wm8994_priv *priv = data;
3433         struct snd_soc_codec *codec = priv->hubs.codec;
3434
3435 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3436         trace_snd_soc_jack_irq(dev_name(codec->dev));
3437 #endif
3438
3439         pm_wakeup_event(codec->dev, 300);
3440
3441         schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3442
3443         return IRQ_HANDLED;
3444 }
3445
3446 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3447 {
3448         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3449
3450         if (!wm8994->jackdet)
3451                 return;
3452
3453         mutex_lock(&wm8994->accdet_lock);
3454
3455         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3456
3457         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3458
3459         mutex_unlock(&wm8994->accdet_lock);
3460
3461         if (wm8994->wm8994->pdata.jd_ext_cap)
3462                 snd_soc_dapm_disable_pin(&codec->dapm,
3463                                          "MICBIAS2");
3464 }
3465
3466 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3467 {
3468         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3469         int report;
3470
3471         report = 0;
3472         if (status & 0x4)
3473                 report |= SND_JACK_BTN_0;
3474
3475         if (status & 0x8)
3476                 report |= SND_JACK_BTN_1;
3477
3478         if (status & 0x10)
3479                 report |= SND_JACK_BTN_2;
3480
3481         if (status & 0x20)
3482                 report |= SND_JACK_BTN_3;
3483
3484         if (status & 0x40)
3485                 report |= SND_JACK_BTN_4;
3486
3487         if (status & 0x80)
3488                 report |= SND_JACK_BTN_5;
3489
3490         snd_soc_jack_report(wm8994->micdet[0].jack, report,
3491                             wm8994->btn_mask);
3492 }
3493
3494 static void wm8958_mic_id(void *data, u16 status)
3495 {
3496         struct snd_soc_codec *codec = data;
3497         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3498
3499         /* Either nothing present or just starting detection */
3500         if (!(status & WM8958_MICD_STS)) {
3501                 /* If nothing present then clear our statuses */
3502                 dev_dbg(codec->dev, "Detected open circuit\n");
3503                 wm8994->jack_mic = false;
3504                 wm8994->mic_detecting = true;
3505
3506                 wm1811_micd_stop(codec);
3507
3508                 wm8958_micd_set_rate(codec);
3509
3510                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3511                                     wm8994->btn_mask |
3512                                     SND_JACK_HEADSET);
3513                 return;
3514         }
3515
3516         /* If the measurement is showing a high impedence we've got a
3517          * microphone.
3518          */
3519         if (status & 0x600) {
3520                 dev_dbg(codec->dev, "Detected microphone\n");
3521
3522                 wm8994->mic_detecting = false;
3523                 wm8994->jack_mic = true;
3524
3525                 wm8958_micd_set_rate(codec);
3526
3527                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3528                                     SND_JACK_HEADSET);
3529         }
3530
3531
3532         if (status & 0xfc) {
3533                 dev_dbg(codec->dev, "Detected headphone\n");
3534                 wm8994->mic_detecting = false;
3535
3536                 wm8958_micd_set_rate(codec);
3537
3538                 /* If we have jackdet that will detect removal */
3539                 wm1811_micd_stop(codec);
3540
3541                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3542                                     SND_JACK_HEADSET);
3543         }
3544 }
3545
3546 /* Deferred mic detection to allow for extra settling time */
3547 static void wm1811_mic_work(struct work_struct *work)
3548 {
3549         struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3550                                                   mic_work.work);
3551         struct wm8994 *control = wm8994->wm8994;
3552         struct snd_soc_codec *codec = wm8994->hubs.codec;
3553
3554         pm_runtime_get_sync(codec->dev);
3555
3556         /* If required for an external cap force MICBIAS on */
3557         if (control->pdata.jd_ext_cap) {
3558                 snd_soc_dapm_force_enable_pin(&codec->dapm,
3559                                               "MICBIAS2");
3560                 snd_soc_dapm_sync(&codec->dapm);
3561         }
3562
3563         mutex_lock(&wm8994->accdet_lock);
3564
3565         dev_dbg(codec->dev, "Starting mic detection\n");
3566
3567         /* Use a user-supplied callback if we have one */
3568         if (wm8994->micd_cb) {
3569                 wm8994->micd_cb(wm8994->micd_cb_data);
3570         } else {
3571                 /*
3572                  * Start off measument of microphone impedence to find out
3573                  * what's actually there.
3574                  */
3575                 wm8994->mic_detecting = true;
3576                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3577
3578                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3579                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3580         }
3581
3582         mutex_unlock(&wm8994->accdet_lock);
3583
3584         pm_runtime_put(codec->dev);
3585 }
3586
3587 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3588 {
3589         struct wm8994_priv *wm8994 = data;
3590         struct wm8994 *control = wm8994->wm8994;
3591         struct snd_soc_codec *codec = wm8994->hubs.codec;
3592         int reg, delay;
3593         bool present;
3594
3595         pm_runtime_get_sync(codec->dev);
3596
3597         mutex_lock(&wm8994->accdet_lock);
3598
3599         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3600         if (reg < 0) {
3601                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3602                 mutex_unlock(&wm8994->accdet_lock);
3603                 pm_runtime_put(codec->dev);
3604                 return IRQ_NONE;
3605         }
3606
3607         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3608
3609         present = reg & WM1811_JACKDET_LVL;
3610
3611         if (present) {
3612                 dev_dbg(codec->dev, "Jack detected\n");
3613
3614                 wm8958_micd_set_rate(codec);
3615
3616                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3617                                     WM8958_MICB2_DISCH, 0);
3618
3619                 /* Disable debounce while inserted */
3620                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3621                                     WM1811_JACKDET_DB, 0);
3622
3623                 delay = control->pdata.micdet_delay;
3624                 schedule_delayed_work(&wm8994->mic_work,
3625                                       msecs_to_jiffies(delay));
3626         } else {
3627                 dev_dbg(codec->dev, "Jack not detected\n");
3628
3629                 cancel_delayed_work_sync(&wm8994->mic_work);
3630
3631                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3632                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3633
3634                 /* Enable debounce while removed */
3635                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3636                                     WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3637
3638                 wm8994->mic_detecting = false;
3639                 wm8994->jack_mic = false;
3640                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3641                                     WM8958_MICD_ENA, 0);
3642                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3643         }
3644
3645         mutex_unlock(&wm8994->accdet_lock);
3646
3647         /* Turn off MICBIAS if it was on for an external cap */
3648         if (control->pdata.jd_ext_cap && !present)
3649                 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3650
3651         if (present)
3652                 snd_soc_jack_report(wm8994->micdet[0].jack,
3653                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3654         else
3655                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3656                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3657                                     wm8994->btn_mask);
3658
3659         /* Since we only report deltas force an update, ensures we
3660          * avoid bootstrapping issues with the core. */
3661         snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3662
3663         pm_runtime_put(codec->dev);
3664         return IRQ_HANDLED;
3665 }
3666
3667 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3668 {
3669         struct wm8994_priv *wm8994 = container_of(work,
3670                                                 struct wm8994_priv,
3671                                                 jackdet_bootstrap.work);
3672         wm1811_jackdet_irq(0, wm8994);
3673 }
3674
3675 /**
3676  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3677  *
3678  * @codec:   WM8958 codec
3679  * @jack:    jack to report detection events on
3680  *
3681  * Enable microphone detection functionality for the WM8958.  By
3682  * default simple detection which supports the detection of up to 6
3683  * buttons plus video and microphone functionality is supported.
3684  *
3685  * The WM8958 has an advanced jack detection facility which is able to
3686  * support complex accessory detection, especially when used in
3687  * conjunction with external circuitry.  In order to provide maximum
3688  * flexiblity a callback is provided which allows a completely custom
3689  * detection algorithm.
3690  */
3691 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3692                       wm1811_micdet_cb det_cb, void *det_cb_data,
3693                       wm1811_mic_id_cb id_cb, void *id_cb_data)
3694 {
3695         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3696         struct wm8994 *control = wm8994->wm8994;
3697         u16 micd_lvl_sel;
3698
3699         switch (control->type) {
3700         case WM1811:
3701         case WM8958:
3702                 break;
3703         default:
3704                 return -EINVAL;
3705         }
3706
3707         if (jack) {
3708                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3709                 snd_soc_dapm_sync(&codec->dapm);
3710
3711                 wm8994->micdet[0].jack = jack;
3712
3713                 if (det_cb) {
3714                         wm8994->micd_cb = det_cb;
3715                         wm8994->micd_cb_data = det_cb_data;
3716                 } else {
3717                         wm8994->mic_detecting = true;
3718                         wm8994->jack_mic = false;
3719                 }
3720
3721                 if (id_cb) {
3722                         wm8994->mic_id_cb = id_cb;
3723                         wm8994->mic_id_cb_data = id_cb_data;
3724                 } else {
3725                         wm8994->mic_id_cb = wm8958_mic_id;
3726                         wm8994->mic_id_cb_data = codec;
3727                 }
3728
3729                 wm8958_micd_set_rate(codec);
3730
3731                 /* Detect microphones and short circuits by default */
3732                 if (control->pdata.micd_lvl_sel)
3733                         micd_lvl_sel = control->pdata.micd_lvl_sel;
3734                 else
3735                         micd_lvl_sel = 0x41;
3736
3737                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3738                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3739                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3740
3741                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3742                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3743
3744                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3745
3746                 /*
3747                  * If we can use jack detection start off with that,
3748                  * otherwise jump straight to microphone detection.
3749                  */
3750                 if (wm8994->jackdet) {
3751                         /* Disable debounce for the initial detect */
3752                         snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3753                                             WM1811_JACKDET_DB, 0);
3754
3755                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3756                                             WM8958_MICB2_DISCH,
3757                                             WM8958_MICB2_DISCH);
3758                         snd_soc_update_bits(codec, WM8994_LDO_1,
3759                                             WM8994_LDO1_DISCH, 0);
3760                         wm1811_jackdet_set_mode(codec,
3761                                                 WM1811_JACKDET_MODE_JACK);
3762                 } else {
3763                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3764                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3765                 }
3766
3767         } else {
3768                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3769                                     WM8958_MICD_ENA, 0);
3770                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3771                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3772                 snd_soc_dapm_sync(&codec->dapm);
3773         }
3774
3775         return 0;
3776 }
3777 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3778
3779 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3780 {
3781         struct wm8994_priv *wm8994 = data;
3782         struct snd_soc_codec *codec = wm8994->hubs.codec;
3783         int reg, count, ret;
3784
3785         /*
3786          * Jack detection may have detected a removal simulataneously
3787          * with an update of the MICDET status; if so it will have
3788          * stopped detection and we can ignore this interrupt.
3789          */
3790         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3791                 return IRQ_HANDLED;
3792
3793         pm_runtime_get_sync(codec->dev);
3794
3795         /* We may occasionally read a detection without an impedence
3796          * range being provided - if that happens loop again.
3797          */
3798         count = 10;
3799         do {
3800                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3801                 if (reg < 0) {
3802                         dev_err(codec->dev,
3803                                 "Failed to read mic detect status: %d\n",
3804                                 reg);
3805                         pm_runtime_put(codec->dev);
3806                         return IRQ_NONE;
3807                 }
3808
3809                 if (!(reg & WM8958_MICD_VALID)) {
3810                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3811                         goto out;
3812                 }
3813
3814                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3815                         break;
3816
3817                 msleep(1);
3818         } while (count--);
3819
3820         if (count == 0)
3821                 dev_warn(codec->dev, "No impedance range reported for jack\n");
3822
3823 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3824         trace_snd_soc_jack_irq(dev_name(codec->dev));
3825 #endif
3826
3827         /* Avoid a transient report when the accessory is being removed */
3828         if (wm8994->jackdet) {
3829                 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3830                 if (ret < 0) {
3831                         dev_err(codec->dev, "Failed to read jack status: %d\n",
3832                                 ret);
3833                 } else if (!(ret & WM1811_JACKDET_LVL)) {
3834                         dev_dbg(codec->dev, "Ignoring removed jack\n");
3835                         goto out;
3836                 }
3837         } else if (!(reg & WM8958_MICD_STS)) {
3838                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3839                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3840                                     wm8994->btn_mask);
3841                 wm8994->mic_detecting = true;
3842                 goto out;
3843         }
3844
3845         if (wm8994->mic_detecting)
3846                 wm8994->mic_id_cb(wm8994->mic_id_cb_data, reg);
3847         else
3848                 wm8958_button_det(codec, reg);
3849
3850 out:
3851         pm_runtime_put(codec->dev);
3852         return IRQ_HANDLED;
3853 }
3854
3855 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3856 {
3857         struct snd_soc_codec *codec = data;
3858
3859         dev_err(codec->dev, "FIFO error\n");
3860
3861         return IRQ_HANDLED;
3862 }
3863
3864 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3865 {
3866         struct snd_soc_codec *codec = data;
3867
3868         dev_err(codec->dev, "Thermal warning\n");
3869
3870         return IRQ_HANDLED;
3871 }
3872
3873 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3874 {
3875         struct snd_soc_codec *codec = data;
3876
3877         dev_crit(codec->dev, "Thermal shutdown\n");
3878
3879         return IRQ_HANDLED;
3880 }
3881
3882 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3883 {
3884         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3885         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3886         struct snd_soc_dapm_context *dapm = &codec->dapm;
3887         unsigned int reg;
3888         int ret, i;
3889
3890         wm8994->hubs.codec = codec;
3891         codec->control_data = control->regmap;
3892
3893         snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3894
3895         mutex_init(&wm8994->accdet_lock);
3896         INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3897                           wm1811_jackdet_bootstrap);
3898
3899         switch (control->type) {
3900         case WM8994:
3901                 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3902                 break;
3903         case WM1811:
3904                 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3905                 break;
3906         default:
3907                 break;
3908         }
3909
3910         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3911                 init_completion(&wm8994->fll_locked[i]);
3912
3913         wm8994->micdet_irq = control->pdata.micdet_irq;
3914
3915         pm_runtime_enable(codec->dev);
3916         pm_runtime_idle(codec->dev);
3917
3918         /* By default use idle_bias_off, will override for WM8994 */
3919         codec->dapm.idle_bias_off = 1;
3920
3921         /* Set revision-specific configuration */
3922         switch (control->type) {
3923         case WM8994:
3924                 /* Single ended line outputs should have VMID on. */
3925                 if (!control->pdata.lineout1_diff ||
3926                     !control->pdata.lineout2_diff)
3927                         codec->dapm.idle_bias_off = 0;
3928
3929                 switch (control->revision) {
3930                 case 2:
3931                 case 3:
3932                         wm8994->hubs.dcs_codes_l = -5;
3933                         wm8994->hubs.dcs_codes_r = -5;
3934                         wm8994->hubs.hp_startup_mode = 1;
3935                         wm8994->hubs.dcs_readback_mode = 1;
3936                         wm8994->hubs.series_startup = 1;
3937                         break;
3938                 default:
3939                         wm8994->hubs.dcs_readback_mode = 2;
3940                         break;
3941                 }
3942                 break;
3943
3944         case WM8958:
3945                 wm8994->hubs.dcs_readback_mode = 1;
3946                 wm8994->hubs.hp_startup_mode = 1;
3947
3948                 switch (control->revision) {
3949                 case 0:
3950                         break;
3951                 default:
3952                         wm8994->fll_byp = true;
3953                         break;
3954                 }
3955                 break;
3956
3957         case WM1811:
3958                 wm8994->hubs.dcs_readback_mode = 2;
3959                 wm8994->hubs.no_series_update = 1;
3960                 wm8994->hubs.hp_startup_mode = 1;
3961                 wm8994->hubs.no_cache_dac_hp_direct = true;
3962                 wm8994->fll_byp = true;
3963
3964                 wm8994->hubs.dcs_codes_l = -9;
3965                 wm8994->hubs.dcs_codes_r = -7;
3966
3967                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3968                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3969                 break;
3970
3971         default:
3972                 break;
3973         }
3974
3975         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3976                            wm8994_fifo_error, "FIFO error", codec);
3977         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3978                            wm8994_temp_warn, "Thermal warning", codec);
3979         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3980                            wm8994_temp_shut, "Thermal shutdown", codec);
3981
3982         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3983                                  wm_hubs_dcs_done, "DC servo done",
3984                                  &wm8994->hubs);
3985         if (ret == 0)
3986                 wm8994->hubs.dcs_done_irq = true;
3987
3988         switch (control->type) {
3989         case WM8994:
3990                 if (wm8994->micdet_irq) {
3991                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3992                                                    wm8994_mic_irq,
3993                                                    IRQF_TRIGGER_RISING,
3994                                                    "Mic1 detect",
3995                                                    wm8994);
3996                         if (ret != 0)
3997                                 dev_warn(codec->dev,
3998                                          "Failed to request Mic1 detect IRQ: %d\n",
3999                                          ret);
4000                 }
4001
4002                 ret = wm8994_request_irq(wm8994->wm8994,
4003                                          WM8994_IRQ_MIC1_SHRT,
4004                                          wm8994_mic_irq, "Mic 1 short",
4005                                          wm8994);
4006                 if (ret != 0)
4007                         dev_warn(codec->dev,
4008                                  "Failed to request Mic1 short IRQ: %d\n",
4009                                  ret);
4010
4011                 ret = wm8994_request_irq(wm8994->wm8994,
4012                                          WM8994_IRQ_MIC2_DET,
4013                                          wm8994_mic_irq, "Mic 2 detect",
4014                                          wm8994);
4015                 if (ret != 0)
4016                         dev_warn(codec->dev,
4017                                  "Failed to request Mic2 detect IRQ: %d\n",
4018                                  ret);
4019
4020                 ret = wm8994_request_irq(wm8994->wm8994,
4021                                          WM8994_IRQ_MIC2_SHRT,
4022                                          wm8994_mic_irq, "Mic 2 short",
4023                                          wm8994);
4024                 if (ret != 0)
4025                         dev_warn(codec->dev,
4026                                  "Failed to request Mic2 short IRQ: %d\n",
4027                                  ret);
4028                 break;
4029
4030         case WM8958:
4031         case WM1811:
4032                 if (wm8994->micdet_irq) {
4033                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4034                                                    wm8958_mic_irq,
4035                                                    IRQF_TRIGGER_RISING,
4036                                                    "Mic detect",
4037                                                    wm8994);
4038                         if (ret != 0)
4039                                 dev_warn(codec->dev,
4040                                          "Failed to request Mic detect IRQ: %d\n",
4041                                          ret);
4042                 } else {
4043                         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4044                                            wm8958_mic_irq, "Mic detect",
4045                                            wm8994);
4046                 }
4047         }
4048
4049         switch (control->type) {
4050         case WM1811:
4051                 if (control->cust_id > 1 || control->revision > 1) {
4052                         ret = wm8994_request_irq(wm8994->wm8994,
4053                                                  WM8994_IRQ_GPIO(6),
4054                                                  wm1811_jackdet_irq, "JACKDET",
4055                                                  wm8994);
4056                         if (ret == 0)
4057                                 wm8994->jackdet = true;
4058                 }
4059                 break;
4060         default:
4061                 break;
4062         }
4063
4064         wm8994->fll_locked_irq = true;
4065         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4066                 ret = wm8994_request_irq(wm8994->wm8994,
4067                                          WM8994_IRQ_FLL1_LOCK + i,
4068                                          wm8994_fll_locked_irq, "FLL lock",
4069                                          &wm8994->fll_locked[i]);
4070                 if (ret != 0)
4071                         wm8994->fll_locked_irq = false;
4072         }
4073
4074         /* Make sure we can read from the GPIOs if they're inputs */
4075         pm_runtime_get_sync(codec->dev);
4076
4077         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
4078          * configured on init - if a system wants to do this dynamically
4079          * at runtime we can deal with that then.
4080          */
4081         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
4082         if (ret < 0) {
4083                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4084                 goto err_irq;
4085         }
4086         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4087                 wm8994->lrclk_shared[0] = 1;
4088                 wm8994_dai[0].symmetric_rates = 1;
4089         } else {
4090                 wm8994->lrclk_shared[0] = 0;
4091         }
4092
4093         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4094         if (ret < 0) {
4095                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4096                 goto err_irq;
4097         }
4098         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4099                 wm8994->lrclk_shared[1] = 1;
4100                 wm8994_dai[1].symmetric_rates = 1;
4101         } else {
4102                 wm8994->lrclk_shared[1] = 0;
4103         }
4104
4105         pm_runtime_put(codec->dev);
4106
4107         /* Latch volume update bits */
4108         for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4109                 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4110                                     wm8994_vu_bits[i].mask,
4111                                     wm8994_vu_bits[i].mask);
4112
4113         /* Set the low bit of the 3D stereo depth so TLV matches */
4114         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4115                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4116                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4117         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4118                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4119                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4120         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4121                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4122                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4123
4124         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4125          * use this; it only affects behaviour on idle TDM clock
4126          * cycles. */
4127         switch (control->type) {
4128         case WM8994:
4129         case WM8958:
4130                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4131                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4132                 break;
4133         default:
4134                 break;
4135         }
4136
4137         /* Put MICBIAS into bypass mode by default on newer devices */
4138         switch (control->type) {
4139         case WM8958:
4140         case WM1811:
4141                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4142                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4143                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4144                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4145                 break;
4146         default:
4147                 break;
4148         }
4149
4150         wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4151         wm_hubs_update_class_w(codec);
4152
4153         wm8994_handle_pdata(wm8994);
4154
4155         wm_hubs_add_analogue_controls(codec);
4156         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4157                              ARRAY_SIZE(wm8994_snd_controls));
4158         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4159                                   ARRAY_SIZE(wm8994_dapm_widgets));
4160
4161         switch (control->type) {
4162         case WM8994:
4163                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4164                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
4165                 if (control->revision < 4) {
4166                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4167                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4168                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4169                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4170                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4171                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4172                 } else {
4173                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4174                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4175                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4176                                                   ARRAY_SIZE(wm8994_adc_widgets));
4177                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4178                                                   ARRAY_SIZE(wm8994_dac_widgets));
4179                 }
4180                 break;
4181         case WM8958:
4182                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4183                                      ARRAY_SIZE(wm8958_snd_controls));
4184                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4185                                           ARRAY_SIZE(wm8958_dapm_widgets));
4186                 if (control->revision < 1) {
4187                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4188                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4189                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4190                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4191                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4192                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4193                 } else {
4194                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4195                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4196                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4197                                                   ARRAY_SIZE(wm8994_adc_widgets));
4198                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4199                                                   ARRAY_SIZE(wm8994_dac_widgets));
4200                 }
4201                 break;
4202
4203         case WM1811:
4204                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4205                                      ARRAY_SIZE(wm8958_snd_controls));
4206                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4207                                           ARRAY_SIZE(wm8958_dapm_widgets));
4208                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4209                                           ARRAY_SIZE(wm8994_lateclk_widgets));
4210                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4211                                           ARRAY_SIZE(wm8994_adc_widgets));
4212                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4213                                           ARRAY_SIZE(wm8994_dac_widgets));
4214                 break;
4215         }
4216
4217         wm_hubs_add_analogue_routes(codec, 0, 0);
4218         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4219
4220         switch (control->type) {
4221         case WM8994:
4222                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4223                                         ARRAY_SIZE(wm8994_intercon));
4224
4225                 if (control->revision < 4) {
4226                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4227                                                 ARRAY_SIZE(wm8994_revd_intercon));
4228                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4229                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4230                 } else {
4231                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4232                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4233                 }
4234                 break;
4235         case WM8958:
4236                 if (control->revision < 1) {
4237                         snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4238                                                 ARRAY_SIZE(wm8994_intercon));
4239                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4240                                                 ARRAY_SIZE(wm8994_revd_intercon));
4241                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4242                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4243                 } else {
4244                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4245                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4246                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4247                                                 ARRAY_SIZE(wm8958_intercon));
4248                 }
4249
4250                 wm8958_dsp2_init(codec);
4251                 break;
4252         case WM1811:
4253                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4254                                         ARRAY_SIZE(wm8994_lateclk_intercon));
4255                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4256                                         ARRAY_SIZE(wm8958_intercon));
4257                 break;
4258         }
4259
4260         return 0;
4261
4262 err_irq:
4263         if (wm8994->jackdet)
4264                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4265         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4266         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4267         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4268         if (wm8994->micdet_irq)
4269                 free_irq(wm8994->micdet_irq, wm8994);
4270         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4271                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4272                                 &wm8994->fll_locked[i]);
4273         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4274                         &wm8994->hubs);
4275         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4276         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4277         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4278
4279         return ret;
4280 }
4281
4282 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4283 {
4284         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4285         struct wm8994 *control = wm8994->wm8994;
4286         int i;
4287
4288         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4289
4290         pm_runtime_disable(codec->dev);
4291
4292         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4293                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4294                                 &wm8994->fll_locked[i]);
4295
4296         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4297                         &wm8994->hubs);
4298         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4299         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4300         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4301
4302         if (wm8994->jackdet)
4303                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4304
4305         switch (control->type) {
4306         case WM8994:
4307                 if (wm8994->micdet_irq)
4308                         free_irq(wm8994->micdet_irq, wm8994);
4309                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4310                                 wm8994);
4311                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4312                                 wm8994);
4313                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4314                                 wm8994);
4315                 break;
4316
4317         case WM1811:
4318         case WM8958:
4319                 if (wm8994->micdet_irq)
4320                         free_irq(wm8994->micdet_irq, wm8994);
4321                 break;
4322         }
4323         release_firmware(wm8994->mbc);
4324         release_firmware(wm8994->mbc_vss);
4325         release_firmware(wm8994->enh_eq);
4326         kfree(wm8994->retune_mobile_texts);
4327         return 0;
4328 }
4329
4330 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4331         .probe =        wm8994_codec_probe,
4332         .remove =       wm8994_codec_remove,
4333         .suspend =      wm8994_codec_suspend,
4334         .resume =       wm8994_codec_resume,
4335         .set_bias_level = wm8994_set_bias_level,
4336 };
4337
4338 static int wm8994_probe(struct platform_device *pdev)
4339 {
4340         struct wm8994_priv *wm8994;
4341
4342         wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4343                               GFP_KERNEL);
4344         if (wm8994 == NULL)
4345                 return -ENOMEM;
4346         platform_set_drvdata(pdev, wm8994);
4347
4348         wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4349
4350         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4351                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
4352 }
4353
4354 static int wm8994_remove(struct platform_device *pdev)
4355 {
4356         snd_soc_unregister_codec(&pdev->dev);
4357         return 0;
4358 }
4359
4360 #ifdef CONFIG_PM_SLEEP
4361 static int wm8994_suspend(struct device *dev)
4362 {
4363         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4364
4365         /* Drop down to power saving mode when system is suspended */
4366         if (wm8994->jackdet && !wm8994->active_refcount)
4367                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4368                                    WM1811_JACKDET_MODE_MASK,
4369                                    wm8994->jackdet_mode);
4370
4371         return 0;
4372 }
4373
4374 static int wm8994_resume(struct device *dev)
4375 {
4376         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4377
4378         if (wm8994->jackdet && wm8994->jackdet_mode)
4379                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4380                                    WM1811_JACKDET_MODE_MASK,
4381                                    WM1811_JACKDET_MODE_AUDIO);
4382
4383         return 0;
4384 }
4385 #endif
4386
4387 static const struct dev_pm_ops wm8994_pm_ops = {
4388         SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4389 };
4390
4391 static struct platform_driver wm8994_codec_driver = {
4392         .driver = {
4393                 .name = "wm8994-codec",
4394                 .owner = THIS_MODULE,
4395                 .pm = &wm8994_pm_ops,
4396         },
4397         .probe = wm8994_probe,
4398         .remove = wm8994_remove,
4399 };
4400
4401 module_platform_driver(wm8994_codec_driver);
4402
4403 MODULE_DESCRIPTION("ASoC WM8994 driver");
4404 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4405 MODULE_LICENSE("GPL");
4406 MODULE_ALIAS("platform:wm8994-codec");