drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
 122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 123 MODULE_PARM_DESC(preliminary_hw_support,
 124                 "Enable preliminary hardware support. "
 125                 "Enable Haswell and ValleyView Support. "
 126                 "(default: false)");
 127
 128 static struct drm_driver driver;
 129 extern int intel_agp_enabled;
 130
 131 #define INTEL_VGA_DEVICE(id, info) {            \
 132         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 133         .class_mask = 0xff0000,                 \
 134         .vendor = 0x8086,                       \
 135         .device = id,                           \
 136         .subvendor = PCI_ANY_ID,                \
 137         .subdevice = PCI_ANY_ID,                \
 138         .driver_data = (unsigned long) info }
 139
 140 static const struct intel_device_info intel_i830_info = {
 141         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 142         .has_overlay = 1, .overlay_needs_physical = 1,
 143 };
 144
 145 static const struct intel_device_info intel_845g_info = {
 146         .gen = 2,
 147         .has_overlay = 1, .overlay_needs_physical = 1,
 148 };
 149
 150 static const struct intel_device_info intel_i85x_info = {
 151         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 152         .cursor_needs_physical = 1,
 153         .has_overlay = 1, .overlay_needs_physical = 1,
 154 };
 155
 156 static const struct intel_device_info intel_i865g_info = {
 157         .gen = 2,
 158         .has_overlay = 1, .overlay_needs_physical = 1,
 159 };
 160
 161 static const struct intel_device_info intel_i915g_info = {
 162         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 163         .has_overlay = 1, .overlay_needs_physical = 1,
 164 };
 165 static const struct intel_device_info intel_i915gm_info = {
 166         .gen = 3, .is_mobile = 1,
 167         .cursor_needs_physical = 1,
 168         .has_overlay = 1, .overlay_needs_physical = 1,
 169         .supports_tv = 1,
 170 };
 171 static const struct intel_device_info intel_i945g_info = {
 172         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 173         .has_overlay = 1, .overlay_needs_physical = 1,
 174 };
 175 static const struct intel_device_info intel_i945gm_info = {
 176         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 177         .has_hotplug = 1, .cursor_needs_physical = 1,
 178         .has_overlay = 1, .overlay_needs_physical = 1,
 179         .supports_tv = 1,
 180 };
 181
 182 static const struct intel_device_info intel_i965g_info = {
 183         .gen = 4, .is_broadwater = 1,
 184         .has_hotplug = 1,
 185         .has_overlay = 1,
 186 };
 187
 188 static const struct intel_device_info intel_i965gm_info = {
 189         .gen = 4, .is_crestline = 1,
 190         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 191         .has_overlay = 1,
 192         .supports_tv = 1,
 193 };
 194
 195 static const struct intel_device_info intel_g33_info = {
 196         .gen = 3, .is_g33 = 1,
 197         .need_gfx_hws = 1, .has_hotplug = 1,
 198         .has_overlay = 1,
 199 };
 200
 201 static const struct intel_device_info intel_g45_info = {
 202         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 203         .has_pipe_cxsr = 1, .has_hotplug = 1,
 204         .has_bsd_ring = 1,
 205 };
 206
 207 static const struct intel_device_info intel_gm45_info = {
 208         .gen = 4, .is_g4x = 1,
 209         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 210         .has_pipe_cxsr = 1, .has_hotplug = 1,
 211         .supports_tv = 1,
 212         .has_bsd_ring = 1,
 213 };
 214
 215 static const struct intel_device_info intel_pineview_info = {
 216         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 217         .need_gfx_hws = 1, .has_hotplug = 1,
 218         .has_overlay = 1,
 219 };
 220
 221 static const struct intel_device_info intel_ironlake_d_info = {
 222         .gen = 5,
 223         .need_gfx_hws = 1, .has_hotplug = 1,
 224         .has_bsd_ring = 1,
 225 };
 226
 227 static const struct intel_device_info intel_ironlake_m_info = {
 228         .gen = 5, .is_mobile = 1,
 229         .need_gfx_hws = 1, .has_hotplug = 1,
 230         .has_fbc = 1,
 231         .has_bsd_ring = 1,
 232 };
 233
 234 static const struct intel_device_info intel_sandybridge_d_info = {
 235         .gen = 6,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_bsd_ring = 1,
 238         .has_blt_ring = 1,
 239         .has_llc = 1,
 240         .has_force_wake = 1,
 241 };
 242
 243 static const struct intel_device_info intel_sandybridge_m_info = {
 244         .gen = 6, .is_mobile = 1,
 245         .need_gfx_hws = 1, .has_hotplug = 1,
 246         .has_fbc = 1,
 247         .has_bsd_ring = 1,
 248         .has_blt_ring = 1,
 249         .has_llc = 1,
 250         .has_force_wake = 1,
 251 };
 252
 253 static const struct intel_device_info intel_ivybridge_d_info = {
 254         .is_ivybridge = 1, .gen = 7,
 255         .need_gfx_hws = 1, .has_hotplug = 1,
 256         .has_bsd_ring = 1,
 257         .has_blt_ring = 1,
 258         .has_llc = 1,
 259         .has_force_wake = 1,
 260 };
 261
 262 static const struct intel_device_info intel_ivybridge_m_info = {
 263         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 264         .need_gfx_hws = 1, .has_hotplug = 1,
 265         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 266         .has_bsd_ring = 1,
 267         .has_blt_ring = 1,
 268         .has_llc = 1,
 269         .has_force_wake = 1,
 270 };
 271
 272 static const struct intel_device_info intel_valleyview_m_info = {
 273         .gen = 7, .is_mobile = 1,
 274         .need_gfx_hws = 1, .has_hotplug = 1,
 275         .has_fbc = 0,
 276         .has_bsd_ring = 1,
 277         .has_blt_ring = 1,
 278         .is_valleyview = 1,
 279         .display_mmio_offset = VLV_DISPLAY_BASE,
 280 };
 281
 282 static const struct intel_device_info intel_valleyview_d_info = {
 283         .gen = 7,
 284         .need_gfx_hws = 1, .has_hotplug = 1,
 285         .has_fbc = 0,
 286         .has_bsd_ring = 1,
 287         .has_blt_ring = 1,
 288         .is_valleyview = 1,
 289         .display_mmio_offset = VLV_DISPLAY_BASE,
 290 };
 291
 292 static const struct intel_device_info intel_haswell_d_info = {
 293         .is_haswell = 1, .gen = 7,
 294         .need_gfx_hws = 1, .has_hotplug = 1,
 295         .has_bsd_ring = 1,
 296         .has_blt_ring = 1,
 297         .has_llc = 1,
 298         .has_force_wake = 1,
 299 };
 300
 301 static const struct intel_device_info intel_haswell_m_info = {
 302         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 303         .need_gfx_hws = 1, .has_hotplug = 1,
 304         .has_bsd_ring = 1,
 305         .has_blt_ring = 1,
 306         .has_llc = 1,
 307         .has_force_wake = 1,
 308 };
 309
 310 static const struct pci_device_id pciidlist[] = {               /* aka */
 311         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 312         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 313         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 314         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 315         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 316         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 317         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 318         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 319         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 320         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 321         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 322         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 323         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 324         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 325         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 326         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 327         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 328         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 329         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 330         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 331         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 332         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 333         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 334         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 335         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 336         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 337         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 338         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 339         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 340         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 341         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 342         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 343         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 344         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 345         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 346         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 347         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 348         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 349         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 350         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 351         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 352         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 353         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 354         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 355         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 356         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 357         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 358         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 359         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 360         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 361         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 362         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 363         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 364         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 365         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 366         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 367         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 368         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 369         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 370         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 371         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 372         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 373         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 374         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 375         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 376         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 377         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 378         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 379         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 380         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 381         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 382         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
 383         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 384         INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
 385         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
 386         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 387         INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
 388         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
 389         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 390         INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
 391         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 392         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 393         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 394         {0, 0, 0}
 395 };
 396
 397 #if defined(CONFIG_DRM_I915_KMS)
 398 MODULE_DEVICE_TABLE(pci, pciidlist);
 399 #endif
 400
 401 void intel_detect_pch(struct drm_device *dev)
 402 {
 403         struct drm_i915_private *dev_priv = dev->dev_private;
 404         struct pci_dev *pch;
 405
 406         /*
 407          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 408          * make graphics device passthrough work easy for VMM, that only
 409          * need to expose ISA bridge to let driver know the real hardware
 410          * underneath. This is a requirement from virtualization team.
 411          */
 412         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 413         if (pch) {
 414                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 415                         unsigned short id;
 416                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 417                         dev_priv->pch_id = id;
 418
 419                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 420                                 dev_priv->pch_type = PCH_IBX;
 421                                 dev_priv->num_pch_pll = 2;
 422                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 423                                 WARN_ON(!IS_GEN5(dev));
 424                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 425                                 dev_priv->pch_type = PCH_CPT;
 426                                 dev_priv->num_pch_pll = 2;
 427                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 428                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 429                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 430                                 /* PantherPoint is CPT compatible */
 431                                 dev_priv->pch_type = PCH_CPT;
 432                                 dev_priv->num_pch_pll = 2;
 433                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 434                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 435                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 436                                 dev_priv->pch_type = PCH_LPT;
 437                                 dev_priv->num_pch_pll = 0;
 438                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 439                                 WARN_ON(!IS_HASWELL(dev));
 440                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 441                                 dev_priv->pch_type = PCH_LPT;
 442                                 dev_priv->num_pch_pll = 0;
 443                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 444                                 WARN_ON(!IS_HASWELL(dev));
 445                         }
 446                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 447                 }
 448                 pci_dev_put(pch);
 449         }
 450 }
 451
 452 bool i915_semaphore_is_enabled(struct drm_device *dev)
 453 {
 454         if (INTEL_INFO(dev)->gen < 6)
 455                 return 0;
 456
 457         if (i915_semaphores >= 0)
 458                 return i915_semaphores;
 459
 460 #ifdef CONFIG_INTEL_IOMMU
 461         /* Enable semaphores on SNB when IO remapping is off */
 462         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 463                 return false;
 464 #endif
 465
 466         return 1;
 467 }
 468
 469 static int i915_drm_freeze(struct drm_device *dev)
 470 {
 471         struct drm_i915_private *dev_priv = dev->dev_private;
 472
 473         intel_set_power_well(dev, true);
 474
 475         drm_kms_helper_poll_disable(dev);
 476
 477         pci_save_state(dev->pdev);
 478
 479         /* If KMS is active, we do the leavevt stuff here */
 480         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 481                 int error = i915_gem_idle(dev);
 482                 if (error) {
 483                         dev_err(&dev->pdev->dev,
 484                                 "GEM idle failed, resume might fail\n");
 485                         return error;
 486                 }
 487
 488                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 489
 490                 intel_modeset_disable(dev);
 491
 492                 drm_irq_uninstall(dev);
 493         }
 494
 495         i915_save_state(dev);
 496
 497         intel_opregion_fini(dev);
 498
 499         /* Modeset on resume, not lid events */
 500         dev_priv->modeset_on_lid = 0;
 501
 502         console_lock();
 503         intel_fbdev_set_suspend(dev, 1);
 504         console_unlock();
 505
 506         return 0;
 507 }
 508
 509 int i915_suspend(struct drm_device *dev, pm_message_t state)
 510 {
 511         int error;
 512
 513         if (!dev || !dev->dev_private) {
 514                 DRM_ERROR("dev: %p\n", dev);
 515                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 516                 return -ENODEV;
 517         }
 518
 519         if (state.event == PM_EVENT_PRETHAW)
 520                 return 0;
 521
 522
 523         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 524                 return 0;
 525
 526         error = i915_drm_freeze(dev);
 527         if (error)
 528                 return error;
 529
 530         if (state.event == PM_EVENT_SUSPEND) {
 531                 /* Shut down the device */
 532                 pci_disable_device(dev->pdev);
 533                 pci_set_power_state(dev->pdev, PCI_D3hot);
 534         }
 535
 536         return 0;
 537 }
 538
 539 void intel_console_resume(struct work_struct *work)
 540 {
 541         struct drm_i915_private *dev_priv =
 542                 container_of(work, struct drm_i915_private,
 543                              console_resume_work);
 544         struct drm_device *dev = dev_priv->dev;
 545
 546         console_lock();
 547         intel_fbdev_set_suspend(dev, 0);
 548         console_unlock();
 549 }
 550
 551 static int __i915_drm_thaw(struct drm_device *dev)
 552 {
 553         struct drm_i915_private *dev_priv = dev->dev_private;
 554         int error = 0;
 555
 556         i915_restore_state(dev);
 557         intel_opregion_setup(dev);
 558
 559         /* KMS EnterVT equivalent */
 560         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 561                 intel_init_pch_refclk(dev);
 562
 563                 mutex_lock(&dev->struct_mutex);
 564                 dev_priv->mm.suspended = 0;
 565
 566                 error = i915_gem_init_hw(dev);
 567                 mutex_unlock(&dev->struct_mutex);
 568
 569                 intel_modeset_init_hw(dev);
 570                 intel_modeset_setup_hw_state(dev, false);
 571                 drm_irq_install(dev);
 572                 intel_hpd_init(dev);
 573         }
 574
 575         intel_opregion_init(dev);
 576
 577         dev_priv->modeset_on_lid = 0;
 578
 579         /*
 580          * The console lock can be pretty contented on resume due
 581          * to all the printk activity.  Try to keep it out of the hot
 582          * path of resume if possible.
 583          */
 584         if (console_trylock()) {
 585                 intel_fbdev_set_suspend(dev, 0);
 586                 console_unlock();
 587         } else {
 588                 schedule_work(&dev_priv->console_resume_work);
 589         }
 590
 591         return error;
 592 }
 593
 594 static int i915_drm_thaw(struct drm_device *dev)
 595 {
 596         int error = 0;
 597
 598         intel_gt_reset(dev);
 599
 600         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 601                 mutex_lock(&dev->struct_mutex);
 602                 i915_gem_restore_gtt_mappings(dev);
 603                 mutex_unlock(&dev->struct_mutex);
 604         }
 605
 606         __i915_drm_thaw(dev);
 607
 608         return error;
 609 }
 610
 611 int i915_resume(struct drm_device *dev)
 612 {
 613         struct drm_i915_private *dev_priv = dev->dev_private;
 614         int ret;
 615
 616         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 617                 return 0;
 618
 619         if (pci_enable_device(dev->pdev))
 620                 return -EIO;
 621
 622         pci_set_master(dev->pdev);
 623
 624         intel_gt_reset(dev);
 625
 626         /*
 627          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 628          * earlier) need this since the BIOS might clear all our scratch PTEs.
 629          */
 630         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 631             !dev_priv->opregion.header) {
 632                 mutex_lock(&dev->struct_mutex);
 633                 i915_gem_restore_gtt_mappings(dev);
 634                 mutex_unlock(&dev->struct_mutex);
 635         }
 636
 637         ret = __i915_drm_thaw(dev);
 638         if (ret)
 639                 return ret;
 640
 641         drm_kms_helper_poll_enable(dev);
 642         return 0;
 643 }
 644
 645 static int i8xx_do_reset(struct drm_device *dev)
 646 {
 647         struct drm_i915_private *dev_priv = dev->dev_private;
 648
 649         if (IS_I85X(dev))
 650                 return -ENODEV;
 651
 652         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 653         POSTING_READ(D_STATE);
 654
 655         if (IS_I830(dev) || IS_845G(dev)) {
 656                 I915_WRITE(DEBUG_RESET_I830,
 657                            DEBUG_RESET_DISPLAY |
 658                            DEBUG_RESET_RENDER |
 659                            DEBUG_RESET_FULL);
 660                 POSTING_READ(DEBUG_RESET_I830);
 661                 msleep(1);
 662
 663                 I915_WRITE(DEBUG_RESET_I830, 0);
 664                 POSTING_READ(DEBUG_RESET_I830);
 665         }
 666
 667         msleep(1);
 668
 669         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 670         POSTING_READ(D_STATE);
 671
 672         return 0;
 673 }
 674
 675 static int i965_reset_complete(struct drm_device *dev)
 676 {
 677         u8 gdrst;
 678         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 679         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 680 }
 681
 682 static int i965_do_reset(struct drm_device *dev)
 683 {
 684         int ret;
 685         u8 gdrst;
 686
 687         /*
 688          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 689          * well as the reset bit (GR/bit 0).  Setting the GR bit
 690          * triggers the reset; when done, the hardware will clear it.
 691          */
 692         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 693         pci_write_config_byte(dev->pdev, I965_GDRST,
 694                               gdrst | GRDOM_RENDER |
 695                               GRDOM_RESET_ENABLE);
 696         ret =  wait_for(i965_reset_complete(dev), 500);
 697         if (ret)
 698                 return ret;
 699
 700         /* We can't reset render&media without also resetting display ... */
 701         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 702         pci_write_config_byte(dev->pdev, I965_GDRST,
 703                               gdrst | GRDOM_MEDIA |
 704                               GRDOM_RESET_ENABLE);
 705
 706         return wait_for(i965_reset_complete(dev), 500);
 707 }
 708
 709 static int ironlake_do_reset(struct drm_device *dev)
 710 {
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         u32 gdrst;
 713         int ret;
 714
 715         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 716         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 717                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 718         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 719         if (ret)
 720                 return ret;
 721
 722         /* We can't reset render&media without also resetting display ... */
 723         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 724         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 725                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 726         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 727 }
 728
 729 static int gen6_do_reset(struct drm_device *dev)
 730 {
 731         struct drm_i915_private *dev_priv = dev->dev_private;
 732         int     ret;
 733         unsigned long irqflags;
 734
 735         /* Hold gt_lock across reset to prevent any register access
 736          * with forcewake not set correctly
 737          */
 738         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 739
 740         /* Reset the chip */
 741
 742         /* GEN6_GDRST is not in the gt power well, no need to check
 743          * for fifo space for the write or forcewake the chip for
 744          * the read
 745          */
 746         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 747
 748         /* Spin waiting for the device to ack the reset request */
 749         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 750
 751         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 752         if (dev_priv->forcewake_count)
 753                 dev_priv->gt.force_wake_get(dev_priv);
 754         else
 755                 dev_priv->gt.force_wake_put(dev_priv);
 756
 757         /* Restore fifo count */
 758         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 759
 760         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 761         return ret;
 762 }
 763
 764 int intel_gpu_reset(struct drm_device *dev)
 765 {
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         int ret = -ENODEV;
 768
 769         switch (INTEL_INFO(dev)->gen) {
 770         case 7:
 771         case 6:
 772                 ret = gen6_do_reset(dev);
 773                 break;
 774         case 5:
 775                 ret = ironlake_do_reset(dev);
 776                 break;
 777         case 4:
 778                 ret = i965_do_reset(dev);
 779                 break;
 780         case 2:
 781                 ret = i8xx_do_reset(dev);
 782                 break;
 783         }
 784
 785         /* Also reset the gpu hangman. */
 786         if (dev_priv->gpu_error.stop_rings) {
 787                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 788                 dev_priv->gpu_error.stop_rings = 0;
 789                 if (ret == -ENODEV) {
 790                         DRM_ERROR("Reset not implemented, but ignoring "
 791                                   "error for simulated gpu hangs\n");
 792                         ret = 0;
 793                 }
 794         }
 795
 796         return ret;
 797 }
 798
 799 /**
 800  * i915_reset - reset chip after a hang
 801  * @dev: drm device to reset
 802  *
 803  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 804  * reset or otherwise an error code.
 805  *
 806  * Procedure is fairly simple:
 807  *   - reset the chip using the reset reg
 808  *   - re-init context state
 809  *   - re-init hardware status page
 810  *   - re-init ring buffer
 811  *   - re-init interrupt state
 812  *   - re-init display
 813  */
 814 int i915_reset(struct drm_device *dev)
 815 {
 816         drm_i915_private_t *dev_priv = dev->dev_private;
 817         int ret;
 818
 819         if (!i915_try_reset)
 820                 return 0;
 821
 822         mutex_lock(&dev->struct_mutex);
 823
 824         i915_gem_reset(dev);
 825
 826         ret = -ENODEV;
 827         if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
 828                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 829         else
 830                 ret = intel_gpu_reset(dev);
 831
 832         dev_priv->gpu_error.last_reset = get_seconds();
 833         if (ret) {
 834                 DRM_ERROR("Failed to reset chip.\n");
 835                 mutex_unlock(&dev->struct_mutex);
 836                 return ret;
 837         }
 838
 839         /* Ok, now get things going again... */
 840
 841         /*
 842          * Everything depends on having the GTT running, so we need to start
 843          * there.  Fortunately we don't need to do this unless we reset the
 844          * chip at a PCI level.
 845          *
 846          * Next we need to restore the context, but we don't use those
 847          * yet either...
 848          *
 849          * Ring buffer needs to be re-initialized in the KMS case, or if X
 850          * was running at the time of the reset (i.e. we weren't VT
 851          * switched away).
 852          */
 853         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 854                         !dev_priv->mm.suspended) {
 855                 struct intel_ring_buffer *ring;
 856                 int i;
 857
 858                 dev_priv->mm.suspended = 0;
 859
 860                 i915_gem_init_swizzling(dev);
 861
 862                 for_each_ring(ring, dev_priv, i)
 863                         ring->init(ring);
 864
 865                 i915_gem_context_init(dev);
 866                 i915_gem_init_ppgtt(dev);
 867
 868                 /*
 869                  * It would make sense to re-init all the other hw state, at
 870                  * least the rps/rc6/emon init done within modeset_init_hw. For
 871                  * some unknown reason, this blows up my ilk, so don't.
 872                  */
 873
 874                 mutex_unlock(&dev->struct_mutex);
 875
 876                 drm_irq_uninstall(dev);
 877                 drm_irq_install(dev);
 878                 intel_hpd_init(dev);
 879         } else {
 880                 mutex_unlock(&dev->struct_mutex);
 881         }
 882
 883         return 0;
 884 }
 885
 886 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 887 {
 888         struct intel_device_info *intel_info =
 889                 (struct intel_device_info *) ent->driver_data;
 890
 891         if (intel_info->is_valleyview)
 892                 if(!i915_preliminary_hw_support) {
 893                         DRM_ERROR("Preliminary hardware support disabled\n");
 894                         return -ENODEV;
 895                 }
 896
 897         /* Only bind to function 0 of the device. Early generations
 898          * used function 1 as a placeholder for multi-head. This causes
 899          * us confusion instead, especially on the systems where both
 900          * functions have the same PCI-ID!
 901          */
 902         if (PCI_FUNC(pdev->devfn))
 903                 return -ENODEV;
 904
 905         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 906          * implementation for gen3 (and only gen3) that used legacy drm maps
 907          * (gasp!) to share buffers between X and the client. Hence we need to
 908          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 909         if (intel_info->gen != 3) {
 910                 driver.driver_features &=
 911                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 912         } else if (!intel_agp_enabled) {
 913                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 914                 return -ENODEV;
 915         }
 916
 917         return drm_get_pci_dev(pdev, ent, &driver);
 918 }
 919
 920 static void
 921 i915_pci_remove(struct pci_dev *pdev)
 922 {
 923         struct drm_device *dev = pci_get_drvdata(pdev);
 924
 925         drm_put_dev(dev);
 926 }
 927
 928 static int i915_pm_suspend(struct device *dev)
 929 {
 930         struct pci_dev *pdev = to_pci_dev(dev);
 931         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 932         int error;
 933
 934         if (!drm_dev || !drm_dev->dev_private) {
 935                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 936                 return -ENODEV;
 937         }
 938
 939         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 940                 return 0;
 941
 942         error = i915_drm_freeze(drm_dev);
 943         if (error)
 944                 return error;
 945
 946         pci_disable_device(pdev);
 947         pci_set_power_state(pdev, PCI_D3hot);
 948
 949         return 0;
 950 }
 951
 952 static int i915_pm_resume(struct device *dev)
 953 {
 954         struct pci_dev *pdev = to_pci_dev(dev);
 955         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 956
 957         return i915_resume(drm_dev);
 958 }
 959
 960 static int i915_pm_freeze(struct device *dev)
 961 {
 962         struct pci_dev *pdev = to_pci_dev(dev);
 963         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 964
 965         if (!drm_dev || !drm_dev->dev_private) {
 966                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 967                 return -ENODEV;
 968         }
 969
 970         return i915_drm_freeze(drm_dev);
 971 }
 972
 973 static int i915_pm_thaw(struct device *dev)
 974 {
 975         struct pci_dev *pdev = to_pci_dev(dev);
 976         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 977
 978         return i915_drm_thaw(drm_dev);
 979 }
 980
 981 static int i915_pm_poweroff(struct device *dev)
 982 {
 983         struct pci_dev *pdev = to_pci_dev(dev);
 984         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 985
 986         return i915_drm_freeze(drm_dev);
 987 }
 988
 989 static const struct dev_pm_ops i915_pm_ops = {
 990         .suspend = i915_pm_suspend,
 991         .resume = i915_pm_resume,
 992         .freeze = i915_pm_freeze,
 993         .thaw = i915_pm_thaw,
 994         .poweroff = i915_pm_poweroff,
 995         .restore = i915_pm_resume,
 996 };
 997
 998 static const struct vm_operations_struct i915_gem_vm_ops = {
 999         .fault = i915_gem_fault,
1000         .open = drm_gem_vm_open,
1001         .close = drm_gem_vm_close,
1002 };
1003
1004 static const struct file_operations i915_driver_fops = {
1005         .owner = THIS_MODULE,
1006         .open = drm_open,
1007         .release = drm_release,
1008         .unlocked_ioctl = drm_ioctl,
1009         .mmap = drm_gem_mmap,
1010         .poll = drm_poll,
1011         .fasync = drm_fasync,
1012         .read = drm_read,
1013 #ifdef CONFIG_COMPAT
1014         .compat_ioctl = i915_compat_ioctl,
1015 #endif
1016         .llseek = noop_llseek,
1017 };
1018
1019 static struct drm_driver driver = {
1020         /* Don't use MTRRs here; the Xserver or userspace app should
1021          * deal with them for Intel hardware.
1022          */
1023         .driver_features =
1024             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1025             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1026         .load = i915_driver_load,
1027         .unload = i915_driver_unload,
1028         .open = i915_driver_open,
1029         .lastclose = i915_driver_lastclose,
1030         .preclose = i915_driver_preclose,
1031         .postclose = i915_driver_postclose,
1032
1033         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1034         .suspend = i915_suspend,
1035         .resume = i915_resume,
1036
1037         .device_is_agp = i915_driver_device_is_agp,
1038         .master_create = i915_master_create,
1039         .master_destroy = i915_master_destroy,
1040 #if defined(CONFIG_DEBUG_FS)
1041         .debugfs_init = i915_debugfs_init,
1042         .debugfs_cleanup = i915_debugfs_cleanup,
1043 #endif
1044         .gem_init_object = i915_gem_init_object,
1045         .gem_free_object = i915_gem_free_object,
1046         .gem_vm_ops = &i915_gem_vm_ops,
1047
1048         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1049         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1050         .gem_prime_export = i915_gem_prime_export,
1051         .gem_prime_import = i915_gem_prime_import,
1052
1053         .dumb_create = i915_gem_dumb_create,
1054         .dumb_map_offset = i915_gem_mmap_gtt,
1055         .dumb_destroy = i915_gem_dumb_destroy,
1056         .ioctls = i915_ioctls,
1057         .fops = &i915_driver_fops,
1058         .name = DRIVER_NAME,
1059         .desc = DRIVER_DESC,
1060         .date = DRIVER_DATE,
1061         .major = DRIVER_MAJOR,
1062         .minor = DRIVER_MINOR,
1063         .patchlevel = DRIVER_PATCHLEVEL,
1064 };
1065
1066 static struct pci_driver i915_pci_driver = {
1067         .name = DRIVER_NAME,
1068         .id_table = pciidlist,
1069         .probe = i915_pci_probe,
1070         .remove = i915_pci_remove,
1071         .driver.pm = &i915_pm_ops,
1072 };
1073
1074 static int __init i915_init(void)
1075 {
1076         driver.num_ioctls = i915_max_ioctl;
1077
1078         /*
1079          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1080          * explicitly disabled with the module pararmeter.
1081          *
1082          * Otherwise, just follow the parameter (defaulting to off).
1083          *
1084          * Allow optional vga_text_mode_force boot option to override
1085          * the default behavior.
1086          */
1087 #if defined(CONFIG_DRM_I915_KMS)
1088         if (i915_modeset != 0)
1089                 driver.driver_features |= DRIVER_MODESET;
1090 #endif
1091         if (i915_modeset == 1)
1092                 driver.driver_features |= DRIVER_MODESET;
1093
1094 #ifdef CONFIG_VGA_CONSOLE
1095         if (vgacon_text_force() && i915_modeset == -1)
1096                 driver.driver_features &= ~DRIVER_MODESET;
1097 #endif
1098
1099         if (!(driver.driver_features & DRIVER_MODESET))
1100                 driver.get_vblank_timestamp = NULL;
1101
1102         return drm_pci_init(&driver, &i915_pci_driver);
1103 }
1104
1105 static void __exit i915_exit(void)
1106 {
1107         drm_pci_exit(&driver, &i915_pci_driver);
1108 }
1109
1110 module_init(i915_init);
1111 module_exit(i915_exit);
1112
1113 MODULE_AUTHOR(DRIVER_AUTHOR);
1114 MODULE_DESCRIPTION(DRIVER_DESC);
1115 MODULE_LICENSE("GPL and additional rights");
1116
1117 /* We give fast paths for the really cool registers */
1118 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1119         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1120          ((reg) < 0x40000) &&            \
1121          ((reg) != FORCEWAKE))
1122 static void
1123 ilk_dummy_write(struct drm_i915_private *dev_priv)
1124 {
1125         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1126          * chip from rc6 before touching it for real. MI_MODE is masked, hence
1127          * harmless to write 0 into. */
1128         I915_WRITE_NOTRACE(MI_MODE, 0);
1129 }
1130
1131 #define __i915_read(x, y) \
1132 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1133         u##x val = 0; \
1134         if (IS_GEN5(dev_priv->dev)) \
1135                 ilk_dummy_write(dev_priv); \
1136         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1137                 unsigned long irqflags; \
1138                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1139                 if (dev_priv->forcewake_count == 0) \
1140                         dev_priv->gt.force_wake_get(dev_priv); \
1141                 val = read##y(dev_priv->regs + reg); \
1142                 if (dev_priv->forcewake_count == 0) \
1143                         dev_priv->gt.force_wake_put(dev_priv); \
1144                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1145         } else { \
1146                 val = read##y(dev_priv->regs + reg); \
1147         } \
1148         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1149         return val; \
1150 }
1151
1152 __i915_read(8, b)
1153 __i915_read(16, w)
1154 __i915_read(32, l)
1155 __i915_read(64, q)
1156 #undef __i915_read
1157
1158 #define __i915_write(x, y) \
1159 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1160         u32 __fifo_ret = 0; \
1161         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1162         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1163                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1164         } \
1165         if (IS_GEN5(dev_priv->dev)) \
1166                 ilk_dummy_write(dev_priv); \
1167         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1168                 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
1169                 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1170         } \
1171         write##y(val, dev_priv->regs + reg); \
1172         if (unlikely(__fifo_ret)) { \
1173                 gen6_gt_check_fifodbg(dev_priv); \
1174         } \
1175         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1176                 DRM_ERROR("Unclaimed write to %x\n", reg); \
1177                 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT);  \
1178         } \
1179 }
1180 __i915_write(8, b)
1181 __i915_write(16, w)
1182 __i915_write(32, l)
1183 __i915_write(64, q)
1184 #undef __i915_write
1185
1186 static const struct register_whitelist {
1187         uint64_t offset;
1188         uint32_t size;
1189         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1190 } whitelist[] = {
1191         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1192 };
1193
1194 int i915_reg_read_ioctl(struct drm_device *dev,
1195                         void *data, struct drm_file *file)
1196 {
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         struct drm_i915_reg_read *reg = data;
1199         struct register_whitelist const *entry = whitelist;
1200         int i;
1201
1202         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1203                 if (entry->offset == reg->offset &&
1204                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1205                         break;
1206         }
1207
1208         if (i == ARRAY_SIZE(whitelist))
1209                 return -EINVAL;
1210
1211         switch (entry->size) {
1212         case 8:
1213                 reg->val = I915_READ64(reg->offset);
1214                 break;
1215         case 4:
1216                 reg->val = I915_READ(reg->offset);
1217                 break;
1218         case 2:
1219                 reg->val = I915_READ16(reg->offset);
1220                 break;
1221         case 1:
1222                 reg->val = I915_READ8(reg->offset);
1223                 break;
1224         default:
1225                 WARN_ON(1);
1226                 return -EINVAL;
1227         }
1228
1229         return 0;
1230 }