drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62         /**
  63          * find_pll() - Find the best values for the PLL
  64          * @limit: limits for the PLL
  65          * @crtc: current CRTC
  66          * @target: target frequency in kHz
  67          * @refclk: reference clock frequency in kHz
  68          * @match_clock: if provided, @best_clock P divider must
  69          *               match the P divider from @match_clock
  70          *               used for LVDS downclocking
  71          * @best_clock: best PLL values found
  72          *
  73          * Returns true on success, false on failure.
  74          */
  75         bool (*find_pll)(const intel_limit_t *limit,
  76                          struct drm_crtc *crtc,
  77                          int target, int refclk,
  78                          intel_clock_t *match_clock,
  79                          intel_clock_t *best_clock);
  80 };
  81
  82 /* FDI */
  83 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  84
  85 int
  86 intel_pch_rawclk(struct drm_device *dev)
  87 {
  88         struct drm_i915_private *dev_priv = dev->dev_private;
  89
  90         WARN_ON(!HAS_PCH_SPLIT(dev));
  91
  92         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  93 }
  94
  95 static bool
  96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                     int target, int refclk, intel_clock_t *match_clock,
  98                     intel_clock_t *best_clock);
  99 static bool
 100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 101                         int target, int refclk, intel_clock_t *match_clock,
 102                         intel_clock_t *best_clock);
 103
 104 static bool
 105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 106                         int target, int refclk, intel_clock_t *match_clock,
 107                         intel_clock_t *best_clock);
 108
 109 static inline u32 /* units of 100MHz */
 110 intel_fdi_link_freq(struct drm_device *dev)
 111 {
 112         if (IS_GEN5(dev)) {
 113                 struct drm_i915_private *dev_priv = dev->dev_private;
 114                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 115         } else
 116                 return 27;
 117 }
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 930000, .max = 1400000 },
 122         .n = { .min = 3, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 2 },
 130         .find_pll = intel_find_best_PLL,
 131 };
 132
 133 static const intel_limit_t intel_limits_i8xx_lvds = {
 134         .dot = { .min = 25000, .max = 350000 },
 135         .vco = { .min = 930000, .max = 1400000 },
 136         .n = { .min = 3, .max = 16 },
 137         .m = { .min = 96, .max = 140 },
 138         .m1 = { .min = 18, .max = 26 },
 139         .m2 = { .min = 6, .max = 16 },
 140         .p = { .min = 4, .max = 128 },
 141         .p1 = { .min = 1, .max = 6 },
 142         .p2 = { .dot_limit = 165000,
 143                 .p2_slow = 14, .p2_fast = 7 },
 144         .find_pll = intel_find_best_PLL,
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_sdvo = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 5, .max = 80 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 200000,
 157                 .p2_slow = 10, .p2_fast = 5 },
 158         .find_pll = intel_find_best_PLL,
 159 };
 160
 161 static const intel_limit_t intel_limits_i9xx_lvds = {
 162         .dot = { .min = 20000, .max = 400000 },
 163         .vco = { .min = 1400000, .max = 2800000 },
 164         .n = { .min = 1, .max = 6 },
 165         .m = { .min = 70, .max = 120 },
 166         .m1 = { .min = 8, .max = 18 },
 167         .m2 = { .min = 3, .max = 7 },
 168         .p = { .min = 7, .max = 98 },
 169         .p1 = { .min = 1, .max = 8 },
 170         .p2 = { .dot_limit = 112000,
 171                 .p2_slow = 14, .p2_fast = 7 },
 172         .find_pll = intel_find_best_PLL,
 173 };
 174
 175
 176 static const intel_limit_t intel_limits_g4x_sdvo = {
 177         .dot = { .min = 25000, .max = 270000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 17, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 10, .max = 30 },
 184         .p1 = { .min = 1, .max = 3},
 185         .p2 = { .dot_limit = 270000,
 186                 .p2_slow = 10,
 187                 .p2_fast = 10
 188         },
 189         .find_pll = intel_g4x_find_best_PLL,
 190 };
 191
 192 static const intel_limit_t intel_limits_g4x_hdmi = {
 193         .dot = { .min = 22000, .max = 400000 },
 194         .vco = { .min = 1750000, .max = 3500000},
 195         .n = { .min = 1, .max = 4 },
 196         .m = { .min = 104, .max = 138 },
 197         .m1 = { .min = 16, .max = 23 },
 198         .m2 = { .min = 5, .max = 11 },
 199         .p = { .min = 5, .max = 80 },
 200         .p1 = { .min = 1, .max = 8},
 201         .p2 = { .dot_limit = 165000,
 202                 .p2_slow = 10, .p2_fast = 5 },
 203         .find_pll = intel_g4x_find_best_PLL,
 204 };
 205
 206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 207         .dot = { .min = 20000, .max = 115000 },
 208         .vco = { .min = 1750000, .max = 3500000 },
 209         .n = { .min = 1, .max = 3 },
 210         .m = { .min = 104, .max = 138 },
 211         .m1 = { .min = 17, .max = 23 },
 212         .m2 = { .min = 5, .max = 11 },
 213         .p = { .min = 28, .max = 112 },
 214         .p1 = { .min = 2, .max = 8 },
 215         .p2 = { .dot_limit = 0,
 216                 .p2_slow = 14, .p2_fast = 14
 217         },
 218         .find_pll = intel_g4x_find_best_PLL,
 219 };
 220
 221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 222         .dot = { .min = 80000, .max = 224000 },
 223         .vco = { .min = 1750000, .max = 3500000 },
 224         .n = { .min = 1, .max = 3 },
 225         .m = { .min = 104, .max = 138 },
 226         .m1 = { .min = 17, .max = 23 },
 227         .m2 = { .min = 5, .max = 11 },
 228         .p = { .min = 14, .max = 42 },
 229         .p1 = { .min = 2, .max = 6 },
 230         .p2 = { .dot_limit = 0,
 231                 .p2_slow = 7, .p2_fast = 7
 232         },
 233         .find_pll = intel_g4x_find_best_PLL,
 234 };
 235
 236 static const intel_limit_t intel_limits_pineview_sdvo = {
 237         .dot = { .min = 20000, .max = 400000},
 238         .vco = { .min = 1700000, .max = 3500000 },
 239         /* Pineview's Ncounter is a ring counter */
 240         .n = { .min = 3, .max = 6 },
 241         .m = { .min = 2, .max = 256 },
 242         /* Pineview only has one combined m divider, which we treat as m2. */
 243         .m1 = { .min = 0, .max = 0 },
 244         .m2 = { .min = 0, .max = 254 },
 245         .p = { .min = 5, .max = 80 },
 246         .p1 = { .min = 1, .max = 8 },
 247         .p2 = { .dot_limit = 200000,
 248                 .p2_slow = 10, .p2_fast = 5 },
 249         .find_pll = intel_find_best_PLL,
 250 };
 251
 252 static const intel_limit_t intel_limits_pineview_lvds = {
 253         .dot = { .min = 20000, .max = 400000 },
 254         .vco = { .min = 1700000, .max = 3500000 },
 255         .n = { .min = 3, .max = 6 },
 256         .m = { .min = 2, .max = 256 },
 257         .m1 = { .min = 0, .max = 0 },
 258         .m2 = { .min = 0, .max = 254 },
 259         .p = { .min = 7, .max = 112 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 112000,
 262                 .p2_slow = 14, .p2_fast = 14 },
 263         .find_pll = intel_find_best_PLL,
 264 };
 265
 266 /* Ironlake / Sandybridge
 267  *
 268  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 269  * the range value for them is (actual_value - 2).
 270  */
 271 static const intel_limit_t intel_limits_ironlake_dac = {
 272         .dot = { .min = 25000, .max = 350000 },
 273         .vco = { .min = 1760000, .max = 3510000 },
 274         .n = { .min = 1, .max = 5 },
 275         .m = { .min = 79, .max = 127 },
 276         .m1 = { .min = 12, .max = 22 },
 277         .m2 = { .min = 5, .max = 9 },
 278         .p = { .min = 5, .max = 80 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 225000,
 281                 .p2_slow = 10, .p2_fast = 5 },
 282         .find_pll = intel_g4x_find_best_PLL,
 283 };
 284
 285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 286         .dot = { .min = 25000, .max = 350000 },
 287         .vco = { .min = 1760000, .max = 3510000 },
 288         .n = { .min = 1, .max = 3 },
 289         .m = { .min = 79, .max = 118 },
 290         .m1 = { .min = 12, .max = 22 },
 291         .m2 = { .min = 5, .max = 9 },
 292         .p = { .min = 28, .max = 112 },
 293         .p1 = { .min = 2, .max = 8 },
 294         .p2 = { .dot_limit = 225000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296         .find_pll = intel_g4x_find_best_PLL,
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 127 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 56 },
 307         .p1 = { .min = 2, .max = 8 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310         .find_pll = intel_g4x_find_best_PLL,
 311 };
 312
 313 /* LVDS 100mhz refclk limits. */
 314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 2 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 28, .max = 112 },
 322         .p1 = { .min = 2, .max = 8 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 14, .p2_fast = 14 },
 325         .find_pll = intel_g4x_find_best_PLL,
 326 };
 327
 328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 329         .dot = { .min = 25000, .max = 350000 },
 330         .vco = { .min = 1760000, .max = 3510000 },
 331         .n = { .min = 1, .max = 3 },
 332         .m = { .min = 79, .max = 126 },
 333         .m1 = { .min = 12, .max = 22 },
 334         .m2 = { .min = 5, .max = 9 },
 335         .p = { .min = 14, .max = 42 },
 336         .p1 = { .min = 2, .max = 6 },
 337         .p2 = { .dot_limit = 225000,
 338                 .p2_slow = 7, .p2_fast = 7 },
 339         .find_pll = intel_g4x_find_best_PLL,
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dac = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 }, /* guess */
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353         .find_pll = intel_vlv_find_best_pll,
 354 };
 355
 356 static const intel_limit_t intel_limits_vlv_hdmi = {
 357         .dot = { .min = 25000, .max = 270000 },
 358         .vco = { .min = 4000000, .max = 6000000 },
 359         .n = { .min = 1, .max = 7 },
 360         .m = { .min = 60, .max = 300 }, /* guess */
 361         .m1 = { .min = 2, .max = 3 },
 362         .m2 = { .min = 11, .max = 156 },
 363         .p = { .min = 10, .max = 30 },
 364         .p1 = { .min = 2, .max = 3 },
 365         .p2 = { .dot_limit = 270000,
 366                 .p2_slow = 2, .p2_fast = 20 },
 367         .find_pll = intel_vlv_find_best_pll,
 368 };
 369
 370 static const intel_limit_t intel_limits_vlv_dp = {
 371         .dot = { .min = 25000, .max = 270000 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m = { .min = 22, .max = 450 },
 375         .m1 = { .min = 2, .max = 3 },
 376         .m2 = { .min = 11, .max = 156 },
 377         .p = { .min = 10, .max = 30 },
 378         .p1 = { .min = 1, .max = 3 },
 379         .p2 = { .dot_limit = 270000,
 380                 .p2_slow = 2, .p2_fast = 20 },
 381         .find_pll = intel_vlv_find_best_pll,
 382 };
 383
 384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 385                                                 int refclk)
 386 {
 387         struct drm_device *dev = crtc->dev;
 388         const intel_limit_t *limit;
 389
 390         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 391                 if (intel_is_dual_link_lvds(dev)) {
 392                         if (refclk == 100000)
 393                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 394                         else
 395                                 limit = &intel_limits_ironlake_dual_lvds;
 396                 } else {
 397                         if (refclk == 100000)
 398                                 limit = &intel_limits_ironlake_single_lvds_100m;
 399                         else
 400                                 limit = &intel_limits_ironlake_single_lvds;
 401                 }
 402         } else
 403                 limit = &intel_limits_ironlake_dac;
 404
 405         return limit;
 406 }
 407
 408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 409 {
 410         struct drm_device *dev = crtc->dev;
 411         const intel_limit_t *limit;
 412
 413         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 414                 if (intel_is_dual_link_lvds(dev))
 415                         limit = &intel_limits_g4x_dual_channel_lvds;
 416                 else
 417                         limit = &intel_limits_g4x_single_channel_lvds;
 418         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 419                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 420                 limit = &intel_limits_g4x_hdmi;
 421         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 422                 limit = &intel_limits_g4x_sdvo;
 423         } else /* The option is for other outputs */
 424                 limit = &intel_limits_i9xx_sdvo;
 425
 426         return limit;
 427 }
 428
 429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 430 {
 431         struct drm_device *dev = crtc->dev;
 432         const intel_limit_t *limit;
 433
 434         if (HAS_PCH_SPLIT(dev))
 435                 limit = intel_ironlake_limit(crtc, refclk);
 436         else if (IS_G4X(dev)) {
 437                 limit = intel_g4x_limit(crtc);
 438         } else if (IS_PINEVIEW(dev)) {
 439                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 440                         limit = &intel_limits_pineview_lvds;
 441                 else
 442                         limit = &intel_limits_pineview_sdvo;
 443         } else if (IS_VALLEYVIEW(dev)) {
 444                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 445                         limit = &intel_limits_vlv_dac;
 446                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 447                         limit = &intel_limits_vlv_hdmi;
 448                 else
 449                         limit = &intel_limits_vlv_dp;
 450         } else if (!IS_GEN2(dev)) {
 451                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 452                         limit = &intel_limits_i9xx_lvds;
 453                 else
 454                         limit = &intel_limits_i9xx_sdvo;
 455         } else {
 456                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 457                         limit = &intel_limits_i8xx_lvds;
 458                 else
 459                         limit = &intel_limits_i8xx_dvo;
 460         }
 461         return limit;
 462 }
 463
 464 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 465 static void pineview_clock(int refclk, intel_clock_t *clock)
 466 {
 467         clock->m = clock->m2 + 2;
 468         clock->p = clock->p1 * clock->p2;
 469         clock->vco = refclk * clock->m / clock->n;
 470         clock->dot = clock->vco / clock->p;
 471 }
 472
 473 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 474 {
 475         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 476 }
 477
 478 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 479 {
 480         if (IS_PINEVIEW(dev)) {
 481                 pineview_clock(refclk, clock);
 482                 return;
 483         }
 484         clock->m = i9xx_dpll_compute_m(clock);
 485         clock->p = clock->p1 * clock->p2;
 486         clock->vco = refclk * clock->m / (clock->n + 2);
 487         clock->dot = clock->vco / clock->p;
 488 }
 489
 490 /**
 491  * Returns whether any output on the specified pipe is of the specified type
 492  */
 493 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 494 {
 495         struct drm_device *dev = crtc->dev;
 496         struct intel_encoder *encoder;
 497
 498         for_each_encoder_on_crtc(dev, crtc, encoder)
 499                 if (encoder->type == type)
 500                         return true;
 501
 502         return false;
 503 }
 504
 505 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 506 /**
 507  * Returns whether the given set of divisors are valid for a given refclk with
 508  * the given connectors.
 509  */
 510
 511 static bool intel_PLL_is_valid(struct drm_device *dev,
 512                                const intel_limit_t *limit,
 513                                const intel_clock_t *clock)
 514 {
 515         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 516                 INTELPllInvalid("p1 out of range\n");
 517         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 518                 INTELPllInvalid("p out of range\n");
 519         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 520                 INTELPllInvalid("m2 out of range\n");
 521         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 522                 INTELPllInvalid("m1 out of range\n");
 523         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 524                 INTELPllInvalid("m1 <= m2\n");
 525         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 526                 INTELPllInvalid("m out of range\n");
 527         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 528                 INTELPllInvalid("n out of range\n");
 529         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 530                 INTELPllInvalid("vco out of range\n");
 531         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 532          * connector, etc., rather than just a single range.
 533          */
 534         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 535                 INTELPllInvalid("dot out of range\n");
 536
 537         return true;
 538 }
 539
 540 static bool
 541 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 542                     int target, int refclk, intel_clock_t *match_clock,
 543                     intel_clock_t *best_clock)
 544
 545 {
 546         struct drm_device *dev = crtc->dev;
 547         intel_clock_t clock;
 548         int err = target;
 549
 550         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 551                 /*
 552                  * For LVDS just rely on its current settings for dual-channel.
 553                  * We haven't figured out how to reliably set up different
 554                  * single/dual channel state, if we even can.
 555                  */
 556                 if (intel_is_dual_link_lvds(dev))
 557                         clock.p2 = limit->p2.p2_fast;
 558                 else
 559                         clock.p2 = limit->p2.p2_slow;
 560         } else {
 561                 if (target < limit->p2.dot_limit)
 562                         clock.p2 = limit->p2.p2_slow;
 563                 else
 564                         clock.p2 = limit->p2.p2_fast;
 565         }
 566
 567         memset(best_clock, 0, sizeof(*best_clock));
 568
 569         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 570              clock.m1++) {
 571                 for (clock.m2 = limit->m2.min;
 572                      clock.m2 <= limit->m2.max; clock.m2++) {
 573                         /* m1 is always 0 in Pineview */
 574                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 575                                 break;
 576                         for (clock.n = limit->n.min;
 577                              clock.n <= limit->n.max; clock.n++) {
 578                                 for (clock.p1 = limit->p1.min;
 579                                         clock.p1 <= limit->p1.max; clock.p1++) {
 580                                         int this_err;
 581
 582                                         intel_clock(dev, refclk, &clock);
 583                                         if (!intel_PLL_is_valid(dev, limit,
 584                                                                 &clock))
 585                                                 continue;
 586                                         if (match_clock &&
 587                                             clock.p != match_clock->p)
 588                                                 continue;
 589
 590                                         this_err = abs(clock.dot - target);
 591                                         if (this_err < err) {
 592                                                 *best_clock = clock;
 593                                                 err = this_err;
 594                                         }
 595                                 }
 596                         }
 597                 }
 598         }
 599
 600         return (err != target);
 601 }
 602
 603 static bool
 604 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 605                         int target, int refclk, intel_clock_t *match_clock,
 606                         intel_clock_t *best_clock)
 607 {
 608         struct drm_device *dev = crtc->dev;
 609         intel_clock_t clock;
 610         int max_n;
 611         bool found;
 612         /* approximately equals target * 0.00585 */
 613         int err_most = (target >> 8) + (target >> 9);
 614         found = false;
 615
 616         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 617                 if (intel_is_dual_link_lvds(dev))
 618                         clock.p2 = limit->p2.p2_fast;
 619                 else
 620                         clock.p2 = limit->p2.p2_slow;
 621         } else {
 622                 if (target < limit->p2.dot_limit)
 623                         clock.p2 = limit->p2.p2_slow;
 624                 else
 625                         clock.p2 = limit->p2.p2_fast;
 626         }
 627
 628         memset(best_clock, 0, sizeof(*best_clock));
 629         max_n = limit->n.max;
 630         /* based on hardware requirement, prefer smaller n to precision */
 631         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 632                 /* based on hardware requirement, prefere larger m1,m2 */
 633                 for (clock.m1 = limit->m1.max;
 634                      clock.m1 >= limit->m1.min; clock.m1--) {
 635                         for (clock.m2 = limit->m2.max;
 636                              clock.m2 >= limit->m2.min; clock.m2--) {
 637                                 for (clock.p1 = limit->p1.max;
 638                                      clock.p1 >= limit->p1.min; clock.p1--) {
 639                                         int this_err;
 640
 641                                         intel_clock(dev, refclk, &clock);
 642                                         if (!intel_PLL_is_valid(dev, limit,
 643                                                                 &clock))
 644                                                 continue;
 645
 646                                         this_err = abs(clock.dot - target);
 647                                         if (this_err < err_most) {
 648                                                 *best_clock = clock;
 649                                                 err_most = this_err;
 650                                                 max_n = clock.n;
 651                                                 found = true;
 652                                         }
 653                                 }
 654                         }
 655                 }
 656         }
 657         return found;
 658 }
 659
 660 static bool
 661 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 662                         int target, int refclk, intel_clock_t *match_clock,
 663                         intel_clock_t *best_clock)
 664 {
 665         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 666         u32 m, n, fastclk;
 667         u32 updrate, minupdate, fracbits, p;
 668         unsigned long bestppm, ppm, absppm;
 669         int dotclk, flag;
 670
 671         flag = 0;
 672         dotclk = target * 1000;
 673         bestppm = 1000000;
 674         ppm = absppm = 0;
 675         fastclk = dotclk / (2*100);
 676         updrate = 0;
 677         minupdate = 19200;
 678         fracbits = 1;
 679         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 680         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 681
 682         /* based on hardware requirement, prefer smaller n to precision */
 683         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 684                 updrate = refclk / n;
 685                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 686                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 687                                 if (p2 > 10)
 688                                         p2 = p2 - 1;
 689                                 p = p1 * p2;
 690                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 691                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 692                                         m2 = (((2*(fastclk * p * n / m1 )) +
 693                                                refclk) / (2*refclk));
 694                                         m = m1 * m2;
 695                                         vco = updrate * m;
 696                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 697                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 698                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 699                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 700                                                         bestppm = 0;
 701                                                         flag = 1;
 702                                                 }
 703                                                 if (absppm < bestppm - 10) {
 704                                                         bestppm = absppm;
 705                                                         flag = 1;
 706                                                 }
 707                                                 if (flag) {
 708                                                         bestn = n;
 709                                                         bestm1 = m1;
 710                                                         bestm2 = m2;
 711                                                         bestp1 = p1;
 712                                                         bestp2 = p2;
 713                                                         flag = 0;
 714                                                 }
 715                                         }
 716                                 }
 717                         }
 718                 }
 719         }
 720         best_clock->n = bestn;
 721         best_clock->m1 = bestm1;
 722         best_clock->m2 = bestm2;
 723         best_clock->p1 = bestp1;
 724         best_clock->p2 = bestp2;
 725
 726         return true;
 727 }
 728
 729 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 730                                              enum pipe pipe)
 731 {
 732         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 734
 735         return intel_crtc->config.cpu_transcoder;
 736 }
 737
 738 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 739 {
 740         struct drm_i915_private *dev_priv = dev->dev_private;
 741         u32 frame, frame_reg = PIPEFRAME(pipe);
 742
 743         frame = I915_READ(frame_reg);
 744
 745         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 746                 DRM_DEBUG_KMS("vblank wait timed out\n");
 747 }
 748
 749 /**
 750  * intel_wait_for_vblank - wait for vblank on a given pipe
 751  * @dev: drm device
 752  * @pipe: pipe to wait for
 753  *
 754  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 755  * mode setting code.
 756  */
 757 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         int pipestat_reg = PIPESTAT(pipe);
 761
 762         if (INTEL_INFO(dev)->gen >= 5) {
 763                 ironlake_wait_for_vblank(dev, pipe);
 764                 return;
 765         }
 766
 767         /* Clear existing vblank status. Note this will clear any other
 768          * sticky status fields as well.
 769          *
 770          * This races with i915_driver_irq_handler() with the result
 771          * that either function could miss a vblank event.  Here it is not
 772          * fatal, as we will either wait upon the next vblank interrupt or
 773          * timeout.  Generally speaking intel_wait_for_vblank() is only
 774          * called during modeset at which time the GPU should be idle and
 775          * should *not* be performing page flips and thus not waiting on
 776          * vblanks...
 777          * Currently, the result of us stealing a vblank from the irq
 778          * handler is that a single frame will be skipped during swapbuffers.
 779          */
 780         I915_WRITE(pipestat_reg,
 781                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 782
 783         /* Wait for vblank interrupt bit to set */
 784         if (wait_for(I915_READ(pipestat_reg) &
 785                      PIPE_VBLANK_INTERRUPT_STATUS,
 786                      50))
 787                 DRM_DEBUG_KMS("vblank wait timed out\n");
 788 }
 789
 790 /*
 791  * intel_wait_for_pipe_off - wait for pipe to turn off
 792  * @dev: drm device
 793  * @pipe: pipe to wait for
 794  *
 795  * After disabling a pipe, we can't wait for vblank in the usual way,
 796  * spinning on the vblank interrupt status bit, since we won't actually
 797  * see an interrupt when the pipe is disabled.
 798  *
 799  * On Gen4 and above:
 800  *   wait for the pipe register state bit to turn off
 801  *
 802  * Otherwise:
 803  *   wait for the display line value to settle (it usually
 804  *   ends up stopping at the start of the next frame).
 805  *
 806  */
 807 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 808 {
 809         struct drm_i915_private *dev_priv = dev->dev_private;
 810         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 811                                                                       pipe);
 812
 813         if (INTEL_INFO(dev)->gen >= 4) {
 814                 int reg = PIPECONF(cpu_transcoder);
 815
 816                 /* Wait for the Pipe State to go off */
 817                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 818                              100))
 819                         WARN(1, "pipe_off wait timed out\n");
 820         } else {
 821                 u32 last_line, line_mask;
 822                 int reg = PIPEDSL(pipe);
 823                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 824
 825                 if (IS_GEN2(dev))
 826                         line_mask = DSL_LINEMASK_GEN2;
 827                 else
 828                         line_mask = DSL_LINEMASK_GEN3;
 829
 830                 /* Wait for the display line to settle */
 831                 do {
 832                         last_line = I915_READ(reg) & line_mask;
 833                         mdelay(5);
 834                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 835                          time_after(timeout, jiffies));
 836                 if (time_after(jiffies, timeout))
 837                         WARN(1, "pipe_off wait timed out\n");
 838         }
 839 }
 840
 841 /*
 842  * ibx_digital_port_connected - is the specified port connected?
 843  * @dev_priv: i915 private structure
 844  * @port: the port to test
 845  *
 846  * Returns true if @port is connected, false otherwise.
 847  */
 848 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 849                                 struct intel_digital_port *port)
 850 {
 851         u32 bit;
 852
 853         if (HAS_PCH_IBX(dev_priv->dev)) {
 854                 switch(port->port) {
 855                 case PORT_B:
 856                         bit = SDE_PORTB_HOTPLUG;
 857                         break;
 858                 case PORT_C:
 859                         bit = SDE_PORTC_HOTPLUG;
 860                         break;
 861                 case PORT_D:
 862                         bit = SDE_PORTD_HOTPLUG;
 863                         break;
 864                 default:
 865                         return true;
 866                 }
 867         } else {
 868                 switch(port->port) {
 869                 case PORT_B:
 870                         bit = SDE_PORTB_HOTPLUG_CPT;
 871                         break;
 872                 case PORT_C:
 873                         bit = SDE_PORTC_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_D:
 876                         bit = SDE_PORTD_HOTPLUG_CPT;
 877                         break;
 878                 default:
 879                         return true;
 880                 }
 881         }
 882
 883         return I915_READ(SDEISR) & bit;
 884 }
 885
 886 static const char *state_string(bool enabled)
 887 {
 888         return enabled ? "on" : "off";
 889 }
 890
 891 /* Only for pre-ILK configs */
 892 static void assert_pll(struct drm_i915_private *dev_priv,
 893                        enum pipe pipe, bool state)
 894 {
 895         int reg;
 896         u32 val;
 897         bool cur_state;
 898
 899         reg = DPLL(pipe);
 900         val = I915_READ(reg);
 901         cur_state = !!(val & DPLL_VCO_ENABLE);
 902         WARN(cur_state != state,
 903              "PLL state assertion failure (expected %s, current %s)\n",
 904              state_string(state), state_string(cur_state));
 905 }
 906 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 907 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 908
 909 /* For ILK+ */
 910 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 911                            struct intel_pch_pll *pll,
 912                            struct intel_crtc *crtc,
 913                            bool state)
 914 {
 915         u32 val;
 916         bool cur_state;
 917
 918         if (HAS_PCH_LPT(dev_priv->dev)) {
 919                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 920                 return;
 921         }
 922
 923         if (WARN (!pll,
 924                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 925                 return;
 926
 927         val = I915_READ(pll->pll_reg);
 928         cur_state = !!(val & DPLL_VCO_ENABLE);
 929         WARN(cur_state != state,
 930              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 931              pll->pll_reg, state_string(state), state_string(cur_state), val);
 932
 933         /* Make sure the selected PLL is correctly attached to the transcoder */
 934         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 935                 u32 pch_dpll;
 936
 937                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 938                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 939                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 940                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 941                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 942                         cur_state = !!(val >> (4*crtc->pipe + 3));
 943                         WARN(cur_state != state,
 944                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 945                              pll->pll_reg == _PCH_DPLL_B,
 946                              state_string(state),
 947                              pipe_name(crtc->pipe),
 948                              val);
 949                 }
 950         }
 951 }
 952 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 953 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 954
 955 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 956                           enum pipe pipe, bool state)
 957 {
 958         int reg;
 959         u32 val;
 960         bool cur_state;
 961         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 962                                                                       pipe);
 963
 964         if (HAS_DDI(dev_priv->dev)) {
 965                 /* DDI does not have a specific FDI_TX register */
 966                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 967                 val = I915_READ(reg);
 968                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 969         } else {
 970                 reg = FDI_TX_CTL(pipe);
 971                 val = I915_READ(reg);
 972                 cur_state = !!(val & FDI_TX_ENABLE);
 973         }
 974         WARN(cur_state != state,
 975              "FDI TX state assertion failure (expected %s, current %s)\n",
 976              state_string(state), state_string(cur_state));
 977 }
 978 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 979 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 980
 981 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 982                           enum pipe pipe, bool state)
 983 {
 984         int reg;
 985         u32 val;
 986         bool cur_state;
 987
 988         reg = FDI_RX_CTL(pipe);
 989         val = I915_READ(reg);
 990         cur_state = !!(val & FDI_RX_ENABLE);
 991         WARN(cur_state != state,
 992              "FDI RX state assertion failure (expected %s, current %s)\n",
 993              state_string(state), state_string(cur_state));
 994 }
 995 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 996 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 997
 998 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 999                                       enum pipe pipe)
1000 {
1001         int reg;
1002         u32 val;
1003
1004         /* ILK FDI PLL is always enabled */
1005         if (dev_priv->info->gen == 5)
1006                 return;
1007
1008         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1009         if (HAS_DDI(dev_priv->dev))
1010                 return;
1011
1012         reg = FDI_TX_CTL(pipe);
1013         val = I915_READ(reg);
1014         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1015 }
1016
1017 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1018                                       enum pipe pipe)
1019 {
1020         int reg;
1021         u32 val;
1022
1023         reg = FDI_RX_CTL(pipe);
1024         val = I915_READ(reg);
1025         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1026 }
1027
1028 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1029                                   enum pipe pipe)
1030 {
1031         int pp_reg, lvds_reg;
1032         u32 val;
1033         enum pipe panel_pipe = PIPE_A;
1034         bool locked = true;
1035
1036         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1037                 pp_reg = PCH_PP_CONTROL;
1038                 lvds_reg = PCH_LVDS;
1039         } else {
1040                 pp_reg = PP_CONTROL;
1041                 lvds_reg = LVDS;
1042         }
1043
1044         val = I915_READ(pp_reg);
1045         if (!(val & PANEL_POWER_ON) ||
1046             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1047                 locked = false;
1048
1049         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1050                 panel_pipe = PIPE_B;
1051
1052         WARN(panel_pipe == pipe && locked,
1053              "panel assertion failure, pipe %c regs locked\n",
1054              pipe_name(pipe));
1055 }
1056
1057 void assert_pipe(struct drm_i915_private *dev_priv,
1058                  enum pipe pipe, bool state)
1059 {
1060         int reg;
1061         u32 val;
1062         bool cur_state;
1063         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1064                                                                       pipe);
1065
1066         /* if we need the pipe A quirk it must be always on */
1067         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1068                 state = true;
1069
1070         if (!intel_display_power_enabled(dev_priv->dev,
1071                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1072                 cur_state = false;
1073         } else {
1074                 reg = PIPECONF(cpu_transcoder);
1075                 val = I915_READ(reg);
1076                 cur_state = !!(val & PIPECONF_ENABLE);
1077         }
1078
1079         WARN(cur_state != state,
1080              "pipe %c assertion failure (expected %s, current %s)\n",
1081              pipe_name(pipe), state_string(state), state_string(cur_state));
1082 }
1083
1084 static void assert_plane(struct drm_i915_private *dev_priv,
1085                          enum plane plane, bool state)
1086 {
1087         int reg;
1088         u32 val;
1089         bool cur_state;
1090
1091         reg = DSPCNTR(plane);
1092         val = I915_READ(reg);
1093         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1094         WARN(cur_state != state,
1095              "plane %c assertion failure (expected %s, current %s)\n",
1096              plane_name(plane), state_string(state), state_string(cur_state));
1097 }
1098
1099 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1100 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1101
1102 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1103                                    enum pipe pipe)
1104 {
1105         int reg, i;
1106         u32 val;
1107         int cur_pipe;
1108
1109         /* Planes are fixed to pipes on ILK+ */
1110         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1111                 reg = DSPCNTR(pipe);
1112                 val = I915_READ(reg);
1113                 WARN((val & DISPLAY_PLANE_ENABLE),
1114                      "plane %c assertion failure, should be disabled but not\n",
1115                      plane_name(pipe));
1116                 return;
1117         }
1118
1119         /* Need to check both planes against the pipe */
1120         for (i = 0; i < 2; i++) {
1121                 reg = DSPCNTR(i);
1122                 val = I915_READ(reg);
1123                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1124                         DISPPLANE_SEL_PIPE_SHIFT;
1125                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1126                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1127                      plane_name(i), pipe_name(pipe));
1128         }
1129 }
1130
1131 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1132                                     enum pipe pipe)
1133 {
1134         int reg, i;
1135         u32 val;
1136
1137         if (!IS_VALLEYVIEW(dev_priv->dev))
1138                 return;
1139
1140         /* Need to check both planes against the pipe */
1141         for (i = 0; i < dev_priv->num_plane; i++) {
1142                 reg = SPCNTR(pipe, i);
1143                 val = I915_READ(reg);
1144                 WARN((val & SP_ENABLE),
1145                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1146                      sprite_name(pipe, i), pipe_name(pipe));
1147         }
1148 }
1149
1150 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1151 {
1152         u32 val;
1153         bool enabled;
1154
1155         if (HAS_PCH_LPT(dev_priv->dev)) {
1156                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1157                 return;
1158         }
1159
1160         val = I915_READ(PCH_DREF_CONTROL);
1161         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1162                             DREF_SUPERSPREAD_SOURCE_MASK));
1163         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1164 }
1165
1166 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1167                                            enum pipe pipe)
1168 {
1169         int reg;
1170         u32 val;
1171         bool enabled;
1172
1173         reg = PCH_TRANSCONF(pipe);
1174         val = I915_READ(reg);
1175         enabled = !!(val & TRANS_ENABLE);
1176         WARN(enabled,
1177              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1178              pipe_name(pipe));
1179 }
1180
1181 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1182                             enum pipe pipe, u32 port_sel, u32 val)
1183 {
1184         if ((val & DP_PORT_EN) == 0)
1185                 return false;
1186
1187         if (HAS_PCH_CPT(dev_priv->dev)) {
1188                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1189                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1190                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1191                         return false;
1192         } else {
1193                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1194                         return false;
1195         }
1196         return true;
1197 }
1198
1199 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1200                               enum pipe pipe, u32 val)
1201 {
1202         if ((val & SDVO_ENABLE) == 0)
1203                 return false;
1204
1205         if (HAS_PCH_CPT(dev_priv->dev)) {
1206                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1207                         return false;
1208         } else {
1209                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1210                         return false;
1211         }
1212         return true;
1213 }
1214
1215 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1216                               enum pipe pipe, u32 val)
1217 {
1218         if ((val & LVDS_PORT_EN) == 0)
1219                 return false;
1220
1221         if (HAS_PCH_CPT(dev_priv->dev)) {
1222                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1223                         return false;
1224         } else {
1225                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1226                         return false;
1227         }
1228         return true;
1229 }
1230
1231 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1232                               enum pipe pipe, u32 val)
1233 {
1234         if ((val & ADPA_DAC_ENABLE) == 0)
1235                 return false;
1236         if (HAS_PCH_CPT(dev_priv->dev)) {
1237                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238                         return false;
1239         } else {
1240                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1241                         return false;
1242         }
1243         return true;
1244 }
1245
1246 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe, int reg, u32 port_sel)
1248 {
1249         u32 val = I915_READ(reg);
1250         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1251              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1252              reg, pipe_name(pipe));
1253
1254         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1255              && (val & DP_PIPEB_SELECT),
1256              "IBX PCH dp port still using transcoder B\n");
1257 }
1258
1259 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1260                                      enum pipe pipe, int reg)
1261 {
1262         u32 val = I915_READ(reg);
1263         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1264              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1265              reg, pipe_name(pipe));
1266
1267         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1268              && (val & SDVO_PIPE_B_SELECT),
1269              "IBX PCH hdmi port still using transcoder B\n");
1270 }
1271
1272 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1273                                       enum pipe pipe)
1274 {
1275         int reg;
1276         u32 val;
1277
1278         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1279         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1280         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1281
1282         reg = PCH_ADPA;
1283         val = I915_READ(reg);
1284         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1285              "PCH VGA enabled on transcoder %c, should be disabled\n",
1286              pipe_name(pipe));
1287
1288         reg = PCH_LVDS;
1289         val = I915_READ(reg);
1290         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1291              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1292              pipe_name(pipe));
1293
1294         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1295         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1296         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1297 }
1298
1299 /**
1300  * intel_enable_pll - enable a PLL
1301  * @dev_priv: i915 private structure
1302  * @pipe: pipe PLL to enable
1303  *
1304  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1305  * make sure the PLL reg is writable first though, since the panel write
1306  * protect mechanism may be enabled.
1307  *
1308  * Note!  This is for pre-ILK only.
1309  *
1310  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1311  */
1312 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1313 {
1314         int reg;
1315         u32 val;
1316
1317         assert_pipe_disabled(dev_priv, pipe);
1318
1319         /* No really, not for ILK+ */
1320         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1321
1322         /* PLL is protected by panel, make sure we can write it */
1323         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1324                 assert_panel_unlocked(dev_priv, pipe);
1325
1326         reg = DPLL(pipe);
1327         val = I915_READ(reg);
1328         val |= DPLL_VCO_ENABLE;
1329
1330         /* We do this three times for luck */
1331         I915_WRITE(reg, val);
1332         POSTING_READ(reg);
1333         udelay(150); /* wait for warmup */
1334         I915_WRITE(reg, val);
1335         POSTING_READ(reg);
1336         udelay(150); /* wait for warmup */
1337         I915_WRITE(reg, val);
1338         POSTING_READ(reg);
1339         udelay(150); /* wait for warmup */
1340 }
1341
1342 /**
1343  * intel_disable_pll - disable a PLL
1344  * @dev_priv: i915 private structure
1345  * @pipe: pipe PLL to disable
1346  *
1347  * Disable the PLL for @pipe, making sure the pipe is off first.
1348  *
1349  * Note!  This is for pre-ILK only.
1350  */
1351 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1352 {
1353         int reg;
1354         u32 val;
1355
1356         /* Don't disable pipe A or pipe A PLLs if needed */
1357         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1358                 return;
1359
1360         /* Make sure the pipe isn't still relying on us */
1361         assert_pipe_disabled(dev_priv, pipe);
1362
1363         reg = DPLL(pipe);
1364         val = I915_READ(reg);
1365         val &= ~DPLL_VCO_ENABLE;
1366         I915_WRITE(reg, val);
1367         POSTING_READ(reg);
1368 }
1369
1370 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1371 {
1372         u32 port_mask;
1373
1374         if (!port)
1375                 port_mask = DPLL_PORTB_READY_MASK;
1376         else
1377                 port_mask = DPLL_PORTC_READY_MASK;
1378
1379         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1380                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1381                      'B' + port, I915_READ(DPLL(0)));
1382 }
1383
1384 /**
1385  * ironlake_enable_pch_pll - enable PCH PLL
1386  * @dev_priv: i915 private structure
1387  * @pipe: pipe PLL to enable
1388  *
1389  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1390  * drives the transcoder clock.
1391  */
1392 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1393 {
1394         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1395         struct intel_pch_pll *pll;
1396         int reg;
1397         u32 val;
1398
1399         /* PCH PLLs only available on ILK, SNB and IVB */
1400         BUG_ON(dev_priv->info->gen < 5);
1401         pll = intel_crtc->pch_pll;
1402         if (pll == NULL)
1403                 return;
1404
1405         if (WARN_ON(pll->refcount == 0))
1406                 return;
1407
1408         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1409                       pll->pll_reg, pll->active, pll->on,
1410                       intel_crtc->base.base.id);
1411
1412         /* PCH refclock must be enabled first */
1413         assert_pch_refclk_enabled(dev_priv);
1414
1415         if (pll->active++ && pll->on) {
1416                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1417                 return;
1418         }
1419
1420         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1421
1422         reg = pll->pll_reg;
1423         val = I915_READ(reg);
1424         val |= DPLL_VCO_ENABLE;
1425         I915_WRITE(reg, val);
1426         POSTING_READ(reg);
1427         udelay(200);
1428
1429         pll->on = true;
1430 }
1431
1432 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1433 {
1434         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1435         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1436         int reg;
1437         u32 val;
1438
1439         /* PCH only available on ILK+ */
1440         BUG_ON(dev_priv->info->gen < 5);
1441         if (pll == NULL)
1442                return;
1443
1444         if (WARN_ON(pll->refcount == 0))
1445                 return;
1446
1447         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1448                       pll->pll_reg, pll->active, pll->on,
1449                       intel_crtc->base.base.id);
1450
1451         if (WARN_ON(pll->active == 0)) {
1452                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1453                 return;
1454         }
1455
1456         if (--pll->active) {
1457                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1458                 return;
1459         }
1460
1461         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1462
1463         /* Make sure transcoder isn't still depending on us */
1464         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1465
1466         reg = pll->pll_reg;
1467         val = I915_READ(reg);
1468         val &= ~DPLL_VCO_ENABLE;
1469         I915_WRITE(reg, val);
1470         POSTING_READ(reg);
1471         udelay(200);
1472
1473         pll->on = false;
1474 }
1475
1476 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1477                                            enum pipe pipe)
1478 {
1479         struct drm_device *dev = dev_priv->dev;
1480         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1481         uint32_t reg, val, pipeconf_val;
1482
1483         /* PCH only available on ILK+ */
1484         BUG_ON(dev_priv->info->gen < 5);
1485
1486         /* Make sure PCH DPLL is enabled */
1487         assert_pch_pll_enabled(dev_priv,
1488                                to_intel_crtc(crtc)->pch_pll,
1489                                to_intel_crtc(crtc));
1490
1491         /* FDI must be feeding us bits for PCH ports */
1492         assert_fdi_tx_enabled(dev_priv, pipe);
1493         assert_fdi_rx_enabled(dev_priv, pipe);
1494
1495         if (HAS_PCH_CPT(dev)) {
1496                 /* Workaround: Set the timing override bit before enabling the
1497                  * pch transcoder. */
1498                 reg = TRANS_CHICKEN2(pipe);
1499                 val = I915_READ(reg);
1500                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1501                 I915_WRITE(reg, val);
1502         }
1503
1504         reg = PCH_TRANSCONF(pipe);
1505         val = I915_READ(reg);
1506         pipeconf_val = I915_READ(PIPECONF(pipe));
1507
1508         if (HAS_PCH_IBX(dev_priv->dev)) {
1509                 /*
1510                  * make the BPC in transcoder be consistent with
1511                  * that in pipeconf reg.
1512                  */
1513                 val &= ~PIPECONF_BPC_MASK;
1514                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1515         }
1516
1517         val &= ~TRANS_INTERLACE_MASK;
1518         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1519                 if (HAS_PCH_IBX(dev_priv->dev) &&
1520                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1521                         val |= TRANS_LEGACY_INTERLACED_ILK;
1522                 else
1523                         val |= TRANS_INTERLACED;
1524         else
1525                 val |= TRANS_PROGRESSIVE;
1526
1527         I915_WRITE(reg, val | TRANS_ENABLE);
1528         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1529                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1530 }
1531
1532 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1533                                       enum transcoder cpu_transcoder)
1534 {
1535         u32 val, pipeconf_val;
1536
1537         /* PCH only available on ILK+ */
1538         BUG_ON(dev_priv->info->gen < 5);
1539
1540         /* FDI must be feeding us bits for PCH ports */
1541         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1542         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1543
1544         /* Workaround: set timing override bit. */
1545         val = I915_READ(_TRANSA_CHICKEN2);
1546         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1547         I915_WRITE(_TRANSA_CHICKEN2, val);
1548
1549         val = TRANS_ENABLE;
1550         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1551
1552         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1553             PIPECONF_INTERLACED_ILK)
1554                 val |= TRANS_INTERLACED;
1555         else
1556                 val |= TRANS_PROGRESSIVE;
1557
1558         I915_WRITE(LPT_TRANSCONF, val);
1559         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1560                 DRM_ERROR("Failed to enable PCH transcoder\n");
1561 }
1562
1563 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1564                                             enum pipe pipe)
1565 {
1566         struct drm_device *dev = dev_priv->dev;
1567         uint32_t reg, val;
1568
1569         /* FDI relies on the transcoder */
1570         assert_fdi_tx_disabled(dev_priv, pipe);
1571         assert_fdi_rx_disabled(dev_priv, pipe);
1572
1573         /* Ports must be off as well */
1574         assert_pch_ports_disabled(dev_priv, pipe);
1575
1576         reg = PCH_TRANSCONF(pipe);
1577         val = I915_READ(reg);
1578         val &= ~TRANS_ENABLE;
1579         I915_WRITE(reg, val);
1580         /* wait for PCH transcoder off, transcoder state */
1581         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1582                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1583
1584         if (!HAS_PCH_IBX(dev)) {
1585                 /* Workaround: Clear the timing override chicken bit again. */
1586                 reg = TRANS_CHICKEN2(pipe);
1587                 val = I915_READ(reg);
1588                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589                 I915_WRITE(reg, val);
1590         }
1591 }
1592
1593 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1594 {
1595         u32 val;
1596
1597         val = I915_READ(LPT_TRANSCONF);
1598         val &= ~TRANS_ENABLE;
1599         I915_WRITE(LPT_TRANSCONF, val);
1600         /* wait for PCH transcoder off, transcoder state */
1601         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1602                 DRM_ERROR("Failed to disable PCH transcoder\n");
1603
1604         /* Workaround: clear timing override bit. */
1605         val = I915_READ(_TRANSA_CHICKEN2);
1606         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1607         I915_WRITE(_TRANSA_CHICKEN2, val);
1608 }
1609
1610 /**
1611  * intel_enable_pipe - enable a pipe, asserting requirements
1612  * @dev_priv: i915 private structure
1613  * @pipe: pipe to enable
1614  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1615  *
1616  * Enable @pipe, making sure that various hardware specific requirements
1617  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1618  *
1619  * @pipe should be %PIPE_A or %PIPE_B.
1620  *
1621  * Will wait until the pipe is actually running (i.e. first vblank) before
1622  * returning.
1623  */
1624 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1625                               bool pch_port)
1626 {
1627         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1628                                                                       pipe);
1629         enum pipe pch_transcoder;
1630         int reg;
1631         u32 val;
1632
1633         assert_planes_disabled(dev_priv, pipe);
1634         assert_sprites_disabled(dev_priv, pipe);
1635
1636         if (HAS_PCH_LPT(dev_priv->dev))
1637                 pch_transcoder = TRANSCODER_A;
1638         else
1639                 pch_transcoder = pipe;
1640
1641         /*
1642          * A pipe without a PLL won't actually be able to drive bits from
1643          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1644          * need the check.
1645          */
1646         if (!HAS_PCH_SPLIT(dev_priv->dev))
1647                 assert_pll_enabled(dev_priv, pipe);
1648         else {
1649                 if (pch_port) {
1650                         /* if driving the PCH, we need FDI enabled */
1651                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1652                         assert_fdi_tx_pll_enabled(dev_priv,
1653                                                   (enum pipe) cpu_transcoder);
1654                 }
1655                 /* FIXME: assert CPU port conditions for SNB+ */
1656         }
1657
1658         reg = PIPECONF(cpu_transcoder);
1659         val = I915_READ(reg);
1660         if (val & PIPECONF_ENABLE)
1661                 return;
1662
1663         I915_WRITE(reg, val | PIPECONF_ENABLE);
1664         intel_wait_for_vblank(dev_priv->dev, pipe);
1665 }
1666
1667 /**
1668  * intel_disable_pipe - disable a pipe, asserting requirements
1669  * @dev_priv: i915 private structure
1670  * @pipe: pipe to disable
1671  *
1672  * Disable @pipe, making sure that various hardware specific requirements
1673  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1674  *
1675  * @pipe should be %PIPE_A or %PIPE_B.
1676  *
1677  * Will wait until the pipe has shut down before returning.
1678  */
1679 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1680                                enum pipe pipe)
1681 {
1682         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1683                                                                       pipe);
1684         int reg;
1685         u32 val;
1686
1687         /*
1688          * Make sure planes won't keep trying to pump pixels to us,
1689          * or we might hang the display.
1690          */
1691         assert_planes_disabled(dev_priv, pipe);
1692         assert_sprites_disabled(dev_priv, pipe);
1693
1694         /* Don't disable pipe A or pipe A PLLs if needed */
1695         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1696                 return;
1697
1698         reg = PIPECONF(cpu_transcoder);
1699         val = I915_READ(reg);
1700         if ((val & PIPECONF_ENABLE) == 0)
1701                 return;
1702
1703         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1704         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1705 }
1706
1707 /*
1708  * Plane regs are double buffered, going from enabled->disabled needs a
1709  * trigger in order to latch.  The display address reg provides this.
1710  */
1711 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1712                                       enum plane plane)
1713 {
1714         if (dev_priv->info->gen >= 4)
1715                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1716         else
1717                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1718 }
1719
1720 /**
1721  * intel_enable_plane - enable a display plane on a given pipe
1722  * @dev_priv: i915 private structure
1723  * @plane: plane to enable
1724  * @pipe: pipe being fed
1725  *
1726  * Enable @plane on @pipe, making sure that @pipe is running first.
1727  */
1728 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1729                                enum plane plane, enum pipe pipe)
1730 {
1731         int reg;
1732         u32 val;
1733
1734         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1735         assert_pipe_enabled(dev_priv, pipe);
1736
1737         reg = DSPCNTR(plane);
1738         val = I915_READ(reg);
1739         if (val & DISPLAY_PLANE_ENABLE)
1740                 return;
1741
1742         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1743         intel_flush_display_plane(dev_priv, plane);
1744         intel_wait_for_vblank(dev_priv->dev, pipe);
1745 }
1746
1747 /**
1748  * intel_disable_plane - disable a display plane
1749  * @dev_priv: i915 private structure
1750  * @plane: plane to disable
1751  * @pipe: pipe consuming the data
1752  *
1753  * Disable @plane; should be an independent operation.
1754  */
1755 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1756                                 enum plane plane, enum pipe pipe)
1757 {
1758         int reg;
1759         u32 val;
1760
1761         reg = DSPCNTR(plane);
1762         val = I915_READ(reg);
1763         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1764                 return;
1765
1766         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1767         intel_flush_display_plane(dev_priv, plane);
1768         intel_wait_for_vblank(dev_priv->dev, pipe);
1769 }
1770
1771 static bool need_vtd_wa(struct drm_device *dev)
1772 {
1773 #ifdef CONFIG_INTEL_IOMMU
1774         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1775                 return true;
1776 #endif
1777         return false;
1778 }
1779
1780 int
1781 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1782                            struct drm_i915_gem_object *obj,
1783                            struct intel_ring_buffer *pipelined)
1784 {
1785         struct drm_i915_private *dev_priv = dev->dev_private;
1786         u32 alignment;
1787         int ret;
1788
1789         switch (obj->tiling_mode) {
1790         case I915_TILING_NONE:
1791                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1792                         alignment = 128 * 1024;
1793                 else if (INTEL_INFO(dev)->gen >= 4)
1794                         alignment = 4 * 1024;
1795                 else
1796                         alignment = 64 * 1024;
1797                 break;
1798         case I915_TILING_X:
1799                 /* pin() will align the object as required by fence */
1800                 alignment = 0;
1801                 break;
1802         case I915_TILING_Y:
1803                 /* Despite that we check this in framebuffer_init userspace can
1804                  * screw us over and change the tiling after the fact. Only
1805                  * pinned buffers can't change their tiling. */
1806                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1807                 return -EINVAL;
1808         default:
1809                 BUG();
1810         }
1811
1812         /* Note that the w/a also requires 64 PTE of padding following the
1813          * bo. We currently fill all unused PTE with the shadow page and so
1814          * we should always have valid PTE following the scanout preventing
1815          * the VT-d warning.
1816          */
1817         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1818                 alignment = 256 * 1024;
1819
1820         dev_priv->mm.interruptible = false;
1821         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1822         if (ret)
1823                 goto err_interruptible;
1824
1825         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1826          * fence, whereas 965+ only requires a fence if using
1827          * framebuffer compression.  For simplicity, we always install
1828          * a fence as the cost is not that onerous.
1829          */
1830         ret = i915_gem_object_get_fence(obj);
1831         if (ret)
1832                 goto err_unpin;
1833
1834         i915_gem_object_pin_fence(obj);
1835
1836         dev_priv->mm.interruptible = true;
1837         return 0;
1838
1839 err_unpin:
1840         i915_gem_object_unpin(obj);
1841 err_interruptible:
1842         dev_priv->mm.interruptible = true;
1843         return ret;
1844 }
1845
1846 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1847 {
1848         i915_gem_object_unpin_fence(obj);
1849         i915_gem_object_unpin(obj);
1850 }
1851
1852 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1853  * is assumed to be a power-of-two. */
1854 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1855                                              unsigned int tiling_mode,
1856                                              unsigned int cpp,
1857                                              unsigned int pitch)
1858 {
1859         if (tiling_mode != I915_TILING_NONE) {
1860                 unsigned int tile_rows, tiles;
1861
1862                 tile_rows = *y / 8;
1863                 *y %= 8;
1864
1865                 tiles = *x / (512/cpp);
1866                 *x %= 512/cpp;
1867
1868                 return tile_rows * pitch * 8 + tiles * 4096;
1869         } else {
1870                 unsigned int offset;
1871
1872                 offset = *y * pitch + *x * cpp;
1873                 *y = 0;
1874                 *x = (offset & 4095) / cpp;
1875                 return offset & -4096;
1876         }
1877 }
1878
1879 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1880                              int x, int y)
1881 {
1882         struct drm_device *dev = crtc->dev;
1883         struct drm_i915_private *dev_priv = dev->dev_private;
1884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1885         struct intel_framebuffer *intel_fb;
1886         struct drm_i915_gem_object *obj;
1887         int plane = intel_crtc->plane;
1888         unsigned long linear_offset;
1889         u32 dspcntr;
1890         u32 reg;
1891
1892         switch (plane) {
1893         case 0:
1894         case 1:
1895                 break;
1896         default:
1897                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1898                 return -EINVAL;
1899         }
1900
1901         intel_fb = to_intel_framebuffer(fb);
1902         obj = intel_fb->obj;
1903
1904         reg = DSPCNTR(plane);
1905         dspcntr = I915_READ(reg);
1906         /* Mask out pixel format bits in case we change it */
1907         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1908         switch (fb->pixel_format) {
1909         case DRM_FORMAT_C8:
1910                 dspcntr |= DISPPLANE_8BPP;
1911                 break;
1912         case DRM_FORMAT_XRGB1555:
1913         case DRM_FORMAT_ARGB1555:
1914                 dspcntr |= DISPPLANE_BGRX555;
1915                 break;
1916         case DRM_FORMAT_RGB565:
1917                 dspcntr |= DISPPLANE_BGRX565;
1918                 break;
1919         case DRM_FORMAT_XRGB8888:
1920         case DRM_FORMAT_ARGB8888:
1921                 dspcntr |= DISPPLANE_BGRX888;
1922                 break;
1923         case DRM_FORMAT_XBGR8888:
1924         case DRM_FORMAT_ABGR8888:
1925                 dspcntr |= DISPPLANE_RGBX888;
1926                 break;
1927         case DRM_FORMAT_XRGB2101010:
1928         case DRM_FORMAT_ARGB2101010:
1929                 dspcntr |= DISPPLANE_BGRX101010;
1930                 break;
1931         case DRM_FORMAT_XBGR2101010:
1932         case DRM_FORMAT_ABGR2101010:
1933                 dspcntr |= DISPPLANE_RGBX101010;
1934                 break;
1935         default:
1936                 BUG();
1937         }
1938
1939         if (INTEL_INFO(dev)->gen >= 4) {
1940                 if (obj->tiling_mode != I915_TILING_NONE)
1941                         dspcntr |= DISPPLANE_TILED;
1942                 else
1943                         dspcntr &= ~DISPPLANE_TILED;
1944         }
1945
1946         I915_WRITE(reg, dspcntr);
1947
1948         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1949
1950         if (INTEL_INFO(dev)->gen >= 4) {
1951                 intel_crtc->dspaddr_offset =
1952                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1953                                                        fb->bits_per_pixel / 8,
1954                                                        fb->pitches[0]);
1955                 linear_offset -= intel_crtc->dspaddr_offset;
1956         } else {
1957                 intel_crtc->dspaddr_offset = linear_offset;
1958         }
1959
1960         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1961                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1962         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1963         if (INTEL_INFO(dev)->gen >= 4) {
1964                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1965                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1966                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1967                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1968         } else
1969                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1970         POSTING_READ(reg);
1971
1972         return 0;
1973 }
1974
1975 static int ironlake_update_plane(struct drm_crtc *crtc,
1976                                  struct drm_framebuffer *fb, int x, int y)
1977 {
1978         struct drm_device *dev = crtc->dev;
1979         struct drm_i915_private *dev_priv = dev->dev_private;
1980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1981         struct intel_framebuffer *intel_fb;
1982         struct drm_i915_gem_object *obj;
1983         int plane = intel_crtc->plane;
1984         unsigned long linear_offset;
1985         u32 dspcntr;
1986         u32 reg;
1987
1988         switch (plane) {
1989         case 0:
1990         case 1:
1991         case 2:
1992                 break;
1993         default:
1994                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1995                 return -EINVAL;
1996         }
1997
1998         intel_fb = to_intel_framebuffer(fb);
1999         obj = intel_fb->obj;
2000
2001         reg = DSPCNTR(plane);
2002         dspcntr = I915_READ(reg);
2003         /* Mask out pixel format bits in case we change it */
2004         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2005         switch (fb->pixel_format) {
2006         case DRM_FORMAT_C8:
2007                 dspcntr |= DISPPLANE_8BPP;
2008                 break;
2009         case DRM_FORMAT_RGB565:
2010                 dspcntr |= DISPPLANE_BGRX565;
2011                 break;
2012         case DRM_FORMAT_XRGB8888:
2013         case DRM_FORMAT_ARGB8888:
2014                 dspcntr |= DISPPLANE_BGRX888;
2015                 break;
2016         case DRM_FORMAT_XBGR8888:
2017         case DRM_FORMAT_ABGR8888:
2018                 dspcntr |= DISPPLANE_RGBX888;
2019                 break;
2020         case DRM_FORMAT_XRGB2101010:
2021         case DRM_FORMAT_ARGB2101010:
2022                 dspcntr |= DISPPLANE_BGRX101010;
2023                 break;
2024         case DRM_FORMAT_XBGR2101010:
2025         case DRM_FORMAT_ABGR2101010:
2026                 dspcntr |= DISPPLANE_RGBX101010;
2027                 break;
2028         default:
2029                 BUG();
2030         }
2031
2032         if (obj->tiling_mode != I915_TILING_NONE)
2033                 dspcntr |= DISPPLANE_TILED;
2034         else
2035                 dspcntr &= ~DISPPLANE_TILED;
2036
2037         /* must disable */
2038         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2039
2040         I915_WRITE(reg, dspcntr);
2041
2042         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2043         intel_crtc->dspaddr_offset =
2044                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2045                                                fb->bits_per_pixel / 8,
2046                                                fb->pitches[0]);
2047         linear_offset -= intel_crtc->dspaddr_offset;
2048
2049         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2050                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2051         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2052         I915_MODIFY_DISPBASE(DSPSURF(plane),
2053                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2054         if (IS_HASWELL(dev)) {
2055                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2056         } else {
2057                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2058                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2059         }
2060         POSTING_READ(reg);
2061
2062         return 0;
2063 }
2064
2065 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2066 static int
2067 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2068                            int x, int y, enum mode_set_atomic state)
2069 {
2070         struct drm_device *dev = crtc->dev;
2071         struct drm_i915_private *dev_priv = dev->dev_private;
2072
2073         if (dev_priv->display.disable_fbc)
2074                 dev_priv->display.disable_fbc(dev);
2075         intel_increase_pllclock(crtc);
2076
2077         return dev_priv->display.update_plane(crtc, fb, x, y);
2078 }
2079
2080 void intel_display_handle_reset(struct drm_device *dev)
2081 {
2082         struct drm_i915_private *dev_priv = dev->dev_private;
2083         struct drm_crtc *crtc;
2084
2085         /*
2086          * Flips in the rings have been nuked by the reset,
2087          * so complete all pending flips so that user space
2088          * will get its events and not get stuck.
2089          *
2090          * Also update the base address of all primary
2091          * planes to the the last fb to make sure we're
2092          * showing the correct fb after a reset.
2093          *
2094          * Need to make two loops over the crtcs so that we
2095          * don't try to grab a crtc mutex before the
2096          * pending_flip_queue really got woken up.
2097          */
2098
2099         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2100                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2101                 enum plane plane = intel_crtc->plane;
2102
2103                 intel_prepare_page_flip(dev, plane);
2104                 intel_finish_page_flip_plane(dev, plane);
2105         }
2106
2107         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2108                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2109
2110                 mutex_lock(&crtc->mutex);
2111                 if (intel_crtc->active)
2112                         dev_priv->display.update_plane(crtc, crtc->fb,
2113                                                        crtc->x, crtc->y);
2114                 mutex_unlock(&crtc->mutex);
2115         }
2116 }
2117
2118 static int
2119 intel_finish_fb(struct drm_framebuffer *old_fb)
2120 {
2121         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2122         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2123         bool was_interruptible = dev_priv->mm.interruptible;
2124         int ret;
2125
2126         /* Big Hammer, we also need to ensure that any pending
2127          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2128          * current scanout is retired before unpinning the old
2129          * framebuffer.
2130          *
2131          * This should only fail upon a hung GPU, in which case we
2132          * can safely continue.
2133          */
2134         dev_priv->mm.interruptible = false;
2135         ret = i915_gem_object_finish_gpu(obj);
2136         dev_priv->mm.interruptible = was_interruptible;
2137
2138         return ret;
2139 }
2140
2141 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2142 {
2143         struct drm_device *dev = crtc->dev;
2144         struct drm_i915_master_private *master_priv;
2145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146
2147         if (!dev->primary->master)
2148                 return;
2149
2150         master_priv = dev->primary->master->driver_priv;
2151         if (!master_priv->sarea_priv)
2152                 return;
2153
2154         switch (intel_crtc->pipe) {
2155         case 0:
2156                 master_priv->sarea_priv->pipeA_x = x;
2157                 master_priv->sarea_priv->pipeA_y = y;
2158                 break;
2159         case 1:
2160                 master_priv->sarea_priv->pipeB_x = x;
2161                 master_priv->sarea_priv->pipeB_y = y;
2162                 break;
2163         default:
2164                 break;
2165         }
2166 }
2167
2168 static int
2169 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2170                     struct drm_framebuffer *fb)
2171 {
2172         struct drm_device *dev = crtc->dev;
2173         struct drm_i915_private *dev_priv = dev->dev_private;
2174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2175         struct drm_framebuffer *old_fb;
2176         int ret;
2177
2178         /* no fb bound */
2179         if (!fb) {
2180                 DRM_ERROR("No FB bound\n");
2181                 return 0;
2182         }
2183
2184         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2185                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2186                           plane_name(intel_crtc->plane),
2187                           INTEL_INFO(dev)->num_pipes);
2188                 return -EINVAL;
2189         }
2190
2191         mutex_lock(&dev->struct_mutex);
2192         ret = intel_pin_and_fence_fb_obj(dev,
2193                                          to_intel_framebuffer(fb)->obj,
2194                                          NULL);
2195         if (ret != 0) {
2196                 mutex_unlock(&dev->struct_mutex);
2197                 DRM_ERROR("pin & fence failed\n");
2198                 return ret;
2199         }
2200
2201         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2202         if (ret) {
2203                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2204                 mutex_unlock(&dev->struct_mutex);
2205                 DRM_ERROR("failed to update base address\n");
2206                 return ret;
2207         }
2208
2209         old_fb = crtc->fb;
2210         crtc->fb = fb;
2211         crtc->x = x;
2212         crtc->y = y;
2213
2214         if (old_fb) {
2215                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2216                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2217         }
2218
2219         intel_update_fbc(dev);
2220         mutex_unlock(&dev->struct_mutex);
2221
2222         intel_crtc_update_sarea_pos(crtc, x, y);
2223
2224         return 0;
2225 }
2226
2227 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2228 {
2229         struct drm_device *dev = crtc->dev;
2230         struct drm_i915_private *dev_priv = dev->dev_private;
2231         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2232         int pipe = intel_crtc->pipe;
2233         u32 reg, temp;
2234
2235         /* enable normal train */
2236         reg = FDI_TX_CTL(pipe);
2237         temp = I915_READ(reg);
2238         if (IS_IVYBRIDGE(dev)) {
2239                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2240                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2241         } else {
2242                 temp &= ~FDI_LINK_TRAIN_NONE;
2243                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2244         }
2245         I915_WRITE(reg, temp);
2246
2247         reg = FDI_RX_CTL(pipe);
2248         temp = I915_READ(reg);
2249         if (HAS_PCH_CPT(dev)) {
2250                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2251                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2252         } else {
2253                 temp &= ~FDI_LINK_TRAIN_NONE;
2254                 temp |= FDI_LINK_TRAIN_NONE;
2255         }
2256         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2257
2258         /* wait one idle pattern time */
2259         POSTING_READ(reg);
2260         udelay(1000);
2261
2262         /* IVB wants error correction enabled */
2263         if (IS_IVYBRIDGE(dev))
2264                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2265                            FDI_FE_ERRC_ENABLE);
2266 }
2267
2268 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2269 {
2270         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2271 }
2272
2273 static void ivb_modeset_global_resources(struct drm_device *dev)
2274 {
2275         struct drm_i915_private *dev_priv = dev->dev_private;
2276         struct intel_crtc *pipe_B_crtc =
2277                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2278         struct intel_crtc *pipe_C_crtc =
2279                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2280         uint32_t temp;
2281
2282         /*
2283          * When everything is off disable fdi C so that we could enable fdi B
2284          * with all lanes. Note that we don't care about enabled pipes without
2285          * an enabled pch encoder.
2286          */
2287         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2288             !pipe_has_enabled_pch(pipe_C_crtc)) {
2289                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2290                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2291
2292                 temp = I915_READ(SOUTH_CHICKEN1);
2293                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2294                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2295                 I915_WRITE(SOUTH_CHICKEN1, temp);
2296         }
2297 }
2298
2299 /* The FDI link training functions for ILK/Ibexpeak. */
2300 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2301 {
2302         struct drm_device *dev = crtc->dev;
2303         struct drm_i915_private *dev_priv = dev->dev_private;
2304         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2305         int pipe = intel_crtc->pipe;
2306         int plane = intel_crtc->plane;
2307         u32 reg, temp, tries;
2308
2309         /* FDI needs bits from pipe & plane first */
2310         assert_pipe_enabled(dev_priv, pipe);
2311         assert_plane_enabled(dev_priv, plane);
2312
2313         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2314            for train result */
2315         reg = FDI_RX_IMR(pipe);
2316         temp = I915_READ(reg);
2317         temp &= ~FDI_RX_SYMBOL_LOCK;
2318         temp &= ~FDI_RX_BIT_LOCK;
2319         I915_WRITE(reg, temp);
2320         I915_READ(reg);
2321         udelay(150);
2322
2323         /* enable CPU FDI TX and PCH FDI RX */
2324         reg = FDI_TX_CTL(pipe);
2325         temp = I915_READ(reg);
2326         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2327         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2328         temp &= ~FDI_LINK_TRAIN_NONE;
2329         temp |= FDI_LINK_TRAIN_PATTERN_1;
2330         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2331
2332         reg = FDI_RX_CTL(pipe);
2333         temp = I915_READ(reg);
2334         temp &= ~FDI_LINK_TRAIN_NONE;
2335         temp |= FDI_LINK_TRAIN_PATTERN_1;
2336         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2337
2338         POSTING_READ(reg);
2339         udelay(150);
2340
2341         /* Ironlake workaround, enable clock pointer after FDI enable*/
2342         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2343         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2344                    FDI_RX_PHASE_SYNC_POINTER_EN);
2345
2346         reg = FDI_RX_IIR(pipe);
2347         for (tries = 0; tries < 5; tries++) {
2348                 temp = I915_READ(reg);
2349                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2350
2351                 if ((temp & FDI_RX_BIT_LOCK)) {
2352                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2353                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2354                         break;
2355                 }
2356         }
2357         if (tries == 5)
2358                 DRM_ERROR("FDI train 1 fail!\n");
2359
2360         /* Train 2 */
2361         reg = FDI_TX_CTL(pipe);
2362         temp = I915_READ(reg);
2363         temp &= ~FDI_LINK_TRAIN_NONE;
2364         temp |= FDI_LINK_TRAIN_PATTERN_2;
2365         I915_WRITE(reg, temp);
2366
2367         reg = FDI_RX_CTL(pipe);
2368         temp = I915_READ(reg);
2369         temp &= ~FDI_LINK_TRAIN_NONE;
2370         temp |= FDI_LINK_TRAIN_PATTERN_2;
2371         I915_WRITE(reg, temp);
2372
2373         POSTING_READ(reg);
2374         udelay(150);
2375
2376         reg = FDI_RX_IIR(pipe);
2377         for (tries = 0; tries < 5; tries++) {
2378                 temp = I915_READ(reg);
2379                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2380
2381                 if (temp & FDI_RX_SYMBOL_LOCK) {
2382                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2383                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2384                         break;
2385                 }
2386         }
2387         if (tries == 5)
2388                 DRM_ERROR("FDI train 2 fail!\n");
2389
2390         DRM_DEBUG_KMS("FDI train done\n");
2391
2392 }
2393
2394 static const int snb_b_fdi_train_param[] = {
2395         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2396         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2397         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2398         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2399 };
2400
2401 /* The FDI link training functions for SNB/Cougarpoint. */
2402 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2403 {
2404         struct drm_device *dev = crtc->dev;
2405         struct drm_i915_private *dev_priv = dev->dev_private;
2406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2407         int pipe = intel_crtc->pipe;
2408         u32 reg, temp, i, retry;
2409
2410         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2411            for train result */
2412         reg = FDI_RX_IMR(pipe);
2413         temp = I915_READ(reg);
2414         temp &= ~FDI_RX_SYMBOL_LOCK;
2415         temp &= ~FDI_RX_BIT_LOCK;
2416         I915_WRITE(reg, temp);
2417
2418         POSTING_READ(reg);
2419         udelay(150);
2420
2421         /* enable CPU FDI TX and PCH FDI RX */
2422         reg = FDI_TX_CTL(pipe);
2423         temp = I915_READ(reg);
2424         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_1;
2428         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2429         /* SNB-B */
2430         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2431         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2432
2433         I915_WRITE(FDI_RX_MISC(pipe),
2434                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         if (HAS_PCH_CPT(dev)) {
2439                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2440                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2441         } else {
2442                 temp &= ~FDI_LINK_TRAIN_NONE;
2443                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2444         }
2445         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446
2447         POSTING_READ(reg);
2448         udelay(150);
2449
2450         for (i = 0; i < 4; i++) {
2451                 reg = FDI_TX_CTL(pipe);
2452                 temp = I915_READ(reg);
2453                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2454                 temp |= snb_b_fdi_train_param[i];
2455                 I915_WRITE(reg, temp);
2456
2457                 POSTING_READ(reg);
2458                 udelay(500);
2459
2460                 for (retry = 0; retry < 5; retry++) {
2461                         reg = FDI_RX_IIR(pipe);
2462                         temp = I915_READ(reg);
2463                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2464                         if (temp & FDI_RX_BIT_LOCK) {
2465                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2466                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2467                                 break;
2468                         }
2469                         udelay(50);
2470                 }
2471                 if (retry < 5)
2472                         break;
2473         }
2474         if (i == 4)
2475                 DRM_ERROR("FDI train 1 fail!\n");
2476
2477         /* Train 2 */
2478         reg = FDI_TX_CTL(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_LINK_TRAIN_NONE;
2481         temp |= FDI_LINK_TRAIN_PATTERN_2;
2482         if (IS_GEN6(dev)) {
2483                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2484                 /* SNB-B */
2485                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2486         }
2487         I915_WRITE(reg, temp);
2488
2489         reg = FDI_RX_CTL(pipe);
2490         temp = I915_READ(reg);
2491         if (HAS_PCH_CPT(dev)) {
2492                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2493                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2494         } else {
2495                 temp &= ~FDI_LINK_TRAIN_NONE;
2496                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2497         }
2498         I915_WRITE(reg, temp);
2499
2500         POSTING_READ(reg);
2501         udelay(150);
2502
2503         for (i = 0; i < 4; i++) {
2504                 reg = FDI_TX_CTL(pipe);
2505                 temp = I915_READ(reg);
2506                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2507                 temp |= snb_b_fdi_train_param[i];
2508                 I915_WRITE(reg, temp);
2509
2510                 POSTING_READ(reg);
2511                 udelay(500);
2512
2513                 for (retry = 0; retry < 5; retry++) {
2514                         reg = FDI_RX_IIR(pipe);
2515                         temp = I915_READ(reg);
2516                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2517                         if (temp & FDI_RX_SYMBOL_LOCK) {
2518                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2519                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2520                                 break;
2521                         }
2522                         udelay(50);
2523                 }
2524                 if (retry < 5)
2525                         break;
2526         }
2527         if (i == 4)
2528                 DRM_ERROR("FDI train 2 fail!\n");
2529
2530         DRM_DEBUG_KMS("FDI train done.\n");
2531 }
2532
2533 /* Manual link training for Ivy Bridge A0 parts */
2534 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2535 {
2536         struct drm_device *dev = crtc->dev;
2537         struct drm_i915_private *dev_priv = dev->dev_private;
2538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539         int pipe = intel_crtc->pipe;
2540         u32 reg, temp, i;
2541
2542         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2543            for train result */
2544         reg = FDI_RX_IMR(pipe);
2545         temp = I915_READ(reg);
2546         temp &= ~FDI_RX_SYMBOL_LOCK;
2547         temp &= ~FDI_RX_BIT_LOCK;
2548         I915_WRITE(reg, temp);
2549
2550         POSTING_READ(reg);
2551         udelay(150);
2552
2553         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2554                       I915_READ(FDI_RX_IIR(pipe)));
2555
2556         /* enable CPU FDI TX and PCH FDI RX */
2557         reg = FDI_TX_CTL(pipe);
2558         temp = I915_READ(reg);
2559         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2560         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2561         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2562         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2563         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2565         temp |= FDI_COMPOSITE_SYNC;
2566         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2567
2568         I915_WRITE(FDI_RX_MISC(pipe),
2569                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2570
2571         reg = FDI_RX_CTL(pipe);
2572         temp = I915_READ(reg);
2573         temp &= ~FDI_LINK_TRAIN_AUTO;
2574         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2575         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2576         temp |= FDI_COMPOSITE_SYNC;
2577         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2578
2579         POSTING_READ(reg);
2580         udelay(150);
2581
2582         for (i = 0; i < 4; i++) {
2583                 reg = FDI_TX_CTL(pipe);
2584                 temp = I915_READ(reg);
2585                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586                 temp |= snb_b_fdi_train_param[i];
2587                 I915_WRITE(reg, temp);
2588
2589                 POSTING_READ(reg);
2590                 udelay(500);
2591
2592                 reg = FDI_RX_IIR(pipe);
2593                 temp = I915_READ(reg);
2594                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2595
2596                 if (temp & FDI_RX_BIT_LOCK ||
2597                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2598                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2599                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2600                         break;
2601                 }
2602         }
2603         if (i == 4)
2604                 DRM_ERROR("FDI train 1 fail!\n");
2605
2606         /* Train 2 */
2607         reg = FDI_TX_CTL(pipe);
2608         temp = I915_READ(reg);
2609         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2610         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2611         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2612         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2613         I915_WRITE(reg, temp);
2614
2615         reg = FDI_RX_CTL(pipe);
2616         temp = I915_READ(reg);
2617         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2618         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2619         I915_WRITE(reg, temp);
2620
2621         POSTING_READ(reg);
2622         udelay(150);
2623
2624         for (i = 0; i < 4; i++) {
2625                 reg = FDI_TX_CTL(pipe);
2626                 temp = I915_READ(reg);
2627                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2628                 temp |= snb_b_fdi_train_param[i];
2629                 I915_WRITE(reg, temp);
2630
2631                 POSTING_READ(reg);
2632                 udelay(500);
2633
2634                 reg = FDI_RX_IIR(pipe);
2635                 temp = I915_READ(reg);
2636                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2637
2638                 if (temp & FDI_RX_SYMBOL_LOCK) {
2639                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2640                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2641                         break;
2642                 }
2643         }
2644         if (i == 4)
2645                 DRM_ERROR("FDI train 2 fail!\n");
2646
2647         DRM_DEBUG_KMS("FDI train done.\n");
2648 }
2649
2650 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2651 {
2652         struct drm_device *dev = intel_crtc->base.dev;
2653         struct drm_i915_private *dev_priv = dev->dev_private;
2654         int pipe = intel_crtc->pipe;
2655         u32 reg, temp;
2656
2657
2658         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2659         reg = FDI_RX_CTL(pipe);
2660         temp = I915_READ(reg);
2661         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2662         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2663         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2664         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2665
2666         POSTING_READ(reg);
2667         udelay(200);
2668
2669         /* Switch from Rawclk to PCDclk */
2670         temp = I915_READ(reg);
2671         I915_WRITE(reg, temp | FDI_PCDCLK);
2672
2673         POSTING_READ(reg);
2674         udelay(200);
2675
2676         /* Enable CPU FDI TX PLL, always on for Ironlake */
2677         reg = FDI_TX_CTL(pipe);
2678         temp = I915_READ(reg);
2679         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2680                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2681
2682                 POSTING_READ(reg);
2683                 udelay(100);
2684         }
2685 }
2686
2687 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2688 {
2689         struct drm_device *dev = intel_crtc->base.dev;
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691         int pipe = intel_crtc->pipe;
2692         u32 reg, temp;
2693
2694         /* Switch from PCDclk to Rawclk */
2695         reg = FDI_RX_CTL(pipe);
2696         temp = I915_READ(reg);
2697         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2698
2699         /* Disable CPU FDI TX PLL */
2700         reg = FDI_TX_CTL(pipe);
2701         temp = I915_READ(reg);
2702         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2703
2704         POSTING_READ(reg);
2705         udelay(100);
2706
2707         reg = FDI_RX_CTL(pipe);
2708         temp = I915_READ(reg);
2709         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2710
2711         /* Wait for the clocks to turn off. */
2712         POSTING_READ(reg);
2713         udelay(100);
2714 }
2715
2716 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2717 {
2718         struct drm_device *dev = crtc->dev;
2719         struct drm_i915_private *dev_priv = dev->dev_private;
2720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2721         int pipe = intel_crtc->pipe;
2722         u32 reg, temp;
2723
2724         /* disable CPU FDI tx and PCH FDI rx */
2725         reg = FDI_TX_CTL(pipe);
2726         temp = I915_READ(reg);
2727         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2728         POSTING_READ(reg);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         temp &= ~(0x7 << 16);
2733         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2734         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2735
2736         POSTING_READ(reg);
2737         udelay(100);
2738
2739         /* Ironlake workaround, disable clock pointer after downing FDI */
2740         if (HAS_PCH_IBX(dev)) {
2741                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2742         }
2743
2744         /* still set train pattern 1 */
2745         reg = FDI_TX_CTL(pipe);
2746         temp = I915_READ(reg);
2747         temp &= ~FDI_LINK_TRAIN_NONE;
2748         temp |= FDI_LINK_TRAIN_PATTERN_1;
2749         I915_WRITE(reg, temp);
2750
2751         reg = FDI_RX_CTL(pipe);
2752         temp = I915_READ(reg);
2753         if (HAS_PCH_CPT(dev)) {
2754                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2755                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2756         } else {
2757                 temp &= ~FDI_LINK_TRAIN_NONE;
2758                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2759         }
2760         /* BPC in FDI rx is consistent with that in PIPECONF */
2761         temp &= ~(0x07 << 16);
2762         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2763         I915_WRITE(reg, temp);
2764
2765         POSTING_READ(reg);
2766         udelay(100);
2767 }
2768
2769 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2770 {
2771         struct drm_device *dev = crtc->dev;
2772         struct drm_i915_private *dev_priv = dev->dev_private;
2773         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774         unsigned long flags;
2775         bool pending;
2776
2777         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2778             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2779                 return false;
2780
2781         spin_lock_irqsave(&dev->event_lock, flags);
2782         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2783         spin_unlock_irqrestore(&dev->event_lock, flags);
2784
2785         return pending;
2786 }
2787
2788 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2789 {
2790         struct drm_device *dev = crtc->dev;
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792
2793         if (crtc->fb == NULL)
2794                 return;
2795
2796         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2797
2798         wait_event(dev_priv->pending_flip_queue,
2799                    !intel_crtc_has_pending_flip(crtc));
2800
2801         mutex_lock(&dev->struct_mutex);
2802         intel_finish_fb(crtc->fb);
2803         mutex_unlock(&dev->struct_mutex);
2804 }
2805
2806 /* Program iCLKIP clock to the desired frequency */
2807 static void lpt_program_iclkip(struct drm_crtc *crtc)
2808 {
2809         struct drm_device *dev = crtc->dev;
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2812         u32 temp;
2813
2814         mutex_lock(&dev_priv->dpio_lock);
2815
2816         /* It is necessary to ungate the pixclk gate prior to programming
2817          * the divisors, and gate it back when it is done.
2818          */
2819         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2820
2821         /* Disable SSCCTL */
2822         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2823                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2824                                 SBI_SSCCTL_DISABLE,
2825                         SBI_ICLK);
2826
2827         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2828         if (crtc->mode.clock == 20000) {
2829                 auxdiv = 1;
2830                 divsel = 0x41;
2831                 phaseinc = 0x20;
2832         } else {
2833                 /* The iCLK virtual clock root frequency is in MHz,
2834                  * but the crtc->mode.clock in in KHz. To get the divisors,
2835                  * it is necessary to divide one by another, so we
2836                  * convert the virtual clock precision to KHz here for higher
2837                  * precision.
2838                  */
2839                 u32 iclk_virtual_root_freq = 172800 * 1000;
2840                 u32 iclk_pi_range = 64;
2841                 u32 desired_divisor, msb_divisor_value, pi_value;
2842
2843                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2844                 msb_divisor_value = desired_divisor / iclk_pi_range;
2845                 pi_value = desired_divisor % iclk_pi_range;
2846
2847                 auxdiv = 0;
2848                 divsel = msb_divisor_value - 2;
2849                 phaseinc = pi_value;
2850         }
2851
2852         /* This should not happen with any sane values */
2853         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2854                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2855         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2856                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2857
2858         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2859                         crtc->mode.clock,
2860                         auxdiv,
2861                         divsel,
2862                         phasedir,
2863                         phaseinc);
2864
2865         /* Program SSCDIVINTPHASE6 */
2866         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2867         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2868         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2869         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2870         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2871         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2872         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2873         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2874
2875         /* Program SSCAUXDIV */
2876         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2877         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2878         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2879         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2880
2881         /* Enable modulator and associated divider */
2882         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2883         temp &= ~SBI_SSCCTL_DISABLE;
2884         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2885
2886         /* Wait for initialization time */
2887         udelay(24);
2888
2889         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2890
2891         mutex_unlock(&dev_priv->dpio_lock);
2892 }
2893
2894 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2895                                                 enum pipe pch_transcoder)
2896 {
2897         struct drm_device *dev = crtc->base.dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2900
2901         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2902                    I915_READ(HTOTAL(cpu_transcoder)));
2903         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2904                    I915_READ(HBLANK(cpu_transcoder)));
2905         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2906                    I915_READ(HSYNC(cpu_transcoder)));
2907
2908         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2909                    I915_READ(VTOTAL(cpu_transcoder)));
2910         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2911                    I915_READ(VBLANK(cpu_transcoder)));
2912         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2913                    I915_READ(VSYNC(cpu_transcoder)));
2914         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2915                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2916 }
2917
2918 /*
2919  * Enable PCH resources required for PCH ports:
2920  *   - PCH PLLs
2921  *   - FDI training & RX/TX
2922  *   - update transcoder timings
2923  *   - DP transcoding bits
2924  *   - transcoder
2925  */
2926 static void ironlake_pch_enable(struct drm_crtc *crtc)
2927 {
2928         struct drm_device *dev = crtc->dev;
2929         struct drm_i915_private *dev_priv = dev->dev_private;
2930         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2931         int pipe = intel_crtc->pipe;
2932         u32 reg, temp;
2933
2934         assert_pch_transcoder_disabled(dev_priv, pipe);
2935
2936         /* Write the TU size bits before fdi link training, so that error
2937          * detection works. */
2938         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2939                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2940
2941         /* For PCH output, training FDI link */
2942         dev_priv->display.fdi_link_train(crtc);
2943
2944         /* XXX: pch pll's can be enabled any time before we enable the PCH
2945          * transcoder, and we actually should do this to not upset any PCH
2946          * transcoder that already use the clock when we share it.
2947          *
2948          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2949          * unconditionally resets the pll - we need that to have the right LVDS
2950          * enable sequence. */
2951         ironlake_enable_pch_pll(intel_crtc);
2952
2953         if (HAS_PCH_CPT(dev)) {
2954                 u32 sel;
2955
2956                 temp = I915_READ(PCH_DPLL_SEL);
2957                 switch (pipe) {
2958                 default:
2959                 case 0:
2960                         temp |= TRANSA_DPLL_ENABLE;
2961                         sel = TRANSA_DPLLB_SEL;
2962                         break;
2963                 case 1:
2964                         temp |= TRANSB_DPLL_ENABLE;
2965                         sel = TRANSB_DPLLB_SEL;
2966                         break;
2967                 case 2:
2968                         temp |= TRANSC_DPLL_ENABLE;
2969                         sel = TRANSC_DPLLB_SEL;
2970                         break;
2971                 }
2972                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2973                         temp |= sel;
2974                 else
2975                         temp &= ~sel;
2976                 I915_WRITE(PCH_DPLL_SEL, temp);
2977         }
2978
2979         /* set transcoder timing, panel must allow it */
2980         assert_panel_unlocked(dev_priv, pipe);
2981         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2982
2983         intel_fdi_normal_train(crtc);
2984
2985         /* For PCH DP, enable TRANS_DP_CTL */
2986         if (HAS_PCH_CPT(dev) &&
2987             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2988              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2989                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2990                 reg = TRANS_DP_CTL(pipe);
2991                 temp = I915_READ(reg);
2992                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2993                           TRANS_DP_SYNC_MASK |
2994                           TRANS_DP_BPC_MASK);
2995                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2996                          TRANS_DP_ENH_FRAMING);
2997                 temp |= bpc << 9; /* same format but at 11:9 */
2998
2999                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3000                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3001                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3002                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3003
3004                 switch (intel_trans_dp_port_sel(crtc)) {
3005                 case PCH_DP_B:
3006                         temp |= TRANS_DP_PORT_SEL_B;
3007                         break;
3008                 case PCH_DP_C:
3009                         temp |= TRANS_DP_PORT_SEL_C;
3010                         break;
3011                 case PCH_DP_D:
3012                         temp |= TRANS_DP_PORT_SEL_D;
3013                         break;
3014                 default:
3015                         BUG();
3016                 }
3017
3018                 I915_WRITE(reg, temp);
3019         }
3020
3021         ironlake_enable_pch_transcoder(dev_priv, pipe);
3022 }
3023
3024 static void lpt_pch_enable(struct drm_crtc *crtc)
3025 {
3026         struct drm_device *dev = crtc->dev;
3027         struct drm_i915_private *dev_priv = dev->dev_private;
3028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3030
3031         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3032
3033         lpt_program_iclkip(crtc);
3034
3035         /* Set transcoder timing. */
3036         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3037
3038         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3039 }
3040
3041 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3042 {
3043         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3044
3045         if (pll == NULL)
3046                 return;
3047
3048         if (pll->refcount == 0) {
3049                 WARN(1, "bad PCH PLL refcount\n");
3050                 return;
3051         }
3052
3053         --pll->refcount;
3054         intel_crtc->pch_pll = NULL;
3055 }
3056
3057 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3058 {
3059         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3060         struct intel_pch_pll *pll;
3061         int i;
3062
3063         pll = intel_crtc->pch_pll;
3064         if (pll) {
3065                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3066                               intel_crtc->base.base.id, pll->pll_reg);
3067                 goto prepare;
3068         }
3069
3070         if (HAS_PCH_IBX(dev_priv->dev)) {
3071                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3072                 i = intel_crtc->pipe;
3073                 pll = &dev_priv->pch_plls[i];
3074
3075                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3076                               intel_crtc->base.base.id, pll->pll_reg);
3077
3078                 goto found;
3079         }
3080
3081         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3082                 pll = &dev_priv->pch_plls[i];
3083
3084                 /* Only want to check enabled timings first */
3085                 if (pll->refcount == 0)
3086                         continue;
3087
3088                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3089                     fp == I915_READ(pll->fp0_reg)) {
3090                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3091                                       intel_crtc->base.base.id,
3092                                       pll->pll_reg, pll->refcount, pll->active);
3093
3094                         goto found;
3095                 }
3096         }
3097
3098         /* Ok no matching timings, maybe there's a free one? */
3099         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3100                 pll = &dev_priv->pch_plls[i];
3101                 if (pll->refcount == 0) {
3102                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3103                                       intel_crtc->base.base.id, pll->pll_reg);
3104                         goto found;
3105                 }
3106         }
3107
3108         return NULL;
3109
3110 found:
3111         intel_crtc->pch_pll = pll;
3112         pll->refcount++;
3113         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3114 prepare: /* separate function? */
3115         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3116
3117         /* Wait for the clocks to stabilize before rewriting the regs */
3118         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3119         POSTING_READ(pll->pll_reg);
3120         udelay(150);
3121
3122         I915_WRITE(pll->fp0_reg, fp);
3123         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3124         pll->on = false;
3125         return pll;
3126 }
3127
3128 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3129 {
3130         struct drm_i915_private *dev_priv = dev->dev_private;
3131         int dslreg = PIPEDSL(pipe);
3132         u32 temp;
3133
3134         temp = I915_READ(dslreg);
3135         udelay(500);
3136         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3137                 if (wait_for(I915_READ(dslreg) != temp, 5))
3138                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3139         }
3140 }
3141
3142 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3143 {
3144         struct drm_device *dev = crtc->base.dev;
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         int pipe = crtc->pipe;
3147
3148         if (crtc->config.pch_pfit.size) {
3149                 /* Force use of hard-coded filter coefficients
3150                  * as some pre-programmed values are broken,
3151                  * e.g. x201.
3152                  */
3153                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3154                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3155                                                  PF_PIPE_SEL_IVB(pipe));
3156                 else
3157                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3158                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3159                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3160         }
3161 }
3162
3163 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3164 {
3165         struct drm_device *dev = crtc->dev;
3166         struct drm_i915_private *dev_priv = dev->dev_private;
3167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168         struct intel_encoder *encoder;
3169         int pipe = intel_crtc->pipe;
3170         int plane = intel_crtc->plane;
3171         u32 temp;
3172
3173         WARN_ON(!crtc->enabled);
3174
3175         if (intel_crtc->active)
3176                 return;
3177
3178         intel_crtc->active = true;
3179
3180         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3181         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3182
3183         intel_update_watermarks(dev);
3184
3185         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3186                 temp = I915_READ(PCH_LVDS);
3187                 if ((temp & LVDS_PORT_EN) == 0)
3188                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3189         }
3190
3191
3192         if (intel_crtc->config.has_pch_encoder) {
3193                 /* Note: FDI PLL enabling _must_ be done before we enable the
3194                  * cpu pipes, hence this is separate from all the other fdi/pch
3195                  * enabling. */
3196                 ironlake_fdi_pll_enable(intel_crtc);
3197         } else {
3198                 assert_fdi_tx_disabled(dev_priv, pipe);
3199                 assert_fdi_rx_disabled(dev_priv, pipe);
3200         }
3201
3202         for_each_encoder_on_crtc(dev, crtc, encoder)
3203                 if (encoder->pre_enable)
3204                         encoder->pre_enable(encoder);
3205
3206         /* Enable panel fitting for LVDS */
3207         ironlake_pfit_enable(intel_crtc);
3208
3209         /*
3210          * On ILK+ LUT must be loaded before the pipe is running but with
3211          * clocks enabled
3212          */
3213         intel_crtc_load_lut(crtc);
3214
3215         intel_enable_pipe(dev_priv, pipe,
3216                           intel_crtc->config.has_pch_encoder);
3217         intel_enable_plane(dev_priv, plane, pipe);
3218
3219         if (intel_crtc->config.has_pch_encoder)
3220                 ironlake_pch_enable(crtc);
3221
3222         mutex_lock(&dev->struct_mutex);
3223         intel_update_fbc(dev);
3224         mutex_unlock(&dev->struct_mutex);
3225
3226         intel_crtc_update_cursor(crtc, true);
3227
3228         for_each_encoder_on_crtc(dev, crtc, encoder)
3229                 encoder->enable(encoder);
3230
3231         if (HAS_PCH_CPT(dev))
3232                 cpt_verify_modeset(dev, intel_crtc->pipe);
3233
3234         /*
3235          * There seems to be a race in PCH platform hw (at least on some
3236          * outputs) where an enabled pipe still completes any pageflip right
3237          * away (as if the pipe is off) instead of waiting for vblank. As soon
3238          * as the first vblank happend, everything works as expected. Hence just
3239          * wait for one vblank before returning to avoid strange things
3240          * happening.
3241          */
3242         intel_wait_for_vblank(dev, intel_crtc->pipe);
3243 }
3244
3245 static void haswell_crtc_enable(struct drm_crtc *crtc)
3246 {
3247         struct drm_device *dev = crtc->dev;
3248         struct drm_i915_private *dev_priv = dev->dev_private;
3249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3250         struct intel_encoder *encoder;
3251         int pipe = intel_crtc->pipe;
3252         int plane = intel_crtc->plane;
3253
3254         WARN_ON(!crtc->enabled);
3255
3256         if (intel_crtc->active)
3257                 return;
3258
3259         intel_crtc->active = true;
3260
3261         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3262         if (intel_crtc->config.has_pch_encoder)
3263                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3264
3265         intel_update_watermarks(dev);
3266
3267         if (intel_crtc->config.has_pch_encoder)
3268                 dev_priv->display.fdi_link_train(crtc);
3269
3270         for_each_encoder_on_crtc(dev, crtc, encoder)
3271                 if (encoder->pre_enable)
3272                         encoder->pre_enable(encoder);
3273
3274         intel_ddi_enable_pipe_clock(intel_crtc);
3275
3276         /* Enable panel fitting for eDP */
3277         ironlake_pfit_enable(intel_crtc);
3278
3279         /*
3280          * On ILK+ LUT must be loaded before the pipe is running but with
3281          * clocks enabled
3282          */
3283         intel_crtc_load_lut(crtc);
3284
3285         intel_ddi_set_pipe_settings(crtc);
3286         intel_ddi_enable_transcoder_func(crtc);
3287
3288         intel_enable_pipe(dev_priv, pipe,
3289                           intel_crtc->config.has_pch_encoder);
3290         intel_enable_plane(dev_priv, plane, pipe);
3291
3292         if (intel_crtc->config.has_pch_encoder)
3293                 lpt_pch_enable(crtc);
3294
3295         mutex_lock(&dev->struct_mutex);
3296         intel_update_fbc(dev);
3297         mutex_unlock(&dev->struct_mutex);
3298
3299         intel_crtc_update_cursor(crtc, true);
3300
3301         for_each_encoder_on_crtc(dev, crtc, encoder)
3302                 encoder->enable(encoder);
3303
3304         /*
3305          * There seems to be a race in PCH platform hw (at least on some
3306          * outputs) where an enabled pipe still completes any pageflip right
3307          * away (as if the pipe is off) instead of waiting for vblank. As soon
3308          * as the first vblank happend, everything works as expected. Hence just
3309          * wait for one vblank before returning to avoid strange things
3310          * happening.
3311          */
3312         intel_wait_for_vblank(dev, intel_crtc->pipe);
3313 }
3314
3315 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3316 {
3317         struct drm_device *dev = crtc->base.dev;
3318         struct drm_i915_private *dev_priv = dev->dev_private;
3319         int pipe = crtc->pipe;
3320
3321         /* To avoid upsetting the power well on haswell only disable the pfit if
3322          * it's in use. The hw state code will make sure we get this right. */
3323         if (crtc->config.pch_pfit.size) {
3324                 I915_WRITE(PF_CTL(pipe), 0);
3325                 I915_WRITE(PF_WIN_POS(pipe), 0);
3326                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3327         }
3328 }
3329
3330 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3331 {
3332         struct drm_device *dev = crtc->dev;
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335         struct intel_encoder *encoder;
3336         int pipe = intel_crtc->pipe;
3337         int plane = intel_crtc->plane;
3338         u32 reg, temp;
3339
3340
3341         if (!intel_crtc->active)
3342                 return;
3343
3344         for_each_encoder_on_crtc(dev, crtc, encoder)
3345                 encoder->disable(encoder);
3346
3347         intel_crtc_wait_for_pending_flips(crtc);
3348         drm_vblank_off(dev, pipe);
3349         intel_crtc_update_cursor(crtc, false);
3350
3351         intel_disable_plane(dev_priv, plane, pipe);
3352
3353         if (dev_priv->cfb_plane == plane)
3354                 intel_disable_fbc(dev);
3355
3356         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3357         intel_disable_pipe(dev_priv, pipe);
3358
3359         ironlake_pfit_disable(intel_crtc);
3360
3361         for_each_encoder_on_crtc(dev, crtc, encoder)
3362                 if (encoder->post_disable)
3363                         encoder->post_disable(encoder);
3364
3365         ironlake_fdi_disable(crtc);
3366
3367         ironlake_disable_pch_transcoder(dev_priv, pipe);
3368         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3369
3370         if (HAS_PCH_CPT(dev)) {
3371                 /* disable TRANS_DP_CTL */
3372                 reg = TRANS_DP_CTL(pipe);
3373                 temp = I915_READ(reg);
3374                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3375                 temp |= TRANS_DP_PORT_SEL_NONE;
3376                 I915_WRITE(reg, temp);
3377
3378                 /* disable DPLL_SEL */
3379                 temp = I915_READ(PCH_DPLL_SEL);
3380                 switch (pipe) {
3381                 case 0:
3382                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3383                         break;
3384                 case 1:
3385                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3386                         break;
3387                 case 2:
3388                         /* C shares PLL A or B */
3389                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3390                         break;
3391                 default:
3392                         BUG(); /* wtf */
3393                 }
3394                 I915_WRITE(PCH_DPLL_SEL, temp);
3395         }
3396
3397         /* disable PCH DPLL */
3398         intel_disable_pch_pll(intel_crtc);
3399
3400         ironlake_fdi_pll_disable(intel_crtc);
3401
3402         intel_crtc->active = false;
3403         intel_update_watermarks(dev);
3404
3405         mutex_lock(&dev->struct_mutex);
3406         intel_update_fbc(dev);
3407         mutex_unlock(&dev->struct_mutex);
3408 }
3409
3410 static void haswell_crtc_disable(struct drm_crtc *crtc)
3411 {
3412         struct drm_device *dev = crtc->dev;
3413         struct drm_i915_private *dev_priv = dev->dev_private;
3414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415         struct intel_encoder *encoder;
3416         int pipe = intel_crtc->pipe;
3417         int plane = intel_crtc->plane;
3418         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3419
3420         if (!intel_crtc->active)
3421                 return;
3422
3423         for_each_encoder_on_crtc(dev, crtc, encoder)
3424                 encoder->disable(encoder);
3425
3426         intel_crtc_wait_for_pending_flips(crtc);
3427         drm_vblank_off(dev, pipe);
3428         intel_crtc_update_cursor(crtc, false);
3429
3430         /* FBC must be disabled before disabling the plane on HSW. */
3431         if (dev_priv->cfb_plane == plane)
3432                 intel_disable_fbc(dev);
3433
3434         intel_disable_plane(dev_priv, plane, pipe);
3435
3436         if (intel_crtc->config.has_pch_encoder)
3437                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3438         intel_disable_pipe(dev_priv, pipe);
3439
3440         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3441
3442         ironlake_pfit_disable(intel_crtc);
3443
3444         intel_ddi_disable_pipe_clock(intel_crtc);
3445
3446         for_each_encoder_on_crtc(dev, crtc, encoder)
3447                 if (encoder->post_disable)
3448                         encoder->post_disable(encoder);
3449
3450         if (intel_crtc->config.has_pch_encoder) {
3451                 lpt_disable_pch_transcoder(dev_priv);
3452                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3453                 intel_ddi_fdi_disable(crtc);
3454         }
3455
3456         intel_crtc->active = false;
3457         intel_update_watermarks(dev);
3458
3459         mutex_lock(&dev->struct_mutex);
3460         intel_update_fbc(dev);
3461         mutex_unlock(&dev->struct_mutex);
3462 }
3463
3464 static void ironlake_crtc_off(struct drm_crtc *crtc)
3465 {
3466         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3467         intel_put_pch_pll(intel_crtc);
3468 }
3469
3470 static void haswell_crtc_off(struct drm_crtc *crtc)
3471 {
3472         intel_ddi_put_crtc_pll(crtc);
3473 }
3474
3475 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3476 {
3477         if (!enable && intel_crtc->overlay) {
3478                 struct drm_device *dev = intel_crtc->base.dev;
3479                 struct drm_i915_private *dev_priv = dev->dev_private;
3480
3481                 mutex_lock(&dev->struct_mutex);
3482                 dev_priv->mm.interruptible = false;
3483                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3484                 dev_priv->mm.interruptible = true;
3485                 mutex_unlock(&dev->struct_mutex);
3486         }
3487
3488         /* Let userspace switch the overlay on again. In most cases userspace
3489          * has to recompute where to put it anyway.
3490          */
3491 }
3492
3493 /**
3494  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3495  * cursor plane briefly if not already running after enabling the display
3496  * plane.
3497  * This workaround avoids occasional blank screens when self refresh is
3498  * enabled.
3499  */
3500 static void
3501 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3502 {
3503         u32 cntl = I915_READ(CURCNTR(pipe));
3504
3505         if ((cntl & CURSOR_MODE) == 0) {
3506                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3507
3508                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3509                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3510                 intel_wait_for_vblank(dev_priv->dev, pipe);
3511                 I915_WRITE(CURCNTR(pipe), cntl);
3512                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3513                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3514         }
3515 }
3516
3517 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3518 {
3519         struct drm_device *dev = crtc->base.dev;
3520         struct drm_i915_private *dev_priv = dev->dev_private;
3521         struct intel_crtc_config *pipe_config = &crtc->config;
3522
3523         if (!crtc->config.gmch_pfit.control)
3524                 return;
3525
3526         /*
3527          * The panel fitter should only be adjusted whilst the pipe is disabled,
3528          * according to register description and PRM.
3529          */
3530         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3531         assert_pipe_disabled(dev_priv, crtc->pipe);
3532
3533         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3534         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3535
3536         /* Border color in case we don't scale up to the full screen. Black by
3537          * default, change to something else for debugging. */
3538         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3539 }
3540
3541 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3542 {
3543         struct drm_device *dev = crtc->dev;
3544         struct drm_i915_private *dev_priv = dev->dev_private;
3545         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546         struct intel_encoder *encoder;
3547         int pipe = intel_crtc->pipe;
3548         int plane = intel_crtc->plane;
3549
3550         WARN_ON(!crtc->enabled);
3551
3552         if (intel_crtc->active)
3553                 return;
3554
3555         intel_crtc->active = true;
3556         intel_update_watermarks(dev);
3557
3558         mutex_lock(&dev_priv->dpio_lock);
3559
3560         for_each_encoder_on_crtc(dev, crtc, encoder)
3561                 if (encoder->pre_pll_enable)
3562                         encoder->pre_pll_enable(encoder);
3563
3564         intel_enable_pll(dev_priv, pipe);
3565
3566         for_each_encoder_on_crtc(dev, crtc, encoder)
3567                 if (encoder->pre_enable)
3568                         encoder->pre_enable(encoder);
3569
3570         /* VLV wants encoder enabling _before_ the pipe is up. */
3571         for_each_encoder_on_crtc(dev, crtc, encoder)
3572                 encoder->enable(encoder);
3573
3574         /* Enable panel fitting for eDP */
3575         i9xx_pfit_enable(intel_crtc);
3576
3577         intel_enable_pipe(dev_priv, pipe, false);
3578         intel_enable_plane(dev_priv, plane, pipe);
3579
3580         intel_crtc_load_lut(crtc);
3581         intel_update_fbc(dev);
3582
3583         /* Give the overlay scaler a chance to enable if it's on this pipe */
3584         intel_crtc_dpms_overlay(intel_crtc, true);
3585         intel_crtc_update_cursor(crtc, true);
3586
3587         mutex_unlock(&dev_priv->dpio_lock);
3588 }
3589
3590 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3591 {
3592         struct drm_device *dev = crtc->dev;
3593         struct drm_i915_private *dev_priv = dev->dev_private;
3594         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3595         struct intel_encoder *encoder;
3596         int pipe = intel_crtc->pipe;
3597         int plane = intel_crtc->plane;
3598
3599         WARN_ON(!crtc->enabled);
3600
3601         if (intel_crtc->active)
3602                 return;
3603
3604         intel_crtc->active = true;
3605         intel_update_watermarks(dev);
3606
3607         intel_enable_pll(dev_priv, pipe);
3608
3609         for_each_encoder_on_crtc(dev, crtc, encoder)
3610                 if (encoder->pre_enable)
3611                         encoder->pre_enable(encoder);
3612
3613         /* Enable panel fitting for LVDS */
3614         i9xx_pfit_enable(intel_crtc);
3615
3616         intel_enable_pipe(dev_priv, pipe, false);
3617         intel_enable_plane(dev_priv, plane, pipe);
3618         if (IS_G4X(dev))
3619                 g4x_fixup_plane(dev_priv, pipe);
3620
3621         intel_crtc_load_lut(crtc);
3622         intel_update_fbc(dev);
3623
3624         /* Give the overlay scaler a chance to enable if it's on this pipe */
3625         intel_crtc_dpms_overlay(intel_crtc, true);
3626         intel_crtc_update_cursor(crtc, true);
3627
3628         for_each_encoder_on_crtc(dev, crtc, encoder)
3629                 encoder->enable(encoder);
3630 }
3631
3632 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3633 {
3634         struct drm_device *dev = crtc->base.dev;
3635         struct drm_i915_private *dev_priv = dev->dev_private;
3636
3637         if (!crtc->config.gmch_pfit.control)
3638                 return;
3639
3640         assert_pipe_disabled(dev_priv, crtc->pipe);
3641
3642         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3643                          I915_READ(PFIT_CONTROL));
3644         I915_WRITE(PFIT_CONTROL, 0);
3645 }
3646
3647 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3648 {
3649         struct drm_device *dev = crtc->dev;
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652         struct intel_encoder *encoder;
3653         int pipe = intel_crtc->pipe;
3654         int plane = intel_crtc->plane;
3655
3656         if (!intel_crtc->active)
3657                 return;
3658
3659         for_each_encoder_on_crtc(dev, crtc, encoder)
3660                 encoder->disable(encoder);
3661
3662         /* Give the overlay scaler a chance to disable if it's on this pipe */
3663         intel_crtc_wait_for_pending_flips(crtc);
3664         drm_vblank_off(dev, pipe);
3665         intel_crtc_dpms_overlay(intel_crtc, false);
3666         intel_crtc_update_cursor(crtc, false);
3667
3668         if (dev_priv->cfb_plane == plane)
3669                 intel_disable_fbc(dev);
3670
3671         intel_disable_plane(dev_priv, plane, pipe);
3672         intel_disable_pipe(dev_priv, pipe);
3673
3674         i9xx_pfit_disable(intel_crtc);
3675
3676         for_each_encoder_on_crtc(dev, crtc, encoder)
3677                 if (encoder->post_disable)
3678                         encoder->post_disable(encoder);
3679
3680         intel_disable_pll(dev_priv, pipe);
3681
3682         intel_crtc->active = false;
3683         intel_update_fbc(dev);
3684         intel_update_watermarks(dev);
3685 }
3686
3687 static void i9xx_crtc_off(struct drm_crtc *crtc)
3688 {
3689 }
3690
3691 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3692                                     bool enabled)
3693 {
3694         struct drm_device *dev = crtc->dev;
3695         struct drm_i915_master_private *master_priv;
3696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3697         int pipe = intel_crtc->pipe;
3698
3699         if (!dev->primary->master)
3700                 return;
3701
3702         master_priv = dev->primary->master->driver_priv;
3703         if (!master_priv->sarea_priv)
3704                 return;
3705
3706         switch (pipe) {
3707         case 0:
3708                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3709                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3710                 break;
3711         case 1:
3712                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3713                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3714                 break;
3715         default:
3716                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3717                 break;
3718         }
3719 }
3720
3721 /**
3722  * Sets the power management mode of the pipe and plane.
3723  */
3724 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3725 {
3726         struct drm_device *dev = crtc->dev;
3727         struct drm_i915_private *dev_priv = dev->dev_private;
3728         struct intel_encoder *intel_encoder;
3729         bool enable = false;
3730
3731         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3732                 enable |= intel_encoder->connectors_active;
3733
3734         if (enable)
3735                 dev_priv->display.crtc_enable(crtc);
3736         else
3737                 dev_priv->display.crtc_disable(crtc);
3738
3739         intel_crtc_update_sarea(crtc, enable);
3740 }
3741
3742 static void intel_crtc_disable(struct drm_crtc *crtc)
3743 {
3744         struct drm_device *dev = crtc->dev;
3745         struct drm_connector *connector;
3746         struct drm_i915_private *dev_priv = dev->dev_private;
3747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3748
3749         /* crtc should still be enabled when we disable it. */
3750         WARN_ON(!crtc->enabled);
3751
3752         dev_priv->display.crtc_disable(crtc);
3753         intel_crtc->eld_vld = false;
3754         intel_crtc_update_sarea(crtc, false);
3755         dev_priv->display.off(crtc);
3756
3757         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3758         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3759
3760         if (crtc->fb) {
3761                 mutex_lock(&dev->struct_mutex);
3762                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3763                 mutex_unlock(&dev->struct_mutex);
3764                 crtc->fb = NULL;
3765         }
3766
3767         /* Update computed state. */
3768         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3769                 if (!connector->encoder || !connector->encoder->crtc)
3770                         continue;
3771
3772                 if (connector->encoder->crtc != crtc)
3773                         continue;
3774
3775                 connector->dpms = DRM_MODE_DPMS_OFF;
3776                 to_intel_encoder(connector->encoder)->connectors_active = false;
3777         }
3778 }
3779
3780 void intel_modeset_disable(struct drm_device *dev)
3781 {
3782         struct drm_crtc *crtc;
3783
3784         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3785                 if (crtc->enabled)
3786                         intel_crtc_disable(crtc);
3787         }
3788 }
3789
3790 void intel_encoder_destroy(struct drm_encoder *encoder)
3791 {
3792         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3793
3794         drm_encoder_cleanup(encoder);
3795         kfree(intel_encoder);
3796 }
3797
3798 /* Simple dpms helper for encodres with just one connector, no cloning and only
3799  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3800  * state of the entire output pipe. */
3801 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3802 {
3803         if (mode == DRM_MODE_DPMS_ON) {
3804                 encoder->connectors_active = true;
3805
3806                 intel_crtc_update_dpms(encoder->base.crtc);
3807         } else {
3808                 encoder->connectors_active = false;
3809
3810                 intel_crtc_update_dpms(encoder->base.crtc);
3811         }
3812 }
3813
3814 /* Cross check the actual hw state with our own modeset state tracking (and it's
3815  * internal consistency). */
3816 static void intel_connector_check_state(struct intel_connector *connector)
3817 {
3818         if (connector->get_hw_state(connector)) {
3819                 struct intel_encoder *encoder = connector->encoder;
3820                 struct drm_crtc *crtc;
3821                 bool encoder_enabled;
3822                 enum pipe pipe;
3823
3824                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3825                               connector->base.base.id,
3826                               drm_get_connector_name(&connector->base));
3827
3828                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3829                      "wrong connector dpms state\n");
3830                 WARN(connector->base.encoder != &encoder->base,
3831                      "active connector not linked to encoder\n");
3832                 WARN(!encoder->connectors_active,
3833                      "encoder->connectors_active not set\n");
3834
3835                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3836                 WARN(!encoder_enabled, "encoder not enabled\n");
3837                 if (WARN_ON(!encoder->base.crtc))
3838                         return;
3839
3840                 crtc = encoder->base.crtc;
3841
3842                 WARN(!crtc->enabled, "crtc not enabled\n");
3843                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3844                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3845                      "encoder active on the wrong pipe\n");
3846         }
3847 }
3848
3849 /* Even simpler default implementation, if there's really no special case to
3850  * consider. */
3851 void intel_connector_dpms(struct drm_connector *connector, int mode)
3852 {
3853         struct intel_encoder *encoder = intel_attached_encoder(connector);
3854
3855         /* All the simple cases only support two dpms states. */
3856         if (mode != DRM_MODE_DPMS_ON)
3857                 mode = DRM_MODE_DPMS_OFF;
3858
3859         if (mode == connector->dpms)
3860                 return;
3861
3862         connector->dpms = mode;
3863
3864         /* Only need to change hw state when actually enabled */
3865         if (encoder->base.crtc)
3866                 intel_encoder_dpms(encoder, mode);
3867         else
3868                 WARN_ON(encoder->connectors_active != false);
3869
3870         intel_modeset_check_state(connector->dev);
3871 }
3872
3873 /* Simple connector->get_hw_state implementation for encoders that support only
3874  * one connector and no cloning and hence the encoder state determines the state
3875  * of the connector. */
3876 bool intel_connector_get_hw_state(struct intel_connector *connector)
3877 {
3878         enum pipe pipe = 0;
3879         struct intel_encoder *encoder = connector->encoder;
3880
3881         return encoder->get_hw_state(encoder, &pipe);
3882 }
3883
3884 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3885                                      struct intel_crtc_config *pipe_config)
3886 {
3887         struct drm_i915_private *dev_priv = dev->dev_private;
3888         struct intel_crtc *pipe_B_crtc =
3889                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3890
3891         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3892                       pipe_name(pipe), pipe_config->fdi_lanes);
3893         if (pipe_config->fdi_lanes > 4) {
3894                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3895                               pipe_name(pipe), pipe_config->fdi_lanes);
3896                 return false;
3897         }
3898
3899         if (IS_HASWELL(dev)) {
3900                 if (pipe_config->fdi_lanes > 2) {
3901                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3902                                       pipe_config->fdi_lanes);
3903                         return false;
3904                 } else {
3905                         return true;
3906                 }
3907         }
3908
3909         if (INTEL_INFO(dev)->num_pipes == 2)
3910                 return true;
3911
3912         /* Ivybridge 3 pipe is really complicated */
3913         switch (pipe) {
3914         case PIPE_A:
3915                 return true;
3916         case PIPE_B:
3917                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3918                     pipe_config->fdi_lanes > 2) {
3919                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3920                                       pipe_name(pipe), pipe_config->fdi_lanes);
3921                         return false;
3922                 }
3923                 return true;
3924         case PIPE_C:
3925                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3926                     pipe_B_crtc->config.fdi_lanes <= 2) {
3927                         if (pipe_config->fdi_lanes > 2) {
3928                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3929                                               pipe_name(pipe), pipe_config->fdi_lanes);
3930                                 return false;
3931                         }
3932                 } else {
3933                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3934                         return false;
3935                 }
3936                 return true;
3937         default:
3938                 BUG();
3939         }
3940 }
3941
3942 #define RETRY 1
3943 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3944                                        struct intel_crtc_config *pipe_config)
3945 {
3946         struct drm_device *dev = intel_crtc->base.dev;
3947         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3948         int target_clock, lane, link_bw;
3949         bool setup_ok, needs_recompute = false;
3950
3951 retry:
3952         /* FDI is a binary signal running at ~2.7GHz, encoding
3953          * each output octet as 10 bits. The actual frequency
3954          * is stored as a divider into a 100MHz clock, and the
3955          * mode pixel clock is stored in units of 1KHz.
3956          * Hence the bw of each lane in terms of the mode signal
3957          * is:
3958          */
3959         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3960
3961         if (pipe_config->pixel_target_clock)
3962                 target_clock = pipe_config->pixel_target_clock;
3963         else
3964                 target_clock = adjusted_mode->clock;
3965
3966         lane = ironlake_get_lanes_required(target_clock, link_bw,
3967                                            pipe_config->pipe_bpp);
3968
3969         pipe_config->fdi_lanes = lane;
3970
3971         if (pipe_config->pixel_multiplier > 1)
3972                 link_bw *= pipe_config->pixel_multiplier;
3973         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
3974                                link_bw, &pipe_config->fdi_m_n);
3975
3976         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
3977                                             intel_crtc->pipe, pipe_config);
3978         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
3979                 pipe_config->pipe_bpp -= 2*3;
3980                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
3981                               pipe_config->pipe_bpp);
3982                 needs_recompute = true;
3983                 pipe_config->bw_constrained = true;
3984
3985                 goto retry;
3986         }
3987
3988         if (needs_recompute)
3989                 return RETRY;
3990
3991         return setup_ok ? 0 : -EINVAL;
3992 }
3993
3994 static int intel_crtc_compute_config(struct drm_crtc *crtc,
3995                                      struct intel_crtc_config *pipe_config)
3996 {
3997         struct drm_device *dev = crtc->dev;
3998         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3999
4000         if (HAS_PCH_SPLIT(dev)) {
4001                 /* FDI link clock is fixed at 2.7G */
4002                 if (pipe_config->requested_mode.clock * 3
4003                     > IRONLAKE_FDI_FREQ * 4)
4004                         return -EINVAL;
4005         }
4006
4007         /* All interlaced capable intel hw wants timings in frames. Note though
4008          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4009          * timings, so we need to be careful not to clobber these.*/
4010         if (!pipe_config->timings_set)
4011                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4012
4013         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4014          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4015          */
4016         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4017                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4018                 return -EINVAL;
4019
4020         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4021                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4022         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4023                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4024                  * for lvds. */
4025                 pipe_config->pipe_bpp = 8*3;
4026         }
4027
4028         if (pipe_config->has_pch_encoder)
4029                 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4030
4031         return 0;
4032 }
4033
4034 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4035 {
4036         return 400000; /* FIXME */
4037 }
4038
4039 static int i945_get_display_clock_speed(struct drm_device *dev)
4040 {
4041         return 400000;
4042 }
4043
4044 static int i915_get_display_clock_speed(struct drm_device *dev)
4045 {
4046         return 333000;
4047 }
4048
4049 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4050 {
4051         return 200000;
4052 }
4053
4054 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4055 {
4056         u16 gcfgc = 0;
4057
4058         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4059
4060         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4061                 return 133000;
4062         else {
4063                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4064                 case GC_DISPLAY_CLOCK_333_MHZ:
4065                         return 333000;
4066                 default:
4067                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4068                         return 190000;
4069                 }
4070         }
4071 }
4072
4073 static int i865_get_display_clock_speed(struct drm_device *dev)
4074 {
4075         return 266000;
4076 }
4077
4078 static int i855_get_display_clock_speed(struct drm_device *dev)
4079 {
4080         u16 hpllcc = 0;
4081         /* Assume that the hardware is in the high speed state.  This
4082          * should be the default.
4083          */
4084         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4085         case GC_CLOCK_133_200:
4086         case GC_CLOCK_100_200:
4087                 return 200000;
4088         case GC_CLOCK_166_250:
4089                 return 250000;
4090         case GC_CLOCK_100_133:
4091                 return 133000;
4092         }
4093
4094         /* Shouldn't happen */
4095         return 0;
4096 }
4097
4098 static int i830_get_display_clock_speed(struct drm_device *dev)
4099 {
4100         return 133000;
4101 }
4102
4103 static void
4104 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4105 {
4106         while (*num > DATA_LINK_M_N_MASK ||
4107                *den > DATA_LINK_M_N_MASK) {
4108                 *num >>= 1;
4109                 *den >>= 1;
4110         }
4111 }
4112
4113 static void compute_m_n(unsigned int m, unsigned int n,
4114                         uint32_t *ret_m, uint32_t *ret_n)
4115 {
4116         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4117         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4118         intel_reduce_m_n_ratio(ret_m, ret_n);
4119 }
4120
4121 void
4122 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4123                        int pixel_clock, int link_clock,
4124                        struct intel_link_m_n *m_n)
4125 {
4126         m_n->tu = 64;
4127
4128         compute_m_n(bits_per_pixel * pixel_clock,
4129                     link_clock * nlanes * 8,
4130                     &m_n->gmch_m, &m_n->gmch_n);
4131
4132         compute_m_n(pixel_clock, link_clock,
4133                     &m_n->link_m, &m_n->link_n);
4134 }
4135
4136 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4137 {
4138         if (i915_panel_use_ssc >= 0)
4139                 return i915_panel_use_ssc != 0;
4140         return dev_priv->vbt.lvds_use_ssc
4141                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4142 }
4143
4144 static int vlv_get_refclk(struct drm_crtc *crtc)
4145 {
4146         struct drm_device *dev = crtc->dev;
4147         struct drm_i915_private *dev_priv = dev->dev_private;
4148         int refclk = 27000; /* for DP & HDMI */
4149
4150         return 100000; /* only one validated so far */
4151
4152         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4153                 refclk = 96000;
4154         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4155                 if (intel_panel_use_ssc(dev_priv))
4156                         refclk = 100000;
4157                 else
4158                         refclk = 96000;
4159         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4160                 refclk = 100000;
4161         }
4162
4163         return refclk;
4164 }
4165
4166 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4167 {
4168         struct drm_device *dev = crtc->dev;
4169         struct drm_i915_private *dev_priv = dev->dev_private;
4170         int refclk;
4171
4172         if (IS_VALLEYVIEW(dev)) {
4173                 refclk = vlv_get_refclk(crtc);
4174         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4175             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4176                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4177                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4178                               refclk / 1000);
4179         } else if (!IS_GEN2(dev)) {
4180                 refclk = 96000;
4181         } else {
4182                 refclk = 48000;
4183         }
4184
4185         return refclk;
4186 }
4187
4188 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4189 {
4190         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4191 }
4192
4193 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4194 {
4195         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4196 }
4197
4198 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4199                                      intel_clock_t *reduced_clock)
4200 {
4201         struct drm_device *dev = crtc->base.dev;
4202         struct drm_i915_private *dev_priv = dev->dev_private;
4203         int pipe = crtc->pipe;
4204         u32 fp, fp2 = 0;
4205
4206         if (IS_PINEVIEW(dev)) {
4207                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4208                 if (reduced_clock)
4209                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4210         } else {
4211                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4212                 if (reduced_clock)
4213                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4214         }
4215
4216         I915_WRITE(FP0(pipe), fp);
4217
4218         crtc->lowfreq_avail = false;
4219         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4220             reduced_clock && i915_powersave) {
4221                 I915_WRITE(FP1(pipe), fp2);
4222                 crtc->lowfreq_avail = true;
4223         } else {
4224                 I915_WRITE(FP1(pipe), fp);
4225         }
4226 }
4227
4228 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4229 {
4230         u32 reg_val;
4231
4232         /*
4233          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4234          * and set it to a reasonable value instead.
4235          */
4236         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4237         reg_val &= 0xffffff00;
4238         reg_val |= 0x00000030;
4239         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4240
4241         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4242         reg_val &= 0x8cffffff;
4243         reg_val = 0x8c000000;
4244         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4245
4246         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4247         reg_val &= 0xffffff00;
4248         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4249
4250         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4251         reg_val &= 0x00ffffff;
4252         reg_val |= 0xb0000000;
4253         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4254 }
4255
4256 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4257                                          struct intel_link_m_n *m_n)
4258 {
4259         struct drm_device *dev = crtc->base.dev;
4260         struct drm_i915_private *dev_priv = dev->dev_private;
4261         int pipe = crtc->pipe;
4262
4263         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4264         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4265         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4266         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4267 }
4268
4269 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4270                                          struct intel_link_m_n *m_n)
4271 {
4272         struct drm_device *dev = crtc->base.dev;
4273         struct drm_i915_private *dev_priv = dev->dev_private;
4274         int pipe = crtc->pipe;
4275         enum transcoder transcoder = crtc->config.cpu_transcoder;
4276
4277         if (INTEL_INFO(dev)->gen >= 5) {
4278                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4279                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4280                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4281                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4282         } else {
4283                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4284                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4285                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4286                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4287         }
4288 }
4289
4290 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4291 {
4292         if (crtc->config.has_pch_encoder)
4293                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4294         else
4295                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4296 }
4297
4298 static void vlv_update_pll(struct intel_crtc *crtc)
4299 {
4300         struct drm_device *dev = crtc->base.dev;
4301         struct drm_i915_private *dev_priv = dev->dev_private;
4302         struct drm_display_mode *adjusted_mode =
4303                 &crtc->config.adjusted_mode;
4304         struct intel_encoder *encoder;
4305         int pipe = crtc->pipe;
4306         u32 dpll, mdiv;
4307         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4308         bool is_hdmi;
4309         u32 coreclk, reg_val, dpll_md;
4310
4311         mutex_lock(&dev_priv->dpio_lock);
4312
4313         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4314
4315         bestn = crtc->config.dpll.n;
4316         bestm1 = crtc->config.dpll.m1;
4317         bestm2 = crtc->config.dpll.m2;
4318         bestp1 = crtc->config.dpll.p1;
4319         bestp2 = crtc->config.dpll.p2;
4320
4321         /* See eDP HDMI DPIO driver vbios notes doc */
4322
4323         /* PLL B needs special handling */
4324         if (pipe)
4325                 vlv_pllb_recal_opamp(dev_priv);
4326
4327         /* Set up Tx target for periodic Rcomp update */
4328         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4329
4330         /* Disable target IRef on PLL */
4331         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4332         reg_val &= 0x00ffffff;
4333         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4334
4335         /* Disable fast lock */
4336         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4337
4338         /* Set idtafcrecal before PLL is enabled */
4339         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4340         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4341         mdiv |= ((bestn << DPIO_N_SHIFT));
4342         mdiv |= (1 << DPIO_K_SHIFT);
4343
4344         /*
4345          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4346          * but we don't support that).
4347          * Note: don't use the DAC post divider as it seems unstable.
4348          */
4349         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4350         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4351
4352         mdiv |= DPIO_ENABLE_CALIBRATION;
4353         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4354
4355         /* Set HBR and RBR LPF coefficients */
4356         if (adjusted_mode->clock == 162000 ||
4357             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4358                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4359                                  0x005f0021);
4360         else
4361                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4362                                  0x00d0000f);
4363
4364         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4365             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4366                 /* Use SSC source */
4367                 if (!pipe)
4368                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4369                                          0x0df40000);
4370                 else
4371                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4372                                          0x0df70000);
4373         } else { /* HDMI or VGA */
4374                 /* Use bend source */
4375                 if (!pipe)
4376                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4377                                          0x0df70000);
4378                 else
4379                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4380                                          0x0df40000);
4381         }
4382
4383         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4384         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4385         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4386             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4387                 coreclk |= 0x01000000;
4388         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4389
4390         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4391
4392         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4393                 if (encoder->pre_pll_enable)
4394                         encoder->pre_pll_enable(encoder);
4395
4396         /* Enable DPIO clock input */
4397         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4398                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4399         if (pipe)
4400                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4401
4402         dpll |= DPLL_VCO_ENABLE;
4403         I915_WRITE(DPLL(pipe), dpll);
4404         POSTING_READ(DPLL(pipe));
4405         udelay(150);
4406
4407         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4408                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4409
4410         dpll_md = 0;
4411         if (crtc->config.pixel_multiplier > 1) {
4412                 dpll_md = (crtc->config.pixel_multiplier - 1)
4413                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4414         }
4415         I915_WRITE(DPLL_MD(pipe), dpll_md);
4416         POSTING_READ(DPLL_MD(pipe));
4417
4418         if (crtc->config.has_dp_encoder)
4419                 intel_dp_set_m_n(crtc);
4420
4421         mutex_unlock(&dev_priv->dpio_lock);
4422 }
4423
4424 static void i9xx_update_pll(struct intel_crtc *crtc,
4425                             intel_clock_t *reduced_clock,
4426                             int num_connectors)
4427 {
4428         struct drm_device *dev = crtc->base.dev;
4429         struct drm_i915_private *dev_priv = dev->dev_private;
4430         struct intel_encoder *encoder;
4431         int pipe = crtc->pipe;
4432         u32 dpll;
4433         bool is_sdvo;
4434         struct dpll *clock = &crtc->config.dpll;
4435
4436         i9xx_update_pll_dividers(crtc, reduced_clock);
4437
4438         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4439                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4440
4441         dpll = DPLL_VGA_MODE_DIS;
4442
4443         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4444                 dpll |= DPLLB_MODE_LVDS;
4445         else
4446                 dpll |= DPLLB_MODE_DAC_SERIAL;
4447
4448         if ((crtc->config.pixel_multiplier > 1) &&
4449             (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4450                 dpll |= (crtc->config.pixel_multiplier - 1)
4451                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4452         }
4453
4454         if (is_sdvo)
4455                 dpll |= DPLL_DVO_HIGH_SPEED;
4456
4457         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4458                 dpll |= DPLL_DVO_HIGH_SPEED;
4459
4460         /* compute bitmask from p1 value */
4461         if (IS_PINEVIEW(dev))
4462                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4463         else {
4464                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4465                 if (IS_G4X(dev) && reduced_clock)
4466                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4467         }
4468         switch (clock->p2) {
4469         case 5:
4470                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4471                 break;
4472         case 7:
4473                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4474                 break;
4475         case 10:
4476                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4477                 break;
4478         case 14:
4479                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4480                 break;
4481         }
4482         if (INTEL_INFO(dev)->gen >= 4)
4483                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4484
4485         if (crtc->config.sdvo_tv_clock)
4486                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4487         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4488                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4489                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4490         else
4491                 dpll |= PLL_REF_INPUT_DREFCLK;
4492
4493         dpll |= DPLL_VCO_ENABLE;
4494         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4495         POSTING_READ(DPLL(pipe));
4496         udelay(150);
4497
4498         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4499                 if (encoder->pre_pll_enable)
4500                         encoder->pre_pll_enable(encoder);
4501
4502         if (crtc->config.has_dp_encoder)
4503                 intel_dp_set_m_n(crtc);
4504
4505         I915_WRITE(DPLL(pipe), dpll);
4506
4507         /* Wait for the clocks to stabilize. */
4508         POSTING_READ(DPLL(pipe));
4509         udelay(150);
4510
4511         if (INTEL_INFO(dev)->gen >= 4) {
4512                 u32 dpll_md = 0;
4513                 if (crtc->config.pixel_multiplier > 1) {
4514                         dpll_md = (crtc->config.pixel_multiplier - 1)
4515                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4516                 }
4517                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4518         } else {
4519                 /* The pixel multiplier can only be updated once the
4520                  * DPLL is enabled and the clocks are stable.
4521                  *
4522                  * So write it again.
4523                  */
4524                 I915_WRITE(DPLL(pipe), dpll);
4525         }
4526 }
4527
4528 static void i8xx_update_pll(struct intel_crtc *crtc,
4529                             struct drm_display_mode *adjusted_mode,
4530                             intel_clock_t *reduced_clock,
4531                             int num_connectors)
4532 {
4533         struct drm_device *dev = crtc->base.dev;
4534         struct drm_i915_private *dev_priv = dev->dev_private;
4535         struct intel_encoder *encoder;
4536         int pipe = crtc->pipe;
4537         u32 dpll;
4538         struct dpll *clock = &crtc->config.dpll;
4539
4540         i9xx_update_pll_dividers(crtc, reduced_clock);
4541
4542         dpll = DPLL_VGA_MODE_DIS;
4543
4544         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4545                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4546         } else {
4547                 if (clock->p1 == 2)
4548                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4549                 else
4550                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4551                 if (clock->p2 == 4)
4552                         dpll |= PLL_P2_DIVIDE_BY_4;
4553         }
4554
4555         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4556                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4557                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4558         else
4559                 dpll |= PLL_REF_INPUT_DREFCLK;
4560
4561         dpll |= DPLL_VCO_ENABLE;
4562         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4563         POSTING_READ(DPLL(pipe));
4564         udelay(150);
4565
4566         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4567                 if (encoder->pre_pll_enable)
4568                         encoder->pre_pll_enable(encoder);
4569
4570         I915_WRITE(DPLL(pipe), dpll);
4571
4572         /* Wait for the clocks to stabilize. */
4573         POSTING_READ(DPLL(pipe));
4574         udelay(150);
4575
4576         /* The pixel multiplier can only be updated once the
4577          * DPLL is enabled and the clocks are stable.
4578          *
4579          * So write it again.
4580          */
4581         I915_WRITE(DPLL(pipe), dpll);
4582 }
4583
4584 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4585                                    struct drm_display_mode *mode,
4586                                    struct drm_display_mode *adjusted_mode)
4587 {
4588         struct drm_device *dev = intel_crtc->base.dev;
4589         struct drm_i915_private *dev_priv = dev->dev_private;
4590         enum pipe pipe = intel_crtc->pipe;
4591         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4592         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4593
4594         /* We need to be careful not to changed the adjusted mode, for otherwise
4595          * the hw state checker will get angry at the mismatch. */
4596         crtc_vtotal = adjusted_mode->crtc_vtotal;
4597         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4598
4599         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4600                 /* the chip adds 2 halflines automatically */
4601                 crtc_vtotal -= 1;
4602                 crtc_vblank_end -= 1;
4603                 vsyncshift = adjusted_mode->crtc_hsync_start
4604                              - adjusted_mode->crtc_htotal / 2;
4605         } else {
4606                 vsyncshift = 0;
4607         }
4608
4609         if (INTEL_INFO(dev)->gen > 3)
4610                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4611
4612         I915_WRITE(HTOTAL(cpu_transcoder),
4613                    (adjusted_mode->crtc_hdisplay - 1) |
4614                    ((adjusted_mode->crtc_htotal - 1) << 16));
4615         I915_WRITE(HBLANK(cpu_transcoder),
4616                    (adjusted_mode->crtc_hblank_start - 1) |
4617                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4618         I915_WRITE(HSYNC(cpu_transcoder),
4619                    (adjusted_mode->crtc_hsync_start - 1) |
4620                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4621
4622         I915_WRITE(VTOTAL(cpu_transcoder),
4623                    (adjusted_mode->crtc_vdisplay - 1) |
4624                    ((crtc_vtotal - 1) << 16));
4625         I915_WRITE(VBLANK(cpu_transcoder),
4626                    (adjusted_mode->crtc_vblank_start - 1) |
4627                    ((crtc_vblank_end - 1) << 16));
4628         I915_WRITE(VSYNC(cpu_transcoder),
4629                    (adjusted_mode->crtc_vsync_start - 1) |
4630                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4631
4632         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4633          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4634          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4635          * bits. */
4636         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4637             (pipe == PIPE_B || pipe == PIPE_C))
4638                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4639
4640         /* pipesrc controls the size that is scaled from, which should
4641          * always be the user's requested size.
4642          */
4643         I915_WRITE(PIPESRC(pipe),
4644                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4645 }
4646
4647 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4648                                    struct intel_crtc_config *pipe_config)
4649 {
4650         struct drm_device *dev = crtc->base.dev;
4651         struct drm_i915_private *dev_priv = dev->dev_private;
4652         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4653         uint32_t tmp;
4654
4655         tmp = I915_READ(HTOTAL(cpu_transcoder));
4656         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4657         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4658         tmp = I915_READ(HBLANK(cpu_transcoder));
4659         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4660         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4661         tmp = I915_READ(HSYNC(cpu_transcoder));
4662         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4663         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4664
4665         tmp = I915_READ(VTOTAL(cpu_transcoder));
4666         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4667         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4668         tmp = I915_READ(VBLANK(cpu_transcoder));
4669         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4670         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4671         tmp = I915_READ(VSYNC(cpu_transcoder));
4672         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4673         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4674
4675         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4676                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4677                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4678                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4679         }
4680
4681         tmp = I915_READ(PIPESRC(crtc->pipe));
4682         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4683         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4684 }
4685
4686 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4687 {
4688         struct drm_device *dev = intel_crtc->base.dev;
4689         struct drm_i915_private *dev_priv = dev->dev_private;
4690         uint32_t pipeconf;
4691
4692         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4693
4694         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4695                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4696                  * core speed.
4697                  *
4698                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4699                  * pipe == 0 check?
4700                  */
4701                 if (intel_crtc->config.requested_mode.clock >
4702                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4703                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4704                 else
4705                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4706         }
4707
4708         /* only g4x and later have fancy bpc/dither controls */
4709         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4710                 pipeconf &= ~(PIPECONF_BPC_MASK |
4711                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4712
4713                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4714                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4715                         pipeconf |= PIPECONF_DITHER_EN |
4716                                     PIPECONF_DITHER_TYPE_SP;
4717
4718                 switch (intel_crtc->config.pipe_bpp) {
4719                 case 18:
4720                         pipeconf |= PIPECONF_6BPC;
4721                         break;
4722                 case 24:
4723                         pipeconf |= PIPECONF_8BPC;
4724                         break;
4725                 case 30:
4726                         pipeconf |= PIPECONF_10BPC;
4727                         break;
4728                 default:
4729                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4730                         BUG();
4731                 }
4732         }
4733
4734         if (HAS_PIPE_CXSR(dev)) {
4735                 if (intel_crtc->lowfreq_avail) {
4736                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4737                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4738                 } else {
4739                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4740                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4741                 }
4742         }
4743
4744         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4745         if (!IS_GEN2(dev) &&
4746             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4747                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4748         else
4749                 pipeconf |= PIPECONF_PROGRESSIVE;
4750
4751         if (IS_VALLEYVIEW(dev)) {
4752                 if (intel_crtc->config.limited_color_range)
4753                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4754                 else
4755                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4756         }
4757
4758         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4759         POSTING_READ(PIPECONF(intel_crtc->pipe));
4760 }
4761
4762 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4763                               int x, int y,
4764                               struct drm_framebuffer *fb)
4765 {
4766         struct drm_device *dev = crtc->dev;
4767         struct drm_i915_private *dev_priv = dev->dev_private;
4768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4769         struct drm_display_mode *adjusted_mode =
4770                 &intel_crtc->config.adjusted_mode;
4771         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4772         int pipe = intel_crtc->pipe;
4773         int plane = intel_crtc->plane;
4774         int refclk, num_connectors = 0;
4775         intel_clock_t clock, reduced_clock;
4776         u32 dspcntr;
4777         bool ok, has_reduced_clock = false;
4778         bool is_lvds = false;
4779         struct intel_encoder *encoder;
4780         const intel_limit_t *limit;
4781         int ret;
4782
4783         for_each_encoder_on_crtc(dev, crtc, encoder) {
4784                 switch (encoder->type) {
4785                 case INTEL_OUTPUT_LVDS:
4786                         is_lvds = true;
4787                         break;
4788                 }
4789
4790                 num_connectors++;
4791         }
4792
4793         refclk = i9xx_get_refclk(crtc, num_connectors);
4794
4795         /*
4796          * Returns a set of divisors for the desired target clock with the given
4797          * refclk, or FALSE.  The returned values represent the clock equation:
4798          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4799          */
4800         limit = intel_limit(crtc, refclk);
4801         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4802                              &clock);
4803         if (!ok) {
4804                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4805                 return -EINVAL;
4806         }
4807
4808         /* Ensure that the cursor is valid for the new mode before changing... */
4809         intel_crtc_update_cursor(crtc, true);
4810
4811         if (is_lvds && dev_priv->lvds_downclock_avail) {
4812                 /*
4813                  * Ensure we match the reduced clock's P to the target clock.
4814                  * If the clocks don't match, we can't switch the display clock
4815                  * by using the FP0/FP1. In such case we will disable the LVDS
4816                  * downclock feature.
4817                 */
4818                 has_reduced_clock = limit->find_pll(limit, crtc,
4819                                                     dev_priv->lvds_downclock,
4820                                                     refclk,
4821                                                     &clock,
4822                                                     &reduced_clock);
4823         }
4824         /* Compat-code for transition, will disappear. */
4825         if (!intel_crtc->config.clock_set) {
4826                 intel_crtc->config.dpll.n = clock.n;
4827                 intel_crtc->config.dpll.m1 = clock.m1;
4828                 intel_crtc->config.dpll.m2 = clock.m2;
4829                 intel_crtc->config.dpll.p1 = clock.p1;
4830                 intel_crtc->config.dpll.p2 = clock.p2;
4831         }
4832
4833         if (IS_GEN2(dev))
4834                 i8xx_update_pll(intel_crtc, adjusted_mode,
4835                                 has_reduced_clock ? &reduced_clock : NULL,
4836                                 num_connectors);
4837         else if (IS_VALLEYVIEW(dev))
4838                 vlv_update_pll(intel_crtc);
4839         else
4840                 i9xx_update_pll(intel_crtc,
4841                                 has_reduced_clock ? &reduced_clock : NULL,
4842                                 num_connectors);
4843
4844         /* Set up the display plane register */
4845         dspcntr = DISPPLANE_GAMMA_ENABLE;
4846
4847         if (!IS_VALLEYVIEW(dev)) {
4848                 if (pipe == 0)
4849                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4850                 else
4851                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4852         }
4853
4854         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4855
4856         /* pipesrc and dspsize control the size that is scaled from,
4857          * which should always be the user's requested size.
4858          */
4859         I915_WRITE(DSPSIZE(plane),
4860                    ((mode->vdisplay - 1) << 16) |
4861                    (mode->hdisplay - 1));
4862         I915_WRITE(DSPPOS(plane), 0);
4863
4864         i9xx_set_pipeconf(intel_crtc);
4865
4866         I915_WRITE(DSPCNTR(plane), dspcntr);
4867         POSTING_READ(DSPCNTR(plane));
4868
4869         ret = intel_pipe_set_base(crtc, x, y, fb);
4870
4871         intel_update_watermarks(dev);
4872
4873         return ret;
4874 }
4875
4876 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4877                                  struct intel_crtc_config *pipe_config)
4878 {
4879         struct drm_device *dev = crtc->base.dev;
4880         struct drm_i915_private *dev_priv = dev->dev_private;
4881         uint32_t tmp;
4882
4883         tmp = I915_READ(PFIT_CONTROL);
4884
4885         if (INTEL_INFO(dev)->gen < 4) {
4886                 if (crtc->pipe != PIPE_B)
4887                         return;
4888
4889                 /* gen2/3 store dither state in pfit control, needs to match */
4890                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4891         } else {
4892                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4893                         return;
4894         }
4895
4896         if (!(tmp & PFIT_ENABLE))
4897                 return;
4898
4899         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4900         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4901         if (INTEL_INFO(dev)->gen < 5)
4902                 pipe_config->gmch_pfit.lvds_border_bits =
4903                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4904 }
4905
4906 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4907                                  struct intel_crtc_config *pipe_config)
4908 {
4909         struct drm_device *dev = crtc->base.dev;
4910         struct drm_i915_private *dev_priv = dev->dev_private;
4911         uint32_t tmp;
4912
4913         pipe_config->cpu_transcoder = crtc->pipe;
4914
4915         tmp = I915_READ(PIPECONF(crtc->pipe));
4916         if (!(tmp & PIPECONF_ENABLE))
4917                 return false;
4918
4919         intel_get_pipe_timings(crtc, pipe_config);
4920
4921         i9xx_get_pfit_config(crtc, pipe_config);
4922
4923         return true;
4924 }
4925
4926 static void ironlake_init_pch_refclk(struct drm_device *dev)
4927 {
4928         struct drm_i915_private *dev_priv = dev->dev_private;
4929         struct drm_mode_config *mode_config = &dev->mode_config;
4930         struct intel_encoder *encoder;
4931         u32 val, final;
4932         bool has_lvds = false;
4933         bool has_cpu_edp = false;
4934         bool has_panel = false;
4935         bool has_ck505 = false;
4936         bool can_ssc = false;
4937
4938         /* We need to take the global config into account */
4939         list_for_each_entry(encoder, &mode_config->encoder_list,
4940                             base.head) {
4941                 switch (encoder->type) {
4942                 case INTEL_OUTPUT_LVDS:
4943                         has_panel = true;
4944                         has_lvds = true;
4945                         break;
4946                 case INTEL_OUTPUT_EDP:
4947                         has_panel = true;
4948                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
4949                                 has_cpu_edp = true;
4950                         break;
4951                 }
4952         }
4953
4954         if (HAS_PCH_IBX(dev)) {
4955                 has_ck505 = dev_priv->vbt.display_clock_mode;
4956                 can_ssc = has_ck505;
4957         } else {
4958                 has_ck505 = false;
4959                 can_ssc = true;
4960         }
4961
4962         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
4963                       has_panel, has_lvds, has_ck505);
4964
4965         /* Ironlake: try to setup display ref clock before DPLL
4966          * enabling. This is only under driver's control after
4967          * PCH B stepping, previous chipset stepping should be
4968          * ignoring this setting.
4969          */
4970         val = I915_READ(PCH_DREF_CONTROL);
4971
4972         /* As we must carefully and slowly disable/enable each source in turn,
4973          * compute the final state we want first and check if we need to
4974          * make any changes at all.
4975          */
4976         final = val;
4977         final &= ~DREF_NONSPREAD_SOURCE_MASK;
4978         if (has_ck505)
4979                 final |= DREF_NONSPREAD_CK505_ENABLE;
4980         else
4981                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4982
4983         final &= ~DREF_SSC_SOURCE_MASK;
4984         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4985         final &= ~DREF_SSC1_ENABLE;
4986
4987         if (has_panel) {
4988                 final |= DREF_SSC_SOURCE_ENABLE;
4989
4990                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4991                         final |= DREF_SSC1_ENABLE;
4992
4993                 if (has_cpu_edp) {
4994                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
4995                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4996                         else
4997                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4998                 } else
4999                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5000         } else {
5001                 final |= DREF_SSC_SOURCE_DISABLE;
5002                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5003         }
5004
5005         if (final == val)
5006                 return;
5007
5008         /* Always enable nonspread source */
5009         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5010
5011         if (has_ck505)
5012                 val |= DREF_NONSPREAD_CK505_ENABLE;
5013         else
5014                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5015
5016         if (has_panel) {
5017                 val &= ~DREF_SSC_SOURCE_MASK;
5018                 val |= DREF_SSC_SOURCE_ENABLE;
5019
5020                 /* SSC must be turned on before enabling the CPU output  */
5021                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5022                         DRM_DEBUG_KMS("Using SSC on panel\n");
5023                         val |= DREF_SSC1_ENABLE;
5024                 } else
5025                         val &= ~DREF_SSC1_ENABLE;
5026
5027                 /* Get SSC going before enabling the outputs */
5028                 I915_WRITE(PCH_DREF_CONTROL, val);
5029                 POSTING_READ(PCH_DREF_CONTROL);
5030                 udelay(200);
5031
5032                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5033
5034                 /* Enable CPU source on CPU attached eDP */
5035                 if (has_cpu_edp) {
5036                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5037                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5038                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5039                         }
5040                         else
5041                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5042                 } else
5043                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5044
5045                 I915_WRITE(PCH_DREF_CONTROL, val);
5046                 POSTING_READ(PCH_DREF_CONTROL);
5047                 udelay(200);
5048         } else {
5049                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5050
5051                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5052
5053                 /* Turn off CPU output */
5054                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5055
5056                 I915_WRITE(PCH_DREF_CONTROL, val);
5057                 POSTING_READ(PCH_DREF_CONTROL);
5058                 udelay(200);
5059
5060                 /* Turn off the SSC source */
5061                 val &= ~DREF_SSC_SOURCE_MASK;
5062                 val |= DREF_SSC_SOURCE_DISABLE;
5063
5064                 /* Turn off SSC1 */
5065                 val &= ~DREF_SSC1_ENABLE;
5066
5067                 I915_WRITE(PCH_DREF_CONTROL, val);
5068                 POSTING_READ(PCH_DREF_CONTROL);
5069                 udelay(200);
5070         }
5071
5072         BUG_ON(val != final);
5073 }
5074
5075 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5076 static void lpt_init_pch_refclk(struct drm_device *dev)
5077 {
5078         struct drm_i915_private *dev_priv = dev->dev_private;
5079         struct drm_mode_config *mode_config = &dev->mode_config;
5080         struct intel_encoder *encoder;
5081         bool has_vga = false;
5082         bool is_sdv = false;
5083         u32 tmp;
5084
5085         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5086                 switch (encoder->type) {
5087                 case INTEL_OUTPUT_ANALOG:
5088                         has_vga = true;
5089                         break;
5090                 }
5091         }
5092
5093         if (!has_vga)
5094                 return;
5095
5096         mutex_lock(&dev_priv->dpio_lock);
5097
5098         /* XXX: Rip out SDV support once Haswell ships for real. */
5099         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5100                 is_sdv = true;
5101
5102         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5103         tmp &= ~SBI_SSCCTL_DISABLE;
5104         tmp |= SBI_SSCCTL_PATHALT;
5105         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5106
5107         udelay(24);
5108
5109         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5110         tmp &= ~SBI_SSCCTL_PATHALT;
5111         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5112
5113         if (!is_sdv) {
5114                 tmp = I915_READ(SOUTH_CHICKEN2);
5115                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5116                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5117
5118                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5119                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5120                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5121
5122                 tmp = I915_READ(SOUTH_CHICKEN2);
5123                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5124                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5125
5126                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5127                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5128                                        100))
5129                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5130         }
5131
5132         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5133         tmp &= ~(0xFF << 24);
5134         tmp |= (0x12 << 24);
5135         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5136
5137         if (is_sdv) {
5138                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5139                 tmp |= 0x7FFF;
5140                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5141         }
5142
5143         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5144         tmp |= (1 << 11);
5145         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5146
5147         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5148         tmp |= (1 << 11);
5149         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5150
5151         if (is_sdv) {
5152                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5153                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5154                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5155
5156                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5157                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5158                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5159
5160                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5161                 tmp |= (0x3F << 8);
5162                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5163
5164                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5165                 tmp |= (0x3F << 8);
5166                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5167         }
5168
5169         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5170         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5171         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5172
5173         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5174         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5175         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5176
5177         if (!is_sdv) {
5178                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5179                 tmp &= ~(7 << 13);
5180                 tmp |= (5 << 13);
5181                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5182
5183                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5184                 tmp &= ~(7 << 13);
5185                 tmp |= (5 << 13);
5186                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5187         }
5188
5189         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5190         tmp &= ~0xFF;
5191         tmp |= 0x1C;
5192         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5193
5194         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5195         tmp &= ~0xFF;
5196         tmp |= 0x1C;
5197         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5198
5199         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5200         tmp &= ~(0xFF << 16);
5201         tmp |= (0x1C << 16);
5202         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5203
5204         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5205         tmp &= ~(0xFF << 16);
5206         tmp |= (0x1C << 16);
5207         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5208
5209         if (!is_sdv) {
5210                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5211                 tmp |= (1 << 27);
5212                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5213
5214                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5215                 tmp |= (1 << 27);
5216                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5217
5218                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5219                 tmp &= ~(0xF << 28);
5220                 tmp |= (4 << 28);
5221                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5222
5223                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5224                 tmp &= ~(0xF << 28);
5225                 tmp |= (4 << 28);
5226                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5227         }
5228
5229         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5230         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5231         tmp |= SBI_DBUFF0_ENABLE;
5232         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5233
5234         mutex_unlock(&dev_priv->dpio_lock);
5235 }
5236
5237 /*
5238  * Initialize reference clocks when the driver loads
5239  */
5240 void intel_init_pch_refclk(struct drm_device *dev)
5241 {
5242         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5243                 ironlake_init_pch_refclk(dev);
5244         else if (HAS_PCH_LPT(dev))
5245                 lpt_init_pch_refclk(dev);
5246 }
5247
5248 static int ironlake_get_refclk(struct drm_crtc *crtc)
5249 {
5250         struct drm_device *dev = crtc->dev;
5251         struct drm_i915_private *dev_priv = dev->dev_private;
5252         struct intel_encoder *encoder;
5253         int num_connectors = 0;
5254         bool is_lvds = false;
5255
5256         for_each_encoder_on_crtc(dev, crtc, encoder) {
5257                 switch (encoder->type) {
5258                 case INTEL_OUTPUT_LVDS:
5259                         is_lvds = true;
5260                         break;
5261                 }
5262                 num_connectors++;
5263         }
5264
5265         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5266                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5267                               dev_priv->vbt.lvds_ssc_freq);
5268                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5269         }
5270
5271         return 120000;
5272 }
5273
5274 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5275 {
5276         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5277         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5278         int pipe = intel_crtc->pipe;
5279         uint32_t val;
5280
5281         val = I915_READ(PIPECONF(pipe));
5282
5283         val &= ~PIPECONF_BPC_MASK;
5284         switch (intel_crtc->config.pipe_bpp) {
5285         case 18:
5286                 val |= PIPECONF_6BPC;
5287                 break;
5288         case 24:
5289                 val |= PIPECONF_8BPC;
5290                 break;
5291         case 30:
5292                 val |= PIPECONF_10BPC;
5293                 break;
5294         case 36:
5295                 val |= PIPECONF_12BPC;
5296                 break;
5297         default:
5298                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5299                 BUG();
5300         }
5301
5302         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5303         if (intel_crtc->config.dither)
5304                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5305
5306         val &= ~PIPECONF_INTERLACE_MASK;
5307         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5308                 val |= PIPECONF_INTERLACED_ILK;
5309         else
5310                 val |= PIPECONF_PROGRESSIVE;
5311
5312         if (intel_crtc->config.limited_color_range)
5313                 val |= PIPECONF_COLOR_RANGE_SELECT;
5314         else
5315                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5316
5317         I915_WRITE(PIPECONF(pipe), val);
5318         POSTING_READ(PIPECONF(pipe));
5319 }
5320
5321 /*
5322  * Set up the pipe CSC unit.
5323  *
5324  * Currently only full range RGB to limited range RGB conversion
5325  * is supported, but eventually this should handle various
5326  * RGB<->YCbCr scenarios as well.
5327  */
5328 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5329 {
5330         struct drm_device *dev = crtc->dev;
5331         struct drm_i915_private *dev_priv = dev->dev_private;
5332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5333         int pipe = intel_crtc->pipe;
5334         uint16_t coeff = 0x7800; /* 1.0 */
5335
5336         /*
5337          * TODO: Check what kind of values actually come out of the pipe
5338          * with these coeff/postoff values and adjust to get the best
5339          * accuracy. Perhaps we even need to take the bpc value into
5340          * consideration.
5341          */
5342
5343         if (intel_crtc->config.limited_color_range)
5344                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5345
5346         /*
5347          * GY/GU and RY/RU should be the other way around according
5348          * to BSpec, but reality doesn't agree. Just set them up in
5349          * a way that results in the correct picture.
5350          */
5351         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5352         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5353
5354         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5355         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5356
5357         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5358         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5359
5360         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5361         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5362         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5363
5364         if (INTEL_INFO(dev)->gen > 6) {
5365                 uint16_t postoff = 0;
5366
5367                 if (intel_crtc->config.limited_color_range)
5368                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5369
5370                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5371                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5372                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5373
5374                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5375         } else {
5376                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5377
5378                 if (intel_crtc->config.limited_color_range)
5379                         mode |= CSC_BLACK_SCREEN_OFFSET;
5380
5381                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5382         }
5383 }
5384
5385 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5386 {
5387         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5389         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5390         uint32_t val;
5391
5392         val = I915_READ(PIPECONF(cpu_transcoder));
5393
5394         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5395         if (intel_crtc->config.dither)
5396                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5397
5398         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5399         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5400                 val |= PIPECONF_INTERLACED_ILK;
5401         else
5402                 val |= PIPECONF_PROGRESSIVE;
5403
5404         I915_WRITE(PIPECONF(cpu_transcoder), val);
5405         POSTING_READ(PIPECONF(cpu_transcoder));
5406 }
5407
5408 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5409                                     struct drm_display_mode *adjusted_mode,
5410                                     intel_clock_t *clock,
5411                                     bool *has_reduced_clock,
5412                                     intel_clock_t *reduced_clock)
5413 {
5414         struct drm_device *dev = crtc->dev;
5415         struct drm_i915_private *dev_priv = dev->dev_private;
5416         struct intel_encoder *intel_encoder;
5417         int refclk;
5418         const intel_limit_t *limit;
5419         bool ret, is_lvds = false;
5420
5421         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5422                 switch (intel_encoder->type) {
5423                 case INTEL_OUTPUT_LVDS:
5424                         is_lvds = true;
5425                         break;
5426                 }
5427         }
5428
5429         refclk = ironlake_get_refclk(crtc);
5430
5431         /*
5432          * Returns a set of divisors for the desired target clock with the given
5433          * refclk, or FALSE.  The returned values represent the clock equation:
5434          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5435          */
5436         limit = intel_limit(crtc, refclk);
5437         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5438                               clock);
5439         if (!ret)
5440                 return false;
5441
5442         if (is_lvds && dev_priv->lvds_downclock_avail) {
5443                 /*
5444                  * Ensure we match the reduced clock's P to the target clock.
5445                  * If the clocks don't match, we can't switch the display clock
5446                  * by using the FP0/FP1. In such case we will disable the LVDS
5447                  * downclock feature.
5448                 */
5449                 *has_reduced_clock = limit->find_pll(limit, crtc,
5450                                                      dev_priv->lvds_downclock,
5451                                                      refclk,
5452                                                      clock,
5453                                                      reduced_clock);
5454         }
5455
5456         return true;
5457 }
5458
5459 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5460 {
5461         struct drm_i915_private *dev_priv = dev->dev_private;
5462         uint32_t temp;
5463
5464         temp = I915_READ(SOUTH_CHICKEN1);
5465         if (temp & FDI_BC_BIFURCATION_SELECT)
5466                 return;
5467
5468         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5469         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5470
5471         temp |= FDI_BC_BIFURCATION_SELECT;
5472         DRM_DEBUG_KMS("enabling fdi C rx\n");
5473         I915_WRITE(SOUTH_CHICKEN1, temp);
5474         POSTING_READ(SOUTH_CHICKEN1);
5475 }
5476
5477 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5478 {
5479         struct drm_device *dev = intel_crtc->base.dev;
5480         struct drm_i915_private *dev_priv = dev->dev_private;
5481
5482         switch (intel_crtc->pipe) {
5483         case PIPE_A:
5484                 break;
5485         case PIPE_B:
5486                 if (intel_crtc->config.fdi_lanes > 2)
5487                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5488                 else
5489                         cpt_enable_fdi_bc_bifurcation(dev);
5490
5491                 break;
5492         case PIPE_C:
5493                 cpt_enable_fdi_bc_bifurcation(dev);
5494
5495                 break;
5496         default:
5497                 BUG();
5498         }
5499 }
5500
5501 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5502 {
5503         /*
5504          * Account for spread spectrum to avoid
5505          * oversubscribing the link. Max center spread
5506          * is 2.5%; use 5% for safety's sake.
5507          */
5508         u32 bps = target_clock * bpp * 21 / 20;
5509         return bps / (link_bw * 8) + 1;
5510 }
5511
5512 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5513 {
5514         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5515 }
5516
5517 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5518                                       u32 *fp,
5519                                       intel_clock_t *reduced_clock, u32 *fp2)
5520 {
5521         struct drm_crtc *crtc = &intel_crtc->base;
5522         struct drm_device *dev = crtc->dev;
5523         struct drm_i915_private *dev_priv = dev->dev_private;
5524         struct intel_encoder *intel_encoder;
5525         uint32_t dpll;
5526         int factor, num_connectors = 0;
5527         bool is_lvds = false, is_sdvo = false;
5528
5529         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5530                 switch (intel_encoder->type) {
5531                 case INTEL_OUTPUT_LVDS:
5532                         is_lvds = true;
5533                         break;
5534                 case INTEL_OUTPUT_SDVO:
5535                 case INTEL_OUTPUT_HDMI:
5536                         is_sdvo = true;
5537                         break;
5538                 }
5539
5540                 num_connectors++;
5541         }
5542
5543         /* Enable autotuning of the PLL clock (if permissible) */
5544         factor = 21;
5545         if (is_lvds) {
5546                 if ((intel_panel_use_ssc(dev_priv) &&
5547                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5548                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5549                         factor = 25;
5550         } else if (intel_crtc->config.sdvo_tv_clock)
5551                 factor = 20;
5552
5553         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5554                 *fp |= FP_CB_TUNE;
5555
5556         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5557                 *fp2 |= FP_CB_TUNE;
5558
5559         dpll = 0;
5560
5561         if (is_lvds)
5562                 dpll |= DPLLB_MODE_LVDS;
5563         else
5564                 dpll |= DPLLB_MODE_DAC_SERIAL;
5565
5566         if (intel_crtc->config.pixel_multiplier > 1) {
5567                 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5568                         << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5569         }
5570
5571         if (is_sdvo)
5572                 dpll |= DPLL_DVO_HIGH_SPEED;
5573         if (intel_crtc->config.has_dp_encoder)
5574                 dpll |= DPLL_DVO_HIGH_SPEED;
5575
5576         /* compute bitmask from p1 value */
5577         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5578         /* also FPA1 */
5579         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5580
5581         switch (intel_crtc->config.dpll.p2) {
5582         case 5:
5583                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5584                 break;
5585         case 7:
5586                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5587                 break;
5588         case 10:
5589                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5590                 break;
5591         case 14:
5592                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5593                 break;
5594         }
5595
5596         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5597                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5598         else
5599                 dpll |= PLL_REF_INPUT_DREFCLK;
5600
5601         return dpll;
5602 }
5603
5604 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5605                                   int x, int y,
5606                                   struct drm_framebuffer *fb)
5607 {
5608         struct drm_device *dev = crtc->dev;
5609         struct drm_i915_private *dev_priv = dev->dev_private;
5610         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5611         struct drm_display_mode *adjusted_mode =
5612                 &intel_crtc->config.adjusted_mode;
5613         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5614         int pipe = intel_crtc->pipe;
5615         int plane = intel_crtc->plane;
5616         int num_connectors = 0;
5617         intel_clock_t clock, reduced_clock;
5618         u32 dpll = 0, fp = 0, fp2 = 0;
5619         bool ok, has_reduced_clock = false;
5620         bool is_lvds = false;
5621         struct intel_encoder *encoder;
5622         int ret;
5623
5624         for_each_encoder_on_crtc(dev, crtc, encoder) {
5625                 switch (encoder->type) {
5626                 case INTEL_OUTPUT_LVDS:
5627                         is_lvds = true;
5628                         break;
5629                 }
5630
5631                 num_connectors++;
5632         }
5633
5634         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5635              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5636
5637         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5638                                      &has_reduced_clock, &reduced_clock);
5639         if (!ok) {
5640                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5641                 return -EINVAL;
5642         }
5643         /* Compat-code for transition, will disappear. */
5644         if (!intel_crtc->config.clock_set) {
5645                 intel_crtc->config.dpll.n = clock.n;
5646                 intel_crtc->config.dpll.m1 = clock.m1;
5647                 intel_crtc->config.dpll.m2 = clock.m2;
5648                 intel_crtc->config.dpll.p1 = clock.p1;
5649                 intel_crtc->config.dpll.p2 = clock.p2;
5650         }
5651
5652         /* Ensure that the cursor is valid for the new mode before changing... */
5653         intel_crtc_update_cursor(crtc, true);
5654
5655         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5656         if (intel_crtc->config.has_pch_encoder) {
5657                 struct intel_pch_pll *pll;
5658
5659                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5660                 if (has_reduced_clock)
5661                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5662
5663                 dpll = ironlake_compute_dpll(intel_crtc,
5664                                              &fp, &reduced_clock,
5665                                              has_reduced_clock ? &fp2 : NULL);
5666
5667                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5668                 if (pll == NULL) {
5669                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5670                                          pipe_name(pipe));
5671                         return -EINVAL;
5672                 }
5673         } else
5674                 intel_put_pch_pll(intel_crtc);
5675
5676         if (intel_crtc->config.has_dp_encoder)
5677                 intel_dp_set_m_n(intel_crtc);
5678
5679         for_each_encoder_on_crtc(dev, crtc, encoder)
5680                 if (encoder->pre_pll_enable)
5681                         encoder->pre_pll_enable(encoder);
5682
5683         if (intel_crtc->pch_pll) {
5684                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5685
5686                 /* Wait for the clocks to stabilize. */
5687                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5688                 udelay(150);
5689
5690                 /* The pixel multiplier can only be updated once the
5691                  * DPLL is enabled and the clocks are stable.
5692                  *
5693                  * So write it again.
5694                  */
5695                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5696         }
5697
5698         intel_crtc->lowfreq_avail = false;
5699         if (intel_crtc->pch_pll) {
5700                 if (is_lvds && has_reduced_clock && i915_powersave) {
5701                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5702                         intel_crtc->lowfreq_avail = true;
5703                 } else {
5704                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5705                 }
5706         }
5707
5708         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5709
5710         if (intel_crtc->config.has_pch_encoder) {
5711                 intel_cpu_transcoder_set_m_n(intel_crtc,
5712                                              &intel_crtc->config.fdi_m_n);
5713         }
5714
5715         if (IS_IVYBRIDGE(dev))
5716                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5717
5718         ironlake_set_pipeconf(crtc);
5719
5720         /* Set up the display plane register */
5721         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5722         POSTING_READ(DSPCNTR(plane));
5723
5724         ret = intel_pipe_set_base(crtc, x, y, fb);
5725
5726         intel_update_watermarks(dev);
5727
5728         return ret;
5729 }
5730
5731 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5732                                         struct intel_crtc_config *pipe_config)
5733 {
5734         struct drm_device *dev = crtc->base.dev;
5735         struct drm_i915_private *dev_priv = dev->dev_private;
5736         enum transcoder transcoder = pipe_config->cpu_transcoder;
5737
5738         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5739         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5740         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5741                                         & ~TU_SIZE_MASK;
5742         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5743         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5744                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5745 }
5746
5747 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5748                                      struct intel_crtc_config *pipe_config)
5749 {
5750         struct drm_device *dev = crtc->base.dev;
5751         struct drm_i915_private *dev_priv = dev->dev_private;
5752         uint32_t tmp;
5753
5754         tmp = I915_READ(PF_CTL(crtc->pipe));
5755
5756         if (tmp & PF_ENABLE) {
5757                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5758                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5759         }
5760 }
5761
5762 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5763                                      struct intel_crtc_config *pipe_config)
5764 {
5765         struct drm_device *dev = crtc->base.dev;
5766         struct drm_i915_private *dev_priv = dev->dev_private;
5767         uint32_t tmp;
5768
5769         pipe_config->cpu_transcoder = crtc->pipe;
5770
5771         tmp = I915_READ(PIPECONF(crtc->pipe));
5772         if (!(tmp & PIPECONF_ENABLE))
5773                 return false;
5774
5775         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5776                 pipe_config->has_pch_encoder = true;
5777
5778                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5779                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5780                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5781
5782                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5783         }
5784
5785         intel_get_pipe_timings(crtc, pipe_config);
5786
5787         ironlake_get_pfit_config(crtc, pipe_config);
5788
5789         return true;
5790 }
5791
5792 static void haswell_modeset_global_resources(struct drm_device *dev)
5793 {
5794         bool enable = false;
5795         struct intel_crtc *crtc;
5796         struct intel_encoder *encoder;
5797
5798         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5799                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5800                         enable = true;
5801                 /* XXX: Should check for edp transcoder here, but thanks to init
5802                  * sequence that's not yet available. Just in case desktop eDP
5803                  * on PORT D is possible on haswell, too. */
5804                 /* Even the eDP panel fitter is outside the always-on well. */
5805                 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5806                         enable = true;
5807         }
5808
5809         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5810                             base.head) {
5811                 if (encoder->type != INTEL_OUTPUT_EDP &&
5812                     encoder->connectors_active)
5813                         enable = true;
5814         }
5815
5816         intel_set_power_well(dev, enable);
5817 }
5818
5819 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5820                                  int x, int y,
5821                                  struct drm_framebuffer *fb)
5822 {
5823         struct drm_device *dev = crtc->dev;
5824         struct drm_i915_private *dev_priv = dev->dev_private;
5825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5826         struct drm_display_mode *adjusted_mode =
5827                 &intel_crtc->config.adjusted_mode;
5828         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5829         int pipe = intel_crtc->pipe;
5830         int plane = intel_crtc->plane;
5831         int num_connectors = 0;
5832         bool is_cpu_edp = false;
5833         struct intel_encoder *encoder;
5834         int ret;
5835
5836         for_each_encoder_on_crtc(dev, crtc, encoder) {
5837                 switch (encoder->type) {
5838                 case INTEL_OUTPUT_EDP:
5839                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5840                                 is_cpu_edp = true;
5841                         break;
5842                 }
5843
5844                 num_connectors++;
5845         }
5846
5847         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5848              num_connectors, pipe_name(pipe));
5849
5850         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5851                 return -EINVAL;
5852
5853         /* Ensure that the cursor is valid for the new mode before changing... */
5854         intel_crtc_update_cursor(crtc, true);
5855
5856         if (intel_crtc->config.has_dp_encoder)
5857                 intel_dp_set_m_n(intel_crtc);
5858
5859         intel_crtc->lowfreq_avail = false;
5860
5861         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5862
5863         if (intel_crtc->config.has_pch_encoder) {
5864                 intel_cpu_transcoder_set_m_n(intel_crtc,
5865                                              &intel_crtc->config.fdi_m_n);
5866         }
5867
5868         haswell_set_pipeconf(crtc);
5869
5870         intel_set_pipe_csc(crtc);
5871
5872         /* Set up the display plane register */
5873         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5874         POSTING_READ(DSPCNTR(plane));
5875
5876         ret = intel_pipe_set_base(crtc, x, y, fb);
5877
5878         intel_update_watermarks(dev);
5879
5880         return ret;
5881 }
5882
5883 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5884                                     struct intel_crtc_config *pipe_config)
5885 {
5886         struct drm_device *dev = crtc->base.dev;
5887         struct drm_i915_private *dev_priv = dev->dev_private;
5888         enum intel_display_power_domain pfit_domain;
5889         uint32_t tmp;
5890
5891         pipe_config->cpu_transcoder = crtc->pipe;
5892         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5893         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5894                 enum pipe trans_edp_pipe;
5895                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5896                 default:
5897                         WARN(1, "unknown pipe linked to edp transcoder\n");
5898                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5899                 case TRANS_DDI_EDP_INPUT_A_ON:
5900                         trans_edp_pipe = PIPE_A;
5901                         break;
5902                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5903                         trans_edp_pipe = PIPE_B;
5904                         break;
5905                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5906                         trans_edp_pipe = PIPE_C;
5907                         break;
5908                 }
5909
5910                 if (trans_edp_pipe == crtc->pipe)
5911                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5912         }
5913
5914         if (!intel_display_power_enabled(dev,
5915                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5916                 return false;
5917
5918         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5919         if (!(tmp & PIPECONF_ENABLE))
5920                 return false;
5921
5922         /*
5923          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5924          * DDI E. So just check whether this pipe is wired to DDI E and whether
5925          * the PCH transcoder is on.
5926          */
5927         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5928         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5929             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5930                 pipe_config->has_pch_encoder = true;
5931
5932                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5933                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5934                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5935
5936                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5937         }
5938
5939         intel_get_pipe_timings(crtc, pipe_config);
5940
5941         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5942         if (intel_display_power_enabled(dev, pfit_domain))
5943                 ironlake_get_pfit_config(crtc, pipe_config);
5944
5945         return true;
5946 }
5947
5948 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5949                                int x, int y,
5950                                struct drm_framebuffer *fb)
5951 {
5952         struct drm_device *dev = crtc->dev;
5953         struct drm_i915_private *dev_priv = dev->dev_private;
5954         struct drm_encoder_helper_funcs *encoder_funcs;
5955         struct intel_encoder *encoder;
5956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957         struct drm_display_mode *adjusted_mode =
5958                 &intel_crtc->config.adjusted_mode;
5959         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5960         int pipe = intel_crtc->pipe;
5961         int ret;
5962
5963         drm_vblank_pre_modeset(dev, pipe);
5964
5965         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5966
5967         drm_vblank_post_modeset(dev, pipe);
5968
5969         if (ret != 0)
5970                 return ret;
5971
5972         for_each_encoder_on_crtc(dev, crtc, encoder) {
5973                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5974                         encoder->base.base.id,
5975                         drm_get_encoder_name(&encoder->base),
5976                         mode->base.id, mode->name);
5977                 if (encoder->mode_set) {
5978                         encoder->mode_set(encoder);
5979                 } else {
5980                         encoder_funcs = encoder->base.helper_private;
5981                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5982                 }
5983         }
5984
5985         return 0;
5986 }
5987
5988 static bool intel_eld_uptodate(struct drm_connector *connector,
5989                                int reg_eldv, uint32_t bits_eldv,
5990                                int reg_elda, uint32_t bits_elda,
5991                                int reg_edid)
5992 {
5993         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5994         uint8_t *eld = connector->eld;
5995         uint32_t i;
5996
5997         i = I915_READ(reg_eldv);
5998         i &= bits_eldv;
5999
6000         if (!eld[0])
6001                 return !i;
6002
6003         if (!i)
6004                 return false;
6005
6006         i = I915_READ(reg_elda);
6007         i &= ~bits_elda;
6008         I915_WRITE(reg_elda, i);
6009
6010         for (i = 0; i < eld[2]; i++)
6011                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6012                         return false;
6013
6014         return true;
6015 }
6016
6017 static void g4x_write_eld(struct drm_connector *connector,
6018                           struct drm_crtc *crtc)
6019 {
6020         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6021         uint8_t *eld = connector->eld;
6022         uint32_t eldv;
6023         uint32_t len;
6024         uint32_t i;
6025
6026         i = I915_READ(G4X_AUD_VID_DID);
6027
6028         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6029                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6030         else
6031                 eldv = G4X_ELDV_DEVCTG;
6032
6033         if (intel_eld_uptodate(connector,
6034                                G4X_AUD_CNTL_ST, eldv,
6035                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6036                                G4X_HDMIW_HDMIEDID))
6037                 return;
6038
6039         i = I915_READ(G4X_AUD_CNTL_ST);
6040         i &= ~(eldv | G4X_ELD_ADDR);
6041         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6042         I915_WRITE(G4X_AUD_CNTL_ST, i);
6043
6044         if (!eld[0])
6045                 return;
6046
6047         len = min_t(uint8_t, eld[2], len);
6048         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6049         for (i = 0; i < len; i++)
6050                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6051
6052         i = I915_READ(G4X_AUD_CNTL_ST);
6053         i |= eldv;
6054         I915_WRITE(G4X_AUD_CNTL_ST, i);
6055 }
6056
6057 static void haswell_write_eld(struct drm_connector *connector,
6058                                      struct drm_crtc *crtc)
6059 {
6060         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6061         uint8_t *eld = connector->eld;
6062         struct drm_device *dev = crtc->dev;
6063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6064         uint32_t eldv;
6065         uint32_t i;
6066         int len;
6067         int pipe = to_intel_crtc(crtc)->pipe;
6068         int tmp;
6069
6070         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6071         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6072         int aud_config = HSW_AUD_CFG(pipe);
6073         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6074
6075
6076         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6077
6078         /* Audio output enable */
6079         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6080         tmp = I915_READ(aud_cntrl_st2);
6081         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6082         I915_WRITE(aud_cntrl_st2, tmp);
6083
6084         /* Wait for 1 vertical blank */
6085         intel_wait_for_vblank(dev, pipe);
6086
6087         /* Set ELD valid state */
6088         tmp = I915_READ(aud_cntrl_st2);
6089         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6090         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6091         I915_WRITE(aud_cntrl_st2, tmp);
6092         tmp = I915_READ(aud_cntrl_st2);
6093         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6094
6095         /* Enable HDMI mode */
6096         tmp = I915_READ(aud_config);
6097         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6098         /* clear N_programing_enable and N_value_index */
6099         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6100         I915_WRITE(aud_config, tmp);
6101
6102         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6103
6104         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6105         intel_crtc->eld_vld = true;
6106
6107         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6108                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6109                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6110                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6111         } else
6112                 I915_WRITE(aud_config, 0);
6113
6114         if (intel_eld_uptodate(connector,
6115                                aud_cntrl_st2, eldv,
6116                                aud_cntl_st, IBX_ELD_ADDRESS,
6117                                hdmiw_hdmiedid))
6118                 return;
6119
6120         i = I915_READ(aud_cntrl_st2);
6121         i &= ~eldv;
6122         I915_WRITE(aud_cntrl_st2, i);
6123
6124         if (!eld[0])
6125                 return;
6126
6127         i = I915_READ(aud_cntl_st);
6128         i &= ~IBX_ELD_ADDRESS;
6129         I915_WRITE(aud_cntl_st, i);
6130         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6131         DRM_DEBUG_DRIVER("port num:%d\n", i);
6132
6133         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6134         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6135         for (i = 0; i < len; i++)
6136                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6137
6138         i = I915_READ(aud_cntrl_st2);
6139         i |= eldv;
6140         I915_WRITE(aud_cntrl_st2, i);
6141
6142 }
6143
6144 static void ironlake_write_eld(struct drm_connector *connector,
6145                                      struct drm_crtc *crtc)
6146 {
6147         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6148         uint8_t *eld = connector->eld;
6149         uint32_t eldv;
6150         uint32_t i;
6151         int len;
6152         int hdmiw_hdmiedid;
6153         int aud_config;
6154         int aud_cntl_st;
6155         int aud_cntrl_st2;
6156         int pipe = to_intel_crtc(crtc)->pipe;
6157
6158         if (HAS_PCH_IBX(connector->dev)) {
6159                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6160                 aud_config = IBX_AUD_CFG(pipe);
6161                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6162                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6163         } else {
6164                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6165                 aud_config = CPT_AUD_CFG(pipe);
6166                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6167                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6168         }
6169
6170         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6171
6172         i = I915_READ(aud_cntl_st);
6173         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6174         if (!i) {
6175                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6176                 /* operate blindly on all ports */
6177                 eldv = IBX_ELD_VALIDB;
6178                 eldv |= IBX_ELD_VALIDB << 4;
6179                 eldv |= IBX_ELD_VALIDB << 8;
6180         } else {
6181                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6182                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6183         }
6184
6185         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6186                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6187                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6188                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6189         } else
6190                 I915_WRITE(aud_config, 0);
6191
6192         if (intel_eld_uptodate(connector,
6193                                aud_cntrl_st2, eldv,
6194                                aud_cntl_st, IBX_ELD_ADDRESS,
6195                                hdmiw_hdmiedid))
6196                 return;
6197
6198         i = I915_READ(aud_cntrl_st2);
6199         i &= ~eldv;
6200         I915_WRITE(aud_cntrl_st2, i);
6201
6202         if (!eld[0])
6203                 return;
6204
6205         i = I915_READ(aud_cntl_st);
6206         i &= ~IBX_ELD_ADDRESS;
6207         I915_WRITE(aud_cntl_st, i);
6208
6209         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6210         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6211         for (i = 0; i < len; i++)
6212                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6213
6214         i = I915_READ(aud_cntrl_st2);
6215         i |= eldv;
6216         I915_WRITE(aud_cntrl_st2, i);
6217 }
6218
6219 void intel_write_eld(struct drm_encoder *encoder,
6220                      struct drm_display_mode *mode)
6221 {
6222         struct drm_crtc *crtc = encoder->crtc;
6223         struct drm_connector *connector;
6224         struct drm_device *dev = encoder->dev;
6225         struct drm_i915_private *dev_priv = dev->dev_private;
6226
6227         connector = drm_select_eld(encoder, mode);
6228         if (!connector)
6229                 return;
6230
6231         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6232                          connector->base.id,
6233                          drm_get_connector_name(connector),
6234                          connector->encoder->base.id,
6235                          drm_get_encoder_name(connector->encoder));
6236
6237         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6238
6239         if (dev_priv->display.write_eld)
6240                 dev_priv->display.write_eld(connector, crtc);
6241 }
6242
6243 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6244 void intel_crtc_load_lut(struct drm_crtc *crtc)
6245 {
6246         struct drm_device *dev = crtc->dev;
6247         struct drm_i915_private *dev_priv = dev->dev_private;
6248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6249         int palreg = PALETTE(intel_crtc->pipe);
6250         int i;
6251
6252         /* The clocks have to be on to load the palette. */
6253         if (!crtc->enabled || !intel_crtc->active)
6254                 return;
6255
6256         /* use legacy palette for Ironlake */
6257         if (HAS_PCH_SPLIT(dev))
6258                 palreg = LGC_PALETTE(intel_crtc->pipe);
6259
6260         for (i = 0; i < 256; i++) {
6261                 I915_WRITE(palreg + 4 * i,
6262                            (intel_crtc->lut_r[i] << 16) |
6263                            (intel_crtc->lut_g[i] << 8) |
6264                            intel_crtc->lut_b[i]);
6265         }
6266 }
6267
6268 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6269 {
6270         struct drm_device *dev = crtc->dev;
6271         struct drm_i915_private *dev_priv = dev->dev_private;
6272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6273         bool visible = base != 0;
6274         u32 cntl;
6275
6276         if (intel_crtc->cursor_visible == visible)
6277                 return;
6278
6279         cntl = I915_READ(_CURACNTR);
6280         if (visible) {
6281                 /* On these chipsets we can only modify the base whilst
6282                  * the cursor is disabled.
6283                  */
6284                 I915_WRITE(_CURABASE, base);
6285
6286                 cntl &= ~(CURSOR_FORMAT_MASK);
6287                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6288                 cntl |= CURSOR_ENABLE |
6289                         CURSOR_GAMMA_ENABLE |
6290                         CURSOR_FORMAT_ARGB;
6291         } else
6292                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6293         I915_WRITE(_CURACNTR, cntl);
6294
6295         intel_crtc->cursor_visible = visible;
6296 }
6297
6298 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6299 {
6300         struct drm_device *dev = crtc->dev;
6301         struct drm_i915_private *dev_priv = dev->dev_private;
6302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6303         int pipe = intel_crtc->pipe;
6304         bool visible = base != 0;
6305
6306         if (intel_crtc->cursor_visible != visible) {
6307                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6308                 if (base) {
6309                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6310                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6311                         cntl |= pipe << 28; /* Connect to correct pipe */
6312                 } else {
6313                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6314                         cntl |= CURSOR_MODE_DISABLE;
6315                 }
6316                 I915_WRITE(CURCNTR(pipe), cntl);
6317
6318                 intel_crtc->cursor_visible = visible;
6319         }
6320         /* and commit changes on next vblank */
6321         I915_WRITE(CURBASE(pipe), base);
6322 }
6323
6324 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6325 {
6326         struct drm_device *dev = crtc->dev;
6327         struct drm_i915_private *dev_priv = dev->dev_private;
6328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6329         int pipe = intel_crtc->pipe;
6330         bool visible = base != 0;
6331
6332         if (intel_crtc->cursor_visible != visible) {
6333                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6334                 if (base) {
6335                         cntl &= ~CURSOR_MODE;
6336                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6337                 } else {
6338                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6339                         cntl |= CURSOR_MODE_DISABLE;
6340                 }
6341                 if (IS_HASWELL(dev))
6342                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6343                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6344
6345                 intel_crtc->cursor_visible = visible;
6346         }
6347         /* and commit changes on next vblank */
6348         I915_WRITE(CURBASE_IVB(pipe), base);
6349 }
6350
6351 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6352 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6353                                      bool on)
6354 {
6355         struct drm_device *dev = crtc->dev;
6356         struct drm_i915_private *dev_priv = dev->dev_private;
6357         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358         int pipe = intel_crtc->pipe;
6359         int x = intel_crtc->cursor_x;
6360         int y = intel_crtc->cursor_y;
6361         u32 base, pos;
6362         bool visible;
6363
6364         pos = 0;
6365
6366         if (on && crtc->enabled && crtc->fb) {
6367                 base = intel_crtc->cursor_addr;
6368                 if (x > (int) crtc->fb->width)
6369                         base = 0;
6370
6371                 if (y > (int) crtc->fb->height)
6372                         base = 0;
6373         } else
6374                 base = 0;
6375
6376         if (x < 0) {
6377                 if (x + intel_crtc->cursor_width < 0)
6378                         base = 0;
6379
6380                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6381                 x = -x;
6382         }
6383         pos |= x << CURSOR_X_SHIFT;
6384
6385         if (y < 0) {
6386                 if (y + intel_crtc->cursor_height < 0)
6387                         base = 0;
6388
6389                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6390                 y = -y;
6391         }
6392         pos |= y << CURSOR_Y_SHIFT;
6393
6394         visible = base != 0;
6395         if (!visible && !intel_crtc->cursor_visible)
6396                 return;
6397
6398         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6399                 I915_WRITE(CURPOS_IVB(pipe), pos);
6400                 ivb_update_cursor(crtc, base);
6401         } else {
6402                 I915_WRITE(CURPOS(pipe), pos);
6403                 if (IS_845G(dev) || IS_I865G(dev))
6404                         i845_update_cursor(crtc, base);
6405                 else
6406                         i9xx_update_cursor(crtc, base);
6407         }
6408 }
6409
6410 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6411                                  struct drm_file *file,
6412                                  uint32_t handle,
6413                                  uint32_t width, uint32_t height)
6414 {
6415         struct drm_device *dev = crtc->dev;
6416         struct drm_i915_private *dev_priv = dev->dev_private;
6417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418         struct drm_i915_gem_object *obj;
6419         uint32_t addr;
6420         int ret;
6421
6422         /* if we want to turn off the cursor ignore width and height */
6423         if (!handle) {
6424                 DRM_DEBUG_KMS("cursor off\n");
6425                 addr = 0;
6426                 obj = NULL;
6427                 mutex_lock(&dev->struct_mutex);
6428                 goto finish;
6429         }
6430
6431         /* Currently we only support 64x64 cursors */
6432         if (width != 64 || height != 64) {
6433                 DRM_ERROR("we currently only support 64x64 cursors\n");
6434                 return -EINVAL;
6435         }
6436
6437         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6438         if (&obj->base == NULL)
6439                 return -ENOENT;
6440
6441         if (obj->base.size < width * height * 4) {
6442                 DRM_ERROR("buffer is to small\n");
6443                 ret = -ENOMEM;
6444                 goto fail;
6445         }
6446
6447         /* we only need to pin inside GTT if cursor is non-phy */
6448         mutex_lock(&dev->struct_mutex);
6449         if (!dev_priv->info->cursor_needs_physical) {
6450                 unsigned alignment;
6451
6452                 if (obj->tiling_mode) {
6453                         DRM_ERROR("cursor cannot be tiled\n");
6454                         ret = -EINVAL;
6455                         goto fail_locked;
6456                 }
6457
6458                 /* Note that the w/a also requires 2 PTE of padding following
6459                  * the bo. We currently fill all unused PTE with the shadow
6460                  * page and so we should always have valid PTE following the
6461                  * cursor preventing the VT-d warning.
6462                  */
6463                 alignment = 0;
6464                 if (need_vtd_wa(dev))
6465                         alignment = 64*1024;
6466
6467                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6468                 if (ret) {
6469                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6470                         goto fail_locked;
6471                 }
6472
6473                 ret = i915_gem_object_put_fence(obj);
6474                 if (ret) {
6475                         DRM_ERROR("failed to release fence for cursor");
6476                         goto fail_unpin;
6477                 }
6478
6479                 addr = obj->gtt_offset;
6480         } else {
6481                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6482                 ret = i915_gem_attach_phys_object(dev, obj,
6483                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6484                                                   align);
6485                 if (ret) {
6486                         DRM_ERROR("failed to attach phys object\n");
6487                         goto fail_locked;
6488                 }
6489                 addr = obj->phys_obj->handle->busaddr;
6490         }
6491
6492         if (IS_GEN2(dev))
6493                 I915_WRITE(CURSIZE, (height << 12) | width);
6494
6495  finish:
6496         if (intel_crtc->cursor_bo) {
6497                 if (dev_priv->info->cursor_needs_physical) {
6498                         if (intel_crtc->cursor_bo != obj)
6499                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6500                 } else
6501                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6502                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6503         }
6504
6505         mutex_unlock(&dev->struct_mutex);
6506
6507         intel_crtc->cursor_addr = addr;
6508         intel_crtc->cursor_bo = obj;
6509         intel_crtc->cursor_width = width;
6510         intel_crtc->cursor_height = height;
6511
6512         intel_crtc_update_cursor(crtc, true);
6513
6514         return 0;
6515 fail_unpin:
6516         i915_gem_object_unpin(obj);
6517 fail_locked:
6518         mutex_unlock(&dev->struct_mutex);
6519 fail:
6520         drm_gem_object_unreference_unlocked(&obj->base);
6521         return ret;
6522 }
6523
6524 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6525 {
6526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6527
6528         intel_crtc->cursor_x = x;
6529         intel_crtc->cursor_y = y;
6530
6531         intel_crtc_update_cursor(crtc, true);
6532
6533         return 0;
6534 }
6535
6536 /** Sets the color ramps on behalf of RandR */
6537 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6538                                  u16 blue, int regno)
6539 {
6540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6541
6542         intel_crtc->lut_r[regno] = red >> 8;
6543         intel_crtc->lut_g[regno] = green >> 8;
6544         intel_crtc->lut_b[regno] = blue >> 8;
6545 }
6546
6547 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6548                              u16 *blue, int regno)
6549 {
6550         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6551
6552         *red = intel_crtc->lut_r[regno] << 8;
6553         *green = intel_crtc->lut_g[regno] << 8;
6554         *blue = intel_crtc->lut_b[regno] << 8;
6555 }
6556
6557 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6558                                  u16 *blue, uint32_t start, uint32_t size)
6559 {
6560         int end = (start + size > 256) ? 256 : start + size, i;
6561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6562
6563         for (i = start; i < end; i++) {
6564                 intel_crtc->lut_r[i] = red[i] >> 8;
6565                 intel_crtc->lut_g[i] = green[i] >> 8;
6566                 intel_crtc->lut_b[i] = blue[i] >> 8;
6567         }
6568
6569         intel_crtc_load_lut(crtc);
6570 }
6571
6572 /* VESA 640x480x72Hz mode to set on the pipe */
6573 static struct drm_display_mode load_detect_mode = {
6574         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6575                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6576 };
6577
6578 static struct drm_framebuffer *
6579 intel_framebuffer_create(struct drm_device *dev,
6580                          struct drm_mode_fb_cmd2 *mode_cmd,
6581                          struct drm_i915_gem_object *obj)
6582 {
6583         struct intel_framebuffer *intel_fb;
6584         int ret;
6585
6586         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6587         if (!intel_fb) {
6588                 drm_gem_object_unreference_unlocked(&obj->base);
6589                 return ERR_PTR(-ENOMEM);
6590         }
6591
6592         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6593         if (ret) {
6594                 drm_gem_object_unreference_unlocked(&obj->base);
6595                 kfree(intel_fb);
6596                 return ERR_PTR(ret);
6597         }
6598
6599         return &intel_fb->base;
6600 }
6601
6602 static u32
6603 intel_framebuffer_pitch_for_width(int width, int bpp)
6604 {
6605         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6606         return ALIGN(pitch, 64);
6607 }
6608
6609 static u32
6610 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6611 {
6612         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6613         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6614 }
6615
6616 static struct drm_framebuffer *
6617 intel_framebuffer_create_for_mode(struct drm_device *dev,
6618                                   struct drm_display_mode *mode,
6619                                   int depth, int bpp)
6620 {
6621         struct drm_i915_gem_object *obj;
6622         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6623
6624         obj = i915_gem_alloc_object(dev,
6625                                     intel_framebuffer_size_for_mode(mode, bpp));
6626         if (obj == NULL)
6627                 return ERR_PTR(-ENOMEM);
6628
6629         mode_cmd.width = mode->hdisplay;
6630         mode_cmd.height = mode->vdisplay;
6631         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6632                                                                 bpp);
6633         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6634
6635         return intel_framebuffer_create(dev, &mode_cmd, obj);
6636 }
6637
6638 static struct drm_framebuffer *
6639 mode_fits_in_fbdev(struct drm_device *dev,
6640                    struct drm_display_mode *mode)
6641 {
6642         struct drm_i915_private *dev_priv = dev->dev_private;
6643         struct drm_i915_gem_object *obj;
6644         struct drm_framebuffer *fb;
6645
6646         if (dev_priv->fbdev == NULL)
6647                 return NULL;
6648
6649         obj = dev_priv->fbdev->ifb.obj;
6650         if (obj == NULL)
6651                 return NULL;
6652
6653         fb = &dev_priv->fbdev->ifb.base;
6654         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6655                                                                fb->bits_per_pixel))
6656                 return NULL;
6657
6658         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6659                 return NULL;
6660
6661         return fb;
6662 }
6663
6664 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6665                                 struct drm_display_mode *mode,
6666                                 struct intel_load_detect_pipe *old)
6667 {
6668         struct intel_crtc *intel_crtc;
6669         struct intel_encoder *intel_encoder =
6670                 intel_attached_encoder(connector);
6671         struct drm_crtc *possible_crtc;
6672         struct drm_encoder *encoder = &intel_encoder->base;
6673         struct drm_crtc *crtc = NULL;
6674         struct drm_device *dev = encoder->dev;
6675         struct drm_framebuffer *fb;
6676         int i = -1;
6677
6678         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6679                       connector->base.id, drm_get_connector_name(connector),
6680                       encoder->base.id, drm_get_encoder_name(encoder));
6681
6682         /*
6683          * Algorithm gets a little messy:
6684          *
6685          *   - if the connector already has an assigned crtc, use it (but make
6686          *     sure it's on first)
6687          *
6688          *   - try to find the first unused crtc that can drive this connector,
6689          *     and use that if we find one
6690          */
6691
6692         /* See if we already have a CRTC for this connector */
6693         if (encoder->crtc) {
6694                 crtc = encoder->crtc;
6695
6696                 mutex_lock(&crtc->mutex);
6697
6698                 old->dpms_mode = connector->dpms;
6699                 old->load_detect_temp = false;
6700
6701                 /* Make sure the crtc and connector are running */
6702                 if (connector->dpms != DRM_MODE_DPMS_ON)
6703                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6704
6705                 return true;
6706         }
6707
6708         /* Find an unused one (if possible) */
6709         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6710                 i++;
6711                 if (!(encoder->possible_crtcs & (1 << i)))
6712                         continue;
6713                 if (!possible_crtc->enabled) {
6714                         crtc = possible_crtc;
6715                         break;
6716                 }
6717         }
6718
6719         /*
6720          * If we didn't find an unused CRTC, don't use any.
6721          */
6722         if (!crtc) {
6723                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6724                 return false;
6725         }
6726
6727         mutex_lock(&crtc->mutex);
6728         intel_encoder->new_crtc = to_intel_crtc(crtc);
6729         to_intel_connector(connector)->new_encoder = intel_encoder;
6730
6731         intel_crtc = to_intel_crtc(crtc);
6732         old->dpms_mode = connector->dpms;
6733         old->load_detect_temp = true;
6734         old->release_fb = NULL;
6735
6736         if (!mode)
6737                 mode = &load_detect_mode;
6738
6739         /* We need a framebuffer large enough to accommodate all accesses
6740          * that the plane may generate whilst we perform load detection.
6741          * We can not rely on the fbcon either being present (we get called
6742          * during its initialisation to detect all boot displays, or it may
6743          * not even exist) or that it is large enough to satisfy the
6744          * requested mode.
6745          */
6746         fb = mode_fits_in_fbdev(dev, mode);
6747         if (fb == NULL) {
6748                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6749                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6750                 old->release_fb = fb;
6751         } else
6752                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6753         if (IS_ERR(fb)) {
6754                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6755                 mutex_unlock(&crtc->mutex);
6756                 return false;
6757         }
6758
6759         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6760                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6761                 if (old->release_fb)
6762                         old->release_fb->funcs->destroy(old->release_fb);
6763                 mutex_unlock(&crtc->mutex);
6764                 return false;
6765         }
6766
6767         /* let the connector get through one full cycle before testing */
6768         intel_wait_for_vblank(dev, intel_crtc->pipe);
6769         return true;
6770 }
6771
6772 void intel_release_load_detect_pipe(struct drm_connector *connector,
6773                                     struct intel_load_detect_pipe *old)
6774 {
6775         struct intel_encoder *intel_encoder =
6776                 intel_attached_encoder(connector);
6777         struct drm_encoder *encoder = &intel_encoder->base;
6778         struct drm_crtc *crtc = encoder->crtc;
6779
6780         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6781                       connector->base.id, drm_get_connector_name(connector),
6782                       encoder->base.id, drm_get_encoder_name(encoder));
6783
6784         if (old->load_detect_temp) {
6785                 to_intel_connector(connector)->new_encoder = NULL;
6786                 intel_encoder->new_crtc = NULL;
6787                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6788
6789                 if (old->release_fb) {
6790                         drm_framebuffer_unregister_private(old->release_fb);
6791                         drm_framebuffer_unreference(old->release_fb);
6792                 }
6793
6794                 mutex_unlock(&crtc->mutex);
6795                 return;
6796         }
6797
6798         /* Switch crtc and encoder back off if necessary */
6799         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6800                 connector->funcs->dpms(connector, old->dpms_mode);
6801
6802         mutex_unlock(&crtc->mutex);
6803 }
6804
6805 /* Returns the clock of the currently programmed mode of the given pipe. */
6806 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6807 {
6808         struct drm_i915_private *dev_priv = dev->dev_private;
6809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6810         int pipe = intel_crtc->pipe;
6811         u32 dpll = I915_READ(DPLL(pipe));
6812         u32 fp;
6813         intel_clock_t clock;
6814
6815         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6816                 fp = I915_READ(FP0(pipe));
6817         else
6818                 fp = I915_READ(FP1(pipe));
6819
6820         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6821         if (IS_PINEVIEW(dev)) {
6822                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6823                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6824         } else {
6825                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6826                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6827         }
6828
6829         if (!IS_GEN2(dev)) {
6830                 if (IS_PINEVIEW(dev))
6831                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6832                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6833                 else
6834                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6835                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6836
6837                 switch (dpll & DPLL_MODE_MASK) {
6838                 case DPLLB_MODE_DAC_SERIAL:
6839                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6840                                 5 : 10;
6841                         break;
6842                 case DPLLB_MODE_LVDS:
6843                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6844                                 7 : 14;
6845                         break;
6846                 default:
6847                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6848                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6849                         return 0;
6850                 }
6851
6852                 /* XXX: Handle the 100Mhz refclk */
6853                 intel_clock(dev, 96000, &clock);
6854         } else {
6855                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6856
6857                 if (is_lvds) {
6858                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6859                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6860                         clock.p2 = 14;
6861
6862                         if ((dpll & PLL_REF_INPUT_MASK) ==
6863                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6864                                 /* XXX: might not be 66MHz */
6865                                 intel_clock(dev, 66000, &clock);
6866                         } else
6867                                 intel_clock(dev, 48000, &clock);
6868                 } else {
6869                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6870                                 clock.p1 = 2;
6871                         else {
6872                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6873                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6874                         }
6875                         if (dpll & PLL_P2_DIVIDE_BY_4)
6876                                 clock.p2 = 4;
6877                         else
6878                                 clock.p2 = 2;
6879
6880                         intel_clock(dev, 48000, &clock);
6881                 }
6882         }
6883
6884         /* XXX: It would be nice to validate the clocks, but we can't reuse
6885          * i830PllIsValid() because it relies on the xf86_config connector
6886          * configuration being accurate, which it isn't necessarily.
6887          */
6888
6889         return clock.dot;
6890 }
6891
6892 /** Returns the currently programmed mode of the given pipe. */
6893 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6894                                              struct drm_crtc *crtc)
6895 {
6896         struct drm_i915_private *dev_priv = dev->dev_private;
6897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6898         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6899         struct drm_display_mode *mode;
6900         int htot = I915_READ(HTOTAL(cpu_transcoder));
6901         int hsync = I915_READ(HSYNC(cpu_transcoder));
6902         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6903         int vsync = I915_READ(VSYNC(cpu_transcoder));
6904
6905         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6906         if (!mode)
6907                 return NULL;
6908
6909         mode->clock = intel_crtc_clock_get(dev, crtc);
6910         mode->hdisplay = (htot & 0xffff) + 1;
6911         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6912         mode->hsync_start = (hsync & 0xffff) + 1;
6913         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6914         mode->vdisplay = (vtot & 0xffff) + 1;
6915         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6916         mode->vsync_start = (vsync & 0xffff) + 1;
6917         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6918
6919         drm_mode_set_name(mode);
6920
6921         return mode;
6922 }
6923
6924 static void intel_increase_pllclock(struct drm_crtc *crtc)
6925 {
6926         struct drm_device *dev = crtc->dev;
6927         drm_i915_private_t *dev_priv = dev->dev_private;
6928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6929         int pipe = intel_crtc->pipe;
6930         int dpll_reg = DPLL(pipe);
6931         int dpll;
6932
6933         if (HAS_PCH_SPLIT(dev))
6934                 return;
6935
6936         if (!dev_priv->lvds_downclock_avail)
6937                 return;
6938
6939         dpll = I915_READ(dpll_reg);
6940         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6941                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6942
6943                 assert_panel_unlocked(dev_priv, pipe);
6944
6945                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6946                 I915_WRITE(dpll_reg, dpll);
6947                 intel_wait_for_vblank(dev, pipe);
6948
6949                 dpll = I915_READ(dpll_reg);
6950                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6951                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6952         }
6953 }
6954
6955 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6956 {
6957         struct drm_device *dev = crtc->dev;
6958         drm_i915_private_t *dev_priv = dev->dev_private;
6959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6960
6961         if (HAS_PCH_SPLIT(dev))
6962                 return;
6963
6964         if (!dev_priv->lvds_downclock_avail)
6965                 return;
6966
6967         /*
6968          * Since this is called by a timer, we should never get here in
6969          * the manual case.
6970          */
6971         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6972                 int pipe = intel_crtc->pipe;
6973                 int dpll_reg = DPLL(pipe);
6974                 int dpll;
6975
6976                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6977
6978                 assert_panel_unlocked(dev_priv, pipe);
6979
6980                 dpll = I915_READ(dpll_reg);
6981                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6982                 I915_WRITE(dpll_reg, dpll);
6983                 intel_wait_for_vblank(dev, pipe);
6984                 dpll = I915_READ(dpll_reg);
6985                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6986                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6987         }
6988
6989 }
6990
6991 void intel_mark_busy(struct drm_device *dev)
6992 {
6993         i915_update_gfx_val(dev->dev_private);
6994 }
6995
6996 void intel_mark_idle(struct drm_device *dev)
6997 {
6998         struct drm_crtc *crtc;
6999
7000         if (!i915_powersave)
7001                 return;
7002
7003         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7004                 if (!crtc->fb)
7005                         continue;
7006
7007                 intel_decrease_pllclock(crtc);
7008         }
7009 }
7010
7011 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7012 {
7013         struct drm_device *dev = obj->base.dev;
7014         struct drm_crtc *crtc;
7015
7016         if (!i915_powersave)
7017                 return;
7018
7019         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7020                 if (!crtc->fb)
7021                         continue;
7022
7023                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7024                         intel_increase_pllclock(crtc);
7025         }
7026 }
7027
7028 static void intel_crtc_destroy(struct drm_crtc *crtc)
7029 {
7030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7031         struct drm_device *dev = crtc->dev;
7032         struct intel_unpin_work *work;
7033         unsigned long flags;
7034
7035         spin_lock_irqsave(&dev->event_lock, flags);
7036         work = intel_crtc->unpin_work;
7037         intel_crtc->unpin_work = NULL;
7038         spin_unlock_irqrestore(&dev->event_lock, flags);
7039
7040         if (work) {
7041                 cancel_work_sync(&work->work);
7042                 kfree(work);
7043         }
7044
7045         drm_crtc_cleanup(crtc);
7046
7047         kfree(intel_crtc);
7048 }
7049
7050 static void intel_unpin_work_fn(struct work_struct *__work)
7051 {
7052         struct intel_unpin_work *work =
7053                 container_of(__work, struct intel_unpin_work, work);
7054         struct drm_device *dev = work->crtc->dev;
7055
7056         mutex_lock(&dev->struct_mutex);
7057         intel_unpin_fb_obj(work->old_fb_obj);
7058         drm_gem_object_unreference(&work->pending_flip_obj->base);
7059         drm_gem_object_unreference(&work->old_fb_obj->base);
7060
7061         intel_update_fbc(dev);
7062         mutex_unlock(&dev->struct_mutex);
7063
7064         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7065         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7066
7067         kfree(work);
7068 }
7069
7070 static void do_intel_finish_page_flip(struct drm_device *dev,
7071                                       struct drm_crtc *crtc)
7072 {
7073         drm_i915_private_t *dev_priv = dev->dev_private;
7074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7075         struct intel_unpin_work *work;
7076         unsigned long flags;
7077
7078         /* Ignore early vblank irqs */
7079         if (intel_crtc == NULL)
7080                 return;
7081
7082         spin_lock_irqsave(&dev->event_lock, flags);
7083         work = intel_crtc->unpin_work;
7084
7085         /* Ensure we don't miss a work->pending update ... */
7086         smp_rmb();
7087
7088         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7089                 spin_unlock_irqrestore(&dev->event_lock, flags);
7090                 return;
7091         }
7092
7093         /* and that the unpin work is consistent wrt ->pending. */
7094         smp_rmb();
7095
7096         intel_crtc->unpin_work = NULL;
7097
7098         if (work->event)
7099                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7100
7101         drm_vblank_put(dev, intel_crtc->pipe);
7102
7103         spin_unlock_irqrestore(&dev->event_lock, flags);
7104
7105         wake_up_all(&dev_priv->pending_flip_queue);
7106
7107         queue_work(dev_priv->wq, &work->work);
7108
7109         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7110 }
7111
7112 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7113 {
7114         drm_i915_private_t *dev_priv = dev->dev_private;
7115         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7116
7117         do_intel_finish_page_flip(dev, crtc);
7118 }
7119
7120 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7121 {
7122         drm_i915_private_t *dev_priv = dev->dev_private;
7123         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7124
7125         do_intel_finish_page_flip(dev, crtc);
7126 }
7127
7128 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7129 {
7130         drm_i915_private_t *dev_priv = dev->dev_private;
7131         struct intel_crtc *intel_crtc =
7132                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7133         unsigned long flags;
7134
7135         /* NB: An MMIO update of the plane base pointer will also
7136          * generate a page-flip completion irq, i.e. every modeset
7137          * is also accompanied by a spurious intel_prepare_page_flip().
7138          */
7139         spin_lock_irqsave(&dev->event_lock, flags);
7140         if (intel_crtc->unpin_work)
7141                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7142         spin_unlock_irqrestore(&dev->event_lock, flags);
7143 }
7144
7145 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7146 {
7147         /* Ensure that the work item is consistent when activating it ... */
7148         smp_wmb();
7149         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7150         /* and that it is marked active as soon as the irq could fire. */
7151         smp_wmb();
7152 }
7153
7154 static int intel_gen2_queue_flip(struct drm_device *dev,
7155                                  struct drm_crtc *crtc,
7156                                  struct drm_framebuffer *fb,
7157                                  struct drm_i915_gem_object *obj)
7158 {
7159         struct drm_i915_private *dev_priv = dev->dev_private;
7160         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7161         u32 flip_mask;
7162         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7163         int ret;
7164
7165         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7166         if (ret)
7167                 goto err;
7168
7169         ret = intel_ring_begin(ring, 6);
7170         if (ret)
7171                 goto err_unpin;
7172
7173         /* Can't queue multiple flips, so wait for the previous
7174          * one to finish before executing the next.
7175          */
7176         if (intel_crtc->plane)
7177                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7178         else
7179                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7180         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7181         intel_ring_emit(ring, MI_NOOP);
7182         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7183                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7184         intel_ring_emit(ring, fb->pitches[0]);
7185         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7186         intel_ring_emit(ring, 0); /* aux display base address, unused */
7187
7188         intel_mark_page_flip_active(intel_crtc);
7189         intel_ring_advance(ring);
7190         return 0;
7191
7192 err_unpin:
7193         intel_unpin_fb_obj(obj);
7194 err:
7195         return ret;
7196 }
7197
7198 static int intel_gen3_queue_flip(struct drm_device *dev,
7199                                  struct drm_crtc *crtc,
7200                                  struct drm_framebuffer *fb,
7201                                  struct drm_i915_gem_object *obj)
7202 {
7203         struct drm_i915_private *dev_priv = dev->dev_private;
7204         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7205         u32 flip_mask;
7206         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7207         int ret;
7208
7209         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7210         if (ret)
7211                 goto err;
7212
7213         ret = intel_ring_begin(ring, 6);
7214         if (ret)
7215                 goto err_unpin;
7216
7217         if (intel_crtc->plane)
7218                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7219         else
7220                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7221         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7222         intel_ring_emit(ring, MI_NOOP);
7223         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7224                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7225         intel_ring_emit(ring, fb->pitches[0]);
7226         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7227         intel_ring_emit(ring, MI_NOOP);
7228
7229         intel_mark_page_flip_active(intel_crtc);
7230         intel_ring_advance(ring);
7231         return 0;
7232
7233 err_unpin:
7234         intel_unpin_fb_obj(obj);
7235 err:
7236         return ret;
7237 }
7238
7239 static int intel_gen4_queue_flip(struct drm_device *dev,
7240                                  struct drm_crtc *crtc,
7241                                  struct drm_framebuffer *fb,
7242                                  struct drm_i915_gem_object *obj)
7243 {
7244         struct drm_i915_private *dev_priv = dev->dev_private;
7245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7246         uint32_t pf, pipesrc;
7247         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7248         int ret;
7249
7250         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7251         if (ret)
7252                 goto err;
7253
7254         ret = intel_ring_begin(ring, 4);
7255         if (ret)
7256                 goto err_unpin;
7257
7258         /* i965+ uses the linear or tiled offsets from the
7259          * Display Registers (which do not change across a page-flip)
7260          * so we need only reprogram the base address.
7261          */
7262         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7263                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7264         intel_ring_emit(ring, fb->pitches[0]);
7265         intel_ring_emit(ring,
7266                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7267                         obj->tiling_mode);
7268
7269         /* XXX Enabling the panel-fitter across page-flip is so far
7270          * untested on non-native modes, so ignore it for now.
7271          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7272          */
7273         pf = 0;
7274         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7275         intel_ring_emit(ring, pf | pipesrc);
7276
7277         intel_mark_page_flip_active(intel_crtc);
7278         intel_ring_advance(ring);
7279         return 0;
7280
7281 err_unpin:
7282         intel_unpin_fb_obj(obj);
7283 err:
7284         return ret;
7285 }
7286
7287 static int intel_gen6_queue_flip(struct drm_device *dev,
7288                                  struct drm_crtc *crtc,
7289                                  struct drm_framebuffer *fb,
7290                                  struct drm_i915_gem_object *obj)
7291 {
7292         struct drm_i915_private *dev_priv = dev->dev_private;
7293         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7294         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7295         uint32_t pf, pipesrc;
7296         int ret;
7297
7298         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7299         if (ret)
7300                 goto err;
7301
7302         ret = intel_ring_begin(ring, 4);
7303         if (ret)
7304                 goto err_unpin;
7305
7306         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7307                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7308         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7309         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7310
7311         /* Contrary to the suggestions in the documentation,
7312          * "Enable Panel Fitter" does not seem to be required when page
7313          * flipping with a non-native mode, and worse causes a normal
7314          * modeset to fail.
7315          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7316          */
7317         pf = 0;
7318         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7319         intel_ring_emit(ring, pf | pipesrc);
7320
7321         intel_mark_page_flip_active(intel_crtc);
7322         intel_ring_advance(ring);
7323         return 0;
7324
7325 err_unpin:
7326         intel_unpin_fb_obj(obj);
7327 err:
7328         return ret;
7329 }
7330
7331 /*
7332  * On gen7 we currently use the blit ring because (in early silicon at least)
7333  * the render ring doesn't give us interrpts for page flip completion, which
7334  * means clients will hang after the first flip is queued.  Fortunately the
7335  * blit ring generates interrupts properly, so use it instead.
7336  */
7337 static int intel_gen7_queue_flip(struct drm_device *dev,
7338                                  struct drm_crtc *crtc,
7339                                  struct drm_framebuffer *fb,
7340                                  struct drm_i915_gem_object *obj)
7341 {
7342         struct drm_i915_private *dev_priv = dev->dev_private;
7343         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7344         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7345         uint32_t plane_bit = 0;
7346         int ret;
7347
7348         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7349         if (ret)
7350                 goto err;
7351
7352         switch(intel_crtc->plane) {
7353         case PLANE_A:
7354                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7355                 break;
7356         case PLANE_B:
7357                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7358                 break;
7359         case PLANE_C:
7360                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7361                 break;
7362         default:
7363                 WARN_ONCE(1, "unknown plane in flip command\n");
7364                 ret = -ENODEV;
7365                 goto err_unpin;
7366         }
7367
7368         ret = intel_ring_begin(ring, 4);
7369         if (ret)
7370                 goto err_unpin;
7371
7372         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7373         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7374         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7375         intel_ring_emit(ring, (MI_NOOP));
7376
7377         intel_mark_page_flip_active(intel_crtc);
7378         intel_ring_advance(ring);
7379         return 0;
7380
7381 err_unpin:
7382         intel_unpin_fb_obj(obj);
7383 err:
7384         return ret;
7385 }
7386
7387 static int intel_default_queue_flip(struct drm_device *dev,
7388                                     struct drm_crtc *crtc,
7389                                     struct drm_framebuffer *fb,
7390                                     struct drm_i915_gem_object *obj)
7391 {
7392         return -ENODEV;
7393 }
7394
7395 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7396                                 struct drm_framebuffer *fb,
7397                                 struct drm_pending_vblank_event *event)
7398 {
7399         struct drm_device *dev = crtc->dev;
7400         struct drm_i915_private *dev_priv = dev->dev_private;
7401         struct drm_framebuffer *old_fb = crtc->fb;
7402         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7404         struct intel_unpin_work *work;
7405         unsigned long flags;
7406         int ret;
7407
7408         /* Can't change pixel format via MI display flips. */
7409         if (fb->pixel_format != crtc->fb->pixel_format)
7410                 return -EINVAL;
7411
7412         /*
7413          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7414          * Note that pitch changes could also affect these register.
7415          */
7416         if (INTEL_INFO(dev)->gen > 3 &&
7417             (fb->offsets[0] != crtc->fb->offsets[0] ||
7418              fb->pitches[0] != crtc->fb->pitches[0]))
7419                 return -EINVAL;
7420
7421         work = kzalloc(sizeof *work, GFP_KERNEL);
7422         if (work == NULL)
7423                 return -ENOMEM;
7424
7425         work->event = event;
7426         work->crtc = crtc;
7427         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7428         INIT_WORK(&work->work, intel_unpin_work_fn);
7429
7430         ret = drm_vblank_get(dev, intel_crtc->pipe);
7431         if (ret)
7432                 goto free_work;
7433
7434         /* We borrow the event spin lock for protecting unpin_work */
7435         spin_lock_irqsave(&dev->event_lock, flags);
7436         if (intel_crtc->unpin_work) {
7437                 spin_unlock_irqrestore(&dev->event_lock, flags);
7438                 kfree(work);
7439                 drm_vblank_put(dev, intel_crtc->pipe);
7440
7441                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7442                 return -EBUSY;
7443         }
7444         intel_crtc->unpin_work = work;
7445         spin_unlock_irqrestore(&dev->event_lock, flags);
7446
7447         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7448                 flush_workqueue(dev_priv->wq);
7449
7450         ret = i915_mutex_lock_interruptible(dev);
7451         if (ret)
7452                 goto cleanup;
7453
7454         /* Reference the objects for the scheduled work. */
7455         drm_gem_object_reference(&work->old_fb_obj->base);
7456         drm_gem_object_reference(&obj->base);
7457
7458         crtc->fb = fb;
7459
7460         work->pending_flip_obj = obj;
7461
7462         work->enable_stall_check = true;
7463
7464         atomic_inc(&intel_crtc->unpin_work_count);
7465         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7466
7467         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7468         if (ret)
7469                 goto cleanup_pending;
7470
7471         intel_disable_fbc(dev);
7472         intel_mark_fb_busy(obj);
7473         mutex_unlock(&dev->struct_mutex);
7474
7475         trace_i915_flip_request(intel_crtc->plane, obj);
7476
7477         return 0;
7478
7479 cleanup_pending:
7480         atomic_dec(&intel_crtc->unpin_work_count);
7481         crtc->fb = old_fb;
7482         drm_gem_object_unreference(&work->old_fb_obj->base);
7483         drm_gem_object_unreference(&obj->base);
7484         mutex_unlock(&dev->struct_mutex);
7485
7486 cleanup:
7487         spin_lock_irqsave(&dev->event_lock, flags);
7488         intel_crtc->unpin_work = NULL;
7489         spin_unlock_irqrestore(&dev->event_lock, flags);
7490
7491         drm_vblank_put(dev, intel_crtc->pipe);
7492 free_work:
7493         kfree(work);
7494
7495         return ret;
7496 }
7497
7498 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7499         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7500         .load_lut = intel_crtc_load_lut,
7501 };
7502
7503 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7504 {
7505         struct intel_encoder *other_encoder;
7506         struct drm_crtc *crtc = &encoder->new_crtc->base;
7507
7508         if (WARN_ON(!crtc))
7509                 return false;
7510
7511         list_for_each_entry(other_encoder,
7512                             &crtc->dev->mode_config.encoder_list,
7513                             base.head) {
7514
7515                 if (&other_encoder->new_crtc->base != crtc ||
7516                     encoder == other_encoder)
7517                         continue;
7518                 else
7519                         return true;
7520         }
7521
7522         return false;
7523 }
7524
7525 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7526                                   struct drm_crtc *crtc)
7527 {
7528         struct drm_device *dev;
7529         struct drm_crtc *tmp;
7530         int crtc_mask = 1;
7531
7532         WARN(!crtc, "checking null crtc?\n");
7533
7534         dev = crtc->dev;
7535
7536         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7537                 if (tmp == crtc)
7538                         break;
7539                 crtc_mask <<= 1;
7540         }
7541
7542         if (encoder->possible_crtcs & crtc_mask)
7543                 return true;
7544         return false;
7545 }
7546
7547 /**
7548  * intel_modeset_update_staged_output_state
7549  *
7550  * Updates the staged output configuration state, e.g. after we've read out the
7551  * current hw state.
7552  */
7553 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7554 {
7555         struct intel_encoder *encoder;
7556         struct intel_connector *connector;
7557
7558         list_for_each_entry(connector, &dev->mode_config.connector_list,
7559                             base.head) {
7560                 connector->new_encoder =
7561                         to_intel_encoder(connector->base.encoder);
7562         }
7563
7564         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7565                             base.head) {
7566                 encoder->new_crtc =
7567                         to_intel_crtc(encoder->base.crtc);
7568         }
7569 }
7570
7571 /**
7572  * intel_modeset_commit_output_state
7573  *
7574  * This function copies the stage display pipe configuration to the real one.
7575  */
7576 static void intel_modeset_commit_output_state(struct drm_device *dev)
7577 {
7578         struct intel_encoder *encoder;
7579         struct intel_connector *connector;
7580
7581         list_for_each_entry(connector, &dev->mode_config.connector_list,
7582                             base.head) {
7583                 connector->base.encoder = &connector->new_encoder->base;
7584         }
7585
7586         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7587                             base.head) {
7588                 encoder->base.crtc = &encoder->new_crtc->base;
7589         }
7590 }
7591
7592 static int
7593 pipe_config_set_bpp(struct drm_crtc *crtc,
7594                     struct drm_framebuffer *fb,
7595                     struct intel_crtc_config *pipe_config)
7596 {
7597         struct drm_device *dev = crtc->dev;
7598         struct drm_connector *connector;
7599         int bpp;
7600
7601         switch (fb->pixel_format) {
7602         case DRM_FORMAT_C8:
7603                 bpp = 8*3; /* since we go through a colormap */
7604                 break;
7605         case DRM_FORMAT_XRGB1555:
7606         case DRM_FORMAT_ARGB1555:
7607                 /* checked in intel_framebuffer_init already */
7608                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7609                         return -EINVAL;
7610         case DRM_FORMAT_RGB565:
7611                 bpp = 6*3; /* min is 18bpp */
7612                 break;
7613         case DRM_FORMAT_XBGR8888:
7614         case DRM_FORMAT_ABGR8888:
7615                 /* checked in intel_framebuffer_init already */
7616                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7617                         return -EINVAL;
7618         case DRM_FORMAT_XRGB8888:
7619         case DRM_FORMAT_ARGB8888:
7620                 bpp = 8*3;
7621                 break;
7622         case DRM_FORMAT_XRGB2101010:
7623         case DRM_FORMAT_ARGB2101010:
7624         case DRM_FORMAT_XBGR2101010:
7625         case DRM_FORMAT_ABGR2101010:
7626                 /* checked in intel_framebuffer_init already */
7627                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7628                         return -EINVAL;
7629                 bpp = 10*3;
7630                 break;
7631         /* TODO: gen4+ supports 16 bpc floating point, too. */
7632         default:
7633                 DRM_DEBUG_KMS("unsupported depth\n");
7634                 return -EINVAL;
7635         }
7636
7637         pipe_config->pipe_bpp = bpp;
7638
7639         /* Clamp display bpp to EDID value */
7640         list_for_each_entry(connector, &dev->mode_config.connector_list,
7641                             head) {
7642                 if (connector->encoder && connector->encoder->crtc != crtc)
7643                         continue;
7644
7645                 /* Don't use an invalid EDID bpc value */
7646                 if (connector->display_info.bpc &&
7647                     connector->display_info.bpc * 3 < bpp) {
7648                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7649                                       bpp, connector->display_info.bpc*3);
7650                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7651                 }
7652
7653                 /* Clamp bpp to 8 on screens without EDID 1.4 */
7654                 if (connector->display_info.bpc == 0 && bpp > 24) {
7655                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7656                                       bpp);
7657                         pipe_config->pipe_bpp = 24;
7658                 }
7659         }
7660
7661         return bpp;
7662 }
7663
7664 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7665                                    struct intel_crtc_config *pipe_config,
7666                                    const char *context)
7667 {
7668         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7669                       context, pipe_name(crtc->pipe));
7670
7671         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7672         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7673                       pipe_config->pipe_bpp, pipe_config->dither);
7674         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7675                       pipe_config->has_pch_encoder,
7676                       pipe_config->fdi_lanes,
7677                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7678                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7679                       pipe_config->fdi_m_n.tu);
7680         DRM_DEBUG_KMS("requested mode:\n");
7681         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7682         DRM_DEBUG_KMS("adjusted mode:\n");
7683         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7684         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7685                       pipe_config->gmch_pfit.control,
7686                       pipe_config->gmch_pfit.pgm_ratios,
7687                       pipe_config->gmch_pfit.lvds_border_bits);
7688         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7689                       pipe_config->pch_pfit.pos,
7690                       pipe_config->pch_pfit.size);
7691 }
7692
7693 static struct intel_crtc_config *
7694 intel_modeset_pipe_config(struct drm_crtc *crtc,
7695                           struct drm_framebuffer *fb,
7696                           struct drm_display_mode *mode)
7697 {
7698         struct drm_device *dev = crtc->dev;
7699         struct drm_encoder_helper_funcs *encoder_funcs;
7700         struct intel_encoder *encoder;
7701         struct intel_crtc_config *pipe_config;
7702         int plane_bpp, ret = -EINVAL;
7703         bool retry = true;
7704
7705         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7706         if (!pipe_config)
7707                 return ERR_PTR(-ENOMEM);
7708
7709         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7710         drm_mode_copy(&pipe_config->requested_mode, mode);
7711         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7712
7713         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7714         if (plane_bpp < 0)
7715                 goto fail;
7716
7717 encoder_retry:
7718         /* Pass our mode to the connectors and the CRTC to give them a chance to
7719          * adjust it according to limitations or connector properties, and also
7720          * a chance to reject the mode entirely.
7721          */
7722         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7723                             base.head) {
7724
7725                 if (&encoder->new_crtc->base != crtc)
7726                         continue;
7727
7728                 if (encoder->compute_config) {
7729                         if (!(encoder->compute_config(encoder, pipe_config))) {
7730                                 DRM_DEBUG_KMS("Encoder config failure\n");
7731                                 goto fail;
7732                         }
7733
7734                         continue;
7735                 }
7736
7737                 encoder_funcs = encoder->base.helper_private;
7738                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7739                                                 &pipe_config->requested_mode,
7740                                                 &pipe_config->adjusted_mode))) {
7741                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7742                         goto fail;
7743                 }
7744         }
7745
7746         ret = intel_crtc_compute_config(crtc, pipe_config);
7747         if (ret < 0) {
7748                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7749                 goto fail;
7750         }
7751
7752         if (ret == RETRY) {
7753                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7754                         ret = -EINVAL;
7755                         goto fail;
7756                 }
7757
7758                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7759                 retry = false;
7760                 goto encoder_retry;
7761         }
7762
7763         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7764         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7765                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7766
7767         return pipe_config;
7768 fail:
7769         kfree(pipe_config);
7770         return ERR_PTR(ret);
7771 }
7772
7773 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7774  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7775 static void
7776 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7777                              unsigned *prepare_pipes, unsigned *disable_pipes)
7778 {
7779         struct intel_crtc *intel_crtc;
7780         struct drm_device *dev = crtc->dev;
7781         struct intel_encoder *encoder;
7782         struct intel_connector *connector;
7783         struct drm_crtc *tmp_crtc;
7784
7785         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7786
7787         /* Check which crtcs have changed outputs connected to them, these need
7788          * to be part of the prepare_pipes mask. We don't (yet) support global
7789          * modeset across multiple crtcs, so modeset_pipes will only have one
7790          * bit set at most. */
7791         list_for_each_entry(connector, &dev->mode_config.connector_list,
7792                             base.head) {
7793                 if (connector->base.encoder == &connector->new_encoder->base)
7794                         continue;
7795
7796                 if (connector->base.encoder) {
7797                         tmp_crtc = connector->base.encoder->crtc;
7798
7799                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7800                 }
7801
7802                 if (connector->new_encoder)
7803                         *prepare_pipes |=
7804                                 1 << connector->new_encoder->new_crtc->pipe;
7805         }
7806
7807         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7808                             base.head) {
7809                 if (encoder->base.crtc == &encoder->new_crtc->base)
7810                         continue;
7811
7812                 if (encoder->base.crtc) {
7813                         tmp_crtc = encoder->base.crtc;
7814
7815                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7816                 }
7817
7818                 if (encoder->new_crtc)
7819                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7820         }
7821
7822         /* Check for any pipes that will be fully disabled ... */
7823         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7824                             base.head) {
7825                 bool used = false;
7826
7827                 /* Don't try to disable disabled crtcs. */
7828                 if (!intel_crtc->base.enabled)
7829                         continue;
7830
7831                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7832                                     base.head) {
7833                         if (encoder->new_crtc == intel_crtc)
7834                                 used = true;
7835                 }
7836
7837                 if (!used)
7838                         *disable_pipes |= 1 << intel_crtc->pipe;
7839         }
7840
7841
7842         /* set_mode is also used to update properties on life display pipes. */
7843         intel_crtc = to_intel_crtc(crtc);
7844         if (crtc->enabled)
7845                 *prepare_pipes |= 1 << intel_crtc->pipe;
7846
7847         /*
7848          * For simplicity do a full modeset on any pipe where the output routing
7849          * changed. We could be more clever, but that would require us to be
7850          * more careful with calling the relevant encoder->mode_set functions.
7851          */
7852         if (*prepare_pipes)
7853                 *modeset_pipes = *prepare_pipes;
7854
7855         /* ... and mask these out. */
7856         *modeset_pipes &= ~(*disable_pipes);
7857         *prepare_pipes &= ~(*disable_pipes);
7858
7859         /*
7860          * HACK: We don't (yet) fully support global modesets. intel_set_config
7861          * obies this rule, but the modeset restore mode of
7862          * intel_modeset_setup_hw_state does not.
7863          */
7864         *modeset_pipes &= 1 << intel_crtc->pipe;
7865         *prepare_pipes &= 1 << intel_crtc->pipe;
7866
7867         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7868                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7869 }
7870
7871 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7872 {
7873         struct drm_encoder *encoder;
7874         struct drm_device *dev = crtc->dev;
7875
7876         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7877                 if (encoder->crtc == crtc)
7878                         return true;
7879
7880         return false;
7881 }
7882
7883 static void
7884 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7885 {
7886         struct intel_encoder *intel_encoder;
7887         struct intel_crtc *intel_crtc;
7888         struct drm_connector *connector;
7889
7890         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7891                             base.head) {
7892                 if (!intel_encoder->base.crtc)
7893                         continue;
7894
7895                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7896
7897                 if (prepare_pipes & (1 << intel_crtc->pipe))
7898                         intel_encoder->connectors_active = false;
7899         }
7900
7901         intel_modeset_commit_output_state(dev);
7902
7903         /* Update computed state. */
7904         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7905                             base.head) {
7906                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7907         }
7908
7909         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7910                 if (!connector->encoder || !connector->encoder->crtc)
7911                         continue;
7912
7913                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7914
7915                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7916                         struct drm_property *dpms_property =
7917                                 dev->mode_config.dpms_property;
7918
7919                         connector->dpms = DRM_MODE_DPMS_ON;
7920                         drm_object_property_set_value(&connector->base,
7921                                                          dpms_property,
7922                                                          DRM_MODE_DPMS_ON);
7923
7924                         intel_encoder = to_intel_encoder(connector->encoder);
7925                         intel_encoder->connectors_active = true;
7926                 }
7927         }
7928
7929 }
7930
7931 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7932         list_for_each_entry((intel_crtc), \
7933                             &(dev)->mode_config.crtc_list, \
7934                             base.head) \
7935                 if (mask & (1 <<(intel_crtc)->pipe))
7936
7937 static bool
7938 intel_pipe_config_compare(struct drm_device *dev,
7939                           struct intel_crtc_config *current_config,
7940                           struct intel_crtc_config *pipe_config)
7941 {
7942 #define PIPE_CONF_CHECK_I(name) \
7943         if (current_config->name != pipe_config->name) { \
7944                 DRM_ERROR("mismatch in " #name " " \
7945                           "(expected %i, found %i)\n", \
7946                           current_config->name, \
7947                           pipe_config->name); \
7948                 return false; \
7949         }
7950
7951 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
7952         if ((current_config->name ^ pipe_config->name) & (mask)) { \
7953                 DRM_ERROR("mismatch in " #name " " \
7954                           "(expected %i, found %i)\n", \
7955                           current_config->name & (mask), \
7956                           pipe_config->name & (mask)); \
7957                 return false; \
7958         }
7959
7960         PIPE_CONF_CHECK_I(cpu_transcoder);
7961
7962         PIPE_CONF_CHECK_I(has_pch_encoder);
7963         PIPE_CONF_CHECK_I(fdi_lanes);
7964         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
7965         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
7966         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
7967         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
7968         PIPE_CONF_CHECK_I(fdi_m_n.tu);
7969
7970         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
7971         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
7972         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
7973         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
7974         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
7975         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
7976
7977         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
7978         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
7979         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
7980         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
7981         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
7982         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
7983
7984         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7985                               DRM_MODE_FLAG_INTERLACE);
7986
7987         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7988                               DRM_MODE_FLAG_PHSYNC);
7989         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7990                               DRM_MODE_FLAG_NHSYNC);
7991         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7992                               DRM_MODE_FLAG_PVSYNC);
7993         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
7994                               DRM_MODE_FLAG_NVSYNC);
7995
7996         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
7997         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
7998
7999         PIPE_CONF_CHECK_I(gmch_pfit.control);
8000         /* pfit ratios are autocomputed by the hw on gen4+ */
8001         if (INTEL_INFO(dev)->gen < 4)
8002                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8003         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8004         PIPE_CONF_CHECK_I(pch_pfit.pos);
8005         PIPE_CONF_CHECK_I(pch_pfit.size);
8006
8007 #undef PIPE_CONF_CHECK_I
8008 #undef PIPE_CONF_CHECK_FLAGS
8009
8010         return true;
8011 }
8012
8013 void
8014 intel_modeset_check_state(struct drm_device *dev)
8015 {
8016         drm_i915_private_t *dev_priv = dev->dev_private;
8017         struct intel_crtc *crtc;
8018         struct intel_encoder *encoder;
8019         struct intel_connector *connector;
8020         struct intel_crtc_config pipe_config;
8021
8022         list_for_each_entry(connector, &dev->mode_config.connector_list,
8023                             base.head) {
8024                 /* This also checks the encoder/connector hw state with the
8025                  * ->get_hw_state callbacks. */
8026                 intel_connector_check_state(connector);
8027
8028                 WARN(&connector->new_encoder->base != connector->base.encoder,
8029                      "connector's staged encoder doesn't match current encoder\n");
8030         }
8031
8032         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8033                             base.head) {
8034                 bool enabled = false;
8035                 bool active = false;
8036                 enum pipe pipe, tracked_pipe;
8037
8038                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8039                               encoder->base.base.id,
8040                               drm_get_encoder_name(&encoder->base));
8041
8042                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8043                      "encoder's stage crtc doesn't match current crtc\n");
8044                 WARN(encoder->connectors_active && !encoder->base.crtc,
8045                      "encoder's active_connectors set, but no crtc\n");
8046
8047                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8048                                     base.head) {
8049                         if (connector->base.encoder != &encoder->base)
8050                                 continue;
8051                         enabled = true;
8052                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8053                                 active = true;
8054                 }
8055                 WARN(!!encoder->base.crtc != enabled,
8056                      "encoder's enabled state mismatch "
8057                      "(expected %i, found %i)\n",
8058                      !!encoder->base.crtc, enabled);
8059                 WARN(active && !encoder->base.crtc,
8060                      "active encoder with no crtc\n");
8061
8062                 WARN(encoder->connectors_active != active,
8063                      "encoder's computed active state doesn't match tracked active state "
8064                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8065
8066                 active = encoder->get_hw_state(encoder, &pipe);
8067                 WARN(active != encoder->connectors_active,
8068                      "encoder's hw state doesn't match sw tracking "
8069                      "(expected %i, found %i)\n",
8070                      encoder->connectors_active, active);
8071
8072                 if (!encoder->base.crtc)
8073                         continue;
8074
8075                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8076                 WARN(active && pipe != tracked_pipe,
8077                      "active encoder's pipe doesn't match"
8078                      "(expected %i, found %i)\n",
8079                      tracked_pipe, pipe);
8080
8081         }
8082
8083         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8084                             base.head) {
8085                 bool enabled = false;
8086                 bool active = false;
8087
8088                 memset(&pipe_config, 0, sizeof(pipe_config));
8089
8090                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8091                               crtc->base.base.id);
8092
8093                 WARN(crtc->active && !crtc->base.enabled,
8094                      "active crtc, but not enabled in sw tracking\n");
8095
8096                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8097                                     base.head) {
8098                         if (encoder->base.crtc != &crtc->base)
8099                                 continue;
8100                         enabled = true;
8101                         if (encoder->connectors_active)
8102                                 active = true;
8103                         if (encoder->get_config)
8104                                 encoder->get_config(encoder, &pipe_config);
8105                 }
8106                 WARN(active != crtc->active,
8107                      "crtc's computed active state doesn't match tracked active state "
8108                      "(expected %i, found %i)\n", active, crtc->active);
8109                 WARN(enabled != crtc->base.enabled,
8110                      "crtc's computed enabled state doesn't match tracked enabled state "
8111                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8112
8113                 active = dev_priv->display.get_pipe_config(crtc,
8114                                                            &pipe_config);
8115                 WARN(crtc->active != active,
8116                      "crtc active state doesn't match with hw state "
8117                      "(expected %i, found %i)\n", crtc->active, active);
8118
8119                 if (active &&
8120                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8121                         WARN(1, "pipe state doesn't match!\n");
8122                         intel_dump_pipe_config(crtc, &pipe_config,
8123                                                "[hw state]");
8124                         intel_dump_pipe_config(crtc, &crtc->config,
8125                                                "[sw state]");
8126                 }
8127         }
8128 }
8129
8130 static int __intel_set_mode(struct drm_crtc *crtc,
8131                             struct drm_display_mode *mode,
8132                             int x, int y, struct drm_framebuffer *fb)
8133 {
8134         struct drm_device *dev = crtc->dev;
8135         drm_i915_private_t *dev_priv = dev->dev_private;
8136         struct drm_display_mode *saved_mode, *saved_hwmode;
8137         struct intel_crtc_config *pipe_config = NULL;
8138         struct intel_crtc *intel_crtc;
8139         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8140         int ret = 0;
8141
8142         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8143         if (!saved_mode)
8144                 return -ENOMEM;
8145         saved_hwmode = saved_mode + 1;
8146
8147         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8148                                      &prepare_pipes, &disable_pipes);
8149
8150         *saved_hwmode = crtc->hwmode;
8151         *saved_mode = crtc->mode;
8152
8153         /* Hack: Because we don't (yet) support global modeset on multiple
8154          * crtcs, we don't keep track of the new mode for more than one crtc.
8155          * Hence simply check whether any bit is set in modeset_pipes in all the
8156          * pieces of code that are not yet converted to deal with mutliple crtcs
8157          * changing their mode at the same time. */
8158         if (modeset_pipes) {
8159                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8160                 if (IS_ERR(pipe_config)) {
8161                         ret = PTR_ERR(pipe_config);
8162                         pipe_config = NULL;
8163
8164                         goto out;
8165                 }
8166                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8167                                        "[modeset]");
8168         }
8169
8170         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8171                 intel_crtc_disable(&intel_crtc->base);
8172
8173         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8174                 if (intel_crtc->base.enabled)
8175                         dev_priv->display.crtc_disable(&intel_crtc->base);
8176         }
8177
8178         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8179          * to set it here already despite that we pass it down the callchain.
8180          */
8181         if (modeset_pipes) {
8182                 crtc->mode = *mode;
8183                 /* mode_set/enable/disable functions rely on a correct pipe
8184                  * config. */
8185                 to_intel_crtc(crtc)->config = *pipe_config;
8186         }
8187
8188         /* Only after disabling all output pipelines that will be changed can we
8189          * update the the output configuration. */
8190         intel_modeset_update_state(dev, prepare_pipes);
8191
8192         if (dev_priv->display.modeset_global_resources)
8193                 dev_priv->display.modeset_global_resources(dev);
8194
8195         /* Set up the DPLL and any encoders state that needs to adjust or depend
8196          * on the DPLL.
8197          */
8198         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8199                 ret = intel_crtc_mode_set(&intel_crtc->base,
8200                                           x, y, fb);
8201                 if (ret)
8202                         goto done;
8203         }
8204
8205         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8206         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8207                 dev_priv->display.crtc_enable(&intel_crtc->base);
8208
8209         if (modeset_pipes) {
8210                 /* Store real post-adjustment hardware mode. */
8211                 crtc->hwmode = pipe_config->adjusted_mode;
8212
8213                 /* Calculate and store various constants which
8214                  * are later needed by vblank and swap-completion
8215                  * timestamping. They are derived from true hwmode.
8216                  */
8217                 drm_calc_timestamping_constants(crtc);
8218         }
8219
8220         /* FIXME: add subpixel order */
8221 done:
8222         if (ret && crtc->enabled) {
8223                 crtc->hwmode = *saved_hwmode;
8224                 crtc->mode = *saved_mode;
8225         }
8226
8227 out:
8228         kfree(pipe_config);
8229         kfree(saved_mode);
8230         return ret;
8231 }
8232
8233 int intel_set_mode(struct drm_crtc *crtc,
8234                      struct drm_display_mode *mode,
8235                      int x, int y, struct drm_framebuffer *fb)
8236 {
8237         int ret;
8238
8239         ret = __intel_set_mode(crtc, mode, x, y, fb);
8240
8241         if (ret == 0)
8242                 intel_modeset_check_state(crtc->dev);
8243
8244         return ret;
8245 }
8246
8247 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8248 {
8249         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8250 }
8251
8252 #undef for_each_intel_crtc_masked
8253
8254 static void intel_set_config_free(struct intel_set_config *config)
8255 {
8256         if (!config)
8257                 return;
8258
8259         kfree(config->save_connector_encoders);
8260         kfree(config->save_encoder_crtcs);
8261         kfree(config);
8262 }
8263
8264 static int intel_set_config_save_state(struct drm_device *dev,
8265                                        struct intel_set_config *config)
8266 {
8267         struct drm_encoder *encoder;
8268         struct drm_connector *connector;
8269         int count;
8270
8271         config->save_encoder_crtcs =
8272                 kcalloc(dev->mode_config.num_encoder,
8273                         sizeof(struct drm_crtc *), GFP_KERNEL);
8274         if (!config->save_encoder_crtcs)
8275                 return -ENOMEM;
8276
8277         config->save_connector_encoders =
8278                 kcalloc(dev->mode_config.num_connector,
8279                         sizeof(struct drm_encoder *), GFP_KERNEL);
8280         if (!config->save_connector_encoders)
8281                 return -ENOMEM;
8282
8283         /* Copy data. Note that driver private data is not affected.
8284          * Should anything bad happen only the expected state is
8285          * restored, not the drivers personal bookkeeping.
8286          */
8287         count = 0;
8288         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8289                 config->save_encoder_crtcs[count++] = encoder->crtc;
8290         }
8291
8292         count = 0;
8293         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8294                 config->save_connector_encoders[count++] = connector->encoder;
8295         }
8296
8297         return 0;
8298 }
8299
8300 static void intel_set_config_restore_state(struct drm_device *dev,
8301                                            struct intel_set_config *config)
8302 {
8303         struct intel_encoder *encoder;
8304         struct intel_connector *connector;
8305         int count;
8306
8307         count = 0;
8308         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8309                 encoder->new_crtc =
8310                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8311         }
8312
8313         count = 0;
8314         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8315                 connector->new_encoder =
8316                         to_intel_encoder(config->save_connector_encoders[count++]);
8317         }
8318 }
8319
8320 static void
8321 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8322                                       struct intel_set_config *config)
8323 {
8324
8325         /* We should be able to check here if the fb has the same properties
8326          * and then just flip_or_move it */
8327         if (set->crtc->fb != set->fb) {
8328                 /* If we have no fb then treat it as a full mode set */
8329                 if (set->crtc->fb == NULL) {
8330                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8331                         config->mode_changed = true;
8332                 } else if (set->fb == NULL) {
8333                         config->mode_changed = true;
8334                 } else if (set->fb->pixel_format !=
8335                            set->crtc->fb->pixel_format) {
8336                         config->mode_changed = true;
8337                 } else
8338                         config->fb_changed = true;
8339         }
8340
8341         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8342                 config->fb_changed = true;
8343
8344         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8345                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8346                 drm_mode_debug_printmodeline(&set->crtc->mode);
8347                 drm_mode_debug_printmodeline(set->mode);
8348                 config->mode_changed = true;
8349         }
8350 }
8351
8352 static int
8353 intel_modeset_stage_output_state(struct drm_device *dev,
8354                                  struct drm_mode_set *set,
8355                                  struct intel_set_config *config)
8356 {
8357         struct drm_crtc *new_crtc;
8358         struct intel_connector *connector;
8359         struct intel_encoder *encoder;
8360         int count, ro;
8361
8362         /* The upper layers ensure that we either disable a crtc or have a list
8363          * of connectors. For paranoia, double-check this. */
8364         WARN_ON(!set->fb && (set->num_connectors != 0));
8365         WARN_ON(set->fb && (set->num_connectors == 0));
8366
8367         count = 0;
8368         list_for_each_entry(connector, &dev->mode_config.connector_list,
8369                             base.head) {
8370                 /* Otherwise traverse passed in connector list and get encoders
8371                  * for them. */
8372                 for (ro = 0; ro < set->num_connectors; ro++) {
8373                         if (set->connectors[ro] == &connector->base) {
8374                                 connector->new_encoder = connector->encoder;
8375                                 break;
8376                         }
8377                 }
8378
8379                 /* If we disable the crtc, disable all its connectors. Also, if
8380                  * the connector is on the changing crtc but not on the new
8381                  * connector list, disable it. */
8382                 if ((!set->fb || ro == set->num_connectors) &&
8383                     connector->base.encoder &&
8384                     connector->base.encoder->crtc == set->crtc) {
8385                         connector->new_encoder = NULL;
8386
8387                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8388                                 connector->base.base.id,
8389                                 drm_get_connector_name(&connector->base));
8390                 }
8391
8392
8393                 if (&connector->new_encoder->base != connector->base.encoder) {
8394                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8395                         config->mode_changed = true;
8396                 }
8397         }
8398         /* connector->new_encoder is now updated for all connectors. */
8399
8400         /* Update crtc of enabled connectors. */
8401         count = 0;
8402         list_for_each_entry(connector, &dev->mode_config.connector_list,
8403                             base.head) {
8404                 if (!connector->new_encoder)
8405                         continue;
8406
8407                 new_crtc = connector->new_encoder->base.crtc;
8408
8409                 for (ro = 0; ro < set->num_connectors; ro++) {
8410                         if (set->connectors[ro] == &connector->base)
8411                                 new_crtc = set->crtc;
8412                 }
8413
8414                 /* Make sure the new CRTC will work with the encoder */
8415                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8416                                            new_crtc)) {
8417                         return -EINVAL;
8418                 }
8419                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8420
8421                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8422                         connector->base.base.id,
8423                         drm_get_connector_name(&connector->base),
8424                         new_crtc->base.id);
8425         }
8426
8427         /* Check for any encoders that needs to be disabled. */
8428         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8429                             base.head) {
8430                 list_for_each_entry(connector,
8431                                     &dev->mode_config.connector_list,
8432                                     base.head) {
8433                         if (connector->new_encoder == encoder) {
8434                                 WARN_ON(!connector->new_encoder->new_crtc);
8435
8436                                 goto next_encoder;
8437                         }
8438                 }
8439                 encoder->new_crtc = NULL;
8440 next_encoder:
8441                 /* Only now check for crtc changes so we don't miss encoders
8442                  * that will be disabled. */
8443                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8444                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8445                         config->mode_changed = true;
8446                 }
8447         }
8448         /* Now we've also updated encoder->new_crtc for all encoders. */
8449
8450         return 0;
8451 }
8452
8453 static int intel_crtc_set_config(struct drm_mode_set *set)
8454 {
8455         struct drm_device *dev;
8456         struct drm_mode_set save_set;
8457         struct intel_set_config *config;
8458         int ret;
8459
8460         BUG_ON(!set);
8461         BUG_ON(!set->crtc);
8462         BUG_ON(!set->crtc->helper_private);
8463
8464         /* Enforce sane interface api - has been abused by the fb helper. */
8465         BUG_ON(!set->mode && set->fb);
8466         BUG_ON(set->fb && set->num_connectors == 0);
8467
8468         if (set->fb) {
8469                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8470                                 set->crtc->base.id, set->fb->base.id,
8471                                 (int)set->num_connectors, set->x, set->y);
8472         } else {
8473                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8474         }
8475
8476         dev = set->crtc->dev;
8477
8478         ret = -ENOMEM;
8479         config = kzalloc(sizeof(*config), GFP_KERNEL);
8480         if (!config)
8481                 goto out_config;
8482
8483         ret = intel_set_config_save_state(dev, config);
8484         if (ret)
8485                 goto out_config;
8486
8487         save_set.crtc = set->crtc;
8488         save_set.mode = &set->crtc->mode;
8489         save_set.x = set->crtc->x;
8490         save_set.y = set->crtc->y;
8491         save_set.fb = set->crtc->fb;
8492
8493         /* Compute whether we need a full modeset, only an fb base update or no
8494          * change at all. In the future we might also check whether only the
8495          * mode changed, e.g. for LVDS where we only change the panel fitter in
8496          * such cases. */
8497         intel_set_config_compute_mode_changes(set, config);
8498
8499         ret = intel_modeset_stage_output_state(dev, set, config);
8500         if (ret)
8501                 goto fail;
8502
8503         if (config->mode_changed) {
8504                 ret = intel_set_mode(set->crtc, set->mode,
8505                                      set->x, set->y, set->fb);
8506                 if (ret) {
8507                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8508                                   set->crtc->base.id, ret);
8509                         goto fail;
8510                 }
8511         } else if (config->fb_changed) {
8512                 intel_crtc_wait_for_pending_flips(set->crtc);
8513
8514                 ret = intel_pipe_set_base(set->crtc,
8515                                           set->x, set->y, set->fb);
8516         }
8517
8518         intel_set_config_free(config);
8519
8520         return 0;
8521
8522 fail:
8523         intel_set_config_restore_state(dev, config);
8524
8525         /* Try to restore the config */
8526         if (config->mode_changed &&
8527             intel_set_mode(save_set.crtc, save_set.mode,
8528                            save_set.x, save_set.y, save_set.fb))
8529                 DRM_ERROR("failed to restore config after modeset failure\n");
8530
8531 out_config:
8532         intel_set_config_free(config);
8533         return ret;
8534 }
8535
8536 static const struct drm_crtc_funcs intel_crtc_funcs = {
8537         .cursor_set = intel_crtc_cursor_set,
8538         .cursor_move = intel_crtc_cursor_move,
8539         .gamma_set = intel_crtc_gamma_set,
8540         .set_config = intel_crtc_set_config,
8541         .destroy = intel_crtc_destroy,
8542         .page_flip = intel_crtc_page_flip,
8543 };
8544
8545 static void intel_cpu_pll_init(struct drm_device *dev)
8546 {
8547         if (HAS_DDI(dev))
8548                 intel_ddi_pll_init(dev);
8549 }
8550
8551 static void intel_pch_pll_init(struct drm_device *dev)
8552 {
8553         drm_i915_private_t *dev_priv = dev->dev_private;
8554         int i;
8555
8556         if (dev_priv->num_pch_pll == 0) {
8557                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8558                 return;
8559         }
8560
8561         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8562                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8563                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8564                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8565         }
8566 }
8567
8568 static void intel_crtc_init(struct drm_device *dev, int pipe)
8569 {
8570         drm_i915_private_t *dev_priv = dev->dev_private;
8571         struct intel_crtc *intel_crtc;
8572         int i;
8573
8574         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8575         if (intel_crtc == NULL)
8576                 return;
8577
8578         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8579
8580         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8581         for (i = 0; i < 256; i++) {
8582                 intel_crtc->lut_r[i] = i;
8583                 intel_crtc->lut_g[i] = i;
8584                 intel_crtc->lut_b[i] = i;
8585         }
8586
8587         /* Swap pipes & planes for FBC on pre-965 */
8588         intel_crtc->pipe = pipe;
8589         intel_crtc->plane = pipe;
8590         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8591                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8592                 intel_crtc->plane = !pipe;
8593         }
8594
8595         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8596                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8597         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8598         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8599
8600         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8601 }
8602
8603 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8604                                 struct drm_file *file)
8605 {
8606         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8607         struct drm_mode_object *drmmode_obj;
8608         struct intel_crtc *crtc;
8609
8610         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8611                 return -ENODEV;
8612
8613         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8614                         DRM_MODE_OBJECT_CRTC);
8615
8616         if (!drmmode_obj) {
8617                 DRM_ERROR("no such CRTC id\n");
8618                 return -EINVAL;
8619         }
8620
8621         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8622         pipe_from_crtc_id->pipe = crtc->pipe;
8623
8624         return 0;
8625 }
8626
8627 static int intel_encoder_clones(struct intel_encoder *encoder)
8628 {
8629         struct drm_device *dev = encoder->base.dev;
8630         struct intel_encoder *source_encoder;
8631         int index_mask = 0;
8632         int entry = 0;
8633
8634         list_for_each_entry(source_encoder,
8635                             &dev->mode_config.encoder_list, base.head) {
8636
8637                 if (encoder == source_encoder)
8638                         index_mask |= (1 << entry);
8639
8640                 /* Intel hw has only one MUX where enocoders could be cloned. */
8641                 if (encoder->cloneable && source_encoder->cloneable)
8642                         index_mask |= (1 << entry);
8643
8644                 entry++;
8645         }
8646
8647         return index_mask;
8648 }
8649
8650 static bool has_edp_a(struct drm_device *dev)
8651 {
8652         struct drm_i915_private *dev_priv = dev->dev_private;
8653
8654         if (!IS_MOBILE(dev))
8655                 return false;
8656
8657         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8658                 return false;
8659
8660         if (IS_GEN5(dev) &&
8661             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8662                 return false;
8663
8664         return true;
8665 }
8666
8667 static void intel_setup_outputs(struct drm_device *dev)
8668 {
8669         struct drm_i915_private *dev_priv = dev->dev_private;
8670         struct intel_encoder *encoder;
8671         bool dpd_is_edp = false;
8672         bool has_lvds;
8673
8674         has_lvds = intel_lvds_init(dev);
8675         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8676                 /* disable the panel fitter on everything but LVDS */
8677                 I915_WRITE(PFIT_CONTROL, 0);
8678         }
8679
8680         if (!IS_ULT(dev))
8681                 intel_crt_init(dev);
8682
8683         if (HAS_DDI(dev)) {
8684                 int found;
8685
8686                 /* Haswell uses DDI functions to detect digital outputs */
8687                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8688                 /* DDI A only supports eDP */
8689                 if (found)
8690                         intel_ddi_init(dev, PORT_A);
8691
8692                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8693                  * register */
8694                 found = I915_READ(SFUSE_STRAP);
8695
8696                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8697                         intel_ddi_init(dev, PORT_B);
8698                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8699                         intel_ddi_init(dev, PORT_C);
8700                 if (found & SFUSE_STRAP_DDID_DETECTED)
8701                         intel_ddi_init(dev, PORT_D);
8702         } else if (HAS_PCH_SPLIT(dev)) {
8703                 int found;
8704                 dpd_is_edp = intel_dpd_is_edp(dev);
8705
8706                 if (has_edp_a(dev))
8707                         intel_dp_init(dev, DP_A, PORT_A);
8708
8709                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8710                         /* PCH SDVOB multiplex with HDMIB */
8711                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8712                         if (!found)
8713                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8714                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8715                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8716                 }
8717
8718                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8719                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8720
8721                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8722                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8723
8724                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8725                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8726
8727                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8728                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8729         } else if (IS_VALLEYVIEW(dev)) {
8730                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8731                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8732                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8733
8734                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8735                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8736                                         PORT_B);
8737                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8738                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8739                 }
8740         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8741                 bool found = false;
8742
8743                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8744                         DRM_DEBUG_KMS("probing SDVOB\n");
8745                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8746                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8747                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8748                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8749                         }
8750
8751                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
8752                                 intel_dp_init(dev, DP_B, PORT_B);
8753                 }
8754
8755                 /* Before G4X SDVOC doesn't have its own detect register */
8756
8757                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8758                         DRM_DEBUG_KMS("probing SDVOC\n");
8759                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8760                 }
8761
8762                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8763
8764                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8765                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8766                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8767                         }
8768                         if (SUPPORTS_INTEGRATED_DP(dev))
8769                                 intel_dp_init(dev, DP_C, PORT_C);
8770                 }
8771
8772                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8773                     (I915_READ(DP_D) & DP_DETECTED))
8774                         intel_dp_init(dev, DP_D, PORT_D);
8775         } else if (IS_GEN2(dev))
8776                 intel_dvo_init(dev);
8777
8778         if (SUPPORTS_TV(dev))
8779                 intel_tv_init(dev);
8780
8781         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8782                 encoder->base.possible_crtcs = encoder->crtc_mask;
8783                 encoder->base.possible_clones =
8784                         intel_encoder_clones(encoder);
8785         }
8786
8787         intel_init_pch_refclk(dev);
8788
8789         drm_helper_move_panel_connectors_to_head(dev);
8790 }
8791
8792 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8793 {
8794         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8795
8796         drm_framebuffer_cleanup(fb);
8797         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8798
8799         kfree(intel_fb);
8800 }
8801
8802 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8803                                                 struct drm_file *file,
8804                                                 unsigned int *handle)
8805 {
8806         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8807         struct drm_i915_gem_object *obj = intel_fb->obj;
8808
8809         return drm_gem_handle_create(file, &obj->base, handle);
8810 }
8811
8812 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8813         .destroy = intel_user_framebuffer_destroy,
8814         .create_handle = intel_user_framebuffer_create_handle,
8815 };
8816
8817 int intel_framebuffer_init(struct drm_device *dev,
8818                            struct intel_framebuffer *intel_fb,
8819                            struct drm_mode_fb_cmd2 *mode_cmd,
8820                            struct drm_i915_gem_object *obj)
8821 {
8822         int ret;
8823
8824         if (obj->tiling_mode == I915_TILING_Y) {
8825                 DRM_DEBUG("hardware does not support tiling Y\n");
8826                 return -EINVAL;
8827         }
8828
8829         if (mode_cmd->pitches[0] & 63) {
8830                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8831                           mode_cmd->pitches[0]);
8832                 return -EINVAL;
8833         }
8834
8835         /* FIXME <= Gen4 stride limits are bit unclear */
8836         if (mode_cmd->pitches[0] > 32768) {
8837                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8838                           mode_cmd->pitches[0]);
8839                 return -EINVAL;
8840         }
8841
8842         if (obj->tiling_mode != I915_TILING_NONE &&
8843             mode_cmd->pitches[0] != obj->stride) {
8844                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8845                           mode_cmd->pitches[0], obj->stride);
8846                 return -EINVAL;
8847         }
8848
8849         /* Reject formats not supported by any plane early. */
8850         switch (mode_cmd->pixel_format) {
8851         case DRM_FORMAT_C8:
8852         case DRM_FORMAT_RGB565:
8853         case DRM_FORMAT_XRGB8888:
8854         case DRM_FORMAT_ARGB8888:
8855                 break;
8856         case DRM_FORMAT_XRGB1555:
8857         case DRM_FORMAT_ARGB1555:
8858                 if (INTEL_INFO(dev)->gen > 3) {
8859                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8860                         return -EINVAL;
8861                 }
8862                 break;
8863         case DRM_FORMAT_XBGR8888:
8864         case DRM_FORMAT_ABGR8888:
8865         case DRM_FORMAT_XRGB2101010:
8866         case DRM_FORMAT_ARGB2101010:
8867         case DRM_FORMAT_XBGR2101010:
8868         case DRM_FORMAT_ABGR2101010:
8869                 if (INTEL_INFO(dev)->gen < 4) {
8870                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8871                         return -EINVAL;
8872                 }
8873                 break;
8874         case DRM_FORMAT_YUYV:
8875         case DRM_FORMAT_UYVY:
8876         case DRM_FORMAT_YVYU:
8877         case DRM_FORMAT_VYUY:
8878                 if (INTEL_INFO(dev)->gen < 5) {
8879                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8880                         return -EINVAL;
8881                 }
8882                 break;
8883         default:
8884                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8885                 return -EINVAL;
8886         }
8887
8888         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8889         if (mode_cmd->offsets[0] != 0)
8890                 return -EINVAL;
8891
8892         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8893         intel_fb->obj = obj;
8894
8895         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8896         if (ret) {
8897                 DRM_ERROR("framebuffer init failed %d\n", ret);
8898                 return ret;
8899         }
8900
8901         return 0;
8902 }
8903
8904 static struct drm_framebuffer *
8905 intel_user_framebuffer_create(struct drm_device *dev,
8906                               struct drm_file *filp,
8907                               struct drm_mode_fb_cmd2 *mode_cmd)
8908 {
8909         struct drm_i915_gem_object *obj;
8910
8911         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8912                                                 mode_cmd->handles[0]));
8913         if (&obj->base == NULL)
8914                 return ERR_PTR(-ENOENT);
8915
8916         return intel_framebuffer_create(dev, mode_cmd, obj);
8917 }
8918
8919 static const struct drm_mode_config_funcs intel_mode_funcs = {
8920         .fb_create = intel_user_framebuffer_create,
8921         .output_poll_changed = intel_fb_output_poll_changed,
8922 };
8923
8924 /* Set up chip specific display functions */
8925 static void intel_init_display(struct drm_device *dev)
8926 {
8927         struct drm_i915_private *dev_priv = dev->dev_private;
8928
8929         if (HAS_DDI(dev)) {
8930                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8931                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8932                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8933                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8934                 dev_priv->display.off = haswell_crtc_off;
8935                 dev_priv->display.update_plane = ironlake_update_plane;
8936         } else if (HAS_PCH_SPLIT(dev)) {
8937                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8938                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8939                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8940                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8941                 dev_priv->display.off = ironlake_crtc_off;
8942                 dev_priv->display.update_plane = ironlake_update_plane;
8943         } else if (IS_VALLEYVIEW(dev)) {
8944                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8945                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8946                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8947                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8948                 dev_priv->display.off = i9xx_crtc_off;
8949                 dev_priv->display.update_plane = i9xx_update_plane;
8950         } else {
8951                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8952                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8953                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8954                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8955                 dev_priv->display.off = i9xx_crtc_off;
8956                 dev_priv->display.update_plane = i9xx_update_plane;
8957         }
8958
8959         /* Returns the core display clock speed */
8960         if (IS_VALLEYVIEW(dev))
8961                 dev_priv->display.get_display_clock_speed =
8962                         valleyview_get_display_clock_speed;
8963         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8964                 dev_priv->display.get_display_clock_speed =
8965                         i945_get_display_clock_speed;
8966         else if (IS_I915G(dev))
8967                 dev_priv->display.get_display_clock_speed =
8968                         i915_get_display_clock_speed;
8969         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8970                 dev_priv->display.get_display_clock_speed =
8971                         i9xx_misc_get_display_clock_speed;
8972         else if (IS_I915GM(dev))
8973                 dev_priv->display.get_display_clock_speed =
8974                         i915gm_get_display_clock_speed;
8975         else if (IS_I865G(dev))
8976                 dev_priv->display.get_display_clock_speed =
8977                         i865_get_display_clock_speed;
8978         else if (IS_I85X(dev))
8979                 dev_priv->display.get_display_clock_speed =
8980                         i855_get_display_clock_speed;
8981         else /* 852, 830 */
8982                 dev_priv->display.get_display_clock_speed =
8983                         i830_get_display_clock_speed;
8984
8985         if (HAS_PCH_SPLIT(dev)) {
8986                 if (IS_GEN5(dev)) {
8987                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8988                         dev_priv->display.write_eld = ironlake_write_eld;
8989                 } else if (IS_GEN6(dev)) {
8990                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8991                         dev_priv->display.write_eld = ironlake_write_eld;
8992                 } else if (IS_IVYBRIDGE(dev)) {
8993                         /* FIXME: detect B0+ stepping and use auto training */
8994                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8995                         dev_priv->display.write_eld = ironlake_write_eld;
8996                         dev_priv->display.modeset_global_resources =
8997                                 ivb_modeset_global_resources;
8998                 } else if (IS_HASWELL(dev)) {
8999                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9000                         dev_priv->display.write_eld = haswell_write_eld;
9001                         dev_priv->display.modeset_global_resources =
9002                                 haswell_modeset_global_resources;
9003                 }
9004         } else if (IS_G4X(dev)) {
9005                 dev_priv->display.write_eld = g4x_write_eld;
9006         }
9007
9008         /* Default just returns -ENODEV to indicate unsupported */
9009         dev_priv->display.queue_flip = intel_default_queue_flip;
9010
9011         switch (INTEL_INFO(dev)->gen) {
9012         case 2:
9013                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9014                 break;
9015
9016         case 3:
9017                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9018                 break;
9019
9020         case 4:
9021         case 5:
9022                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9023                 break;
9024
9025         case 6:
9026                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9027                 break;
9028         case 7:
9029                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9030                 break;
9031         }
9032 }
9033
9034 /*
9035  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9036  * resume, or other times.  This quirk makes sure that's the case for
9037  * affected systems.
9038  */
9039 static void quirk_pipea_force(struct drm_device *dev)
9040 {
9041         struct drm_i915_private *dev_priv = dev->dev_private;
9042
9043         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9044         DRM_INFO("applying pipe a force quirk\n");
9045 }
9046
9047 /*
9048  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9049  */
9050 static void quirk_ssc_force_disable(struct drm_device *dev)
9051 {
9052         struct drm_i915_private *dev_priv = dev->dev_private;
9053         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9054         DRM_INFO("applying lvds SSC disable quirk\n");
9055 }
9056
9057 /*
9058  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9059  * brightness value
9060  */
9061 static void quirk_invert_brightness(struct drm_device *dev)
9062 {
9063         struct drm_i915_private *dev_priv = dev->dev_private;
9064         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9065         DRM_INFO("applying inverted panel brightness quirk\n");
9066 }
9067
9068 struct intel_quirk {
9069         int device;
9070         int subsystem_vendor;
9071         int subsystem_device;
9072         void (*hook)(struct drm_device *dev);
9073 };
9074
9075 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9076 struct intel_dmi_quirk {
9077         void (*hook)(struct drm_device *dev);
9078         const struct dmi_system_id (*dmi_id_list)[];
9079 };
9080
9081 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9082 {
9083         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9084         return 1;
9085 }
9086
9087 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9088         {
9089                 .dmi_id_list = &(const struct dmi_system_id[]) {
9090                         {
9091                                 .callback = intel_dmi_reverse_brightness,
9092                                 .ident = "NCR Corporation",
9093                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9094                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9095                                 },
9096                         },
9097                         { }  /* terminating entry */
9098                 },
9099                 .hook = quirk_invert_brightness,
9100         },
9101 };
9102
9103 static struct intel_quirk intel_quirks[] = {
9104         /* HP Mini needs pipe A force quirk (LP: #322104) */
9105         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9106
9107         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9108         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9109
9110         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9111         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9112
9113         /* 830/845 need to leave pipe A & dpll A up */
9114         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9115         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9116
9117         /* Lenovo U160 cannot use SSC on LVDS */
9118         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9119
9120         /* Sony Vaio Y cannot use SSC on LVDS */
9121         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9122
9123         /* Acer Aspire 5734Z must invert backlight brightness */
9124         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9125
9126         /* Acer/eMachines G725 */
9127         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9128
9129         /* Acer/eMachines e725 */
9130         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9131
9132         /* Acer/Packard Bell NCL20 */
9133         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9134
9135         /* Acer Aspire 4736Z */
9136         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9137 };
9138
9139 static void intel_init_quirks(struct drm_device *dev)
9140 {
9141         struct pci_dev *d = dev->pdev;
9142         int i;
9143
9144         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9145                 struct intel_quirk *q = &intel_quirks[i];
9146
9147                 if (d->device == q->device &&
9148                     (d->subsystem_vendor == q->subsystem_vendor ||
9149                      q->subsystem_vendor == PCI_ANY_ID) &&
9150                     (d->subsystem_device == q->subsystem_device ||
9151                      q->subsystem_device == PCI_ANY_ID))
9152                         q->hook(dev);
9153         }
9154         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9155                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9156                         intel_dmi_quirks[i].hook(dev);
9157         }
9158 }
9159
9160 /* Disable the VGA plane that we never use */
9161 static void i915_disable_vga(struct drm_device *dev)
9162 {
9163         struct drm_i915_private *dev_priv = dev->dev_private;
9164         u8 sr1;
9165         u32 vga_reg = i915_vgacntrl_reg(dev);
9166
9167         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9168         outb(SR01, VGA_SR_INDEX);
9169         sr1 = inb(VGA_SR_DATA);
9170         outb(sr1 | 1<<5, VGA_SR_DATA);
9171         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9172         udelay(300);
9173
9174         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9175         POSTING_READ(vga_reg);
9176 }
9177
9178 void intel_modeset_init_hw(struct drm_device *dev)
9179 {
9180         intel_init_power_well(dev);
9181
9182         intel_prepare_ddi(dev);
9183
9184         intel_init_clock_gating(dev);
9185
9186         mutex_lock(&dev->struct_mutex);
9187         intel_enable_gt_powersave(dev);
9188         mutex_unlock(&dev->struct_mutex);
9189 }
9190
9191 void intel_modeset_suspend_hw(struct drm_device *dev)
9192 {
9193         intel_suspend_hw(dev);
9194 }
9195
9196 void intel_modeset_init(struct drm_device *dev)
9197 {
9198         struct drm_i915_private *dev_priv = dev->dev_private;
9199         int i, j, ret;
9200
9201         drm_mode_config_init(dev);
9202
9203         dev->mode_config.min_width = 0;
9204         dev->mode_config.min_height = 0;
9205
9206         dev->mode_config.preferred_depth = 24;
9207         dev->mode_config.prefer_shadow = 1;
9208
9209         dev->mode_config.funcs = &intel_mode_funcs;
9210
9211         intel_init_quirks(dev);
9212
9213         intel_init_pm(dev);
9214
9215         if (INTEL_INFO(dev)->num_pipes == 0)
9216                 return;
9217
9218         intel_init_display(dev);
9219
9220         if (IS_GEN2(dev)) {
9221                 dev->mode_config.max_width = 2048;
9222                 dev->mode_config.max_height = 2048;
9223         } else if (IS_GEN3(dev)) {
9224                 dev->mode_config.max_width = 4096;
9225                 dev->mode_config.max_height = 4096;
9226         } else {
9227                 dev->mode_config.max_width = 8192;
9228                 dev->mode_config.max_height = 8192;
9229         }
9230         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9231
9232         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9233                       INTEL_INFO(dev)->num_pipes,
9234                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9235
9236         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9237                 intel_crtc_init(dev, i);
9238                 for (j = 0; j < dev_priv->num_plane; j++) {
9239                         ret = intel_plane_init(dev, i, j);
9240                         if (ret)
9241                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9242                                               pipe_name(i), sprite_name(i, j), ret);
9243                 }
9244         }
9245
9246         intel_cpu_pll_init(dev);
9247         intel_pch_pll_init(dev);
9248
9249         /* Just disable it once at startup */
9250         i915_disable_vga(dev);
9251         intel_setup_outputs(dev);
9252
9253         /* Just in case the BIOS is doing something questionable. */
9254         intel_disable_fbc(dev);
9255 }
9256
9257 static void
9258 intel_connector_break_all_links(struct intel_connector *connector)
9259 {
9260         connector->base.dpms = DRM_MODE_DPMS_OFF;
9261         connector->base.encoder = NULL;
9262         connector->encoder->connectors_active = false;
9263         connector->encoder->base.crtc = NULL;
9264 }
9265
9266 static void intel_enable_pipe_a(struct drm_device *dev)
9267 {
9268         struct intel_connector *connector;
9269         struct drm_connector *crt = NULL;
9270         struct intel_load_detect_pipe load_detect_temp;
9271
9272         /* We can't just switch on the pipe A, we need to set things up with a
9273          * proper mode and output configuration. As a gross hack, enable pipe A
9274          * by enabling the load detect pipe once. */
9275         list_for_each_entry(connector,
9276                             &dev->mode_config.connector_list,
9277                             base.head) {
9278                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9279                         crt = &connector->base;
9280                         break;
9281                 }
9282         }
9283
9284         if (!crt)
9285                 return;
9286
9287         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9288                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9289
9290
9291 }
9292
9293 static bool
9294 intel_check_plane_mapping(struct intel_crtc *crtc)
9295 {
9296         struct drm_device *dev = crtc->base.dev;
9297         struct drm_i915_private *dev_priv = dev->dev_private;
9298         u32 reg, val;
9299
9300         if (INTEL_INFO(dev)->num_pipes == 1)
9301                 return true;
9302
9303         reg = DSPCNTR(!crtc->plane);
9304         val = I915_READ(reg);
9305
9306         if ((val & DISPLAY_PLANE_ENABLE) &&
9307             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9308                 return false;
9309
9310         return true;
9311 }
9312
9313 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9314 {
9315         struct drm_device *dev = crtc->base.dev;
9316         struct drm_i915_private *dev_priv = dev->dev_private;
9317         u32 reg;
9318
9319         /* Clear any frame start delays used for debugging left by the BIOS */
9320         reg = PIPECONF(crtc->config.cpu_transcoder);
9321         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9322
9323         /* We need to sanitize the plane -> pipe mapping first because this will
9324          * disable the crtc (and hence change the state) if it is wrong. Note
9325          * that gen4+ has a fixed plane -> pipe mapping.  */
9326         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9327                 struct intel_connector *connector;
9328                 bool plane;
9329
9330                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9331                               crtc->base.base.id);
9332
9333                 /* Pipe has the wrong plane attached and the plane is active.
9334                  * Temporarily change the plane mapping and disable everything
9335                  * ...  */
9336                 plane = crtc->plane;
9337                 crtc->plane = !plane;
9338                 dev_priv->display.crtc_disable(&crtc->base);
9339                 crtc->plane = plane;
9340
9341                 /* ... and break all links. */
9342                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9343                                     base.head) {
9344                         if (connector->encoder->base.crtc != &crtc->base)
9345                                 continue;
9346
9347                         intel_connector_break_all_links(connector);
9348                 }
9349
9350                 WARN_ON(crtc->active);
9351                 crtc->base.enabled = false;
9352         }
9353
9354         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9355             crtc->pipe == PIPE_A && !crtc->active) {
9356                 /* BIOS forgot to enable pipe A, this mostly happens after
9357                  * resume. Force-enable the pipe to fix this, the update_dpms
9358                  * call below we restore the pipe to the right state, but leave
9359                  * the required bits on. */
9360                 intel_enable_pipe_a(dev);
9361         }
9362
9363         /* Adjust the state of the output pipe according to whether we
9364          * have active connectors/encoders. */
9365         intel_crtc_update_dpms(&crtc->base);
9366
9367         if (crtc->active != crtc->base.enabled) {
9368                 struct intel_encoder *encoder;
9369
9370                 /* This can happen either due to bugs in the get_hw_state
9371                  * functions or because the pipe is force-enabled due to the
9372                  * pipe A quirk. */
9373                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9374                               crtc->base.base.id,
9375                               crtc->base.enabled ? "enabled" : "disabled",
9376                               crtc->active ? "enabled" : "disabled");
9377
9378                 crtc->base.enabled = crtc->active;
9379
9380                 /* Because we only establish the connector -> encoder ->
9381                  * crtc links if something is active, this means the
9382                  * crtc is now deactivated. Break the links. connector
9383                  * -> encoder links are only establish when things are
9384                  *  actually up, hence no need to break them. */
9385                 WARN_ON(crtc->active);
9386
9387                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9388                         WARN_ON(encoder->connectors_active);
9389                         encoder->base.crtc = NULL;
9390                 }
9391         }
9392 }
9393
9394 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9395 {
9396         struct intel_connector *connector;
9397         struct drm_device *dev = encoder->base.dev;
9398
9399         /* We need to check both for a crtc link (meaning that the
9400          * encoder is active and trying to read from a pipe) and the
9401          * pipe itself being active. */
9402         bool has_active_crtc = encoder->base.crtc &&
9403                 to_intel_crtc(encoder->base.crtc)->active;
9404
9405         if (encoder->connectors_active && !has_active_crtc) {
9406                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9407                               encoder->base.base.id,
9408                               drm_get_encoder_name(&encoder->base));
9409
9410                 /* Connector is active, but has no active pipe. This is
9411                  * fallout from our resume register restoring. Disable
9412                  * the encoder manually again. */
9413                 if (encoder->base.crtc) {
9414                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9415                                       encoder->base.base.id,
9416                                       drm_get_encoder_name(&encoder->base));
9417                         encoder->disable(encoder);
9418                 }
9419
9420                 /* Inconsistent output/port/pipe state happens presumably due to
9421                  * a bug in one of the get_hw_state functions. Or someplace else
9422                  * in our code, like the register restore mess on resume. Clamp
9423                  * things to off as a safer default. */
9424                 list_for_each_entry(connector,
9425                                     &dev->mode_config.connector_list,
9426                                     base.head) {
9427                         if (connector->encoder != encoder)
9428                                 continue;
9429
9430                         intel_connector_break_all_links(connector);
9431                 }
9432         }
9433         /* Enabled encoders without active connectors will be fixed in
9434          * the crtc fixup. */
9435 }
9436
9437 void i915_redisable_vga(struct drm_device *dev)
9438 {
9439         struct drm_i915_private *dev_priv = dev->dev_private;
9440         u32 vga_reg = i915_vgacntrl_reg(dev);
9441
9442         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9443                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9444                 i915_disable_vga(dev);
9445         }
9446 }
9447
9448 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9449  * and i915 state tracking structures. */
9450 void intel_modeset_setup_hw_state(struct drm_device *dev,
9451                                   bool force_restore)
9452 {
9453         struct drm_i915_private *dev_priv = dev->dev_private;
9454         enum pipe pipe;
9455         struct drm_plane *plane;
9456         struct intel_crtc *crtc;
9457         struct intel_encoder *encoder;
9458         struct intel_connector *connector;
9459
9460         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9461                             base.head) {
9462                 memset(&crtc->config, 0, sizeof(crtc->config));
9463
9464                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9465                                                                  &crtc->config);
9466
9467                 crtc->base.enabled = crtc->active;
9468
9469                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9470                               crtc->base.base.id,
9471                               crtc->active ? "enabled" : "disabled");
9472         }
9473
9474         if (HAS_DDI(dev))
9475                 intel_ddi_setup_hw_pll_state(dev);
9476
9477         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9478                             base.head) {
9479                 pipe = 0;
9480
9481                 if (encoder->get_hw_state(encoder, &pipe)) {
9482                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9483                         encoder->base.crtc = &crtc->base;
9484                         if (encoder->get_config)
9485                                 encoder->get_config(encoder, &crtc->config);
9486                 } else {
9487                         encoder->base.crtc = NULL;
9488                 }
9489
9490                 encoder->connectors_active = false;
9491                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9492                               encoder->base.base.id,
9493                               drm_get_encoder_name(&encoder->base),
9494                               encoder->base.crtc ? "enabled" : "disabled",
9495                               pipe);
9496         }
9497
9498         list_for_each_entry(connector, &dev->mode_config.connector_list,
9499                             base.head) {
9500                 if (connector->get_hw_state(connector)) {
9501                         connector->base.dpms = DRM_MODE_DPMS_ON;
9502                         connector->encoder->connectors_active = true;
9503                         connector->base.encoder = &connector->encoder->base;
9504                 } else {
9505                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9506                         connector->base.encoder = NULL;
9507                 }
9508                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9509                               connector->base.base.id,
9510                               drm_get_connector_name(&connector->base),
9511                               connector->base.encoder ? "enabled" : "disabled");
9512         }
9513
9514         /* HW state is read out, now we need to sanitize this mess. */
9515         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9516                             base.head) {
9517                 intel_sanitize_encoder(encoder);
9518         }
9519
9520         for_each_pipe(pipe) {
9521                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9522                 intel_sanitize_crtc(crtc);
9523                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9524         }
9525
9526         if (force_restore) {
9527                 /*
9528                  * We need to use raw interfaces for restoring state to avoid
9529                  * checking (bogus) intermediate states.
9530                  */
9531                 for_each_pipe(pipe) {
9532                         struct drm_crtc *crtc =
9533                                 dev_priv->pipe_to_crtc_mapping[pipe];
9534
9535                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9536                                          crtc->fb);
9537                 }
9538                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9539                         intel_plane_restore(plane);
9540
9541                 i915_redisable_vga(dev);
9542         } else {
9543                 intel_modeset_update_staged_output_state(dev);
9544         }
9545
9546         intel_modeset_check_state(dev);
9547
9548         drm_mode_config_reset(dev);
9549 }
9550
9551 void intel_modeset_gem_init(struct drm_device *dev)
9552 {
9553         intel_modeset_init_hw(dev);
9554
9555         intel_setup_overlay(dev);
9556
9557         intel_modeset_setup_hw_state(dev, false);
9558 }
9559
9560 void intel_modeset_cleanup(struct drm_device *dev)
9561 {
9562         struct drm_i915_private *dev_priv = dev->dev_private;
9563         struct drm_crtc *crtc;
9564         struct intel_crtc *intel_crtc;
9565
9566         /*
9567          * Interrupts and polling as the first thing to avoid creating havoc.
9568          * Too much stuff here (turning of rps, connectors, ...) would
9569          * experience fancy races otherwise.
9570          */
9571         drm_irq_uninstall(dev);
9572         cancel_work_sync(&dev_priv->hotplug_work);
9573         /*
9574          * Due to the hpd irq storm handling the hotplug work can re-arm the
9575          * poll handlers. Hence disable polling after hpd handling is shut down.
9576          */
9577         drm_kms_helper_poll_fini(dev);
9578
9579         mutex_lock(&dev->struct_mutex);
9580
9581         intel_unregister_dsm_handler();
9582
9583         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9584                 /* Skip inactive CRTCs */
9585                 if (!crtc->fb)
9586                         continue;
9587
9588                 intel_crtc = to_intel_crtc(crtc);
9589                 intel_increase_pllclock(crtc);
9590         }
9591
9592         intel_disable_fbc(dev);
9593
9594         intel_disable_gt_powersave(dev);
9595
9596         ironlake_teardown_rc6(dev);
9597
9598         mutex_unlock(&dev->struct_mutex);
9599
9600         /* flush any delayed tasks or pending work */
9601         flush_scheduled_work();
9602
9603         /* destroy backlight, if any, before the connectors */
9604         intel_panel_destroy_backlight(dev);
9605
9606         drm_mode_config_cleanup(dev);
9607
9608         intel_cleanup_overlay(dev);
9609 }
9610
9611 /*
9612  * Return which encoder is currently attached for connector.
9613  */
9614 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9615 {
9616         return &intel_attached_encoder(connector)->base;
9617 }
9618
9619 void intel_connector_attach_encoder(struct intel_connector *connector,
9620                                     struct intel_encoder *encoder)
9621 {
9622         connector->encoder = encoder;
9623         drm_mode_connector_attach_encoder(&connector->base,
9624                                           &encoder->base);
9625 }
9626
9627 /*
9628  * set vga decode state - true == enable VGA decode
9629  */
9630 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9631 {
9632         struct drm_i915_private *dev_priv = dev->dev_private;
9633         u16 gmch_ctrl;
9634
9635         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9636         if (state)
9637                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9638         else
9639                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9640         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9641         return 0;
9642 }
9643
9644 #ifdef CONFIG_DEBUG_FS
9645 #include <linux/seq_file.h>
9646
9647 struct intel_display_error_state {
9648
9649         u32 power_well_driver;
9650
9651         struct intel_cursor_error_state {
9652                 u32 control;
9653                 u32 position;
9654                 u32 base;
9655                 u32 size;
9656         } cursor[I915_MAX_PIPES];
9657
9658         struct intel_pipe_error_state {
9659                 enum transcoder cpu_transcoder;
9660                 u32 conf;
9661                 u32 source;
9662
9663                 u32 htotal;
9664                 u32 hblank;
9665                 u32 hsync;
9666                 u32 vtotal;
9667                 u32 vblank;
9668                 u32 vsync;
9669         } pipe[I915_MAX_PIPES];
9670
9671         struct intel_plane_error_state {
9672                 u32 control;
9673                 u32 stride;
9674                 u32 size;
9675                 u32 pos;
9676                 u32 addr;
9677                 u32 surface;
9678                 u32 tile_offset;
9679         } plane[I915_MAX_PIPES];
9680 };
9681
9682 struct intel_display_error_state *
9683 intel_display_capture_error_state(struct drm_device *dev)
9684 {
9685         drm_i915_private_t *dev_priv = dev->dev_private;
9686         struct intel_display_error_state *error;
9687         enum transcoder cpu_transcoder;
9688         int i;
9689
9690         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9691         if (error == NULL)
9692                 return NULL;
9693
9694         if (HAS_POWER_WELL(dev))
9695                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9696
9697         for_each_pipe(i) {
9698                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9699                 error->pipe[i].cpu_transcoder = cpu_transcoder;
9700
9701                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9702                         error->cursor[i].control = I915_READ(CURCNTR(i));
9703                         error->cursor[i].position = I915_READ(CURPOS(i));
9704                         error->cursor[i].base = I915_READ(CURBASE(i));
9705                 } else {
9706                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9707                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9708                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9709                 }
9710
9711                 error->plane[i].control = I915_READ(DSPCNTR(i));
9712                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9713                 if (INTEL_INFO(dev)->gen <= 3) {
9714                         error->plane[i].size = I915_READ(DSPSIZE(i));
9715                         error->plane[i].pos = I915_READ(DSPPOS(i));
9716                 }
9717                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9718                         error->plane[i].addr = I915_READ(DSPADDR(i));
9719                 if (INTEL_INFO(dev)->gen >= 4) {
9720                         error->plane[i].surface = I915_READ(DSPSURF(i));
9721                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9722                 }
9723
9724                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9725                 error->pipe[i].source = I915_READ(PIPESRC(i));
9726                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9727                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9728                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9729                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9730                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9731                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9732         }
9733
9734         /* In the code above we read the registers without checking if the power
9735          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9736          * prevent the next I915_WRITE from detecting it and printing an error
9737          * message. */
9738         if (HAS_POWER_WELL(dev))
9739                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9740
9741         return error;
9742 }
9743
9744 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9745
9746 void
9747 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9748                                 struct drm_device *dev,
9749                                 struct intel_display_error_state *error)
9750 {
9751         int i;
9752
9753         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9754         if (HAS_POWER_WELL(dev))
9755                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9756                            error->power_well_driver);
9757         for_each_pipe(i) {
9758                 err_printf(m, "Pipe [%d]:\n", i);
9759                 err_printf(m, "  CPU transcoder: %c\n",
9760                            transcoder_name(error->pipe[i].cpu_transcoder));
9761                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9762                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9763                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9764                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9765                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9766                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9767                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9768                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9769
9770                 err_printf(m, "Plane [%d]:\n", i);
9771                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9772                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9773                 if (INTEL_INFO(dev)->gen <= 3) {
9774                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9775                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
9776                 }
9777                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9778                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9779                 if (INTEL_INFO(dev)->gen >= 4) {
9780                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9781                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9782                 }
9783
9784                 err_printf(m, "Cursor [%d]:\n", i);
9785                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9786                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
9787                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9788         }
9789 }
9790 #endif