2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __RV770_DPM_H__
24 #define __RV770_DPM_H__
26 #include "rv770_smc.h"
28 struct rv770_clock_registers {
29 u32 cg_spll_func_cntl;
30 u32 cg_spll_func_cntl_2;
31 u32 cg_spll_func_cntl_3;
32 u32 cg_spll_spread_spectrum;
33 u32 cg_spll_spread_spectrum_2;
34 u32 mpll_ad_func_cntl;
35 u32 mpll_ad_func_cntl_2;
36 u32 mpll_dq_func_cntl;
37 u32 mpll_dq_func_cntl_2;
44 struct rv730_clock_registers {
45 u32 cg_spll_func_cntl;
46 u32 cg_spll_func_cntl_2;
47 u32 cg_spll_func_cntl_3;
48 u32 cg_spll_spread_spectrum;
49 u32 cg_spll_spread_spectrum_2;
59 union r7xx_clock_registers {
60 struct rv770_clock_registers rv770;
61 struct rv730_clock_registers rv730;
64 struct vddc_table_entry {
71 #define MAX_NO_OF_MVDD_VALUES 2
72 #define MAX_NO_VREG_STEPS 32
74 struct rv7xx_power_info {
78 bool dynamic_pcie_gen2;
81 bool voltage_control; /* vddc */
86 bool gfx_clock_gating;
90 bool thermal_protection;
95 union r7xx_clock_registers clk_regs;
96 u32 s0_vid_lower_smio_cntl;
100 u32 mvdd_split_frequency;
101 u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES];
103 u16 max_vddc_in_table;
104 u16 min_vddc_in_table;
105 struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS];
106 u8 valid_vddc_entries;
108 u32 mclk_odt_threshold;
115 u32 active_auto_throttle_sources;
116 u32 mclk_stutter_mode_threshold;
117 u32 mclk_strobe_mode_threshold;
118 u32 mclk_edc_enable_threshold;
128 u32 restricted_levels;
134 u16 state_table_start;
137 /* scratch structs */
138 RV770_SMC_STATETABLE smc_statetable;
145 u16 vddci; /* eg+ only */
150 struct rv7xx_pl high;
151 struct rv7xx_pl medium;
156 #define RV770_RLP_DFLT 10
157 #define RV770_RMP_DFLT 25
158 #define RV770_LHP_DFLT 25
159 #define RV770_LMP_DFLT 10
160 #define RV770_VRC_DFLT 0x003f
161 #define RV770_ASI_DFLT 1000
162 #define RV770_HASI_DFLT 200000
163 #define RV770_MGCGTTLOCAL0_DFLT 0x00100000
164 #define RV7XX_MGCGTTLOCAL0_DFLT 0
165 #define RV770_MGCGTTLOCAL1_DFLT 0xFFFF0000
166 #define RV770_MGCGCGTSSMCTRL_DFLT 0x55940000
168 #define MVDD_LOW_INDEX 0
169 #define MVDD_HIGH_INDEX 1
171 #define MVDD_LOW_VALUE 0
172 #define MVDD_HIGH_VALUE 0xffff
174 #define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */
175 #define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */
178 int rv730_populate_sclk_value(struct radeon_device *rdev,
180 RV770_SMC_SCLK_VALUE *sclk);
181 int rv730_populate_mclk_value(struct radeon_device *rdev,
182 u32 engine_clock, u32 memory_clock,
183 LPRV7XX_SMC_MCLK_VALUE mclk);
184 void rv730_read_clock_registers(struct radeon_device *rdev);
185 int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
186 RV770_SMC_STATETABLE *table);
187 int rv730_populate_smc_initial_state(struct radeon_device *rdev,
188 struct radeon_ps *radeon_initial_state,
189 RV770_SMC_STATETABLE *table);
190 void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
191 struct radeon_ps *radeon_state);
192 void rv730_power_gating_enable(struct radeon_device *rdev,
194 void rv730_start_dpm(struct radeon_device *rdev);
195 void rv730_stop_dpm(struct radeon_device *rdev);
196 void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt);
197 void rv730_get_odt_values(struct radeon_device *rdev);
200 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
201 RV770_SMC_SCLK_VALUE *sclk);
202 int rv740_populate_mclk_value(struct radeon_device *rdev,
203 u32 engine_clock, u32 memory_clock,
204 RV7XX_SMC_MCLK_VALUE *mclk);
205 void rv740_read_clock_registers(struct radeon_device *rdev);
206 int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
207 RV770_SMC_STATETABLE *table);
208 void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
210 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
211 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
212 u32 rv740_get_decoded_reference_divider(u32 encoded_ref);
215 u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf);
216 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
217 RV770_SMC_VOLTAGE_VALUE *voltage);
218 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
219 RV770_SMC_VOLTAGE_VALUE *voltage);
220 u8 rv770_get_seq_value(struct radeon_device *rdev,
221 struct rv7xx_pl *pl);
222 int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
223 RV770_SMC_VOLTAGE_VALUE *voltage);
224 u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
226 void rv770_program_response_times(struct radeon_device *rdev);
227 int rv770_populate_smc_sp(struct radeon_device *rdev,
228 struct radeon_ps *radeon_state,
229 RV770_SMC_SWSTATE *smc_state);
230 int rv770_populate_smc_t(struct radeon_device *rdev,
231 struct radeon_ps *radeon_state,
232 RV770_SMC_SWSTATE *smc_state);
233 void rv770_read_voltage_smio_registers(struct radeon_device *rdev);
234 void rv770_get_memory_type(struct radeon_device *rdev);
235 void r7xx_start_smc(struct radeon_device *rdev);
236 u8 rv770_get_memory_module_index(struct radeon_device *rdev);
237 void rv770_get_max_vddc(struct radeon_device *rdev);
238 void rv770_get_pcie_gen2_status(struct radeon_device *rdev);
239 void rv770_enable_acpi_pm(struct radeon_device *rdev);
240 void rv770_restore_cgcg(struct radeon_device *rdev);
241 bool rv770_dpm_enabled(struct radeon_device *rdev);
242 void rv770_enable_voltage_control(struct radeon_device *rdev,
244 void rv770_enable_backbias(struct radeon_device *rdev,
246 void rv770_enable_thermal_protection(struct radeon_device *rdev,
248 void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
249 enum radeon_dpm_auto_throttle_src source,
251 void rv770_setup_bsp(struct radeon_device *rdev);
252 void rv770_program_git(struct radeon_device *rdev);
253 void rv770_program_tp(struct radeon_device *rdev);
254 void rv770_program_tpp(struct radeon_device *rdev);
255 void rv770_program_sstp(struct radeon_device *rdev);
256 void rv770_program_engine_speed_parameters(struct radeon_device *rdev);
257 void rv770_program_vc(struct radeon_device *rdev);
258 void rv770_clear_vc(struct radeon_device *rdev);
259 int rv770_upload_firmware(struct radeon_device *rdev);
260 void rv770_stop_dpm(struct radeon_device *rdev);
261 void r7xx_stop_smc(struct radeon_device *rdev);
262 void rv770_reset_smio_status(struct radeon_device *rdev);
263 int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
264 int rv770_unrestrict_performance_levels_after_switch(struct radeon_device *rdev);
265 int rv770_halt_smc(struct radeon_device *rdev);
266 int rv770_resume_smc(struct radeon_device *rdev);
267 int rv770_set_sw_state(struct radeon_device *rdev);
268 int rv770_set_boot_state(struct radeon_device *rdev);
269 int rv7xx_parse_power_table(struct radeon_device *rdev);
270 void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
271 struct radeon_ps *new_ps,
272 struct radeon_ps *old_ps);
273 void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
274 struct radeon_ps *new_ps,
275 struct radeon_ps *old_ps);
278 int rv770_read_smc_soft_register(struct radeon_device *rdev,
279 u16 reg_offset, u32 *value);
280 int rv770_write_smc_soft_register(struct radeon_device *rdev,
281 u16 reg_offset, u32 value);
284 int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
285 int min_temp, int max_temp);