drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139
 140 /* helper to disable agp */
 141 /**
 142  * radeon_agp_disable - AGP disable helper function
 143  *
 144  * @rdev: radeon device pointer
 145  *
 146  * Removes AGP flags and changes the gart callbacks on AGP
 147  * cards when using the internal gart rather than AGP (all asics).
 148  */
 149 void radeon_agp_disable(struct radeon_device *rdev)
 150 {
 151         rdev->flags &= ~RADEON_IS_AGP;
 152         if (rdev->family >= CHIP_R600) {
 153                 DRM_INFO("Forcing AGP to PCIE mode\n");
 154                 rdev->flags |= RADEON_IS_PCIE;
 155         } else if (rdev->family >= CHIP_RV515 ||
 156                         rdev->family == CHIP_RV380 ||
 157                         rdev->family == CHIP_RV410 ||
 158                         rdev->family == CHIP_R423) {
 159                 DRM_INFO("Forcing AGP to PCIE mode\n");
 160                 rdev->flags |= RADEON_IS_PCIE;
 161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 162                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 163         } else {
 164                 DRM_INFO("Forcing AGP to PCI mode\n");
 165                 rdev->flags |= RADEON_IS_PCI;
 166                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 167                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 168         }
 169         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 170 }
 171
 172 /*
 173  * ASIC
 174  */
 175 static struct radeon_asic r100_asic = {
 176         .init = &r100_init,
 177         .fini = &r100_fini,
 178         .suspend = &r100_suspend,
 179         .resume = &r100_resume,
 180         .vga_set_state = &r100_vga_set_state,
 181         .asic_reset = &r100_asic_reset,
 182         .ioctl_wait_idle = NULL,
 183         .gui_idle = &r100_gui_idle,
 184         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 185         .gart = {
 186                 .tlb_flush = &r100_pci_gart_tlb_flush,
 187                 .set_page = &r100_pci_gart_set_page,
 188         },
 189         .ring = {
 190                 [RADEON_RING_TYPE_GFX_INDEX] = {
 191                         .ib_execute = &r100_ring_ib_execute,
 192                         .emit_fence = &r100_fence_ring_emit,
 193                         .emit_semaphore = &r100_semaphore_ring_emit,
 194                         .cs_parse = &r100_cs_parse,
 195                         .ring_start = &r100_ring_start,
 196                         .ring_test = &r100_ring_test,
 197                         .ib_test = &r100_ib_test,
 198                         .is_lockup = &r100_gpu_is_lockup,
 199                         .get_rptr = &radeon_ring_generic_get_rptr,
 200                         .get_wptr = &radeon_ring_generic_get_wptr,
 201                         .set_wptr = &radeon_ring_generic_set_wptr,
 202                 }
 203         },
 204         .irq = {
 205                 .set = &r100_irq_set,
 206                 .process = &r100_irq_process,
 207         },
 208         .display = {
 209                 .bandwidth_update = &r100_bandwidth_update,
 210                 .get_vblank_counter = &r100_get_vblank_counter,
 211                 .wait_for_vblank = &r100_wait_for_vblank,
 212                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 213                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 214         },
 215         .copy = {
 216                 .blit = &r100_copy_blit,
 217                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 218                 .dma = NULL,
 219                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 220                 .copy = &r100_copy_blit,
 221                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 222         },
 223         .surface = {
 224                 .set_reg = r100_set_surface_reg,
 225                 .clear_reg = r100_clear_surface_reg,
 226         },
 227         .hpd = {
 228                 .init = &r100_hpd_init,
 229                 .fini = &r100_hpd_fini,
 230                 .sense = &r100_hpd_sense,
 231                 .set_polarity = &r100_hpd_set_polarity,
 232         },
 233         .pm = {
 234                 .misc = &r100_pm_misc,
 235                 .prepare = &r100_pm_prepare,
 236                 .finish = &r100_pm_finish,
 237                 .init_profile = &r100_pm_init_profile,
 238                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 239                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 240                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 241                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 242                 .set_memory_clock = NULL,
 243                 .get_pcie_lanes = NULL,
 244                 .set_pcie_lanes = NULL,
 245                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 246         },
 247         .pflip = {
 248                 .pre_page_flip = &r100_pre_page_flip,
 249                 .page_flip = &r100_page_flip,
 250                 .post_page_flip = &r100_post_page_flip,
 251         },
 252 };
 253
 254 static struct radeon_asic r200_asic = {
 255         .init = &r100_init,
 256         .fini = &r100_fini,
 257         .suspend = &r100_suspend,
 258         .resume = &r100_resume,
 259         .vga_set_state = &r100_vga_set_state,
 260         .asic_reset = &r100_asic_reset,
 261         .ioctl_wait_idle = NULL,
 262         .gui_idle = &r100_gui_idle,
 263         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 264         .gart = {
 265                 .tlb_flush = &r100_pci_gart_tlb_flush,
 266                 .set_page = &r100_pci_gart_set_page,
 267         },
 268         .ring = {
 269                 [RADEON_RING_TYPE_GFX_INDEX] = {
 270                         .ib_execute = &r100_ring_ib_execute,
 271                         .emit_fence = &r100_fence_ring_emit,
 272                         .emit_semaphore = &r100_semaphore_ring_emit,
 273                         .cs_parse = &r100_cs_parse,
 274                         .ring_start = &r100_ring_start,
 275                         .ring_test = &r100_ring_test,
 276                         .ib_test = &r100_ib_test,
 277                         .is_lockup = &r100_gpu_is_lockup,
 278                         .get_rptr = &radeon_ring_generic_get_rptr,
 279                         .get_wptr = &radeon_ring_generic_get_wptr,
 280                         .set_wptr = &radeon_ring_generic_set_wptr,
 281                 }
 282         },
 283         .irq = {
 284                 .set = &r100_irq_set,
 285                 .process = &r100_irq_process,
 286         },
 287         .display = {
 288                 .bandwidth_update = &r100_bandwidth_update,
 289                 .get_vblank_counter = &r100_get_vblank_counter,
 290                 .wait_for_vblank = &r100_wait_for_vblank,
 291                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 292                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 293         },
 294         .copy = {
 295                 .blit = &r100_copy_blit,
 296                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 297                 .dma = &r200_copy_dma,
 298                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 299                 .copy = &r100_copy_blit,
 300                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 301         },
 302         .surface = {
 303                 .set_reg = r100_set_surface_reg,
 304                 .clear_reg = r100_clear_surface_reg,
 305         },
 306         .hpd = {
 307                 .init = &r100_hpd_init,
 308                 .fini = &r100_hpd_fini,
 309                 .sense = &r100_hpd_sense,
 310                 .set_polarity = &r100_hpd_set_polarity,
 311         },
 312         .pm = {
 313                 .misc = &r100_pm_misc,
 314                 .prepare = &r100_pm_prepare,
 315                 .finish = &r100_pm_finish,
 316                 .init_profile = &r100_pm_init_profile,
 317                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 318                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 319                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 320                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 321                 .set_memory_clock = NULL,
 322                 .get_pcie_lanes = NULL,
 323                 .set_pcie_lanes = NULL,
 324                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 325         },
 326         .pflip = {
 327                 .pre_page_flip = &r100_pre_page_flip,
 328                 .page_flip = &r100_page_flip,
 329                 .post_page_flip = &r100_post_page_flip,
 330         },
 331 };
 332
 333 static struct radeon_asic r300_asic = {
 334         .init = &r300_init,
 335         .fini = &r300_fini,
 336         .suspend = &r300_suspend,
 337         .resume = &r300_resume,
 338         .vga_set_state = &r100_vga_set_state,
 339         .asic_reset = &r300_asic_reset,
 340         .ioctl_wait_idle = NULL,
 341         .gui_idle = &r100_gui_idle,
 342         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 343         .gart = {
 344                 .tlb_flush = &r100_pci_gart_tlb_flush,
 345                 .set_page = &r100_pci_gart_set_page,
 346         },
 347         .ring = {
 348                 [RADEON_RING_TYPE_GFX_INDEX] = {
 349                         .ib_execute = &r100_ring_ib_execute,
 350                         .emit_fence = &r300_fence_ring_emit,
 351                         .emit_semaphore = &r100_semaphore_ring_emit,
 352                         .cs_parse = &r300_cs_parse,
 353                         .ring_start = &r300_ring_start,
 354                         .ring_test = &r100_ring_test,
 355                         .ib_test = &r100_ib_test,
 356                         .is_lockup = &r100_gpu_is_lockup,
 357                         .get_rptr = &radeon_ring_generic_get_rptr,
 358                         .get_wptr = &radeon_ring_generic_get_wptr,
 359                         .set_wptr = &radeon_ring_generic_set_wptr,
 360                 }
 361         },
 362         .irq = {
 363                 .set = &r100_irq_set,
 364                 .process = &r100_irq_process,
 365         },
 366         .display = {
 367                 .bandwidth_update = &r100_bandwidth_update,
 368                 .get_vblank_counter = &r100_get_vblank_counter,
 369                 .wait_for_vblank = &r100_wait_for_vblank,
 370                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 371                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 372         },
 373         .copy = {
 374                 .blit = &r100_copy_blit,
 375                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 376                 .dma = &r200_copy_dma,
 377                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 378                 .copy = &r100_copy_blit,
 379                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 380         },
 381         .surface = {
 382                 .set_reg = r100_set_surface_reg,
 383                 .clear_reg = r100_clear_surface_reg,
 384         },
 385         .hpd = {
 386                 .init = &r100_hpd_init,
 387                 .fini = &r100_hpd_fini,
 388                 .sense = &r100_hpd_sense,
 389                 .set_polarity = &r100_hpd_set_polarity,
 390         },
 391         .pm = {
 392                 .misc = &r100_pm_misc,
 393                 .prepare = &r100_pm_prepare,
 394                 .finish = &r100_pm_finish,
 395                 .init_profile = &r100_pm_init_profile,
 396                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 397                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 398                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 399                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 400                 .set_memory_clock = NULL,
 401                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 402                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 403                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 404         },
 405         .pflip = {
 406                 .pre_page_flip = &r100_pre_page_flip,
 407                 .page_flip = &r100_page_flip,
 408                 .post_page_flip = &r100_post_page_flip,
 409         },
 410 };
 411
 412 static struct radeon_asic r300_asic_pcie = {
 413         .init = &r300_init,
 414         .fini = &r300_fini,
 415         .suspend = &r300_suspend,
 416         .resume = &r300_resume,
 417         .vga_set_state = &r100_vga_set_state,
 418         .asic_reset = &r300_asic_reset,
 419         .ioctl_wait_idle = NULL,
 420         .gui_idle = &r100_gui_idle,
 421         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 422         .gart = {
 423                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 424                 .set_page = &rv370_pcie_gart_set_page,
 425         },
 426         .ring = {
 427                 [RADEON_RING_TYPE_GFX_INDEX] = {
 428                         .ib_execute = &r100_ring_ib_execute,
 429                         .emit_fence = &r300_fence_ring_emit,
 430                         .emit_semaphore = &r100_semaphore_ring_emit,
 431                         .cs_parse = &r300_cs_parse,
 432                         .ring_start = &r300_ring_start,
 433                         .ring_test = &r100_ring_test,
 434                         .ib_test = &r100_ib_test,
 435                         .is_lockup = &r100_gpu_is_lockup,
 436                         .get_rptr = &radeon_ring_generic_get_rptr,
 437                         .get_wptr = &radeon_ring_generic_get_wptr,
 438                         .set_wptr = &radeon_ring_generic_set_wptr,
 439                 }
 440         },
 441         .irq = {
 442                 .set = &r100_irq_set,
 443                 .process = &r100_irq_process,
 444         },
 445         .display = {
 446                 .bandwidth_update = &r100_bandwidth_update,
 447                 .get_vblank_counter = &r100_get_vblank_counter,
 448                 .wait_for_vblank = &r100_wait_for_vblank,
 449                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 450                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 451         },
 452         .copy = {
 453                 .blit = &r100_copy_blit,
 454                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 455                 .dma = &r200_copy_dma,
 456                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 457                 .copy = &r100_copy_blit,
 458                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 459         },
 460         .surface = {
 461                 .set_reg = r100_set_surface_reg,
 462                 .clear_reg = r100_clear_surface_reg,
 463         },
 464         .hpd = {
 465                 .init = &r100_hpd_init,
 466                 .fini = &r100_hpd_fini,
 467                 .sense = &r100_hpd_sense,
 468                 .set_polarity = &r100_hpd_set_polarity,
 469         },
 470         .pm = {
 471                 .misc = &r100_pm_misc,
 472                 .prepare = &r100_pm_prepare,
 473                 .finish = &r100_pm_finish,
 474                 .init_profile = &r100_pm_init_profile,
 475                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 476                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 477                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 478                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 479                 .set_memory_clock = NULL,
 480                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 481                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 482                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 483         },
 484         .pflip = {
 485                 .pre_page_flip = &r100_pre_page_flip,
 486                 .page_flip = &r100_page_flip,
 487                 .post_page_flip = &r100_post_page_flip,
 488         },
 489 };
 490
 491 static struct radeon_asic r420_asic = {
 492         .init = &r420_init,
 493         .fini = &r420_fini,
 494         .suspend = &r420_suspend,
 495         .resume = &r420_resume,
 496         .vga_set_state = &r100_vga_set_state,
 497         .asic_reset = &r300_asic_reset,
 498         .ioctl_wait_idle = NULL,
 499         .gui_idle = &r100_gui_idle,
 500         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 501         .gart = {
 502                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 503                 .set_page = &rv370_pcie_gart_set_page,
 504         },
 505         .ring = {
 506                 [RADEON_RING_TYPE_GFX_INDEX] = {
 507                         .ib_execute = &r100_ring_ib_execute,
 508                         .emit_fence = &r300_fence_ring_emit,
 509                         .emit_semaphore = &r100_semaphore_ring_emit,
 510                         .cs_parse = &r300_cs_parse,
 511                         .ring_start = &r300_ring_start,
 512                         .ring_test = &r100_ring_test,
 513                         .ib_test = &r100_ib_test,
 514                         .is_lockup = &r100_gpu_is_lockup,
 515                         .get_rptr = &radeon_ring_generic_get_rptr,
 516                         .get_wptr = &radeon_ring_generic_get_wptr,
 517                         .set_wptr = &radeon_ring_generic_set_wptr,
 518                 }
 519         },
 520         .irq = {
 521                 .set = &r100_irq_set,
 522                 .process = &r100_irq_process,
 523         },
 524         .display = {
 525                 .bandwidth_update = &r100_bandwidth_update,
 526                 .get_vblank_counter = &r100_get_vblank_counter,
 527                 .wait_for_vblank = &r100_wait_for_vblank,
 528                 .set_backlight_level = &atombios_set_backlight_level,
 529                 .get_backlight_level = &atombios_get_backlight_level,
 530         },
 531         .copy = {
 532                 .blit = &r100_copy_blit,
 533                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 534                 .dma = &r200_copy_dma,
 535                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 536                 .copy = &r100_copy_blit,
 537                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 538         },
 539         .surface = {
 540                 .set_reg = r100_set_surface_reg,
 541                 .clear_reg = r100_clear_surface_reg,
 542         },
 543         .hpd = {
 544                 .init = &r100_hpd_init,
 545                 .fini = &r100_hpd_fini,
 546                 .sense = &r100_hpd_sense,
 547                 .set_polarity = &r100_hpd_set_polarity,
 548         },
 549         .pm = {
 550                 .misc = &r100_pm_misc,
 551                 .prepare = &r100_pm_prepare,
 552                 .finish = &r100_pm_finish,
 553                 .init_profile = &r420_pm_init_profile,
 554                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 555                 .get_engine_clock = &radeon_atom_get_engine_clock,
 556                 .set_engine_clock = &radeon_atom_set_engine_clock,
 557                 .get_memory_clock = &radeon_atom_get_memory_clock,
 558                 .set_memory_clock = &radeon_atom_set_memory_clock,
 559                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 560                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 561                 .set_clock_gating = &radeon_atom_set_clock_gating,
 562         },
 563         .pflip = {
 564                 .pre_page_flip = &r100_pre_page_flip,
 565                 .page_flip = &r100_page_flip,
 566                 .post_page_flip = &r100_post_page_flip,
 567         },
 568 };
 569
 570 static struct radeon_asic rs400_asic = {
 571         .init = &rs400_init,
 572         .fini = &rs400_fini,
 573         .suspend = &rs400_suspend,
 574         .resume = &rs400_resume,
 575         .vga_set_state = &r100_vga_set_state,
 576         .asic_reset = &r300_asic_reset,
 577         .ioctl_wait_idle = NULL,
 578         .gui_idle = &r100_gui_idle,
 579         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 580         .gart = {
 581                 .tlb_flush = &rs400_gart_tlb_flush,
 582                 .set_page = &rs400_gart_set_page,
 583         },
 584         .ring = {
 585                 [RADEON_RING_TYPE_GFX_INDEX] = {
 586                         .ib_execute = &r100_ring_ib_execute,
 587                         .emit_fence = &r300_fence_ring_emit,
 588                         .emit_semaphore = &r100_semaphore_ring_emit,
 589                         .cs_parse = &r300_cs_parse,
 590                         .ring_start = &r300_ring_start,
 591                         .ring_test = &r100_ring_test,
 592                         .ib_test = &r100_ib_test,
 593                         .is_lockup = &r100_gpu_is_lockup,
 594                         .get_rptr = &radeon_ring_generic_get_rptr,
 595                         .get_wptr = &radeon_ring_generic_get_wptr,
 596                         .set_wptr = &radeon_ring_generic_set_wptr,
 597                 }
 598         },
 599         .irq = {
 600                 .set = &r100_irq_set,
 601                 .process = &r100_irq_process,
 602         },
 603         .display = {
 604                 .bandwidth_update = &r100_bandwidth_update,
 605                 .get_vblank_counter = &r100_get_vblank_counter,
 606                 .wait_for_vblank = &r100_wait_for_vblank,
 607                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 608                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 609         },
 610         .copy = {
 611                 .blit = &r100_copy_blit,
 612                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 613                 .dma = &r200_copy_dma,
 614                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 615                 .copy = &r100_copy_blit,
 616                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 617         },
 618         .surface = {
 619                 .set_reg = r100_set_surface_reg,
 620                 .clear_reg = r100_clear_surface_reg,
 621         },
 622         .hpd = {
 623                 .init = &r100_hpd_init,
 624                 .fini = &r100_hpd_fini,
 625                 .sense = &r100_hpd_sense,
 626                 .set_polarity = &r100_hpd_set_polarity,
 627         },
 628         .pm = {
 629                 .misc = &r100_pm_misc,
 630                 .prepare = &r100_pm_prepare,
 631                 .finish = &r100_pm_finish,
 632                 .init_profile = &r100_pm_init_profile,
 633                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 634                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 635                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 636                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 637                 .set_memory_clock = NULL,
 638                 .get_pcie_lanes = NULL,
 639                 .set_pcie_lanes = NULL,
 640                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 641         },
 642         .pflip = {
 643                 .pre_page_flip = &r100_pre_page_flip,
 644                 .page_flip = &r100_page_flip,
 645                 .post_page_flip = &r100_post_page_flip,
 646         },
 647 };
 648
 649 static struct radeon_asic rs600_asic = {
 650         .init = &rs600_init,
 651         .fini = &rs600_fini,
 652         .suspend = &rs600_suspend,
 653         .resume = &rs600_resume,
 654         .vga_set_state = &r100_vga_set_state,
 655         .asic_reset = &rs600_asic_reset,
 656         .ioctl_wait_idle = NULL,
 657         .gui_idle = &r100_gui_idle,
 658         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 659         .gart = {
 660                 .tlb_flush = &rs600_gart_tlb_flush,
 661                 .set_page = &rs600_gart_set_page,
 662         },
 663         .ring = {
 664                 [RADEON_RING_TYPE_GFX_INDEX] = {
 665                         .ib_execute = &r100_ring_ib_execute,
 666                         .emit_fence = &r300_fence_ring_emit,
 667                         .emit_semaphore = &r100_semaphore_ring_emit,
 668                         .cs_parse = &r300_cs_parse,
 669                         .ring_start = &r300_ring_start,
 670                         .ring_test = &r100_ring_test,
 671                         .ib_test = &r100_ib_test,
 672                         .is_lockup = &r100_gpu_is_lockup,
 673                         .get_rptr = &radeon_ring_generic_get_rptr,
 674                         .get_wptr = &radeon_ring_generic_get_wptr,
 675                         .set_wptr = &radeon_ring_generic_set_wptr,
 676                 }
 677         },
 678         .irq = {
 679                 .set = &rs600_irq_set,
 680                 .process = &rs600_irq_process,
 681         },
 682         .display = {
 683                 .bandwidth_update = &rs600_bandwidth_update,
 684                 .get_vblank_counter = &rs600_get_vblank_counter,
 685                 .wait_for_vblank = &avivo_wait_for_vblank,
 686                 .set_backlight_level = &atombios_set_backlight_level,
 687                 .get_backlight_level = &atombios_get_backlight_level,
 688                 .hdmi_enable = &r600_hdmi_enable,
 689                 .hdmi_setmode = &r600_hdmi_setmode,
 690         },
 691         .copy = {
 692                 .blit = &r100_copy_blit,
 693                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 694                 .dma = &r200_copy_dma,
 695                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 696                 .copy = &r100_copy_blit,
 697                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 698         },
 699         .surface = {
 700                 .set_reg = r100_set_surface_reg,
 701                 .clear_reg = r100_clear_surface_reg,
 702         },
 703         .hpd = {
 704                 .init = &rs600_hpd_init,
 705                 .fini = &rs600_hpd_fini,
 706                 .sense = &rs600_hpd_sense,
 707                 .set_polarity = &rs600_hpd_set_polarity,
 708         },
 709         .pm = {
 710                 .misc = &rs600_pm_misc,
 711                 .prepare = &rs600_pm_prepare,
 712                 .finish = &rs600_pm_finish,
 713                 .init_profile = &r420_pm_init_profile,
 714                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 715                 .get_engine_clock = &radeon_atom_get_engine_clock,
 716                 .set_engine_clock = &radeon_atom_set_engine_clock,
 717                 .get_memory_clock = &radeon_atom_get_memory_clock,
 718                 .set_memory_clock = &radeon_atom_set_memory_clock,
 719                 .get_pcie_lanes = NULL,
 720                 .set_pcie_lanes = NULL,
 721                 .set_clock_gating = &radeon_atom_set_clock_gating,
 722         },
 723         .pflip = {
 724                 .pre_page_flip = &rs600_pre_page_flip,
 725                 .page_flip = &rs600_page_flip,
 726                 .post_page_flip = &rs600_post_page_flip,
 727         },
 728 };
 729
 730 static struct radeon_asic rs690_asic = {
 731         .init = &rs690_init,
 732         .fini = &rs690_fini,
 733         .suspend = &rs690_suspend,
 734         .resume = &rs690_resume,
 735         .vga_set_state = &r100_vga_set_state,
 736         .asic_reset = &rs600_asic_reset,
 737         .ioctl_wait_idle = NULL,
 738         .gui_idle = &r100_gui_idle,
 739         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 740         .gart = {
 741                 .tlb_flush = &rs400_gart_tlb_flush,
 742                 .set_page = &rs400_gart_set_page,
 743         },
 744         .ring = {
 745                 [RADEON_RING_TYPE_GFX_INDEX] = {
 746                         .ib_execute = &r100_ring_ib_execute,
 747                         .emit_fence = &r300_fence_ring_emit,
 748                         .emit_semaphore = &r100_semaphore_ring_emit,
 749                         .cs_parse = &r300_cs_parse,
 750                         .ring_start = &r300_ring_start,
 751                         .ring_test = &r100_ring_test,
 752                         .ib_test = &r100_ib_test,
 753                         .is_lockup = &r100_gpu_is_lockup,
 754                         .get_rptr = &radeon_ring_generic_get_rptr,
 755                         .get_wptr = &radeon_ring_generic_get_wptr,
 756                         .set_wptr = &radeon_ring_generic_set_wptr,
 757                 }
 758         },
 759         .irq = {
 760                 .set = &rs600_irq_set,
 761                 .process = &rs600_irq_process,
 762         },
 763         .display = {
 764                 .get_vblank_counter = &rs600_get_vblank_counter,
 765                 .bandwidth_update = &rs690_bandwidth_update,
 766                 .wait_for_vblank = &avivo_wait_for_vblank,
 767                 .set_backlight_level = &atombios_set_backlight_level,
 768                 .get_backlight_level = &atombios_get_backlight_level,
 769                 .hdmi_enable = &r600_hdmi_enable,
 770                 .hdmi_setmode = &r600_hdmi_setmode,
 771         },
 772         .copy = {
 773                 .blit = &r100_copy_blit,
 774                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 775                 .dma = &r200_copy_dma,
 776                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 777                 .copy = &r200_copy_dma,
 778                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 779         },
 780         .surface = {
 781                 .set_reg = r100_set_surface_reg,
 782                 .clear_reg = r100_clear_surface_reg,
 783         },
 784         .hpd = {
 785                 .init = &rs600_hpd_init,
 786                 .fini = &rs600_hpd_fini,
 787                 .sense = &rs600_hpd_sense,
 788                 .set_polarity = &rs600_hpd_set_polarity,
 789         },
 790         .pm = {
 791                 .misc = &rs600_pm_misc,
 792                 .prepare = &rs600_pm_prepare,
 793                 .finish = &rs600_pm_finish,
 794                 .init_profile = &r420_pm_init_profile,
 795                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 796                 .get_engine_clock = &radeon_atom_get_engine_clock,
 797                 .set_engine_clock = &radeon_atom_set_engine_clock,
 798                 .get_memory_clock = &radeon_atom_get_memory_clock,
 799                 .set_memory_clock = &radeon_atom_set_memory_clock,
 800                 .get_pcie_lanes = NULL,
 801                 .set_pcie_lanes = NULL,
 802                 .set_clock_gating = &radeon_atom_set_clock_gating,
 803         },
 804         .pflip = {
 805                 .pre_page_flip = &rs600_pre_page_flip,
 806                 .page_flip = &rs600_page_flip,
 807                 .post_page_flip = &rs600_post_page_flip,
 808         },
 809 };
 810
 811 static struct radeon_asic rv515_asic = {
 812         .init = &rv515_init,
 813         .fini = &rv515_fini,
 814         .suspend = &rv515_suspend,
 815         .resume = &rv515_resume,
 816         .vga_set_state = &r100_vga_set_state,
 817         .asic_reset = &rs600_asic_reset,
 818         .ioctl_wait_idle = NULL,
 819         .gui_idle = &r100_gui_idle,
 820         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 821         .gart = {
 822                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 823                 .set_page = &rv370_pcie_gart_set_page,
 824         },
 825         .ring = {
 826                 [RADEON_RING_TYPE_GFX_INDEX] = {
 827                         .ib_execute = &r100_ring_ib_execute,
 828                         .emit_fence = &r300_fence_ring_emit,
 829                         .emit_semaphore = &r100_semaphore_ring_emit,
 830                         .cs_parse = &r300_cs_parse,
 831                         .ring_start = &rv515_ring_start,
 832                         .ring_test = &r100_ring_test,
 833                         .ib_test = &r100_ib_test,
 834                         .is_lockup = &r100_gpu_is_lockup,
 835                         .get_rptr = &radeon_ring_generic_get_rptr,
 836                         .get_wptr = &radeon_ring_generic_get_wptr,
 837                         .set_wptr = &radeon_ring_generic_set_wptr,
 838                 }
 839         },
 840         .irq = {
 841                 .set = &rs600_irq_set,
 842                 .process = &rs600_irq_process,
 843         },
 844         .display = {
 845                 .get_vblank_counter = &rs600_get_vblank_counter,
 846                 .bandwidth_update = &rv515_bandwidth_update,
 847                 .wait_for_vblank = &avivo_wait_for_vblank,
 848                 .set_backlight_level = &atombios_set_backlight_level,
 849                 .get_backlight_level = &atombios_get_backlight_level,
 850         },
 851         .copy = {
 852                 .blit = &r100_copy_blit,
 853                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 854                 .dma = &r200_copy_dma,
 855                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 856                 .copy = &r100_copy_blit,
 857                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 858         },
 859         .surface = {
 860                 .set_reg = r100_set_surface_reg,
 861                 .clear_reg = r100_clear_surface_reg,
 862         },
 863         .hpd = {
 864                 .init = &rs600_hpd_init,
 865                 .fini = &rs600_hpd_fini,
 866                 .sense = &rs600_hpd_sense,
 867                 .set_polarity = &rs600_hpd_set_polarity,
 868         },
 869         .pm = {
 870                 .misc = &rs600_pm_misc,
 871                 .prepare = &rs600_pm_prepare,
 872                 .finish = &rs600_pm_finish,
 873                 .init_profile = &r420_pm_init_profile,
 874                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 875                 .get_engine_clock = &radeon_atom_get_engine_clock,
 876                 .set_engine_clock = &radeon_atom_set_engine_clock,
 877                 .get_memory_clock = &radeon_atom_get_memory_clock,
 878                 .set_memory_clock = &radeon_atom_set_memory_clock,
 879                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 880                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 881                 .set_clock_gating = &radeon_atom_set_clock_gating,
 882         },
 883         .pflip = {
 884                 .pre_page_flip = &rs600_pre_page_flip,
 885                 .page_flip = &rs600_page_flip,
 886                 .post_page_flip = &rs600_post_page_flip,
 887         },
 888 };
 889
 890 static struct radeon_asic r520_asic = {
 891         .init = &r520_init,
 892         .fini = &rv515_fini,
 893         .suspend = &rv515_suspend,
 894         .resume = &r520_resume,
 895         .vga_set_state = &r100_vga_set_state,
 896         .asic_reset = &rs600_asic_reset,
 897         .ioctl_wait_idle = NULL,
 898         .gui_idle = &r100_gui_idle,
 899         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 900         .gart = {
 901                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 902                 .set_page = &rv370_pcie_gart_set_page,
 903         },
 904         .ring = {
 905                 [RADEON_RING_TYPE_GFX_INDEX] = {
 906                         .ib_execute = &r100_ring_ib_execute,
 907                         .emit_fence = &r300_fence_ring_emit,
 908                         .emit_semaphore = &r100_semaphore_ring_emit,
 909                         .cs_parse = &r300_cs_parse,
 910                         .ring_start = &rv515_ring_start,
 911                         .ring_test = &r100_ring_test,
 912                         .ib_test = &r100_ib_test,
 913                         .is_lockup = &r100_gpu_is_lockup,
 914                         .get_rptr = &radeon_ring_generic_get_rptr,
 915                         .get_wptr = &radeon_ring_generic_get_wptr,
 916                         .set_wptr = &radeon_ring_generic_set_wptr,
 917                 }
 918         },
 919         .irq = {
 920                 .set = &rs600_irq_set,
 921                 .process = &rs600_irq_process,
 922         },
 923         .display = {
 924                 .bandwidth_update = &rv515_bandwidth_update,
 925                 .get_vblank_counter = &rs600_get_vblank_counter,
 926                 .wait_for_vblank = &avivo_wait_for_vblank,
 927                 .set_backlight_level = &atombios_set_backlight_level,
 928                 .get_backlight_level = &atombios_get_backlight_level,
 929         },
 930         .copy = {
 931                 .blit = &r100_copy_blit,
 932                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 933                 .dma = &r200_copy_dma,
 934                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 935                 .copy = &r100_copy_blit,
 936                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 937         },
 938         .surface = {
 939                 .set_reg = r100_set_surface_reg,
 940                 .clear_reg = r100_clear_surface_reg,
 941         },
 942         .hpd = {
 943                 .init = &rs600_hpd_init,
 944                 .fini = &rs600_hpd_fini,
 945                 .sense = &rs600_hpd_sense,
 946                 .set_polarity = &rs600_hpd_set_polarity,
 947         },
 948         .pm = {
 949                 .misc = &rs600_pm_misc,
 950                 .prepare = &rs600_pm_prepare,
 951                 .finish = &rs600_pm_finish,
 952                 .init_profile = &r420_pm_init_profile,
 953                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 954                 .get_engine_clock = &radeon_atom_get_engine_clock,
 955                 .set_engine_clock = &radeon_atom_set_engine_clock,
 956                 .get_memory_clock = &radeon_atom_get_memory_clock,
 957                 .set_memory_clock = &radeon_atom_set_memory_clock,
 958                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 959                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 960                 .set_clock_gating = &radeon_atom_set_clock_gating,
 961         },
 962         .pflip = {
 963                 .pre_page_flip = &rs600_pre_page_flip,
 964                 .page_flip = &rs600_page_flip,
 965                 .post_page_flip = &rs600_post_page_flip,
 966         },
 967 };
 968
 969 static struct radeon_asic r600_asic = {
 970         .init = &r600_init,
 971         .fini = &r600_fini,
 972         .suspend = &r600_suspend,
 973         .resume = &r600_resume,
 974         .vga_set_state = &r600_vga_set_state,
 975         .asic_reset = &r600_asic_reset,
 976         .ioctl_wait_idle = r600_ioctl_wait_idle,
 977         .gui_idle = &r600_gui_idle,
 978         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 979         .get_xclk = &r600_get_xclk,
 980         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 981         .gart = {
 982                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 983                 .set_page = &rs600_gart_set_page,
 984         },
 985         .ring = {
 986                 [RADEON_RING_TYPE_GFX_INDEX] = {
 987                         .ib_execute = &r600_ring_ib_execute,
 988                         .emit_fence = &r600_fence_ring_emit,
 989                         .emit_semaphore = &r600_semaphore_ring_emit,
 990                         .cs_parse = &r600_cs_parse,
 991                         .ring_test = &r600_ring_test,
 992                         .ib_test = &r600_ib_test,
 993                         .is_lockup = &r600_gfx_is_lockup,
 994                         .get_rptr = &radeon_ring_generic_get_rptr,
 995                         .get_wptr = &radeon_ring_generic_get_wptr,
 996                         .set_wptr = &radeon_ring_generic_set_wptr,
 997                 },
 998                 [R600_RING_TYPE_DMA_INDEX] = {
 999                         .ib_execute = &r600_dma_ring_ib_execute,
1000                         .emit_fence = &r600_dma_fence_ring_emit,
1001                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1002                         .cs_parse = &r600_dma_cs_parse,
1003                         .ring_test = &r600_dma_ring_test,
1004                         .ib_test = &r600_dma_ib_test,
1005                         .is_lockup = &r600_dma_is_lockup,
1006                         .get_rptr = &radeon_ring_generic_get_rptr,
1007                         .get_wptr = &radeon_ring_generic_get_wptr,
1008                         .set_wptr = &radeon_ring_generic_set_wptr,
1009                 }
1010         },
1011         .irq = {
1012                 .set = &r600_irq_set,
1013                 .process = &r600_irq_process,
1014         },
1015         .display = {
1016                 .bandwidth_update = &rv515_bandwidth_update,
1017                 .get_vblank_counter = &rs600_get_vblank_counter,
1018                 .wait_for_vblank = &avivo_wait_for_vblank,
1019                 .set_backlight_level = &atombios_set_backlight_level,
1020                 .get_backlight_level = &atombios_get_backlight_level,
1021                 .hdmi_enable = &r600_hdmi_enable,
1022                 .hdmi_setmode = &r600_hdmi_setmode,
1023         },
1024         .copy = {
1025                 .blit = &r600_copy_blit,
1026                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1027                 .dma = &r600_copy_dma,
1028                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1029                 .copy = &r600_copy_dma,
1030                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1031         },
1032         .surface = {
1033                 .set_reg = r600_set_surface_reg,
1034                 .clear_reg = r600_clear_surface_reg,
1035         },
1036         .hpd = {
1037                 .init = &r600_hpd_init,
1038                 .fini = &r600_hpd_fini,
1039                 .sense = &r600_hpd_sense,
1040                 .set_polarity = &r600_hpd_set_polarity,
1041         },
1042         .pm = {
1043                 .misc = &r600_pm_misc,
1044                 .prepare = &rs600_pm_prepare,
1045                 .finish = &rs600_pm_finish,
1046                 .init_profile = &r600_pm_init_profile,
1047                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1048                 .get_engine_clock = &radeon_atom_get_engine_clock,
1049                 .set_engine_clock = &radeon_atom_set_engine_clock,
1050                 .get_memory_clock = &radeon_atom_get_memory_clock,
1051                 .set_memory_clock = &radeon_atom_set_memory_clock,
1052                 .get_pcie_lanes = &r600_get_pcie_lanes,
1053                 .set_pcie_lanes = &r600_set_pcie_lanes,
1054                 .set_clock_gating = NULL,
1055                 .get_temperature = &rv6xx_get_temp,
1056         },
1057         .pflip = {
1058                 .pre_page_flip = &rs600_pre_page_flip,
1059                 .page_flip = &rs600_page_flip,
1060                 .post_page_flip = &rs600_post_page_flip,
1061         },
1062 };
1063
1064 static struct radeon_asic rv6xx_asic = {
1065         .init = &r600_init,
1066         .fini = &r600_fini,
1067         .suspend = &r600_suspend,
1068         .resume = &r600_resume,
1069         .vga_set_state = &r600_vga_set_state,
1070         .asic_reset = &r600_asic_reset,
1071         .ioctl_wait_idle = r600_ioctl_wait_idle,
1072         .gui_idle = &r600_gui_idle,
1073         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1074         .get_xclk = &r600_get_xclk,
1075         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1076         .gart = {
1077                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078                 .set_page = &rs600_gart_set_page,
1079         },
1080         .ring = {
1081                 [RADEON_RING_TYPE_GFX_INDEX] = {
1082                         .ib_execute = &r600_ring_ib_execute,
1083                         .emit_fence = &r600_fence_ring_emit,
1084                         .emit_semaphore = &r600_semaphore_ring_emit,
1085                         .cs_parse = &r600_cs_parse,
1086                         .ring_test = &r600_ring_test,
1087                         .ib_test = &r600_ib_test,
1088                         .is_lockup = &r600_gfx_is_lockup,
1089                         .get_rptr = &radeon_ring_generic_get_rptr,
1090                         .get_wptr = &radeon_ring_generic_get_wptr,
1091                         .set_wptr = &radeon_ring_generic_set_wptr,
1092                 },
1093                 [R600_RING_TYPE_DMA_INDEX] = {
1094                         .ib_execute = &r600_dma_ring_ib_execute,
1095                         .emit_fence = &r600_dma_fence_ring_emit,
1096                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097                         .cs_parse = &r600_dma_cs_parse,
1098                         .ring_test = &r600_dma_ring_test,
1099                         .ib_test = &r600_dma_ib_test,
1100                         .is_lockup = &r600_dma_is_lockup,
1101                         .get_rptr = &radeon_ring_generic_get_rptr,
1102                         .get_wptr = &radeon_ring_generic_get_wptr,
1103                         .set_wptr = &radeon_ring_generic_set_wptr,
1104                 }
1105         },
1106         .irq = {
1107                 .set = &r600_irq_set,
1108                 .process = &r600_irq_process,
1109         },
1110         .display = {
1111                 .bandwidth_update = &rv515_bandwidth_update,
1112                 .get_vblank_counter = &rs600_get_vblank_counter,
1113                 .wait_for_vblank = &avivo_wait_for_vblank,
1114                 .set_backlight_level = &atombios_set_backlight_level,
1115                 .get_backlight_level = &atombios_get_backlight_level,
1116         },
1117         .copy = {
1118                 .blit = &r600_copy_blit,
1119                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1120                 .dma = &r600_copy_dma,
1121                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1122                 .copy = &r600_copy_dma,
1123                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1124         },
1125         .surface = {
1126                 .set_reg = r600_set_surface_reg,
1127                 .clear_reg = r600_clear_surface_reg,
1128         },
1129         .hpd = {
1130                 .init = &r600_hpd_init,
1131                 .fini = &r600_hpd_fini,
1132                 .sense = &r600_hpd_sense,
1133                 .set_polarity = &r600_hpd_set_polarity,
1134         },
1135         .pm = {
1136                 .misc = &r600_pm_misc,
1137                 .prepare = &rs600_pm_prepare,
1138                 .finish = &rs600_pm_finish,
1139                 .init_profile = &r600_pm_init_profile,
1140                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1141                 .get_engine_clock = &radeon_atom_get_engine_clock,
1142                 .set_engine_clock = &radeon_atom_set_engine_clock,
1143                 .get_memory_clock = &radeon_atom_get_memory_clock,
1144                 .set_memory_clock = &radeon_atom_set_memory_clock,
1145                 .get_pcie_lanes = &r600_get_pcie_lanes,
1146                 .set_pcie_lanes = &r600_set_pcie_lanes,
1147                 .set_clock_gating = NULL,
1148                 .get_temperature = &rv6xx_get_temp,
1149         },
1150         .dpm = {
1151                 .init = &rv6xx_dpm_init,
1152                 .setup_asic = &rv6xx_setup_asic,
1153                 .enable = &rv6xx_dpm_enable,
1154                 .disable = &rv6xx_dpm_disable,
1155                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1156                 .set_power_state = &rv6xx_dpm_set_power_state,
1157                 .post_set_power_state = &r600_dpm_post_set_power_state,
1158                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1159                 .fini = &rv6xx_dpm_fini,
1160                 .get_sclk = &rv6xx_dpm_get_sclk,
1161                 .get_mclk = &rv6xx_dpm_get_mclk,
1162                 .print_power_state = &rv6xx_dpm_print_power_state,
1163                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1164         },
1165         .pflip = {
1166                 .pre_page_flip = &rs600_pre_page_flip,
1167                 .page_flip = &rs600_page_flip,
1168                 .post_page_flip = &rs600_post_page_flip,
1169         },
1170 };
1171
1172 static struct radeon_asic rs780_asic = {
1173         .init = &r600_init,
1174         .fini = &r600_fini,
1175         .suspend = &r600_suspend,
1176         .resume = &r600_resume,
1177         .vga_set_state = &r600_vga_set_state,
1178         .asic_reset = &r600_asic_reset,
1179         .ioctl_wait_idle = r600_ioctl_wait_idle,
1180         .gui_idle = &r600_gui_idle,
1181         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1182         .get_xclk = &r600_get_xclk,
1183         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1184         .gart = {
1185                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1186                 .set_page = &rs600_gart_set_page,
1187         },
1188         .ring = {
1189                 [RADEON_RING_TYPE_GFX_INDEX] = {
1190                         .ib_execute = &r600_ring_ib_execute,
1191                         .emit_fence = &r600_fence_ring_emit,
1192                         .emit_semaphore = &r600_semaphore_ring_emit,
1193                         .cs_parse = &r600_cs_parse,
1194                         .ring_test = &r600_ring_test,
1195                         .ib_test = &r600_ib_test,
1196                         .is_lockup = &r600_gfx_is_lockup,
1197                         .get_rptr = &radeon_ring_generic_get_rptr,
1198                         .get_wptr = &radeon_ring_generic_get_wptr,
1199                         .set_wptr = &radeon_ring_generic_set_wptr,
1200                 },
1201                 [R600_RING_TYPE_DMA_INDEX] = {
1202                         .ib_execute = &r600_dma_ring_ib_execute,
1203                         .emit_fence = &r600_dma_fence_ring_emit,
1204                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1205                         .cs_parse = &r600_dma_cs_parse,
1206                         .ring_test = &r600_dma_ring_test,
1207                         .ib_test = &r600_dma_ib_test,
1208                         .is_lockup = &r600_dma_is_lockup,
1209                         .get_rptr = &radeon_ring_generic_get_rptr,
1210                         .get_wptr = &radeon_ring_generic_get_wptr,
1211                         .set_wptr = &radeon_ring_generic_set_wptr,
1212                 }
1213         },
1214         .irq = {
1215                 .set = &r600_irq_set,
1216                 .process = &r600_irq_process,
1217         },
1218         .display = {
1219                 .bandwidth_update = &rs690_bandwidth_update,
1220                 .get_vblank_counter = &rs600_get_vblank_counter,
1221                 .wait_for_vblank = &avivo_wait_for_vblank,
1222                 .set_backlight_level = &atombios_set_backlight_level,
1223                 .get_backlight_level = &atombios_get_backlight_level,
1224                 .hdmi_enable = &r600_hdmi_enable,
1225                 .hdmi_setmode = &r600_hdmi_setmode,
1226         },
1227         .copy = {
1228                 .blit = &r600_copy_blit,
1229                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1230                 .dma = &r600_copy_dma,
1231                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1232                 .copy = &r600_copy_dma,
1233                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1234         },
1235         .surface = {
1236                 .set_reg = r600_set_surface_reg,
1237                 .clear_reg = r600_clear_surface_reg,
1238         },
1239         .hpd = {
1240                 .init = &r600_hpd_init,
1241                 .fini = &r600_hpd_fini,
1242                 .sense = &r600_hpd_sense,
1243                 .set_polarity = &r600_hpd_set_polarity,
1244         },
1245         .pm = {
1246                 .misc = &r600_pm_misc,
1247                 .prepare = &rs600_pm_prepare,
1248                 .finish = &rs600_pm_finish,
1249                 .init_profile = &rs780_pm_init_profile,
1250                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1251                 .get_engine_clock = &radeon_atom_get_engine_clock,
1252                 .set_engine_clock = &radeon_atom_set_engine_clock,
1253                 .get_memory_clock = NULL,
1254                 .set_memory_clock = NULL,
1255                 .get_pcie_lanes = NULL,
1256                 .set_pcie_lanes = NULL,
1257                 .set_clock_gating = NULL,
1258                 .get_temperature = &rv6xx_get_temp,
1259         },
1260         .dpm = {
1261                 .init = &rs780_dpm_init,
1262                 .setup_asic = &rs780_dpm_setup_asic,
1263                 .enable = &rs780_dpm_enable,
1264                 .disable = &rs780_dpm_disable,
1265                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1266                 .set_power_state = &rs780_dpm_set_power_state,
1267                 .post_set_power_state = &r600_dpm_post_set_power_state,
1268                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1269                 .fini = &rs780_dpm_fini,
1270                 .get_sclk = &rs780_dpm_get_sclk,
1271                 .get_mclk = &rs780_dpm_get_mclk,
1272                 .print_power_state = &rs780_dpm_print_power_state,
1273         },
1274         .pflip = {
1275                 .pre_page_flip = &rs600_pre_page_flip,
1276                 .page_flip = &rs600_page_flip,
1277                 .post_page_flip = &rs600_post_page_flip,
1278         },
1279 };
1280
1281 static struct radeon_asic rv770_asic = {
1282         .init = &rv770_init,
1283         .fini = &rv770_fini,
1284         .suspend = &rv770_suspend,
1285         .resume = &rv770_resume,
1286         .asic_reset = &r600_asic_reset,
1287         .vga_set_state = &r600_vga_set_state,
1288         .ioctl_wait_idle = r600_ioctl_wait_idle,
1289         .gui_idle = &r600_gui_idle,
1290         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1291         .get_xclk = &rv770_get_xclk,
1292         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1293         .gart = {
1294                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1295                 .set_page = &rs600_gart_set_page,
1296         },
1297         .ring = {
1298                 [RADEON_RING_TYPE_GFX_INDEX] = {
1299                         .ib_execute = &r600_ring_ib_execute,
1300                         .emit_fence = &r600_fence_ring_emit,
1301                         .emit_semaphore = &r600_semaphore_ring_emit,
1302                         .cs_parse = &r600_cs_parse,
1303                         .ring_test = &r600_ring_test,
1304                         .ib_test = &r600_ib_test,
1305                         .is_lockup = &r600_gfx_is_lockup,
1306                         .get_rptr = &radeon_ring_generic_get_rptr,
1307                         .get_wptr = &radeon_ring_generic_get_wptr,
1308                         .set_wptr = &radeon_ring_generic_set_wptr,
1309                 },
1310                 [R600_RING_TYPE_DMA_INDEX] = {
1311                         .ib_execute = &r600_dma_ring_ib_execute,
1312                         .emit_fence = &r600_dma_fence_ring_emit,
1313                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1314                         .cs_parse = &r600_dma_cs_parse,
1315                         .ring_test = &r600_dma_ring_test,
1316                         .ib_test = &r600_dma_ib_test,
1317                         .is_lockup = &r600_dma_is_lockup,
1318                         .get_rptr = &radeon_ring_generic_get_rptr,
1319                         .get_wptr = &radeon_ring_generic_get_wptr,
1320                         .set_wptr = &radeon_ring_generic_set_wptr,
1321                 },
1322                 [R600_RING_TYPE_UVD_INDEX] = {
1323                         .ib_execute = &r600_uvd_ib_execute,
1324                         .emit_fence = &r600_uvd_fence_emit,
1325                         .emit_semaphore = &r600_uvd_semaphore_emit,
1326                         .cs_parse = &radeon_uvd_cs_parse,
1327                         .ring_test = &r600_uvd_ring_test,
1328                         .ib_test = &r600_uvd_ib_test,
1329                         .is_lockup = &radeon_ring_test_lockup,
1330                         .get_rptr = &radeon_ring_generic_get_rptr,
1331                         .get_wptr = &radeon_ring_generic_get_wptr,
1332                         .set_wptr = &radeon_ring_generic_set_wptr,
1333                 }
1334         },
1335         .irq = {
1336                 .set = &r600_irq_set,
1337                 .process = &r600_irq_process,
1338         },
1339         .display = {
1340                 .bandwidth_update = &rv515_bandwidth_update,
1341                 .get_vblank_counter = &rs600_get_vblank_counter,
1342                 .wait_for_vblank = &avivo_wait_for_vblank,
1343                 .set_backlight_level = &atombios_set_backlight_level,
1344                 .get_backlight_level = &atombios_get_backlight_level,
1345                 .hdmi_enable = &r600_hdmi_enable,
1346                 .hdmi_setmode = &r600_hdmi_setmode,
1347         },
1348         .copy = {
1349                 .blit = &r600_copy_blit,
1350                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1351                 .dma = &rv770_copy_dma,
1352                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1353                 .copy = &rv770_copy_dma,
1354                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1355         },
1356         .surface = {
1357                 .set_reg = r600_set_surface_reg,
1358                 .clear_reg = r600_clear_surface_reg,
1359         },
1360         .hpd = {
1361                 .init = &r600_hpd_init,
1362                 .fini = &r600_hpd_fini,
1363                 .sense = &r600_hpd_sense,
1364                 .set_polarity = &r600_hpd_set_polarity,
1365         },
1366         .pm = {
1367                 .misc = &rv770_pm_misc,
1368                 .prepare = &rs600_pm_prepare,
1369                 .finish = &rs600_pm_finish,
1370                 .init_profile = &r600_pm_init_profile,
1371                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1372                 .get_engine_clock = &radeon_atom_get_engine_clock,
1373                 .set_engine_clock = &radeon_atom_set_engine_clock,
1374                 .get_memory_clock = &radeon_atom_get_memory_clock,
1375                 .set_memory_clock = &radeon_atom_set_memory_clock,
1376                 .get_pcie_lanes = &r600_get_pcie_lanes,
1377                 .set_pcie_lanes = &r600_set_pcie_lanes,
1378                 .set_clock_gating = &radeon_atom_set_clock_gating,
1379                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1380                 .get_temperature = &rv770_get_temp,
1381         },
1382         .dpm = {
1383                 .init = &rv770_dpm_init,
1384                 .setup_asic = &rv770_dpm_setup_asic,
1385                 .enable = &rv770_dpm_enable,
1386                 .disable = &rv770_dpm_disable,
1387                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1388                 .set_power_state = &rv770_dpm_set_power_state,
1389                 .post_set_power_state = &r600_dpm_post_set_power_state,
1390                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1391                 .fini = &rv770_dpm_fini,
1392                 .get_sclk = &rv770_dpm_get_sclk,
1393                 .get_mclk = &rv770_dpm_get_mclk,
1394                 .print_power_state = &rv770_dpm_print_power_state,
1395                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1396                 .force_performance_level = &rv770_dpm_force_performance_level,
1397         },
1398         .pflip = {
1399                 .pre_page_flip = &rs600_pre_page_flip,
1400                 .page_flip = &rv770_page_flip,
1401                 .post_page_flip = &rs600_post_page_flip,
1402         },
1403 };
1404
1405 static struct radeon_asic evergreen_asic = {
1406         .init = &evergreen_init,
1407         .fini = &evergreen_fini,
1408         .suspend = &evergreen_suspend,
1409         .resume = &evergreen_resume,
1410         .asic_reset = &evergreen_asic_reset,
1411         .vga_set_state = &r600_vga_set_state,
1412         .ioctl_wait_idle = r600_ioctl_wait_idle,
1413         .gui_idle = &r600_gui_idle,
1414         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1415         .get_xclk = &rv770_get_xclk,
1416         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1417         .gart = {
1418                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1419                 .set_page = &rs600_gart_set_page,
1420         },
1421         .ring = {
1422                 [RADEON_RING_TYPE_GFX_INDEX] = {
1423                         .ib_execute = &evergreen_ring_ib_execute,
1424                         .emit_fence = &r600_fence_ring_emit,
1425                         .emit_semaphore = &r600_semaphore_ring_emit,
1426                         .cs_parse = &evergreen_cs_parse,
1427                         .ring_test = &r600_ring_test,
1428                         .ib_test = &r600_ib_test,
1429                         .is_lockup = &evergreen_gfx_is_lockup,
1430                         .get_rptr = &radeon_ring_generic_get_rptr,
1431                         .get_wptr = &radeon_ring_generic_get_wptr,
1432                         .set_wptr = &radeon_ring_generic_set_wptr,
1433                 },
1434                 [R600_RING_TYPE_DMA_INDEX] = {
1435                         .ib_execute = &evergreen_dma_ring_ib_execute,
1436                         .emit_fence = &evergreen_dma_fence_ring_emit,
1437                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1438                         .cs_parse = &evergreen_dma_cs_parse,
1439                         .ring_test = &r600_dma_ring_test,
1440                         .ib_test = &r600_dma_ib_test,
1441                         .is_lockup = &evergreen_dma_is_lockup,
1442                         .get_rptr = &radeon_ring_generic_get_rptr,
1443                         .get_wptr = &radeon_ring_generic_get_wptr,
1444                         .set_wptr = &radeon_ring_generic_set_wptr,
1445                 },
1446                 [R600_RING_TYPE_UVD_INDEX] = {
1447                         .ib_execute = &r600_uvd_ib_execute,
1448                         .emit_fence = &r600_uvd_fence_emit,
1449                         .emit_semaphore = &r600_uvd_semaphore_emit,
1450                         .cs_parse = &radeon_uvd_cs_parse,
1451                         .ring_test = &r600_uvd_ring_test,
1452                         .ib_test = &r600_uvd_ib_test,
1453                         .is_lockup = &radeon_ring_test_lockup,
1454                         .get_rptr = &radeon_ring_generic_get_rptr,
1455                         .get_wptr = &radeon_ring_generic_get_wptr,
1456                         .set_wptr = &radeon_ring_generic_set_wptr,
1457                 }
1458         },
1459         .irq = {
1460                 .set = &evergreen_irq_set,
1461                 .process = &evergreen_irq_process,
1462         },
1463         .display = {
1464                 .bandwidth_update = &evergreen_bandwidth_update,
1465                 .get_vblank_counter = &evergreen_get_vblank_counter,
1466                 .wait_for_vblank = &dce4_wait_for_vblank,
1467                 .set_backlight_level = &atombios_set_backlight_level,
1468                 .get_backlight_level = &atombios_get_backlight_level,
1469                 .hdmi_enable = &evergreen_hdmi_enable,
1470                 .hdmi_setmode = &evergreen_hdmi_setmode,
1471         },
1472         .copy = {
1473                 .blit = &r600_copy_blit,
1474                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1475                 .dma = &evergreen_copy_dma,
1476                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1477                 .copy = &evergreen_copy_dma,
1478                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1479         },
1480         .surface = {
1481                 .set_reg = r600_set_surface_reg,
1482                 .clear_reg = r600_clear_surface_reg,
1483         },
1484         .hpd = {
1485                 .init = &evergreen_hpd_init,
1486                 .fini = &evergreen_hpd_fini,
1487                 .sense = &evergreen_hpd_sense,
1488                 .set_polarity = &evergreen_hpd_set_polarity,
1489         },
1490         .pm = {
1491                 .misc = &evergreen_pm_misc,
1492                 .prepare = &evergreen_pm_prepare,
1493                 .finish = &evergreen_pm_finish,
1494                 .init_profile = &r600_pm_init_profile,
1495                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1496                 .get_engine_clock = &radeon_atom_get_engine_clock,
1497                 .set_engine_clock = &radeon_atom_set_engine_clock,
1498                 .get_memory_clock = &radeon_atom_get_memory_clock,
1499                 .set_memory_clock = &radeon_atom_set_memory_clock,
1500                 .get_pcie_lanes = &r600_get_pcie_lanes,
1501                 .set_pcie_lanes = &r600_set_pcie_lanes,
1502                 .set_clock_gating = NULL,
1503                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1504                 .get_temperature = &evergreen_get_temp,
1505         },
1506         .dpm = {
1507                 .init = &cypress_dpm_init,
1508                 .setup_asic = &cypress_dpm_setup_asic,
1509                 .enable = &cypress_dpm_enable,
1510                 .disable = &cypress_dpm_disable,
1511                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1512                 .set_power_state = &cypress_dpm_set_power_state,
1513                 .post_set_power_state = &r600_dpm_post_set_power_state,
1514                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1515                 .fini = &cypress_dpm_fini,
1516                 .get_sclk = &rv770_dpm_get_sclk,
1517                 .get_mclk = &rv770_dpm_get_mclk,
1518                 .print_power_state = &rv770_dpm_print_power_state,
1519                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1520                 .force_performance_level = &rv770_dpm_force_performance_level,
1521         },
1522         .pflip = {
1523                 .pre_page_flip = &evergreen_pre_page_flip,
1524                 .page_flip = &evergreen_page_flip,
1525                 .post_page_flip = &evergreen_post_page_flip,
1526         },
1527 };
1528
1529 static struct radeon_asic sumo_asic = {
1530         .init = &evergreen_init,
1531         .fini = &evergreen_fini,
1532         .suspend = &evergreen_suspend,
1533         .resume = &evergreen_resume,
1534         .asic_reset = &evergreen_asic_reset,
1535         .vga_set_state = &r600_vga_set_state,
1536         .ioctl_wait_idle = r600_ioctl_wait_idle,
1537         .gui_idle = &r600_gui_idle,
1538         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1539         .get_xclk = &r600_get_xclk,
1540         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1541         .gart = {
1542                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1543                 .set_page = &rs600_gart_set_page,
1544         },
1545         .ring = {
1546                 [RADEON_RING_TYPE_GFX_INDEX] = {
1547                         .ib_execute = &evergreen_ring_ib_execute,
1548                         .emit_fence = &r600_fence_ring_emit,
1549                         .emit_semaphore = &r600_semaphore_ring_emit,
1550                         .cs_parse = &evergreen_cs_parse,
1551                         .ring_test = &r600_ring_test,
1552                         .ib_test = &r600_ib_test,
1553                         .is_lockup = &evergreen_gfx_is_lockup,
1554                         .get_rptr = &radeon_ring_generic_get_rptr,
1555                         .get_wptr = &radeon_ring_generic_get_wptr,
1556                         .set_wptr = &radeon_ring_generic_set_wptr,
1557                 },
1558                 [R600_RING_TYPE_DMA_INDEX] = {
1559                         .ib_execute = &evergreen_dma_ring_ib_execute,
1560                         .emit_fence = &evergreen_dma_fence_ring_emit,
1561                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1562                         .cs_parse = &evergreen_dma_cs_parse,
1563                         .ring_test = &r600_dma_ring_test,
1564                         .ib_test = &r600_dma_ib_test,
1565                         .is_lockup = &evergreen_dma_is_lockup,
1566                         .get_rptr = &radeon_ring_generic_get_rptr,
1567                         .get_wptr = &radeon_ring_generic_get_wptr,
1568                         .set_wptr = &radeon_ring_generic_set_wptr,
1569                 },
1570                 [R600_RING_TYPE_UVD_INDEX] = {
1571                         .ib_execute = &r600_uvd_ib_execute,
1572                         .emit_fence = &r600_uvd_fence_emit,
1573                         .emit_semaphore = &r600_uvd_semaphore_emit,
1574                         .cs_parse = &radeon_uvd_cs_parse,
1575                         .ring_test = &r600_uvd_ring_test,
1576                         .ib_test = &r600_uvd_ib_test,
1577                         .is_lockup = &radeon_ring_test_lockup,
1578                         .get_rptr = &radeon_ring_generic_get_rptr,
1579                         .get_wptr = &radeon_ring_generic_get_wptr,
1580                         .set_wptr = &radeon_ring_generic_set_wptr,
1581                 }
1582         },
1583         .irq = {
1584                 .set = &evergreen_irq_set,
1585                 .process = &evergreen_irq_process,
1586         },
1587         .display = {
1588                 .bandwidth_update = &evergreen_bandwidth_update,
1589                 .get_vblank_counter = &evergreen_get_vblank_counter,
1590                 .wait_for_vblank = &dce4_wait_for_vblank,
1591                 .set_backlight_level = &atombios_set_backlight_level,
1592                 .get_backlight_level = &atombios_get_backlight_level,
1593                 .hdmi_enable = &evergreen_hdmi_enable,
1594                 .hdmi_setmode = &evergreen_hdmi_setmode,
1595         },
1596         .copy = {
1597                 .blit = &r600_copy_blit,
1598                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1599                 .dma = &evergreen_copy_dma,
1600                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1601                 .copy = &evergreen_copy_dma,
1602                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1603         },
1604         .surface = {
1605                 .set_reg = r600_set_surface_reg,
1606                 .clear_reg = r600_clear_surface_reg,
1607         },
1608         .hpd = {
1609                 .init = &evergreen_hpd_init,
1610                 .fini = &evergreen_hpd_fini,
1611                 .sense = &evergreen_hpd_sense,
1612                 .set_polarity = &evergreen_hpd_set_polarity,
1613         },
1614         .pm = {
1615                 .misc = &evergreen_pm_misc,
1616                 .prepare = &evergreen_pm_prepare,
1617                 .finish = &evergreen_pm_finish,
1618                 .init_profile = &sumo_pm_init_profile,
1619                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1620                 .get_engine_clock = &radeon_atom_get_engine_clock,
1621                 .set_engine_clock = &radeon_atom_set_engine_clock,
1622                 .get_memory_clock = NULL,
1623                 .set_memory_clock = NULL,
1624                 .get_pcie_lanes = NULL,
1625                 .set_pcie_lanes = NULL,
1626                 .set_clock_gating = NULL,
1627                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1628                 .get_temperature = &sumo_get_temp,
1629         },
1630         .dpm = {
1631                 .init = &sumo_dpm_init,
1632                 .setup_asic = &sumo_dpm_setup_asic,
1633                 .enable = &sumo_dpm_enable,
1634                 .disable = &sumo_dpm_disable,
1635                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1636                 .set_power_state = &sumo_dpm_set_power_state,
1637                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1638                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1639                 .fini = &sumo_dpm_fini,
1640                 .get_sclk = &sumo_dpm_get_sclk,
1641                 .get_mclk = &sumo_dpm_get_mclk,
1642                 .print_power_state = &sumo_dpm_print_power_state,
1643                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1644                 .force_performance_level = &sumo_dpm_force_performance_level,
1645         },
1646         .pflip = {
1647                 .pre_page_flip = &evergreen_pre_page_flip,
1648                 .page_flip = &evergreen_page_flip,
1649                 .post_page_flip = &evergreen_post_page_flip,
1650         },
1651 };
1652
1653 static struct radeon_asic btc_asic = {
1654         .init = &evergreen_init,
1655         .fini = &evergreen_fini,
1656         .suspend = &evergreen_suspend,
1657         .resume = &evergreen_resume,
1658         .asic_reset = &evergreen_asic_reset,
1659         .vga_set_state = &r600_vga_set_state,
1660         .ioctl_wait_idle = r600_ioctl_wait_idle,
1661         .gui_idle = &r600_gui_idle,
1662         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1663         .get_xclk = &rv770_get_xclk,
1664         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1665         .gart = {
1666                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1667                 .set_page = &rs600_gart_set_page,
1668         },
1669         .ring = {
1670                 [RADEON_RING_TYPE_GFX_INDEX] = {
1671                         .ib_execute = &evergreen_ring_ib_execute,
1672                         .emit_fence = &r600_fence_ring_emit,
1673                         .emit_semaphore = &r600_semaphore_ring_emit,
1674                         .cs_parse = &evergreen_cs_parse,
1675                         .ring_test = &r600_ring_test,
1676                         .ib_test = &r600_ib_test,
1677                         .is_lockup = &evergreen_gfx_is_lockup,
1678                         .get_rptr = &radeon_ring_generic_get_rptr,
1679                         .get_wptr = &radeon_ring_generic_get_wptr,
1680                         .set_wptr = &radeon_ring_generic_set_wptr,
1681                 },
1682                 [R600_RING_TYPE_DMA_INDEX] = {
1683                         .ib_execute = &evergreen_dma_ring_ib_execute,
1684                         .emit_fence = &evergreen_dma_fence_ring_emit,
1685                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1686                         .cs_parse = &evergreen_dma_cs_parse,
1687                         .ring_test = &r600_dma_ring_test,
1688                         .ib_test = &r600_dma_ib_test,
1689                         .is_lockup = &evergreen_dma_is_lockup,
1690                         .get_rptr = &radeon_ring_generic_get_rptr,
1691                         .get_wptr = &radeon_ring_generic_get_wptr,
1692                         .set_wptr = &radeon_ring_generic_set_wptr,
1693                 },
1694                 [R600_RING_TYPE_UVD_INDEX] = {
1695                         .ib_execute = &r600_uvd_ib_execute,
1696                         .emit_fence = &r600_uvd_fence_emit,
1697                         .emit_semaphore = &r600_uvd_semaphore_emit,
1698                         .cs_parse = &radeon_uvd_cs_parse,
1699                         .ring_test = &r600_uvd_ring_test,
1700                         .ib_test = &r600_uvd_ib_test,
1701                         .is_lockup = &radeon_ring_test_lockup,
1702                         .get_rptr = &radeon_ring_generic_get_rptr,
1703                         .get_wptr = &radeon_ring_generic_get_wptr,
1704                         .set_wptr = &radeon_ring_generic_set_wptr,
1705                 }
1706         },
1707         .irq = {
1708                 .set = &evergreen_irq_set,
1709                 .process = &evergreen_irq_process,
1710         },
1711         .display = {
1712                 .bandwidth_update = &evergreen_bandwidth_update,
1713                 .get_vblank_counter = &evergreen_get_vblank_counter,
1714                 .wait_for_vblank = &dce4_wait_for_vblank,
1715                 .set_backlight_level = &atombios_set_backlight_level,
1716                 .get_backlight_level = &atombios_get_backlight_level,
1717                 .hdmi_enable = &evergreen_hdmi_enable,
1718                 .hdmi_setmode = &evergreen_hdmi_setmode,
1719         },
1720         .copy = {
1721                 .blit = &r600_copy_blit,
1722                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1723                 .dma = &evergreen_copy_dma,
1724                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1725                 .copy = &evergreen_copy_dma,
1726                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1727         },
1728         .surface = {
1729                 .set_reg = r600_set_surface_reg,
1730                 .clear_reg = r600_clear_surface_reg,
1731         },
1732         .hpd = {
1733                 .init = &evergreen_hpd_init,
1734                 .fini = &evergreen_hpd_fini,
1735                 .sense = &evergreen_hpd_sense,
1736                 .set_polarity = &evergreen_hpd_set_polarity,
1737         },
1738         .pm = {
1739                 .misc = &evergreen_pm_misc,
1740                 .prepare = &evergreen_pm_prepare,
1741                 .finish = &evergreen_pm_finish,
1742                 .init_profile = &btc_pm_init_profile,
1743                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1744                 .get_engine_clock = &radeon_atom_get_engine_clock,
1745                 .set_engine_clock = &radeon_atom_set_engine_clock,
1746                 .get_memory_clock = &radeon_atom_get_memory_clock,
1747                 .set_memory_clock = &radeon_atom_set_memory_clock,
1748                 .get_pcie_lanes = &r600_get_pcie_lanes,
1749                 .set_pcie_lanes = &r600_set_pcie_lanes,
1750                 .set_clock_gating = NULL,
1751                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1752                 .get_temperature = &evergreen_get_temp,
1753         },
1754         .dpm = {
1755                 .init = &btc_dpm_init,
1756                 .setup_asic = &btc_dpm_setup_asic,
1757                 .enable = &btc_dpm_enable,
1758                 .disable = &btc_dpm_disable,
1759                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1760                 .set_power_state = &btc_dpm_set_power_state,
1761                 .post_set_power_state = &btc_dpm_post_set_power_state,
1762                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1763                 .fini = &btc_dpm_fini,
1764                 .get_sclk = &btc_dpm_get_sclk,
1765                 .get_mclk = &btc_dpm_get_mclk,
1766                 .print_power_state = &rv770_dpm_print_power_state,
1767                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1768                 .force_performance_level = &rv770_dpm_force_performance_level,
1769         },
1770         .pflip = {
1771                 .pre_page_flip = &evergreen_pre_page_flip,
1772                 .page_flip = &evergreen_page_flip,
1773                 .post_page_flip = &evergreen_post_page_flip,
1774         },
1775 };
1776
1777 static struct radeon_asic cayman_asic = {
1778         .init = &cayman_init,
1779         .fini = &cayman_fini,
1780         .suspend = &cayman_suspend,
1781         .resume = &cayman_resume,
1782         .asic_reset = &cayman_asic_reset,
1783         .vga_set_state = &r600_vga_set_state,
1784         .ioctl_wait_idle = r600_ioctl_wait_idle,
1785         .gui_idle = &r600_gui_idle,
1786         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1787         .get_xclk = &rv770_get_xclk,
1788         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1789         .gart = {
1790                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1791                 .set_page = &rs600_gart_set_page,
1792         },
1793         .vm = {
1794                 .init = &cayman_vm_init,
1795                 .fini = &cayman_vm_fini,
1796                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1797                 .set_page = &cayman_vm_set_page,
1798         },
1799         .ring = {
1800                 [RADEON_RING_TYPE_GFX_INDEX] = {
1801                         .ib_execute = &cayman_ring_ib_execute,
1802                         .ib_parse = &evergreen_ib_parse,
1803                         .emit_fence = &cayman_fence_ring_emit,
1804                         .emit_semaphore = &r600_semaphore_ring_emit,
1805                         .cs_parse = &evergreen_cs_parse,
1806                         .ring_test = &r600_ring_test,
1807                         .ib_test = &r600_ib_test,
1808                         .is_lockup = &cayman_gfx_is_lockup,
1809                         .vm_flush = &cayman_vm_flush,
1810                         .get_rptr = &radeon_ring_generic_get_rptr,
1811                         .get_wptr = &radeon_ring_generic_get_wptr,
1812                         .set_wptr = &radeon_ring_generic_set_wptr,
1813                 },
1814                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1815                         .ib_execute = &cayman_ring_ib_execute,
1816                         .ib_parse = &evergreen_ib_parse,
1817                         .emit_fence = &cayman_fence_ring_emit,
1818                         .emit_semaphore = &r600_semaphore_ring_emit,
1819                         .cs_parse = &evergreen_cs_parse,
1820                         .ring_test = &r600_ring_test,
1821                         .ib_test = &r600_ib_test,
1822                         .is_lockup = &cayman_gfx_is_lockup,
1823                         .vm_flush = &cayman_vm_flush,
1824                         .get_rptr = &radeon_ring_generic_get_rptr,
1825                         .get_wptr = &radeon_ring_generic_get_wptr,
1826                         .set_wptr = &radeon_ring_generic_set_wptr,
1827                 },
1828                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1829                         .ib_execute = &cayman_ring_ib_execute,
1830                         .ib_parse = &evergreen_ib_parse,
1831                         .emit_fence = &cayman_fence_ring_emit,
1832                         .emit_semaphore = &r600_semaphore_ring_emit,
1833                         .cs_parse = &evergreen_cs_parse,
1834                         .ring_test = &r600_ring_test,
1835                         .ib_test = &r600_ib_test,
1836                         .is_lockup = &cayman_gfx_is_lockup,
1837                         .vm_flush = &cayman_vm_flush,
1838                         .get_rptr = &radeon_ring_generic_get_rptr,
1839                         .get_wptr = &radeon_ring_generic_get_wptr,
1840                         .set_wptr = &radeon_ring_generic_set_wptr,
1841                 },
1842                 [R600_RING_TYPE_DMA_INDEX] = {
1843                         .ib_execute = &cayman_dma_ring_ib_execute,
1844                         .ib_parse = &evergreen_dma_ib_parse,
1845                         .emit_fence = &evergreen_dma_fence_ring_emit,
1846                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1847                         .cs_parse = &evergreen_dma_cs_parse,
1848                         .ring_test = &r600_dma_ring_test,
1849                         .ib_test = &r600_dma_ib_test,
1850                         .is_lockup = &cayman_dma_is_lockup,
1851                         .vm_flush = &cayman_dma_vm_flush,
1852                         .get_rptr = &radeon_ring_generic_get_rptr,
1853                         .get_wptr = &radeon_ring_generic_get_wptr,
1854                         .set_wptr = &radeon_ring_generic_set_wptr,
1855                 },
1856                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1857                         .ib_execute = &cayman_dma_ring_ib_execute,
1858                         .ib_parse = &evergreen_dma_ib_parse,
1859                         .emit_fence = &evergreen_dma_fence_ring_emit,
1860                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1861                         .cs_parse = &evergreen_dma_cs_parse,
1862                         .ring_test = &r600_dma_ring_test,
1863                         .ib_test = &r600_dma_ib_test,
1864                         .is_lockup = &cayman_dma_is_lockup,
1865                         .vm_flush = &cayman_dma_vm_flush,
1866                         .get_rptr = &radeon_ring_generic_get_rptr,
1867                         .get_wptr = &radeon_ring_generic_get_wptr,
1868                         .set_wptr = &radeon_ring_generic_set_wptr,
1869                 },
1870                 [R600_RING_TYPE_UVD_INDEX] = {
1871                         .ib_execute = &r600_uvd_ib_execute,
1872                         .emit_fence = &r600_uvd_fence_emit,
1873                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1874                         .cs_parse = &radeon_uvd_cs_parse,
1875                         .ring_test = &r600_uvd_ring_test,
1876                         .ib_test = &r600_uvd_ib_test,
1877                         .is_lockup = &radeon_ring_test_lockup,
1878                         .get_rptr = &radeon_ring_generic_get_rptr,
1879                         .get_wptr = &radeon_ring_generic_get_wptr,
1880                         .set_wptr = &radeon_ring_generic_set_wptr,
1881                 }
1882         },
1883         .irq = {
1884                 .set = &evergreen_irq_set,
1885                 .process = &evergreen_irq_process,
1886         },
1887         .display = {
1888                 .bandwidth_update = &evergreen_bandwidth_update,
1889                 .get_vblank_counter = &evergreen_get_vblank_counter,
1890                 .wait_for_vblank = &dce4_wait_for_vblank,
1891                 .set_backlight_level = &atombios_set_backlight_level,
1892                 .get_backlight_level = &atombios_get_backlight_level,
1893                 .hdmi_enable = &evergreen_hdmi_enable,
1894                 .hdmi_setmode = &evergreen_hdmi_setmode,
1895         },
1896         .copy = {
1897                 .blit = &r600_copy_blit,
1898                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1899                 .dma = &evergreen_copy_dma,
1900                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1901                 .copy = &evergreen_copy_dma,
1902                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1903         },
1904         .surface = {
1905                 .set_reg = r600_set_surface_reg,
1906                 .clear_reg = r600_clear_surface_reg,
1907         },
1908         .hpd = {
1909                 .init = &evergreen_hpd_init,
1910                 .fini = &evergreen_hpd_fini,
1911                 .sense = &evergreen_hpd_sense,
1912                 .set_polarity = &evergreen_hpd_set_polarity,
1913         },
1914         .pm = {
1915                 .misc = &evergreen_pm_misc,
1916                 .prepare = &evergreen_pm_prepare,
1917                 .finish = &evergreen_pm_finish,
1918                 .init_profile = &btc_pm_init_profile,
1919                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1920                 .get_engine_clock = &radeon_atom_get_engine_clock,
1921                 .set_engine_clock = &radeon_atom_set_engine_clock,
1922                 .get_memory_clock = &radeon_atom_get_memory_clock,
1923                 .set_memory_clock = &radeon_atom_set_memory_clock,
1924                 .get_pcie_lanes = &r600_get_pcie_lanes,
1925                 .set_pcie_lanes = &r600_set_pcie_lanes,
1926                 .set_clock_gating = NULL,
1927                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1928                 .get_temperature = &evergreen_get_temp,
1929         },
1930         .dpm = {
1931                 .init = &ni_dpm_init,
1932                 .setup_asic = &ni_dpm_setup_asic,
1933                 .enable = &ni_dpm_enable,
1934                 .disable = &ni_dpm_disable,
1935                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1936                 .set_power_state = &ni_dpm_set_power_state,
1937                 .post_set_power_state = &ni_dpm_post_set_power_state,
1938                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1939                 .fini = &ni_dpm_fini,
1940                 .get_sclk = &ni_dpm_get_sclk,
1941                 .get_mclk = &ni_dpm_get_mclk,
1942                 .print_power_state = &ni_dpm_print_power_state,
1943                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1944                 .force_performance_level = &ni_dpm_force_performance_level,
1945         },
1946         .pflip = {
1947                 .pre_page_flip = &evergreen_pre_page_flip,
1948                 .page_flip = &evergreen_page_flip,
1949                 .post_page_flip = &evergreen_post_page_flip,
1950         },
1951 };
1952
1953 static struct radeon_asic trinity_asic = {
1954         .init = &cayman_init,
1955         .fini = &cayman_fini,
1956         .suspend = &cayman_suspend,
1957         .resume = &cayman_resume,
1958         .asic_reset = &cayman_asic_reset,
1959         .vga_set_state = &r600_vga_set_state,
1960         .ioctl_wait_idle = r600_ioctl_wait_idle,
1961         .gui_idle = &r600_gui_idle,
1962         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1963         .get_xclk = &r600_get_xclk,
1964         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1965         .gart = {
1966                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1967                 .set_page = &rs600_gart_set_page,
1968         },
1969         .vm = {
1970                 .init = &cayman_vm_init,
1971                 .fini = &cayman_vm_fini,
1972                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1973                 .set_page = &cayman_vm_set_page,
1974         },
1975         .ring = {
1976                 [RADEON_RING_TYPE_GFX_INDEX] = {
1977                         .ib_execute = &cayman_ring_ib_execute,
1978                         .ib_parse = &evergreen_ib_parse,
1979                         .emit_fence = &cayman_fence_ring_emit,
1980                         .emit_semaphore = &r600_semaphore_ring_emit,
1981                         .cs_parse = &evergreen_cs_parse,
1982                         .ring_test = &r600_ring_test,
1983                         .ib_test = &r600_ib_test,
1984                         .is_lockup = &cayman_gfx_is_lockup,
1985                         .vm_flush = &cayman_vm_flush,
1986                         .get_rptr = &radeon_ring_generic_get_rptr,
1987                         .get_wptr = &radeon_ring_generic_get_wptr,
1988                         .set_wptr = &radeon_ring_generic_set_wptr,
1989                 },
1990                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1991                         .ib_execute = &cayman_ring_ib_execute,
1992                         .ib_parse = &evergreen_ib_parse,
1993                         .emit_fence = &cayman_fence_ring_emit,
1994                         .emit_semaphore = &r600_semaphore_ring_emit,
1995                         .cs_parse = &evergreen_cs_parse,
1996                         .ring_test = &r600_ring_test,
1997                         .ib_test = &r600_ib_test,
1998                         .is_lockup = &cayman_gfx_is_lockup,
1999                         .vm_flush = &cayman_vm_flush,
2000                         .get_rptr = &radeon_ring_generic_get_rptr,
2001                         .get_wptr = &radeon_ring_generic_get_wptr,
2002                         .set_wptr = &radeon_ring_generic_set_wptr,
2003                 },
2004                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2005                         .ib_execute = &cayman_ring_ib_execute,
2006                         .ib_parse = &evergreen_ib_parse,
2007                         .emit_fence = &cayman_fence_ring_emit,
2008                         .emit_semaphore = &r600_semaphore_ring_emit,
2009                         .cs_parse = &evergreen_cs_parse,
2010                         .ring_test = &r600_ring_test,
2011                         .ib_test = &r600_ib_test,
2012                         .is_lockup = &cayman_gfx_is_lockup,
2013                         .vm_flush = &cayman_vm_flush,
2014                         .get_rptr = &radeon_ring_generic_get_rptr,
2015                         .get_wptr = &radeon_ring_generic_get_wptr,
2016                         .set_wptr = &radeon_ring_generic_set_wptr,
2017                 },
2018                 [R600_RING_TYPE_DMA_INDEX] = {
2019                         .ib_execute = &cayman_dma_ring_ib_execute,
2020                         .ib_parse = &evergreen_dma_ib_parse,
2021                         .emit_fence = &evergreen_dma_fence_ring_emit,
2022                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2023                         .cs_parse = &evergreen_dma_cs_parse,
2024                         .ring_test = &r600_dma_ring_test,
2025                         .ib_test = &r600_dma_ib_test,
2026                         .is_lockup = &cayman_dma_is_lockup,
2027                         .vm_flush = &cayman_dma_vm_flush,
2028                         .get_rptr = &radeon_ring_generic_get_rptr,
2029                         .get_wptr = &radeon_ring_generic_get_wptr,
2030                         .set_wptr = &radeon_ring_generic_set_wptr,
2031                 },
2032                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2033                         .ib_execute = &cayman_dma_ring_ib_execute,
2034                         .ib_parse = &evergreen_dma_ib_parse,
2035                         .emit_fence = &evergreen_dma_fence_ring_emit,
2036                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2037                         .cs_parse = &evergreen_dma_cs_parse,
2038                         .ring_test = &r600_dma_ring_test,
2039                         .ib_test = &r600_dma_ib_test,
2040                         .is_lockup = &cayman_dma_is_lockup,
2041                         .vm_flush = &cayman_dma_vm_flush,
2042                         .get_rptr = &radeon_ring_generic_get_rptr,
2043                         .get_wptr = &radeon_ring_generic_get_wptr,
2044                         .set_wptr = &radeon_ring_generic_set_wptr,
2045                 },
2046                 [R600_RING_TYPE_UVD_INDEX] = {
2047                         .ib_execute = &r600_uvd_ib_execute,
2048                         .emit_fence = &r600_uvd_fence_emit,
2049                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2050                         .cs_parse = &radeon_uvd_cs_parse,
2051                         .ring_test = &r600_uvd_ring_test,
2052                         .ib_test = &r600_uvd_ib_test,
2053                         .is_lockup = &radeon_ring_test_lockup,
2054                         .get_rptr = &radeon_ring_generic_get_rptr,
2055                         .get_wptr = &radeon_ring_generic_get_wptr,
2056                         .set_wptr = &radeon_ring_generic_set_wptr,
2057                 }
2058         },
2059         .irq = {
2060                 .set = &evergreen_irq_set,
2061                 .process = &evergreen_irq_process,
2062         },
2063         .display = {
2064                 .bandwidth_update = &dce6_bandwidth_update,
2065                 .get_vblank_counter = &evergreen_get_vblank_counter,
2066                 .wait_for_vblank = &dce4_wait_for_vblank,
2067                 .set_backlight_level = &atombios_set_backlight_level,
2068                 .get_backlight_level = &atombios_get_backlight_level,
2069         },
2070         .copy = {
2071                 .blit = &r600_copy_blit,
2072                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2073                 .dma = &evergreen_copy_dma,
2074                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2075                 .copy = &evergreen_copy_dma,
2076                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2077         },
2078         .surface = {
2079                 .set_reg = r600_set_surface_reg,
2080                 .clear_reg = r600_clear_surface_reg,
2081         },
2082         .hpd = {
2083                 .init = &evergreen_hpd_init,
2084                 .fini = &evergreen_hpd_fini,
2085                 .sense = &evergreen_hpd_sense,
2086                 .set_polarity = &evergreen_hpd_set_polarity,
2087         },
2088         .pm = {
2089                 .misc = &evergreen_pm_misc,
2090                 .prepare = &evergreen_pm_prepare,
2091                 .finish = &evergreen_pm_finish,
2092                 .init_profile = &sumo_pm_init_profile,
2093                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2094                 .get_engine_clock = &radeon_atom_get_engine_clock,
2095                 .set_engine_clock = &radeon_atom_set_engine_clock,
2096                 .get_memory_clock = NULL,
2097                 .set_memory_clock = NULL,
2098                 .get_pcie_lanes = NULL,
2099                 .set_pcie_lanes = NULL,
2100                 .set_clock_gating = NULL,
2101                 .set_uvd_clocks = &sumo_set_uvd_clocks,
2102                 .get_temperature = &tn_get_temp,
2103         },
2104         .dpm = {
2105                 .init = &trinity_dpm_init,
2106                 .setup_asic = &trinity_dpm_setup_asic,
2107                 .enable = &trinity_dpm_enable,
2108                 .disable = &trinity_dpm_disable,
2109                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
2110                 .set_power_state = &trinity_dpm_set_power_state,
2111                 .post_set_power_state = &trinity_dpm_post_set_power_state,
2112                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
2113                 .fini = &trinity_dpm_fini,
2114                 .get_sclk = &trinity_dpm_get_sclk,
2115                 .get_mclk = &trinity_dpm_get_mclk,
2116                 .print_power_state = &trinity_dpm_print_power_state,
2117                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
2118         },
2119         .pflip = {
2120                 .pre_page_flip = &evergreen_pre_page_flip,
2121                 .page_flip = &evergreen_page_flip,
2122                 .post_page_flip = &evergreen_post_page_flip,
2123         },
2124 };
2125
2126 static struct radeon_asic si_asic = {
2127         .init = &si_init,
2128         .fini = &si_fini,
2129         .suspend = &si_suspend,
2130         .resume = &si_resume,
2131         .asic_reset = &si_asic_reset,
2132         .vga_set_state = &r600_vga_set_state,
2133         .ioctl_wait_idle = r600_ioctl_wait_idle,
2134         .gui_idle = &r600_gui_idle,
2135         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2136         .get_xclk = &si_get_xclk,
2137         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
2138         .gart = {
2139                 .tlb_flush = &si_pcie_gart_tlb_flush,
2140                 .set_page = &rs600_gart_set_page,
2141         },
2142         .vm = {
2143                 .init = &si_vm_init,
2144                 .fini = &si_vm_fini,
2145                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2146                 .set_page = &si_vm_set_page,
2147         },
2148         .ring = {
2149                 [RADEON_RING_TYPE_GFX_INDEX] = {
2150                         .ib_execute = &si_ring_ib_execute,
2151                         .ib_parse = &si_ib_parse,
2152                         .emit_fence = &si_fence_ring_emit,
2153                         .emit_semaphore = &r600_semaphore_ring_emit,
2154                         .cs_parse = NULL,
2155                         .ring_test = &r600_ring_test,
2156                         .ib_test = &r600_ib_test,
2157                         .is_lockup = &si_gfx_is_lockup,
2158                         .vm_flush = &si_vm_flush,
2159                         .get_rptr = &radeon_ring_generic_get_rptr,
2160                         .get_wptr = &radeon_ring_generic_get_wptr,
2161                         .set_wptr = &radeon_ring_generic_set_wptr,
2162                 },
2163                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2164                         .ib_execute = &si_ring_ib_execute,
2165                         .ib_parse = &si_ib_parse,
2166                         .emit_fence = &si_fence_ring_emit,
2167                         .emit_semaphore = &r600_semaphore_ring_emit,
2168                         .cs_parse = NULL,
2169                         .ring_test = &r600_ring_test,
2170                         .ib_test = &r600_ib_test,
2171                         .is_lockup = &si_gfx_is_lockup,
2172                         .vm_flush = &si_vm_flush,
2173                         .get_rptr = &radeon_ring_generic_get_rptr,
2174                         .get_wptr = &radeon_ring_generic_get_wptr,
2175                         .set_wptr = &radeon_ring_generic_set_wptr,
2176                 },
2177                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2178                         .ib_execute = &si_ring_ib_execute,
2179                         .ib_parse = &si_ib_parse,
2180                         .emit_fence = &si_fence_ring_emit,
2181                         .emit_semaphore = &r600_semaphore_ring_emit,
2182                         .cs_parse = NULL,
2183                         .ring_test = &r600_ring_test,
2184                         .ib_test = &r600_ib_test,
2185                         .is_lockup = &si_gfx_is_lockup,
2186                         .vm_flush = &si_vm_flush,
2187                         .get_rptr = &radeon_ring_generic_get_rptr,
2188                         .get_wptr = &radeon_ring_generic_get_wptr,
2189                         .set_wptr = &radeon_ring_generic_set_wptr,
2190                 },
2191                 [R600_RING_TYPE_DMA_INDEX] = {
2192                         .ib_execute = &cayman_dma_ring_ib_execute,
2193                         .ib_parse = &evergreen_dma_ib_parse,
2194                         .emit_fence = &evergreen_dma_fence_ring_emit,
2195                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2196                         .cs_parse = NULL,
2197                         .ring_test = &r600_dma_ring_test,
2198                         .ib_test = &r600_dma_ib_test,
2199                         .is_lockup = &si_dma_is_lockup,
2200                         .vm_flush = &si_dma_vm_flush,
2201                         .get_rptr = &radeon_ring_generic_get_rptr,
2202                         .get_wptr = &radeon_ring_generic_get_wptr,
2203                         .set_wptr = &radeon_ring_generic_set_wptr,
2204                 },
2205                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2206                         .ib_execute = &cayman_dma_ring_ib_execute,
2207                         .ib_parse = &evergreen_dma_ib_parse,
2208                         .emit_fence = &evergreen_dma_fence_ring_emit,
2209                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2210                         .cs_parse = NULL,
2211                         .ring_test = &r600_dma_ring_test,
2212                         .ib_test = &r600_dma_ib_test,
2213                         .is_lockup = &si_dma_is_lockup,
2214                         .vm_flush = &si_dma_vm_flush,
2215                         .get_rptr = &radeon_ring_generic_get_rptr,
2216                         .get_wptr = &radeon_ring_generic_get_wptr,
2217                         .set_wptr = &radeon_ring_generic_set_wptr,
2218                 },
2219                 [R600_RING_TYPE_UVD_INDEX] = {
2220                         .ib_execute = &r600_uvd_ib_execute,
2221                         .emit_fence = &r600_uvd_fence_emit,
2222                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2223                         .cs_parse = &radeon_uvd_cs_parse,
2224                         .ring_test = &r600_uvd_ring_test,
2225                         .ib_test = &r600_uvd_ib_test,
2226                         .is_lockup = &radeon_ring_test_lockup,
2227                         .get_rptr = &radeon_ring_generic_get_rptr,
2228                         .get_wptr = &radeon_ring_generic_get_wptr,
2229                         .set_wptr = &radeon_ring_generic_set_wptr,
2230                 }
2231         },
2232         .irq = {
2233                 .set = &si_irq_set,
2234                 .process = &si_irq_process,
2235         },
2236         .display = {
2237                 .bandwidth_update = &dce6_bandwidth_update,
2238                 .get_vblank_counter = &evergreen_get_vblank_counter,
2239                 .wait_for_vblank = &dce4_wait_for_vblank,
2240                 .set_backlight_level = &atombios_set_backlight_level,
2241                 .get_backlight_level = &atombios_get_backlight_level,
2242         },
2243         .copy = {
2244                 .blit = NULL,
2245                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2246                 .dma = &si_copy_dma,
2247                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2248                 .copy = &si_copy_dma,
2249                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2250         },
2251         .surface = {
2252                 .set_reg = r600_set_surface_reg,
2253                 .clear_reg = r600_clear_surface_reg,
2254         },
2255         .hpd = {
2256                 .init = &evergreen_hpd_init,
2257                 .fini = &evergreen_hpd_fini,
2258                 .sense = &evergreen_hpd_sense,
2259                 .set_polarity = &evergreen_hpd_set_polarity,
2260         },
2261         .pm = {
2262                 .misc = &evergreen_pm_misc,
2263                 .prepare = &evergreen_pm_prepare,
2264                 .finish = &evergreen_pm_finish,
2265                 .init_profile = &sumo_pm_init_profile,
2266                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2267                 .get_engine_clock = &radeon_atom_get_engine_clock,
2268                 .set_engine_clock = &radeon_atom_set_engine_clock,
2269                 .get_memory_clock = &radeon_atom_get_memory_clock,
2270                 .set_memory_clock = &radeon_atom_set_memory_clock,
2271                 .get_pcie_lanes = &r600_get_pcie_lanes,
2272                 .set_pcie_lanes = &r600_set_pcie_lanes,
2273                 .set_clock_gating = NULL,
2274                 .set_uvd_clocks = &si_set_uvd_clocks,
2275                 .get_temperature = &si_get_temp,
2276         },
2277         .dpm = {
2278                 .init = &si_dpm_init,
2279                 .setup_asic = &si_dpm_setup_asic,
2280                 .enable = &si_dpm_enable,
2281                 .disable = &si_dpm_disable,
2282                 .pre_set_power_state = &si_dpm_pre_set_power_state,
2283                 .set_power_state = &si_dpm_set_power_state,
2284                 .post_set_power_state = &si_dpm_post_set_power_state,
2285                 .display_configuration_changed = &si_dpm_display_configuration_changed,
2286                 .fini = &si_dpm_fini,
2287                 .get_sclk = &ni_dpm_get_sclk,
2288                 .get_mclk = &ni_dpm_get_mclk,
2289                 .print_power_state = &ni_dpm_print_power_state,
2290                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
2291                 .force_performance_level = &si_dpm_force_performance_level,
2292         },
2293         .pflip = {
2294                 .pre_page_flip = &evergreen_pre_page_flip,
2295                 .page_flip = &evergreen_page_flip,
2296                 .post_page_flip = &evergreen_post_page_flip,
2297         },
2298 };
2299
2300 static struct radeon_asic ci_asic = {
2301         .init = &cik_init,
2302         .fini = &cik_fini,
2303         .suspend = &cik_suspend,
2304         .resume = &cik_resume,
2305         .asic_reset = &cik_asic_reset,
2306         .vga_set_state = &r600_vga_set_state,
2307         .ioctl_wait_idle = NULL,
2308         .gui_idle = &r600_gui_idle,
2309         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2310         .get_xclk = &cik_get_xclk,
2311         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2312         .gart = {
2313                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2314                 .set_page = &rs600_gart_set_page,
2315         },
2316         .vm = {
2317                 .init = &cik_vm_init,
2318                 .fini = &cik_vm_fini,
2319                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2320                 .set_page = &cik_vm_set_page,
2321         },
2322         .ring = {
2323                 [RADEON_RING_TYPE_GFX_INDEX] = {
2324                         .ib_execute = &cik_ring_ib_execute,
2325                         .ib_parse = &cik_ib_parse,
2326                         .emit_fence = &cik_fence_gfx_ring_emit,
2327                         .emit_semaphore = &cik_semaphore_ring_emit,
2328                         .cs_parse = NULL,
2329                         .ring_test = &cik_ring_test,
2330                         .ib_test = &cik_ib_test,
2331                         .is_lockup = &cik_gfx_is_lockup,
2332                         .vm_flush = &cik_vm_flush,
2333                         .get_rptr = &radeon_ring_generic_get_rptr,
2334                         .get_wptr = &radeon_ring_generic_get_wptr,
2335                         .set_wptr = &radeon_ring_generic_set_wptr,
2336                 },
2337                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2338                         .ib_execute = &cik_ring_ib_execute,
2339                         .ib_parse = &cik_ib_parse,
2340                         .emit_fence = &cik_fence_compute_ring_emit,
2341                         .emit_semaphore = &cik_semaphore_ring_emit,
2342                         .cs_parse = NULL,
2343                         .ring_test = &cik_ring_test,
2344                         .ib_test = &cik_ib_test,
2345                         .is_lockup = &cik_gfx_is_lockup,
2346                         .vm_flush = &cik_vm_flush,
2347                         .get_rptr = &cik_compute_ring_get_rptr,
2348                         .get_wptr = &cik_compute_ring_get_wptr,
2349                         .set_wptr = &cik_compute_ring_set_wptr,
2350                 },
2351                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2352                         .ib_execute = &cik_ring_ib_execute,
2353                         .ib_parse = &cik_ib_parse,
2354                         .emit_fence = &cik_fence_compute_ring_emit,
2355                         .emit_semaphore = &cik_semaphore_ring_emit,
2356                         .cs_parse = NULL,
2357                         .ring_test = &cik_ring_test,
2358                         .ib_test = &cik_ib_test,
2359                         .is_lockup = &cik_gfx_is_lockup,
2360                         .vm_flush = &cik_vm_flush,
2361                         .get_rptr = &cik_compute_ring_get_rptr,
2362                         .get_wptr = &cik_compute_ring_get_wptr,
2363                         .set_wptr = &cik_compute_ring_set_wptr,
2364                 },
2365                 [R600_RING_TYPE_DMA_INDEX] = {
2366                         .ib_execute = &cik_sdma_ring_ib_execute,
2367                         .ib_parse = &cik_ib_parse,
2368                         .emit_fence = &cik_sdma_fence_ring_emit,
2369                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2370                         .cs_parse = NULL,
2371                         .ring_test = &cik_sdma_ring_test,
2372                         .ib_test = &cik_sdma_ib_test,
2373                         .is_lockup = &cik_sdma_is_lockup,
2374                         .vm_flush = &cik_dma_vm_flush,
2375                         .get_rptr = &radeon_ring_generic_get_rptr,
2376                         .get_wptr = &radeon_ring_generic_get_wptr,
2377                         .set_wptr = &radeon_ring_generic_set_wptr,
2378                 },
2379                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2380                         .ib_execute = &cik_sdma_ring_ib_execute,
2381                         .ib_parse = &cik_ib_parse,
2382                         .emit_fence = &cik_sdma_fence_ring_emit,
2383                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2384                         .cs_parse = NULL,
2385                         .ring_test = &cik_sdma_ring_test,
2386                         .ib_test = &cik_sdma_ib_test,
2387                         .is_lockup = &cik_sdma_is_lockup,
2388                         .vm_flush = &cik_dma_vm_flush,
2389                         .get_rptr = &radeon_ring_generic_get_rptr,
2390                         .get_wptr = &radeon_ring_generic_get_wptr,
2391                         .set_wptr = &radeon_ring_generic_set_wptr,
2392                 },
2393                 [R600_RING_TYPE_UVD_INDEX] = {
2394                         .ib_execute = &r600_uvd_ib_execute,
2395                         .emit_fence = &r600_uvd_fence_emit,
2396                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2397                         .cs_parse = &radeon_uvd_cs_parse,
2398                         .ring_test = &r600_uvd_ring_test,
2399                         .ib_test = &r600_uvd_ib_test,
2400                         .is_lockup = &radeon_ring_test_lockup,
2401                         .get_rptr = &radeon_ring_generic_get_rptr,
2402                         .get_wptr = &radeon_ring_generic_get_wptr,
2403                         .set_wptr = &radeon_ring_generic_set_wptr,
2404                 }
2405         },
2406         .irq = {
2407                 .set = &cik_irq_set,
2408                 .process = &cik_irq_process,
2409         },
2410         .display = {
2411                 .bandwidth_update = &dce8_bandwidth_update,
2412                 .get_vblank_counter = &evergreen_get_vblank_counter,
2413                 .wait_for_vblank = &dce4_wait_for_vblank,
2414         },
2415         .copy = {
2416                 .blit = NULL,
2417                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2418                 .dma = &cik_copy_dma,
2419                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2420                 .copy = &cik_copy_dma,
2421                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2422         },
2423         .surface = {
2424                 .set_reg = r600_set_surface_reg,
2425                 .clear_reg = r600_clear_surface_reg,
2426         },
2427         .hpd = {
2428                 .init = &evergreen_hpd_init,
2429                 .fini = &evergreen_hpd_fini,
2430                 .sense = &evergreen_hpd_sense,
2431                 .set_polarity = &evergreen_hpd_set_polarity,
2432         },
2433         .pm = {
2434                 .misc = &evergreen_pm_misc,
2435                 .prepare = &evergreen_pm_prepare,
2436                 .finish = &evergreen_pm_finish,
2437                 .init_profile = &sumo_pm_init_profile,
2438                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2439                 .get_engine_clock = &radeon_atom_get_engine_clock,
2440                 .set_engine_clock = &radeon_atom_set_engine_clock,
2441                 .get_memory_clock = &radeon_atom_get_memory_clock,
2442                 .set_memory_clock = &radeon_atom_set_memory_clock,
2443                 .get_pcie_lanes = NULL,
2444                 .set_pcie_lanes = NULL,
2445                 .set_clock_gating = NULL,
2446                 .set_uvd_clocks = &cik_set_uvd_clocks,
2447         },
2448         .pflip = {
2449                 .pre_page_flip = &evergreen_pre_page_flip,
2450                 .page_flip = &evergreen_page_flip,
2451                 .post_page_flip = &evergreen_post_page_flip,
2452         },
2453 };
2454
2455 static struct radeon_asic kv_asic = {
2456         .init = &cik_init,
2457         .fini = &cik_fini,
2458         .suspend = &cik_suspend,
2459         .resume = &cik_resume,
2460         .asic_reset = &cik_asic_reset,
2461         .vga_set_state = &r600_vga_set_state,
2462         .ioctl_wait_idle = NULL,
2463         .gui_idle = &r600_gui_idle,
2464         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2465         .get_xclk = &cik_get_xclk,
2466         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2467         .gart = {
2468                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2469                 .set_page = &rs600_gart_set_page,
2470         },
2471         .vm = {
2472                 .init = &cik_vm_init,
2473                 .fini = &cik_vm_fini,
2474                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2475                 .set_page = &cik_vm_set_page,
2476         },
2477         .ring = {
2478                 [RADEON_RING_TYPE_GFX_INDEX] = {
2479                         .ib_execute = &cik_ring_ib_execute,
2480                         .ib_parse = &cik_ib_parse,
2481                         .emit_fence = &cik_fence_gfx_ring_emit,
2482                         .emit_semaphore = &cik_semaphore_ring_emit,
2483                         .cs_parse = NULL,
2484                         .ring_test = &cik_ring_test,
2485                         .ib_test = &cik_ib_test,
2486                         .is_lockup = &cik_gfx_is_lockup,
2487                         .vm_flush = &cik_vm_flush,
2488                         .get_rptr = &radeon_ring_generic_get_rptr,
2489                         .get_wptr = &radeon_ring_generic_get_wptr,
2490                         .set_wptr = &radeon_ring_generic_set_wptr,
2491                 },
2492                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2493                         .ib_execute = &cik_ring_ib_execute,
2494                         .ib_parse = &cik_ib_parse,
2495                         .emit_fence = &cik_fence_compute_ring_emit,
2496                         .emit_semaphore = &cik_semaphore_ring_emit,
2497                         .cs_parse = NULL,
2498                         .ring_test = &cik_ring_test,
2499                         .ib_test = &cik_ib_test,
2500                         .is_lockup = &cik_gfx_is_lockup,
2501                         .vm_flush = &cik_vm_flush,
2502                         .get_rptr = &cik_compute_ring_get_rptr,
2503                         .get_wptr = &cik_compute_ring_get_wptr,
2504                         .set_wptr = &cik_compute_ring_set_wptr,
2505                 },
2506                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2507                         .ib_execute = &cik_ring_ib_execute,
2508                         .ib_parse = &cik_ib_parse,
2509                         .emit_fence = &cik_fence_compute_ring_emit,
2510                         .emit_semaphore = &cik_semaphore_ring_emit,
2511                         .cs_parse = NULL,
2512                         .ring_test = &cik_ring_test,
2513                         .ib_test = &cik_ib_test,
2514                         .is_lockup = &cik_gfx_is_lockup,
2515                         .vm_flush = &cik_vm_flush,
2516                         .get_rptr = &cik_compute_ring_get_rptr,
2517                         .get_wptr = &cik_compute_ring_get_wptr,
2518                         .set_wptr = &cik_compute_ring_set_wptr,
2519                 },
2520                 [R600_RING_TYPE_DMA_INDEX] = {
2521                         .ib_execute = &cik_sdma_ring_ib_execute,
2522                         .ib_parse = &cik_ib_parse,
2523                         .emit_fence = &cik_sdma_fence_ring_emit,
2524                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2525                         .cs_parse = NULL,
2526                         .ring_test = &cik_sdma_ring_test,
2527                         .ib_test = &cik_sdma_ib_test,
2528                         .is_lockup = &cik_sdma_is_lockup,
2529                         .vm_flush = &cik_dma_vm_flush,
2530                         .get_rptr = &radeon_ring_generic_get_rptr,
2531                         .get_wptr = &radeon_ring_generic_get_wptr,
2532                         .set_wptr = &radeon_ring_generic_set_wptr,
2533                 },
2534                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2535                         .ib_execute = &cik_sdma_ring_ib_execute,
2536                         .ib_parse = &cik_ib_parse,
2537                         .emit_fence = &cik_sdma_fence_ring_emit,
2538                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2539                         .cs_parse = NULL,
2540                         .ring_test = &cik_sdma_ring_test,
2541                         .ib_test = &cik_sdma_ib_test,
2542                         .is_lockup = &cik_sdma_is_lockup,
2543                         .vm_flush = &cik_dma_vm_flush,
2544                         .get_rptr = &radeon_ring_generic_get_rptr,
2545                         .get_wptr = &radeon_ring_generic_get_wptr,
2546                         .set_wptr = &radeon_ring_generic_set_wptr,
2547                 },
2548                 [R600_RING_TYPE_UVD_INDEX] = {
2549                         .ib_execute = &r600_uvd_ib_execute,
2550                         .emit_fence = &r600_uvd_fence_emit,
2551                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2552                         .cs_parse = &radeon_uvd_cs_parse,
2553                         .ring_test = &r600_uvd_ring_test,
2554                         .ib_test = &r600_uvd_ib_test,
2555                         .is_lockup = &radeon_ring_test_lockup,
2556                         .get_rptr = &radeon_ring_generic_get_rptr,
2557                         .get_wptr = &radeon_ring_generic_get_wptr,
2558                         .set_wptr = &radeon_ring_generic_set_wptr,
2559                 }
2560         },
2561         .irq = {
2562                 .set = &cik_irq_set,
2563                 .process = &cik_irq_process,
2564         },
2565         .display = {
2566                 .bandwidth_update = &dce8_bandwidth_update,
2567                 .get_vblank_counter = &evergreen_get_vblank_counter,
2568                 .wait_for_vblank = &dce4_wait_for_vblank,
2569         },
2570         .copy = {
2571                 .blit = NULL,
2572                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2573                 .dma = &cik_copy_dma,
2574                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2575                 .copy = &cik_copy_dma,
2576                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2577         },
2578         .surface = {
2579                 .set_reg = r600_set_surface_reg,
2580                 .clear_reg = r600_clear_surface_reg,
2581         },
2582         .hpd = {
2583                 .init = &evergreen_hpd_init,
2584                 .fini = &evergreen_hpd_fini,
2585                 .sense = &evergreen_hpd_sense,
2586                 .set_polarity = &evergreen_hpd_set_polarity,
2587         },
2588         .pm = {
2589                 .misc = &evergreen_pm_misc,
2590                 .prepare = &evergreen_pm_prepare,
2591                 .finish = &evergreen_pm_finish,
2592                 .init_profile = &sumo_pm_init_profile,
2593                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2594                 .get_engine_clock = &radeon_atom_get_engine_clock,
2595                 .set_engine_clock = &radeon_atom_set_engine_clock,
2596                 .get_memory_clock = &radeon_atom_get_memory_clock,
2597                 .set_memory_clock = &radeon_atom_set_memory_clock,
2598                 .get_pcie_lanes = NULL,
2599                 .set_pcie_lanes = NULL,
2600                 .set_clock_gating = NULL,
2601                 .set_uvd_clocks = &cik_set_uvd_clocks,
2602         },
2603         .pflip = {
2604                 .pre_page_flip = &evergreen_pre_page_flip,
2605                 .page_flip = &evergreen_page_flip,
2606                 .post_page_flip = &evergreen_post_page_flip,
2607         },
2608 };
2609
2610 /**
2611  * radeon_asic_init - register asic specific callbacks
2612  *
2613  * @rdev: radeon device pointer
2614  *
2615  * Registers the appropriate asic specific callbacks for each
2616  * chip family.  Also sets other asics specific info like the number
2617  * of crtcs and the register aperture accessors (all asics).
2618  * Returns 0 for success.
2619  */
2620 int radeon_asic_init(struct radeon_device *rdev)
2621 {
2622         radeon_register_accessor_init(rdev);
2623
2624         /* set the number of crtcs */
2625         if (rdev->flags & RADEON_SINGLE_CRTC)
2626                 rdev->num_crtc = 1;
2627         else
2628                 rdev->num_crtc = 2;
2629
2630         rdev->has_uvd = false;
2631
2632         switch (rdev->family) {
2633         case CHIP_R100:
2634         case CHIP_RV100:
2635         case CHIP_RS100:
2636         case CHIP_RV200:
2637         case CHIP_RS200:
2638                 rdev->asic = &r100_asic;
2639                 break;
2640         case CHIP_R200:
2641         case CHIP_RV250:
2642         case CHIP_RS300:
2643         case CHIP_RV280:
2644                 rdev->asic = &r200_asic;
2645                 break;
2646         case CHIP_R300:
2647         case CHIP_R350:
2648         case CHIP_RV350:
2649         case CHIP_RV380:
2650                 if (rdev->flags & RADEON_IS_PCIE)
2651                         rdev->asic = &r300_asic_pcie;
2652                 else
2653                         rdev->asic = &r300_asic;
2654                 break;
2655         case CHIP_R420:
2656         case CHIP_R423:
2657         case CHIP_RV410:
2658                 rdev->asic = &r420_asic;
2659                 /* handle macs */
2660                 if (rdev->bios == NULL) {
2661                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2662                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2663                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2664                         rdev->asic->pm.set_memory_clock = NULL;
2665                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2666                 }
2667                 break;
2668         case CHIP_RS400:
2669         case CHIP_RS480:
2670                 rdev->asic = &rs400_asic;
2671                 break;
2672         case CHIP_RS600:
2673                 rdev->asic = &rs600_asic;
2674                 break;
2675         case CHIP_RS690:
2676         case CHIP_RS740:
2677                 rdev->asic = &rs690_asic;
2678                 break;
2679         case CHIP_RV515:
2680                 rdev->asic = &rv515_asic;
2681                 break;
2682         case CHIP_R520:
2683         case CHIP_RV530:
2684         case CHIP_RV560:
2685         case CHIP_RV570:
2686         case CHIP_R580:
2687                 rdev->asic = &r520_asic;
2688                 break;
2689         case CHIP_R600:
2690                 rdev->asic = &r600_asic;
2691                 break;
2692         case CHIP_RV610:
2693         case CHIP_RV630:
2694         case CHIP_RV620:
2695         case CHIP_RV635:
2696         case CHIP_RV670:
2697                 rdev->asic = &rv6xx_asic;
2698                 rdev->has_uvd = true;
2699                 break;
2700         case CHIP_RS780:
2701         case CHIP_RS880:
2702                 rdev->asic = &rs780_asic;
2703                 rdev->has_uvd = true;
2704                 break;
2705         case CHIP_RV770:
2706         case CHIP_RV730:
2707         case CHIP_RV710:
2708         case CHIP_RV740:
2709                 rdev->asic = &rv770_asic;
2710                 rdev->has_uvd = true;
2711                 break;
2712         case CHIP_CEDAR:
2713         case CHIP_REDWOOD:
2714         case CHIP_JUNIPER:
2715         case CHIP_CYPRESS:
2716         case CHIP_HEMLOCK:
2717                 /* set num crtcs */
2718                 if (rdev->family == CHIP_CEDAR)
2719                         rdev->num_crtc = 4;
2720                 else
2721                         rdev->num_crtc = 6;
2722                 rdev->asic = &evergreen_asic;
2723                 rdev->has_uvd = true;
2724                 break;
2725         case CHIP_PALM:
2726         case CHIP_SUMO:
2727         case CHIP_SUMO2:
2728                 rdev->asic = &sumo_asic;
2729                 rdev->has_uvd = true;
2730                 break;
2731         case CHIP_BARTS:
2732         case CHIP_TURKS:
2733         case CHIP_CAICOS:
2734                 /* set num crtcs */
2735                 if (rdev->family == CHIP_CAICOS)
2736                         rdev->num_crtc = 4;
2737                 else
2738                         rdev->num_crtc = 6;
2739                 rdev->asic = &btc_asic;
2740                 rdev->has_uvd = true;
2741                 break;
2742         case CHIP_CAYMAN:
2743                 rdev->asic = &cayman_asic;
2744                 /* set num crtcs */
2745                 rdev->num_crtc = 6;
2746                 rdev->has_uvd = true;
2747                 break;
2748         case CHIP_ARUBA:
2749                 rdev->asic = &trinity_asic;
2750                 /* set num crtcs */
2751                 rdev->num_crtc = 4;
2752                 rdev->has_uvd = true;
2753                 break;
2754         case CHIP_TAHITI:
2755         case CHIP_PITCAIRN:
2756         case CHIP_VERDE:
2757         case CHIP_OLAND:
2758         case CHIP_HAINAN:
2759                 rdev->asic = &si_asic;
2760                 /* set num crtcs */
2761                 if (rdev->family == CHIP_HAINAN)
2762                         rdev->num_crtc = 0;
2763                 else if (rdev->family == CHIP_OLAND)
2764                         rdev->num_crtc = 2;
2765                 else
2766                         rdev->num_crtc = 6;
2767                 if (rdev->family == CHIP_HAINAN)
2768                         rdev->has_uvd = false;
2769                 else
2770                         rdev->has_uvd = true;
2771                 break;
2772         case CHIP_BONAIRE:
2773                 rdev->asic = &ci_asic;
2774                 rdev->num_crtc = 6;
2775                 break;
2776         case CHIP_KAVERI:
2777         case CHIP_KABINI:
2778                 rdev->asic = &kv_asic;
2779                 /* set num crtcs */
2780                 if (rdev->family == CHIP_KAVERI)
2781                         rdev->num_crtc = 4;
2782                 else
2783                         rdev->num_crtc = 2;
2784                 break;
2785         default:
2786                 /* FIXME: not supported yet */
2787                 return -EINVAL;
2788         }
2789
2790         if (rdev->flags & RADEON_IS_IGP) {
2791                 rdev->asic->pm.get_memory_clock = NULL;
2792                 rdev->asic->pm.set_memory_clock = NULL;
2793         }
2794
2795         return 0;
2796 }
2797