drivers/infiniband/hw/cxgb4/qp.c

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34
  35 #include "iw_cxgb4.h"
  36
  37 static int db_delay_usecs = 1;
  38 module_param(db_delay_usecs, int, 0644);
  39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  40
  41 static int ocqp_support = 1;
  42 module_param(ocqp_support, int, 0644);
  43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  44
  45 int db_fc_threshold = 2000;
  46 module_param(db_fc_threshold, int, 0644);
  47 MODULE_PARM_DESC(db_fc_threshold, "QP count/threshold that triggers automatic "
  48                  "db flow control mode (default = 2000)");
  49
  50 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  51 {
  52         unsigned long flag;
  53         spin_lock_irqsave(&qhp->lock, flag);
  54         qhp->attr.state = state;
  55         spin_unlock_irqrestore(&qhp->lock, flag);
  56 }
  57
  58 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  59 {
  60         c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  61 }
  62
  63 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  64 {
  65         dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
  66                           pci_unmap_addr(sq, mapping));
  67 }
  68
  69 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  70 {
  71         if (t4_sq_onchip(sq))
  72                 dealloc_oc_sq(rdev, sq);
  73         else
  74                 dealloc_host_sq(rdev, sq);
  75 }
  76
  77 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  78 {
  79         if (!ocqp_support || !t4_ocqp_supported())
  80                 return -ENOSYS;
  81         sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
  82         if (!sq->dma_addr)
  83                 return -ENOMEM;
  84         sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
  85                         rdev->lldi.vr->ocq.start;
  86         sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
  87                                             rdev->lldi.vr->ocq.start);
  88         sq->flags |= T4_SQ_ONCHIP;
  89         return 0;
  90 }
  91
  92 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  93 {
  94         sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
  95                                        &(sq->dma_addr), GFP_KERNEL);
  96         if (!sq->queue)
  97                 return -ENOMEM;
  98         sq->phys_addr = virt_to_phys(sq->queue);
  99         pci_unmap_addr_set(sq, mapping, sq->dma_addr);
 100         return 0;
 101 }
 102
 103 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
 104 {
 105         int ret = -ENOSYS;
 106         if (user)
 107                 ret = alloc_oc_sq(rdev, sq);
 108         if (ret)
 109                 ret = alloc_host_sq(rdev, sq);
 110         return ret;
 111 }
 112
 113 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 114                       struct c4iw_dev_ucontext *uctx)
 115 {
 116         /*
 117          * uP clears EQ contexts when the connection exits rdma mode,
 118          * so no need to post a RESET WR for these EQs.
 119          */
 120         dma_free_coherent(&(rdev->lldi.pdev->dev),
 121                           wq->rq.memsize, wq->rq.queue,
 122                           dma_unmap_addr(&wq->rq, mapping));
 123         dealloc_sq(rdev, &wq->sq);
 124         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 125         kfree(wq->rq.sw_rq);
 126         kfree(wq->sq.sw_sq);
 127         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 128         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 129         return 0;
 130 }
 131
 132 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 133                      struct t4_cq *rcq, struct t4_cq *scq,
 134                      struct c4iw_dev_ucontext *uctx)
 135 {
 136         int user = (uctx != &rdev->uctx);
 137         struct fw_ri_res_wr *res_wr;
 138         struct fw_ri_res *res;
 139         int wr_len;
 140         struct c4iw_wr_wait wr_wait;
 141         struct sk_buff *skb;
 142         int ret;
 143         int eqsize;
 144
 145         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 146         if (!wq->sq.qid)
 147                 return -ENOMEM;
 148
 149         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 150         if (!wq->rq.qid) {
 151                 ret = -ENOMEM;
 152                 goto free_sq_qid;
 153         }
 154
 155         if (!user) {
 156                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
 157                                  GFP_KERNEL);
 158                 if (!wq->sq.sw_sq) {
 159                         ret = -ENOMEM;
 160                         goto free_rq_qid;
 161                 }
 162
 163                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
 164                                  GFP_KERNEL);
 165                 if (!wq->rq.sw_rq) {
 166                         ret = -ENOMEM;
 167                         goto free_sw_sq;
 168                 }
 169         }
 170
 171         /*
 172          * RQT must be a power of 2.
 173          */
 174         wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
 175         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 176         if (!wq->rq.rqt_hwaddr) {
 177                 ret = -ENOMEM;
 178                 goto free_sw_rq;
 179         }
 180
 181         ret = alloc_sq(rdev, &wq->sq, user);
 182         if (ret)
 183                 goto free_hwaddr;
 184         memset(wq->sq.queue, 0, wq->sq.memsize);
 185         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 186
 187         wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
 188                                           wq->rq.memsize, &(wq->rq.dma_addr),
 189                                           GFP_KERNEL);
 190         if (!wq->rq.queue) {
 191                 ret = -ENOMEM;
 192                 goto free_sq;
 193         }
 194         PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
 195                 __func__, wq->sq.queue,
 196                 (unsigned long long)virt_to_phys(wq->sq.queue),
 197                 wq->rq.queue,
 198                 (unsigned long long)virt_to_phys(wq->rq.queue));
 199         memset(wq->rq.queue, 0, wq->rq.memsize);
 200         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 201
 202         wq->db = rdev->lldi.db_reg;
 203         wq->gts = rdev->lldi.gts_reg;
 204         if (user) {
 205                 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
 206                                         (wq->sq.qid << rdev->qpshift);
 207                 wq->sq.udb &= PAGE_MASK;
 208                 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
 209                                         (wq->rq.qid << rdev->qpshift);
 210                 wq->rq.udb &= PAGE_MASK;
 211         }
 212         wq->rdev = rdev;
 213         wq->rq.msn = 1;
 214
 215         /* build fw_ri_res_wr */
 216         wr_len = sizeof *res_wr + 2 * sizeof *res;
 217
 218         skb = alloc_skb(wr_len, GFP_KERNEL);
 219         if (!skb) {
 220                 ret = -ENOMEM;
 221                 goto free_dma;
 222         }
 223         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
 224
 225         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
 226         memset(res_wr, 0, wr_len);
 227         res_wr->op_nres = cpu_to_be32(
 228                         FW_WR_OP(FW_RI_RES_WR) |
 229                         V_FW_RI_RES_WR_NRES(2) |
 230                         FW_WR_COMPL(1));
 231         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 232         res_wr->cookie = (unsigned long) &wr_wait;
 233         res = res_wr->res;
 234         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 235         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 236
 237         /*
 238          * eqsize is the number of 64B entries plus the status page size.
 239          */
 240         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 241
 242         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 243                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 244                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 245                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 246                 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
 247                 V_FW_RI_RES_WR_IQID(scq->cqid));
 248         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 249                 V_FW_RI_RES_WR_DCAEN(0) |
 250                 V_FW_RI_RES_WR_DCACPU(0) |
 251                 V_FW_RI_RES_WR_FBMIN(2) |
 252                 V_FW_RI_RES_WR_FBMAX(2) |
 253                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 254                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 255                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 256         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 257         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 258         res++;
 259         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 260         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 261
 262         /*
 263          * eqsize is the number of 64B entries plus the status page size.
 264          */
 265         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 266         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 267                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 268                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 269                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 270                 V_FW_RI_RES_WR_IQID(rcq->cqid));
 271         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 272                 V_FW_RI_RES_WR_DCAEN(0) |
 273                 V_FW_RI_RES_WR_DCACPU(0) |
 274                 V_FW_RI_RES_WR_FBMIN(2) |
 275                 V_FW_RI_RES_WR_FBMAX(2) |
 276                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 277                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 278                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 279         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 280         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 281
 282         c4iw_init_wr_wait(&wr_wait);
 283
 284         ret = c4iw_ofld_send(rdev, skb);
 285         if (ret)
 286                 goto free_dma;
 287         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
 288         if (ret)
 289                 goto free_dma;
 290
 291         PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
 292              __func__, wq->sq.qid, wq->rq.qid, wq->db,
 293              (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
 294
 295         return 0;
 296 free_dma:
 297         dma_free_coherent(&(rdev->lldi.pdev->dev),
 298                           wq->rq.memsize, wq->rq.queue,
 299                           dma_unmap_addr(&wq->rq, mapping));
 300 free_sq:
 301         dealloc_sq(rdev, &wq->sq);
 302 free_hwaddr:
 303         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 304 free_sw_rq:
 305         kfree(wq->rq.sw_rq);
 306 free_sw_sq:
 307         kfree(wq->sq.sw_sq);
 308 free_rq_qid:
 309         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 310 free_sq_qid:
 311         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 312         return ret;
 313 }
 314
 315 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 316                       struct ib_send_wr *wr, int max, u32 *plenp)
 317 {
 318         u8 *dstp, *srcp;
 319         u32 plen = 0;
 320         int i;
 321         int rem, len;
 322
 323         dstp = (u8 *)immdp->data;
 324         for (i = 0; i < wr->num_sge; i++) {
 325                 if ((plen + wr->sg_list[i].length) > max)
 326                         return -EMSGSIZE;
 327                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 328                 plen += wr->sg_list[i].length;
 329                 rem = wr->sg_list[i].length;
 330                 while (rem) {
 331                         if (dstp == (u8 *)&sq->queue[sq->size])
 332                                 dstp = (u8 *)sq->queue;
 333                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 334                                 len = rem;
 335                         else
 336                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 337                         memcpy(dstp, srcp, len);
 338                         dstp += len;
 339                         srcp += len;
 340                         rem -= len;
 341                 }
 342         }
 343         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 344         if (len)
 345                 memset(dstp, 0, len);
 346         immdp->op = FW_RI_DATA_IMMD;
 347         immdp->r1 = 0;
 348         immdp->r2 = 0;
 349         immdp->immdlen = cpu_to_be32(plen);
 350         *plenp = plen;
 351         return 0;
 352 }
 353
 354 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 355                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 356                       int num_sge, u32 *plenp)
 357
 358 {
 359         int i;
 360         u32 plen = 0;
 361         __be64 *flitp = (__be64 *)isglp->sge;
 362
 363         for (i = 0; i < num_sge; i++) {
 364                 if ((plen + sg_list[i].length) < plen)
 365                         return -EMSGSIZE;
 366                 plen += sg_list[i].length;
 367                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 368                                      sg_list[i].length);
 369                 if (++flitp == queue_end)
 370                         flitp = queue_start;
 371                 *flitp = cpu_to_be64(sg_list[i].addr);
 372                 if (++flitp == queue_end)
 373                         flitp = queue_start;
 374         }
 375         *flitp = (__force __be64)0;
 376         isglp->op = FW_RI_DATA_ISGL;
 377         isglp->r1 = 0;
 378         isglp->nsge = cpu_to_be16(num_sge);
 379         isglp->r2 = 0;
 380         if (plenp)
 381                 *plenp = plen;
 382         return 0;
 383 }
 384
 385 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 386                            struct ib_send_wr *wr, u8 *len16)
 387 {
 388         u32 plen;
 389         int size;
 390         int ret;
 391
 392         if (wr->num_sge > T4_MAX_SEND_SGE)
 393                 return -EINVAL;
 394         switch (wr->opcode) {
 395         case IB_WR_SEND:
 396                 if (wr->send_flags & IB_SEND_SOLICITED)
 397                         wqe->send.sendop_pkd = cpu_to_be32(
 398                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
 399                 else
 400                         wqe->send.sendop_pkd = cpu_to_be32(
 401                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
 402                 wqe->send.stag_inv = 0;
 403                 break;
 404         case IB_WR_SEND_WITH_INV:
 405                 if (wr->send_flags & IB_SEND_SOLICITED)
 406                         wqe->send.sendop_pkd = cpu_to_be32(
 407                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
 408                 else
 409                         wqe->send.sendop_pkd = cpu_to_be32(
 410                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
 411                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 412                 break;
 413
 414         default:
 415                 return -EINVAL;
 416         }
 417
 418         plen = 0;
 419         if (wr->num_sge) {
 420                 if (wr->send_flags & IB_SEND_INLINE) {
 421                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 422                                          T4_MAX_SEND_INLINE, &plen);
 423                         if (ret)
 424                                 return ret;
 425                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 426                                plen;
 427                 } else {
 428                         ret = build_isgl((__be64 *)sq->queue,
 429                                          (__be64 *)&sq->queue[sq->size],
 430                                          wqe->send.u.isgl_src,
 431                                          wr->sg_list, wr->num_sge, &plen);
 432                         if (ret)
 433                                 return ret;
 434                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 435                                wr->num_sge * sizeof(struct fw_ri_sge);
 436                 }
 437         } else {
 438                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 439                 wqe->send.u.immd_src[0].r1 = 0;
 440                 wqe->send.u.immd_src[0].r2 = 0;
 441                 wqe->send.u.immd_src[0].immdlen = 0;
 442                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 443                 plen = 0;
 444         }
 445         *len16 = DIV_ROUND_UP(size, 16);
 446         wqe->send.plen = cpu_to_be32(plen);
 447         return 0;
 448 }
 449
 450 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 451                             struct ib_send_wr *wr, u8 *len16)
 452 {
 453         u32 plen;
 454         int size;
 455         int ret;
 456
 457         if (wr->num_sge > T4_MAX_SEND_SGE)
 458                 return -EINVAL;
 459         wqe->write.r2 = 0;
 460         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
 461         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
 462         if (wr->num_sge) {
 463                 if (wr->send_flags & IB_SEND_INLINE) {
 464                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 465                                          T4_MAX_WRITE_INLINE, &plen);
 466                         if (ret)
 467                                 return ret;
 468                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 469                                plen;
 470                 } else {
 471                         ret = build_isgl((__be64 *)sq->queue,
 472                                          (__be64 *)&sq->queue[sq->size],
 473                                          wqe->write.u.isgl_src,
 474                                          wr->sg_list, wr->num_sge, &plen);
 475                         if (ret)
 476                                 return ret;
 477                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 478                                wr->num_sge * sizeof(struct fw_ri_sge);
 479                 }
 480         } else {
 481                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 482                 wqe->write.u.immd_src[0].r1 = 0;
 483                 wqe->write.u.immd_src[0].r2 = 0;
 484                 wqe->write.u.immd_src[0].immdlen = 0;
 485                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 486                 plen = 0;
 487         }
 488         *len16 = DIV_ROUND_UP(size, 16);
 489         wqe->write.plen = cpu_to_be32(plen);
 490         return 0;
 491 }
 492
 493 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 494 {
 495         if (wr->num_sge > 1)
 496                 return -EINVAL;
 497         if (wr->num_sge) {
 498                 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
 499                 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
 500                                                         >> 32));
 501                 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
 502                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 503                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 504                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 505                                                          >> 32));
 506                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 507         } else {
 508                 wqe->read.stag_src = cpu_to_be32(2);
 509                 wqe->read.to_src_hi = 0;
 510                 wqe->read.to_src_lo = 0;
 511                 wqe->read.stag_sink = cpu_to_be32(2);
 512                 wqe->read.plen = 0;
 513                 wqe->read.to_sink_hi = 0;
 514                 wqe->read.to_sink_lo = 0;
 515         }
 516         wqe->read.r2 = 0;
 517         wqe->read.r5 = 0;
 518         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 519         return 0;
 520 }
 521
 522 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 523                            struct ib_recv_wr *wr, u8 *len16)
 524 {
 525         int ret;
 526
 527         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 528                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 529                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 530         if (ret)
 531                 return ret;
 532         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 533                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 534         return 0;
 535 }
 536
 537 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
 538                          struct ib_send_wr *wr, u8 *len16)
 539 {
 540
 541         struct fw_ri_immd *imdp;
 542         __be64 *p;
 543         int i;
 544         int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
 545         int rem;
 546
 547         if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
 548                 return -EINVAL;
 549
 550         wqe->fr.qpbinde_to_dcacpu = 0;
 551         wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
 552         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 553         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
 554         wqe->fr.len_hi = 0;
 555         wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
 556         wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
 557         wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
 558         wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
 559                                         0xffffffff);
 560         WARN_ON(pbllen > T4_MAX_FR_IMMD);
 561         imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 562         imdp->op = FW_RI_DATA_IMMD;
 563         imdp->r1 = 0;
 564         imdp->r2 = 0;
 565         imdp->immdlen = cpu_to_be32(pbllen);
 566         p = (__be64 *)(imdp + 1);
 567         rem = pbllen;
 568         for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 569                 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
 570                 rem -= sizeof *p;
 571                 if (++p == (__be64 *)&sq->queue[sq->size])
 572                         p = (__be64 *)sq->queue;
 573         }
 574         BUG_ON(rem < 0);
 575         while (rem) {
 576                 *p = 0;
 577                 rem -= sizeof *p;
 578                 if (++p == (__be64 *)&sq->queue[sq->size])
 579                         p = (__be64 *)sq->queue;
 580         }
 581         *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
 582         return 0;
 583 }
 584
 585 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
 586                           u8 *len16)
 587 {
 588         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 589         wqe->inv.r2 = 0;
 590         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 591         return 0;
 592 }
 593
 594 void c4iw_qp_add_ref(struct ib_qp *qp)
 595 {
 596         PDBG("%s ib_qp %p\n", __func__, qp);
 597         atomic_inc(&(to_c4iw_qp(qp)->refcnt));
 598 }
 599
 600 void c4iw_qp_rem_ref(struct ib_qp *qp)
 601 {
 602         PDBG("%s ib_qp %p\n", __func__, qp);
 603         if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
 604                 wake_up(&(to_c4iw_qp(qp)->wait));
 605 }
 606
 607 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 608                    struct ib_send_wr **bad_wr)
 609 {
 610         int err = 0;
 611         u8 len16 = 0;
 612         enum fw_wr_opcodes fw_opcode = 0;
 613         enum fw_ri_wr_flags fw_flags;
 614         struct c4iw_qp *qhp;
 615         union t4_wr *wqe;
 616         u32 num_wrs;
 617         struct t4_swsqe *swsqe;
 618         unsigned long flag;
 619         u16 idx = 0;
 620
 621         qhp = to_c4iw_qp(ibqp);
 622         spin_lock_irqsave(&qhp->lock, flag);
 623         if (t4_wq_in_error(&qhp->wq)) {
 624                 spin_unlock_irqrestore(&qhp->lock, flag);
 625                 return -EINVAL;
 626         }
 627         num_wrs = t4_sq_avail(&qhp->wq);
 628         if (num_wrs == 0) {
 629                 spin_unlock_irqrestore(&qhp->lock, flag);
 630                 return -ENOMEM;
 631         }
 632         while (wr) {
 633                 if (num_wrs == 0) {
 634                         err = -ENOMEM;
 635                         *bad_wr = wr;
 636                         break;
 637                 }
 638                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
 639                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
 640
 641                 fw_flags = 0;
 642                 if (wr->send_flags & IB_SEND_SOLICITED)
 643                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
 644                 if (wr->send_flags & IB_SEND_SIGNALED)
 645                         fw_flags |= FW_RI_COMPLETION_FLAG;
 646                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
 647                 switch (wr->opcode) {
 648                 case IB_WR_SEND_WITH_INV:
 649                 case IB_WR_SEND:
 650                         if (wr->send_flags & IB_SEND_FENCE)
 651                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
 652                         fw_opcode = FW_RI_SEND_WR;
 653                         if (wr->opcode == IB_WR_SEND)
 654                                 swsqe->opcode = FW_RI_SEND;
 655                         else
 656                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
 657                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
 658                         break;
 659                 case IB_WR_RDMA_WRITE:
 660                         fw_opcode = FW_RI_RDMA_WRITE_WR;
 661                         swsqe->opcode = FW_RI_RDMA_WRITE;
 662                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
 663                         break;
 664                 case IB_WR_RDMA_READ:
 665                 case IB_WR_RDMA_READ_WITH_INV:
 666                         fw_opcode = FW_RI_RDMA_READ_WR;
 667                         swsqe->opcode = FW_RI_READ_REQ;
 668                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 669                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 670                         else
 671                                 fw_flags = 0;
 672                         err = build_rdma_read(wqe, wr, &len16);
 673                         if (err)
 674                                 break;
 675                         swsqe->read_len = wr->sg_list[0].length;
 676                         if (!qhp->wq.sq.oldest_read)
 677                                 qhp->wq.sq.oldest_read = swsqe;
 678                         break;
 679                 case IB_WR_FAST_REG_MR:
 680                         fw_opcode = FW_RI_FR_NSMR_WR;
 681                         swsqe->opcode = FW_RI_FAST_REGISTER;
 682                         err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
 683                         break;
 684                 case IB_WR_LOCAL_INV:
 685                         if (wr->send_flags & IB_SEND_FENCE)
 686                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
 687                         fw_opcode = FW_RI_INV_LSTAG_WR;
 688                         swsqe->opcode = FW_RI_LOCAL_INV;
 689                         err = build_inv_stag(wqe, wr, &len16);
 690                         break;
 691                 default:
 692                         PDBG("%s post of type=%d TBD!\n", __func__,
 693                              wr->opcode);
 694                         err = -EINVAL;
 695                 }
 696                 if (err) {
 697                         *bad_wr = wr;
 698                         break;
 699                 }
 700                 swsqe->idx = qhp->wq.sq.pidx;
 701                 swsqe->complete = 0;
 702                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
 703                 swsqe->wr_id = wr->wr_id;
 704
 705                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
 706
 707                 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
 708                      __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
 709                      swsqe->opcode, swsqe->read_len);
 710                 wr = wr->next;
 711                 num_wrs--;
 712                 t4_sq_produce(&qhp->wq, len16);
 713                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 714         }
 715         if (t4_wq_db_enabled(&qhp->wq))
 716                 t4_ring_sq_db(&qhp->wq, idx);
 717         spin_unlock_irqrestore(&qhp->lock, flag);
 718         return err;
 719 }
 720
 721 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 722                       struct ib_recv_wr **bad_wr)
 723 {
 724         int err = 0;
 725         struct c4iw_qp *qhp;
 726         union t4_recv_wr *wqe;
 727         u32 num_wrs;
 728         u8 len16 = 0;
 729         unsigned long flag;
 730         u16 idx = 0;
 731
 732         qhp = to_c4iw_qp(ibqp);
 733         spin_lock_irqsave(&qhp->lock, flag);
 734         if (t4_wq_in_error(&qhp->wq)) {
 735                 spin_unlock_irqrestore(&qhp->lock, flag);
 736                 return -EINVAL;
 737         }
 738         num_wrs = t4_rq_avail(&qhp->wq);
 739         if (num_wrs == 0) {
 740                 spin_unlock_irqrestore(&qhp->lock, flag);
 741                 return -ENOMEM;
 742         }
 743         while (wr) {
 744                 if (wr->num_sge > T4_MAX_RECV_SGE) {
 745                         err = -EINVAL;
 746                         *bad_wr = wr;
 747                         break;
 748                 }
 749                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
 750                                            qhp->wq.rq.wq_pidx *
 751                                            T4_EQ_ENTRY_SIZE);
 752                 if (num_wrs)
 753                         err = build_rdma_recv(qhp, wqe, wr, &len16);
 754                 else
 755                         err = -ENOMEM;
 756                 if (err) {
 757                         *bad_wr = wr;
 758                         break;
 759                 }
 760
 761                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
 762
 763                 wqe->recv.opcode = FW_RI_RECV_WR;
 764                 wqe->recv.r1 = 0;
 765                 wqe->recv.wrid = qhp->wq.rq.pidx;
 766                 wqe->recv.r2[0] = 0;
 767                 wqe->recv.r2[1] = 0;
 768                 wqe->recv.r2[2] = 0;
 769                 wqe->recv.len16 = len16;
 770                 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
 771                      (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
 772                 t4_rq_produce(&qhp->wq, len16);
 773                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 774                 wr = wr->next;
 775                 num_wrs--;
 776         }
 777         if (t4_wq_db_enabled(&qhp->wq))
 778                 t4_ring_rq_db(&qhp->wq, idx);
 779         spin_unlock_irqrestore(&qhp->lock, flag);
 780         return err;
 781 }
 782
 783 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
 784 {
 785         return -ENOSYS;
 786 }
 787
 788 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
 789                                     u8 *ecode)
 790 {
 791         int status;
 792         int tagged;
 793         int opcode;
 794         int rqtype;
 795         int send_inv;
 796
 797         if (!err_cqe) {
 798                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 799                 *ecode = 0;
 800                 return;
 801         }
 802
 803         status = CQE_STATUS(err_cqe);
 804         opcode = CQE_OPCODE(err_cqe);
 805         rqtype = RQ_TYPE(err_cqe);
 806         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
 807                    (opcode == FW_RI_SEND_WITH_SE_INV);
 808         tagged = (opcode == FW_RI_RDMA_WRITE) ||
 809                  (rqtype && (opcode == FW_RI_READ_RESP));
 810
 811         switch (status) {
 812         case T4_ERR_STAG:
 813                 if (send_inv) {
 814                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 815                         *ecode = RDMAP_CANT_INV_STAG;
 816                 } else {
 817                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 818                         *ecode = RDMAP_INV_STAG;
 819                 }
 820                 break;
 821         case T4_ERR_PDID:
 822                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 823                 if ((opcode == FW_RI_SEND_WITH_INV) ||
 824                     (opcode == FW_RI_SEND_WITH_SE_INV))
 825                         *ecode = RDMAP_CANT_INV_STAG;
 826                 else
 827                         *ecode = RDMAP_STAG_NOT_ASSOC;
 828                 break;
 829         case T4_ERR_QPID:
 830                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 831                 *ecode = RDMAP_STAG_NOT_ASSOC;
 832                 break;
 833         case T4_ERR_ACCESS:
 834                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 835                 *ecode = RDMAP_ACC_VIOL;
 836                 break;
 837         case T4_ERR_WRAP:
 838                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 839                 *ecode = RDMAP_TO_WRAP;
 840                 break;
 841         case T4_ERR_BOUND:
 842                 if (tagged) {
 843                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 844                         *ecode = DDPT_BASE_BOUNDS;
 845                 } else {
 846                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 847                         *ecode = RDMAP_BASE_BOUNDS;
 848                 }
 849                 break;
 850         case T4_ERR_INVALIDATE_SHARED_MR:
 851         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
 852                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 853                 *ecode = RDMAP_CANT_INV_STAG;
 854                 break;
 855         case T4_ERR_ECC:
 856         case T4_ERR_ECC_PSTAG:
 857         case T4_ERR_INTERNAL_ERR:
 858                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
 859                 *ecode = 0;
 860                 break;
 861         case T4_ERR_OUT_OF_RQE:
 862                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 863                 *ecode = DDPU_INV_MSN_NOBUF;
 864                 break;
 865         case T4_ERR_PBL_ADDR_BOUND:
 866                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 867                 *ecode = DDPT_BASE_BOUNDS;
 868                 break;
 869         case T4_ERR_CRC:
 870                 *layer_type = LAYER_MPA|DDP_LLP;
 871                 *ecode = MPA_CRC_ERR;
 872                 break;
 873         case T4_ERR_MARKER:
 874                 *layer_type = LAYER_MPA|DDP_LLP;
 875                 *ecode = MPA_MARKER_ERR;
 876                 break;
 877         case T4_ERR_PDU_LEN_ERR:
 878                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 879                 *ecode = DDPU_MSG_TOOBIG;
 880                 break;
 881         case T4_ERR_DDP_VERSION:
 882                 if (tagged) {
 883                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 884                         *ecode = DDPT_INV_VERS;
 885                 } else {
 886                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 887                         *ecode = DDPU_INV_VERS;
 888                 }
 889                 break;
 890         case T4_ERR_RDMA_VERSION:
 891                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 892                 *ecode = RDMAP_INV_VERS;
 893                 break;
 894         case T4_ERR_OPCODE:
 895                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 896                 *ecode = RDMAP_INV_OPCODE;
 897                 break;
 898         case T4_ERR_DDP_QUEUE_NUM:
 899                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 900                 *ecode = DDPU_INV_QN;
 901                 break;
 902         case T4_ERR_MSN:
 903         case T4_ERR_MSN_GAP:
 904         case T4_ERR_MSN_RANGE:
 905         case T4_ERR_IRD_OVERFLOW:
 906                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 907                 *ecode = DDPU_INV_MSN_RANGE;
 908                 break;
 909         case T4_ERR_TBIT:
 910                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
 911                 *ecode = 0;
 912                 break;
 913         case T4_ERR_MO:
 914                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 915                 *ecode = DDPU_INV_MO;
 916                 break;
 917         default:
 918                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 919                 *ecode = 0;
 920                 break;
 921         }
 922 }
 923
 924 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
 925                            gfp_t gfp)
 926 {
 927         struct fw_ri_wr *wqe;
 928         struct sk_buff *skb;
 929         struct terminate_message *term;
 930
 931         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
 932              qhp->ep->hwtid);
 933
 934         skb = alloc_skb(sizeof *wqe, gfp);
 935         if (!skb)
 936                 return;
 937         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
 938
 939         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
 940         memset(wqe, 0, sizeof *wqe);
 941         wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
 942         wqe->flowid_len16 = cpu_to_be32(
 943                 FW_WR_FLOWID(qhp->ep->hwtid) |
 944                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
 945
 946         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
 947         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
 948         term = (struct terminate_message *)wqe->u.terminate.termmsg;
 949         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
 950                 term->layer_etype = qhp->attr.layer_etype;
 951                 term->ecode = qhp->attr.ecode;
 952         } else
 953                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
 954         c4iw_ofld_send(&qhp->rhp->rdev, skb);
 955 }
 956
 957 /*
 958  * Assumes qhp lock is held.
 959  */
 960 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
 961                        struct c4iw_cq *schp)
 962 {
 963         int count;
 964         int flushed;
 965         unsigned long flag;
 966
 967         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
 968
 969         /* locking hierarchy: cq lock first, then qp lock. */
 970         spin_lock_irqsave(&rchp->lock, flag);
 971         spin_lock(&qhp->lock);
 972         c4iw_flush_hw_cq(&rchp->cq);
 973         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
 974         flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
 975         spin_unlock(&qhp->lock);
 976         spin_unlock_irqrestore(&rchp->lock, flag);
 977         if (flushed) {
 978                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
 979                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
 980                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
 981         }
 982
 983         /* locking hierarchy: cq lock first, then qp lock. */
 984         spin_lock_irqsave(&schp->lock, flag);
 985         spin_lock(&qhp->lock);
 986         c4iw_flush_hw_cq(&schp->cq);
 987         c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
 988         flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
 989         spin_unlock(&qhp->lock);
 990         spin_unlock_irqrestore(&schp->lock, flag);
 991         if (flushed) {
 992                 spin_lock_irqsave(&schp->comp_handler_lock, flag);
 993                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
 994                 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
 995         }
 996 }
 997
 998 static void flush_qp(struct c4iw_qp *qhp)
 999 {
1000         struct c4iw_cq *rchp, *schp;
1001         unsigned long flag;
1002
1003         rchp = get_chp(qhp->rhp, qhp->attr.rcq);
1004         schp = get_chp(qhp->rhp, qhp->attr.scq);
1005
1006         if (qhp->ibqp.uobject) {
1007                 t4_set_wq_in_error(&qhp->wq);
1008                 t4_set_cq_in_error(&rchp->cq);
1009                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1010                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1011                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1012                 if (schp != rchp) {
1013                         t4_set_cq_in_error(&schp->cq);
1014                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1015                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1016                                         schp->ibcq.cq_context);
1017                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1018                 }
1019                 return;
1020         }
1021         __flush_qp(qhp, rchp, schp);
1022 }
1023
1024 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1025                      struct c4iw_ep *ep)
1026 {
1027         struct fw_ri_wr *wqe;
1028         int ret;
1029         struct sk_buff *skb;
1030
1031         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1032              ep->hwtid);
1033
1034         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1035         if (!skb)
1036                 return -ENOMEM;
1037         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1038
1039         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1040         memset(wqe, 0, sizeof *wqe);
1041         wqe->op_compl = cpu_to_be32(
1042                 FW_WR_OP(FW_RI_INIT_WR) |
1043                 FW_WR_COMPL(1));
1044         wqe->flowid_len16 = cpu_to_be32(
1045                 FW_WR_FLOWID(ep->hwtid) |
1046                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1047         wqe->cookie = (unsigned long) &ep->com.wr_wait;
1048
1049         wqe->u.fini.type = FW_RI_TYPE_FINI;
1050         ret = c4iw_ofld_send(&rhp->rdev, skb);
1051         if (ret)
1052                 goto out;
1053
1054         ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1055                              qhp->wq.sq.qid, __func__);
1056 out:
1057         PDBG("%s ret %d\n", __func__, ret);
1058         return ret;
1059 }
1060
1061 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1062 {
1063         PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1064         memset(&init->u, 0, sizeof init->u);
1065         switch (p2p_type) {
1066         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1067                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1068                 init->u.write.stag_sink = cpu_to_be32(1);
1069                 init->u.write.to_sink = cpu_to_be64(1);
1070                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1071                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1072                                                    sizeof(struct fw_ri_immd),
1073                                                    16);
1074                 break;
1075         case FW_RI_INIT_P2PTYPE_READ_REQ:
1076                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1077                 init->u.read.stag_src = cpu_to_be32(1);
1078                 init->u.read.to_src_lo = cpu_to_be32(1);
1079                 init->u.read.stag_sink = cpu_to_be32(1);
1080                 init->u.read.to_sink_lo = cpu_to_be32(1);
1081                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1082                 break;
1083         }
1084 }
1085
1086 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1087 {
1088         struct fw_ri_wr *wqe;
1089         int ret;
1090         struct sk_buff *skb;
1091
1092         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1093              qhp->ep->hwtid);
1094
1095         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1096         if (!skb)
1097                 return -ENOMEM;
1098         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1099
1100         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1101         memset(wqe, 0, sizeof *wqe);
1102         wqe->op_compl = cpu_to_be32(
1103                 FW_WR_OP(FW_RI_INIT_WR) |
1104                 FW_WR_COMPL(1));
1105         wqe->flowid_len16 = cpu_to_be32(
1106                 FW_WR_FLOWID(qhp->ep->hwtid) |
1107                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1108
1109         wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1110
1111         wqe->u.init.type = FW_RI_TYPE_INIT;
1112         wqe->u.init.mpareqbit_p2ptype =
1113                 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1114                 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1115         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1116         if (qhp->attr.mpa_attr.recv_marker_enabled)
1117                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1118         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1119                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1120         if (qhp->attr.mpa_attr.crc_enabled)
1121                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1122
1123         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1124                             FW_RI_QP_RDMA_WRITE_ENABLE |
1125                             FW_RI_QP_BIND_ENABLE;
1126         if (!qhp->ibqp.uobject)
1127                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1128                                      FW_RI_QP_STAG0_ENABLE;
1129         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1130         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1131         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1132         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1133         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1134         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1135         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1136         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1137         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1138         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1139         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1140         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1141         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1142                                          rhp->rdev.lldi.vr->rq.start);
1143         if (qhp->attr.mpa_attr.initiator)
1144                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1145
1146         ret = c4iw_ofld_send(&rhp->rdev, skb);
1147         if (ret)
1148                 goto out;
1149
1150         ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1151                                   qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1152 out:
1153         PDBG("%s ret %d\n", __func__, ret);
1154         return ret;
1155 }
1156
1157 /*
1158  * Called by the library when the qp has user dbs disabled due to
1159  * a DB_FULL condition.  This function will single-thread all user
1160  * DB rings to avoid overflowing the hw db-fifo.
1161  */
1162 static int ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 inc)
1163 {
1164         int delay = db_delay_usecs;
1165
1166         mutex_lock(&qhp->rhp->db_mutex);
1167         do {
1168
1169                 /*
1170                  * The interrupt threshold is dbfifo_int_thresh << 6. So
1171                  * make sure we don't cross that and generate an interrupt.
1172                  */
1173                 if (cxgb4_dbfifo_count(qhp->rhp->rdev.lldi.ports[0], 1) <
1174                     (qhp->rhp->rdev.lldi.dbfifo_int_thresh << 5)) {
1175                         writel(QID(qid) | PIDX(inc), qhp->wq.db);
1176                         break;
1177                 }
1178                 set_current_state(TASK_UNINTERRUPTIBLE);
1179                 schedule_timeout(usecs_to_jiffies(delay));
1180                 delay = min(delay << 1, 2000);
1181         } while (1);
1182         mutex_unlock(&qhp->rhp->db_mutex);
1183         return 0;
1184 }
1185
1186 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1187                    enum c4iw_qp_attr_mask mask,
1188                    struct c4iw_qp_attributes *attrs,
1189                    int internal)
1190 {
1191         int ret = 0;
1192         struct c4iw_qp_attributes newattr = qhp->attr;
1193         int disconnect = 0;
1194         int terminate = 0;
1195         int abort = 0;
1196         int free = 0;
1197         struct c4iw_ep *ep = NULL;
1198
1199         PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1200              qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1201              (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1202
1203         mutex_lock(&qhp->mutex);
1204
1205         /* Process attr changes if in IDLE */
1206         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1207                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1208                         ret = -EIO;
1209                         goto out;
1210                 }
1211                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1212                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1213                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1214                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1215                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1216                         newattr.enable_bind = attrs->enable_bind;
1217                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1218                         if (attrs->max_ord > c4iw_max_read_depth) {
1219                                 ret = -EINVAL;
1220                                 goto out;
1221                         }
1222                         newattr.max_ord = attrs->max_ord;
1223                 }
1224                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1225                         if (attrs->max_ird > c4iw_max_read_depth) {
1226                                 ret = -EINVAL;
1227                                 goto out;
1228                         }
1229                         newattr.max_ird = attrs->max_ird;
1230                 }
1231                 qhp->attr = newattr;
1232         }
1233
1234         if (mask & C4IW_QP_ATTR_SQ_DB) {
1235                 ret = ring_kernel_db(qhp, qhp->wq.sq.qid, attrs->sq_db_inc);
1236                 goto out;
1237         }
1238         if (mask & C4IW_QP_ATTR_RQ_DB) {
1239                 ret = ring_kernel_db(qhp, qhp->wq.rq.qid, attrs->rq_db_inc);
1240                 goto out;
1241         }
1242
1243         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1244                 goto out;
1245         if (qhp->attr.state == attrs->next_state)
1246                 goto out;
1247
1248         switch (qhp->attr.state) {
1249         case C4IW_QP_STATE_IDLE:
1250                 switch (attrs->next_state) {
1251                 case C4IW_QP_STATE_RTS:
1252                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1253                                 ret = -EINVAL;
1254                                 goto out;
1255                         }
1256                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1257                                 ret = -EINVAL;
1258                                 goto out;
1259                         }
1260                         qhp->attr.mpa_attr = attrs->mpa_attr;
1261                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1262                         qhp->ep = qhp->attr.llp_stream_handle;
1263                         set_state(qhp, C4IW_QP_STATE_RTS);
1264
1265                         /*
1266                          * Ref the endpoint here and deref when we
1267                          * disassociate the endpoint from the QP.  This
1268                          * happens in CLOSING->IDLE transition or *->ERROR
1269                          * transition.
1270                          */
1271                         c4iw_get_ep(&qhp->ep->com);
1272                         ret = rdma_init(rhp, qhp);
1273                         if (ret)
1274                                 goto err;
1275                         break;
1276                 case C4IW_QP_STATE_ERROR:
1277                         set_state(qhp, C4IW_QP_STATE_ERROR);
1278                         flush_qp(qhp);
1279                         break;
1280                 default:
1281                         ret = -EINVAL;
1282                         goto out;
1283                 }
1284                 break;
1285         case C4IW_QP_STATE_RTS:
1286                 switch (attrs->next_state) {
1287                 case C4IW_QP_STATE_CLOSING:
1288                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1289                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1290                         ep = qhp->ep;
1291                         if (!internal) {
1292                                 abort = 0;
1293                                 disconnect = 1;
1294                                 c4iw_get_ep(&qhp->ep->com);
1295                         }
1296                         if (qhp->ibqp.uobject)
1297                                 t4_set_wq_in_error(&qhp->wq);
1298                         ret = rdma_fini(rhp, qhp, ep);
1299                         if (ret)
1300                                 goto err;
1301                         break;
1302                 case C4IW_QP_STATE_TERMINATE:
1303                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1304                         qhp->attr.layer_etype = attrs->layer_etype;
1305                         qhp->attr.ecode = attrs->ecode;
1306                         if (qhp->ibqp.uobject)
1307                                 t4_set_wq_in_error(&qhp->wq);
1308                         ep = qhp->ep;
1309                         if (!internal)
1310                                 terminate = 1;
1311                         disconnect = 1;
1312                         c4iw_get_ep(&qhp->ep->com);
1313                         break;
1314                 case C4IW_QP_STATE_ERROR:
1315                         set_state(qhp, C4IW_QP_STATE_ERROR);
1316                         if (qhp->ibqp.uobject)
1317                                 t4_set_wq_in_error(&qhp->wq);
1318                         if (!internal) {
1319                                 abort = 1;
1320                                 disconnect = 1;
1321                                 ep = qhp->ep;
1322                                 c4iw_get_ep(&qhp->ep->com);
1323                         }
1324                         goto err;
1325                         break;
1326                 default:
1327                         ret = -EINVAL;
1328                         goto out;
1329                 }
1330                 break;
1331         case C4IW_QP_STATE_CLOSING:
1332                 if (!internal) {
1333                         ret = -EINVAL;
1334                         goto out;
1335                 }
1336                 switch (attrs->next_state) {
1337                 case C4IW_QP_STATE_IDLE:
1338                         flush_qp(qhp);
1339                         set_state(qhp, C4IW_QP_STATE_IDLE);
1340                         qhp->attr.llp_stream_handle = NULL;
1341                         c4iw_put_ep(&qhp->ep->com);
1342                         qhp->ep = NULL;
1343                         wake_up(&qhp->wait);
1344                         break;
1345                 case C4IW_QP_STATE_ERROR:
1346                         goto err;
1347                 default:
1348                         ret = -EINVAL;
1349                         goto err;
1350                 }
1351                 break;
1352         case C4IW_QP_STATE_ERROR:
1353                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1354                         ret = -EINVAL;
1355                         goto out;
1356                 }
1357                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1358                         ret = -EINVAL;
1359                         goto out;
1360                 }
1361                 set_state(qhp, C4IW_QP_STATE_IDLE);
1362                 break;
1363         case C4IW_QP_STATE_TERMINATE:
1364                 if (!internal) {
1365                         ret = -EINVAL;
1366                         goto out;
1367                 }
1368                 goto err;
1369                 break;
1370         default:
1371                 printk(KERN_ERR "%s in a bad state %d\n",
1372                        __func__, qhp->attr.state);
1373                 ret = -EINVAL;
1374                 goto err;
1375                 break;
1376         }
1377         goto out;
1378 err:
1379         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1380              qhp->wq.sq.qid);
1381
1382         /* disassociate the LLP connection */
1383         qhp->attr.llp_stream_handle = NULL;
1384         if (!ep)
1385                 ep = qhp->ep;
1386         qhp->ep = NULL;
1387         set_state(qhp, C4IW_QP_STATE_ERROR);
1388         free = 1;
1389         abort = 1;
1390         wake_up(&qhp->wait);
1391         BUG_ON(!ep);
1392         flush_qp(qhp);
1393 out:
1394         mutex_unlock(&qhp->mutex);
1395
1396         if (terminate)
1397                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1398
1399         /*
1400          * If disconnect is 1, then we need to initiate a disconnect
1401          * on the EP.  This can be a normal close (RTS->CLOSING) or
1402          * an abnormal close (RTS/CLOSING->ERROR).
1403          */
1404         if (disconnect) {
1405                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1406                                                          GFP_KERNEL);
1407                 c4iw_put_ep(&ep->com);
1408         }
1409
1410         /*
1411          * If free is 1, then we've disassociated the EP from the QP
1412          * and we need to dereference the EP.
1413          */
1414         if (free)
1415                 c4iw_put_ep(&ep->com);
1416         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1417         return ret;
1418 }
1419
1420 static int enable_qp_db(int id, void *p, void *data)
1421 {
1422         struct c4iw_qp *qp = p;
1423
1424         t4_enable_wq_db(&qp->wq);
1425         return 0;
1426 }
1427
1428 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1429 {
1430         struct c4iw_dev *rhp;
1431         struct c4iw_qp *qhp;
1432         struct c4iw_qp_attributes attrs;
1433         struct c4iw_ucontext *ucontext;
1434
1435         qhp = to_c4iw_qp(ib_qp);
1436         rhp = qhp->rhp;
1437
1438         attrs.next_state = C4IW_QP_STATE_ERROR;
1439         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1440                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1441         else
1442                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1443         wait_event(qhp->wait, !qhp->ep);
1444
1445         spin_lock_irq(&rhp->lock);
1446         remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1447         rhp->qpcnt--;
1448         BUG_ON(rhp->qpcnt < 0);
1449         if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) {
1450                 rhp->rdev.stats.db_state_transitions++;
1451                 rhp->db_state = NORMAL;
1452                 idr_for_each(&rhp->qpidr, enable_qp_db, NULL);
1453         }
1454         spin_unlock_irq(&rhp->lock);
1455         atomic_dec(&qhp->refcnt);
1456         wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1457
1458         ucontext = ib_qp->uobject ?
1459                    to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1460         destroy_qp(&rhp->rdev, &qhp->wq,
1461                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1462
1463         PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1464         kfree(qhp);
1465         return 0;
1466 }
1467
1468 static int disable_qp_db(int id, void *p, void *data)
1469 {
1470         struct c4iw_qp *qp = p;
1471
1472         t4_disable_wq_db(&qp->wq);
1473         return 0;
1474 }
1475
1476 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1477                              struct ib_udata *udata)
1478 {
1479         struct c4iw_dev *rhp;
1480         struct c4iw_qp *qhp;
1481         struct c4iw_pd *php;
1482         struct c4iw_cq *schp;
1483         struct c4iw_cq *rchp;
1484         struct c4iw_create_qp_resp uresp;
1485         int sqsize, rqsize;
1486         struct c4iw_ucontext *ucontext;
1487         int ret;
1488         struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1489
1490         PDBG("%s ib_pd %p\n", __func__, pd);
1491
1492         if (attrs->qp_type != IB_QPT_RC)
1493                 return ERR_PTR(-EINVAL);
1494
1495         php = to_c4iw_pd(pd);
1496         rhp = php->rhp;
1497         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1498         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1499         if (!schp || !rchp)
1500                 return ERR_PTR(-EINVAL);
1501
1502         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1503                 return ERR_PTR(-EINVAL);
1504
1505         rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1506         if (rqsize > T4_MAX_RQ_SIZE)
1507                 return ERR_PTR(-E2BIG);
1508
1509         sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1510         if (sqsize > T4_MAX_SQ_SIZE)
1511                 return ERR_PTR(-E2BIG);
1512
1513         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1514
1515
1516         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1517         if (!qhp)
1518                 return ERR_PTR(-ENOMEM);
1519         qhp->wq.sq.size = sqsize;
1520         qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1521         qhp->wq.rq.size = rqsize;
1522         qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1523
1524         if (ucontext) {
1525                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1526                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1527         }
1528
1529         PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1530              __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1531
1532         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1533                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1534         if (ret)
1535                 goto err1;
1536
1537         attrs->cap.max_recv_wr = rqsize - 1;
1538         attrs->cap.max_send_wr = sqsize - 1;
1539         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1540
1541         qhp->rhp = rhp;
1542         qhp->attr.pd = php->pdid;
1543         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1544         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1545         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1546         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1547         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1548         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1549         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1550         qhp->attr.state = C4IW_QP_STATE_IDLE;
1551         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1552         qhp->attr.enable_rdma_read = 1;
1553         qhp->attr.enable_rdma_write = 1;
1554         qhp->attr.enable_bind = 1;
1555         qhp->attr.max_ord = 1;
1556         qhp->attr.max_ird = 1;
1557         spin_lock_init(&qhp->lock);
1558         mutex_init(&qhp->mutex);
1559         init_waitqueue_head(&qhp->wait);
1560         atomic_set(&qhp->refcnt, 1);
1561
1562         spin_lock_irq(&rhp->lock);
1563         if (rhp->db_state != NORMAL)
1564                 t4_disable_wq_db(&qhp->wq);
1565         if (++rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) {
1566                 rhp->rdev.stats.db_state_transitions++;
1567                 rhp->db_state = FLOW_CONTROL;
1568                 idr_for_each(&rhp->qpidr, disable_qp_db, NULL);
1569         }
1570         ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1571         spin_unlock_irq(&rhp->lock);
1572         if (ret)
1573                 goto err2;
1574
1575         if (udata) {
1576                 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1577                 if (!mm1) {
1578                         ret = -ENOMEM;
1579                         goto err3;
1580                 }
1581                 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1582                 if (!mm2) {
1583                         ret = -ENOMEM;
1584                         goto err4;
1585                 }
1586                 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1587                 if (!mm3) {
1588                         ret = -ENOMEM;
1589                         goto err5;
1590                 }
1591                 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1592                 if (!mm4) {
1593                         ret = -ENOMEM;
1594                         goto err6;
1595                 }
1596                 if (t4_sq_onchip(&qhp->wq.sq)) {
1597                         mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1598                         if (!mm5) {
1599                                 ret = -ENOMEM;
1600                                 goto err7;
1601                         }
1602                         uresp.flags = C4IW_QPF_ONCHIP;
1603                 } else
1604                         uresp.flags = 0;
1605                 uresp.qid_mask = rhp->rdev.qpmask;
1606                 uresp.sqid = qhp->wq.sq.qid;
1607                 uresp.sq_size = qhp->wq.sq.size;
1608                 uresp.sq_memsize = qhp->wq.sq.memsize;
1609                 uresp.rqid = qhp->wq.rq.qid;
1610                 uresp.rq_size = qhp->wq.rq.size;
1611                 uresp.rq_memsize = qhp->wq.rq.memsize;
1612                 spin_lock(&ucontext->mmap_lock);
1613                 if (mm5) {
1614                         uresp.ma_sync_key = ucontext->key;
1615                         ucontext->key += PAGE_SIZE;
1616                 }
1617                 uresp.sq_key = ucontext->key;
1618                 ucontext->key += PAGE_SIZE;
1619                 uresp.rq_key = ucontext->key;
1620                 ucontext->key += PAGE_SIZE;
1621                 uresp.sq_db_gts_key = ucontext->key;
1622                 ucontext->key += PAGE_SIZE;
1623                 uresp.rq_db_gts_key = ucontext->key;
1624                 ucontext->key += PAGE_SIZE;
1625                 spin_unlock(&ucontext->mmap_lock);
1626                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1627                 if (ret)
1628                         goto err8;
1629                 mm1->key = uresp.sq_key;
1630                 mm1->addr = qhp->wq.sq.phys_addr;
1631                 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1632                 insert_mmap(ucontext, mm1);
1633                 mm2->key = uresp.rq_key;
1634                 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1635                 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1636                 insert_mmap(ucontext, mm2);
1637                 mm3->key = uresp.sq_db_gts_key;
1638                 mm3->addr = qhp->wq.sq.udb;
1639                 mm3->len = PAGE_SIZE;
1640                 insert_mmap(ucontext, mm3);
1641                 mm4->key = uresp.rq_db_gts_key;
1642                 mm4->addr = qhp->wq.rq.udb;
1643                 mm4->len = PAGE_SIZE;
1644                 insert_mmap(ucontext, mm4);
1645                 if (mm5) {
1646                         mm5->key = uresp.ma_sync_key;
1647                         mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1648                                     + A_PCIE_MA_SYNC) & PAGE_MASK;
1649                         mm5->len = PAGE_SIZE;
1650                         insert_mmap(ucontext, mm5);
1651                 }
1652         }
1653         qhp->ibqp.qp_num = qhp->wq.sq.qid;
1654         init_timer(&(qhp->timer));
1655         PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1656              __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1657              qhp->wq.sq.qid);
1658         return &qhp->ibqp;
1659 err8:
1660         kfree(mm5);
1661 err7:
1662         kfree(mm4);
1663 err6:
1664         kfree(mm3);
1665 err5:
1666         kfree(mm2);
1667 err4:
1668         kfree(mm1);
1669 err3:
1670         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1671 err2:
1672         destroy_qp(&rhp->rdev, &qhp->wq,
1673                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1674 err1:
1675         kfree(qhp);
1676         return ERR_PTR(ret);
1677 }
1678
1679 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1680                       int attr_mask, struct ib_udata *udata)
1681 {
1682         struct c4iw_dev *rhp;
1683         struct c4iw_qp *qhp;
1684         enum c4iw_qp_attr_mask mask = 0;
1685         struct c4iw_qp_attributes attrs;
1686
1687         PDBG("%s ib_qp %p\n", __func__, ibqp);
1688
1689         /* iwarp does not support the RTR state */
1690         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1691                 attr_mask &= ~IB_QP_STATE;
1692
1693         /* Make sure we still have something left to do */
1694         if (!attr_mask)
1695                 return 0;
1696
1697         memset(&attrs, 0, sizeof attrs);
1698         qhp = to_c4iw_qp(ibqp);
1699         rhp = qhp->rhp;
1700
1701         attrs.next_state = c4iw_convert_state(attr->qp_state);
1702         attrs.enable_rdma_read = (attr->qp_access_flags &
1703                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
1704         attrs.enable_rdma_write = (attr->qp_access_flags &
1705                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1706         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1707
1708
1709         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1710         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1711                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1712                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1713                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1714
1715         /*
1716          * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1717          * ringing the queue db when we're in DB_FULL mode.
1718          */
1719         attrs.sq_db_inc = attr->sq_psn;
1720         attrs.rq_db_inc = attr->rq_psn;
1721         mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1722         mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1723
1724         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1725 }
1726
1727 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1728 {
1729         PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1730         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1731 }
1732
1733 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1734                      int attr_mask, struct ib_qp_init_attr *init_attr)
1735 {
1736         struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1737
1738         memset(attr, 0, sizeof *attr);
1739         memset(init_attr, 0, sizeof *init_attr);
1740         attr->qp_state = to_ib_qp_state(qhp->attr.state);
1741         return 0;
1742 }