2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <drm/i915_drm.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_dp_helper.h>
37 * _wait_for - magic (register) wait macro
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
44 #define _wait_for(COND, MS, W) ({ \
45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
48 if (time_after(jiffies, timeout__)) { \
53 if (W && drm_can_sleep()) { \
62 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
63 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
67 #define KHz(x) (1000*x)
68 #define MHz(x) KHz(1000*x)
71 * Display related stuff
74 /* store information about an Ixxx DVO */
75 /* The i830->i865 use multiple DVOs with multiple i2cs */
76 /* the i915, i945 have a single sDVO i2c bus - which is different */
78 /* maximum connectors per crtcs in the mode set */
79 #define INTELFB_CONN_LIMIT 4
81 #define INTEL_I2C_BUS_DVO 1
82 #define INTEL_I2C_BUS_SDVO 2
84 /* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86 #define INTEL_OUTPUT_UNUSED 0
87 #define INTEL_OUTPUT_ANALOG 1
88 #define INTEL_OUTPUT_DVO 2
89 #define INTEL_OUTPUT_SDVO 3
90 #define INTEL_OUTPUT_LVDS 4
91 #define INTEL_OUTPUT_TVOUT 5
92 #define INTEL_OUTPUT_HDMI 6
93 #define INTEL_OUTPUT_DISPLAYPORT 7
94 #define INTEL_OUTPUT_EDP 8
95 #define INTEL_OUTPUT_UNKNOWN 9
97 #define INTEL_DVO_CHIP_NONE 0
98 #define INTEL_DVO_CHIP_LVDS 1
99 #define INTEL_DVO_CHIP_TMDS 2
100 #define INTEL_DVO_CHIP_TVOUT 4
102 struct intel_framebuffer {
103 struct drm_framebuffer base;
104 struct drm_i915_gem_object *obj;
108 struct drm_fb_helper helper;
109 struct intel_framebuffer ifb;
110 struct list_head fbdev_list;
111 struct drm_display_mode *our_mode;
114 struct intel_encoder {
115 struct drm_encoder base;
117 * The new crtc this encoder will be driven from. Only differs from
118 * base->crtc while a modeset is in progress.
120 struct intel_crtc *new_crtc;
124 * Intel hw has only one MUX where encoders could be clone, hence a
125 * simple flag is enough to compute the possible_clones mask.
128 bool connectors_active;
129 void (*hot_plug)(struct intel_encoder *);
130 bool (*compute_config)(struct intel_encoder *,
131 struct intel_crtc_config *);
132 void (*pre_pll_enable)(struct intel_encoder *);
133 void (*pre_enable)(struct intel_encoder *);
134 void (*enable)(struct intel_encoder *);
135 void (*mode_set)(struct intel_encoder *intel_encoder);
136 void (*disable)(struct intel_encoder *);
137 void (*post_disable)(struct intel_encoder *);
138 /* Read out the current hw state of this connector, returning true if
139 * the encoder is active. If the encoder is enabled it also set the pipe
140 * it is connected to in the pipe parameter. */
141 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
142 /* Reconstructs the equivalent mode flags for the current hardware
144 void (*get_config)(struct intel_encoder *,
145 struct intel_crtc_config *pipe_config);
147 enum hpd_pin hpd_pin;
151 struct drm_display_mode *fixed_mode;
155 struct intel_connector {
156 struct drm_connector base;
158 * The fixed encoder this connector is connected to.
160 struct intel_encoder *encoder;
163 * The new encoder this connector will be driven. Only differs from
164 * encoder while a modeset is in progress.
166 struct intel_encoder *new_encoder;
168 /* Reads out the current hw, returning true if the connector is enabled
169 * and active (i.e. dpms ON state). */
170 bool (*get_hw_state)(struct intel_connector *);
172 /* Panel info for eDP and LVDS */
173 struct intel_panel panel;
175 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
178 /* since POLL and HPD connectors may use the same HPD line keep the native
179 state of connector->polled in case hotplug storm detection changes it */
183 typedef struct dpll {
195 struct intel_crtc_config {
196 struct drm_display_mode requested_mode;
197 struct drm_display_mode adjusted_mode;
198 /* This flag must be set by the encoder's compute_config callback if it
199 * changes the crtc timings in the mode to prevent the crtc fixup from
200 * overwriting them. Currently only lvds needs that. */
202 /* Whether to set up the PCH/FDI. Note that we never allow sharing
203 * between pch encoders and cpu encoders. */
204 bool has_pch_encoder;
206 /* CPU Transcoder for the pipe. Currently this can only differ from the
207 * pipe on Haswell (where we have a special eDP transcoder). */
208 enum transcoder cpu_transcoder;
211 * Use reduced/limited/broadcast rbg range, compressing from the full
212 * range fed into the crtcs.
214 bool limited_color_range;
216 /* DP has a bunch of special case unfortunately, so mark the pipe
221 * Enable dithering, used when the selected pipe bpp doesn't match the
226 /* Controls for the clock computation, to override various stages. */
229 /* SDVO TV has a bunch of special case. To make multifunction encoders
230 * work correctly, we need to track this at runtime.*/
234 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
235 * required. This is set in the 2nd loop of calling encoder's
236 * ->compute_config if the first pick doesn't work out.
240 /* Settings for the intel dpll used on pretty much everything but
245 struct intel_link_m_n dp_m_n;
247 * This is currently used by DP and HDMI encoders since those can have a
248 * target pixel clock != the port link clock (which is currently stored
249 * in adjusted_mode->clock).
251 int pixel_target_clock;
252 /* Used by SDVO (and if we ever fix it, HDMI). */
253 unsigned pixel_multiplier;
255 /* Panel fitter controls for gen2-gen4 + VLV */
259 u32 lvds_border_bits;
262 /* Panel fitter placement and size for Ironlake+ */
268 /* FDI configuration, only valid if has_pch_encoder is set. */
270 struct intel_link_m_n fdi_m_n;
274 struct drm_crtc base;
277 u8 lut_r[256], lut_g[256], lut_b[256];
279 * Whether the crtc and the connected output pipeline is active. Implies
280 * that crtc->enabled is set, i.e. the current mode configuration has
281 * some outputs connected to this crtc.
285 bool primary_disabled; /* is the crtc obscured by a plane? */
287 struct intel_overlay *overlay;
288 struct intel_unpin_work *unpin_work;
290 atomic_t unpin_work_count;
292 /* Display surface base address adjustement for pageflips. Note that on
293 * gen4+ this only adjusts up to a tile, offsets within a tile are
294 * handled in the hw itself (with the TILEOFF register). */
295 unsigned long dspaddr_offset;
297 struct drm_i915_gem_object *cursor_bo;
298 uint32_t cursor_addr;
299 int16_t cursor_x, cursor_y;
300 int16_t cursor_width, cursor_height;
303 struct intel_crtc_config config;
305 /* We can share PLLs across outputs if the timings match */
306 struct intel_pch_pll *pch_pll;
307 uint32_t ddi_pll_sel;
309 /* reset counter value when the last flip was submitted */
310 unsigned int reset_counter;
312 /* Access to these should be protected by dev_priv->irq_lock. */
313 bool cpu_fifo_underrun_disabled;
314 bool pch_fifo_underrun_disabled;
318 struct drm_plane base;
321 struct drm_i915_gem_object *obj;
324 u32 lut_r[1024], lut_g[1024], lut_b[1024];
326 unsigned int crtc_w, crtc_h;
327 uint32_t src_x, src_y;
328 uint32_t src_w, src_h;
329 void (*update_plane)(struct drm_plane *plane,
330 struct drm_framebuffer *fb,
331 struct drm_i915_gem_object *obj,
332 int crtc_x, int crtc_y,
333 unsigned int crtc_w, unsigned int crtc_h,
334 uint32_t x, uint32_t y,
335 uint32_t src_w, uint32_t src_h);
336 void (*disable_plane)(struct drm_plane *plane);
337 int (*update_colorkey)(struct drm_plane *plane,
338 struct drm_intel_sprite_colorkey *key);
339 void (*get_colorkey)(struct drm_plane *plane,
340 struct drm_intel_sprite_colorkey *key);
343 struct intel_watermark_params {
344 unsigned long fifo_size;
345 unsigned long max_wm;
346 unsigned long default_wm;
347 unsigned long guard_size;
348 unsigned long cacheline_size;
351 struct cxsr_latency {
354 unsigned long fsb_freq;
355 unsigned long mem_freq;
356 unsigned long display_sr;
357 unsigned long display_hpll_disable;
358 unsigned long cursor_sr;
359 unsigned long cursor_hpll_disable;
362 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
363 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
364 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
365 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
366 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
368 #define DIP_HEADER_SIZE 5
370 #define DIP_TYPE_AVI 0x82
371 #define DIP_VERSION_AVI 0x2
372 #define DIP_LEN_AVI 13
373 #define DIP_AVI_PR_1 0
374 #define DIP_AVI_PR_2 1
375 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
376 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
377 #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
379 #define DIP_TYPE_SPD 0x83
380 #define DIP_VERSION_SPD 0x1
381 #define DIP_LEN_SPD 25
382 #define DIP_SPD_UNKNOWN 0
383 #define DIP_SPD_DSTB 0x1
384 #define DIP_SPD_DVDP 0x2
385 #define DIP_SPD_DVHS 0x3
386 #define DIP_SPD_HDDVR 0x4
387 #define DIP_SPD_DVC 0x5
388 #define DIP_SPD_DSC 0x6
389 #define DIP_SPD_VCD 0x7
390 #define DIP_SPD_GAME 0x8
391 #define DIP_SPD_PC 0x9
392 #define DIP_SPD_BD 0xa
393 #define DIP_SPD_SCD 0xb
395 struct dip_infoframe {
396 uint8_t type; /* HB0 */
397 uint8_t ver; /* HB1 */
398 uint8_t len; /* HB2 - body len, not including checksum */
399 uint8_t ecc; /* Header ECC */
400 uint8_t checksum; /* PB0 */
403 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
405 /* PB2 - C 7:6, M 5:4, R 3:0 */
407 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
411 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
414 uint16_t top_bar_end;
415 uint16_t bottom_bar_start;
416 uint16_t left_bar_end;
417 uint16_t right_bar_start;
418 } __attribute__ ((packed)) avi;
423 } __attribute__ ((packed)) spd;
425 } __attribute__ ((packed)) body;
426 } __attribute__((packed));
431 uint32_t color_range;
432 bool color_range_auto;
435 enum hdmi_force_audio force_audio;
436 bool rgb_quant_range_selectable;
437 void (*write_infoframe)(struct drm_encoder *encoder,
438 struct dip_infoframe *frame);
439 void (*set_infoframes)(struct drm_encoder *encoder,
440 struct drm_display_mode *adjusted_mode);
443 #define DP_MAX_DOWNSTREAM_PORTS 0x10
444 #define DP_LINK_CONFIGURATION_SIZE 9
448 uint32_t aux_ch_ctl_reg;
450 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
452 enum hdmi_force_audio force_audio;
453 uint32_t color_range;
454 bool color_range_auto;
457 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
458 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
459 struct i2c_adapter adapter;
460 struct i2c_algo_dp_aux_data algo;
461 uint8_t train_set[4];
462 int panel_power_up_delay;
463 int panel_power_down_delay;
464 int panel_power_cycle_delay;
465 int backlight_on_delay;
466 int backlight_off_delay;
467 struct delayed_work panel_vdd_work;
469 struct intel_connector *attached_connector;
472 struct intel_digital_port {
473 struct intel_encoder base;
477 struct intel_hdmi hdmi;
481 vlv_dport_to_channel(struct intel_digital_port *dport)
483 switch (dport->port) {
493 static inline struct drm_crtc *
494 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
496 struct drm_i915_private *dev_priv = dev->dev_private;
497 return dev_priv->pipe_to_crtc_mapping[pipe];
500 static inline struct drm_crtc *
501 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
503 struct drm_i915_private *dev_priv = dev->dev_private;
504 return dev_priv->plane_to_crtc_mapping[plane];
507 struct intel_unpin_work {
508 struct work_struct work;
509 struct drm_crtc *crtc;
510 struct drm_i915_gem_object *old_fb_obj;
511 struct drm_i915_gem_object *pending_flip_obj;
512 struct drm_pending_vblank_event *event;
514 #define INTEL_FLIP_INACTIVE 0
515 #define INTEL_FLIP_PENDING 1
516 #define INTEL_FLIP_COMPLETE 2
517 bool enable_stall_check;
520 struct intel_fbc_work {
521 struct delayed_work work;
522 struct drm_crtc *crtc;
523 struct drm_framebuffer *fb;
527 int intel_pch_rawclk(struct drm_device *dev);
529 int intel_connector_update_modes(struct drm_connector *connector,
531 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
533 extern void intel_attach_force_audio_property(struct drm_connector *connector);
534 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
536 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
537 extern void intel_crt_init(struct drm_device *dev);
538 extern void intel_hdmi_init(struct drm_device *dev,
539 int hdmi_reg, enum port port);
540 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
541 struct intel_connector *intel_connector);
542 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
543 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
544 struct intel_crtc_config *pipe_config);
545 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
546 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
548 extern void intel_dvo_init(struct drm_device *dev);
549 extern void intel_tv_init(struct drm_device *dev);
550 extern void intel_mark_busy(struct drm_device *dev);
551 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
552 extern void intel_mark_idle(struct drm_device *dev);
553 extern bool intel_lvds_init(struct drm_device *dev);
554 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
555 extern void intel_dp_init(struct drm_device *dev, int output_reg,
557 extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
558 struct intel_connector *intel_connector);
559 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
560 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
561 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
562 extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
563 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
564 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
565 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
566 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
567 struct intel_crtc_config *pipe_config);
568 extern bool intel_dpd_is_edp(struct drm_device *dev);
569 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
570 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
571 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
572 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
573 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
574 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
575 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
576 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
580 extern int intel_panel_init(struct intel_panel *panel,
581 struct drm_display_mode *fixed_mode);
582 extern void intel_panel_fini(struct intel_panel *panel);
584 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
585 struct drm_display_mode *adjusted_mode);
586 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
587 struct intel_crtc_config *pipe_config,
589 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
590 struct intel_crtc_config *pipe_config,
592 extern void intel_panel_set_backlight(struct drm_device *dev,
594 extern int intel_panel_setup_backlight(struct drm_connector *connector);
595 extern void intel_panel_enable_backlight(struct drm_device *dev,
597 extern void intel_panel_disable_backlight(struct drm_device *dev);
598 extern void intel_panel_destroy_backlight(struct drm_device *dev);
599 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
601 struct intel_set_config {
602 struct drm_encoder **save_connector_encoders;
603 struct drm_crtc **save_encoder_crtcs;
609 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
610 int x, int y, struct drm_framebuffer *old_fb);
611 extern void intel_modeset_disable(struct drm_device *dev);
612 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
613 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
614 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
615 extern void intel_encoder_destroy(struct drm_encoder *encoder);
616 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
617 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
618 extern void intel_connector_dpms(struct drm_connector *, int mode);
619 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
620 extern void intel_modeset_check_state(struct drm_device *dev);
621 extern void intel_plane_restore(struct drm_plane *plane);
624 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
626 return to_intel_connector(connector)->encoder;
629 static inline struct intel_digital_port *
630 enc_to_dig_port(struct drm_encoder *encoder)
632 return container_of(encoder, struct intel_digital_port, base.base);
635 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
637 return &enc_to_dig_port(encoder)->dp;
640 static inline struct intel_digital_port *
641 dp_to_dig_port(struct intel_dp *intel_dp)
643 return container_of(intel_dp, struct intel_digital_port, dp);
646 static inline struct intel_digital_port *
647 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
649 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
652 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
653 struct intel_digital_port *port);
655 extern void intel_connector_attach_encoder(struct intel_connector *connector,
656 struct intel_encoder *encoder);
657 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
659 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
660 struct drm_crtc *crtc);
661 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
662 struct drm_file *file_priv);
663 extern enum transcoder
664 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
666 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
667 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
668 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
669 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
671 struct intel_load_detect_pipe {
672 struct drm_framebuffer *release_fb;
673 bool load_detect_temp;
676 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
677 struct drm_display_mode *mode,
678 struct intel_load_detect_pipe *old);
679 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
680 struct intel_load_detect_pipe *old);
682 extern void intelfb_restore(void);
683 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
684 u16 blue, int regno);
685 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
686 u16 *blue, int regno);
687 extern void intel_enable_clock_gating(struct drm_device *dev);
689 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
690 struct drm_i915_gem_object *obj,
691 struct intel_ring_buffer *pipelined);
692 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
694 extern int intel_framebuffer_init(struct drm_device *dev,
695 struct intel_framebuffer *ifb,
696 struct drm_mode_fb_cmd2 *mode_cmd,
697 struct drm_i915_gem_object *obj);
698 extern int intel_fbdev_init(struct drm_device *dev);
699 extern void intel_fbdev_initial_config(struct drm_device *dev);
700 extern void intel_fbdev_fini(struct drm_device *dev);
701 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
702 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
703 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
704 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
706 extern void intel_setup_overlay(struct drm_device *dev);
707 extern void intel_cleanup_overlay(struct drm_device *dev);
708 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
709 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
710 struct drm_file *file_priv);
711 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
712 struct drm_file *file_priv);
714 extern void intel_fb_output_poll_changed(struct drm_device *dev);
715 extern void intel_fb_restore_mode(struct drm_device *dev);
717 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
719 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
720 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
722 extern void intel_init_clock_gating(struct drm_device *dev);
723 extern void intel_suspend_hw(struct drm_device *dev);
724 extern void intel_write_eld(struct drm_encoder *encoder,
725 struct drm_display_mode *mode);
726 extern void intel_prepare_ddi(struct drm_device *dev);
727 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
728 extern void intel_ddi_init(struct drm_device *dev, enum port port);
730 /* For use by IVB LP watermark workaround in intel_sprite.c */
731 extern void intel_update_watermarks(struct drm_device *dev);
732 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
733 uint32_t sprite_width,
735 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
736 struct drm_display_mode *mode);
738 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
739 unsigned int tiling_mode,
743 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
744 struct drm_file *file_priv);
745 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
746 struct drm_file *file_priv);
748 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
749 extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
752 /* Power-related functions, located in intel_pm.c */
753 extern void intel_init_pm(struct drm_device *dev);
755 extern bool intel_fbc_enabled(struct drm_device *dev);
756 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
757 extern void intel_update_fbc(struct drm_device *dev);
759 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
760 extern void intel_gpu_ips_teardown(void);
762 extern bool intel_display_power_enabled(struct drm_device *dev,
763 enum intel_display_power_domain domain);
764 extern void intel_init_power_well(struct drm_device *dev);
765 extern void intel_set_power_well(struct drm_device *dev, bool enable);
766 extern void intel_enable_gt_powersave(struct drm_device *dev);
767 extern void intel_disable_gt_powersave(struct drm_device *dev);
768 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
769 extern void ironlake_teardown_rc6(struct drm_device *dev);
771 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
773 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
774 extern void intel_ddi_pll_init(struct drm_device *dev);
775 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
776 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
777 enum transcoder cpu_transcoder);
778 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
779 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
780 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
781 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
782 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
783 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
784 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
786 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
787 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
789 extern void intel_display_handle_reset(struct drm_device *dev);
790 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
793 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
794 enum transcoder pch_transcoder,
797 #endif /* __INTEL_DRV_H__ */