drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "sid.h"
  27 #include "r600_dpm.h"
  28 #include "si_dpm.h"
  29 #include "atom.h"
  30 #include <linux/math64.h>
  31 #include <linux/seq_file.h>
  32
  33 #define MC_CG_ARB_FREQ_F0           0x0a
  34 #define MC_CG_ARB_FREQ_F1           0x0b
  35 #define MC_CG_ARB_FREQ_F2           0x0c
  36 #define MC_CG_ARB_FREQ_F3           0x0d
  37
  38 #define SMC_RAM_END                 0x20000
  39
  40 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  41
  42 static const struct si_cac_config_reg cac_weights_tahiti[] =
  43 {
  44         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  45         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  46         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  47         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  48         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  49         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  50         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  54         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  55         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  56         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  57         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  58         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  59         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  60         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  61         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  62         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  63         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  64         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  65         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  66         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  67         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  68         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  75         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  76         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  77         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  79         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  80         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  81         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  82         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  83         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  84         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  85         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  86         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 104         { 0xFFFFFFFF }
 105 };
 106
 107 static const struct si_cac_config_reg lcac_tahiti[] =
 108 {
 109         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 110         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 111         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 112         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 113         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 114         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 115         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 116         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 117         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 118         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 119         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 120         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 123         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 124         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 125         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 126         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 127         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 128         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 129         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 130         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 133         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 134         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 137         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 138         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 139         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 140         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 141         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 142         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 143         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 144         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 145         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 146         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 147         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 148         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 149         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 150         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 151         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 152         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 153         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 154         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 155         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 156         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 157         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 158         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 161         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 162         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 163         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 164         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 165         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 166         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 167         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 168         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 169         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 173         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 174         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 175         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 176         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 177         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 178         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 179         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 180         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 183         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 184         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 185         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 186         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 187         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 188         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 189         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 190         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 191         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 192         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 195         { 0xFFFFFFFF }
 196
 197 };
 198
 199 static const struct si_cac_config_reg cac_override_tahiti[] =
 200 {
 201         { 0xFFFFFFFF }
 202 };
 203
 204 static const struct si_powertune_data powertune_data_tahiti =
 205 {
 206         ((1 << 16) | 27027),
 207         6,
 208         0,
 209         4,
 210         95,
 211         {
 212                 0UL,
 213                 0UL,
 214                 4521550UL,
 215                 309631529UL,
 216                 -1270850L,
 217                 4513710L,
 218                 40
 219         },
 220         595000000UL,
 221         12,
 222         {
 223                 0,
 224                 0,
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0
 231         },
 232         true
 233 };
 234
 235 static const struct si_dte_data dte_data_tahiti =
 236 {
 237         { 1159409, 0, 0, 0, 0 },
 238         { 777, 0, 0, 0, 0 },
 239         2,
 240         54000,
 241         127000,
 242         25,
 243         2,
 244         10,
 245         13,
 246         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 247         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 248         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 249         85,
 250         false
 251 };
 252
 253 static const struct si_dte_data dte_data_tahiti_le =
 254 {
 255         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 256         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 257         0x5,
 258         0xAFC8,
 259         0x64,
 260         0x32,
 261         1,
 262         0,
 263         0x10,
 264         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 265         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 266         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 267         85,
 268         true
 269 };
 270
 271 static const struct si_dte_data dte_data_tahiti_pro =
 272 {
 273         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 274         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 275         5,
 276         45000,
 277         100,
 278         0xA,
 279         1,
 280         0,
 281         0x10,
 282         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 283         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 284         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 285         90,
 286         true
 287 };
 288
 289 static const struct si_dte_data dte_data_new_zealand =
 290 {
 291         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 292         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 293         0x5,
 294         0xAFC8,
 295         0x69,
 296         0x32,
 297         1,
 298         0,
 299         0x10,
 300         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 301         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 302         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 303         85,
 304         true
 305 };
 306
 307 static const struct si_dte_data dte_data_aruba_pro =
 308 {
 309         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 310         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 311         5,
 312         45000,
 313         100,
 314         0xA,
 315         1,
 316         0,
 317         0x10,
 318         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 319         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 320         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 321         90,
 322         true
 323 };
 324
 325 static const struct si_dte_data dte_data_malta =
 326 {
 327         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 328         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 329         5,
 330         45000,
 331         100,
 332         0xA,
 333         1,
 334         0,
 335         0x10,
 336         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 337         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 338         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 339         90,
 340         true
 341 };
 342
 343 struct si_cac_config_reg cac_weights_pitcairn[] =
 344 {
 345         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 346         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 347         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 348         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 349         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 350         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 351         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 352         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 353         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 354         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 355         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 356         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 357         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 358         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 359         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 360         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 361         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 363         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 364         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 365         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 366         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 367         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 368         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 369         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 370         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 371         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 372         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 373         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 374         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 376         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 377         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 378         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 379         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 380         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 381         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 382         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 383         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 384         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 385         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 386         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 405         { 0xFFFFFFFF }
 406 };
 407
 408 static const struct si_cac_config_reg lcac_pitcairn[] =
 409 {
 410         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 411         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 412         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 413         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 414         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 415         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 416         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 417         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 418         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 419         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 420         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 421         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 422         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 423         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 424         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 425         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 426         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 427         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 428         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 429         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 430         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 431         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 432         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 433         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 434         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 435         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 436         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 437         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 438         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 439         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 440         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 441         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 442         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 443         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 444         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 445         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 446         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 447         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 448         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 449         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 450         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 451         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 452         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 453         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 454         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 455         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 456         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 458         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 459         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 462         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 463         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 464         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 465         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 466         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 467         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 468         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 470         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 471         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 472         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 473         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 474         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 475         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 476         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 477         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 478         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 479         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 480         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 481         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 482         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 483         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 484         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 485         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 486         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 487         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 488         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 489         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 490         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 491         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 492         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 493         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 496         { 0xFFFFFFFF }
 497 };
 498
 499 static const struct si_cac_config_reg cac_override_pitcairn[] =
 500 {
 501     { 0xFFFFFFFF }
 502 };
 503
 504 static const struct si_powertune_data powertune_data_pitcairn =
 505 {
 506         ((1 << 16) | 27027),
 507         5,
 508         0,
 509         6,
 510         100,
 511         {
 512                 51600000UL,
 513                 1800000UL,
 514                 7194395UL,
 515                 309631529UL,
 516                 -1270850L,
 517                 4513710L,
 518                 100
 519         },
 520         117830498UL,
 521         12,
 522         {
 523                 0,
 524                 0,
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0
 531         },
 532         true
 533 };
 534
 535 static const struct si_dte_data dte_data_pitcairn =
 536 {
 537         { 0, 0, 0, 0, 0 },
 538         { 0, 0, 0, 0, 0 },
 539         0,
 540         0,
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 547         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         0,
 550         false
 551 };
 552
 553 static const struct si_dte_data dte_data_curacao_xt =
 554 {
 555         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 556         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 557         5,
 558         45000,
 559         100,
 560         0xA,
 561         1,
 562         0,
 563         0x10,
 564         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 565         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 566         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 567         90,
 568         true
 569 };
 570
 571 static const struct si_dte_data dte_data_curacao_pro =
 572 {
 573         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 574         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 575         5,
 576         45000,
 577         100,
 578         0xA,
 579         1,
 580         0,
 581         0x10,
 582         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 583         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 584         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 585         90,
 586         true
 587 };
 588
 589 static const struct si_dte_data dte_data_neptune_xt =
 590 {
 591         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 592         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 593         5,
 594         45000,
 595         100,
 596         0xA,
 597         1,
 598         0,
 599         0x10,
 600         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 601         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 602         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 603         90,
 604         true
 605 };
 606
 607 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 608 {
 609         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 610         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 611         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 612         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 613         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 614         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 615         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 616         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 617         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 618         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 619         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 620         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 621         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 622         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 623         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 624         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 625         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 626         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 627         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 628         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 629         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 630         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 631         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 632         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 633         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 634         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 635         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 636         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 637         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 638         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 639         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 640         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 641         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 642         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 643         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 644         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 645         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 646         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 647         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 648         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 649         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 650         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 651         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 652         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 669         { 0xFFFFFFFF }
 670 };
 671
 672 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 673 {
 674         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 675         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 676         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 677         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 678         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 679         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 680         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 681         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 682         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 683         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 684         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 685         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 686         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 687         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 688         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 689         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 690         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 691         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 692         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 693         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 694         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 695         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 696         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 697         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 698         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 699         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 700         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 701         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 702         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 703         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 704         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 705         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 706         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 707         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 708         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 709         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 710         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 711         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 712         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 713         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 714         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 715         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 716         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 717         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 734         { 0xFFFFFFFF }
 735 };
 736
 737 static const struct si_cac_config_reg cac_weights_heathrow[] =
 738 {
 739         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 740         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 741         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 743         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 745         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 746         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 747         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 748         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 749         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 750         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 751         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 752         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 753         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 754         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 755         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 756         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 757         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 758         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 759         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 760         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 761         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 762         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 763         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 764         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 765         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 766         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 767         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 768         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 769         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 770         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 771         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 772         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 773         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 774         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 775         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 776         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 777         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 778         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 779         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 780         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 781         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 782         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 799         { 0xFFFFFFFF }
 800 };
 801
 802 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 803 {
 804         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 805         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 806         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 808         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 810         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 811         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 812         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 813         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 814         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 815         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 816         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 817         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 818         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 819         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 820         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 821         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 822         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 823         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 824         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 825         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 826         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 827         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 828         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 829         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 830         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 831         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 832         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 833         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 834         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 835         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 836         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 837         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 838         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 839         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 840         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 841         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 842         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 843         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 844         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 845         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 846         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 847         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 864         { 0xFFFFFFFF }
 865 };
 866
 867 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 868 {
 869         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 870         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 871         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 873         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 875         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 876         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 877         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 878         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 879         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 880         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 881         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 882         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 883         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 884         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 885         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 886         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 887         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 888         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 889         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 890         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 891         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 892         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 893         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 894         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 895         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 896         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 897         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 898         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 899         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 900         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 901         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 902         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 903         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 904         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 905         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 906         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 907         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 908         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 909         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 910         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 911         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 912         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 929         { 0xFFFFFFFF }
 930 };
 931
 932 static const struct si_cac_config_reg lcac_cape_verde[] =
 933 {
 934         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 935         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 936         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 937         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 938         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 939         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 940         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 941         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 942         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 943         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 944         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 945         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 947         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 948         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 949         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 950         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 951         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 952         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 953         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 954         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 955         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 959         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 962         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 963         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 964         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 965         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 966         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 967         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 968         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 969         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 970         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 971         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 972         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 973         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 974         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 975         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 976         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 977         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 979         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 980         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 981         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0xFFFFFFFF }
 989 };
 990
 991 static const struct si_cac_config_reg cac_override_cape_verde[] =
 992 {
 993     { 0xFFFFFFFF }
 994 };
 995
 996 static const struct si_powertune_data powertune_data_cape_verde =
 997 {
 998         ((1 << 16) | 0x6993),
 999         5,
1000         0,
1001         7,
1002         105,
1003         {
1004                 0UL,
1005                 0UL,
1006                 7194395UL,
1007                 309631529UL,
1008                 -1270850L,
1009                 4513710L,
1010                 100
1011         },
1012         117830498UL,
1013         12,
1014         {
1015                 0,
1016                 0,
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0
1023         },
1024         true
1025 };
1026
1027 static const struct si_dte_data dte_data_cape_verde =
1028 {
1029         { 0, 0, 0, 0, 0 },
1030         { 0, 0, 0, 0, 0 },
1031         0,
1032         0,
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         0,
1042         false
1043 };
1044
1045 static const struct si_dte_data dte_data_venus_xtx =
1046 {
1047         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1048         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1049         5,
1050         55000,
1051         0x69,
1052         0xA,
1053         1,
1054         0,
1055         0x3,
1056         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         90,
1060         true
1061 };
1062
1063 static const struct si_dte_data dte_data_venus_xt =
1064 {
1065         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1066         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1067         5,
1068         55000,
1069         0x69,
1070         0xA,
1071         1,
1072         0,
1073         0x3,
1074         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         90,
1078         true
1079 };
1080
1081 static const struct si_dte_data dte_data_venus_pro =
1082 {
1083         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1084         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1085         5,
1086         55000,
1087         0x69,
1088         0xA,
1089         1,
1090         0,
1091         0x3,
1092         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         90,
1096         true
1097 };
1098
1099 struct si_cac_config_reg cac_weights_oland[] =
1100 {
1101         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1102         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1103         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1104         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1105         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1106         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1107         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1108         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1110         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1111         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1112         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1113         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1114         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1115         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1116         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1117         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1118         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1119         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1120         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1121         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1122         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1123         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1124         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1125         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1126         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1127         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1128         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1129         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1130         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1131         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1132         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1133         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1134         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1135         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1136         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1137         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1138         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1139         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1141         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1142         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1144         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1161         { 0xFFFFFFFF }
1162 };
1163
1164 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1165 {
1166         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1167         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1168         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1169         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1170         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1171         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1172         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1173         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1175         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1176         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1177         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1178         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1179         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1180         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1181         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1182         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1183         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1184         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1185         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1186         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1187         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1188         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1189         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1190         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1191         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1192         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1193         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1194         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1195         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1196         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1197         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1198         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1199         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1200         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1201         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1202         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1203         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1204         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1206         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1207         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1209         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1213         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1226         { 0xFFFFFFFF }
1227 };
1228
1229 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1230 {
1231         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1232         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1233         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1235         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1238         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1240         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1241         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1242         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1243         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1244         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1245         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1246         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1247         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1248         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1249         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1250         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1251         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1252         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1253         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1254         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1255         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1256         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1257         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1258         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1259         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1260         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1261         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1262         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1263         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1264         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1265         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1266         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1267         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1268         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1269         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1271         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1272         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1274         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1278         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1291         { 0xFFFFFFFF }
1292 };
1293
1294 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1295 {
1296         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1297         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1298         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1300         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1303         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1305         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1306         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1307         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1308         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1309         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1310         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1311         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1312         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1313         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1314         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1315         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1316         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1317         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1318         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1319         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1320         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1321         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1322         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1323         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1324         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1325         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1326         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1327         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1328         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1329         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1330         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1331         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1332         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1333         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1334         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1336         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1337         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1339         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1343         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1356         { 0xFFFFFFFF }
1357 };
1358
1359 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1360 {
1361         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1362         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1363         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1365         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1368         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1370         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1371         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1372         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1373         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1374         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1375         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1376         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1377         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1378         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1379         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1380         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1381         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1382         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1383         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1384         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1385         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1386         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1387         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1388         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1389         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1390         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1391         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1392         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1393         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1394         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1395         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1396         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1397         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1398         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1399         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1401         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1402         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1404         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1408         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1421         { 0xFFFFFFFF }
1422 };
1423
1424 static const struct si_cac_config_reg lcac_oland[] =
1425 {
1426         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1427         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1428         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1431         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1437         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1439         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1443         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1455         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1457         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0xFFFFFFFF }
1469 };
1470
1471 static const struct si_cac_config_reg lcac_mars_pro[] =
1472 {
1473         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1474         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1475         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1478         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1484         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1490         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1502         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1504         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0xFFFFFFFF }
1516 };
1517
1518 static const struct si_cac_config_reg cac_override_oland[] =
1519 {
1520         { 0xFFFFFFFF }
1521 };
1522
1523 static const struct si_powertune_data powertune_data_oland =
1524 {
1525         ((1 << 16) | 0x6993),
1526         5,
1527         0,
1528         7,
1529         105,
1530         {
1531                 0UL,
1532                 0UL,
1533                 7194395UL,
1534                 309631529UL,
1535                 -1270850L,
1536                 4513710L,
1537                 100
1538         },
1539         117830498UL,
1540         12,
1541         {
1542                 0,
1543                 0,
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0
1550         },
1551         true
1552 };
1553
1554 static const struct si_powertune_data powertune_data_mars_pro =
1555 {
1556         ((1 << 16) | 0x6993),
1557         5,
1558         0,
1559         7,
1560         105,
1561         {
1562                 0UL,
1563                 0UL,
1564                 7194395UL,
1565                 309631529UL,
1566                 -1270850L,
1567                 4513710L,
1568                 100
1569         },
1570         117830498UL,
1571         12,
1572         {
1573                 0,
1574                 0,
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0
1581         },
1582         true
1583 };
1584
1585 static const struct si_dte_data dte_data_oland =
1586 {
1587         { 0, 0, 0, 0, 0 },
1588         { 0, 0, 0, 0, 0 },
1589         0,
1590         0,
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         0,
1600         false
1601 };
1602
1603 static const struct si_dte_data dte_data_mars_pro =
1604 {
1605         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1606         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1607         5,
1608         55000,
1609         105,
1610         0xA,
1611         1,
1612         0,
1613         0x10,
1614         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1615         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1616         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1617         90,
1618         true
1619 };
1620
1621 static const struct si_dte_data dte_data_sun_xt =
1622 {
1623         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1624         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1625         5,
1626         55000,
1627         105,
1628         0xA,
1629         1,
1630         0,
1631         0x10,
1632         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1633         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1634         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1635         90,
1636         true
1637 };
1638
1639
1640 static const struct si_cac_config_reg cac_weights_hainan[] =
1641 {
1642         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1643         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1644         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1645         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1646         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1647         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1648         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1649         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1650         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1652         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1653         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1654         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1655         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1656         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1657         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1658         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1659         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1660         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1661         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1662         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1663         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1664         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1665         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1666         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1667         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1668         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1669         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1670         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1671         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1673         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1677         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1678         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1679         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1680         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1681         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1682         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1683         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1684         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1685         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1686         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1702         { 0xFFFFFFFF }
1703 };
1704
1705 static const struct si_powertune_data powertune_data_hainan =
1706 {
1707         ((1 << 16) | 0x6993),
1708         5,
1709         0,
1710         9,
1711         105,
1712         {
1713                 0UL,
1714                 0UL,
1715                 7194395UL,
1716                 309631529UL,
1717                 -1270850L,
1718                 4513710L,
1719                 100
1720         },
1721         117830498UL,
1722         12,
1723         {
1724                 0,
1725                 0,
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0
1732         },
1733         true
1734 };
1735
1736 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1737 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1738 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1739 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1740
1741 static int si_populate_voltage_value(struct radeon_device *rdev,
1742                                      const struct atom_voltage_table *table,
1743                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1744 static int si_get_std_voltage_value(struct radeon_device *rdev,
1745                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1746                                     u16 *std_voltage);
1747 static int si_write_smc_soft_register(struct radeon_device *rdev,
1748                                       u16 reg_offset, u32 value);
1749 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1750                                          struct rv7xx_pl *pl,
1751                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1752 static int si_calculate_sclk_params(struct radeon_device *rdev,
1753                                     u32 engine_clock,
1754                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1755
1756 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1757 {
1758         struct si_power_info *pi = rdev->pm.dpm.priv;
1759
1760         return pi;
1761 }
1762
1763 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1764                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1765 {
1766         s64 kt, kv, leakage_w, i_leakage, vddc;
1767         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1768
1769         i_leakage = drm_int2fixp(ileakage / 100);
1770         vddc = div64_s64(drm_int2fixp(v), 1000);
1771         temperature = div64_s64(drm_int2fixp(t), 1000);
1772
1773         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1774         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1775         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1776         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1777         t_ref = drm_int2fixp(coeff->t_ref);
1778
1779         kt = drm_fixp_div(drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, temperature)),
1780                           drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, t_ref)));
1781         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1782
1783         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1784
1785         *leakage = drm_fixp2int(leakage_w * 1000);
1786 }
1787
1788 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1789                                              const struct ni_leakage_coeffients *coeff,
1790                                              u16 v,
1791                                              s32 t,
1792                                              u32 i_leakage,
1793                                              u32 *leakage)
1794 {
1795         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1796 }
1797
1798 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1799                                                const u32 fixed_kt, u16 v,
1800                                                u32 ileakage, u32 *leakage)
1801 {
1802         s64 kt, kv, leakage_w, i_leakage, vddc;
1803
1804         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1805         vddc = div64_s64(drm_int2fixp(v), 1000);
1806
1807         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1808         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1809                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1810
1811         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1812
1813         *leakage = drm_fixp2int(leakage_w * 1000);
1814 }
1815
1816 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1817                                        const struct ni_leakage_coeffients *coeff,
1818                                        const u32 fixed_kt,
1819                                        u16 v,
1820                                        u32 i_leakage,
1821                                        u32 *leakage)
1822 {
1823         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1824 }
1825
1826
1827 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1828                                    struct si_dte_data *dte_data)
1829 {
1830         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1831         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1832         u32 k = dte_data->k;
1833         u32 t_max = dte_data->max_t;
1834         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1835         u32 t_0 = dte_data->t0;
1836         u32 i;
1837
1838         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1839                 dte_data->tdep_count = 3;
1840
1841                 for (i = 0; i < k; i++) {
1842                         dte_data->r[i] =
1843                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1844                                 (p_limit2  * (u32)100);
1845                 }
1846
1847                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1848
1849                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1850                         dte_data->tdep_r[i] = dte_data->r[4];
1851                 }
1852         } else {
1853                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1854         }
1855 }
1856
1857 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1858 {
1859         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1860         struct si_power_info *si_pi = si_get_pi(rdev);
1861         bool update_dte_from_pl2 = false;
1862
1863         if (rdev->family == CHIP_TAHITI) {
1864                 si_pi->cac_weights = cac_weights_tahiti;
1865                 si_pi->lcac_config = lcac_tahiti;
1866                 si_pi->cac_override = cac_override_tahiti;
1867                 si_pi->powertune_data = &powertune_data_tahiti;
1868                 si_pi->dte_data = dte_data_tahiti;
1869
1870                 switch (rdev->pdev->device) {
1871                 case 0x6798:
1872                         si_pi->dte_data.enable_dte_by_default = true;
1873                         break;
1874                 case 0x6799:
1875                         si_pi->dte_data = dte_data_new_zealand;
1876                         break;
1877                 case 0x6790:
1878                 case 0x6791:
1879                 case 0x6792:
1880                 case 0x679E:
1881                         si_pi->dte_data = dte_data_aruba_pro;
1882                         update_dte_from_pl2 = true;
1883                         break;
1884                 case 0x679B:
1885                         si_pi->dte_data = dte_data_malta;
1886                         update_dte_from_pl2 = true;
1887                         break;
1888                 case 0x679A:
1889                         si_pi->dte_data = dte_data_tahiti_pro;
1890                         update_dte_from_pl2 = true;
1891                         break;
1892                 default:
1893                         if (si_pi->dte_data.enable_dte_by_default == true)
1894                                 DRM_ERROR("DTE is not enabled!\n");
1895                         break;
1896                 }
1897         } else if (rdev->family == CHIP_PITCAIRN) {
1898                 switch (rdev->pdev->device) {
1899                 case 0x6810:
1900                 case 0x6818:
1901                         si_pi->cac_weights = cac_weights_pitcairn;
1902                         si_pi->lcac_config = lcac_pitcairn;
1903                         si_pi->cac_override = cac_override_pitcairn;
1904                         si_pi->powertune_data = &powertune_data_pitcairn;
1905                         si_pi->dte_data = dte_data_curacao_xt;
1906                         update_dte_from_pl2 = true;
1907                         break;
1908                 case 0x6819:
1909                 case 0x6811:
1910                         si_pi->cac_weights = cac_weights_pitcairn;
1911                         si_pi->lcac_config = lcac_pitcairn;
1912                         si_pi->cac_override = cac_override_pitcairn;
1913                         si_pi->powertune_data = &powertune_data_pitcairn;
1914                         si_pi->dte_data = dte_data_curacao_pro;
1915                         update_dte_from_pl2 = true;
1916                         break;
1917                 case 0x6800:
1918                 case 0x6806:
1919                         si_pi->cac_weights = cac_weights_pitcairn;
1920                         si_pi->lcac_config = lcac_pitcairn;
1921                         si_pi->cac_override = cac_override_pitcairn;
1922                         si_pi->powertune_data = &powertune_data_pitcairn;
1923                         si_pi->dte_data = dte_data_neptune_xt;
1924                         update_dte_from_pl2 = true;
1925                         break;
1926                 default:
1927                         si_pi->cac_weights = cac_weights_pitcairn;
1928                         si_pi->lcac_config = lcac_pitcairn;
1929                         si_pi->cac_override = cac_override_pitcairn;
1930                         si_pi->powertune_data = &powertune_data_pitcairn;
1931                         si_pi->dte_data = dte_data_pitcairn;
1932                 }
1933         } else if (rdev->family == CHIP_VERDE) {
1934                 si_pi->lcac_config = lcac_cape_verde;
1935                 si_pi->cac_override = cac_override_cape_verde;
1936                 si_pi->powertune_data = &powertune_data_cape_verde;
1937
1938                 switch (rdev->pdev->device) {
1939                 case 0x683B:
1940                 case 0x683F:
1941                 case 0x6829:
1942                 case 0x6835:
1943                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1944                         si_pi->dte_data = dte_data_cape_verde;
1945                         break;
1946                 case 0x6825:
1947                 case 0x6827:
1948                         si_pi->cac_weights = cac_weights_heathrow;
1949                         si_pi->dte_data = dte_data_cape_verde;
1950                         break;
1951                 case 0x6824:
1952                 case 0x682D:
1953                         si_pi->cac_weights = cac_weights_chelsea_xt;
1954                         si_pi->dte_data = dte_data_cape_verde;
1955                         break;
1956                 case 0x682F:
1957                         si_pi->cac_weights = cac_weights_chelsea_pro;
1958                         si_pi->dte_data = dte_data_cape_verde;
1959                         break;
1960                 case 0x6820:
1961                         si_pi->cac_weights = cac_weights_heathrow;
1962                         si_pi->dte_data = dte_data_venus_xtx;
1963                         break;
1964                 case 0x6821:
1965                         si_pi->cac_weights = cac_weights_heathrow;
1966                         si_pi->dte_data = dte_data_venus_xt;
1967                         break;
1968                 case 0x6823:
1969                         si_pi->cac_weights = cac_weights_chelsea_pro;
1970                         si_pi->dte_data = dte_data_venus_pro;
1971                         break;
1972                 case 0x682B:
1973                         si_pi->cac_weights = cac_weights_chelsea_pro;
1974                         si_pi->dte_data = dte_data_venus_pro;
1975                         break;
1976                 default:
1977                         si_pi->cac_weights = cac_weights_cape_verde;
1978                         si_pi->dte_data = dte_data_cape_verde;
1979                         break;
1980                 }
1981         } else if (rdev->family == CHIP_OLAND) {
1982                 switch (rdev->pdev->device) {
1983                 case 0x6601:
1984                 case 0x6621:
1985                 case 0x6603:
1986                         si_pi->cac_weights = cac_weights_mars_pro;
1987                         si_pi->lcac_config = lcac_mars_pro;
1988                         si_pi->cac_override = cac_override_oland;
1989                         si_pi->powertune_data = &powertune_data_mars_pro;
1990                         si_pi->dte_data = dte_data_mars_pro;
1991                         update_dte_from_pl2 = true;
1992                         break;
1993                 case 0x6600:
1994                 case 0x6606:
1995                 case 0x6620:
1996                         si_pi->cac_weights = cac_weights_mars_xt;
1997                         si_pi->lcac_config = lcac_mars_pro;
1998                         si_pi->cac_override = cac_override_oland;
1999                         si_pi->powertune_data = &powertune_data_mars_pro;
2000                         si_pi->dte_data = dte_data_mars_pro;
2001                         update_dte_from_pl2 = true;
2002                         break;
2003                 case 0x6611:
2004                         si_pi->cac_weights = cac_weights_oland_pro;
2005                         si_pi->lcac_config = lcac_mars_pro;
2006                         si_pi->cac_override = cac_override_oland;
2007                         si_pi->powertune_data = &powertune_data_mars_pro;
2008                         si_pi->dte_data = dte_data_mars_pro;
2009                         update_dte_from_pl2 = true;
2010                         break;
2011                 case 0x6610:
2012                         si_pi->cac_weights = cac_weights_oland_xt;
2013                         si_pi->lcac_config = lcac_mars_pro;
2014                         si_pi->cac_override = cac_override_oland;
2015                         si_pi->powertune_data = &powertune_data_mars_pro;
2016                         si_pi->dte_data = dte_data_mars_pro;
2017                         update_dte_from_pl2 = true;
2018                         break;
2019                 default:
2020                         si_pi->cac_weights = cac_weights_oland;
2021                         si_pi->lcac_config = lcac_oland;
2022                         si_pi->cac_override = cac_override_oland;
2023                         si_pi->powertune_data = &powertune_data_oland;
2024                         si_pi->dte_data = dte_data_oland;
2025                         break;
2026                 }
2027         } else if (rdev->family == CHIP_HAINAN) {
2028                 si_pi->cac_weights = cac_weights_hainan;
2029                 si_pi->lcac_config = lcac_oland;
2030                 si_pi->cac_override = cac_override_oland;
2031                 si_pi->powertune_data = &powertune_data_hainan;
2032                 si_pi->dte_data = dte_data_sun_xt;
2033                 update_dte_from_pl2 = true;
2034         } else {
2035                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2036                 return;
2037         }
2038
2039         ni_pi->enable_power_containment = false;
2040         ni_pi->enable_cac = false;
2041         ni_pi->enable_sq_ramping = false;
2042         si_pi->enable_dte = false;
2043
2044         if (si_pi->powertune_data->enable_powertune_by_default) {
2045                 ni_pi->enable_power_containment= true;
2046                 ni_pi->enable_cac = true;
2047                 if (si_pi->dte_data.enable_dte_by_default) {
2048                         si_pi->enable_dte = true;
2049                         if (update_dte_from_pl2)
2050                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2051
2052                 }
2053                 ni_pi->enable_sq_ramping = true;
2054         }
2055
2056         ni_pi->driver_calculate_cac_leakage = true;
2057         ni_pi->cac_configuration_required = true;
2058
2059         if (ni_pi->cac_configuration_required) {
2060                 ni_pi->support_cac_long_term_average = true;
2061                 si_pi->dyn_powertune_data.l2_lta_window_size =
2062                         si_pi->powertune_data->l2_lta_window_size_default;
2063                 si_pi->dyn_powertune_data.lts_truncate =
2064                         si_pi->powertune_data->lts_truncate_default;
2065         } else {
2066                 ni_pi->support_cac_long_term_average = false;
2067                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2068                 si_pi->dyn_powertune_data.lts_truncate = 0;
2069         }
2070
2071         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2072 }
2073
2074 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2075 {
2076         return 1;
2077 }
2078
2079 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2080 {
2081         u32 xclk;
2082         u32 wintime;
2083         u32 cac_window;
2084         u32 cac_window_size;
2085
2086         xclk = radeon_get_xclk(rdev);
2087
2088         if (xclk == 0)
2089                 return 0;
2090
2091         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2092         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2093
2094         wintime = (cac_window_size * 100) / xclk;
2095
2096         return wintime;
2097 }
2098
2099 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2100 {
2101         return power_in_watts;
2102 }
2103
2104 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2105                                             bool adjust_polarity,
2106                                             u32 tdp_adjustment,
2107                                             u32 *tdp_limit,
2108                                             u32 *near_tdp_limit)
2109 {
2110         u32 adjustment_delta, max_tdp_limit;
2111
2112         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2113                 return -EINVAL;
2114
2115         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2116
2117         if (adjust_polarity) {
2118                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2119                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2120         } else {
2121                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2122                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2123                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2124                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2125                 else
2126                         *near_tdp_limit = 0;
2127         }
2128
2129         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2130                 return -EINVAL;
2131         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2132                 return -EINVAL;
2133
2134         return 0;
2135 }
2136
2137 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2138                                       struct radeon_ps *radeon_state)
2139 {
2140         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2141         struct si_power_info *si_pi = si_get_pi(rdev);
2142
2143         if (ni_pi->enable_power_containment) {
2144                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2145                 PP_SIslands_PAPMParameters *papm_parm;
2146                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2147                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2148                 u32 tdp_limit;
2149                 u32 near_tdp_limit;
2150                 int ret;
2151
2152                 if (scaling_factor == 0)
2153                         return -EINVAL;
2154
2155                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2156
2157                 ret = si_calculate_adjusted_tdp_limits(rdev,
2158                                                        false, /* ??? */
2159                                                        rdev->pm.dpm.tdp_adjustment,
2160                                                        &tdp_limit,
2161                                                        &near_tdp_limit);
2162                 if (ret)
2163                         return ret;
2164
2165                 smc_table->dpm2Params.TDPLimit =
2166                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2167                 smc_table->dpm2Params.NearTDPLimit =
2168                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2169                 smc_table->dpm2Params.SafePowerLimit =
2170                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2171
2172                 ret = si_copy_bytes_to_smc(rdev,
2173                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2174                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2175                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2176                                            sizeof(u32) * 3,
2177                                            si_pi->sram_end);
2178                 if (ret)
2179                         return ret;
2180
2181                 if (si_pi->enable_ppm) {
2182                         papm_parm = &si_pi->papm_parm;
2183                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2184                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2185                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2186                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2187                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2188                         papm_parm->PlatformPowerLimit = 0xffffffff;
2189                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2190
2191                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2192                                                    (u8 *)papm_parm,
2193                                                    sizeof(PP_SIslands_PAPMParameters),
2194                                                    si_pi->sram_end);
2195                         if (ret)
2196                                 return ret;
2197                 }
2198         }
2199         return 0;
2200 }
2201
2202 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2203                                         struct radeon_ps *radeon_state)
2204 {
2205         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2206         struct si_power_info *si_pi = si_get_pi(rdev);
2207
2208         if (ni_pi->enable_power_containment) {
2209                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2210                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2211                 int ret;
2212
2213                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2214
2215                 smc_table->dpm2Params.NearTDPLimit =
2216                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2217                 smc_table->dpm2Params.SafePowerLimit =
2218                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2219
2220                 ret = si_copy_bytes_to_smc(rdev,
2221                                            (si_pi->state_table_start +
2222                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2223                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2224                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2225                                            sizeof(u32) * 2,
2226                                            si_pi->sram_end);
2227                 if (ret)
2228                         return ret;
2229         }
2230
2231         return 0;
2232 }
2233
2234 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2235                                                const u16 prev_std_vddc,
2236                                                const u16 curr_std_vddc)
2237 {
2238         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2239         u64 prev_vddc = (u64)prev_std_vddc;
2240         u64 curr_vddc = (u64)curr_std_vddc;
2241         u64 pwr_efficiency_ratio, n, d;
2242
2243         if ((prev_vddc == 0) || (curr_vddc == 0))
2244                 return 0;
2245
2246         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2247         d = prev_vddc * prev_vddc;
2248         pwr_efficiency_ratio = div64_u64(n, d);
2249
2250         if (pwr_efficiency_ratio > (u64)0xFFFF)
2251                 return 0;
2252
2253         return (u16)pwr_efficiency_ratio;
2254 }
2255
2256 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2257                                             struct radeon_ps *radeon_state)
2258 {
2259         struct si_power_info *si_pi = si_get_pi(rdev);
2260
2261         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2262             radeon_state->vclk && radeon_state->dclk)
2263                 return true;
2264
2265         return false;
2266 }
2267
2268 static int si_populate_power_containment_values(struct radeon_device *rdev,
2269                                                 struct radeon_ps *radeon_state,
2270                                                 SISLANDS_SMC_SWSTATE *smc_state)
2271 {
2272         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2273         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2274         struct ni_ps *state = ni_get_ps(radeon_state);
2275         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2276         u32 prev_sclk;
2277         u32 max_sclk;
2278         u32 min_sclk;
2279         u16 prev_std_vddc;
2280         u16 curr_std_vddc;
2281         int i;
2282         u16 pwr_efficiency_ratio;
2283         u8 max_ps_percent;
2284         bool disable_uvd_power_tune;
2285         int ret;
2286
2287         if (ni_pi->enable_power_containment == false)
2288                 return 0;
2289
2290         if (state->performance_level_count == 0)
2291                 return -EINVAL;
2292
2293         if (smc_state->levelCount != state->performance_level_count)
2294                 return -EINVAL;
2295
2296         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2297
2298         smc_state->levels[0].dpm2.MaxPS = 0;
2299         smc_state->levels[0].dpm2.NearTDPDec = 0;
2300         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2301         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2302         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2303
2304         for (i = 1; i < state->performance_level_count; i++) {
2305                 prev_sclk = state->performance_levels[i-1].sclk;
2306                 max_sclk  = state->performance_levels[i].sclk;
2307                 if (i == 1)
2308                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2309                 else
2310                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2311
2312                 if (prev_sclk > max_sclk)
2313                         return -EINVAL;
2314
2315                 if ((max_ps_percent == 0) ||
2316                     (prev_sclk == max_sclk) ||
2317                     disable_uvd_power_tune) {
2318                         min_sclk = max_sclk;
2319                 } else if (i == 1) {
2320                         min_sclk = prev_sclk;
2321                 } else {
2322                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2323                 }
2324
2325                 if (min_sclk < state->performance_levels[0].sclk)
2326                         min_sclk = state->performance_levels[0].sclk;
2327
2328                 if (min_sclk == 0)
2329                         return -EINVAL;
2330
2331                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2332                                                 state->performance_levels[i-1].vddc, &vddc);
2333                 if (ret)
2334                         return ret;
2335
2336                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2337                 if (ret)
2338                         return ret;
2339
2340                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2341                                                 state->performance_levels[i].vddc, &vddc);
2342                 if (ret)
2343                         return ret;
2344
2345                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2346                 if (ret)
2347                         return ret;
2348
2349                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2350                                                                            prev_std_vddc, curr_std_vddc);
2351
2352                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2353                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2354                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2355                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2356                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2357         }
2358
2359         return 0;
2360 }
2361
2362 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2363                                          struct radeon_ps *radeon_state,
2364                                          SISLANDS_SMC_SWSTATE *smc_state)
2365 {
2366         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2367         struct ni_ps *state = ni_get_ps(radeon_state);
2368         u32 sq_power_throttle, sq_power_throttle2;
2369         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2370         int i;
2371
2372         if (state->performance_level_count == 0)
2373                 return -EINVAL;
2374
2375         if (smc_state->levelCount != state->performance_level_count)
2376                 return -EINVAL;
2377
2378         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2379                 return -EINVAL;
2380
2381         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2382                 enable_sq_ramping = false;
2383
2384         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2385                 enable_sq_ramping = false;
2386
2387         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2388                 enable_sq_ramping = false;
2389
2390         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2391                 enable_sq_ramping = false;
2392
2393         if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2394                 enable_sq_ramping = false;
2395
2396         for (i = 0; i < state->performance_level_count; i++) {
2397                 sq_power_throttle = 0;
2398                 sq_power_throttle2 = 0;
2399
2400                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2401                     enable_sq_ramping) {
2402                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2403                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2404                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2405                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2406                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2407                 } else {
2408                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2409                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2410                 }
2411
2412                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2413                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2414         }
2415
2416         return 0;
2417 }
2418
2419 static int si_enable_power_containment(struct radeon_device *rdev,
2420                                        struct radeon_ps *radeon_new_state,
2421                                        bool enable)
2422 {
2423         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2424         PPSMC_Result smc_result;
2425         int ret = 0;
2426
2427         if (ni_pi->enable_power_containment) {
2428                 if (enable) {
2429                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2430                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2431                                 if (smc_result != PPSMC_Result_OK) {
2432                                         ret = -EINVAL;
2433                                         ni_pi->pc_enabled = false;
2434                                 } else {
2435                                         ni_pi->pc_enabled = true;
2436                                 }
2437                         }
2438                 } else {
2439                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2440                         if (smc_result != PPSMC_Result_OK)
2441                                 ret = -EINVAL;
2442                         ni_pi->pc_enabled = false;
2443                 }
2444         }
2445
2446         return ret;
2447 }
2448
2449 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2450 {
2451         struct si_power_info *si_pi = si_get_pi(rdev);
2452         int ret = 0;
2453         struct si_dte_data *dte_data = &si_pi->dte_data;
2454         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2455         u32 table_size;
2456         u8 tdep_count;
2457         u32 i;
2458
2459         if (dte_data == NULL)
2460                 si_pi->enable_dte = false;
2461
2462         if (si_pi->enable_dte == false)
2463                 return 0;
2464
2465         if (dte_data->k <= 0)
2466                 return -EINVAL;
2467
2468         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2469         if (dte_tables == NULL) {
2470                 si_pi->enable_dte = false;
2471                 return -ENOMEM;
2472         }
2473
2474         table_size = dte_data->k;
2475
2476         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2477                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2478
2479         tdep_count = dte_data->tdep_count;
2480         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2481                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2482
2483         dte_tables->K = cpu_to_be32(table_size);
2484         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2485         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2486         dte_tables->WindowSize = dte_data->window_size;
2487         dte_tables->temp_select = dte_data->temp_select;
2488         dte_tables->DTE_mode = dte_data->dte_mode;
2489         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2490
2491         if (tdep_count > 0)
2492                 table_size--;
2493
2494         for (i = 0; i < table_size; i++) {
2495                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2496                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2497         }
2498
2499         dte_tables->Tdep_count = tdep_count;
2500
2501         for (i = 0; i < (u32)tdep_count; i++) {
2502                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2503                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2504                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2505         }
2506
2507         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2508                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2509         kfree(dte_tables);
2510
2511         return ret;
2512 }
2513
2514 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2515                                           u16 *max, u16 *min)
2516 {
2517         struct si_power_info *si_pi = si_get_pi(rdev);
2518         struct radeon_cac_leakage_table *table =
2519                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2520         u32 i;
2521         u32 v0_loadline;
2522
2523
2524         if (table == NULL)
2525                 return -EINVAL;
2526
2527         *max = 0;
2528         *min = 0xFFFF;
2529
2530         for (i = 0; i < table->count; i++) {
2531                 if (table->entries[i].vddc > *max)
2532                         *max = table->entries[i].vddc;
2533                 if (table->entries[i].vddc < *min)
2534                         *min = table->entries[i].vddc;
2535         }
2536
2537         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2538                 return -EINVAL;
2539
2540         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2541
2542         if (v0_loadline > 0xFFFFUL)
2543                 return -EINVAL;
2544
2545         *min = (u16)v0_loadline;
2546
2547         if ((*min > *max) || (*max == 0) || (*min == 0))
2548                 return -EINVAL;
2549
2550         return 0;
2551 }
2552
2553 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2554 {
2555         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2556                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2557 }
2558
2559 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2560                                      PP_SIslands_CacConfig *cac_tables,
2561                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2562                                      u16 t0, u16 t_step)
2563 {
2564         struct si_power_info *si_pi = si_get_pi(rdev);
2565         u32 leakage;
2566         unsigned int i, j;
2567         s32 t;
2568         u32 smc_leakage;
2569         u32 scaling_factor;
2570         u16 voltage;
2571
2572         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2573
2574         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2575                 t = (1000 * (i * t_step + t0));
2576
2577                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2578                         voltage = vddc_max - (vddc_step * j);
2579
2580                         si_calculate_leakage_for_v_and_t(rdev,
2581                                                          &si_pi->powertune_data->leakage_coefficients,
2582                                                          voltage,
2583                                                          t,
2584                                                          si_pi->dyn_powertune_data.cac_leakage,
2585                                                          &leakage);
2586
2587                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2588
2589                         if (smc_leakage > 0xFFFF)
2590                                 smc_leakage = 0xFFFF;
2591
2592                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2593                                 cpu_to_be16((u16)smc_leakage);
2594                 }
2595         }
2596         return 0;
2597 }
2598
2599 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2600                                             PP_SIslands_CacConfig *cac_tables,
2601                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2602 {
2603         struct si_power_info *si_pi = si_get_pi(rdev);
2604         u32 leakage;
2605         unsigned int i, j;
2606         u32 smc_leakage;
2607         u32 scaling_factor;
2608         u16 voltage;
2609
2610         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2611
2612         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2613                 voltage = vddc_max - (vddc_step * j);
2614
2615                 si_calculate_leakage_for_v(rdev,
2616                                            &si_pi->powertune_data->leakage_coefficients,
2617                                            si_pi->powertune_data->fixed_kt,
2618                                            voltage,
2619                                            si_pi->dyn_powertune_data.cac_leakage,
2620                                            &leakage);
2621
2622                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2623
2624                 if (smc_leakage > 0xFFFF)
2625                         smc_leakage = 0xFFFF;
2626
2627                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2628                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2629                                 cpu_to_be16((u16)smc_leakage);
2630         }
2631         return 0;
2632 }
2633
2634 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2635 {
2636         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2637         struct si_power_info *si_pi = si_get_pi(rdev);
2638         PP_SIslands_CacConfig *cac_tables = NULL;
2639         u16 vddc_max, vddc_min, vddc_step;
2640         u16 t0, t_step;
2641         u32 load_line_slope, reg;
2642         int ret = 0;
2643         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2644
2645         if (ni_pi->enable_cac == false)
2646                 return 0;
2647
2648         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2649         if (!cac_tables)
2650                 return -ENOMEM;
2651
2652         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2653         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2654         WREG32(CG_CAC_CTRL, reg);
2655
2656         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2657         si_pi->dyn_powertune_data.dc_pwr_value =
2658                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2659         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2660         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2661
2662         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2663
2664         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2665         if (ret)
2666                 goto done_free;
2667
2668         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2669         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2670         t_step = 4;
2671         t0 = 60;
2672
2673         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2674                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2675                                                 vddc_max, vddc_min, vddc_step,
2676                                                 t0, t_step);
2677         else
2678                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2679                                                        vddc_max, vddc_min, vddc_step);
2680         if (ret)
2681                 goto done_free;
2682
2683         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2684
2685         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2686         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2687         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2688         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2689         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2690         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2691         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2692         cac_tables->calculation_repeats = cpu_to_be32(2);
2693         cac_tables->dc_cac = cpu_to_be32(0);
2694         cac_tables->log2_PG_LKG_SCALE = 12;
2695         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2696         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2697         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2698
2699         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2700                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2701
2702         if (ret)
2703                 goto done_free;
2704
2705         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2706
2707 done_free:
2708         if (ret) {
2709                 ni_pi->enable_cac = false;
2710                 ni_pi->enable_power_containment = false;
2711         }
2712
2713         kfree(cac_tables);
2714
2715         return 0;
2716 }
2717
2718 static int si_program_cac_config_registers(struct radeon_device *rdev,
2719                                            const struct si_cac_config_reg *cac_config_regs)
2720 {
2721         const struct si_cac_config_reg *config_regs = cac_config_regs;
2722         u32 data = 0, offset;
2723
2724         if (!config_regs)
2725                 return -EINVAL;
2726
2727         while (config_regs->offset != 0xFFFFFFFF) {
2728                 switch (config_regs->type) {
2729                 case SISLANDS_CACCONFIG_CGIND:
2730                         offset = SMC_CG_IND_START + config_regs->offset;
2731                         if (offset < SMC_CG_IND_END)
2732                                 data = RREG32_SMC(offset);
2733                         break;
2734                 default:
2735                         data = RREG32(config_regs->offset << 2);
2736                         break;
2737                 }
2738
2739                 data &= ~config_regs->mask;
2740                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2741
2742                 switch (config_regs->type) {
2743                 case SISLANDS_CACCONFIG_CGIND:
2744                         offset = SMC_CG_IND_START + config_regs->offset;
2745                         if (offset < SMC_CG_IND_END)
2746                                 WREG32_SMC(offset, data);
2747                         break;
2748                 default:
2749                         WREG32(config_regs->offset << 2, data);
2750                         break;
2751                 }
2752                 config_regs++;
2753         }
2754         return 0;
2755 }
2756
2757 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2758 {
2759         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2760         struct si_power_info *si_pi = si_get_pi(rdev);
2761         int ret;
2762
2763         if ((ni_pi->enable_cac == false) ||
2764             (ni_pi->cac_configuration_required == false))
2765                 return 0;
2766
2767         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2768         if (ret)
2769                 return ret;
2770         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2771         if (ret)
2772                 return ret;
2773         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2774         if (ret)
2775                 return ret;
2776
2777         return 0;
2778 }
2779
2780 static int si_enable_smc_cac(struct radeon_device *rdev,
2781                              struct radeon_ps *radeon_new_state,
2782                              bool enable)
2783 {
2784         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2785         struct si_power_info *si_pi = si_get_pi(rdev);
2786         PPSMC_Result smc_result;
2787         int ret = 0;
2788
2789         if (ni_pi->enable_cac) {
2790                 if (enable) {
2791                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2792                                 if (ni_pi->support_cac_long_term_average) {
2793                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2794                                         if (smc_result != PPSMC_Result_OK)
2795                                                 ni_pi->support_cac_long_term_average = false;
2796                                 }
2797
2798                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2799                                 if (smc_result != PPSMC_Result_OK) {
2800                                         ret = -EINVAL;
2801                                         ni_pi->cac_enabled = false;
2802                                 } else {
2803                                         ni_pi->cac_enabled = true;
2804                                 }
2805
2806                                 if (si_pi->enable_dte) {
2807                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2808                                         if (smc_result != PPSMC_Result_OK)
2809                                                 ret = -EINVAL;
2810                                 }
2811                         }
2812                 } else if (ni_pi->cac_enabled) {
2813                         if (si_pi->enable_dte)
2814                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2815
2816                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2817
2818                         ni_pi->cac_enabled = false;
2819
2820                         if (ni_pi->support_cac_long_term_average)
2821                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2822                 }
2823         }
2824         return ret;
2825 }
2826
2827 static int si_init_smc_spll_table(struct radeon_device *rdev)
2828 {
2829         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2830         struct si_power_info *si_pi = si_get_pi(rdev);
2831         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2832         SISLANDS_SMC_SCLK_VALUE sclk_params;
2833         u32 fb_div, p_div;
2834         u32 clk_s, clk_v;
2835         u32 sclk = 0;
2836         int ret = 0;
2837         u32 tmp;
2838         int i;
2839
2840         if (si_pi->spll_table_start == 0)
2841                 return -EINVAL;
2842
2843         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2844         if (spll_table == NULL)
2845                 return -ENOMEM;
2846
2847         for (i = 0; i < 256; i++) {
2848                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2849                 if (ret)
2850                         break;
2851
2852                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2853                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2854                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2855                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2856
2857                 fb_div &= ~0x00001FFF;
2858                 fb_div >>= 1;
2859                 clk_v >>= 6;
2860
2861                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2862                         ret = -EINVAL;
2863                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2864                         ret = -EINVAL;
2865                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2866                         ret = -EINVAL;
2867                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2868                         ret = -EINVAL;
2869
2870                 if (ret)
2871                         break;
2872
2873                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2874                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2875                 spll_table->freq[i] = cpu_to_be32(tmp);
2876
2877                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2878                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2879                 spll_table->ss[i] = cpu_to_be32(tmp);
2880
2881                 sclk += 512;
2882         }
2883
2884
2885         if (!ret)
2886                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2887                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2888                                            si_pi->sram_end);
2889
2890         if (ret)
2891                 ni_pi->enable_power_containment = false;
2892
2893         kfree(spll_table);
2894
2895         return ret;
2896 }
2897
2898 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2899                                         struct radeon_ps *rps)
2900 {
2901         struct ni_ps *ps = ni_get_ps(rps);
2902         struct radeon_clock_and_voltage_limits *max_limits;
2903         bool disable_mclk_switching;
2904         u32 mclk, sclk;
2905         u16 vddc, vddci;
2906         int i;
2907
2908         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2909             ni_dpm_vblank_too_short(rdev))
2910                 disable_mclk_switching = true;
2911         else
2912                 disable_mclk_switching = false;
2913
2914         if (rdev->pm.dpm.ac_power)
2915                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2916         else
2917                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2918
2919         for (i = ps->performance_level_count - 2; i >= 0; i--) {
2920                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2921                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2922         }
2923         if (rdev->pm.dpm.ac_power == false) {
2924                 for (i = 0; i < ps->performance_level_count; i++) {
2925                         if (ps->performance_levels[i].mclk > max_limits->mclk)
2926                                 ps->performance_levels[i].mclk = max_limits->mclk;
2927                         if (ps->performance_levels[i].sclk > max_limits->sclk)
2928                                 ps->performance_levels[i].sclk = max_limits->sclk;
2929                         if (ps->performance_levels[i].vddc > max_limits->vddc)
2930                                 ps->performance_levels[i].vddc = max_limits->vddc;
2931                         if (ps->performance_levels[i].vddci > max_limits->vddci)
2932                                 ps->performance_levels[i].vddci = max_limits->vddci;
2933                 }
2934         }
2935
2936         /* XXX validate the min clocks required for display */
2937
2938         if (disable_mclk_switching) {
2939                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
2940                 sclk = ps->performance_levels[0].sclk;
2941                 vddc = ps->performance_levels[0].vddc;
2942                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
2943         } else {
2944                 sclk = ps->performance_levels[0].sclk;
2945                 mclk = ps->performance_levels[0].mclk;
2946                 vddc = ps->performance_levels[0].vddc;
2947                 vddci = ps->performance_levels[0].vddci;
2948         }
2949
2950         /* adjusted low state */
2951         ps->performance_levels[0].sclk = sclk;
2952         ps->performance_levels[0].mclk = mclk;
2953         ps->performance_levels[0].vddc = vddc;
2954         ps->performance_levels[0].vddci = vddci;
2955
2956         for (i = 1; i < ps->performance_level_count; i++) {
2957                 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
2958                         ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
2959                 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
2960                         ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
2961         }
2962
2963         if (disable_mclk_switching) {
2964                 mclk = ps->performance_levels[0].mclk;
2965                 for (i = 1; i < ps->performance_level_count; i++) {
2966                         if (mclk < ps->performance_levels[i].mclk)
2967                                 mclk = ps->performance_levels[i].mclk;
2968                 }
2969                 for (i = 0; i < ps->performance_level_count; i++) {
2970                         ps->performance_levels[i].mclk = mclk;
2971                         ps->performance_levels[i].vddci = vddci;
2972                 }
2973         } else {
2974                 for (i = 1; i < ps->performance_level_count; i++) {
2975                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
2976                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
2977                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
2978                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
2979                 }
2980         }
2981
2982         for (i = 0; i < ps->performance_level_count; i++)
2983                 btc_adjust_clock_combinations(rdev, max_limits,
2984                                               &ps->performance_levels[i]);
2985
2986         for (i = 0; i < ps->performance_level_count; i++) {
2987                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2988                                                    ps->performance_levels[i].sclk,
2989                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
2990                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2991                                                    ps->performance_levels[i].mclk,
2992                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
2993                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2994                                                    ps->performance_levels[i].mclk,
2995                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
2996                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2997                                                    rdev->clock.current_dispclk,
2998                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
2999         }
3000
3001         for (i = 0; i < ps->performance_level_count; i++) {
3002                 btc_apply_voltage_delta_rules(rdev,
3003                                               max_limits->vddc, max_limits->vddci,
3004                                               &ps->performance_levels[i].vddc,
3005                                               &ps->performance_levels[i].vddci);
3006         }
3007
3008         ps->dc_compatible = true;
3009         for (i = 0; i < ps->performance_level_count; i++) {
3010                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3011                         ps->dc_compatible = false;
3012         }
3013
3014 }
3015
3016 #if 0
3017 static int si_read_smc_soft_register(struct radeon_device *rdev,
3018                                      u16 reg_offset, u32 *value)
3019 {
3020         struct si_power_info *si_pi = si_get_pi(rdev);
3021
3022         return si_read_smc_sram_dword(rdev,
3023                                       si_pi->soft_regs_start + reg_offset, value,
3024                                       si_pi->sram_end);
3025 }
3026 #endif
3027
3028 static int si_write_smc_soft_register(struct radeon_device *rdev,
3029                                       u16 reg_offset, u32 value)
3030 {
3031         struct si_power_info *si_pi = si_get_pi(rdev);
3032
3033         return si_write_smc_sram_dword(rdev,
3034                                        si_pi->soft_regs_start + reg_offset,
3035                                        value, si_pi->sram_end);
3036 }
3037
3038 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3039 {
3040         bool ret = false;
3041         u32 tmp, width, row, column, bank, density;
3042         bool is_memory_gddr5, is_special;
3043
3044         tmp = RREG32(MC_SEQ_MISC0);
3045         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3046         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3047                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3048
3049         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3050         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3051
3052         tmp = RREG32(MC_ARB_RAMCFG);
3053         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3054         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3055         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3056
3057         density = (1 << (row + column - 20 + bank)) * width;
3058
3059         if ((rdev->pdev->device == 0x6819) &&
3060             is_memory_gddr5 && is_special && (density == 0x400))
3061                 ret = true;
3062
3063         return ret;
3064 }
3065
3066 static void si_get_leakage_vddc(struct radeon_device *rdev)
3067 {
3068         struct si_power_info *si_pi = si_get_pi(rdev);
3069         u16 vddc, count = 0;
3070         int i, ret;
3071
3072         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3073                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3074
3075                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3076                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3077                         si_pi->leakage_voltage.entries[count].leakage_index =
3078                                 SISLANDS_LEAKAGE_INDEX0 + i;
3079                         count++;
3080                 }
3081         }
3082         si_pi->leakage_voltage.count = count;
3083 }
3084
3085 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3086                                                      u32 index, u16 *leakage_voltage)
3087 {
3088         struct si_power_info *si_pi = si_get_pi(rdev);
3089         int i;
3090
3091         if (leakage_voltage == NULL)
3092                 return -EINVAL;
3093
3094         if ((index & 0xff00) != 0xff00)
3095                 return -EINVAL;
3096
3097         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3098                 return -EINVAL;
3099
3100         if (index < SISLANDS_LEAKAGE_INDEX0)
3101                 return -EINVAL;
3102
3103         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3104                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3105                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3106                         return 0;
3107                 }
3108         }
3109         return -EAGAIN;
3110 }
3111
3112 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3113 {
3114         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3115         bool want_thermal_protection;
3116         enum radeon_dpm_event_src dpm_event_src;
3117
3118         switch (sources) {
3119         case 0:
3120         default:
3121                 want_thermal_protection = false;
3122                 break;
3123         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3124                 want_thermal_protection = true;
3125                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3126                 break;
3127         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3128                 want_thermal_protection = true;
3129                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3130                 break;
3131         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3132               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3133                 want_thermal_protection = true;
3134                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3135                 break;
3136         }
3137
3138         if (want_thermal_protection) {
3139                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3140                 if (pi->thermal_protection)
3141                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3142         } else {
3143                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3144         }
3145 }
3146
3147 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3148                                            enum radeon_dpm_auto_throttle_src source,
3149                                            bool enable)
3150 {
3151         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3152
3153         if (enable) {
3154                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3155                         pi->active_auto_throttle_sources |= 1 << source;
3156                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3157                 }
3158         } else {
3159                 if (pi->active_auto_throttle_sources & (1 << source)) {
3160                         pi->active_auto_throttle_sources &= ~(1 << source);
3161                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3162                 }
3163         }
3164 }
3165
3166 static void si_start_dpm(struct radeon_device *rdev)
3167 {
3168         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3169 }
3170
3171 static void si_stop_dpm(struct radeon_device *rdev)
3172 {
3173         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3174 }
3175
3176 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3177 {
3178         if (enable)
3179                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3180         else
3181                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3182
3183 }
3184
3185 #if 0
3186 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3187                                                u32 thermal_level)
3188 {
3189         PPSMC_Result ret;
3190
3191         if (thermal_level == 0) {
3192                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3193                 if (ret == PPSMC_Result_OK)
3194                         return 0;
3195                 else
3196                         return -EINVAL;
3197         }
3198         return 0;
3199 }
3200
3201 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3202 {
3203         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3204 }
3205 #endif
3206
3207 #if 0
3208 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3209 {
3210         if (ac_power)
3211                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3212                         0 : -EINVAL;
3213
3214         return 0;
3215 }
3216 #endif
3217
3218 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3219                                                       PPSMC_Msg msg, u32 parameter)
3220 {
3221         WREG32(SMC_SCRATCH0, parameter);
3222         return si_send_msg_to_smc(rdev, msg);
3223 }
3224
3225 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3226 {
3227         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3228                 return -EINVAL;
3229
3230         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3231                 0 : -EINVAL;
3232 }
3233
3234 int si_dpm_force_performance_level(struct radeon_device *rdev,
3235                                    enum radeon_dpm_forced_level level)
3236 {
3237         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3238         struct ni_ps *ps = ni_get_ps(rps);
3239         u32 levels;
3240
3241         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3242                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
3243                         return -EINVAL;
3244
3245                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3246                         return -EINVAL;
3247         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3248                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3249                         return -EINVAL;
3250
3251                 levels = ps->performance_level_count - 1;
3252                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3253                         return -EINVAL;
3254         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3255                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3256                         return -EINVAL;
3257
3258                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
3259                         return -EINVAL;
3260         }
3261
3262         rdev->pm.dpm.forced_level = level;
3263
3264         return 0;
3265 }
3266
3267 static int si_set_boot_state(struct radeon_device *rdev)
3268 {
3269         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3270                 0 : -EINVAL;
3271 }
3272
3273 static int si_set_sw_state(struct radeon_device *rdev)
3274 {
3275         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3276                 0 : -EINVAL;
3277 }
3278
3279 static int si_halt_smc(struct radeon_device *rdev)
3280 {
3281         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3282                 return -EINVAL;
3283
3284         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3285                 0 : -EINVAL;
3286 }
3287
3288 static int si_resume_smc(struct radeon_device *rdev)
3289 {
3290         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3291                 return -EINVAL;
3292
3293         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3294                 0 : -EINVAL;
3295 }
3296
3297 static void si_dpm_start_smc(struct radeon_device *rdev)
3298 {
3299         si_program_jump_on_start(rdev);
3300         si_start_smc(rdev);
3301         si_start_smc_clock(rdev);
3302 }
3303
3304 static void si_dpm_stop_smc(struct radeon_device *rdev)
3305 {
3306         si_reset_smc(rdev);
3307         si_stop_smc_clock(rdev);
3308 }
3309
3310 static int si_process_firmware_header(struct radeon_device *rdev)
3311 {
3312         struct si_power_info *si_pi = si_get_pi(rdev);
3313         u32 tmp;
3314         int ret;
3315
3316         ret = si_read_smc_sram_dword(rdev,
3317                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3318                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3319                                      &tmp, si_pi->sram_end);
3320         if (ret)
3321                 return ret;
3322
3323         si_pi->state_table_start = tmp;
3324
3325         ret = si_read_smc_sram_dword(rdev,
3326                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3327                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3328                                      &tmp, si_pi->sram_end);
3329         if (ret)
3330                 return ret;
3331
3332         si_pi->soft_regs_start = tmp;
3333
3334         ret = si_read_smc_sram_dword(rdev,
3335                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3336                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3337                                      &tmp, si_pi->sram_end);
3338         if (ret)
3339                 return ret;
3340
3341         si_pi->mc_reg_table_start = tmp;
3342
3343         ret = si_read_smc_sram_dword(rdev,
3344                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3345                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3346                                      &tmp, si_pi->sram_end);
3347         if (ret)
3348                 return ret;
3349
3350         si_pi->arb_table_start = tmp;
3351
3352         ret = si_read_smc_sram_dword(rdev,
3353                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3354                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3355                                      &tmp, si_pi->sram_end);
3356         if (ret)
3357                 return ret;
3358
3359         si_pi->cac_table_start = tmp;
3360
3361         ret = si_read_smc_sram_dword(rdev,
3362                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3363                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3364                                      &tmp, si_pi->sram_end);
3365         if (ret)
3366                 return ret;
3367
3368         si_pi->dte_table_start = tmp;
3369
3370         ret = si_read_smc_sram_dword(rdev,
3371                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3372                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3373                                      &tmp, si_pi->sram_end);
3374         if (ret)
3375                 return ret;
3376
3377         si_pi->spll_table_start = tmp;
3378
3379         ret = si_read_smc_sram_dword(rdev,
3380                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3381                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3382                                      &tmp, si_pi->sram_end);
3383         if (ret)
3384                 return ret;
3385
3386         si_pi->papm_cfg_table_start = tmp;
3387
3388         return ret;
3389 }
3390
3391 static void si_read_clock_registers(struct radeon_device *rdev)
3392 {
3393         struct si_power_info *si_pi = si_get_pi(rdev);
3394
3395         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3396         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3397         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3398         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3399         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3400         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3401         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3402         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3403         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3404         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3405         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3406         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3407         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3408         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3409         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3410 }
3411
3412 static void si_enable_thermal_protection(struct radeon_device *rdev,
3413                                           bool enable)
3414 {
3415         if (enable)
3416                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3417         else
3418                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3419 }
3420
3421 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3422 {
3423         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3424 }
3425
3426 #if 0
3427 static int si_enter_ulp_state(struct radeon_device *rdev)
3428 {
3429         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3430
3431         udelay(25000);
3432
3433         return 0;
3434 }
3435
3436 static int si_exit_ulp_state(struct radeon_device *rdev)
3437 {
3438         int i;
3439
3440         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3441
3442         udelay(7000);
3443
3444         for (i = 0; i < rdev->usec_timeout; i++) {
3445                 if (RREG32(SMC_RESP_0) == 1)
3446                         break;
3447                 udelay(1000);
3448         }
3449
3450         return 0;
3451 }
3452 #endif
3453
3454 static int si_notify_smc_display_change(struct radeon_device *rdev,
3455                                      bool has_display)
3456 {
3457         PPSMC_Msg msg = has_display ?
3458                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3459
3460         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3461                 0 : -EINVAL;
3462 }
3463
3464 static void si_program_response_times(struct radeon_device *rdev)
3465 {
3466         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3467         u32 vddc_dly, acpi_dly, vbi_dly;
3468         u32 reference_clock;
3469
3470         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3471
3472         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3473         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3474
3475         if (voltage_response_time == 0)
3476                 voltage_response_time = 1000;
3477
3478         acpi_delay_time = 15000;
3479         vbi_time_out = 100000;
3480
3481         reference_clock = radeon_get_xclk(rdev);
3482
3483         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3484         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3485         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3486
3487         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3488         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3489         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3490         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3491 }
3492
3493 static void si_program_ds_registers(struct radeon_device *rdev)
3494 {
3495         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3496         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3497
3498         if (eg_pi->sclk_deep_sleep) {
3499                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3500                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3501                          ~AUTOSCALE_ON_SS_CLEAR);
3502         }
3503 }
3504
3505 static void si_program_display_gap(struct radeon_device *rdev)
3506 {
3507         u32 tmp, pipe;
3508         int i;
3509
3510         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3511         if (rdev->pm.dpm.new_active_crtc_count > 0)
3512                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3513         else
3514                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3515
3516         if (rdev->pm.dpm.new_active_crtc_count > 1)
3517                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3518         else
3519                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3520
3521         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3522
3523         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3524         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3525
3526         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3527             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3528                 /* find the first active crtc */
3529                 for (i = 0; i < rdev->num_crtc; i++) {
3530                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3531                                 break;
3532                 }
3533                 if (i == rdev->num_crtc)
3534                         pipe = 0;
3535                 else
3536                         pipe = i;
3537
3538                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3539                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3540                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3541         }
3542
3543         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3544 }
3545
3546 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3547 {
3548         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3549
3550         if (enable) {
3551                 if (pi->sclk_ss)
3552                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3553         } else {
3554                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3555                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3556         }
3557 }
3558
3559 static void si_setup_bsp(struct radeon_device *rdev)
3560 {
3561         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3562         u32 xclk = radeon_get_xclk(rdev);
3563
3564         r600_calculate_u_and_p(pi->asi,
3565                                xclk,
3566                                16,
3567                                &pi->bsp,
3568                                &pi->bsu);
3569
3570         r600_calculate_u_and_p(pi->pasi,
3571                                xclk,
3572                                16,
3573                                &pi->pbsp,
3574                                &pi->pbsu);
3575
3576
3577         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3578         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3579
3580         WREG32(CG_BSP, pi->dsp);
3581 }
3582
3583 static void si_program_git(struct radeon_device *rdev)
3584 {
3585         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3586 }
3587
3588 static void si_program_tp(struct radeon_device *rdev)
3589 {
3590         int i;
3591         enum r600_td td = R600_TD_DFLT;
3592
3593         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3594                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3595
3596         if (td == R600_TD_AUTO)
3597                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3598         else
3599                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3600
3601         if (td == R600_TD_UP)
3602                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3603
3604         if (td == R600_TD_DOWN)
3605                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3606 }
3607
3608 static void si_program_tpp(struct radeon_device *rdev)
3609 {
3610         WREG32(CG_TPC, R600_TPC_DFLT);
3611 }
3612
3613 static void si_program_sstp(struct radeon_device *rdev)
3614 {
3615         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3616 }
3617
3618 static void si_enable_display_gap(struct radeon_device *rdev)
3619 {
3620         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3621
3622         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3623         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3624                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3625
3626         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3627         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3628                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3629         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3630 }
3631
3632 static void si_program_vc(struct radeon_device *rdev)
3633 {
3634         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3635
3636         WREG32(CG_FTV, pi->vrc);
3637 }
3638
3639 static void si_clear_vc(struct radeon_device *rdev)
3640 {
3641         WREG32(CG_FTV, 0);
3642 }
3643
3644 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3645 {
3646         u8 mc_para_index;
3647
3648         if (memory_clock < 10000)
3649                 mc_para_index = 0;
3650         else if (memory_clock >= 80000)
3651                 mc_para_index = 0x0f;
3652         else
3653                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3654         return mc_para_index;
3655 }
3656
3657 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3658 {
3659         u8 mc_para_index;
3660
3661         if (strobe_mode) {
3662                 if (memory_clock < 12500)
3663                         mc_para_index = 0x00;
3664                 else if (memory_clock > 47500)
3665                         mc_para_index = 0x0f;
3666                 else
3667                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3668         } else {
3669                 if (memory_clock < 65000)
3670                         mc_para_index = 0x00;
3671                 else if (memory_clock > 135000)
3672                         mc_para_index = 0x0f;
3673                 else
3674                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3675         }
3676         return mc_para_index;
3677 }
3678
3679 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3680 {
3681         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3682         bool strobe_mode = false;
3683         u8 result = 0;
3684
3685         if (mclk <= pi->mclk_strobe_mode_threshold)
3686                 strobe_mode = true;
3687
3688         if (pi->mem_gddr5)
3689                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3690         else
3691                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3692
3693         if (strobe_mode)
3694                 result |= SISLANDS_SMC_STROBE_ENABLE;
3695
3696         return result;
3697 }
3698
3699 static int si_upload_firmware(struct radeon_device *rdev)
3700 {
3701         struct si_power_info *si_pi = si_get_pi(rdev);
3702         int ret;
3703
3704         si_reset_smc(rdev);
3705         si_stop_smc_clock(rdev);
3706
3707         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3708
3709         return ret;
3710 }
3711
3712 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3713                                               const struct atom_voltage_table *table,
3714                                               const struct radeon_phase_shedding_limits_table *limits)
3715 {
3716         u32 data, num_bits, num_levels;
3717
3718         if ((table == NULL) || (limits == NULL))
3719                 return false;
3720
3721         data = table->mask_low;
3722
3723         num_bits = hweight32(data);
3724
3725         if (num_bits == 0)
3726                 return false;
3727
3728         num_levels = (1 << num_bits);
3729
3730         if (table->count != num_levels)
3731                 return false;
3732
3733         if (limits->count != (num_levels - 1))
3734                 return false;
3735
3736         return true;
3737 }
3738
3739 static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3740                                                      struct atom_voltage_table *voltage_table)
3741 {
3742         unsigned int i, diff;
3743
3744         if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS)
3745                 return;
3746
3747         diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS;
3748
3749         for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++)
3750                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3751
3752         voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS;
3753 }
3754
3755 static int si_construct_voltage_tables(struct radeon_device *rdev)
3756 {
3757         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3758         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3759         struct si_power_info *si_pi = si_get_pi(rdev);
3760         int ret;
3761
3762         ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3763                                             VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3764         if (ret)
3765                 return ret;
3766
3767         if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3768                 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table);
3769
3770         if (eg_pi->vddci_control) {
3771                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3772                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3773                 if (ret)
3774                         return ret;
3775
3776                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3777                         si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table);
3778         }
3779
3780         if (pi->mvdd_control) {
3781                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3782                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3783
3784                 if (ret) {
3785                         pi->mvdd_control = false;
3786                         return ret;
3787                 }
3788
3789                 if (si_pi->mvdd_voltage_table.count == 0) {
3790                         pi->mvdd_control = false;
3791                         return -EINVAL;
3792                 }
3793
3794                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3795                         si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table);
3796         }
3797
3798         if (si_pi->vddc_phase_shed_control) {
3799                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3800                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3801                 if (ret)
3802                         si_pi->vddc_phase_shed_control = false;
3803
3804                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3805                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3806                         si_pi->vddc_phase_shed_control = false;
3807         }
3808
3809         return 0;
3810 }
3811
3812 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3813                                           const struct atom_voltage_table *voltage_table,
3814                                           SISLANDS_SMC_STATETABLE *table)
3815 {
3816         unsigned int i;
3817
3818         for (i = 0; i < voltage_table->count; i++)
3819                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3820 }
3821
3822 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3823                                           SISLANDS_SMC_STATETABLE *table)
3824 {
3825         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3826         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3827         struct si_power_info *si_pi = si_get_pi(rdev);
3828         u8 i;
3829
3830         if (eg_pi->vddc_voltage_table.count) {
3831                 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3832                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3833                         cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3834
3835                 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3836                         if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3837                                 table->maxVDDCIndexInPPTable = i;
3838                                 break;
3839                         }
3840                 }
3841         }
3842
3843         if (eg_pi->vddci_voltage_table.count) {
3844                 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3845
3846                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3847                         cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3848         }
3849
3850
3851         if (si_pi->mvdd_voltage_table.count) {
3852                 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3853
3854                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3855                         cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3856         }
3857
3858         if (si_pi->vddc_phase_shed_control) {
3859                 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3860                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3861                         si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3862
3863                         table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3864                                 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3865
3866                         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3867                                                    (u32)si_pi->vddc_phase_shed_table.phase_delay);
3868                 } else {
3869                         si_pi->vddc_phase_shed_control = false;
3870                 }
3871         }
3872
3873         return 0;
3874 }
3875
3876 static int si_populate_voltage_value(struct radeon_device *rdev,
3877                                      const struct atom_voltage_table *table,
3878                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3879 {
3880         unsigned int i;
3881
3882         for (i = 0; i < table->count; i++) {
3883                 if (value <= table->entries[i].value) {
3884                         voltage->index = (u8)i;
3885                         voltage->value = cpu_to_be16(table->entries[i].value);
3886                         break;
3887                 }
3888         }
3889
3890         if (i >= table->count)
3891                 return -EINVAL;
3892
3893         return 0;
3894 }
3895
3896 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
3897                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3898 {
3899         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3900         struct si_power_info *si_pi = si_get_pi(rdev);
3901
3902         if (pi->mvdd_control) {
3903                 if (mclk <= pi->mvdd_split_frequency)
3904                         voltage->index = 0;
3905                 else
3906                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
3907
3908                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
3909         }
3910         return 0;
3911 }
3912
3913 static int si_get_std_voltage_value(struct radeon_device *rdev,
3914                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
3915                                     u16 *std_voltage)
3916 {
3917         u16 v_index;
3918         bool voltage_found = false;
3919         *std_voltage = be16_to_cpu(voltage->value);
3920
3921         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
3922                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
3923                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
3924                                 return -EINVAL;
3925
3926                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3927                                 if (be16_to_cpu(voltage->value) ==
3928                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3929                                         voltage_found = true;
3930                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3931                                                 *std_voltage =
3932                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3933                                         else
3934                                                 *std_voltage =
3935                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3936                                         break;
3937                                 }
3938                         }
3939
3940                         if (!voltage_found) {
3941                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3942                                         if (be16_to_cpu(voltage->value) <=
3943                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3944                                                 voltage_found = true;
3945                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3946                                                         *std_voltage =
3947                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3948                                                 else
3949                                                         *std_voltage =
3950                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3951                                                 break;
3952                                         }
3953                                 }
3954                         }
3955                 } else {
3956                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3957                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
3958                 }
3959         }
3960
3961         return 0;
3962 }
3963
3964 static int si_populate_std_voltage_value(struct radeon_device *rdev,
3965                                          u16 value, u8 index,
3966                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3967 {
3968         voltage->index = index;
3969         voltage->value = cpu_to_be16(value);
3970
3971         return 0;
3972 }
3973
3974 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
3975                                             const struct radeon_phase_shedding_limits_table *limits,
3976                                             u16 voltage, u32 sclk, u32 mclk,
3977                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
3978 {
3979         unsigned int i;
3980
3981         for (i = 0; i < limits->count; i++) {
3982                 if ((voltage <= limits->entries[i].voltage) &&
3983                     (sclk <= limits->entries[i].sclk) &&
3984                     (mclk <= limits->entries[i].mclk))
3985                         break;
3986         }
3987
3988         smc_voltage->phase_settings = (u8)i;
3989
3990         return 0;
3991 }
3992
3993 static int si_init_arb_table_index(struct radeon_device *rdev)
3994 {
3995         struct si_power_info *si_pi = si_get_pi(rdev);
3996         u32 tmp;
3997         int ret;
3998
3999         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4000         if (ret)
4001                 return ret;
4002
4003         tmp &= 0x00FFFFFF;
4004         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4005
4006         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4007 }
4008
4009 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4010 {
4011         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4012 }
4013
4014 static int si_reset_to_default(struct radeon_device *rdev)
4015 {
4016         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4017                 0 : -EINVAL;
4018 }
4019
4020 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4021 {
4022         struct si_power_info *si_pi = si_get_pi(rdev);
4023         u32 tmp;
4024         int ret;
4025
4026         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4027                                      &tmp, si_pi->sram_end);
4028         if (ret)
4029                 return ret;
4030
4031         tmp = (tmp >> 24) & 0xff;
4032
4033         if (tmp == MC_CG_ARB_FREQ_F0)
4034                 return 0;
4035
4036         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4037 }
4038
4039 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4040                                             u32 engine_clock)
4041 {
4042         u32 dram_rows;
4043         u32 dram_refresh_rate;
4044         u32 mc_arb_rfsh_rate;
4045         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4046
4047         if (tmp >= 4)
4048                 dram_rows = 16384;
4049         else
4050                 dram_rows = 1 << (tmp + 10);
4051
4052         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4053         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4054
4055         return mc_arb_rfsh_rate;
4056 }
4057
4058 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4059                                                 struct rv7xx_pl *pl,
4060                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4061 {
4062         u32 dram_timing;
4063         u32 dram_timing2;
4064         u32 burst_time;
4065
4066         arb_regs->mc_arb_rfsh_rate =
4067                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4068
4069         radeon_atom_set_engine_dram_timings(rdev,
4070                                             pl->sclk,
4071                                             pl->mclk);
4072
4073         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4074         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4075         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4076
4077         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4078         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4079         arb_regs->mc_arb_burst_time = (u8)burst_time;
4080
4081         return 0;
4082 }
4083
4084 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4085                                                   struct radeon_ps *radeon_state,
4086                                                   unsigned int first_arb_set)
4087 {
4088         struct si_power_info *si_pi = si_get_pi(rdev);
4089         struct ni_ps *state = ni_get_ps(radeon_state);
4090         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4091         int i, ret = 0;
4092
4093         for (i = 0; i < state->performance_level_count; i++) {
4094                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4095                 if (ret)
4096                         break;
4097                 ret = si_copy_bytes_to_smc(rdev,
4098                                            si_pi->arb_table_start +
4099                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4100                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4101                                            (u8 *)&arb_regs,
4102                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4103                                            si_pi->sram_end);
4104                 if (ret)
4105                         break;
4106         }
4107
4108         return ret;
4109 }
4110
4111 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4112                                                struct radeon_ps *radeon_new_state)
4113 {
4114         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4115                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4116 }
4117
4118 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4119                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4120 {
4121         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4122         struct si_power_info *si_pi = si_get_pi(rdev);
4123
4124         if (pi->mvdd_control)
4125                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4126                                                  si_pi->mvdd_bootup_value, voltage);
4127
4128         return 0;
4129 }
4130
4131 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4132                                          struct radeon_ps *radeon_initial_state,
4133                                          SISLANDS_SMC_STATETABLE *table)
4134 {
4135         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4136         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4137         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4138         struct si_power_info *si_pi = si_get_pi(rdev);
4139         u32 reg;
4140         int ret;
4141
4142         table->initialState.levels[0].mclk.vDLL_CNTL =
4143                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4144         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4145                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4146         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4147                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4148         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4149                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4150         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4151                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4152         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4153                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4154         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4155                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4156         table->initialState.levels[0].mclk.vMPLL_SS =
4157                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4158         table->initialState.levels[0].mclk.vMPLL_SS2 =
4159                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4160
4161         table->initialState.levels[0].mclk.mclk_value =
4162                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4163
4164         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4165                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4166         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4167                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4168         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4169                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4170         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4171                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4172         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4173                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4174         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4175                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4176
4177         table->initialState.levels[0].sclk.sclk_value =
4178                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4179
4180         table->initialState.levels[0].arbRefreshState =
4181                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4182
4183         table->initialState.levels[0].ACIndex = 0;
4184
4185         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4186                                         initial_state->performance_levels[0].vddc,
4187                                         &table->initialState.levels[0].vddc);
4188
4189         if (!ret) {
4190                 u16 std_vddc;
4191
4192                 ret = si_get_std_voltage_value(rdev,
4193                                                &table->initialState.levels[0].vddc,
4194                                                &std_vddc);
4195                 if (!ret)
4196                         si_populate_std_voltage_value(rdev, std_vddc,
4197                                                       table->initialState.levels[0].vddc.index,
4198                                                       &table->initialState.levels[0].std_vddc);
4199         }
4200
4201         if (eg_pi->vddci_control)
4202                 si_populate_voltage_value(rdev,
4203                                           &eg_pi->vddci_voltage_table,
4204                                           initial_state->performance_levels[0].vddci,
4205                                           &table->initialState.levels[0].vddci);
4206
4207         if (si_pi->vddc_phase_shed_control)
4208                 si_populate_phase_shedding_value(rdev,
4209                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4210                                                  initial_state->performance_levels[0].vddc,
4211                                                  initial_state->performance_levels[0].sclk,
4212                                                  initial_state->performance_levels[0].mclk,
4213                                                  &table->initialState.levels[0].vddc);
4214
4215         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4216
4217         reg = CG_R(0xffff) | CG_L(0);
4218         table->initialState.levels[0].aT = cpu_to_be32(reg);
4219
4220         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4221
4222         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4223
4224         if (pi->mem_gddr5) {
4225                 table->initialState.levels[0].strobeMode =
4226                         si_get_strobe_mode_settings(rdev,
4227                                                     initial_state->performance_levels[0].mclk);
4228
4229                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4230                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4231                 else
4232                         table->initialState.levels[0].mcFlags =  0;
4233         }
4234
4235         table->initialState.levelCount = 1;
4236
4237         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4238
4239         table->initialState.levels[0].dpm2.MaxPS = 0;
4240         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4241         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4242         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4243         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4244
4245         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4246         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4247
4248         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4249         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4250
4251         return 0;
4252 }
4253
4254 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4255                                       SISLANDS_SMC_STATETABLE *table)
4256 {
4257         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4258         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4259         struct si_power_info *si_pi = si_get_pi(rdev);
4260         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4261         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4262         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4263         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4264         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4265         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4266         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4267         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4268         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4269         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4270         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4271         u32 reg;
4272         int ret;
4273
4274         table->ACPIState = table->initialState;
4275
4276         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4277
4278         if (pi->acpi_vddc) {
4279                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4280                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4281                 if (!ret) {
4282                         u16 std_vddc;
4283
4284                         ret = si_get_std_voltage_value(rdev,
4285                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4286                         if (!ret)
4287                                 si_populate_std_voltage_value(rdev, std_vddc,
4288                                                               table->ACPIState.levels[0].vddc.index,
4289                                                               &table->ACPIState.levels[0].std_vddc);
4290                 }
4291                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4292
4293                 if (si_pi->vddc_phase_shed_control) {
4294                         si_populate_phase_shedding_value(rdev,
4295                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4296                                                          pi->acpi_vddc,
4297                                                          0,
4298                                                          0,
4299                                                          &table->ACPIState.levels[0].vddc);
4300                 }
4301         } else {
4302                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4303                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4304                 if (!ret) {
4305                         u16 std_vddc;
4306
4307                         ret = si_get_std_voltage_value(rdev,
4308                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4309
4310                         if (!ret)
4311                                 si_populate_std_voltage_value(rdev, std_vddc,
4312                                                               table->ACPIState.levels[0].vddc.index,
4313                                                               &table->ACPIState.levels[0].std_vddc);
4314                 }
4315                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4316                                                                                     si_pi->sys_pcie_mask,
4317                                                                                     si_pi->boot_pcie_gen,
4318                                                                                     RADEON_PCIE_GEN1);
4319
4320                 if (si_pi->vddc_phase_shed_control)
4321                         si_populate_phase_shedding_value(rdev,
4322                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4323                                                          pi->min_vddc_in_table,
4324                                                          0,
4325                                                          0,
4326                                                          &table->ACPIState.levels[0].vddc);
4327         }
4328
4329         if (pi->acpi_vddc) {
4330                 if (eg_pi->acpi_vddci)
4331                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4332                                                   eg_pi->acpi_vddci,
4333                                                   &table->ACPIState.levels[0].vddci);
4334         }
4335
4336         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4337         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4338
4339         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4340
4341         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4342         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4343
4344         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4345                 cpu_to_be32(dll_cntl);
4346         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4347                 cpu_to_be32(mclk_pwrmgt_cntl);
4348         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4349                 cpu_to_be32(mpll_ad_func_cntl);
4350         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4351                 cpu_to_be32(mpll_dq_func_cntl);
4352         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4353                 cpu_to_be32(mpll_func_cntl);
4354         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4355                 cpu_to_be32(mpll_func_cntl_1);
4356         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4357                 cpu_to_be32(mpll_func_cntl_2);
4358         table->ACPIState.levels[0].mclk.vMPLL_SS =
4359                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4360         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4361                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4362
4363         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4364                 cpu_to_be32(spll_func_cntl);
4365         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4366                 cpu_to_be32(spll_func_cntl_2);
4367         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4368                 cpu_to_be32(spll_func_cntl_3);
4369         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4370                 cpu_to_be32(spll_func_cntl_4);
4371
4372         table->ACPIState.levels[0].mclk.mclk_value = 0;
4373         table->ACPIState.levels[0].sclk.sclk_value = 0;
4374
4375         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4376
4377         if (eg_pi->dynamic_ac_timing)
4378                 table->ACPIState.levels[0].ACIndex = 0;
4379
4380         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4381         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4382         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4383         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4384         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4385
4386         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4387         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4388
4389         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4390         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4391
4392         return 0;
4393 }
4394
4395 static int si_populate_ulv_state(struct radeon_device *rdev,
4396                                  SISLANDS_SMC_SWSTATE *state)
4397 {
4398         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4399         struct si_power_info *si_pi = si_get_pi(rdev);
4400         struct si_ulv_param *ulv = &si_pi->ulv;
4401         u32 sclk_in_sr = 1350; /* ??? */
4402         int ret;
4403
4404         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4405                                             &state->levels[0]);
4406         if (!ret) {
4407                 if (eg_pi->sclk_deep_sleep) {
4408                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4409                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4410                         else
4411                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4412                 }
4413                 if (ulv->one_pcie_lane_in_ulv)
4414                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4415                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4416                 state->levels[0].ACIndex = 1;
4417                 state->levels[0].std_vddc = state->levels[0].vddc;
4418                 state->levelCount = 1;
4419
4420                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4421         }
4422
4423         return ret;
4424 }
4425
4426 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4427 {
4428         struct si_power_info *si_pi = si_get_pi(rdev);
4429         struct si_ulv_param *ulv = &si_pi->ulv;
4430         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4431         int ret;
4432
4433         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4434                                                    &arb_regs);
4435         if (ret)
4436                 return ret;
4437
4438         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4439                                    ulv->volt_change_delay);
4440
4441         ret = si_copy_bytes_to_smc(rdev,
4442                                    si_pi->arb_table_start +
4443                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4444                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4445                                    (u8 *)&arb_regs,
4446                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4447                                    si_pi->sram_end);
4448
4449         return ret;
4450 }
4451
4452 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4453 {
4454         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4455
4456         pi->mvdd_split_frequency = 30000;
4457 }
4458
4459 static int si_init_smc_table(struct radeon_device *rdev)
4460 {
4461         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4462         struct si_power_info *si_pi = si_get_pi(rdev);
4463         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4464         const struct si_ulv_param *ulv = &si_pi->ulv;
4465         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4466         int ret;
4467         u32 lane_width;
4468         u32 vr_hot_gpio;
4469
4470         si_populate_smc_voltage_tables(rdev, table);
4471
4472         switch (rdev->pm.int_thermal_type) {
4473         case THERMAL_TYPE_SI:
4474         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4475                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4476                 break;
4477         case THERMAL_TYPE_NONE:
4478                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4479                 break;
4480         default:
4481                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4482                 break;
4483         }
4484
4485         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4486                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4487
4488         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4489                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4490                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4491         }
4492
4493         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4494                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4495
4496         if (pi->mem_gddr5)
4497                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4498
4499         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4500                 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4501
4502         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4503                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4504                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4505                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4506                                            vr_hot_gpio);
4507         }
4508
4509         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4510         if (ret)
4511                 return ret;
4512
4513         ret = si_populate_smc_acpi_state(rdev, table);
4514         if (ret)
4515                 return ret;
4516
4517         table->driverState = table->initialState;
4518
4519         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4520                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4521         if (ret)
4522                 return ret;
4523
4524         if (ulv->supported && ulv->pl.vddc) {
4525                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4526                 if (ret)
4527                         return ret;
4528
4529                 ret = si_program_ulv_memory_timing_parameters(rdev);
4530                 if (ret)
4531                         return ret;
4532
4533                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4534                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4535
4536                 lane_width = radeon_get_pcie_lanes(rdev);
4537                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4538         } else {
4539                 table->ULVState = table->initialState;
4540         }
4541
4542         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4543                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4544                                     si_pi->sram_end);
4545 }
4546
4547 static int si_calculate_sclk_params(struct radeon_device *rdev,
4548                                     u32 engine_clock,
4549                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4550 {
4551         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4552         struct si_power_info *si_pi = si_get_pi(rdev);
4553         struct atom_clock_dividers dividers;
4554         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4555         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4556         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4557         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4558         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4559         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4560         u64 tmp;
4561         u32 reference_clock = rdev->clock.spll.reference_freq;
4562         u32 reference_divider;
4563         u32 fbdiv;
4564         int ret;
4565
4566         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4567                                              engine_clock, false, &dividers);
4568         if (ret)
4569                 return ret;
4570
4571         reference_divider = 1 + dividers.ref_div;
4572
4573         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4574         do_div(tmp, reference_clock);
4575         fbdiv = (u32) tmp;
4576
4577         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4578         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4579         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4580
4581         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4582         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4583
4584         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4585         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4586         spll_func_cntl_3 |= SPLL_DITHEN;
4587
4588         if (pi->sclk_ss) {
4589                 struct radeon_atom_ss ss;
4590                 u32 vco_freq = engine_clock * dividers.post_div;
4591
4592                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4593                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4594                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4595                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4596
4597                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4598                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4599                         cg_spll_spread_spectrum |= SSEN;
4600
4601                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4602                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4603                 }
4604         }
4605
4606         sclk->sclk_value = engine_clock;
4607         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4608         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4609         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4610         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4611         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4612         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4613
4614         return 0;
4615 }
4616
4617 static int si_populate_sclk_value(struct radeon_device *rdev,
4618                                   u32 engine_clock,
4619                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4620 {
4621         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4622         int ret;
4623
4624         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4625         if (!ret) {
4626                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4627                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4628                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4629                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4630                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4631                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4632                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4633         }
4634
4635         return ret;
4636 }
4637
4638 static int si_populate_mclk_value(struct radeon_device *rdev,
4639                                   u32 engine_clock,
4640                                   u32 memory_clock,
4641                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4642                                   bool strobe_mode,
4643                                   bool dll_state_on)
4644 {
4645         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4646         struct si_power_info *si_pi = si_get_pi(rdev);
4647         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4648         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4649         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4650         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4651         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4652         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4653         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4654         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4655         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4656         struct atom_mpll_param mpll_param;
4657         int ret;
4658
4659         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4660         if (ret)
4661                 return ret;
4662
4663         mpll_func_cntl &= ~BWCTRL_MASK;
4664         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4665
4666         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4667         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4668                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4669
4670         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4671         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4672
4673         if (pi->mem_gddr5) {
4674                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4675                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4676                         YCLK_POST_DIV(mpll_param.post_div);
4677         }
4678
4679         if (pi->mclk_ss) {
4680                 struct radeon_atom_ss ss;
4681                 u32 freq_nom;
4682                 u32 tmp;
4683                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4684
4685                 if (pi->mem_gddr5)
4686                         freq_nom = memory_clock * 4;
4687                 else
4688                         freq_nom = memory_clock * 2;
4689
4690                 tmp = freq_nom / reference_clock;
4691                 tmp = tmp * tmp;
4692                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4693                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4694                         u32 clks = reference_clock * 5 / ss.rate;
4695                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4696
4697                         mpll_ss1 &= ~CLKV_MASK;
4698                         mpll_ss1 |= CLKV(clkv);
4699
4700                         mpll_ss2 &= ~CLKS_MASK;
4701                         mpll_ss2 |= CLKS(clks);
4702                 }
4703         }
4704
4705         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4706         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4707
4708         if (dll_state_on)
4709                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4710         else
4711                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4712
4713         mclk->mclk_value = cpu_to_be32(memory_clock);
4714         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4715         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4716         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4717         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4718         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4719         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4720         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4721         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4722         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4723
4724         return 0;
4725 }
4726
4727 static void si_populate_smc_sp(struct radeon_device *rdev,
4728                                struct radeon_ps *radeon_state,
4729                                SISLANDS_SMC_SWSTATE *smc_state)
4730 {
4731         struct ni_ps *ps = ni_get_ps(radeon_state);
4732         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4733         int i;
4734
4735         for (i = 0; i < ps->performance_level_count - 1; i++)
4736                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4737
4738         smc_state->levels[ps->performance_level_count - 1].bSP =
4739                 cpu_to_be32(pi->psp);
4740 }
4741
4742 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4743                                          struct rv7xx_pl *pl,
4744                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4745 {
4746         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4747         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4748         struct si_power_info *si_pi = si_get_pi(rdev);
4749         int ret;
4750         bool dll_state_on;
4751         u16 std_vddc;
4752         bool gmc_pg = false;
4753
4754         if (eg_pi->pcie_performance_request &&
4755             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4756                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4757         else
4758                 level->gen2PCIE = (u8)pl->pcie_gen;
4759
4760         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4761         if (ret)
4762                 return ret;
4763
4764         level->mcFlags =  0;
4765
4766         if (pi->mclk_stutter_mode_threshold &&
4767             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4768             !eg_pi->uvd_enabled &&
4769             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4770             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4771                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4772
4773                 if (gmc_pg)
4774                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4775         }
4776
4777         if (pi->mem_gddr5) {
4778                 if (pl->mclk > pi->mclk_edc_enable_threshold)
4779                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4780
4781                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4782                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4783
4784                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4785
4786                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4787                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4788                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4789                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4790                         else
4791                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4792                 } else {
4793                         dll_state_on = false;
4794                 }
4795         } else {
4796                 level->strobeMode = si_get_strobe_mode_settings(rdev,
4797                                                                 pl->mclk);
4798
4799                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4800         }
4801
4802         ret = si_populate_mclk_value(rdev,
4803                                      pl->sclk,
4804                                      pl->mclk,
4805                                      &level->mclk,
4806                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4807         if (ret)
4808                 return ret;
4809
4810         ret = si_populate_voltage_value(rdev,
4811                                         &eg_pi->vddc_voltage_table,
4812                                         pl->vddc, &level->vddc);
4813         if (ret)
4814                 return ret;
4815
4816
4817         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4818         if (ret)
4819                 return ret;
4820
4821         ret = si_populate_std_voltage_value(rdev, std_vddc,
4822                                             level->vddc.index, &level->std_vddc);
4823         if (ret)
4824                 return ret;
4825
4826         if (eg_pi->vddci_control) {
4827                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4828                                                 pl->vddci, &level->vddci);
4829                 if (ret)
4830                         return ret;
4831         }
4832
4833         if (si_pi->vddc_phase_shed_control) {
4834                 ret = si_populate_phase_shedding_value(rdev,
4835                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4836                                                        pl->vddc,
4837                                                        pl->sclk,
4838                                                        pl->mclk,
4839                                                        &level->vddc);
4840                 if (ret)
4841                         return ret;
4842         }
4843
4844         level->MaxPoweredUpCU = si_pi->max_cu;
4845
4846         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4847
4848         return ret;
4849 }
4850
4851 static int si_populate_smc_t(struct radeon_device *rdev,
4852                              struct radeon_ps *radeon_state,
4853                              SISLANDS_SMC_SWSTATE *smc_state)
4854 {
4855         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4856         struct ni_ps *state = ni_get_ps(radeon_state);
4857         u32 a_t;
4858         u32 t_l, t_h;
4859         u32 high_bsp;
4860         int i, ret;
4861
4862         if (state->performance_level_count >= 9)
4863                 return -EINVAL;
4864
4865         if (state->performance_level_count < 2) {
4866                 a_t = CG_R(0xffff) | CG_L(0);
4867                 smc_state->levels[0].aT = cpu_to_be32(a_t);
4868                 return 0;
4869         }
4870
4871         smc_state->levels[0].aT = cpu_to_be32(0);
4872
4873         for (i = 0; i <= state->performance_level_count - 2; i++) {
4874                 ret = r600_calculate_at(
4875                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4876                         100 * R600_AH_DFLT,
4877                         state->performance_levels[i + 1].sclk,
4878                         state->performance_levels[i].sclk,
4879                         &t_l,
4880                         &t_h);
4881
4882                 if (ret) {
4883                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4884                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
4885                 }
4886
4887                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
4888                 a_t |= CG_R(t_l * pi->bsp / 20000);
4889                 smc_state->levels[i].aT = cpu_to_be32(a_t);
4890
4891                 high_bsp = (i == state->performance_level_count - 2) ?
4892                         pi->pbsp : pi->bsp;
4893                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
4894                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
4895         }
4896
4897         return 0;
4898 }
4899
4900 static int si_disable_ulv(struct radeon_device *rdev)
4901 {
4902         struct si_power_info *si_pi = si_get_pi(rdev);
4903         struct si_ulv_param *ulv = &si_pi->ulv;
4904
4905         if (ulv->supported)
4906                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
4907                         0 : -EINVAL;
4908
4909         return 0;
4910 }
4911
4912 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
4913                                        struct radeon_ps *radeon_state)
4914 {
4915         const struct si_power_info *si_pi = si_get_pi(rdev);
4916         const struct si_ulv_param *ulv = &si_pi->ulv;
4917         const struct ni_ps *state = ni_get_ps(radeon_state);
4918         int i;
4919
4920         if (state->performance_levels[0].mclk != ulv->pl.mclk)
4921                 return false;
4922
4923         /* XXX validate against display requirements! */
4924
4925         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
4926                 if (rdev->clock.current_dispclk <=
4927                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
4928                         if (ulv->pl.vddc <
4929                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
4930                                 return false;
4931                 }
4932         }
4933
4934         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
4935                 return false;
4936
4937         return true;
4938 }
4939
4940 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
4941                                                        struct radeon_ps *radeon_new_state)
4942 {
4943         const struct si_power_info *si_pi = si_get_pi(rdev);
4944         const struct si_ulv_param *ulv = &si_pi->ulv;
4945
4946         if (ulv->supported) {
4947                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
4948                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
4949                                 0 : -EINVAL;
4950         }
4951         return 0;
4952 }
4953
4954 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
4955                                          struct radeon_ps *radeon_state,
4956                                          SISLANDS_SMC_SWSTATE *smc_state)
4957 {
4958         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4959         struct ni_power_info *ni_pi = ni_get_pi(rdev);
4960         struct si_power_info *si_pi = si_get_pi(rdev);
4961         struct ni_ps *state = ni_get_ps(radeon_state);
4962         int i, ret;
4963         u32 threshold;
4964         u32 sclk_in_sr = 1350; /* ??? */
4965
4966         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
4967                 return -EINVAL;
4968
4969         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
4970
4971         if (radeon_state->vclk && radeon_state->dclk) {
4972                 eg_pi->uvd_enabled = true;
4973                 if (eg_pi->smu_uvd_hs)
4974                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
4975         } else {
4976                 eg_pi->uvd_enabled = false;
4977         }
4978
4979         if (state->dc_compatible)
4980                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
4981
4982         smc_state->levelCount = 0;
4983         for (i = 0; i < state->performance_level_count; i++) {
4984                 if (eg_pi->sclk_deep_sleep) {
4985                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
4986                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4987                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4988                                 else
4989                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4990                         }
4991                 }
4992
4993                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
4994                                                     &smc_state->levels[i]);
4995                 smc_state->levels[i].arbRefreshState =
4996                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
4997
4998                 if (ret)
4999                         return ret;
5000
5001                 if (ni_pi->enable_power_containment)
5002                         smc_state->levels[i].displayWatermark =
5003                                 (state->performance_levels[i].sclk < threshold) ?
5004                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5005                 else
5006                         smc_state->levels[i].displayWatermark = (i < 2) ?
5007                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5008
5009                 if (eg_pi->dynamic_ac_timing)
5010                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5011                 else
5012                         smc_state->levels[i].ACIndex = 0;
5013
5014                 smc_state->levelCount++;
5015         }
5016
5017         si_write_smc_soft_register(rdev,
5018                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5019                                    threshold / 512);
5020
5021         si_populate_smc_sp(rdev, radeon_state, smc_state);
5022
5023         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5024         if (ret)
5025                 ni_pi->enable_power_containment = false;
5026
5027         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5028         if (ret)
5029                 ni_pi->enable_sq_ramping = false;
5030
5031         return si_populate_smc_t(rdev, radeon_state, smc_state);
5032 }
5033
5034 static int si_upload_sw_state(struct radeon_device *rdev,
5035                               struct radeon_ps *radeon_new_state)
5036 {
5037         struct si_power_info *si_pi = si_get_pi(rdev);
5038         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5039         int ret;
5040         u32 address = si_pi->state_table_start +
5041                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5042         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5043                 ((new_state->performance_level_count - 1) *
5044                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5045         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5046
5047         memset(smc_state, 0, state_size);
5048
5049         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5050         if (ret)
5051                 return ret;
5052
5053         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5054                                    state_size, si_pi->sram_end);
5055
5056         return ret;
5057 }
5058
5059 static int si_upload_ulv_state(struct radeon_device *rdev)
5060 {
5061         struct si_power_info *si_pi = si_get_pi(rdev);
5062         struct si_ulv_param *ulv = &si_pi->ulv;
5063         int ret = 0;
5064
5065         if (ulv->supported && ulv->pl.vddc) {
5066                 u32 address = si_pi->state_table_start +
5067                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5068                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5069                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5070
5071                 memset(smc_state, 0, state_size);
5072
5073                 ret = si_populate_ulv_state(rdev, smc_state);
5074                 if (!ret)
5075                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5076                                                    state_size, si_pi->sram_end);
5077         }
5078
5079         return ret;
5080 }
5081
5082 static int si_upload_smc_data(struct radeon_device *rdev)
5083 {
5084         struct radeon_crtc *radeon_crtc = NULL;
5085         int i;
5086
5087         if (rdev->pm.dpm.new_active_crtc_count == 0)
5088                 return 0;
5089
5090         for (i = 0; i < rdev->num_crtc; i++) {
5091                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5092                         radeon_crtc = rdev->mode_info.crtcs[i];
5093                         break;
5094                 }
5095         }
5096
5097         if (radeon_crtc == NULL)
5098                 return 0;
5099
5100         if (radeon_crtc->line_time <= 0)
5101                 return 0;
5102
5103         if (si_write_smc_soft_register(rdev,
5104                                        SI_SMC_SOFT_REGISTER_crtc_index,
5105                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5106                 return 0;
5107
5108         if (si_write_smc_soft_register(rdev,
5109                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5110                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5111                 return 0;
5112
5113         if (si_write_smc_soft_register(rdev,
5114                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5115                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5116                 return 0;
5117
5118         return 0;
5119 }
5120
5121 static int si_set_mc_special_registers(struct radeon_device *rdev,
5122                                        struct si_mc_reg_table *table)
5123 {
5124         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5125         u8 i, j, k;
5126         u32 temp_reg;
5127
5128         for (i = 0, j = table->last; i < table->last; i++) {
5129                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5130                         return -EINVAL;
5131                 switch (table->mc_reg_address[i].s1 << 2) {
5132                 case MC_SEQ_MISC1:
5133                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5134                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5135                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5136                         for (k = 0; k < table->num_entries; k++)
5137                                 table->mc_reg_table_entry[k].mc_data[j] =
5138                                         ((temp_reg & 0xffff0000)) |
5139                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5140                         j++;
5141                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5142                                 return -EINVAL;
5143
5144                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5145                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5146                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5147                         for (k = 0; k < table->num_entries; k++) {
5148                                 table->mc_reg_table_entry[k].mc_data[j] =
5149                                         (temp_reg & 0xffff0000) |
5150                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5151                                 if (!pi->mem_gddr5)
5152                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5153                         }
5154                         j++;
5155                         if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5156                                 return -EINVAL;
5157
5158                         if (!pi->mem_gddr5) {
5159                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5160                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5161                                 for (k = 0; k < table->num_entries; k++)
5162                                         table->mc_reg_table_entry[k].mc_data[j] =
5163                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5164                                 j++;
5165                                 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5166                                         return -EINVAL;
5167                         }
5168                         break;
5169                 case MC_SEQ_RESERVE_M:
5170                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5171                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5172                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5173                         for(k = 0; k < table->num_entries; k++)
5174                                 table->mc_reg_table_entry[k].mc_data[j] =
5175                                         (temp_reg & 0xffff0000) |
5176                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5177                         j++;
5178                         if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5179                                 return -EINVAL;
5180                         break;
5181                 default:
5182                         break;
5183                 }
5184         }
5185
5186         table->last = j;
5187
5188         return 0;
5189 }
5190
5191 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5192 {
5193         bool result = true;
5194
5195         switch (in_reg) {
5196         case  MC_SEQ_RAS_TIMING >> 2:
5197                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5198                 break;
5199         case MC_SEQ_CAS_TIMING >> 2:
5200                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5201                 break;
5202         case MC_SEQ_MISC_TIMING >> 2:
5203                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5204                 break;
5205         case MC_SEQ_MISC_TIMING2 >> 2:
5206                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5207                 break;
5208         case MC_SEQ_RD_CTL_D0 >> 2:
5209                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5210                 break;
5211         case MC_SEQ_RD_CTL_D1 >> 2:
5212                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5213                 break;
5214         case MC_SEQ_WR_CTL_D0 >> 2:
5215                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5216                 break;
5217         case MC_SEQ_WR_CTL_D1 >> 2:
5218                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5219                 break;
5220         case MC_PMG_CMD_EMRS >> 2:
5221                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5222                 break;
5223         case MC_PMG_CMD_MRS >> 2:
5224                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5225                 break;
5226         case MC_PMG_CMD_MRS1 >> 2:
5227                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5228                 break;
5229         case MC_SEQ_PMG_TIMING >> 2:
5230                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5231                 break;
5232         case MC_PMG_CMD_MRS2 >> 2:
5233                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5234                 break;
5235         case MC_SEQ_WR_CTL_2 >> 2:
5236                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5237                 break;
5238         default:
5239                 result = false;
5240                 break;
5241         }
5242
5243         return result;
5244 }
5245
5246 static void si_set_valid_flag(struct si_mc_reg_table *table)
5247 {
5248         u8 i, j;
5249
5250         for (i = 0; i < table->last; i++) {
5251                 for (j = 1; j < table->num_entries; j++) {
5252                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5253                                 table->valid_flag |= 1 << i;
5254                                 break;
5255                         }
5256                 }
5257         }
5258 }
5259
5260 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5261 {
5262         u32 i;
5263         u16 address;
5264
5265         for (i = 0; i < table->last; i++)
5266                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5267                         address : table->mc_reg_address[i].s1;
5268
5269 }
5270
5271 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5272                                       struct si_mc_reg_table *si_table)
5273 {
5274         u8 i, j;
5275
5276         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5277                 return -EINVAL;
5278         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5279                 return -EINVAL;
5280
5281         for (i = 0; i < table->last; i++)
5282                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5283         si_table->last = table->last;
5284
5285         for (i = 0; i < table->num_entries; i++) {
5286                 si_table->mc_reg_table_entry[i].mclk_max =
5287                         table->mc_reg_table_entry[i].mclk_max;
5288                 for (j = 0; j < table->last; j++) {
5289                         si_table->mc_reg_table_entry[i].mc_data[j] =
5290                                 table->mc_reg_table_entry[i].mc_data[j];
5291                 }
5292         }
5293         si_table->num_entries = table->num_entries;
5294
5295         return 0;
5296 }
5297
5298 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5299 {
5300         struct si_power_info *si_pi = si_get_pi(rdev);
5301         struct atom_mc_reg_table *table;
5302         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5303         u8 module_index = rv770_get_memory_module_index(rdev);
5304         int ret;
5305
5306         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5307         if (!table)
5308                 return -ENOMEM;
5309
5310         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5311         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5312         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5313         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5314         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5315         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5316         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5317         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5318         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5319         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5320         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5321         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5322         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5323         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5324
5325         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5326         if (ret)
5327                 goto init_mc_done;
5328
5329         ret = si_copy_vbios_mc_reg_table(table, si_table);
5330         if (ret)
5331                 goto init_mc_done;
5332
5333         si_set_s0_mc_reg_index(si_table);
5334
5335         ret = si_set_mc_special_registers(rdev, si_table);
5336         if (ret)
5337                 goto init_mc_done;
5338
5339         si_set_valid_flag(si_table);
5340
5341 init_mc_done:
5342         kfree(table);
5343
5344         return ret;
5345
5346 }
5347
5348 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5349                                          SMC_SIslands_MCRegisters *mc_reg_table)
5350 {
5351         struct si_power_info *si_pi = si_get_pi(rdev);
5352         u32 i, j;
5353
5354         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5355                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5356                         if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
5357                                 break;
5358                         mc_reg_table->address[i].s0 =
5359                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5360                         mc_reg_table->address[i].s1 =
5361                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5362                         i++;
5363                 }
5364         }
5365         mc_reg_table->last = (u8)i;
5366 }
5367
5368 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5369                                     SMC_SIslands_MCRegisterSet *data,
5370                                     u32 num_entries, u32 valid_flag)
5371 {
5372         u32 i, j;
5373
5374         for(i = 0, j = 0; j < num_entries; j++) {
5375                 if (valid_flag & (1 << j)) {
5376                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5377                         i++;
5378                 }
5379         }
5380 }
5381
5382 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5383                                                  struct rv7xx_pl *pl,
5384                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5385 {
5386         struct si_power_info *si_pi = si_get_pi(rdev);
5387         u32 i = 0;
5388
5389         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5390                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5391                         break;
5392         }
5393
5394         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5395                 --i;
5396
5397         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5398                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5399                                 si_pi->mc_reg_table.valid_flag);
5400 }
5401
5402 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5403                                            struct radeon_ps *radeon_state,
5404                                            SMC_SIslands_MCRegisters *mc_reg_table)
5405 {
5406         struct ni_ps *state = ni_get_ps(radeon_state);
5407         int i;
5408
5409         for (i = 0; i < state->performance_level_count; i++) {
5410                 si_convert_mc_reg_table_entry_to_smc(rdev,
5411                                                      &state->performance_levels[i],
5412                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5413         }
5414 }
5415
5416 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5417                                     struct radeon_ps *radeon_boot_state)
5418 {
5419         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5420         struct si_power_info *si_pi = si_get_pi(rdev);
5421         struct si_ulv_param *ulv = &si_pi->ulv;
5422         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5423
5424         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5425
5426         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5427
5428         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5429
5430         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5431                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5432
5433         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5434                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5435                                 si_pi->mc_reg_table.last,
5436                                 si_pi->mc_reg_table.valid_flag);
5437
5438         if (ulv->supported && ulv->pl.vddc != 0)
5439                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5440                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5441         else
5442                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5443                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5444                                         si_pi->mc_reg_table.last,
5445                                         si_pi->mc_reg_table.valid_flag);
5446
5447         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5448
5449         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5450                                     (u8 *)smc_mc_reg_table,
5451                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5452 }
5453
5454 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5455                                   struct radeon_ps *radeon_new_state)
5456 {
5457         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5458         struct si_power_info *si_pi = si_get_pi(rdev);
5459         u32 address = si_pi->mc_reg_table_start +
5460                 offsetof(SMC_SIslands_MCRegisters,
5461                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5462         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5463
5464         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5465
5466         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5467
5468
5469         return si_copy_bytes_to_smc(rdev, address,
5470                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5471                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5472                                     si_pi->sram_end);
5473
5474 }
5475
5476 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5477 {
5478         if (enable)
5479                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5480         else
5481                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5482 }
5483
5484 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5485                                                       struct radeon_ps *radeon_state)
5486 {
5487         struct ni_ps *state = ni_get_ps(radeon_state);
5488         int i;
5489         u16 pcie_speed, max_speed = 0;
5490
5491         for (i = 0; i < state->performance_level_count; i++) {
5492                 pcie_speed = state->performance_levels[i].pcie_gen;
5493                 if (max_speed < pcie_speed)
5494                         max_speed = pcie_speed;
5495         }
5496         return max_speed;
5497 }
5498
5499 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5500 {
5501         u32 speed_cntl;
5502
5503         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5504         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5505
5506         return (u16)speed_cntl;
5507 }
5508
5509 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5510                                                              struct radeon_ps *radeon_new_state,
5511                                                              struct radeon_ps *radeon_current_state)
5512 {
5513         struct si_power_info *si_pi = si_get_pi(rdev);
5514         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5515         enum radeon_pcie_gen current_link_speed;
5516
5517         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5518                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5519         else
5520                 current_link_speed = si_pi->force_pcie_gen;
5521
5522         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5523         si_pi->pspp_notify_required = false;
5524         if (target_link_speed > current_link_speed) {
5525                 switch (target_link_speed) {
5526 #if defined(CONFIG_ACPI)
5527                 case RADEON_PCIE_GEN3:
5528                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5529                                 break;
5530                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5531                         if (current_link_speed == RADEON_PCIE_GEN2)
5532                                 break;
5533                 case RADEON_PCIE_GEN2:
5534                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5535                                 break;
5536 #endif
5537                 default:
5538                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5539                         break;
5540                 }
5541         } else {
5542                 if (target_link_speed < current_link_speed)
5543                         si_pi->pspp_notify_required = true;
5544         }
5545 }
5546
5547 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5548                                                            struct radeon_ps *radeon_new_state,
5549                                                            struct radeon_ps *radeon_current_state)
5550 {
5551         struct si_power_info *si_pi = si_get_pi(rdev);
5552         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5553         u8 request;
5554
5555         if (si_pi->pspp_notify_required) {
5556                 if (target_link_speed == RADEON_PCIE_GEN3)
5557                         request = PCIE_PERF_REQ_PECI_GEN3;
5558                 else if (target_link_speed == RADEON_PCIE_GEN2)
5559                         request = PCIE_PERF_REQ_PECI_GEN2;
5560                 else
5561                         request = PCIE_PERF_REQ_PECI_GEN1;
5562
5563                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5564                     (si_get_current_pcie_speed(rdev) > 0))
5565                         return;
5566
5567 #if defined(CONFIG_ACPI)
5568                 radeon_acpi_pcie_performance_request(rdev, request, false);
5569 #endif
5570         }
5571 }
5572
5573 #if 0
5574 static int si_ds_request(struct radeon_device *rdev,
5575                          bool ds_status_on, u32 count_write)
5576 {
5577         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5578
5579         if (eg_pi->sclk_deep_sleep) {
5580                 if (ds_status_on)
5581                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5582                                 PPSMC_Result_OK) ?
5583                                 0 : -EINVAL;
5584                 else
5585                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5586                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5587         }
5588         return 0;
5589 }
5590 #endif
5591
5592 static void si_set_max_cu_value(struct radeon_device *rdev)
5593 {
5594         struct si_power_info *si_pi = si_get_pi(rdev);
5595
5596         if (rdev->family == CHIP_VERDE) {
5597                 switch (rdev->pdev->device) {
5598                 case 0x6820:
5599                 case 0x6825:
5600                 case 0x6821:
5601                 case 0x6823:
5602                 case 0x6827:
5603                         si_pi->max_cu = 10;
5604                         break;
5605                 case 0x682D:
5606                 case 0x6824:
5607                 case 0x682F:
5608                 case 0x6826:
5609                         si_pi->max_cu = 8;
5610                         break;
5611                 case 0x6828:
5612                 case 0x6830:
5613                 case 0x6831:
5614                 case 0x6838:
5615                 case 0x6839:
5616                 case 0x683D:
5617                         si_pi->max_cu = 10;
5618                         break;
5619                 case 0x683B:
5620                 case 0x683F:
5621                 case 0x6829:
5622                         si_pi->max_cu = 8;
5623                         break;
5624                 default:
5625                         si_pi->max_cu = 0;
5626                         break;
5627                 }
5628         } else {
5629                 si_pi->max_cu = 0;
5630         }
5631 }
5632
5633 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5634                                                              struct radeon_clock_voltage_dependency_table *table)
5635 {
5636         u32 i;
5637         int j;
5638         u16 leakage_voltage;
5639
5640         if (table) {
5641                 for (i = 0; i < table->count; i++) {
5642                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5643                                                                           table->entries[i].v,
5644                                                                           &leakage_voltage)) {
5645                         case 0:
5646                                 table->entries[i].v = leakage_voltage;
5647                                 break;
5648                         case -EAGAIN:
5649                                 return -EINVAL;
5650                         case -EINVAL:
5651                         default:
5652                                 break;
5653                         }
5654                 }
5655
5656                 for (j = (table->count - 2); j >= 0; j--) {
5657                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5658                                 table->entries[j].v : table->entries[j + 1].v;
5659                 }
5660         }
5661         return 0;
5662 }
5663
5664 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5665 {
5666         int ret = 0;
5667
5668         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5669                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5670         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5671                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5672         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5673                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5674         return ret;
5675 }
5676
5677 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5678                                           struct radeon_ps *radeon_new_state,
5679                                           struct radeon_ps *radeon_current_state)
5680 {
5681         u32 lane_width;
5682         u32 new_lane_width =
5683                 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5684         u32 current_lane_width =
5685                 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5686
5687         if (new_lane_width != current_lane_width) {
5688                 radeon_set_pcie_lanes(rdev, new_lane_width);
5689                 lane_width = radeon_get_pcie_lanes(rdev);
5690                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5691         }
5692 }
5693
5694 void si_dpm_setup_asic(struct radeon_device *rdev)
5695 {
5696         rv770_get_memory_type(rdev);
5697         si_read_clock_registers(rdev);
5698         si_enable_acpi_power_management(rdev);
5699 }
5700
5701 static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5702                                         int min_temp, int max_temp)
5703 {
5704         int low_temp = 0 * 1000;
5705         int high_temp = 255 * 1000;
5706
5707         if (low_temp < min_temp)
5708                 low_temp = min_temp;
5709         if (high_temp > max_temp)
5710                 high_temp = max_temp;
5711         if (high_temp < low_temp) {
5712                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5713                 return -EINVAL;
5714         }
5715
5716         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5717         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5718         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5719
5720         rdev->pm.dpm.thermal.min_temp = low_temp;
5721         rdev->pm.dpm.thermal.max_temp = high_temp;
5722
5723         return 0;
5724 }
5725
5726 int si_dpm_enable(struct radeon_device *rdev)
5727 {
5728         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5729         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5730         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5731         int ret;
5732
5733         if (si_is_smc_running(rdev))
5734                 return -EINVAL;
5735         if (pi->voltage_control)
5736                 si_enable_voltage_control(rdev, true);
5737         if (pi->mvdd_control)
5738                 si_get_mvdd_configuration(rdev);
5739         if (pi->voltage_control) {
5740                 ret = si_construct_voltage_tables(rdev);
5741                 if (ret) {
5742                         DRM_ERROR("si_construct_voltage_tables failed\n");
5743                         return ret;
5744                 }
5745         }
5746         if (eg_pi->dynamic_ac_timing) {
5747                 ret = si_initialize_mc_reg_table(rdev);
5748                 if (ret)
5749                         eg_pi->dynamic_ac_timing = false;
5750         }
5751         if (pi->dynamic_ss)
5752                 si_enable_spread_spectrum(rdev, true);
5753         if (pi->thermal_protection)
5754                 si_enable_thermal_protection(rdev, true);
5755         si_setup_bsp(rdev);
5756         si_program_git(rdev);
5757         si_program_tp(rdev);
5758         si_program_tpp(rdev);
5759         si_program_sstp(rdev);
5760         si_enable_display_gap(rdev);
5761         si_program_vc(rdev);
5762         ret = si_upload_firmware(rdev);
5763         if (ret) {
5764                 DRM_ERROR("si_upload_firmware failed\n");
5765                 return ret;
5766         }
5767         ret = si_process_firmware_header(rdev);
5768         if (ret) {
5769                 DRM_ERROR("si_process_firmware_header failed\n");
5770                 return ret;
5771         }
5772         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5773         if (ret) {
5774                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5775                 return ret;
5776         }
5777         ret = si_init_smc_table(rdev);
5778         if (ret) {
5779                 DRM_ERROR("si_init_smc_table failed\n");
5780                 return ret;
5781         }
5782         ret = si_init_smc_spll_table(rdev);
5783         if (ret) {
5784                 DRM_ERROR("si_init_smc_spll_table failed\n");
5785                 return ret;
5786         }
5787         ret = si_init_arb_table_index(rdev);
5788         if (ret) {
5789                 DRM_ERROR("si_init_arb_table_index failed\n");
5790                 return ret;
5791         }
5792         if (eg_pi->dynamic_ac_timing) {
5793                 ret = si_populate_mc_reg_table(rdev, boot_ps);
5794                 if (ret) {
5795                         DRM_ERROR("si_populate_mc_reg_table failed\n");
5796                         return ret;
5797                 }
5798         }
5799         ret = si_initialize_smc_cac_tables(rdev);
5800         if (ret) {
5801                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5802                 return ret;
5803         }
5804         ret = si_initialize_hardware_cac_manager(rdev);
5805         if (ret) {
5806                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5807                 return ret;
5808         }
5809         ret = si_initialize_smc_dte_tables(rdev);
5810         if (ret) {
5811                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5812                 return ret;
5813         }
5814         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5815         if (ret) {
5816                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5817                 return ret;
5818         }
5819         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5820         if (ret) {
5821                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5822                 return ret;
5823         }
5824         si_program_response_times(rdev);
5825         si_program_ds_registers(rdev);
5826         si_dpm_start_smc(rdev);
5827         ret = si_notify_smc_display_change(rdev, false);
5828         if (ret) {
5829                 DRM_ERROR("si_notify_smc_display_change failed\n");
5830                 return ret;
5831         }
5832         si_enable_sclk_control(rdev, true);
5833         si_start_dpm(rdev);
5834
5835         if (rdev->irq.installed &&
5836             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5837                 PPSMC_Result result;
5838
5839                 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5840                 if (ret)
5841                         return ret;
5842                 rdev->irq.dpm_thermal = true;
5843                 radeon_irq_set(rdev);
5844                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5845
5846                 if (result != PPSMC_Result_OK)
5847                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5848         }
5849
5850         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5851
5852         ni_update_current_ps(rdev, boot_ps);
5853
5854         return 0;
5855 }
5856
5857 void si_dpm_disable(struct radeon_device *rdev)
5858 {
5859         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5860         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5861
5862         if (!si_is_smc_running(rdev))
5863                 return;
5864         si_disable_ulv(rdev);
5865         si_clear_vc(rdev);
5866         if (pi->thermal_protection)
5867                 si_enable_thermal_protection(rdev, false);
5868         si_enable_power_containment(rdev, boot_ps, false);
5869         si_enable_smc_cac(rdev, boot_ps, false);
5870         si_enable_spread_spectrum(rdev, false);
5871         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5872         si_stop_dpm(rdev);
5873         si_reset_to_default(rdev);
5874         si_dpm_stop_smc(rdev);
5875         si_force_switch_to_arb_f0(rdev);
5876
5877         ni_update_current_ps(rdev, boot_ps);
5878 }
5879
5880 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
5881 {
5882         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5883         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5884         struct radeon_ps *new_ps = &requested_ps;
5885
5886         ni_update_requested_ps(rdev, new_ps);
5887
5888         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
5889
5890         return 0;
5891 }
5892
5893 static int si_power_control_set_level(struct radeon_device *rdev)
5894 {
5895         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
5896         int ret;
5897
5898         ret = si_restrict_performance_levels_before_switch(rdev);
5899         if (ret)
5900                 return ret;
5901         ret = si_halt_smc(rdev);
5902         if (ret)
5903                 return ret;
5904         ret = si_populate_smc_tdp_limits(rdev, new_ps);
5905         if (ret)
5906                 return ret;
5907         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
5908         if (ret)
5909                 return ret;
5910         ret = si_resume_smc(rdev);
5911         if (ret)
5912                 return ret;
5913         ret = si_set_sw_state(rdev);
5914         if (ret)
5915                 return ret;
5916         return 0;
5917 }
5918
5919 int si_dpm_set_power_state(struct radeon_device *rdev)
5920 {
5921         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5922         struct radeon_ps *new_ps = &eg_pi->requested_rps;
5923         struct radeon_ps *old_ps = &eg_pi->current_rps;
5924         int ret;
5925
5926         ret = si_disable_ulv(rdev);
5927         if (ret) {
5928                 DRM_ERROR("si_disable_ulv failed\n");
5929                 return ret;
5930         }
5931         ret = si_restrict_performance_levels_before_switch(rdev);
5932         if (ret) {
5933                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
5934                 return ret;
5935         }
5936         if (eg_pi->pcie_performance_request)
5937                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5938         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
5939         ret = si_enable_power_containment(rdev, new_ps, false);
5940         if (ret) {
5941                 DRM_ERROR("si_enable_power_containment failed\n");
5942                 return ret;
5943         }
5944         ret = si_enable_smc_cac(rdev, new_ps, false);
5945         if (ret) {
5946                 DRM_ERROR("si_enable_smc_cac failed\n");
5947                 return ret;
5948         }
5949         ret = si_halt_smc(rdev);
5950         if (ret) {
5951                 DRM_ERROR("si_halt_smc failed\n");
5952                 return ret;
5953         }
5954         ret = si_upload_sw_state(rdev, new_ps);
5955         if (ret) {
5956                 DRM_ERROR("si_upload_sw_state failed\n");
5957                 return ret;
5958         }
5959         ret = si_upload_smc_data(rdev);
5960         if (ret) {
5961                 DRM_ERROR("si_upload_smc_data failed\n");
5962                 return ret;
5963         }
5964         ret = si_upload_ulv_state(rdev);
5965         if (ret) {
5966                 DRM_ERROR("si_upload_ulv_state failed\n");
5967                 return ret;
5968         }
5969         if (eg_pi->dynamic_ac_timing) {
5970                 ret = si_upload_mc_reg_table(rdev, new_ps);
5971                 if (ret) {
5972                         DRM_ERROR("si_upload_mc_reg_table failed\n");
5973                         return ret;
5974                 }
5975         }
5976         ret = si_program_memory_timing_parameters(rdev, new_ps);
5977         if (ret) {
5978                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
5979                 return ret;
5980         }
5981         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
5982
5983         ret = si_resume_smc(rdev);
5984         if (ret) {
5985                 DRM_ERROR("si_resume_smc failed\n");
5986                 return ret;
5987         }
5988         ret = si_set_sw_state(rdev);
5989         if (ret) {
5990                 DRM_ERROR("si_set_sw_state failed\n");
5991                 return ret;
5992         }
5993         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
5994         if (eg_pi->pcie_performance_request)
5995                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5996         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
5997         if (ret) {
5998                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
5999                 return ret;
6000         }
6001         ret = si_enable_smc_cac(rdev, new_ps, true);
6002         if (ret) {
6003                 DRM_ERROR("si_enable_smc_cac failed\n");
6004                 return ret;
6005         }
6006         ret = si_enable_power_containment(rdev, new_ps, true);
6007         if (ret) {
6008                 DRM_ERROR("si_enable_power_containment failed\n");
6009                 return ret;
6010         }
6011
6012         ret = si_power_control_set_level(rdev);
6013         if (ret) {
6014                 DRM_ERROR("si_power_control_set_level failed\n");
6015                 return ret;
6016         }
6017
6018 #if 0
6019         /* XXX */
6020         ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
6021         if (ret) {
6022                 DRM_ERROR("si_dpm_force_performance_level failed\n");
6023                 return ret;
6024         }
6025 #else
6026         rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
6027 #endif
6028
6029         return 0;
6030 }
6031
6032 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6033 {
6034         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6035         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6036
6037         ni_update_current_ps(rdev, new_ps);
6038 }
6039
6040
6041 void si_dpm_reset_asic(struct radeon_device *rdev)
6042 {
6043         si_restrict_performance_levels_before_switch(rdev);
6044         si_disable_ulv(rdev);
6045         si_set_boot_state(rdev);
6046 }
6047
6048 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6049 {
6050         si_program_display_gap(rdev);
6051 }
6052
6053 union power_info {
6054         struct _ATOM_POWERPLAY_INFO info;
6055         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6056         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6057         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6058         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6059         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6060 };
6061
6062 union pplib_clock_info {
6063         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6064         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6065         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6066         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6067         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6068 };
6069
6070 union pplib_power_state {
6071         struct _ATOM_PPLIB_STATE v1;
6072         struct _ATOM_PPLIB_STATE_V2 v2;
6073 };
6074
6075 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6076                                           struct radeon_ps *rps,
6077                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6078                                           u8 table_rev)
6079 {
6080         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6081         rps->class = le16_to_cpu(non_clock_info->usClassification);
6082         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6083
6084         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6085                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6086                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6087         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6088                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6089                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6090         } else {
6091                 rps->vclk = 0;
6092                 rps->dclk = 0;
6093         }
6094
6095         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6096                 rdev->pm.dpm.boot_ps = rps;
6097         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6098                 rdev->pm.dpm.uvd_ps = rps;
6099 }
6100
6101 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6102                                       struct radeon_ps *rps, int index,
6103                                       union pplib_clock_info *clock_info)
6104 {
6105         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6106         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6107         struct si_power_info *si_pi = si_get_pi(rdev);
6108         struct ni_ps *ps = ni_get_ps(rps);
6109         u16 leakage_voltage;
6110         struct rv7xx_pl *pl = &ps->performance_levels[index];
6111         int ret;
6112
6113         ps->performance_level_count = index + 1;
6114
6115         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6116         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6117         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6118         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6119
6120         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6121         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6122         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6123         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6124                                                  si_pi->sys_pcie_mask,
6125                                                  si_pi->boot_pcie_gen,
6126                                                  clock_info->si.ucPCIEGen);
6127
6128         /* patch up vddc if necessary */
6129         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6130                                                         &leakage_voltage);
6131         if (ret == 0)
6132                 pl->vddc = leakage_voltage;
6133
6134         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6135                 pi->acpi_vddc = pl->vddc;
6136                 eg_pi->acpi_vddci = pl->vddci;
6137                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6138         }
6139
6140         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6141             index == 0) {
6142                 /* XXX disable for A0 tahiti */
6143                 si_pi->ulv.supported = true;
6144                 si_pi->ulv.pl = *pl;
6145                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6146                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6147                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6148                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6149         }
6150
6151         if (pi->min_vddc_in_table > pl->vddc)
6152                 pi->min_vddc_in_table = pl->vddc;
6153
6154         if (pi->max_vddc_in_table < pl->vddc)
6155                 pi->max_vddc_in_table = pl->vddc;
6156
6157         /* patch up boot state */
6158         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6159                 u16 vddc, vddci, mvdd;
6160                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6161                 pl->mclk = rdev->clock.default_mclk;
6162                 pl->sclk = rdev->clock.default_sclk;
6163                 pl->vddc = vddc;
6164                 pl->vddci = vddci;
6165                 si_pi->mvdd_bootup_value = mvdd;
6166         }
6167
6168         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6169             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6170                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6171                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6172                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6173                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6174         }
6175 }
6176
6177 static int si_parse_power_table(struct radeon_device *rdev)
6178 {
6179         struct radeon_mode_info *mode_info = &rdev->mode_info;
6180         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6181         union pplib_power_state *power_state;
6182         int i, j, k, non_clock_array_index, clock_array_index;
6183         union pplib_clock_info *clock_info;
6184         struct _StateArray *state_array;
6185         struct _ClockInfoArray *clock_info_array;
6186         struct _NonClockInfoArray *non_clock_info_array;
6187         union power_info *power_info;
6188         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6189         u16 data_offset;
6190         u8 frev, crev;
6191         u8 *power_state_offset;
6192         struct ni_ps *ps;
6193
6194         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6195                                    &frev, &crev, &data_offset))
6196                 return -EINVAL;
6197         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6198
6199         state_array = (struct _StateArray *)
6200                 (mode_info->atom_context->bios + data_offset +
6201                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6202         clock_info_array = (struct _ClockInfoArray *)
6203                 (mode_info->atom_context->bios + data_offset +
6204                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6205         non_clock_info_array = (struct _NonClockInfoArray *)
6206                 (mode_info->atom_context->bios + data_offset +
6207                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6208
6209         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6210                                   state_array->ucNumEntries, GFP_KERNEL);
6211         if (!rdev->pm.dpm.ps)
6212                 return -ENOMEM;
6213         power_state_offset = (u8 *)state_array->states;
6214         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
6215         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
6216         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
6217         for (i = 0; i < state_array->ucNumEntries; i++) {
6218                 power_state = (union pplib_power_state *)power_state_offset;
6219                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6220                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6221                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6222                 if (!rdev->pm.power_state[i].clock_info)
6223                         return -EINVAL;
6224                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6225                 if (ps == NULL) {
6226                         kfree(rdev->pm.dpm.ps);
6227                         return -ENOMEM;
6228                 }
6229                 rdev->pm.dpm.ps[i].ps_priv = ps;
6230                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6231                                               non_clock_info,
6232                                               non_clock_info_array->ucEntrySize);
6233                 k = 0;
6234                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6235                         clock_array_index = power_state->v2.clockInfoIndex[j];
6236                         if (clock_array_index >= clock_info_array->ucNumEntries)
6237                                 continue;
6238                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6239                                 break;
6240                         clock_info = (union pplib_clock_info *)
6241                                 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6242                         si_parse_pplib_clock_info(rdev,
6243                                                   &rdev->pm.dpm.ps[i], k,
6244                                                   clock_info);
6245                         k++;
6246                 }
6247                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6248         }
6249         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6250         return 0;
6251 }
6252
6253 int si_dpm_init(struct radeon_device *rdev)
6254 {
6255         struct rv7xx_power_info *pi;
6256         struct evergreen_power_info *eg_pi;
6257         struct ni_power_info *ni_pi;
6258         struct si_power_info *si_pi;
6259         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
6260         u16 data_offset, size;
6261         u8 frev, crev;
6262         struct atom_clock_dividers dividers;
6263         int ret;
6264         u32 mask;
6265
6266         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6267         if (si_pi == NULL)
6268                 return -ENOMEM;
6269         rdev->pm.dpm.priv = si_pi;
6270         ni_pi = &si_pi->ni;
6271         eg_pi = &ni_pi->eg;
6272         pi = &eg_pi->rv7xx;
6273
6274         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6275         if (ret)
6276                 si_pi->sys_pcie_mask = 0;
6277         else
6278                 si_pi->sys_pcie_mask = mask;
6279         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6280         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6281
6282         si_set_max_cu_value(rdev);
6283
6284         rv770_get_max_vddc(rdev);
6285         si_get_leakage_vddc(rdev);
6286         si_patch_dependency_tables_based_on_leakage(rdev);
6287
6288         pi->acpi_vddc = 0;
6289         eg_pi->acpi_vddci = 0;
6290         pi->min_vddc_in_table = 0;
6291         pi->max_vddc_in_table = 0;
6292
6293         ret = si_parse_power_table(rdev);
6294         if (ret)
6295                 return ret;
6296         ret = r600_parse_extended_power_table(rdev);
6297         if (ret)
6298                 return ret;
6299
6300         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6301                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6302         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6303                 r600_free_extended_power_table(rdev);
6304                 return -ENOMEM;
6305         }
6306         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6307         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6308         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6309         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6310         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6311         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6312         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6313         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6314         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6315
6316         if (rdev->pm.dpm.voltage_response_time == 0)
6317                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6318         if (rdev->pm.dpm.backbias_response_time == 0)
6319                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6320
6321         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6322                                              0, false, &dividers);
6323         if (ret)
6324                 pi->ref_div = dividers.ref_div + 1;
6325         else
6326                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6327
6328         eg_pi->smu_uvd_hs = false;
6329
6330         pi->mclk_strobe_mode_threshold = 40000;
6331         if (si_is_special_1gb_platform(rdev))
6332                 pi->mclk_stutter_mode_threshold = 0;
6333         else
6334                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6335         pi->mclk_edc_enable_threshold = 40000;
6336         eg_pi->mclk_edc_wr_enable_threshold = 40000;
6337
6338         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6339
6340         pi->voltage_control =
6341                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6342
6343         pi->mvdd_control =
6344                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6345
6346         eg_pi->vddci_control =
6347                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6348
6349         si_pi->vddc_phase_shed_control =
6350                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6351
6352         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
6353                                    &frev, &crev, &data_offset)) {
6354                 pi->sclk_ss = true;
6355                 pi->mclk_ss = true;
6356                 pi->dynamic_ss = true;
6357         } else {
6358                 pi->sclk_ss = false;
6359                 pi->mclk_ss = false;
6360                 pi->dynamic_ss = true;
6361         }
6362
6363         pi->asi = RV770_ASI_DFLT;
6364         pi->pasi = CYPRESS_HASI_DFLT;
6365         pi->vrc = SISLANDS_VRC_DFLT;
6366
6367         pi->gfx_clock_gating = true;
6368
6369         eg_pi->sclk_deep_sleep = true;
6370         si_pi->sclk_deep_sleep_above_low = false;
6371
6372         if (pi->gfx_clock_gating &&
6373             (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
6374                 pi->thermal_protection = true;
6375         else
6376                 pi->thermal_protection = false;
6377
6378         eg_pi->dynamic_ac_timing = true;
6379
6380         eg_pi->light_sleep = true;
6381 #if defined(CONFIG_ACPI)
6382         eg_pi->pcie_performance_request =
6383                 radeon_acpi_is_pcie_performance_request_supported(rdev);
6384 #else
6385         eg_pi->pcie_performance_request = false;
6386 #endif
6387
6388         si_pi->sram_end = SMC_RAM_END;
6389
6390         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6391         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6392         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6393         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6394         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6395         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6396         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6397
6398         si_initialize_powertune_defaults(rdev);
6399
6400         return 0;
6401 }
6402
6403 void si_dpm_fini(struct radeon_device *rdev)
6404 {
6405         int i;
6406
6407         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6408                 kfree(rdev->pm.dpm.ps[i].ps_priv);
6409         }
6410         kfree(rdev->pm.dpm.ps);
6411         kfree(rdev->pm.dpm.priv);
6412         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6413         r600_free_extended_power_table(rdev);
6414 }
6415
6416 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6417                                                     struct seq_file *m)
6418 {
6419         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
6420         struct ni_ps *ps = ni_get_ps(rps);
6421         struct rv7xx_pl *pl;
6422         u32 current_index =
6423                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6424                 CURRENT_STATE_INDEX_SHIFT;
6425
6426         if (current_index >= ps->performance_level_count) {
6427                 seq_printf(m, "invalid dpm profile %d\n", current_index);
6428         } else {
6429                 pl = &ps->performance_levels[current_index];
6430                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6431                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6432                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6433         }
6434 }