drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 void
 113 intel_edp_link_config(struct intel_encoder *intel_encoder,
 114                        int *lane_num, int *link_bw)
 115 {
 116         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 117
 118         *lane_num = intel_dp->lane_count;
 119         *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 120 }
 121
 122 int
 123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 124                        struct drm_display_mode *mode)
 125 {
 126         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 127         struct intel_connector *intel_connector = intel_dp->attached_connector;
 128
 129         if (intel_connector->panel.fixed_mode)
 130                 return intel_connector->panel.fixed_mode->clock;
 131         else
 132                 return mode->clock;
 133 }
 134
 135 static int
 136 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 137 {
 138         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 139
 140         switch (max_link_bw) {
 141         case DP_LINK_BW_1_62:
 142         case DP_LINK_BW_2_7:
 143                 break;
 144         default:
 145                 max_link_bw = DP_LINK_BW_1_62;
 146                 break;
 147         }
 148         return max_link_bw;
 149 }
 150
 151 /*
 152  * The units on the numbers in the next two are... bizarre.  Examples will
 153  * make it clearer; this one parallels an example in the eDP spec.
 154  *
 155  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 156  *
 157  *     270000 * 1 * 8 / 10 == 216000
 158  *
 159  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 160  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 161  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 162  * 119000.  At 18bpp that's 2142000 kilobits per second.
 163  *
 164  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 165  * get the result in decakilobits instead of kilobits.
 166  */
 167
 168 static int
 169 intel_dp_link_required(int pixel_clock, int bpp)
 170 {
 171         return (pixel_clock * bpp + 9) / 10;
 172 }
 173
 174 static int
 175 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 176 {
 177         return (max_link_clock * max_lanes * 8) / 10;
 178 }
 179
 180 static bool
 181 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 182                           struct drm_display_mode *mode,
 183                           bool adjust_mode)
 184 {
 185         int max_link_clock =
 186                 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 187         int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 188         int max_rate, mode_rate;
 189
 190         mode_rate = intel_dp_link_required(mode->clock, 24);
 191         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 192
 193         if (mode_rate > max_rate) {
 194                 mode_rate = intel_dp_link_required(mode->clock, 18);
 195                 if (mode_rate > max_rate)
 196                         return false;
 197
 198                 if (adjust_mode)
 199                         mode->private_flags
 200                                 |= INTEL_MODE_DP_FORCE_6BPC;
 201
 202                 return true;
 203         }
 204
 205         return true;
 206 }
 207
 208 static int
 209 intel_dp_mode_valid(struct drm_connector *connector,
 210                     struct drm_display_mode *mode)
 211 {
 212         struct intel_dp *intel_dp = intel_attached_dp(connector);
 213         struct intel_connector *intel_connector = to_intel_connector(connector);
 214         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 215
 216         if (is_edp(intel_dp) && fixed_mode) {
 217                 if (mode->hdisplay > fixed_mode->hdisplay)
 218                         return MODE_PANEL;
 219
 220                 if (mode->vdisplay > fixed_mode->vdisplay)
 221                         return MODE_PANEL;
 222         }
 223
 224         if (!intel_dp_adjust_dithering(intel_dp, mode, false))
 225                 return MODE_CLOCK_HIGH;
 226
 227         if (mode->clock < 10000)
 228                 return MODE_CLOCK_LOW;
 229
 230         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 231                 return MODE_H_ILLEGAL;
 232
 233         return MODE_OK;
 234 }
 235
 236 static uint32_t
 237 pack_aux(uint8_t *src, int src_bytes)
 238 {
 239         int     i;
 240         uint32_t v = 0;
 241
 242         if (src_bytes > 4)
 243                 src_bytes = 4;
 244         for (i = 0; i < src_bytes; i++)
 245                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 246         return v;
 247 }
 248
 249 static void
 250 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 251 {
 252         int i;
 253         if (dst_bytes > 4)
 254                 dst_bytes = 4;
 255         for (i = 0; i < dst_bytes; i++)
 256                 dst[i] = src >> ((3-i) * 8);
 257 }
 258
 259 /* hrawclock is 1/4 the FSB frequency */
 260 static int
 261 intel_hrawclk(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         uint32_t clkcfg;
 265
 266         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 267         if (IS_VALLEYVIEW(dev))
 268                 return 200;
 269
 270         clkcfg = I915_READ(CLKCFG);
 271         switch (clkcfg & CLKCFG_FSB_MASK) {
 272         case CLKCFG_FSB_400:
 273                 return 100;
 274         case CLKCFG_FSB_533:
 275                 return 133;
 276         case CLKCFG_FSB_667:
 277                 return 166;
 278         case CLKCFG_FSB_800:
 279                 return 200;
 280         case CLKCFG_FSB_1067:
 281                 return 266;
 282         case CLKCFG_FSB_1333:
 283                 return 333;
 284         /* these two are just a guess; one of them might be right */
 285         case CLKCFG_FSB_1600:
 286         case CLKCFG_FSB_1600_ALT:
 287                 return 400;
 288         default:
 289                 return 133;
 290         }
 291 }
 292
 293 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 294 {
 295         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 296         struct drm_i915_private *dev_priv = dev->dev_private;
 297
 298         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 299 }
 300
 301 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 302 {
 303         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 304         struct drm_i915_private *dev_priv = dev->dev_private;
 305
 306         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 307 }
 308
 309 static void
 310 intel_dp_check_edp(struct intel_dp *intel_dp)
 311 {
 312         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314
 315         if (!is_edp(intel_dp))
 316                 return;
 317         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 318                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 319                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 320                               I915_READ(PCH_PP_STATUS),
 321                               I915_READ(PCH_PP_CONTROL));
 322         }
 323 }
 324
 325 static uint32_t
 326 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 327 {
 328         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 329         struct drm_device *dev = intel_dig_port->base.base.dev;
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 332         uint32_t status;
 333         bool done;
 334
 335 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 336         if (has_aux_irq)
 337                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 338                                           msecs_to_jiffies(10));
 339         else
 340                 done = wait_for_atomic(C, 10) == 0;
 341         if (!done)
 342                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 343                           has_aux_irq);
 344 #undef C
 345
 346         return status;
 347 }
 348
 349 static int
 350 intel_dp_aux_ch(struct intel_dp *intel_dp,
 351                 uint8_t *send, int send_bytes,
 352                 uint8_t *recv, int recv_size)
 353 {
 354         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 355         struct drm_device *dev = intel_dig_port->base.base.dev;
 356         struct drm_i915_private *dev_priv = dev->dev_private;
 357         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 358         uint32_t ch_data = ch_ctl + 4;
 359         int i, ret, recv_bytes;
 360         uint32_t status;
 361         uint32_t aux_clock_divider;
 362         int try, precharge;
 363         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 364
 365         /* dp aux is extremely sensitive to irq latency, hence request the
 366          * lowest possible wakeup latency and so prevent the cpu from going into
 367          * deep sleep states.
 368          */
 369         pm_qos_update_request(&dev_priv->pm_qos, 0);
 370
 371         intel_dp_check_edp(intel_dp);
 372         /* The clock divider is based off the hrawclk,
 373          * and would like to run at 2MHz. So, take the
 374          * hrawclk value and divide by 2 and use that
 375          *
 376          * Note that PCH attached eDP panels should use a 125MHz input
 377          * clock divider.
 378          */
 379         if (is_cpu_edp(intel_dp)) {
 380                 if (HAS_DDI(dev))
 381                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 382                 else if (IS_VALLEYVIEW(dev))
 383                         aux_clock_divider = 100;
 384                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 385                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 386                 else
 387                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 388         } else if (HAS_PCH_SPLIT(dev))
 389                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 390         else
 391                 aux_clock_divider = intel_hrawclk(dev) / 2;
 392
 393         if (IS_GEN6(dev))
 394                 precharge = 3;
 395         else
 396                 precharge = 5;
 397
 398         /* Try to wait for any previous AUX channel activity */
 399         for (try = 0; try < 3; try++) {
 400                 status = I915_READ_NOTRACE(ch_ctl);
 401                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 402                         break;
 403                 msleep(1);
 404         }
 405
 406         if (try == 3) {
 407                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 408                      I915_READ(ch_ctl));
 409                 ret = -EBUSY;
 410                 goto out;
 411         }
 412
 413         /* Must try at least 3 times according to DP spec */
 414         for (try = 0; try < 5; try++) {
 415                 /* Load the send data into the aux channel data registers */
 416                 for (i = 0; i < send_bytes; i += 4)
 417                         I915_WRITE(ch_data + i,
 418                                    pack_aux(send + i, send_bytes - i));
 419
 420                 /* Send the command and wait for it to complete */
 421                 I915_WRITE(ch_ctl,
 422                            DP_AUX_CH_CTL_SEND_BUSY |
 423                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 424                            DP_AUX_CH_CTL_TIME_OUT_400us |
 425                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 426                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 427                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 428                            DP_AUX_CH_CTL_DONE |
 429                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 430                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 431
 432                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 433
 434                 /* Clear done status and any errors */
 435                 I915_WRITE(ch_ctl,
 436                            status |
 437                            DP_AUX_CH_CTL_DONE |
 438                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 439                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 440
 441                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 442                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 443                         continue;
 444                 if (status & DP_AUX_CH_CTL_DONE)
 445                         break;
 446         }
 447
 448         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 449                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 450                 ret = -EBUSY;
 451                 goto out;
 452         }
 453
 454         /* Check for timeout or receive error.
 455          * Timeouts occur when the sink is not connected
 456          */
 457         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 458                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 459                 ret = -EIO;
 460                 goto out;
 461         }
 462
 463         /* Timeouts occur when the device isn't connected, so they're
 464          * "normal" -- don't fill the kernel log with these */
 465         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 466                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 467                 ret = -ETIMEDOUT;
 468                 goto out;
 469         }
 470
 471         /* Unload any bytes sent back from the other side */
 472         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 473                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 474         if (recv_bytes > recv_size)
 475                 recv_bytes = recv_size;
 476
 477         for (i = 0; i < recv_bytes; i += 4)
 478                 unpack_aux(I915_READ(ch_data + i),
 479                            recv + i, recv_bytes - i);
 480
 481         ret = recv_bytes;
 482 out:
 483         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 484
 485         return ret;
 486 }
 487
 488 /* Write data to the aux channel in native mode */
 489 static int
 490 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 491                           uint16_t address, uint8_t *send, int send_bytes)
 492 {
 493         int ret;
 494         uint8_t msg[20];
 495         int msg_bytes;
 496         uint8_t ack;
 497
 498         intel_dp_check_edp(intel_dp);
 499         if (send_bytes > 16)
 500                 return -1;
 501         msg[0] = AUX_NATIVE_WRITE << 4;
 502         msg[1] = address >> 8;
 503         msg[2] = address & 0xff;
 504         msg[3] = send_bytes - 1;
 505         memcpy(&msg[4], send, send_bytes);
 506         msg_bytes = send_bytes + 4;
 507         for (;;) {
 508                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 509                 if (ret < 0)
 510                         return ret;
 511                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 512                         break;
 513                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 514                         udelay(100);
 515                 else
 516                         return -EIO;
 517         }
 518         return send_bytes;
 519 }
 520
 521 /* Write a single byte to the aux channel in native mode */
 522 static int
 523 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 524                             uint16_t address, uint8_t byte)
 525 {
 526         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 527 }
 528
 529 /* read bytes from a native aux channel */
 530 static int
 531 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 532                          uint16_t address, uint8_t *recv, int recv_bytes)
 533 {
 534         uint8_t msg[4];
 535         int msg_bytes;
 536         uint8_t reply[20];
 537         int reply_bytes;
 538         uint8_t ack;
 539         int ret;
 540
 541         intel_dp_check_edp(intel_dp);
 542         msg[0] = AUX_NATIVE_READ << 4;
 543         msg[1] = address >> 8;
 544         msg[2] = address & 0xff;
 545         msg[3] = recv_bytes - 1;
 546
 547         msg_bytes = 4;
 548         reply_bytes = recv_bytes + 1;
 549
 550         for (;;) {
 551                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 552                                       reply, reply_bytes);
 553                 if (ret == 0)
 554                         return -EPROTO;
 555                 if (ret < 0)
 556                         return ret;
 557                 ack = reply[0];
 558                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 559                         memcpy(recv, reply + 1, ret - 1);
 560                         return ret - 1;
 561                 }
 562                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 563                         udelay(100);
 564                 else
 565                         return -EIO;
 566         }
 567 }
 568
 569 static int
 570 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 571                     uint8_t write_byte, uint8_t *read_byte)
 572 {
 573         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 574         struct intel_dp *intel_dp = container_of(adapter,
 575                                                 struct intel_dp,
 576                                                 adapter);
 577         uint16_t address = algo_data->address;
 578         uint8_t msg[5];
 579         uint8_t reply[2];
 580         unsigned retry;
 581         int msg_bytes;
 582         int reply_bytes;
 583         int ret;
 584
 585         intel_dp_check_edp(intel_dp);
 586         /* Set up the command byte */
 587         if (mode & MODE_I2C_READ)
 588                 msg[0] = AUX_I2C_READ << 4;
 589         else
 590                 msg[0] = AUX_I2C_WRITE << 4;
 591
 592         if (!(mode & MODE_I2C_STOP))
 593                 msg[0] |= AUX_I2C_MOT << 4;
 594
 595         msg[1] = address >> 8;
 596         msg[2] = address;
 597
 598         switch (mode) {
 599         case MODE_I2C_WRITE:
 600                 msg[3] = 0;
 601                 msg[4] = write_byte;
 602                 msg_bytes = 5;
 603                 reply_bytes = 1;
 604                 break;
 605         case MODE_I2C_READ:
 606                 msg[3] = 0;
 607                 msg_bytes = 4;
 608                 reply_bytes = 2;
 609                 break;
 610         default:
 611                 msg_bytes = 3;
 612                 reply_bytes = 1;
 613                 break;
 614         }
 615
 616         for (retry = 0; retry < 5; retry++) {
 617                 ret = intel_dp_aux_ch(intel_dp,
 618                                       msg, msg_bytes,
 619                                       reply, reply_bytes);
 620                 if (ret < 0) {
 621                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 622                         return ret;
 623                 }
 624
 625                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 626                 case AUX_NATIVE_REPLY_ACK:
 627                         /* I2C-over-AUX Reply field is only valid
 628                          * when paired with AUX ACK.
 629                          */
 630                         break;
 631                 case AUX_NATIVE_REPLY_NACK:
 632                         DRM_DEBUG_KMS("aux_ch native nack\n");
 633                         return -EREMOTEIO;
 634                 case AUX_NATIVE_REPLY_DEFER:
 635                         udelay(100);
 636                         continue;
 637                 default:
 638                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 639                                   reply[0]);
 640                         return -EREMOTEIO;
 641                 }
 642
 643                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 644                 case AUX_I2C_REPLY_ACK:
 645                         if (mode == MODE_I2C_READ) {
 646                                 *read_byte = reply[1];
 647                         }
 648                         return reply_bytes - 1;
 649                 case AUX_I2C_REPLY_NACK:
 650                         DRM_DEBUG_KMS("aux_i2c nack\n");
 651                         return -EREMOTEIO;
 652                 case AUX_I2C_REPLY_DEFER:
 653                         DRM_DEBUG_KMS("aux_i2c defer\n");
 654                         udelay(100);
 655                         break;
 656                 default:
 657                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 658                         return -EREMOTEIO;
 659                 }
 660         }
 661
 662         DRM_ERROR("too many retries, giving up\n");
 663         return -EREMOTEIO;
 664 }
 665
 666 static int
 667 intel_dp_i2c_init(struct intel_dp *intel_dp,
 668                   struct intel_connector *intel_connector, const char *name)
 669 {
 670         int     ret;
 671
 672         DRM_DEBUG_KMS("i2c_init %s\n", name);
 673         intel_dp->algo.running = false;
 674         intel_dp->algo.address = 0;
 675         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 676
 677         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 678         intel_dp->adapter.owner = THIS_MODULE;
 679         intel_dp->adapter.class = I2C_CLASS_DDC;
 680         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 681         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 682         intel_dp->adapter.algo_data = &intel_dp->algo;
 683         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 684
 685         ironlake_edp_panel_vdd_on(intel_dp);
 686         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 687         ironlake_edp_panel_vdd_off(intel_dp, false);
 688         return ret;
 689 }
 690
 691 bool
 692 intel_dp_mode_fixup(struct drm_encoder *encoder,
 693                     const struct drm_display_mode *mode,
 694                     struct drm_display_mode *adjusted_mode)
 695 {
 696         struct drm_device *dev = encoder->dev;
 697         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 698         struct intel_connector *intel_connector = intel_dp->attached_connector;
 699         int lane_count, clock;
 700         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 701         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 702         int bpp, mode_rate;
 703         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 704
 705         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 706                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 707                                        adjusted_mode);
 708                 intel_pch_panel_fitting(dev,
 709                                         intel_connector->panel.fitting_mode,
 710                                         mode, adjusted_mode);
 711         }
 712
 713         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 714                 return false;
 715
 716         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 717                       "max bw %02x pixel clock %iKHz\n",
 718                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 719
 720         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
 721                 return false;
 722
 723         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 724
 725         if (intel_dp->color_range_auto) {
 726                 /*
 727                  * See:
 728                  * CEA-861-E - 5.1 Default Encoding Parameters
 729                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 730                  */
 731                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 732                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 733                 else
 734                         intel_dp->color_range = 0;
 735         }
 736
 737         if (intel_dp->color_range)
 738                 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
 739
 740         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 741
 742         for (clock = 0; clock <= max_clock; clock++) {
 743                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 744                         int link_bw_clock =
 745                                 drm_dp_bw_code_to_link_rate(bws[clock]);
 746                         int link_avail = intel_dp_max_data_rate(link_bw_clock,
 747                                                                 lane_count);
 748
 749                         if (mode_rate <= link_avail) {
 750                                 intel_dp->link_bw = bws[clock];
 751                                 intel_dp->lane_count = lane_count;
 752                                 adjusted_mode->clock = link_bw_clock;
 753                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 754                                                 "count %d clock %d bpp %d\n",
 755                                        intel_dp->link_bw, intel_dp->lane_count,
 756                                        adjusted_mode->clock, bpp);
 757                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 758                                               mode_rate, link_avail);
 759                                 return true;
 760                         }
 761                 }
 762         }
 763
 764         return false;
 765 }
 766
 767 void
 768 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 769                  struct drm_display_mode *adjusted_mode)
 770 {
 771         struct drm_device *dev = crtc->dev;
 772         struct intel_encoder *intel_encoder;
 773         struct intel_dp *intel_dp;
 774         struct drm_i915_private *dev_priv = dev->dev_private;
 775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 776         int lane_count = 4;
 777         struct intel_link_m_n m_n;
 778         int pipe = intel_crtc->pipe;
 779         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 780         int target_clock;
 781
 782         /*
 783          * Find the lane count in the intel_encoder private
 784          */
 785         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 786                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
 787
 788                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 789                     intel_encoder->type == INTEL_OUTPUT_EDP)
 790                 {
 791                         lane_count = intel_dp->lane_count;
 792                         break;
 793                 }
 794         }
 795
 796         target_clock = mode->clock;
 797         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 798                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
 799                         target_clock = intel_edp_target_clock(intel_encoder,
 800                                                               mode);
 801                         break;
 802                 }
 803         }
 804
 805         /*
 806          * Compute the GMCH and Link ratios. The '3' here is
 807          * the number of bytes_per_pixel post-LUT, which we always
 808          * set up for 8-bits of R/G/B, or 3 bytes total.
 809          */
 810         intel_link_compute_m_n(intel_crtc->bpp, lane_count,
 811                                target_clock, adjusted_mode->clock, &m_n);
 812
 813         if (HAS_DDI(dev)) {
 814                 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
 815                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 816                 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
 817                 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
 818                 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 819         } else if (HAS_PCH_SPLIT(dev)) {
 820                 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 821                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 822                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 823                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 824         } else if (IS_VALLEYVIEW(dev)) {
 825                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 826                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 827                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 828                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 829         } else {
 830                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 831                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 832                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 833                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 834                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 835         }
 836 }
 837
 838 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 839 {
 840         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 841         intel_dp->link_configuration[0] = intel_dp->link_bw;
 842         intel_dp->link_configuration[1] = intel_dp->lane_count;
 843         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 844         /*
 845          * Check for DPCD version > 1.1 and enhanced framing support
 846          */
 847         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 848             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 849                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 850         }
 851 }
 852
 853 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 854 {
 855         struct drm_device *dev = crtc->dev;
 856         struct drm_i915_private *dev_priv = dev->dev_private;
 857         u32 dpa_ctl;
 858
 859         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 860         dpa_ctl = I915_READ(DP_A);
 861         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 862
 863         if (clock < 200000) {
 864                 /* For a long time we've carried around a ILK-DevA w/a for the
 865                  * 160MHz clock. If we're really unlucky, it's still required.
 866                  */
 867                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 868                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 869         } else {
 870                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 871         }
 872
 873         I915_WRITE(DP_A, dpa_ctl);
 874
 875         POSTING_READ(DP_A);
 876         udelay(500);
 877 }
 878
 879 static void
 880 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 881                   struct drm_display_mode *adjusted_mode)
 882 {
 883         struct drm_device *dev = encoder->dev;
 884         struct drm_i915_private *dev_priv = dev->dev_private;
 885         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 886         struct drm_crtc *crtc = encoder->crtc;
 887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 888
 889         /*
 890          * There are four kinds of DP registers:
 891          *
 892          *      IBX PCH
 893          *      SNB CPU
 894          *      IVB CPU
 895          *      CPT PCH
 896          *
 897          * IBX PCH and CPU are the same for almost everything,
 898          * except that the CPU DP PLL is configured in this
 899          * register
 900          *
 901          * CPT PCH is quite different, having many bits moved
 902          * to the TRANS_DP_CTL register instead. That
 903          * configuration happens (oddly) in ironlake_pch_enable
 904          */
 905
 906         /* Preserve the BIOS-computed detected bit. This is
 907          * supposed to be read-only.
 908          */
 909         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 910
 911         /* Handle DP bits in common between all three register formats */
 912         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 913
 914         switch (intel_dp->lane_count) {
 915         case 1:
 916                 intel_dp->DP |= DP_PORT_WIDTH_1;
 917                 break;
 918         case 2:
 919                 intel_dp->DP |= DP_PORT_WIDTH_2;
 920                 break;
 921         case 4:
 922                 intel_dp->DP |= DP_PORT_WIDTH_4;
 923                 break;
 924         }
 925         if (intel_dp->has_audio) {
 926                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 927                                  pipe_name(intel_crtc->pipe));
 928                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 929                 intel_write_eld(encoder, adjusted_mode);
 930         }
 931
 932         intel_dp_init_link_config(intel_dp);
 933
 934         /* Split out the IBX/CPU vs CPT settings */
 935
 936         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 937                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 938                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 939                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 940                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 941                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 942
 943                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 944                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 945
 946                 intel_dp->DP |= intel_crtc->pipe << 29;
 947
 948                 /* don't miss out required setting for eDP */
 949                 if (adjusted_mode->clock < 200000)
 950                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 951                 else
 952                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 953         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 954                 if (!HAS_PCH_SPLIT(dev))
 955                         intel_dp->DP |= intel_dp->color_range;
 956
 957                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 958                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 959                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 960                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 961                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 962
 963                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 964                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 965
 966                 if (intel_crtc->pipe == 1)
 967                         intel_dp->DP |= DP_PIPEB_SELECT;
 968
 969                 if (is_cpu_edp(intel_dp)) {
 970                         /* don't miss out required setting for eDP */
 971                         if (adjusted_mode->clock < 200000)
 972                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 973                         else
 974                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 975                 }
 976         } else {
 977                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 978         }
 979
 980         if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
 981                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
 982 }
 983
 984 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 985 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 986
 987 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 988 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 989
 990 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 991 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 992
 993 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 994                                        u32 mask,
 995                                        u32 value)
 996 {
 997         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 998         struct drm_i915_private *dev_priv = dev->dev_private;
 999
1000         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1001                       mask, value,
1002                       I915_READ(PCH_PP_STATUS),
1003                       I915_READ(PCH_PP_CONTROL));
1004
1005         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1006                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1007                           I915_READ(PCH_PP_STATUS),
1008                           I915_READ(PCH_PP_CONTROL));
1009         }
1010 }
1011
1012 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1013 {
1014         DRM_DEBUG_KMS("Wait for panel power on\n");
1015         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1016 }
1017
1018 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1019 {
1020         DRM_DEBUG_KMS("Wait for panel power off time\n");
1021         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1022 }
1023
1024 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1025 {
1026         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1027         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1028 }
1029
1030
1031 /* Read the current pp_control value, unlocking the register if it
1032  * is locked
1033  */
1034
1035 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1036 {
1037         u32     control = I915_READ(PCH_PP_CONTROL);
1038
1039         control &= ~PANEL_UNLOCK_MASK;
1040         control |= PANEL_UNLOCK_REGS;
1041         return control;
1042 }
1043
1044 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1045 {
1046         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1047         struct drm_i915_private *dev_priv = dev->dev_private;
1048         u32 pp;
1049
1050         if (!is_edp(intel_dp))
1051                 return;
1052         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1053
1054         WARN(intel_dp->want_panel_vdd,
1055              "eDP VDD already requested on\n");
1056
1057         intel_dp->want_panel_vdd = true;
1058
1059         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1060                 DRM_DEBUG_KMS("eDP VDD already on\n");
1061                 return;
1062         }
1063
1064         if (!ironlake_edp_have_panel_power(intel_dp))
1065                 ironlake_wait_panel_power_cycle(intel_dp);
1066
1067         pp = ironlake_get_pp_control(dev_priv);
1068         pp |= EDP_FORCE_VDD;
1069         I915_WRITE(PCH_PP_CONTROL, pp);
1070         POSTING_READ(PCH_PP_CONTROL);
1071         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1072                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1073
1074         /*
1075          * If the panel wasn't on, delay before accessing aux channel
1076          */
1077         if (!ironlake_edp_have_panel_power(intel_dp)) {
1078                 DRM_DEBUG_KMS("eDP was not running\n");
1079                 msleep(intel_dp->panel_power_up_delay);
1080         }
1081 }
1082
1083 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1084 {
1085         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1086         struct drm_i915_private *dev_priv = dev->dev_private;
1087         u32 pp;
1088
1089         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1090
1091         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1092                 pp = ironlake_get_pp_control(dev_priv);
1093                 pp &= ~EDP_FORCE_VDD;
1094                 I915_WRITE(PCH_PP_CONTROL, pp);
1095                 POSTING_READ(PCH_PP_CONTROL);
1096
1097                 /* Make sure sequencer is idle before allowing subsequent activity */
1098                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1099                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1100
1101                 msleep(intel_dp->panel_power_down_delay);
1102         }
1103 }
1104
1105 static void ironlake_panel_vdd_work(struct work_struct *__work)
1106 {
1107         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1108                                                  struct intel_dp, panel_vdd_work);
1109         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1110
1111         mutex_lock(&dev->mode_config.mutex);
1112         ironlake_panel_vdd_off_sync(intel_dp);
1113         mutex_unlock(&dev->mode_config.mutex);
1114 }
1115
1116 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1117 {
1118         if (!is_edp(intel_dp))
1119                 return;
1120
1121         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1122         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1123
1124         intel_dp->want_panel_vdd = false;
1125
1126         if (sync) {
1127                 ironlake_panel_vdd_off_sync(intel_dp);
1128         } else {
1129                 /*
1130                  * Queue the timer to fire a long
1131                  * time from now (relative to the power down delay)
1132                  * to keep the panel power up across a sequence of operations
1133                  */
1134                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1135                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1136         }
1137 }
1138
1139 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1140 {
1141         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1142         struct drm_i915_private *dev_priv = dev->dev_private;
1143         u32 pp;
1144
1145         if (!is_edp(intel_dp))
1146                 return;
1147
1148         DRM_DEBUG_KMS("Turn eDP power on\n");
1149
1150         if (ironlake_edp_have_panel_power(intel_dp)) {
1151                 DRM_DEBUG_KMS("eDP power already on\n");
1152                 return;
1153         }
1154
1155         ironlake_wait_panel_power_cycle(intel_dp);
1156
1157         pp = ironlake_get_pp_control(dev_priv);
1158         if (IS_GEN5(dev)) {
1159                 /* ILK workaround: disable reset around power sequence */
1160                 pp &= ~PANEL_POWER_RESET;
1161                 I915_WRITE(PCH_PP_CONTROL, pp);
1162                 POSTING_READ(PCH_PP_CONTROL);
1163         }
1164
1165         pp |= POWER_TARGET_ON;
1166         if (!IS_GEN5(dev))
1167                 pp |= PANEL_POWER_RESET;
1168
1169         I915_WRITE(PCH_PP_CONTROL, pp);
1170         POSTING_READ(PCH_PP_CONTROL);
1171
1172         ironlake_wait_panel_on(intel_dp);
1173
1174         if (IS_GEN5(dev)) {
1175                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1176                 I915_WRITE(PCH_PP_CONTROL, pp);
1177                 POSTING_READ(PCH_PP_CONTROL);
1178         }
1179 }
1180
1181 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1182 {
1183         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1184         struct drm_i915_private *dev_priv = dev->dev_private;
1185         u32 pp;
1186
1187         if (!is_edp(intel_dp))
1188                 return;
1189
1190         DRM_DEBUG_KMS("Turn eDP power off\n");
1191
1192         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1193
1194         pp = ironlake_get_pp_control(dev_priv);
1195         /* We need to switch off panel power _and_ force vdd, for otherwise some
1196          * panels get very unhappy and cease to work. */
1197         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1198         I915_WRITE(PCH_PP_CONTROL, pp);
1199         POSTING_READ(PCH_PP_CONTROL);
1200
1201         intel_dp->want_panel_vdd = false;
1202
1203         ironlake_wait_panel_off(intel_dp);
1204 }
1205
1206 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1207 {
1208         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1209         struct drm_device *dev = intel_dig_port->base.base.dev;
1210         struct drm_i915_private *dev_priv = dev->dev_private;
1211         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1212         u32 pp;
1213
1214         if (!is_edp(intel_dp))
1215                 return;
1216
1217         DRM_DEBUG_KMS("\n");
1218         /*
1219          * If we enable the backlight right away following a panel power
1220          * on, we may see slight flicker as the panel syncs with the eDP
1221          * link.  So delay a bit to make sure the image is solid before
1222          * allowing it to appear.
1223          */
1224         msleep(intel_dp->backlight_on_delay);
1225         pp = ironlake_get_pp_control(dev_priv);
1226         pp |= EDP_BLC_ENABLE;
1227         I915_WRITE(PCH_PP_CONTROL, pp);
1228         POSTING_READ(PCH_PP_CONTROL);
1229
1230         intel_panel_enable_backlight(dev, pipe);
1231 }
1232
1233 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1234 {
1235         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1236         struct drm_i915_private *dev_priv = dev->dev_private;
1237         u32 pp;
1238
1239         if (!is_edp(intel_dp))
1240                 return;
1241
1242         intel_panel_disable_backlight(dev);
1243
1244         DRM_DEBUG_KMS("\n");
1245         pp = ironlake_get_pp_control(dev_priv);
1246         pp &= ~EDP_BLC_ENABLE;
1247         I915_WRITE(PCH_PP_CONTROL, pp);
1248         POSTING_READ(PCH_PP_CONTROL);
1249         msleep(intel_dp->backlight_off_delay);
1250 }
1251
1252 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1253 {
1254         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1255         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1256         struct drm_device *dev = crtc->dev;
1257         struct drm_i915_private *dev_priv = dev->dev_private;
1258         u32 dpa_ctl;
1259
1260         assert_pipe_disabled(dev_priv,
1261                              to_intel_crtc(crtc)->pipe);
1262
1263         DRM_DEBUG_KMS("\n");
1264         dpa_ctl = I915_READ(DP_A);
1265         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1266         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1267
1268         /* We don't adjust intel_dp->DP while tearing down the link, to
1269          * facilitate link retraining (e.g. after hotplug). Hence clear all
1270          * enable bits here to ensure that we don't enable too much. */
1271         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1272         intel_dp->DP |= DP_PLL_ENABLE;
1273         I915_WRITE(DP_A, intel_dp->DP);
1274         POSTING_READ(DP_A);
1275         udelay(200);
1276 }
1277
1278 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1279 {
1280         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1281         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1282         struct drm_device *dev = crtc->dev;
1283         struct drm_i915_private *dev_priv = dev->dev_private;
1284         u32 dpa_ctl;
1285
1286         assert_pipe_disabled(dev_priv,
1287                              to_intel_crtc(crtc)->pipe);
1288
1289         dpa_ctl = I915_READ(DP_A);
1290         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1291              "dp pll off, should be on\n");
1292         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1293
1294         /* We can't rely on the value tracked for the DP register in
1295          * intel_dp->DP because link_down must not change that (otherwise link
1296          * re-training will fail. */
1297         dpa_ctl &= ~DP_PLL_ENABLE;
1298         I915_WRITE(DP_A, dpa_ctl);
1299         POSTING_READ(DP_A);
1300         udelay(200);
1301 }
1302
1303 /* If the sink supports it, try to set the power state appropriately */
1304 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1305 {
1306         int ret, i;
1307
1308         /* Should have a valid DPCD by this point */
1309         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1310                 return;
1311
1312         if (mode != DRM_MODE_DPMS_ON) {
1313                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1314                                                   DP_SET_POWER_D3);
1315                 if (ret != 1)
1316                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1317         } else {
1318                 /*
1319                  * When turning on, we need to retry for 1ms to give the sink
1320                  * time to wake up.
1321                  */
1322                 for (i = 0; i < 3; i++) {
1323                         ret = intel_dp_aux_native_write_1(intel_dp,
1324                                                           DP_SET_POWER,
1325                                                           DP_SET_POWER_D0);
1326                         if (ret == 1)
1327                                 break;
1328                         msleep(1);
1329                 }
1330         }
1331 }
1332
1333 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1334                                   enum pipe *pipe)
1335 {
1336         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1337         struct drm_device *dev = encoder->base.dev;
1338         struct drm_i915_private *dev_priv = dev->dev_private;
1339         u32 tmp = I915_READ(intel_dp->output_reg);
1340
1341         if (!(tmp & DP_PORT_EN))
1342                 return false;
1343
1344         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1345                 *pipe = PORT_TO_PIPE_CPT(tmp);
1346         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1347                 *pipe = PORT_TO_PIPE(tmp);
1348         } else {
1349                 u32 trans_sel;
1350                 u32 trans_dp;
1351                 int i;
1352
1353                 switch (intel_dp->output_reg) {
1354                 case PCH_DP_B:
1355                         trans_sel = TRANS_DP_PORT_SEL_B;
1356                         break;
1357                 case PCH_DP_C:
1358                         trans_sel = TRANS_DP_PORT_SEL_C;
1359                         break;
1360                 case PCH_DP_D:
1361                         trans_sel = TRANS_DP_PORT_SEL_D;
1362                         break;
1363                 default:
1364                         return true;
1365                 }
1366
1367                 for_each_pipe(i) {
1368                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1369                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1370                                 *pipe = i;
1371                                 return true;
1372                         }
1373                 }
1374
1375                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1376                               intel_dp->output_reg);
1377         }
1378
1379         return true;
1380 }
1381
1382 static void intel_disable_dp(struct intel_encoder *encoder)
1383 {
1384         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1385
1386         /* Make sure the panel is off before trying to change the mode. But also
1387          * ensure that we have vdd while we switch off the panel. */
1388         ironlake_edp_panel_vdd_on(intel_dp);
1389         ironlake_edp_backlight_off(intel_dp);
1390         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1391         ironlake_edp_panel_off(intel_dp);
1392
1393         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1394         if (!is_cpu_edp(intel_dp))
1395                 intel_dp_link_down(intel_dp);
1396 }
1397
1398 static void intel_post_disable_dp(struct intel_encoder *encoder)
1399 {
1400         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1401
1402         if (is_cpu_edp(intel_dp)) {
1403                 intel_dp_link_down(intel_dp);
1404                 ironlake_edp_pll_off(intel_dp);
1405         }
1406 }
1407
1408 static void intel_enable_dp(struct intel_encoder *encoder)
1409 {
1410         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1411         struct drm_device *dev = encoder->base.dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1414
1415         if (WARN_ON(dp_reg & DP_PORT_EN))
1416                 return;
1417
1418         ironlake_edp_panel_vdd_on(intel_dp);
1419         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1420         intel_dp_start_link_train(intel_dp);
1421         ironlake_edp_panel_on(intel_dp);
1422         ironlake_edp_panel_vdd_off(intel_dp, true);
1423         intel_dp_complete_link_train(intel_dp);
1424         ironlake_edp_backlight_on(intel_dp);
1425 }
1426
1427 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1428 {
1429         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1430
1431         if (is_cpu_edp(intel_dp))
1432                 ironlake_edp_pll_on(intel_dp);
1433 }
1434
1435 /*
1436  * Native read with retry for link status and receiver capability reads for
1437  * cases where the sink may still be asleep.
1438  */
1439 static bool
1440 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1441                                uint8_t *recv, int recv_bytes)
1442 {
1443         int ret, i;
1444
1445         /*
1446          * Sinks are *supposed* to come up within 1ms from an off state,
1447          * but we're also supposed to retry 3 times per the spec.
1448          */
1449         for (i = 0; i < 3; i++) {
1450                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1451                                                recv_bytes);
1452                 if (ret == recv_bytes)
1453                         return true;
1454                 msleep(1);
1455         }
1456
1457         return false;
1458 }
1459
1460 /*
1461  * Fetch AUX CH registers 0x202 - 0x207 which contain
1462  * link status information
1463  */
1464 static bool
1465 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1466 {
1467         return intel_dp_aux_native_read_retry(intel_dp,
1468                                               DP_LANE0_1_STATUS,
1469                                               link_status,
1470                                               DP_LINK_STATUS_SIZE);
1471 }
1472
1473 #if 0
1474 static char     *voltage_names[] = {
1475         "0.4V", "0.6V", "0.8V", "1.2V"
1476 };
1477 static char     *pre_emph_names[] = {
1478         "0dB", "3.5dB", "6dB", "9.5dB"
1479 };
1480 static char     *link_train_names[] = {
1481         "pattern 1", "pattern 2", "idle", "off"
1482 };
1483 #endif
1484
1485 /*
1486  * These are source-specific values; current Intel hardware supports
1487  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1488  */
1489
1490 static uint8_t
1491 intel_dp_voltage_max(struct intel_dp *intel_dp)
1492 {
1493         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1494
1495         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1496                 return DP_TRAIN_VOLTAGE_SWING_800;
1497         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1498                 return DP_TRAIN_VOLTAGE_SWING_1200;
1499         else
1500                 return DP_TRAIN_VOLTAGE_SWING_800;
1501 }
1502
1503 static uint8_t
1504 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1505 {
1506         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1507
1508         if (HAS_DDI(dev)) {
1509                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1510                 case DP_TRAIN_VOLTAGE_SWING_400:
1511                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1512                 case DP_TRAIN_VOLTAGE_SWING_600:
1513                         return DP_TRAIN_PRE_EMPHASIS_6;
1514                 case DP_TRAIN_VOLTAGE_SWING_800:
1515                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1516                 case DP_TRAIN_VOLTAGE_SWING_1200:
1517                 default:
1518                         return DP_TRAIN_PRE_EMPHASIS_0;
1519                 }
1520         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1521                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1522                 case DP_TRAIN_VOLTAGE_SWING_400:
1523                         return DP_TRAIN_PRE_EMPHASIS_6;
1524                 case DP_TRAIN_VOLTAGE_SWING_600:
1525                 case DP_TRAIN_VOLTAGE_SWING_800:
1526                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1527                 default:
1528                         return DP_TRAIN_PRE_EMPHASIS_0;
1529                 }
1530         } else {
1531                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1532                 case DP_TRAIN_VOLTAGE_SWING_400:
1533                         return DP_TRAIN_PRE_EMPHASIS_6;
1534                 case DP_TRAIN_VOLTAGE_SWING_600:
1535                         return DP_TRAIN_PRE_EMPHASIS_6;
1536                 case DP_TRAIN_VOLTAGE_SWING_800:
1537                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1538                 case DP_TRAIN_VOLTAGE_SWING_1200:
1539                 default:
1540                         return DP_TRAIN_PRE_EMPHASIS_0;
1541                 }
1542         }
1543 }
1544
1545 static void
1546 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1547 {
1548         uint8_t v = 0;
1549         uint8_t p = 0;
1550         int lane;
1551         uint8_t voltage_max;
1552         uint8_t preemph_max;
1553
1554         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1555                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1556                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1557
1558                 if (this_v > v)
1559                         v = this_v;
1560                 if (this_p > p)
1561                         p = this_p;
1562         }
1563
1564         voltage_max = intel_dp_voltage_max(intel_dp);
1565         if (v >= voltage_max)
1566                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1567
1568         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1569         if (p >= preemph_max)
1570                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1571
1572         for (lane = 0; lane < 4; lane++)
1573                 intel_dp->train_set[lane] = v | p;
1574 }
1575
1576 static uint32_t
1577 intel_gen4_signal_levels(uint8_t train_set)
1578 {
1579         uint32_t        signal_levels = 0;
1580
1581         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1582         case DP_TRAIN_VOLTAGE_SWING_400:
1583         default:
1584                 signal_levels |= DP_VOLTAGE_0_4;
1585                 break;
1586         case DP_TRAIN_VOLTAGE_SWING_600:
1587                 signal_levels |= DP_VOLTAGE_0_6;
1588                 break;
1589         case DP_TRAIN_VOLTAGE_SWING_800:
1590                 signal_levels |= DP_VOLTAGE_0_8;
1591                 break;
1592         case DP_TRAIN_VOLTAGE_SWING_1200:
1593                 signal_levels |= DP_VOLTAGE_1_2;
1594                 break;
1595         }
1596         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1597         case DP_TRAIN_PRE_EMPHASIS_0:
1598         default:
1599                 signal_levels |= DP_PRE_EMPHASIS_0;
1600                 break;
1601         case DP_TRAIN_PRE_EMPHASIS_3_5:
1602                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1603                 break;
1604         case DP_TRAIN_PRE_EMPHASIS_6:
1605                 signal_levels |= DP_PRE_EMPHASIS_6;
1606                 break;
1607         case DP_TRAIN_PRE_EMPHASIS_9_5:
1608                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1609                 break;
1610         }
1611         return signal_levels;
1612 }
1613
1614 /* Gen6's DP voltage swing and pre-emphasis control */
1615 static uint32_t
1616 intel_gen6_edp_signal_levels(uint8_t train_set)
1617 {
1618         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1619                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1620         switch (signal_levels) {
1621         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1622         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1623                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1624         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1625                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1626         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1627         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1628                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1629         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1630         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1631                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1632         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1633         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1634                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1635         default:
1636                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1637                               "0x%x\n", signal_levels);
1638                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1639         }
1640 }
1641
1642 /* Gen7's DP voltage swing and pre-emphasis control */
1643 static uint32_t
1644 intel_gen7_edp_signal_levels(uint8_t train_set)
1645 {
1646         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1647                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1648         switch (signal_levels) {
1649         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1650                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1651         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1652                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1653         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1654                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1655
1656         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1657                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1658         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1659                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1660
1661         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1662                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1663         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1664                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1665
1666         default:
1667                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1668                               "0x%x\n", signal_levels);
1669                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1670         }
1671 }
1672
1673 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1674 static uint32_t
1675 intel_hsw_signal_levels(uint8_t train_set)
1676 {
1677         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1678                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1679         switch (signal_levels) {
1680         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1681                 return DDI_BUF_EMP_400MV_0DB_HSW;
1682         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1683                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1684         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1685                 return DDI_BUF_EMP_400MV_6DB_HSW;
1686         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1687                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1688
1689         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1690                 return DDI_BUF_EMP_600MV_0DB_HSW;
1691         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1692                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1693         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1694                 return DDI_BUF_EMP_600MV_6DB_HSW;
1695
1696         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1697                 return DDI_BUF_EMP_800MV_0DB_HSW;
1698         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1699                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1700         default:
1701                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1702                               "0x%x\n", signal_levels);
1703                 return DDI_BUF_EMP_400MV_0DB_HSW;
1704         }
1705 }
1706
1707 /* Properly updates "DP" with the correct signal levels. */
1708 static void
1709 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1710 {
1711         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1712         struct drm_device *dev = intel_dig_port->base.base.dev;
1713         uint32_t signal_levels, mask;
1714         uint8_t train_set = intel_dp->train_set[0];
1715
1716         if (HAS_DDI(dev)) {
1717                 signal_levels = intel_hsw_signal_levels(train_set);
1718                 mask = DDI_BUF_EMP_MASK;
1719         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1720                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1721                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1722         } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1723                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1724                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1725         } else {
1726                 signal_levels = intel_gen4_signal_levels(train_set);
1727                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1728         }
1729
1730         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1731
1732         *DP = (*DP & ~mask) | signal_levels;
1733 }
1734
1735 static bool
1736 intel_dp_set_link_train(struct intel_dp *intel_dp,
1737                         uint32_t dp_reg_value,
1738                         uint8_t dp_train_pat)
1739 {
1740         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1741         struct drm_device *dev = intel_dig_port->base.base.dev;
1742         struct drm_i915_private *dev_priv = dev->dev_private;
1743         enum port port = intel_dig_port->port;
1744         int ret;
1745         uint32_t temp;
1746
1747         if (HAS_DDI(dev)) {
1748                 temp = I915_READ(DP_TP_CTL(port));
1749
1750                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1751                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1752                 else
1753                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1754
1755                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1756                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1757                 case DP_TRAINING_PATTERN_DISABLE:
1758
1759                         if (port != PORT_A) {
1760                                 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1761                                 I915_WRITE(DP_TP_CTL(port), temp);
1762
1763                                 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1764                                               DP_TP_STATUS_IDLE_DONE), 1))
1765                                         DRM_ERROR("Timed out waiting for DP idle patterns\n");
1766
1767                                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1768                         }
1769
1770                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1771
1772                         break;
1773                 case DP_TRAINING_PATTERN_1:
1774                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1775                         break;
1776                 case DP_TRAINING_PATTERN_2:
1777                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1778                         break;
1779                 case DP_TRAINING_PATTERN_3:
1780                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1781                         break;
1782                 }
1783                 I915_WRITE(DP_TP_CTL(port), temp);
1784
1785         } else if (HAS_PCH_CPT(dev) &&
1786                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1787                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1788
1789                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1790                 case DP_TRAINING_PATTERN_DISABLE:
1791                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1792                         break;
1793                 case DP_TRAINING_PATTERN_1:
1794                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1795                         break;
1796                 case DP_TRAINING_PATTERN_2:
1797                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1798                         break;
1799                 case DP_TRAINING_PATTERN_3:
1800                         DRM_ERROR("DP training pattern 3 not supported\n");
1801                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1802                         break;
1803                 }
1804
1805         } else {
1806                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1807
1808                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1809                 case DP_TRAINING_PATTERN_DISABLE:
1810                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1811                         break;
1812                 case DP_TRAINING_PATTERN_1:
1813                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1814                         break;
1815                 case DP_TRAINING_PATTERN_2:
1816                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1817                         break;
1818                 case DP_TRAINING_PATTERN_3:
1819                         DRM_ERROR("DP training pattern 3 not supported\n");
1820                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1821                         break;
1822                 }
1823         }
1824
1825         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1826         POSTING_READ(intel_dp->output_reg);
1827
1828         intel_dp_aux_native_write_1(intel_dp,
1829                                     DP_TRAINING_PATTERN_SET,
1830                                     dp_train_pat);
1831
1832         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1833             DP_TRAINING_PATTERN_DISABLE) {
1834                 ret = intel_dp_aux_native_write(intel_dp,
1835                                                 DP_TRAINING_LANE0_SET,
1836                                                 intel_dp->train_set,
1837                                                 intel_dp->lane_count);
1838                 if (ret != intel_dp->lane_count)
1839                         return false;
1840         }
1841
1842         return true;
1843 }
1844
1845 /* Enable corresponding port and start training pattern 1 */
1846 void
1847 intel_dp_start_link_train(struct intel_dp *intel_dp)
1848 {
1849         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1850         struct drm_device *dev = encoder->dev;
1851         int i;
1852         uint8_t voltage;
1853         bool clock_recovery = false;
1854         int voltage_tries, loop_tries;
1855         uint32_t DP = intel_dp->DP;
1856
1857         if (HAS_DDI(dev))
1858                 intel_ddi_prepare_link_retrain(encoder);
1859
1860         /* Write the link configuration data */
1861         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1862                                   intel_dp->link_configuration,
1863                                   DP_LINK_CONFIGURATION_SIZE);
1864
1865         DP |= DP_PORT_EN;
1866
1867         memset(intel_dp->train_set, 0, 4);
1868         voltage = 0xff;
1869         voltage_tries = 0;
1870         loop_tries = 0;
1871         clock_recovery = false;
1872         for (;;) {
1873                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1874                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1875
1876                 intel_dp_set_signal_levels(intel_dp, &DP);
1877
1878                 /* Set training pattern 1 */
1879                 if (!intel_dp_set_link_train(intel_dp, DP,
1880                                              DP_TRAINING_PATTERN_1 |
1881                                              DP_LINK_SCRAMBLING_DISABLE))
1882                         break;
1883
1884                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1885                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1886                         DRM_ERROR("failed to get link status\n");
1887                         break;
1888                 }
1889
1890                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1891                         DRM_DEBUG_KMS("clock recovery OK\n");
1892                         clock_recovery = true;
1893                         break;
1894                 }
1895
1896                 /* Check to see if we've tried the max voltage */
1897                 for (i = 0; i < intel_dp->lane_count; i++)
1898                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1899                                 break;
1900                 if (i == intel_dp->lane_count) {
1901                         ++loop_tries;
1902                         if (loop_tries == 5) {
1903                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1904                                 break;
1905                         }
1906                         memset(intel_dp->train_set, 0, 4);
1907                         voltage_tries = 0;
1908                         continue;
1909                 }
1910
1911                 /* Check to see if we've tried the same voltage 5 times */
1912                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1913                         ++voltage_tries;
1914                         if (voltage_tries == 5) {
1915                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1916                                 break;
1917                         }
1918                 } else
1919                         voltage_tries = 0;
1920                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1921
1922                 /* Compute new intel_dp->train_set as requested by target */
1923                 intel_get_adjust_train(intel_dp, link_status);
1924         }
1925
1926         intel_dp->DP = DP;
1927 }
1928
1929 void
1930 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1931 {
1932         bool channel_eq = false;
1933         int tries, cr_tries;
1934         uint32_t DP = intel_dp->DP;
1935
1936         /* channel equalization */
1937         tries = 0;
1938         cr_tries = 0;
1939         channel_eq = false;
1940         for (;;) {
1941                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1942
1943                 if (cr_tries > 5) {
1944                         DRM_ERROR("failed to train DP, aborting\n");
1945                         intel_dp_link_down(intel_dp);
1946                         break;
1947                 }
1948
1949                 intel_dp_set_signal_levels(intel_dp, &DP);
1950
1951                 /* channel eq pattern */
1952                 if (!intel_dp_set_link_train(intel_dp, DP,
1953                                              DP_TRAINING_PATTERN_2 |
1954                                              DP_LINK_SCRAMBLING_DISABLE))
1955                         break;
1956
1957                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1958                 if (!intel_dp_get_link_status(intel_dp, link_status))
1959                         break;
1960
1961                 /* Make sure clock is still ok */
1962                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1963                         intel_dp_start_link_train(intel_dp);
1964                         cr_tries++;
1965                         continue;
1966                 }
1967
1968                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1969                         channel_eq = true;
1970                         break;
1971                 }
1972
1973                 /* Try 5 times, then try clock recovery if that fails */
1974                 if (tries > 5) {
1975                         intel_dp_link_down(intel_dp);
1976                         intel_dp_start_link_train(intel_dp);
1977                         tries = 0;
1978                         cr_tries++;
1979                         continue;
1980                 }
1981
1982                 /* Compute new intel_dp->train_set as requested by target */
1983                 intel_get_adjust_train(intel_dp, link_status);
1984                 ++tries;
1985         }
1986
1987         if (channel_eq)
1988                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1989
1990         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1991 }
1992
1993 static void
1994 intel_dp_link_down(struct intel_dp *intel_dp)
1995 {
1996         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1997         struct drm_device *dev = intel_dig_port->base.base.dev;
1998         struct drm_i915_private *dev_priv = dev->dev_private;
1999         struct intel_crtc *intel_crtc =
2000                 to_intel_crtc(intel_dig_port->base.base.crtc);
2001         uint32_t DP = intel_dp->DP;
2002
2003         /*
2004          * DDI code has a strict mode set sequence and we should try to respect
2005          * it, otherwise we might hang the machine in many different ways. So we
2006          * really should be disabling the port only on a complete crtc_disable
2007          * sequence. This function is just called under two conditions on DDI
2008          * code:
2009          * - Link train failed while doing crtc_enable, and on this case we
2010          *   really should respect the mode set sequence and wait for a
2011          *   crtc_disable.
2012          * - Someone turned the monitor off and intel_dp_check_link_status
2013          *   called us. We don't need to disable the whole port on this case, so
2014          *   when someone turns the monitor on again,
2015          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2016          *   train.
2017          */
2018         if (HAS_DDI(dev))
2019                 return;
2020
2021         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2022                 return;
2023
2024         DRM_DEBUG_KMS("\n");
2025
2026         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2027                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2028                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2029         } else {
2030                 DP &= ~DP_LINK_TRAIN_MASK;
2031                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2032         }
2033         POSTING_READ(intel_dp->output_reg);
2034
2035         /* We don't really know why we're doing this */
2036         intel_wait_for_vblank(dev, intel_crtc->pipe);
2037
2038         if (HAS_PCH_IBX(dev) &&
2039             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2040                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2041
2042                 /* Hardware workaround: leaving our transcoder select
2043                  * set to transcoder B while it's off will prevent the
2044                  * corresponding HDMI output on transcoder A.
2045                  *
2046                  * Combine this with another hardware workaround:
2047                  * transcoder select bit can only be cleared while the
2048                  * port is enabled.
2049                  */
2050                 DP &= ~DP_PIPEB_SELECT;
2051                 I915_WRITE(intel_dp->output_reg, DP);
2052
2053                 /* Changes to enable or select take place the vblank
2054                  * after being written.
2055                  */
2056                 if (WARN_ON(crtc == NULL)) {
2057                         /* We should never try to disable a port without a crtc
2058                          * attached. For paranoia keep the code around for a
2059                          * bit. */
2060                         POSTING_READ(intel_dp->output_reg);
2061                         msleep(50);
2062                 } else
2063                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2064         }
2065
2066         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2067         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2068         POSTING_READ(intel_dp->output_reg);
2069         msleep(intel_dp->panel_power_down_delay);
2070 }
2071
2072 static bool
2073 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2074 {
2075         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2076
2077         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2078                                            sizeof(intel_dp->dpcd)) == 0)
2079                 return false; /* aux transfer failed */
2080
2081         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2082                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2083         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2084
2085         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2086                 return false; /* DPCD not present */
2087
2088         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2089               DP_DWN_STRM_PORT_PRESENT))
2090                 return true; /* native DP sink */
2091
2092         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2093                 return true; /* no per-port downstream info */
2094
2095         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2096                                            intel_dp->downstream_ports,
2097                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2098                 return false; /* downstream port status fetch failed */
2099
2100         return true;
2101 }
2102
2103 static void
2104 intel_dp_probe_oui(struct intel_dp *intel_dp)
2105 {
2106         u8 buf[3];
2107
2108         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2109                 return;
2110
2111         ironlake_edp_panel_vdd_on(intel_dp);
2112
2113         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2114                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2115                               buf[0], buf[1], buf[2]);
2116
2117         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2118                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2119                               buf[0], buf[1], buf[2]);
2120
2121         ironlake_edp_panel_vdd_off(intel_dp, false);
2122 }
2123
2124 static bool
2125 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2126 {
2127         int ret;
2128
2129         ret = intel_dp_aux_native_read_retry(intel_dp,
2130                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2131                                              sink_irq_vector, 1);
2132         if (!ret)
2133                 return false;
2134
2135         return true;
2136 }
2137
2138 static void
2139 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2140 {
2141         /* NAK by default */
2142         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2143 }
2144
2145 /*
2146  * According to DP spec
2147  * 5.1.2:
2148  *  1. Read DPCD
2149  *  2. Configure link according to Receiver Capabilities
2150  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2151  *  4. Check link status on receipt of hot-plug interrupt
2152  */
2153
2154 void
2155 intel_dp_check_link_status(struct intel_dp *intel_dp)
2156 {
2157         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2158         u8 sink_irq_vector;
2159         u8 link_status[DP_LINK_STATUS_SIZE];
2160
2161         if (!intel_encoder->connectors_active)
2162                 return;
2163
2164         if (WARN_ON(!intel_encoder->base.crtc))
2165                 return;
2166
2167         /* Try to read receiver status if the link appears to be up */
2168         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2169                 intel_dp_link_down(intel_dp);
2170                 return;
2171         }
2172
2173         /* Now read the DPCD to see if it's actually running */
2174         if (!intel_dp_get_dpcd(intel_dp)) {
2175                 intel_dp_link_down(intel_dp);
2176                 return;
2177         }
2178
2179         /* Try to read the source of the interrupt */
2180         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2181             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2182                 /* Clear interrupt source */
2183                 intel_dp_aux_native_write_1(intel_dp,
2184                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2185                                             sink_irq_vector);
2186
2187                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2188                         intel_dp_handle_test_request(intel_dp);
2189                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2190                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2191         }
2192
2193         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2194                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2195                               drm_get_encoder_name(&intel_encoder->base));
2196                 intel_dp_start_link_train(intel_dp);
2197                 intel_dp_complete_link_train(intel_dp);
2198         }
2199 }
2200
2201 /* XXX this is probably wrong for multiple downstream ports */
2202 static enum drm_connector_status
2203 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2204 {
2205         uint8_t *dpcd = intel_dp->dpcd;
2206         bool hpd;
2207         uint8_t type;
2208
2209         if (!intel_dp_get_dpcd(intel_dp))
2210                 return connector_status_disconnected;
2211
2212         /* if there's no downstream port, we're done */
2213         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2214                 return connector_status_connected;
2215
2216         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2217         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2218         if (hpd) {
2219                 uint8_t reg;
2220                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2221                                                     &reg, 1))
2222                         return connector_status_unknown;
2223                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2224                                               : connector_status_disconnected;
2225         }
2226
2227         /* If no HPD, poke DDC gently */
2228         if (drm_probe_ddc(&intel_dp->adapter))
2229                 return connector_status_connected;
2230
2231         /* Well we tried, say unknown for unreliable port types */
2232         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2233         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2234                 return connector_status_unknown;
2235
2236         /* Anything else is out of spec, warn and ignore */
2237         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2238         return connector_status_disconnected;
2239 }
2240
2241 static enum drm_connector_status
2242 ironlake_dp_detect(struct intel_dp *intel_dp)
2243 {
2244         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2245         struct drm_i915_private *dev_priv = dev->dev_private;
2246         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2247         enum drm_connector_status status;
2248
2249         /* Can't disconnect eDP, but you can close the lid... */
2250         if (is_edp(intel_dp)) {
2251                 status = intel_panel_detect(dev);
2252                 if (status == connector_status_unknown)
2253                         status = connector_status_connected;
2254                 return status;
2255         }
2256
2257         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2258                 return connector_status_disconnected;
2259
2260         return intel_dp_detect_dpcd(intel_dp);
2261 }
2262
2263 static enum drm_connector_status
2264 g4x_dp_detect(struct intel_dp *intel_dp)
2265 {
2266         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2269         uint32_t bit;
2270
2271         /* Can't disconnect eDP, but you can close the lid... */
2272         if (is_edp(intel_dp)) {
2273                 enum drm_connector_status status;
2274
2275                 status = intel_panel_detect(dev);
2276                 if (status == connector_status_unknown)
2277                         status = connector_status_connected;
2278                 return status;
2279         }
2280
2281         switch (intel_dig_port->port) {
2282         case PORT_B:
2283                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2284                 break;
2285         case PORT_C:
2286                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2287                 break;
2288         case PORT_D:
2289                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2290                 break;
2291         default:
2292                 return connector_status_unknown;
2293         }
2294
2295         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2296                 return connector_status_disconnected;
2297
2298         return intel_dp_detect_dpcd(intel_dp);
2299 }
2300
2301 static struct edid *
2302 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2303 {
2304         struct intel_connector *intel_connector = to_intel_connector(connector);
2305
2306         /* use cached edid if we have one */
2307         if (intel_connector->edid) {
2308                 struct edid *edid;
2309                 int size;
2310
2311                 /* invalid edid */
2312                 if (IS_ERR(intel_connector->edid))
2313                         return NULL;
2314
2315                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2316                 edid = kmalloc(size, GFP_KERNEL);
2317                 if (!edid)
2318                         return NULL;
2319
2320                 memcpy(edid, intel_connector->edid, size);
2321                 return edid;
2322         }
2323
2324         return drm_get_edid(connector, adapter);
2325 }
2326
2327 static int
2328 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2329 {
2330         struct intel_connector *intel_connector = to_intel_connector(connector);
2331
2332         /* use cached edid if we have one */
2333         if (intel_connector->edid) {
2334                 /* invalid edid */
2335                 if (IS_ERR(intel_connector->edid))
2336                         return 0;
2337
2338                 return intel_connector_update_modes(connector,
2339                                                     intel_connector->edid);
2340         }
2341
2342         return intel_ddc_get_modes(connector, adapter);
2343 }
2344
2345 static enum drm_connector_status
2346 intel_dp_detect(struct drm_connector *connector, bool force)
2347 {
2348         struct intel_dp *intel_dp = intel_attached_dp(connector);
2349         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2350         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2351         struct drm_device *dev = connector->dev;
2352         enum drm_connector_status status;
2353         struct edid *edid = NULL;
2354
2355         intel_dp->has_audio = false;
2356
2357         if (HAS_PCH_SPLIT(dev))
2358                 status = ironlake_dp_detect(intel_dp);
2359         else
2360                 status = g4x_dp_detect(intel_dp);
2361
2362         if (status != connector_status_connected)
2363                 return status;
2364
2365         intel_dp_probe_oui(intel_dp);
2366
2367         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2368                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2369         } else {
2370                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2371                 if (edid) {
2372                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2373                         kfree(edid);
2374                 }
2375         }
2376
2377         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2378                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2379         return connector_status_connected;
2380 }
2381
2382 static int intel_dp_get_modes(struct drm_connector *connector)
2383 {
2384         struct intel_dp *intel_dp = intel_attached_dp(connector);
2385         struct intel_connector *intel_connector = to_intel_connector(connector);
2386         struct drm_device *dev = connector->dev;
2387         int ret;
2388
2389         /* We should parse the EDID data and find out if it has an audio sink
2390          */
2391
2392         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2393         if (ret)
2394                 return ret;
2395
2396         /* if eDP has no EDID, fall back to fixed mode */
2397         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2398                 struct drm_display_mode *mode;
2399                 mode = drm_mode_duplicate(dev,
2400                                           intel_connector->panel.fixed_mode);
2401                 if (mode) {
2402                         drm_mode_probed_add(connector, mode);
2403                         return 1;
2404                 }
2405         }
2406         return 0;
2407 }
2408
2409 static bool
2410 intel_dp_detect_audio(struct drm_connector *connector)
2411 {
2412         struct intel_dp *intel_dp = intel_attached_dp(connector);
2413         struct edid *edid;
2414         bool has_audio = false;
2415
2416         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2417         if (edid) {
2418                 has_audio = drm_detect_monitor_audio(edid);
2419                 kfree(edid);
2420         }
2421
2422         return has_audio;
2423 }
2424
2425 static int
2426 intel_dp_set_property(struct drm_connector *connector,
2427                       struct drm_property *property,
2428                       uint64_t val)
2429 {
2430         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2431         struct intel_connector *intel_connector = to_intel_connector(connector);
2432         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2433         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2434         int ret;
2435
2436         ret = drm_object_property_set_value(&connector->base, property, val);
2437         if (ret)
2438                 return ret;
2439
2440         if (property == dev_priv->force_audio_property) {
2441                 int i = val;
2442                 bool has_audio;
2443
2444                 if (i == intel_dp->force_audio)
2445                         return 0;
2446
2447                 intel_dp->force_audio = i;
2448
2449                 if (i == HDMI_AUDIO_AUTO)
2450                         has_audio = intel_dp_detect_audio(connector);
2451                 else
2452                         has_audio = (i == HDMI_AUDIO_ON);
2453
2454                 if (has_audio == intel_dp->has_audio)
2455                         return 0;
2456
2457                 intel_dp->has_audio = has_audio;
2458                 goto done;
2459         }
2460
2461         if (property == dev_priv->broadcast_rgb_property) {
2462                 switch (val) {
2463                 case INTEL_BROADCAST_RGB_AUTO:
2464                         intel_dp->color_range_auto = true;
2465                         break;
2466                 case INTEL_BROADCAST_RGB_FULL:
2467                         intel_dp->color_range_auto = false;
2468                         intel_dp->color_range = 0;
2469                         break;
2470                 case INTEL_BROADCAST_RGB_LIMITED:
2471                         intel_dp->color_range_auto = false;
2472                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2473                         break;
2474                 default:
2475                         return -EINVAL;
2476                 }
2477                 goto done;
2478         }
2479
2480         if (is_edp(intel_dp) &&
2481             property == connector->dev->mode_config.scaling_mode_property) {
2482                 if (val == DRM_MODE_SCALE_NONE) {
2483                         DRM_DEBUG_KMS("no scaling not supported\n");
2484                         return -EINVAL;
2485                 }
2486
2487                 if (intel_connector->panel.fitting_mode == val) {
2488                         /* the eDP scaling property is not changed */
2489                         return 0;
2490                 }
2491                 intel_connector->panel.fitting_mode = val;
2492
2493                 goto done;
2494         }
2495
2496         return -EINVAL;
2497
2498 done:
2499         if (intel_encoder->base.crtc)
2500                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2501
2502         return 0;
2503 }
2504
2505 static void
2506 intel_dp_destroy(struct drm_connector *connector)
2507 {
2508         struct drm_device *dev = connector->dev;
2509         struct intel_dp *intel_dp = intel_attached_dp(connector);
2510         struct intel_connector *intel_connector = to_intel_connector(connector);
2511
2512         if (!IS_ERR_OR_NULL(intel_connector->edid))
2513                 kfree(intel_connector->edid);
2514
2515         if (is_edp(intel_dp)) {
2516                 intel_panel_destroy_backlight(dev);
2517                 intel_panel_fini(&intel_connector->panel);
2518         }
2519
2520         drm_sysfs_connector_remove(connector);
2521         drm_connector_cleanup(connector);
2522         kfree(connector);
2523 }
2524
2525 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2526 {
2527         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2528         struct intel_dp *intel_dp = &intel_dig_port->dp;
2529         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2530
2531         i2c_del_adapter(&intel_dp->adapter);
2532         drm_encoder_cleanup(encoder);
2533         if (is_edp(intel_dp)) {
2534                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2535                 mutex_lock(&dev->mode_config.mutex);
2536                 ironlake_panel_vdd_off_sync(intel_dp);
2537                 mutex_unlock(&dev->mode_config.mutex);
2538         }
2539         kfree(intel_dig_port);
2540 }
2541
2542 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2543         .mode_fixup = intel_dp_mode_fixup,
2544         .mode_set = intel_dp_mode_set,
2545 };
2546
2547 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2548         .dpms = intel_connector_dpms,
2549         .detect = intel_dp_detect,
2550         .fill_modes = drm_helper_probe_single_connector_modes,
2551         .set_property = intel_dp_set_property,
2552         .destroy = intel_dp_destroy,
2553 };
2554
2555 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2556         .get_modes = intel_dp_get_modes,
2557         .mode_valid = intel_dp_mode_valid,
2558         .best_encoder = intel_best_encoder,
2559 };
2560
2561 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2562         .destroy = intel_dp_encoder_destroy,
2563 };
2564
2565 static void
2566 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2567 {
2568         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2569
2570         intel_dp_check_link_status(intel_dp);
2571 }
2572
2573 /* Return which DP Port should be selected for Transcoder DP control */
2574 int
2575 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2576 {
2577         struct drm_device *dev = crtc->dev;
2578         struct intel_encoder *intel_encoder;
2579         struct intel_dp *intel_dp;
2580
2581         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2582                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2583
2584                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2585                     intel_encoder->type == INTEL_OUTPUT_EDP)
2586                         return intel_dp->output_reg;
2587         }
2588
2589         return -1;
2590 }
2591
2592 /* check the VBT to see whether the eDP is on DP-D port */
2593 bool intel_dpd_is_edp(struct drm_device *dev)
2594 {
2595         struct drm_i915_private *dev_priv = dev->dev_private;
2596         struct child_device_config *p_child;
2597         int i;
2598
2599         if (!dev_priv->child_dev_num)
2600                 return false;
2601
2602         for (i = 0; i < dev_priv->child_dev_num; i++) {
2603                 p_child = dev_priv->child_dev + i;
2604
2605                 if (p_child->dvo_port == PORT_IDPD &&
2606                     p_child->device_type == DEVICE_TYPE_eDP)
2607                         return true;
2608         }
2609         return false;
2610 }
2611
2612 static void
2613 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2614 {
2615         struct intel_connector *intel_connector = to_intel_connector(connector);
2616
2617         intel_attach_force_audio_property(connector);
2618         intel_attach_broadcast_rgb_property(connector);
2619         intel_dp->color_range_auto = true;
2620
2621         if (is_edp(intel_dp)) {
2622                 drm_mode_create_scaling_mode_property(connector->dev);
2623                 drm_object_attach_property(
2624                         &connector->base,
2625                         connector->dev->mode_config.scaling_mode_property,
2626                         DRM_MODE_SCALE_ASPECT);
2627                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2628         }
2629 }
2630
2631 static void
2632 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2633                                     struct intel_dp *intel_dp,
2634                                     struct edp_power_seq *out)
2635 {
2636         struct drm_i915_private *dev_priv = dev->dev_private;
2637         struct edp_power_seq cur, vbt, spec, final;
2638         u32 pp_on, pp_off, pp_div, pp;
2639
2640         /* Workaround: Need to write PP_CONTROL with the unlock key as
2641          * the very first thing. */
2642         pp = ironlake_get_pp_control(dev_priv);
2643         I915_WRITE(PCH_PP_CONTROL, pp);
2644
2645         pp_on = I915_READ(PCH_PP_ON_DELAYS);
2646         pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2647         pp_div = I915_READ(PCH_PP_DIVISOR);
2648
2649         /* Pull timing values out of registers */
2650         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2651                 PANEL_POWER_UP_DELAY_SHIFT;
2652
2653         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2654                 PANEL_LIGHT_ON_DELAY_SHIFT;
2655
2656         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2657                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2658
2659         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2660                 PANEL_POWER_DOWN_DELAY_SHIFT;
2661
2662         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2663                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2664
2665         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2666                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2667
2668         vbt = dev_priv->edp.pps;
2669
2670         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2671          * our hw here, which are all in 100usec. */
2672         spec.t1_t3 = 210 * 10;
2673         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2674         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2675         spec.t10 = 500 * 10;
2676         /* This one is special and actually in units of 100ms, but zero
2677          * based in the hw (so we need to add 100 ms). But the sw vbt
2678          * table multiplies it with 1000 to make it in units of 100usec,
2679          * too. */
2680         spec.t11_t12 = (510 + 100) * 10;
2681
2682         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2683                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2684
2685         /* Use the max of the register settings and vbt. If both are
2686          * unset, fall back to the spec limits. */
2687 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2688                                        spec.field : \
2689                                        max(cur.field, vbt.field))
2690         assign_final(t1_t3);
2691         assign_final(t8);
2692         assign_final(t9);
2693         assign_final(t10);
2694         assign_final(t11_t12);
2695 #undef assign_final
2696
2697 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2698         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2699         intel_dp->backlight_on_delay = get_delay(t8);
2700         intel_dp->backlight_off_delay = get_delay(t9);
2701         intel_dp->panel_power_down_delay = get_delay(t10);
2702         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2703 #undef get_delay
2704
2705         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2706                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2707                       intel_dp->panel_power_cycle_delay);
2708
2709         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2710                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2711
2712         if (out)
2713                 *out = final;
2714 }
2715
2716 static void
2717 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2718                                               struct intel_dp *intel_dp,
2719                                               struct edp_power_seq *seq)
2720 {
2721         struct drm_i915_private *dev_priv = dev->dev_private;
2722         u32 pp_on, pp_off, pp_div;
2723
2724         /* And finally store the new values in the power sequencer. */
2725         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2726                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2727         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2728                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2729         /* Compute the divisor for the pp clock, simply match the Bspec
2730          * formula. */
2731         pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2732                         << PP_REFERENCE_DIVIDER_SHIFT;
2733         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2734                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2735
2736         /* Haswell doesn't have any port selection bits for the panel
2737          * power sequencer any more. */
2738         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2739                 if (is_cpu_edp(intel_dp))
2740                         pp_on |= PANEL_POWER_PORT_DP_A;
2741                 else
2742                         pp_on |= PANEL_POWER_PORT_DP_D;
2743         }
2744
2745         I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2746         I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2747         I915_WRITE(PCH_PP_DIVISOR, pp_div);
2748
2749         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2750                       I915_READ(PCH_PP_ON_DELAYS),
2751                       I915_READ(PCH_PP_OFF_DELAYS),
2752                       I915_READ(PCH_PP_DIVISOR));
2753 }
2754
2755 void
2756 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2757                         struct intel_connector *intel_connector)
2758 {
2759         struct drm_connector *connector = &intel_connector->base;
2760         struct intel_dp *intel_dp = &intel_dig_port->dp;
2761         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2762         struct drm_device *dev = intel_encoder->base.dev;
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764         struct drm_display_mode *fixed_mode = NULL;
2765         struct edp_power_seq power_seq = { 0 };
2766         enum port port = intel_dig_port->port;
2767         const char *name = NULL;
2768         int type;
2769
2770         /* Preserve the current hw state. */
2771         intel_dp->DP = I915_READ(intel_dp->output_reg);
2772         intel_dp->attached_connector = intel_connector;
2773
2774         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2775                 if (intel_dpd_is_edp(dev))
2776                         intel_dp->is_pch_edp = true;
2777
2778         /*
2779          * FIXME : We need to initialize built-in panels before external panels.
2780          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2781          */
2782         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2783                 type = DRM_MODE_CONNECTOR_eDP;
2784                 intel_encoder->type = INTEL_OUTPUT_EDP;
2785         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2786                 type = DRM_MODE_CONNECTOR_eDP;
2787                 intel_encoder->type = INTEL_OUTPUT_EDP;
2788         } else {
2789                 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2790                  * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2791                  * rewrite it.
2792                  */
2793                 type = DRM_MODE_CONNECTOR_DisplayPort;
2794         }
2795
2796         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2797         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2798
2799         connector->polled = DRM_CONNECTOR_POLL_HPD;
2800         connector->interlace_allowed = true;
2801         connector->doublescan_allowed = 0;
2802
2803         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2804                           ironlake_panel_vdd_work);
2805
2806         intel_connector_attach_encoder(intel_connector, intel_encoder);
2807         drm_sysfs_connector_add(connector);
2808
2809         if (HAS_DDI(dev))
2810                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2811         else
2812                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2813
2814         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2815         if (HAS_DDI(dev)) {
2816                 switch (intel_dig_port->port) {
2817                 case PORT_A:
2818                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2819                         break;
2820                 case PORT_B:
2821                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2822                         break;
2823                 case PORT_C:
2824                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2825                         break;
2826                 case PORT_D:
2827                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2828                         break;
2829                 default:
2830                         BUG();
2831                 }
2832         }
2833
2834         /* Set up the DDC bus. */
2835         switch (port) {
2836         case PORT_A:
2837                 name = "DPDDC-A";
2838                 break;
2839         case PORT_B:
2840                 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS;
2841                 name = "DPDDC-B";
2842                 break;
2843         case PORT_C:
2844                 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS;
2845                 name = "DPDDC-C";
2846                 break;
2847         case PORT_D:
2848                 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS;
2849                 name = "DPDDC-D";
2850                 break;
2851         default:
2852                 WARN(1, "Invalid port %c\n", port_name(port));
2853                 break;
2854         }
2855
2856         if (is_edp(intel_dp))
2857                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2858
2859         intel_dp_i2c_init(intel_dp, intel_connector, name);
2860
2861         /* Cache DPCD and EDID for edp. */
2862         if (is_edp(intel_dp)) {
2863                 bool ret;
2864                 struct drm_display_mode *scan;
2865                 struct edid *edid;
2866
2867                 ironlake_edp_panel_vdd_on(intel_dp);
2868                 ret = intel_dp_get_dpcd(intel_dp);
2869                 ironlake_edp_panel_vdd_off(intel_dp, false);
2870
2871                 if (ret) {
2872                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2873                                 dev_priv->no_aux_handshake =
2874                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2875                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2876                 } else {
2877                         /* if this fails, presume the device is a ghost */
2878                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2879                         intel_dp_encoder_destroy(&intel_encoder->base);
2880                         intel_dp_destroy(connector);
2881                         return;
2882                 }
2883
2884                 /* We now know it's not a ghost, init power sequence regs. */
2885                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2886                                                               &power_seq);
2887
2888                 ironlake_edp_panel_vdd_on(intel_dp);
2889                 edid = drm_get_edid(connector, &intel_dp->adapter);
2890                 if (edid) {
2891                         if (drm_add_edid_modes(connector, edid)) {
2892                                 drm_mode_connector_update_edid_property(connector, edid);
2893                                 drm_edid_to_eld(connector, edid);
2894                         } else {
2895                                 kfree(edid);
2896                                 edid = ERR_PTR(-EINVAL);
2897                         }
2898                 } else {
2899                         edid = ERR_PTR(-ENOENT);
2900                 }
2901                 intel_connector->edid = edid;
2902
2903                 /* prefer fixed mode from EDID if available */
2904                 list_for_each_entry(scan, &connector->probed_modes, head) {
2905                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2906                                 fixed_mode = drm_mode_duplicate(dev, scan);
2907                                 break;
2908                         }
2909                 }
2910
2911                 /* fallback to VBT if available for eDP */
2912                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2913                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2914                         if (fixed_mode)
2915                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2916                 }
2917
2918                 ironlake_edp_panel_vdd_off(intel_dp, false);
2919         }
2920
2921         if (is_edp(intel_dp)) {
2922                 intel_panel_init(&intel_connector->panel, fixed_mode);
2923                 intel_panel_setup_backlight(connector);
2924         }
2925
2926         intel_dp_add_properties(intel_dp, connector);
2927
2928         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2929          * 0xd.  Failure to do so will result in spurious interrupts being
2930          * generated on the port when a cable is not attached.
2931          */
2932         if (IS_G4X(dev) && !IS_GM45(dev)) {
2933                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2934                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2935         }
2936 }
2937
2938 void
2939 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2940 {
2941         struct intel_digital_port *intel_dig_port;
2942         struct intel_encoder *intel_encoder;
2943         struct drm_encoder *encoder;
2944         struct intel_connector *intel_connector;
2945
2946         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2947         if (!intel_dig_port)
2948                 return;
2949
2950         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2951         if (!intel_connector) {
2952                 kfree(intel_dig_port);
2953                 return;
2954         }
2955
2956         intel_encoder = &intel_dig_port->base;
2957         encoder = &intel_encoder->base;
2958
2959         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2960                          DRM_MODE_ENCODER_TMDS);
2961         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2962
2963         intel_encoder->enable = intel_enable_dp;
2964         intel_encoder->pre_enable = intel_pre_enable_dp;
2965         intel_encoder->disable = intel_disable_dp;
2966         intel_encoder->post_disable = intel_post_disable_dp;
2967         intel_encoder->get_hw_state = intel_dp_get_hw_state;
2968
2969         intel_dig_port->port = port;
2970         intel_dig_port->dp.output_reg = output_reg;
2971
2972         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2973         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2974         intel_encoder->cloneable = false;
2975         intel_encoder->hot_plug = intel_dp_hot_plug;
2976
2977         intel_dp_init_connector(intel_dig_port, intel_connector);
2978 }